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// fdc to cpu ack; 0/1: frame data pool not empty/frame data pool empty; 48x64 bits of space 120 MFE_U16 reg_mfe_s_fdc_done_clr:1; // fdc done clear (write one clear) 121 MFE_U16 reg_mfe_s_fdc_done:1; // fdc done; indicate to CPU that data has been written to internal buffer 122 MFE_U16 reg48_dummy:8; 123 MFE_U16 reg_mfe_s_fdc_bs_vld:1; // set for bitstream write out (write one clear) 124 }; 125 MFE_U16 reg48; 126 }; 127 } RegFdcDone; 128 129 130 typedef struct _wqt_info_ { 131 union { 132 struct { 133 MFE_U16 reg_mfe_s_tbc_rw:1; // table mode; 0: read, 1: write 134 MFE_U16 reg_mfe_s_tbc_done_clr:1; // table done clear (write one clear) 135 MFE_U16 reg_mfe_s_tbc_done:1; // table done; indicate to CPU that (1) data has been written to table (2) table output is ready at reg_mfe_s_tbc_rdata 136 MFE_U16 reg49_dummy:5; 137 MFE_U16 reg_mfe_s_tbc_adr:6; // table address 138 }; 139 MFE_U16 reg49; 140 }; 141 } RegWQTDone; 142 143 144 typedef struct _qt_rb_check_info_ { 145 union { 146 struct { 147 MFE_U16 reg_mfe_s_tbc_rdata:16; // table mode; 0: read, 1: write 148 }; 149 MFE_U16 reg4b; 150 }; 151 } RegQT_RB_CHECK; 152 #ifdef _MFE_A3_ 153 typedef struct _qt_rb_check_reg03_info_ { 154 union { 155 struct { 156 MFE_U16 reg_mfe_g_er_mode:2; // 0/1/2/3: mby/bs/mby+bs/off 157 MFE_U16 reg_mfe_g_er_mby:2; // 0/1/2/3: every 1/2/4/8 mb row(s) (error resilence) 158 MFE_U16 reg_mfe_g_packed_mode:1; // frame buffer format for 422 packed mode; 0/1: YVYU/YUYV 159 MFE_U16 reg_mfe_g_qmode:1; // quantization method; 0/1: h263/mp4 160 MFE_U16 reg_mfe_g_tbc_mode:1; // table mode; 0: SW control, 1: HW control 161 MFE_U16 reg_mfe_g_fldpic_en:1; //field picture coding 162 MFE_U16 reg_mfe_g_dct_only_en:1; // [NOT SUPPORRTED] reg_mfe_g_dct_only_en 163 MFE_U16 reg_mfe_g_mstar_tile:1; // input buffer format; 0: m4ve tiled mode, 1: mstar tiled mode 164 MFE_U16 reg_mfe_g_mstar_tile_field_split:1; // input field buffer format; 0: top/bottom fields interlaced(new), 1: fields split(old) 165 MFE_U16 reg_mfe_g_fldpic_idx:1; // input field buffer order; 0: top, 1: bottom 166 }; 167 MFE_U16 reg03; 168 }; 169 } RegQT_RB_CHECK_REG03; 170 #else 171 typedef struct _qt_rb_check_reg03_info_ { 172 union { 173 struct { 174 MFE_U16 reg_mfe_g_er_mode:2; // 0/1/2/3: mby/bs/mby+bs/off 175 MFE_U16 reg_mfe_g_er_mby:2; // 0/1/2/3: every 1/2/4/8 mb row(s) (error resilence) 176 MFE_U16 reg_mfe_g_packed_mode:1; // frame buffer format for 422 packed mode; 0/1: YVYU/YUYV 177 MFE_U16 reg_mfe_g_qmode:1; // quantization method; 0/1: h263/mp4 178 MFE_U16 reg_mfe_g_tbc_mode:1; // table mode; 0: SW control, 1: HW control 179 MFE_U16 reg_mfe_g_fldpic_en:1; //field picture coding 180 }; 181 MFE_U16 reg03; 182 }; 183 } RegQT_RB_CHECK_REG03; 184 #endif 185 186 typedef struct _miu_protection_info_ { 187 union { 188 struct { 189 MFE_U16 reg_mfe_s_marb_ubound_0_high:OUTBUF_HI_BITS; // MIU protect for MPEG4 BSP obuf 190 #if (10-OUTBUF_HI_BITS)>0 191 MFE_U16 reg_mfe_59_reserved:(10-OUTBUF_HI_BITS); 192 #endif 193 MFE_U16 reg_mfe_s_marb_miu_bound_err:1; //miu write protection, miu bound error status for write port 0 ~ 3 194 #ifndef _MFE_A3_ 195 MFE_U16 reg_mfe_s_marb_miu_off:1; //miu write protection, miu off 196 MFE_U16 reg_mfe_s_marb_miu_bound_en:4; //miu write protection, miu bound enable for write port 0 ~ 3 197 #endif 198 }; 199 MFE_U16 reg59; 200 }; 201 } MIU_PRO_REG; 202 203 typedef struct _miu_protection_info2_ { 204 union { 205 struct { 206 MFE_U16 reg_mfe_g_mp4_itlc:1; // 0/1: MPEG4 progressive/interlaced mode 207 MFE_U16 reg_mfe_g_mp4_pskip_off:1; // 0/1: MPEG4 enable/disable p skip mode 208 MFE_U16 reg_mfe_g_mp4_acp:2; // [0]: 0/1: sw/hw acp selection; [1]: sw default value: 0/1: disable/enable acp; current version off 209 MFE_U16 reg_mfe_g_mp4_rounding_ctrl:1; // mp4 rounding control specified as in spec 210 MFE_U16 reg_mfe_g_er_hec:1; // 0/1: header extension code off/on 211 MFE_U16 reg_mfe_g_er_hec_t:3; // HEC counter reset values 212 MFE_U16 reg_mfe_g_er_h263_unit:2; // 0/1/2: unit is 1/2/4, for calculating gob_num. 213 MFE_U16 reg_mfe_g_mp4_direct_en:1; // MPEG4 direct enable 214 MFE_U16 reg_mfe_g_mp4_direct_mvstore:1; // [M]: enable storing of mv & skip_mb information to DRAM in P(or sometimes I) frame 215 }; 216 MFE_U16 reg19; 217 }; 218 } MIU_PRO_REG2; 219 typedef struct _mfe_reg_ { 220 // [GLOBAL SETTING] 221 union { 222 struct { 223 MFE_U16 reg_mfe_g_frame_start_sw:1; // frame start (1T clk_mfe) 224 MFE_U16 reg_mfe_g_soft_rstz:1; // software reset; 0/1: reset/not reset 225 MFE_U16 reg_mfe_g_enc_mode:2; // 0/1/2/3: MPEG4/H263/H264/JPEG 226 MFE_U16 reg_mfe_g_frame_type:2; // 0/1/2: I/P/B 227 MFE_U16 reg_mfe_g_ref_no:1; // 0/1: 1 frame/2 frames 228 MFE_U16 reg_mfe_g_mbr_en:1; // 0/1: disable/enable MB-level Rate control 229 MFE_U16 reg_mfe_g_qscale:6; // frame level qscale: [H264]: 1 ~ 51; [MPEG4]: 1 ~ 31 230 MFE_U16 reg_mfe_g_rec_en:1; // reconstruct enable 231 }; 232 MFE_U16 reg00; 233 }; 234 union { 235 struct { 236 MFE_U16 reg_mfe_g_pic_width:12; // picture width 237 }; 238 MFE_U16 reg01; 239 }; 240 union { 241 struct { 242 MFE_U16 reg_mfe_g_pic_height:12; // picture height 243 }; 244 MFE_U16 reg02; 245 }; 246 union { 247 struct { 248 MFE_U16 reg_mfe_g_er_mode:2; // 0/1/2/3: mby/bs/mby+bs/off 249 MFE_U16 reg_mfe_g_er_mby:2; // 0/1/2/3: every 1/2/4/8 mb row(s) (error resilence) 250 MFE_U16 reg_mfe_g_packed_mode:1; // frame buffer format for 422 packed mode; 0/1: YVYU/YUYV 251 MFE_U16 reg_mfe_g_qmode:1; // quantization method; 0/1: h263/mp4 252 MFE_U16 reg_mfe_g_tbc_mode:1; // table mode; 0: SW control, 1: HW control 253 MFE_U16 reg_mfe_g_fldpic_en:1; //field picture coding 254 }; 255 MFE_U16 reg03; 256 }; 257 union { 258 struct { 259 MFE_U16 reg_mfe_g_er_bs_th:16; // er_bs mode threshold 260 }; 261 MFE_U16 reg04; 262 }; 263 union { 264 struct { 265 MFE_U16 reg_mfe_g_inter_pref:16; // inter prediction preference 266 }; 267 MFE_U16 reg05; 268 }; 269 union { 270 struct { 271 MFE_U16 reg_mfe_g_cur_y_adr_low:16; // current luma base address 272 }; 273 MFE_U16 reg06; 274 }; 275 union { 276 struct { 277 MFE_U16 reg_mfe_g_cur_y_adr_high:ADDR_HI_BITS; // current luma base address 278 }; 279 MFE_U16 reg07; 280 }; 281 union { 282 struct { 283 MFE_U16 reg_mfe_g_cur_c_adr_low:16; // current chroma base address 284 }; 285 MFE_U16 reg08; 286 }; 287 union { 288 struct { 289 MFE_U16 reg_mfe_g_cur_c_adr_high:ADDR_HI_BITS; // current chroma base address 290 }; 291 MFE_U16 reg09; 292 }; 293 union { 294 struct { 295 MFE_U16 reg_mfe_g_ref_y_adr0_low:16; // reference luma base address0 296 }; 297 MFE_U16 reg0a; 298 }; 299 union { 300 struct { 301 MFE_U16 reg_mfe_g_ref_y_adr0_high:ADDR_HI_BITS; // reference luma base address0 302 }; 303 MFE_U16 reg0b; 304 }; 305 union { 306 struct { 307 MFE_U16 reg_mfe_g_ref_y_adr1_low:16; // reference luma base address1 308 }; 309 MFE_U16 reg0c; 310 }; 311 union { 312 struct { 313 MFE_U16 reg_mfe_g_ref_y_adr1_high:ADDR_HI_BITS; // reference luma base address0 314 }; 315 MFE_U16 reg0d; 316 }; 317 union { 318 struct { 319 MFE_U16 reg_mfe_g_ref_c_adr0_low:16; // reference chroma base address0 320 }; 321 MFE_U16 reg0e; 322 }; 323 union { 324 struct { 325 MFE_U16 reg_mfe_g_ref_c_adr0_high:ADDR_HI_BITS; // reference chroma base address0 326 }; 327 MFE_U16 reg0f; 328 }; 329 union { 330 struct { 331 MFE_U16 reg_mfe_g_ref_c_adr1_low:16; // reference chroma base address1 332 }; 333 MFE_U16 reg10; 334 }; 335 union { 336 struct { 337 MFE_U16 reg_mfe_g_ref_c_adr1_high:ADDR_HI_BITS; // reference chroma base address1 338 }; 339 MFE_U16 reg11; 340 }; 341 union { 342 struct { 343 MFE_U16 reg_mfe_g_rec_y_adr_low:16; // reconstructed luma base address 344 }; 345 MFE_U16 reg12; 346 }; 347 union { 348 struct { 349 MFE_U16 reg_mfe_g_rec_y_adr_high:ADDR_HI_BITS; // reconstructed luma base address 350 }; 351 MFE_U16 reg13; 352 }; 353 union { 354 struct { 355 MFE_U16 reg_mfe_g_rec_c_adr_low:16; // reconstructed chroma base address 356 }; 357 MFE_U16 reg14; 358 }; 359 union { 360 struct { 361 MFE_U16 reg_mfe_g_rec_c_adr_high:ADDR_HI_BITS; // reconstructed chroma base address 362 }; 363 MFE_U16 reg15; 364 }; 365 union { 366 struct { // clock gating 367 MFE_U16 gate_cry_crc_sram:1; 368 MFE_U16 gate_qtab_dbfdc_dbqtb_sram:1; 369 MFE_U16 gate_mcy_mcc_sram:1; 370 MFE_U16 gate_res0_res1_sram:1; 371 MFE_U16 gate_ieap:1; 372 MFE_U16 gate_dct_idct:1; 373 MFE_U16 gate_dbf:1; 374 }; 375 MFE_U16 reg16; 376 }; 377 union { 378 struct { 379 MFE_U16 reserved_reg17; 380 }; 381 MFE_U16 reg17; 382 }; 383 // [JPEG] 384 union { 385 struct { 386 MFE_U16 reg_mfe_g_jpe_enc_mode:2; // JPE encode mode; 2'b00/2'b01/2'b10/2'b11: 420/422/444/gray; current version supports 422 only 387 MFE_U16 reg_mfe_g_jpe_buffer_mode:1; // JPE buffer mode; 0/1: double buffer mode/frame buffer mode 388 MFE_U16 reg_mfe_g_jpe_multibuf_mode:2; // JPE multi-buffer mode; 0/1/2: 2/4/8 buffers 389 MFE_U16 reg_mfe_g_jpe_qfactor:4; // JPE q factor; 0 ~ 15: (1 ~ 16)/4 390 MFE_U16 reg_mfe_g_jpe_fsvs_mode:2; // JPE fsvs generation mode; 0/1/2: pure sw/sw+hw/hw 391 MFE_U16 reg18_dummy:4; 392 MFE_U16 reg_mfe_g_viu_soft_rstz:1; // viu software reset; 0/1: reset/not reset 393 }; 394 MFE_U16 reg18; 395 }; 396 // [MPEG4/H263] 397 union { 398 struct { 399 MFE_U16 reg_mfe_g_mp4_itlc:1; // 0/1: MPEG4 progressive/interlaced mode 400 MFE_U16 reg_mfe_g_mp4_pskip_off:1; // 0/1: MPEG4 enable/disable p skip mode 401 MFE_U16 reg_mfe_g_mp4_acp:2; // [0]: 0/1: sw/hw acp selection; [1]: sw default value: 0/1: disable/enable acp; current version off 402 MFE_U16 reg_mfe_g_mp4_rounding_ctrl:1; // mp4 rounding control specified as in spec 403 MFE_U16 reg_mfe_g_er_hec:1; // 0/1: header extension code off/on 404 MFE_U16 reg_mfe_g_er_hec_t:3; // HEC counter reset values 405 MFE_U16 reg_mfe_g_er_h263_unit:2; // 0/1/2: unit is 1/2/4, for calculating gob_num. 406 MFE_U16 reg_mfe_g_mp4_direct_en:1; // MPEG4 direct enable 407 MFE_U16 reg_mfe_g_mp4_direct_mvstore:1; // [M]: enable storing of mv & skip_mb information to DRAM in P(or sometimes I) frame 408 }; 409 MFE_U16 reg19; 410 }; 411 union { 412 struct { 413 MFE_U16 reg_mfe_g_mp4_direct_pref:8; // used in mp4 only, mp4 direct mode preference value 414 MFE_U16 reg_mfe_g_mp4_direct_trb:3; // used in mp4 only, mp4 direct mode trb (P0-B distance) 415 MFE_U16 reg_mfe_g_mp4_direct_trd:3; // used in mp4 only, mp4 direct mode trd (P0-P1 distance) 416 }; 417 MFE_U16 reg1a; 418 }; 419 union { 420 struct { 421 MFE_U16 reg_mfe_g_mp4_flddct_diff_thr:8; // used in mp4 only, mp4 field dct difference threshold 422 MFE_U16 reg_mfe_g_mp4_flddct_en:1; // used in mp4 only, mp4 field dct enable 423 }; 424 MFE_U16 reg1b; 425 }; 426 // [IRQ & important IP status checkings] 427 union { 428 struct { 429 MFE_U16 reg_mfe_g_irq_mask:8; // 0/1: irq not-mask/mask 430 MFE_U16 reg_mfe_g_irq_force:8; // 0/1: set corresponding interrupt as usual/force corresponding interrupt 431 }; 432 MFE_U16 reg1c; 433 }; 434 union { 435 struct { 436 MFE_U16 reg_mfe_g_irq_clr0:1; // 0/1: not clear interrupt/clear interrupt 0 437 MFE_U16 reg_mfe_g_irq_clr1:1; // 0/1: not clear interrupt/clear interrupt 1 438 MFE_U16 reg_mfe_g_irq_clr2:1; // 0/1: not clear interrupt/clear interrupt 2 439 MFE_U16 reg_mfe_g_irq_clr3:1; // 0/1: not clear interrupt/clear interrupt 3 440 MFE_U16 reg_mfe_g_irq_clr4:1; // 0/1: not clear interrupt/clear interrupt 4 441 MFE_U16 reg_mfe_g_irq_clr5:1; // 0/1: not clear interrupt/clear interrupt 5 442 MFE_U16 reg_mfe_g_irq_clr6:1; // 0/1: not clear interrupt/clear interrupt 6 443 MFE_U16 reg_mfe_g_irq_clr7:1; // 0/1: not clear interrupt/clear interrupt 7 444 MFE_U16 reg_mfe_g_swrst_safe:1; // to indicate there're no miu activities that need to pay attention to 445 }; 446 MFE_U16 reg1d; 447 }; 448 union { 449 struct { 450 MFE_U16 reg_mfe_g_irq_cpu:8; // status of interrupt on CPU side 451 MFE_U16 reg_mfe_g_irq_ip:8; // status of interrupt on IP side 452 }; 453 MFE_U16 reg1e; 454 }; 455 union { 456 struct { 457 MFE_U16 reserved_reg1f; 458 }; 459 MFE_U16 reg1f; 460 }; 461 // [ME setting] 462 union { 463 struct { 464 MFE_U16 reg_mfe_s_me_4x4_disable:1; // 4x4_disable 465 MFE_U16 reg_mfe_s_me_8x4_disable:1; // 8x4_disable 466 MFE_U16 reg_mfe_s_me_4x8_disable:1; // 4x8_disable 467 MFE_U16 reg_mfe_s_me_16x8_disable:1; // 16x8_disable 468 MFE_U16 reg_mfe_s_me_8x16_disable:1; // 8x16_disable 469 MFE_U16 reg_mfe_s_me_8x8_disable:1; // 8x8_disable 470 MFE_U16 reg_mfe_s_me_16x16_disable:1; // 16x16_disable 471 MFE_U16 reg_mfe_s_mesr_adapt:1; // me search range auto-adaptive; 0/1: off/on 472 MFE_U16 reg_mfe_s_me_ref_en_mode:2; // ref enable mode: 2'b01/2'b10/2'b11: ref0 enable/ref1 enable/ref0&1 enable 473 }; 474 MFE_U16 reg20; 475 }; 476 // [IME PIPELINE] 477 union { 478 struct { 479 MFE_U16 reg_mfe_s_ime_sr16:1; // search range limited to (h,v) = (+/-16, +/-16); 0/1: search range 32/16 480 MFE_U16 reg_mfe_s_ime_umv_disable:1; // 0/1: UMV enable/disable 481 MFE_U16 reg_mfe_s_ime_ime_wait_fme:1; // 0/1: ime wait fme/fme wait ime 482 MFE_U16 reg_mfe_s_ime_boundrect_en:1; // ime bounding rectangle enable (needed for level 3.0 and below) 483 MFE_U16 reg_mfe_s_ime_h264_p8x8_ctrl_en:1; // ime h264 max p8x8 count control enable 484 MFE_U16 reg21_dummy:3; 485 MFE_U16 reg_mfe_s_ime_h264_p8x8_max:6; // ime h264 max p8x8 count; value 0 is prohibited 486 // Max P8x8 MB count = 16 * reg_mfe_s_ime_h264_p8x8_max 487 }; 488 MFE_U16 reg21; 489 }; 490 union { 491 struct { 492 MFE_U16 reg_mfe_s_ime_mesr_max_addr:8; // me search range max depth 493 MFE_U16 reg_mfe_s_ime_mesr_min_addr:8; // me search range min depth 494 }; 495 MFE_U16 reg22; 496 }; 497 union { 498 struct { 499 MFE_U16 reg_mfe_s_ime_mvx_min:6; // me mvx min; 0/�K/62 --> -32/�K/30 500 MFE_U16 reg24_dummy:2; 501 MFE_U16 reg_mfe_s_ime_mvx_max:6; // me mvx max; 0/�K/62 --> -32/�K/30 502 }; 503 MFE_U16 reg23; 504 }; 505 union { 506 struct { 507 MFE_U16 reg_mfe_s_ime_mvy_min:6; // me mvy min; 0/�K/62 --> -32/�K/30 508 MFE_U16 reg25_dummy:2; 509 MFE_U16 reg_mfe_s_ime_mvy_max:6; // me mvy max; 0/�K62/ --> -32/�K/30 510 }; 511 MFE_U16 reg24; 512 }; 513 // [FME pipeline] 514 union { 515 struct { 516 MFE_U16 reg_mfe_s_fme_quarter_disable:1; // 0/1: Quarter fine-tune enable/disable 517 MFE_U16 reg_mfe_s_fme_half_disable:1; // 0/1: Half fine-tune enable/disable 518 MFE_U16 /*reg_mfe_s_fme_one_mode*/reg26_dummy:1; 519 MFE_U16 reg_mfe_s_fme_pmv_enable:1; // 0/1: disable/enable Previous Skip MV mode 520 MFE_U16 reg_mfe_s_fme_mode_no:1; // 0: one mode. 1: two mode. 521 MFE_U16 reg_mfe_s_fme_mode0_refno:1; // 0: one ref. for mode0 1: two ref. for mode0 522 MFE_U16 reg_mfe_s_fme_mode1_refno:1; // 0: one ref. for mode1 1: two ref. for mode1 523 MFE_U16 reg_mfe_s_fme_mode2_refno:1; // 0: one ref. for mode2 1: two ref. for mode2 524 MFE_U16 reg_mfe_s_fme_skip:1; // fme skip 525 MFE_U16 reg_mfe_s_fme_pipeline_on:1; //0/1: FME pipeline off/on 526 }; 527 MFE_U16 reg25; 528 }; 529 // MBR 530 union { 531 struct { 532 MFE_U16 reg_mfe_s_mbr_pqp_dlimit:2; // previous qp diff limit 533 MFE_U16 reg_mfe_s_mbr_uqp_dlimit:2; // upper qp diff limit 534 MFE_U16 reg_mfe_s_mbr_tmb_bits:12; // target MB bits 535 }; 536 MFE_U16 reg26; 537 }; 538 union { 539 struct { 540 MFE_U16 reg_mfe_s_mbr_frame_qstep:13; // frame level qp's qstep 541 }; 542 MFE_U16 reg27; 543 }; 544 union { 545 struct { 546 MFE_U16 reg_mfe_s_mbr_last_frm_avg_qp_low:16; // last frame average qp (status register) 547 }; 548 MFE_U16 reg28; 549 }; 550 union { 551 struct { 552 MFE_U16 reg_mfe_s_mbr_last_frm_avg_qp_high:LAST_FRAME_AVGQP_HI_BITS; // last frame average qp (status register) 553 MFE_U16 reg_mfe_s_mbr_qp_cidx_offset:5; // [H264] chroma qp index offset (+12). Spec range is [-12,12] 554 }; 555 MFE_U16 reg29; 556 }; 557 union { 558 struct { 559 MFE_U16 reg_mfe_s_mbr_qp_min:6; // qp min 560 MFE_U16 reg_mfe_s_mbr_qp_max:6; // qp max 561 MFE_U16 reg_mfe_s_mvdctl_ref0_offset:2; // H264 mvy offset adjustment for MCC if ref is frame 0: 0/1/2: 0/+2/-2 562 MFE_U16 reg_mfe_s_mvdctl_ref1_offset:2; // H264 mvy offset adjustment for MCC if ref is frame 1: 0/1/2: 0/+2/-2 563 }; 564 MFE_U16 reg2a; 565 }; 566 // IEAP 567 union { 568 struct { 569 MFE_U16 reg_mfe_s_ieap_last_mode:4; // software control of the last mode of Intra4x4 mode 0 ~ 8 570 MFE_U16 reg_mfe_s_ieap_constraint_intra:1; // software control constraint intra; 0/1: OFF/ON 571 MFE_U16 reg_mfe_s_ieap_ccest_en:1; // software control cost estimator; 0/1: OFF/ON 572 MFE_U16 reg_mfe_s_ieap_ccest_thr:2; // threshold of cost estimator set 0 ~ 3 for threshold 1 ~ 4 573 MFE_U16 reg_mfe_s_ieap_drop_i16:1; // software control stop-Intra16x16-mode; 1:w/o I16M, 0:w/i I16MB 574 }; 575 MFE_U16 reg2b; 576 }; 577 // QUAN 578 union { 579 struct { 580 MFE_U16 reg_mfe_s_quan_idx_last:6; // the index of the last non-zero coefficient in the zig-zag order 581 MFE_U16 reg_mfe_s_quan_idx_swlast:1; // software control of the index of the last non-zero coefficient in the zig-zag order; 0/1: disable/enable 582 }; 583 MFE_U16 reg2c; 584 }; 585 // TXIP control & debug 586 union { 587 struct { 588 MFE_U16 reg_mfe_s_txip_mbx:9; //txip mbx 589 MFE_U16 reg_mfe_s_txip_sng_mb:1; //0/1: disable/enable txip controller stop-and-go mechanism using (txip_mbx == reg_mfe_g_debug_trig_mbx) & (txip_mby == reg_mfe_g_debug_trig_mby) 590 MFE_U16 reg_mfe_s_txip_sng_set:1; //txip controller stop-and-go mechanism using this register bit: 0/1: go/stop 591 MFE_U16 reg_mfe_s_txip_dbf_full_halt_en:1; //txip controller stop-and-go mechanism using double buffer fullness as criterion; 0/1: disable/enable 592 }; 593 MFE_U16 reg2d; 594 }; 595 union { 596 struct { 597 MFE_U16 reg_mfe_s_txip_mby:9; // txip mby 598 }; 599 MFE_U16 reg2e; 600 }; 601 union { 602 struct { 603 MFE_U16 reg_mfe_s_txip_irfsh_mb_s0:12; // intra refresh mb start 0 604 MFE_U16 reg_mfe_s_txip_irfsh_en:2; // intra refresh enable bits: bit0: enable condition 0; bit 1: enable condition 1 605 }; 606 MFE_U16 reg2f; 607 }; 608 union { 609 struct { 610 MFE_U16 reg_mfe_s_txip_irfsh_mb_e0:12; // intra refresh mb end 0 611 }; 612 MFE_U16 reg30; 613 }; 614 union { 615 struct { 616 MFE_U16 reg_mfe_s_txip_irfsh_mb_s1:12; // intra refresh mb start 1 617 }; 618 MFE_U16 reg31; 619 }; 620 union { 621 struct { 622 MFE_U16 reg_mfe_s_txip_irfsh_mb_e1:12; // intra refresh mb end 1 623 MFE_U16 reg_mfe_s_txip_timeout_en:1; // txip time out enable 624 MFE_U16 reg_mfe_s_txip_wait_mode:1; // txip waiting mode to move to next MB; 0/1: idle count/cycle count 625 }; 626 MFE_U16 reg32; 627 }; 628 union { 629 struct { 630 MFE_U16 reg_mfe_s_txip_idle_cnt:16; // wait mode is 0: txip idle count (x 64T)/ wait mode is 1: txip total processing count (x 64T) 631 }; 632 MFE_U16 reg33; 633 }; 634 union { 635 struct { 636 MFE_U16 reg_mfe_s_txip_timeout:16; // txip timeout count (x 64T) 637 }; 638 MFE_U16 reg34; 639 }; 640 // [ECDB PIPELINE] 641 // ECDB control & debug 642 union { 643 struct { 644 MFE_U16 reg_mfe_s_ecdb_mbx:9; // ecdb mbx 645 }; 646 MFE_U16 reg35; 647 }; 648 union { 649 struct { 650 MFE_U16 reg_mfe_s_ecdb_mby:9; // ecdb mby 651 }; 652 MFE_U16 reg36; 653 }; 654 // MDC 655 union { 656 struct { 657 MFE_U16 reg_mfe_s_mdc_total_mb_bw:4; // total mb bit width used in video_pkt 658 MFE_U16 reg_mfe_s_mdc_m4vpktpzero:1; // MPEG4 video packet preceding zeros: 0/1: 16/17 zeros 659 MFE_U16 reg_mfe_s_mdc_m4time:2; // MPEG4 modulo time base: 0/1/2/3: 0/10/110/1110 660 MFE_U16 reg_mfe_s_mdc_m4iadcvlc_th:3; // MPEG4 intra dc vlc threshold 661 MFE_U16 reg_mfe_s_mdc_m4vop_tinc_bw:4; // vop_time_increment bit width 662 }; 663 MFE_U16 reg37; 664 }; 665 union { 666 struct { 667 MFE_U16 reg_mfe_s_mdc_m4vop_tinc:15; // vop_time_increment 668 }; 669 MFE_U16 reg38; 670 }; 671 union { 672 struct { 673 MFE_U16 reg_mfe_s_mdc_gob_frame_id:2; // H263 gob frame id 674 MFE_U16 reg_mfe_s_mdc_h264_nal_ref_idc:2; // nal_ref_idc 675 MFE_U16 reg_mfe_s_mdc_h264_nal_unit_type:1; // 0/1: 1/5 676 MFE_U16 reg_mfe_s_mdc_h264_fnum_bits:2; // H264 frame num bits 677 MFE_U16 reg_mfe_s_mdc_h264_dbf_control:1; // dbf control present flag 678 MFE_U16 reg_mfe_s_mdc_h264_fnum_value:8; // H264 frame num value 679 }; 680 MFE_U16 reg39; 681 }; 682 union { 683 struct { 684 MFE_U16 reg_mfe_s_mdc_h264_idr_pic_id:3; 685 MFE_U16 reg_mfe_s_mdc_h264_disable_dbf_idc:2; 686 MFE_U16 reg_mfe_s_mdc_h264_alpha:4; // slice_alpha_c0_offset_div2 687 MFE_U16 reg_mfe_s_mdc_h264_beta:4; // slice_beta_offset_div2 688 MFE_U16 reg_mfe_s_mdc_h264_ridx_aor_flag:1; // reference index active override flag 689 }; 690 MFE_U16 reg3a; 691 }; 692 // BSPOBUF/MVOBUF 693 union { 694 struct { 695 MFE_U16 reg_mfe_s_bspobuf_set_adr:1; // set bsp obuf start address(write one clear) 696 MFE_U16 reg_mfe_s_mvobuf_set_adr:1; // set mv obuf start address (write one clear) 697 MFE_U16 reg_mfe_s_bspobuf_fifo_th:3; // bsp obuf threshold 698 MFE_U16 reg_mfe_s_mvobuf_fifo_th:3; // mv obuf threshold 699 MFE_U16 reg_mfe_s_bsp_fdc_skip:1; // fdc skip enable; 0: fdc skip disable, 1: fdc skip enable 700 }; 701 MFE_U16 reg3b; 702 }; 703 union { 704 struct { 705 MFE_U16 reg_mfe_s_bspobuf_sadr_low:16; // bsp obuf start address 706 }; 707 MFE_U16 reg3c; 708 }; 709 union { 710 struct { 711 MFE_U16 reg_mfe_s_bspobuf_sadr_high:OUTBUF_HI_BITS; // bsp obuf start address 712 }; 713 MFE_U16 reg3d; 714 }; 715 union { 716 struct { 717 MFE_U16 reg_mfe_s_bspobuf_eadr_low:16; // bsp obuf end address 718 }; 719 MFE_U16 reg3e; 720 }; 721 union { 722 struct { 723 MFE_U16 reg_mfe_s_bspobuf_eadr_high:OUTBUF_HI_BITS; // bsp obuf end address 724 }; 725 MFE_U16 reg3f; 726 }; 727 union { 728 struct { 729 MFE_U16 reg_mfe_s_mvobuf_sadr_low:16; // mv obuf start address 730 }; 731 MFE_U16 reg40; 732 }; 733 union { 734 struct { 735 MFE_U16 reg_mfe_s_mvobuf_sadr_high:OUTBUF_HI_BITS; // mv obuf start address 736 }; 737 MFE_U16 reg41; 738 }; 739 union { 740 struct { 741 MFE_U16 reg_mfe_s_bsp_bit_cnt_low:16; // encoded bit count (one frame) 742 }; 743 MFE_U16 reg42; 744 }; 745 union { 746 struct { 747 MFE_U16 reg_mfe_s_bsp_bit_cnt_high:BITCOUNT_HI_BITS; // encoded bit count (one frame) 748 }; 749 MFE_U16 reg43; 750 }; 751 union { 752 struct { 753 MFE_U16 reg_mfe_s_bspobuf_wptr_low:16; // bspobuf write pointer (8 byte unit) 754 }; 755 MFE_U16 reg44; 756 }; 757 union { 758 struct { 759 MFE_U16 reg_mfe_s_bspobuf_wptr_high:OUTBUF_HI_BITS; // bspobuf write pointer (8 byte unit) 760 }; 761 MFE_U16 reg45; 762 }; 763 // FDC 764 union { 765 struct { 766 MFE_U16 reg_mfe_s_fdc_bs:16; // cpu to fdc bitstream data 767 }; 768 MFE_U16 reg46; 769 }; 770 union { 771 struct { 772 MFE_U16 reg_mfe_s_fdc_bs_len:5; // cpu to fdc bitstream len; 0 ~ 16 773 MFE_U16 reg_mfe_s_fdc_bs_count:10; // cpu to fdc round count 774 }; 775 MFE_U16 reg47; 776 }; 777 // [Table Control] 778 union { 779 struct { 780 MFE_U16 reg_mfe_s_fdc_ack:1; // fdc to cpu ack; 0/1: frame data pool not empty/frame data pool empty; 48x64 bits of space 781 MFE_U16 reg_mfe_s_fdc_done_clr:1; // fdc done clear (write one clear) 782 MFE_U16 reg_mfe_s_fdc_done:1; // fdc done; indicate to CPU that data has been written to internal buffer 783 MFE_U16 reg48_dummy:8; 784 MFE_U16 reg_mfe_s_fdc_bs_vld:1; // set for bitstream write out (write one clear) 785 MFE_U16 reg_mfe_s_tbc_en:1; // set for table read & write ; 1: enable, 0: disable (write one clear) 786 }; 787 MFE_U16 reg48; 788 }; 789 union { 790 struct { 791 MFE_U16 reg_mfe_s_tbc_rw:1; // table mode; 0: read, 1: write 792 MFE_U16 reg_mfe_s_tbc_done_clr:1; // table done clear (write one clear) 793 MFE_U16 reg_mfe_s_tbc_done:1; // table done; indicate to CPU that (1) data has been written to table (2) table output is ready at reg_mfe_s_tbc_rdata 794 MFE_U16 reg49_dummy:5; 795 MFE_U16 reg_mfe_s_tbc_adr:6; // table address 796 }; 797 MFE_U16 reg49; 798 }; 799 union { 800 struct { 801 MFE_U16 reg_mfe_s_tbc_wdata:16; // table write data 802 }; 803 MFE_U16 reg4a; 804 }; 805 union { 806 struct { 807 MFE_U16 reg_mfe_s_tbc_rdata:16; // table read data 808 }; 809 MFE_U16 reg4b; 810 }; 811 // [Get Neighbor] 812 union { 813 struct { 814 MFE_U16 reg_mfe_s_gn_sadr_low:16; // gn base adr low 815 }; 816 MFE_U16 reg4c; 817 }; 818 union { 819 struct { 820 MFE_U16 reg_mfe_s_gn_sadr_high:OUTBUF_HI_BITS; // gn base adr high 821 }; 822 MFE_U16 reg4d; 823 }; 824 union { 825 struct { 826 MFE_U16 reg_mfe_s_gn_mvibuf_sadr_low:16; // mv ibuf start address low 827 }; 828 MFE_U16 reg4e; 829 }; 830 union { 831 struct { 832 MFE_U16 reg_mfe_s_gn_mvibuf_sadr_high:OUTBUF_HI_BITS; // mv ibuf start address high 833 }; 834 MFE_U16 reg4f; 835 }; 836 union { 837 struct { 838 MFE_U16 reg_mfe_s_marb_mrpriority_sw:2; // mfe2mi_rpriority software programmable 839 MFE_U16 reg_mfe_s_marb_mr_timeout_ref:1; //miu read burst timeout count start point 840 MFE_U16 reg_mfe_s_marb_mr_nwait_mw:1; //miu read not wait mi2mfe_wrdy 841 MFE_U16 reg_mfe_s_marb_mwpriority_sw:2; //mfe2mi_wpriority software programmable 842 MFE_U16 reg_mfe_s_marb_mw_timeout_ref:1; //miu write burst timeout count start point 843 MFE_U16 reg_mfe_s_marb_mw_nwait_mr:1; //miu read not wait mi2mfe_wrdy 844 MFE_U16 reg_mfe_s_marb_mr_pending:4; //max. pending read requests to miu 845 MFE_U16 reg_mfe_s_marb_32b_ad_nswap:1; //32bits miu address not swap. only for 32bits mode 846 MFE_U16 reg_mfe_s_marb_miu_wmode:1; //0/1: original miu protocol/new miu protocol(wd_en) 847 848 }; 849 MFE_U16 reg56; 850 }; 851 union { 852 struct { 853 MFE_U16 reg_mfe_s_marb_ubound_0_low:16; // MIU protect for MPEG4 BSP obuf 854 }; 855 MFE_U16 reg58; 856 }; 857 union { 858 struct { 859 MFE_U16 reg_mfe_s_marb_ubound_0_high:OUTBUF_HI_BITS; // MIU protect for MPEG4 BSP obuf 860 #if (10-OUTBUF_HI_BITS)>0 861 MFE_U16 reg_mfe_59_reserved:(10-OUTBUF_HI_BITS); 862 #endif 863 MFE_U16 reg_mfe_s_marb_miu_bound_err:1; //miu write protection, miu bound error status for write port 0 ~ 3 864 #ifndef _MFE_A3_ 865 MFE_U16 reg_mfe_s_marb_miu_off:1; //miu write protection, miu off 866 MFE_U16 reg_mfe_s_marb_miu_bound_en:4; //miu write protection, miu bound enable for write port 0 ~ 3 867 #endif 868 }; 869 MFE_U16 reg59; 870 }; 871 union { 872 struct { 873 MFE_U16 reg_mfe_s_marb_lbound_0_low:16; // MIU protect for MPEG4 BSP obuf 874 }; 875 MFE_U16 reg5a; 876 }; 877 union { 878 struct { 879 MFE_U16 reg_mfe_s_marb_lbound_0_high:OUTBUF_HI_BITS; // MIU protect for MPEG4 BSP obuf 880 #ifdef _MFE_A3_ 881 MFE_U16 reg_mfe_s_marb_miu_bound_en_0:1; // 882 #endif 883 }; 884 MFE_U16 reg5b; 885 }; 886 union { 887 struct { 888 MFE_U16 reg_mfe_s_marb_ubound_1_low:16; // MIU Upper bound protect for MPEG4 MC obuf rec 889 }; 890 MFE_U16 reg5c; 891 }; 892 union { 893 struct { 894 MFE_U16 reg_mfe_s_marb_ubound_1_high:OUTBUF_HI_BITS; // MIU Upper bound protect for MPEG4 MC obuf rec 895 }; 896 MFE_U16 reg5d; 897 }; 898 union { 899 struct { 900 MFE_U16 reg_mfe_s_marb_lbound_1_low:16; // MIU Lower bound protect for MPEG4 MC obuf 901 }; 902 MFE_U16 reg5e; 903 }; 904 union { 905 struct { 906 MFE_U16 reg_mfe_s_marb_lbound_1_high:OUTBUF_HI_BITS; // MIU Lower bound protect for MPEG4 MC obuf 907 #ifdef _MFE_A3_ 908 MFE_U16 reg_mfe_s_marb_miu_bound_en_1:1; // 909 #endif 910 }; 911 MFE_U16 reg5f; 912 }; 913 union { 914 struct { 915 MFE_U16 reg_mfe_s_marb_ubound_2_low:16; // MIU protect for MPEG4 MV obuf 916 }; 917 MFE_U16 reg60; 918 }; 919 union { 920 struct { 921 MFE_U16 reg_mfe_s_marb_ubound_2_high:OUTBUF_HI_BITS; // MIU protect for MPEG4 MV obuf 922 }; 923 MFE_U16 reg61; 924 }; 925 union { 926 struct { 927 MFE_U16 reg_mfe_s_marb_lbound_2_low:16; // MIU protect for MPEG4 MV obuf 928 }; 929 MFE_U16 reg62; 930 }; 931 union { 932 struct { 933 MFE_U16 reg_mfe_s_marb_lbound_2_high:OUTBUF_HI_BITS; // MIU protect for MPEG4 MV obuf 934 #ifdef _MFE_A3_ 935 MFE_U16 reg_mfe_s_marb_miu_bound_en_2:1; // 936 #endif 937 }; 938 MFE_U16 reg63; 939 }; 940 union { 941 struct { 942 MFE_U16 reg_mfe_s_marb_ubound_3_low:16; // MIU protect for MPEG4 GN 943 }; 944 MFE_U16 reg64; 945 }; 946 union { 947 struct { 948 MFE_U16 reg_mfe_s_marb_ubound_3_high:OUTBUF_HI_BITS; // MIU protect for MPEG4 GN 949 }; 950 MFE_U16 reg65; 951 }; 952 union { 953 struct { 954 MFE_U16 reg_mfe_s_marb_lbound_3_low:16; // MIU protect for MPEG4 GN 955 }; 956 MFE_U16 reg66; 957 }; 958 union { 959 struct { 960 MFE_U16 reg_mfe_s_marb_lbound_3_high:OUTBUF_HI_BITS; // MIU protect for MPEG4 GN 961 #ifdef _MFE_A3_ 962 MFE_U16 reg_mfe_s_marb_miu_bound_en_3:1; // 963 MFE_U16 reg_mfe_s_marb_miu_off:1; // 964 MFE_U16 reg_mfe_s_marb_miu_bound_err:1; // 965 #endif 966 }; 967 MFE_U16 reg67; 968 }; 969 union { 970 struct { 971 MFE_U16 reg_mfe_s_mbr_qstep_min:7; // qstep min (note: max value of qstep_min is 128 because condition is qstep <= qstep_min) 972 }; 973 MFE_U16 reg6e; 974 }; 975 union { 976 struct { 977 MFE_U16 reg_mfe_s_mbr_qstep_max:13; // qstep max 978 }; 979 MFE_U16 reg6f; 980 }; 981 union { 982 struct { 983 MFE_U16 reg_mfe_g_debug_mode:6; // debug mode 984 MFE_U16 reg_mfe_g_debug_trig_cycle:10; // wait (8 * reg_mfe_g_debug_trig_cycle) cycles 985 }; 986 MFE_U16 reg70; 987 }; 988 union { 989 struct { 990 MFE_U16 reg_mfe_g_debug_trig_mbx:9; // debug trigger mbx 991 }; 992 MFE_U16 reg71; 993 }; 994 union { 995 struct { 996 MFE_U16 reg_mfe_g_debug_trig_mby:9; // debug trigger mby 997 }; 998 MFE_U16 reg72; 999 }; 1000 union { 1001 struct { 1002 MFE_U16 reg_mfe_g_debug_trig:1; // reg trigger (write one clear) 1003 MFE_U16 reg_mfe_g_debug_trig_mode:2; // debug trigger mode; 0/1/2/3: reg_trigger/3rd stage (mbx, mby)/frame start 1004 MFE_U16 reg_mfe_g_debug_en:1; // debug enable 1005 MFE_U16 reg_mfe_g_crc_mode:4; //'h0: Disable,��hc: bsp obuf, 'hd: mc obuf, 'hd: mc obuf 1006 MFE_U16 reg_mfe_g_debug_tcycle_chk_en:1; //enable total cycle check 1007 MFE_U16 reg_mfe_g_debug_tcycle_chk_sel:1; //select total cycle and report it on reg_mfe_g_crc_result[15:0] 1008 }; 1009 MFE_U16 reg73; 1010 }; 1011 union { 1012 struct { 1013 MFE_U16 reg_mfe_g_debug_state0:16; // "debug state for TXIP/ECDB submodule {txip2q_en, txip2iq_en, txip2mbr_en, txip2zmem_en, txip2dpcm_en, 1014 // txip2mve_en, txip2mcobuf_en, txip2mbldr_en, ecdb2mdc_en, 1015 // ecdb2rlc_en, ecdb2vlc_en, 5'd0}" 1016 }; 1017 MFE_U16 reg74; 1018 }; 1019 union { 1020 struct { 1021 MFE_U16 reg_mfe_g_debug_state1; // "debug state for ME submodule {3'd0, load_w4_ok, load_w3_ok, load_w2_ok, load_w1_ok, load_w0_ok, 2'd0, 1022 // busy_ime, busy_fme, busy_mesr, busy_iacost, end_this_mb, init_this_mb" 1023 }; 1024 MFE_U16 reg75; 1025 }; 1026 union { 1027 struct { 1028 MFE_U16 reg_mfe_g_crc_result0:16; // CRC64[15..0] 1029 }; 1030 MFE_U16 reg76; 1031 }; 1032 union { 1033 struct { 1034 MFE_U16 reg_mfe_g_crc_result1:16; // CRC64[31..16] 1035 }; 1036 MFE_U16 reg77; 1037 }; 1038 union { 1039 struct { 1040 MFE_U16 reg_mfe_g_crc_result2:16; // CRC64[47..32] 1041 }; 1042 MFE_U16 reg78; 1043 }; 1044 union { 1045 struct { 1046 MFE_U16 reg_mfe_g_crc_result3:16; // CRC64[63..48] 1047 }; 1048 MFE_U16 reg79; 1049 }; 1050 union { 1051 struct { 1052 MFE_U16 reg_mfe_g_bist_fail0; 1053 }; 1054 MFE_U16 reg7a; 1055 }; 1056 union { 1057 struct { 1058 MFE_U16 reg_mfe_g_bist_fail1; 1059 }; 1060 MFE_U16 reg7b; 1061 }; 1062 union { 1063 struct { 1064 MFE_U16 reg_mfe_g_bist_fail2; 1065 }; 1066 MFE_U16 reg7c; 1067 }; 1068 union { 1069 struct { 1070 MFE_U16 reg_mfe_rsv0; 1071 }; 1072 MFE_U16 reg7d; 1073 }; 1074 union { 1075 struct { 1076 MFE_U16 reg_mfe_rsv1; 1077 }; 1078 MFE_U16 reg7e; 1079 }; 1080 union { 1081 struct { 1082 MFE_U16 reg_mfe_rsv2; 1083 }; 1084 MFE_U16 reg7f; 1085 }; 1086 1087 } MFE_REG; 1088 1089 ////////////////////////////////////////////////////////////////////////// 1090 // PERFORMANCE 1091 ////////////////////////////////////////////////////////////////////////// 1092 1093 #define CLOCK_GATING // Enable clock gating 1094 1095 #define FME_PIPELINE_OPEN // Enable David's FME speedup version 1096 1097 //#define DONT_PUT_FDC 1098 1099 ////////////////////////////////////////////////////////////////////////// 1100 // DEBUG Flags: FDC && QTable 1101 ////////////////////////////////////////////////////////////////////////// 1102 1103 //#define CHECK_FDC_DONE // Verify if hw receives the fdc command 1104 1105 //#define CHECK_WriteQTable_DONE // Verify if hw receives the WriteQTable command 1106 1107 //#define QTABLE_READBACK_CHECK // Verify all WriteQTable Value 1108 1109 ////////////////////////////////////////////////////////////////////////// 1110 // DEBUG Flags: StopAndGo series 1111 ////////////////////////////////////////////////////////////////////////// 1112 1113 #define STOP_FRAME 0 1114 #define STOP_MBX 7 1115 #define STOP_MBY 7 1116 // #define TEST_MB_STOPANDGO 1117 // #define TEST_MB_STOPANDDROP 1118 1119 // #define TEST_STOPANDGO 1120 // #define TEST_STOPANDDROP 1121 1122 1123 ////////////////////////////////////////////////////////////////////////// 1124 // DEBUG Flags: test miu protection 1125 ////////////////////////////////////////////////////////////////////////// 1126 1127 1128 #define TEST_MIU_PROTECTION_MODE 0 1129 1130 1131 1132 1133 1134 #ifdef REG_JPEG_CMODEL 1135 1136 ////////////////////////////////////////////////////////////////////////// 1137 // DEBUG Flags: continuous shot test (JPEG only) 1138 ////////////////////////////////////////////////////////////////////////// 1139 1140 //#define TEST_CONTINUOUS_SHOT 1141 //#define CONTINUOUS_SHOT_NUMBER 5 //number of test shot 1142 1143 ////////////////////////////////////////////////////////////////////////// 1144 // DEBUG Flags: input row mode test (JPEG only) 1145 ////////////////////////////////////////////////////////////////////////// 1146 //JPEG row mode only! 1147 // #define TEST_INPUT_ROW_MODE_HW 1148 1149 #ifdef TEST_INPUT_ROW_MODE_HW 1150 #ifndef DONT_PUT_FDC 1151 #define DONT_PUT_FDC 1152 #endif 1153 1154 #define NUM_OF_ROW_DONE_BEFORE_FS 1 1155 #endif 1156 1157 //JPEG row mode only! only check fs_fail_irq 1158 //#define TEST_INPUT_ROW_MODE_SW_HW 1159 #ifdef TEST_INPUT_ROW_MODE_SW_HW 1160 #define NUM_OF_ROW_DONE_BEFORE_FS 1 1161 #endif 1162 #endif // REG_JPEG_CMODEL 1163 ////////////////////////////////////////////////////////////////////////// 1164 // DEBUG Flags: test CRC mode 1165 ////////////////////////////////////////////////////////////////////////// 1166 #define TEST_CRC_MODE 1167 1168 #endif 1169 1170