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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef MHAL_FRC_H 96 #define MHAL_FRC_H 97 98 #include "hwreg_frc_map.h" 99 #include "hwreg_frc.h" 100 #include "hwreg_sc.h" 101 102 #ifdef MHAL_FRC_C 103 #define INTERFACE 104 #else 105 #define INTERFACE extern 106 #endif 107 108 //------------------------------------------------------------------------------------------------- 109 // Macro and Define 110 //------------------------------------------------------------------------------------------------- 111 #define FRC_MIU1_MEM_ADDR 0x20000000 112 #define CRYSTAL_CLOCK 12000000ul//24000000ul 113 #define MST_CLOCK_HZ CRYSTAL_CLOCK 114 #define MST_CLOCK_KHZ (MST_CLOCK_HZ / 1000) 115 #define MST_CLOCK_MHZ (MST_CLOCK_KHZ / 1000) 116 #define FRC_MAP_REG(reg) (((reg)>>8)&0xFF), ((reg)&0xFF) 117 #define FRC_IP_ALL 0xff 118 #define FRC_IP_NULL 0xff 119 #define REG_ADDR_SIZE 2 120 #define REG_MASK_SIZE 1 121 //#define REG_TABLE_END 0xFFFF 122 #define _END_OF_TBL_ 0xFFFF 123 #define MS_ALG_CMD_LEN 16 124 #define FRC_BK_SWITCH(_x_)\ 125 MDrv_WriteByte(REG_FRC_BANK_BASE, _x_) 126 #define FRC_BK_CURRENT \ 127 MDrv_ReadByte(REG_FRC_BANK_BASE) 128 129 #define VSTART_OFFSET 2 130 #define VSYNCSTART_OFFSET 14 131 #define VSYNC_FRONT_PORCH 11 132 133 #define FRCR2_MBX_QUEUESIZE 10 134 135 #define GOP_FSC_FHD_OFFSET_H 0x02 136 #define GOP_FSC_FHD_OFFSET_V 0x0C 137 #define GOP_FSC_4K_OFFSET_H 0x02 138 #define GOP_FSC_4K_OFFSET_V 0x0C 139 #define GOP_NO_FSC_OFFSET_H 0x00 140 #define GOP_NO_FSC_OFFSET_V 0x00 141 142 typedef struct 143 { 144 MS_U8 *pIPTable; 145 MS_U8 u8TabNums; 146 MS_U8 u8TabIdx; 147 } EN_FRC_IP_Info; 148 149 typedef struct 150 { 151 MS_U8 *pIPTable; 152 MS_U8 u8TabNums; 153 } EN_FRC_IPTAB_INFO; 154 155 typedef struct __attribute__((packed)) 156 { 157 MS_U8 u8FRC_InputType_Num; 158 MS_U8 u8FRC_IP_Num; 159 }FRCTABLE_INFO; 160 161 162 typedef enum 163 { 164 E_FRC_op2_gamma_table = 1, // gamma table 165 E_FRC_od_table = 2, // OD table 166 E_FRC_ld_table = 3, // Local diming table 167 } FRC_CLIENT_TABLE; 168 169 //------------------------------------------------------------------------------------------------- 170 // Structure enum 171 //------------------------------------------------------------------------------------------------- 172 173 typedef enum 174 { 175 FRC_IP_MEM_IP_YC_8 = 0x00, 176 FRC_IP_MEM_IP_YC_10 = 0x01, 177 FRC_IP_MEM_IP_RGB_8 = 0x02, 178 FRC_IP_MEM_IP_RGB_10 = 0x03, 179 FRC_IP_MEM_IP_YC_10_SPECIAL = 0x04, 180 FRC_IP_MEM_IP_YUV_8 = 0x05, 181 FRC_IP_MEM_IP_RGB_10_SPECIAL = 0x06, 182 FRC_IP_MEM_IP_YUV_10_SPECIAL = 0x07 183 184 } FRC_IP_MEM_MODE_e; 185 186 typedef enum 187 { 188 FRC_MIRROR_OFF, 189 FRC_MIRROR_H_MODE, 190 FRC_MIRROR_V_MODE, 191 FRC_MIRROR_HV_MODE 192 } FRC_MirrorModeType_e; 193 194 typedef struct MST_PANEL_INFO_s 195 { 196 // Basic 197 MS_U16 u16HStart; //ursa scaler 198 MS_U16 u16VStart; //ursa scaler 199 MS_U16 u16Width; //ursa scaler 200 MS_U16 u16Height; //ursa scaler 201 MS_U16 u16HTotal; //ursa scaler 202 MS_U16 u16VTotal; //ursa scaler 203 204 MS_U16 u16DE_VStart; 205 206 MS_U16 u16DefaultVFreq; 207 208 // LPLL 209 MS_U16 u16LPLL_InputDiv; 210 MS_U16 u16LPLL_LoopDiv; 211 MS_U16 u16LPLL_OutputDiv; 212 213 MS_U8 u8LPLL_Type; 214 MS_U8 u8LPLL_Mode; 215 216 // sync 217 MS_U8 u8HSyncWidth; 218 MS_BOOL bPnlDblVSync; 219 220 // output control 221 MS_U16 u16OCTRL; 222 MS_U16 u16OSTRL; 223 MS_U16 u16ODRV; 224 MS_U16 u16DITHCTRL; 225 226 // MOD 227 MS_U16 u16MOD_CTRL0; // BIT2: tiMode, BIT5: lvdsSwapPol, BIT6: lvdsSwapCh 228 MS_U8 u8MOD_CTRL2; 229 MS_U16 u16MOD_CTRL9; 230 MS_U16 u16MOD_CTRLA; // BIT2: invertDE, BIT3: invertVS, BIT12: invertHS 231 MS_U8 u8MOD_CTRLB; // BIT0~1: panelBitNums 232 233 MS_U8 u8MOD_CTRL77; //pre-emphasis level 234 MS_U8 u8MOD_CTRL78; 235 //LGE [vivakjh] 2008/11/12 Add for DVB PDP Panel 236 //Additional Info.(V Total) 237 MS_U16 u16VTotal60Hz; //ursa scaler 238 MS_U16 u16VTotal50Hz; //ursa scaler 239 MS_U16 u16VTotal48Hz; //ursa scaler 240 //[vivakjh] 2008/12/23 Add for adjusting the MRE in PDP S6 241 MS_U16 u16VStart60Hz; 242 MS_U16 u16VStart50Hz; 243 MS_U16 u16VStart48Hz; 244 MS_U16 u16VBackPorch60Hz; 245 MS_U16 u16VBackPorch50Hz; 246 MS_U16 u16VBackPorch48Hz; 247 248 /*Panel Option 249 0: LCD 250 1: PDP 251 2: LCD_NO_FRC 252 3: LCD_TCON 253 */ 254 MS_U8 u8LCDorPDP; 255 256 MS_U32 u32LimitD5d6d7; //thchen 20081216 257 MS_U16 u16LimitOffset; //thchen 20081216 258 MS_U8 u8LvdsSwingUp; 259 MS_BOOL bTTL_10BIT; 260 MS_BOOL bOD_DataPath; 261 262 //------------------------------------------------------------------------------------------------- 263 // FRC Control 264 //------------------------------------------------------------------------------------------------- 265 MS_BOOL bFRC; 266 MS_U16 u16MOD_SwingLevel; 267 MS_U16 u16MOD_SwingCLK; 268 MS_U16 u16output_cfg_10; 269 MS_U16 u16output_cfg_11; 270 MS_U16 u16output_cfg_12; 271 MS_U8 u8output_cfg_13; 272 MS_U8 u8PanelNoiseDith; 273 MS_U8 u8lvdsSwapCh; 274 MS_U8 u8FRC3DPanelType; 275 276 MS_BOOL bdither6Bits; 277 MS_BOOL blvdsShiftPair; 278 MS_BOOL blvdsSwapPair; 279 280 // TGEN 281 MS_U16 u16HSyncStart; 282 MS_U16 u16HSyncEnd; 283 MS_U16 u16VSyncStart; 284 MS_U16 u16VSyncEnd; 285 MS_U16 u16VTrigX; 286 MS_U16 u16VTrigY; 287 288 // EPI 289 MS_BOOL bepiLRSwap; 290 MS_BOOL bepiLMirror; 291 MS_BOOL bepiRMirror; 292 293 } MST_PANEL_INFO_t, *PMST_PANEL_INFO_t; 294 295 // for composer setting 296 typedef enum 297 { 298 E_FRC_COMPOSER_SOURCE_MODE_VIP = 0, // only STGEN disable case use this! 299 E_FRC_COMPOSER_SOURCE_MODE_FSC = 1, 300 E_FRC_COMPOSER_SOURCE_MODE_FRC = 2, 301 E_FRC_COMPOSER_SOURCE_MODE_VIP_FB = 3, 302 } E_FRC_COMPOSER_SOURCE_MODE; 303 304 typedef enum 305 { 306 E_FRC_PIPE_DELAY_MODE_FIXED = 0, 307 E_FRC_PIPE_DELAY_MODE_USER = 1, 308 E_FRC_PIPE_DELAY_MODE_AUTO = 2, 309 } E_FRC_PIPE_DELAY_MODE; 310 311 typedef enum 312 { 313 E_FRC_TGEN_LOCK_SOURCE_MODE_FROM_IP = 0, // with FRC case 314 E_FRC_TGEN_LOCK_SOURCE_MODE_FROM_TGEN = 1, // no FRC case 315 } E_FRC_TGEN_LOCK_SOURCE_MODE; 316 317 typedef enum 318 { 319 E_FRC_STGEN_ODCLK_1 = 0, // ODLCK 320 E_FRC_STGEN_ODCLK_2 = 1, // ODLCK/2 321 E_FRC_STGEN_ODCLK_4 = 2, // ODCLK/4 322 } E_FRC_STGEN_ODCLK; 323 324 typedef enum 325 { 326 E_FRC_FSC_SOURCE_MODE_MDE = 0, // vip to fsc's de selection use MDE 327 E_FRC_FSC_SOURCE_MODE_FDE = 1, 328 } E_FRC_FSC_SOURCE_MODE; 329 330 typedef enum 331 { 332 E_FRC_MLOAD_TRIG_MODE_FROM_OP1 = 0, // no FRC case, menuload trig form tgen 333 E_FRC_MLOAD_TRIG_MODE_FROM_OP2 = 1, // with FRC case, menuload trig form stgen 334 } E_FRC_MLOAD_TRIG_MODE; 335 336 //------------------------------------------------------------------------------------------------- 337 // Function and Variable 338 //------------------------------------------------------------------------------------------------- 339 #define MHal_FRC_IsRGB(args...) 0 340 341 #define MHal_FRC_TGEN_SWReset(args...) 342 #define MHal_FRC_TGEN_DoubleBuf(args...) 343 #define MHal_FRC_TGEN_SetVTotal(args...) 344 #define MHal_FRC_TGEN_SetHTotal(args...) 345 #define MHal_FRC_TGEN_SetVTrigY(args...) 346 #define MHal_FRC_TGEN_SetVTrigX(args...) 347 #define MHal_FRC_TGEN_SetVSyncStartEndY(args...) 348 #define MHal_FRC_TGEN_SetHSyncStartEndX(args...) 349 #define MHal_FRC_TGEN_SetFdeStartEndY(args...) 350 #define MHal_FRC_TGEN_SetFdeStartEndX(args...) 351 #define MHal_FRC_TGEN_SetMdeStartEndY(args...) 352 #define MHal_FRC_TGEN_SetMdeStartEndX(args...) 353 #define MHal_FRC_TGEN_SetSubMdeStartEndY(args...) 354 #define MHal_FRC_TGEN_SetSubMdeStartEndX(args...) 355 356 #define MHal_FRC_TGEN_FpllRefPointY(args...) 357 #define MHal_FRC_TGEN_1Clk2PixOut(args...) 358 #define MHal_FRC_TGEN_SetSyncHcnt(args...) 359 #define MHal_FRC_TGEN_SetClrSyncAhead(args...) 360 361 #define MHal_FRC_TGEN_Init(args...) 362 #define MHal_FRC_TGEN_Enable_LockMode(args...) 363 #define MHal_FRC_TGEN_Enable_Source_Select_Mode(args...) 364 //INTERFACE void MHal_FRC_TGEN_Set_Lock_Source(void *pInstance, E_FRC_TGEN_LOCK_SOURCE_MODE eMode); 365 #define MHal_FRC_TGEN_Enable_Lock_Source(args...) 366 367 #define MHal_FRC_SetYTrig(args...) 368 369 #define MHal_FRC_Enable_MiuMask(args...) 370 #define MHal_FRC_Disable_MiuMask(args...) 371 #define MHal_FRC_set_miusel(args...) 372 373 #define MHal_FRC_PNLInfo_Transform(args...) 374 #define MHal_FRC_IPM_SoftwareReset(args...) 375 #define MHal_FRC_IPM_RWEn(args...) 376 #define MHal_FRC_IPM_RW_CEN_Select(args...) 377 #define MHal_FRC_IPM_SetYuv10Bit(args...) 378 #define MHal_FRC_IPM_SetMr(args...) 379 #define MHal_FRC_IPM_SetMemoryMode(args...) 380 #define MHal_FRC_IPM_YC444To422Control(args...) 381 #define MHal_FRC_IPM_SetFrameBufferNum(args...) 382 #define MHal_FRC_IPM_CeLineCountEn(args...) 383 #define MHal_FRC_IPM_SetBaseAddr(args...) 384 #define MHal_FRC_IPM_R_SetBaseAddr(args...) 385 #define MHal_FRC_IPM_SetIp2Mc(args...) 386 #define MHal_FRC_IPM_SetYCoutLinePitch(args...) 387 #define MHal_FRC_IPM_SetReadFetchNumber(args...) 388 #define MHal_FRC_IPM_SetWriteFetchNumber(args...) 389 #define MHal_FRC_IPM_SetRfifoThr(args...) 390 #define MHal_FRC_IPM_SetWfifoThr(args...) 391 #define MHal_FRC_IPM_SetReadLength(args...) 392 #define MHal_FRC_IPM_SetWriteLength(args...) 393 #define MHal_FRC_IPM_SetHTotalPixellimit(args...) 394 #define MHal_FRC_IPM_SetVTotalPixellimit(args...) 395 #define MHal_FRC_IPM_SetRmaskNum(args...) 396 #define MHal_FRC_IPM_SetWmaskNum(args...) 397 #define MHal_FRC_IPM_SetMirrorMode(args...) 398 #define MHal_FRC_IPM_PacketInitCnt(args...) 399 #define MHal_FRC_IPM_SetLvdsInputMode(args...) 400 #define MHal_FRC_IPM_SetOsdWinIdx(args...) 401 #define MHal_FRC_IPM_SetVPulseLineRst(args...) 402 #define MHal_FRC_IPM_SetVPulseLoc(args...) 403 #define MHal_FRC_IPM_SetLockIntCtrl(args...) 404 #define MHal_FRC_IPM_SetBlankBoundary(args...) 405 #define MHal_FRC_IPM_GetHTotal(args...) 0 406 #define MHal_FRC_IPM_GetVTotal(args...) 0 407 #define MHal_FRC_IPM_GetHde(args...) 0 408 #define MHal_FRC_IPM_GetVde(args...) 0 409 #define MHal_FRC_IPM_Csc(args...) 410 #define MHal_FRC_IPM_CscDither(args...) 411 #define MHal_FRC_IPM_CscRound(args...) 412 #define MHal_FRC_IPM_CscSaturation(args...) 413 #define MHal_FRC_IPM_CheckBoardEn(args...) 414 #define MHal_FRC_IPM_SetIpCtrl(args...) 415 #define MHal_FRC_IPM_SetHRefLock(args...) 416 #define MHal_FRC_IPM_GetHdeCount(args...) 0 417 #define MHal_FRC_IPM_TestPattern(args...) 418 #define MHal_FRC_IPM_SetHTotal(args...) 419 #define MHal_FRC_IPM_SetVTotal(args...) 420 #define MHal_FRC_IPM_HActive(args...) 421 #define MHal_FRC_IPM_VActive(args...) 422 #define MHal_FRC_IPM_GetYcoutLinePitch(args...) 0 423 #define MHal_FRC_IPM_GetWriteFetchNum(args...) 0 424 #define MHal_FRC_IPM_GetReadFetchNum(args...) 0 425 #define MHal_FRC_IPM_GetLineLimit(args...) 0 426 #define MHal_FRC_IPM_SetPacketCount(args...) 427 #define MHal_FRC_IPM_GetFrameYcout(args...) 0 428 #define MHal_FRC_IPM_3DFlag_In_SWMode_En(args...) 429 #define MHal_FRC_IPM_3DFlag_In_SWMode_SetIdx(args...) 430 #define MHal_FRC_IPM_3DFlag_In_HWMode_SrcSel(args...) 431 #define MHal_FRC_IPM_GetIPVfreqX10(args...) 0 432 433 434 435 #define MHal_FRC_OPM_SetFbLineOffset_Data(args...) 436 #define MHal_FRC_OPM_SetFbLineOffset_Me3(args...) 437 #define MHal_FRC_OPM_SetSrcPixNum(args...) 438 #define MHal_FRC_OPM_SetSrcLineNum(args...) 439 #define MHal_FRC_OPM_CeLineCountEn(args...) 440 #define MHal_FRC_OPM_SetLbiSrcPixelNum_Left(args...) 441 #define MHal_FRC_OPM_SetLbiReadPixelNum_Left(args...) 442 #define MHal_FRC_OPM_SetLbiSkipEn(args...) 443 #define MHal_FRC_OPM_SetLbiSkipNum_Left(args...) 444 #define MHal_FRC_OPM_SetLbiSrcPixelNum_Right(args...) 445 #define MHal_FRC_OPM_SetLbiReadPixelNum_Right(args...) 446 #define MHal_FRC_OPM_SetLbiSkipEn3D(args...) 447 #define MHal_FRC_OPM_SetLbiSkipNum_Right(args...) 448 #define MHal_FRC_OPM_FuncEn(args...) 449 #define MHal_FRC_OPM_3dFuncEn(args...) 450 #define MHal_FRC_OPM_SetBaseOffset_Data0(args...) 451 #define MHal_FRC_OPM_SetBaseOffset_Data1(args...) 452 #define MHal_FRC_OPM_SetBaseOffset_Me0(args...) 453 #define MHal_FRC_OPM_SetBaseOffset_Me1(args...) 454 #define MHal_FRC_OPM_SetBaseOffset_Me3(args...) 455 #define MHal_FRC_OPM_SetBaseOffset_Da0_L(args...) 456 #define MHal_FRC_OPM_SetBaseOffset_Da1_L(args...) 457 #define MHal_FRC_OPM_SetBaseOffset_Me0_L(args...) 458 #define MHal_FRC_OPM_SetBaseOffset_Me1_L(args...) 459 #define MHal_FRC_OPM_SetBaseOffset_Me3_L(args...) 460 #define MHal_FRC_OPM_SetBaseOffset_Mr1_L(args...) 461 #define MHal_FRC_OPM_SetBaseOffset_Mr1(args...) 462 #define MHal_FRC_OPM_SetDebugMask(args...) 463 #define MHal_FRC_OPM_SwReset(args...) 464 #define MHal_FRC_OPM_enableBaseAdrMr(args...) 465 #define MHal_FRC_OPM_SetBaseAddr(args...) 466 #define MHal_FRC_OPM_R_SetBaseAddr(args...) 467 #define MHal_FRC_OPM_SetMlbOutRstCycle(args...) 468 #define MHal_FRC_OPM_SetFifoTrigThr(args...) 469 #define MHal_FRC_OPM_SetFifoMaxReadReq(args...) 470 #define MHal_FRC_OPM_SetGatingClk(args...) 471 #define MHal_FRC_SetMemMode(args...) 472 473 #define MHal_FRC_OP2_ColorMatrixEn(args...) 474 #define MHal_FRC_OP2_CscDitherEn(args...) 475 #define MHal_FRC_OP2_DataPathEn(args...) 476 #define MHal_FRC_OP2_DebugFuncEn(args...) 477 #define MHal_FRC_OP2_SetGain_R(args...) 478 #define MHal_FRC_OP2_SetGain_G(args...) 479 #define MHal_FRC_OP2_SetGain_B(args...) 480 #define MHal_FRC_OP2_SetOffset_R(args...) 481 #define MHal_FRC_OP2_SetOffset_G(args...) 482 #define MHal_FRC_OP2_SetOffset_B(args...) 483 #define MHal_FRC_OP2_SetDither(args...) 484 #define MHal_FRC_OP2_PAFRC_FuncEn(args...) 485 #define MHal_FRC_OP2_PAFRC_FuncEn2(args...) 486 #define MHal_FRC_OP2_PAFRC_FuncEn3(args...) 487 #define MHal_FRC_OP2_PAFRC_Set2x2BlockRotDir(args...) 488 #define MHal_FRC_OP2_PAFRC_TopBoxFrSeq(args...) 489 #define MHal_FRC_OP2_PAFRC_TopBoxFrC2Seq(args...) 490 #define MHal_FRC_OP2_PAFRC_SetBoxRotDir(args...) 491 #define MHal_FRC_OP2_PAFRC_Set8x8BoxRotDir(args...) 492 #define MHal_FRC_OP2_PAFRC_SetBlockEntities(args...) 493 #define MHal_FRC_OP2_PAFRC_PolarityCtrl(args...) 494 #define MHal_FRC_OP2_PAFRC_SetBoxLsbValue(args...) 495 496 #define MHal_FRC_SCTOP_SCMI_Bypass_Enable(args...) 497 #define MHal_FRC_SCTOP_FRC_Bypass_Enable(args...) 498 499 #define MHal_FRC_SNR_SetPixelHorixontalNum(args...) 500 #define MHal_FRC_SNR_SetLineVerticalNum(args...) 501 502 #define MHal_FRC_SCP_HSU1_HSP(args...) 503 #define MHal_FRC_SCP_HSU1_Init_Position(args...) 504 #define MHal_FRC_SCP_HSU1_Scaling_Mode(args...) 505 #define MHal_FRC_SCP_HSU1_444to422_Mode(args...) 506 #define MHal_FRC_SCP_HSU1_VSU_Scaling_Mode(args...) 507 #define MHal_FRC_SCP_HSU1_VSU_Scaling_coef(args...) 508 #define MHal_FRC_SCP_HSU2_HSP(args...) 509 #define MHal_FRC_SCP_HSU2_Init_Position(args...) 510 #define MHal_FRC_SCP_HSU2_Scaling_Mode(args...) 511 512 #define MHal_FRC_OD_SetBaseAddr(args...) 513 #define MHal_FRC_LD_SetBaseAddr(args...) 514 #define MHal_FRC_LD_Edge2D_SetBaseAddr(args...) 515 #define MHal_FRC_ME1_SetBaseAddr(args...) 516 #define MHal_FRC_ME2_SetBaseAddr(args...) 517 #define MHal_FRC_2D3D_Render_SetBaseAddr(args...) 518 #define MHal_FRC_2D3D_Render_Detection_SetBaseAddr(args...) 519 #define MHal_FRC_Halo_SetBaseAddr(args...) 520 #define MHal_FRC_OverDriverSwitch(args...) 521 #define MHal_FRC_OD_Init(args...) 522 #define MHal_FRC_Tx_SetTgen(args...) 523 #define MHal_XC_Is_DSForceIndexEnabled(args...) 524 525 // for FRC init 526 #define MHal_FRC_Init(args...) 527 #define MHal_FRC_ByPass_Enable(args...) 528 529 #define MHal_FRC_LoadTabelbySrcType(args...) 530 #define MHal_FRC_Set_3D_QMap(args...) 531 532 533 //FRC R2 Mail Box Control 534 #define MHal_XC_SendCmdToFRC(args...) 0 535 #define MHal_XC_GetMsgFromFRC(args...) 0 536 537 #define Hal_XC_FRC_R2_Get_SwVersion(args...) 0 538 #define Hal_XC_FRC_R2_Get_CmdVersion(args...) 0 539 #define Hal_XC_FRC_R2_Init(args...) 0 540 #define Hal_XC_FRC_R2_Set_Timing(args...) 0 541 #define Hal_XC_FRC_R2_Set_InputFrameSize(args...) 0 542 #define Hal_XC_FRC_R2_Set_OutputFrameSize(args...) 0 543 #define Hal_XC_FRC_R2_Set_FPLL_Lockdone(args...) 0 544 #define Hal_XC_FRC_R2_Enable_MEMC(args...) 0 545 546 #define Hal_XC_FRC_R2_Set_Input3DFormat(args...) 547 #define Hal_XC_FRC_R2_Set_MfcMode(args...) 548 #define Hal_XC_FRC_R2_Set_MfcDemoMode(args...) 549 #define Hal_XC_FRC_R2_Set_LocalDimmingMode(args...) 550 #define Hal_XC_FRC_R2_Set_2DTo3DMode(args...) 0 551 552 //FRC auto download 553 #define Hal_FRC_ADLG_set_base_addr(args...) 554 #define Hal_FRC_ADLG_set_depth(args...) 555 #define Hal_FRC_ADLG_set_dma(args...) 556 #define Hal_FRC_ADLG_set_on_off(args...) 557 558 #define Hal_FRC_get_table_idx(args...) FRC_NOTSUPPORT_MODE 559 560 #define MHal_XC_OC_set_HSyncStartEnd(args...) 561 #define MHal_XC_OC_set_VSyncStartEnd(args...) 562 #define MHal_XC_OC_set_HFdeStartEnd(args...) 563 #define MHal_XC_OC_set_VFdeStartEnd(args...) 564 #define MHal_XC_OC_set_HTotal(args...) 565 #define MHal_XC_OC_set_VTotal(args...) 566 567 #define MHal_FRC_IPM_SetOffset(args...) 568 #define MHal_FRC_IPM_SetFetchNum(args...) 569 #define MHal_FRC_OPM_SetOffset(args...) 570 #define MHal_FRC_OPM_SetFetchNum(args...) 571 #define MHal_FRC_HSU_SetScalingSize(args...) 572 #define MHal_FRC_VSU_SetScalingSize(args...) 573 #define MHal_FRC_CSC_SelectPath(args...) 574 575 #define MHal_FRC_interrupt_mask(args...) 576 #define MHal_FRC_Mute(args...) 577 #define MHal_FRC_3DLR_Select(args...) 578 579 #define MHal_FRC_Composer_User_Mode_Enable(args...) 580 #define MHal_FRC_Set_Composer_User_Mode(args...) 581 582 #define MHal_FRC_Set_Pipe_Delay_Mode(args...) 583 #define MHal_FRC_Set_Pipe_Delay_Value(args...) 584 #define MHal_FRC_Set_Pipe_Delay_Reset(args...) 585 586 #define MHal_FRC_Set_STGEN_ODCLK(args...) 587 #define MHal_FRC_Set_FSC_DE_Selection(args...) 588 #define MHal_FRC_IsFHDToFSC(args...) 0 589 #define MHal_FRC_IsSupportFRC_byEfuse(args...) 0 590 #define MHal_FRC_AdjustGOPPosition(args...) 591 #define MHal_FRC_GetGOPOffset(args...) 592 593 #define MHal_FRC_Set_Mload_Trig_Mode(args...) 594 595 #define MHal_FRC_Mute(args...) 596 #define MHal_FRC_SetMemFormat(args...) 597 #define MHal_FRC_Tx_SetTgen(args...) 598 #define MHal_FRC_IPM_Init(args...) 599 #define MHal_FRC_UpdateMDE(args...) 600 INTERFACE MS_BOOL Hal_XC_Get_Stgen_Lock_Ip_status(void *pInstance); 601 #undef INTERFACE 602 #endif /* MHAL_FRC_H */ 603 604