1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2006-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 #include "MFE_chip.h"
96 #include "mfe_common.h"
97 #include "mfe_type.h"
98 #include "ms_dprintf.h"
99
100 #include "mdrv_mfe_io.h"
101 #include "mdrv_mfe_st.h"
102
103 #ifdef _FPGA_
104 #include "fpga_def.h"
105 #endif
106
107 #if defined(_MFE_T8_)&&defined(_KERNEL_MODE_)
108 #include <linux/autoconf.h>
109 #include <linux/module.h>
110 #include <linux/moduleparam.h>
111 #include <linux/init.h>
112 #include <linux/sched.h>
113 #include <linux/kernel.h>
114 //#include "chip_int.h"
115
116 #include <linux/fs.h>
117 #include <linux/cdev.h>
118 #include <linux/errno.h>
119 #include <linux/delay.h>
120 #include <linux/kdev_t.h>
121 #include <linux/slab.h>
122 #include <linux/mm.h>
123 #include <linux/ioport.h>
124 #include <linux/interrupt.h>
125 #include <linux/workqueue.h>
126 #include <linux/poll.h>
127 #include <linux/wait.h>
128 #include <linux/cdev.h>
129 #include <linux/time.h> //added
130 #include <linux/timer.h> //added
131 #include <asm/io.h>
132 #include "mdrv_probe.h"
133 // #include "pthread_map.h"
134 #else
135 #include <semaphore.h>
136 #include "pthread.h"
137 #endif
138
139 #ifdef _ENABLE_ISR_
140 static int attach_ISR=1; //for AEON ISR attach
141 #endif
142
143 #ifdef _AEON_PLATFORM_
144 #ifdef _MFE_T8_
145 #include "mdrv_irq.h"
146 #include "drvISR.h"
147 #endif
148
149 #endif
150
151 #if defined(WIN32) && defined(_ENABLE_ISR_)
152 //#include <malloc.h>
153 #include <windows.h>
154 #include "pthread.h"
155 #endif
156
157 #if defined(_MFE_T8_)&&defined(_MIPS_PLATFORM_)&&(!defined(_KERNEL_MODE_))
158 #include "MsCommon.h"
159 #include "MsOS.h"
160 #include "drvMMIO.h"
161 #include "pthread_map.h"
162 #endif
163
164 #if defined(_MFE_T8_)&&defined(_MIPS_PLATFORM_)&&defined(_KERNEL_MODE_)
165 #include <linux/kernel.h>
166 #include <linux/string.h>
167 #include <linux/semaphore.h>
168 #include <linux/interrupt.h>
169 #include <linux/kdev_t.h>
170 #include "chip_int.h"
171 #include "mst_devid.h"
172 #include "mdrv_probe.h"
173 #include "mst_devid.h"
174 //#include "./Aeon/drvMFE.h"
175 #else
176 //#include "drvMFE.h"
177 #include <string.h>
178 #endif
179
180 #include "mhal_mfe.h"
181 #include "memmap.h"
182 #include "mdrv_mfe.h"
183 #include "stdarg.h"
184
185 #include "BufMng.h"
186
187
188 #ifdef WIN32
189 #include "sigdump_api.h"
190 #endif
191
192
193 #if defined(_MFE_T8_)&&defined(_MIPS_PLATFORM_)&&defined(_KERNEL_MODE_)
194 #include "mdrv_system.h" //for addr_phy2log
195 #endif
196
197 MFE_HW_STATUS hw_status;
198
199 OutBitSBUF outbitsbuf[MAX_OUTBUFFER];
200 int rbits_index=0;
201 static MFE_U32 _MFE_U32MFEEvent = 0;
202 BITSFRAME_INFO bitsframe[MAX_OUTBUFFER];
203
204 MFE_CONFIG gMfeConfig, *gpMfeConfig = &gMfeConfig;
205 GOPINFO gGopInfo, *gpGopInfo = &gGopInfo;
206
207 #ifdef CRC_CHECK
208 #include "CRC64.h"
209 CRC_INFO gCRC_AllFrames;
210 CRC_INFO gCRC_DramBitstream;
211 #endif
212 volatile MFE_STAT encode_state;
213 MFE_BOOL g_bForceIframe = FALSE;
214
215 MFE_U32 MFE_U32MFEMIUOffset=0;
216
217 MFE_U32 MFEClockLevel = 3; //0 to 3 = 123,144,172,192 MHz
218
219 #ifdef _WIN32 //!defined(_AEON_PLATFORM_) && !defined(_MIPS_PLATFORM_)
220 MFE_S8 Script_Buffer[2048];
221 #endif
222
223 // This is for Main() FPGA test-case verification.
224 #define _MAIN_TEST_
225 #if defined(_MAIN_TEST_)
226 #if defined(_MFE_T8_)&&defined(_KERNEL_MODE_)
227
228 #else
229 // extern int TEST_CASE_FORMAT;
230 // extern int TEST_CASE_NUM;
231 #endif
232 #endif
233
234 #ifdef DRV_MFE_TIME_MEASURE
235 #include "mdrv_types.h"
236 #include "../scaler/titania8/mhal_utility.h"
237 #include "../scaler/titania8/mhal_scaler_reg.h"
238
MFE_MsOS_START_TIMER(void)239 void MFE_MsOS_START_TIMER (void)
240 {
241 REG_WR(REG_PIU_TIMER0(0x00), 0x0);
242 REG_WR(REG_PIU_TIMER0(0x00), 0x1);
243 }
244
MFE_MsOS_PRINT_TIMER(void)245 static inline void MFE_MsOS_PRINT_TIMER (void)
246 {
247 MFE_U32 MFE_U32Timer;
248 MFE_U32Timer = ((MFE_U32)REG_RR(REG_PIU_TIMER0(0x04))) |
249 ((MFE_U32)REG_RR(REG_PIU_TIMER0(0x05)) << 16); // h0005:h0004
250 //printk("MFE encode time=%u us\n", MFE_U32Timer/12);
251 printk("%u\n", MFE_U32Timer/12);
252 }
253 #endif
254
255
256
257 #if defined(_MFE_T8_)&&defined(_KERNEL_MODE_)
258 struct MFE_Dev g_MFE_Dev;
259 static wait_queue_head_t _MFE_wait_queue;
260 static spinlock_t _spinlock;
261
262 MFE_S32 MDrv_MFE_Open(struct inode *inode, struct file *filp);
263 MFE_S32 MDrv_MFE_Release(struct inode *inode, struct file *filp);
264 MFE_S32 MDrv_MFE__mmap(struct file *filp, struct vm_area_struct *vma);
265 static MFE_U32 MDrv_MFE_poll(struct file *filp, poll_table *wait);
266
267 int MDrv_MFE_Ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg);
268 struct file_operations MFE_Fops = {
269 .owner = THIS_MODULE,
270 .ioctl = MDrv_MFE_Ioctl,
271 .open = MDrv_MFE_Open,
272 .release = MDrv_MFE_Release,
273 .mmap = MDrv_MFE__mmap,
274 .poll = MDrv_MFE_poll,
275 };
276 #else
277 #if defined(_MFE_UTOPIA_)&&defined(_MIPS_PLATFORM_)
278 MFE_S32 _MFE_wait_queue;
279 #else
280 sem_t _MFE_wait_queue;
281 #endif
282 pthread_mutex_t _spinlock;
283 #define wake_up(a) sem_post(a)
284 #define spin_lock pthread_mutex_lock
285 #define spin_unlock pthread_mutex_unlock
286 #define spin_lock_init pthread_mutex_init
287 #ifdef _WIN32
288 #define PROBE_IO_ENTRY
289 #define _IOC_NR
290 #define PROBE_IO_EXIT
291 #else
292 #define PROBE_IO_ENTRY(fmt, args...)
293 //#define _IOC_NR(fmt, args...)
294 #define PROBE_IO_EXIT(fmt, args...)
295 #endif
296 #define MDRV_MAJOR_MFE 0
297 #endif //defined(_MFE_T8_)&&defined(_KERNEL_MODE_)
298
299
MDrv_MFE_Sem_Init(void)300 static void MDrv_MFE_Sem_Init(void)
301 {
302 char name[] = "DRV_MFE_SEM";
303 #if defined(_MFE_UTOPIA_)&&defined(_MIPS_PLATFORM_)
304 _MFE_wait_queue = MsOS_CreateSemaphore(0,E_MSOS_FIFO ,name) ;
305 #elif !(defined(_MFE_T8_)&&defined(_KERNEL_MODE_))
306 sem_init(&_MFE_wait_queue, 0, 0);
307 #endif
308
309 }
310
MDrv_MFE_Sem_Wait(MFE_U32 u32WaitMs)311 static MFE_BOOL MDrv_MFE_Sem_Wait(MFE_U32 u32WaitMs)
312 {
313 #if defined(_MFE_UTOPIA_)&&defined(_MIPS_PLATFORM_)
314 return MsOS_ObtainSemaphore(_MFE_wait_queue, u32WaitMs);
315 #elif !(defined(_MFE_T8_)&&defined(_KERNEL_MODE_))
316 sem_wait(&_MFE_wait_queue);
317 #endif
318
319 }
320
MDrv_MFE_Sem_Destroy(void)321 static void MDrv_MFE_Sem_Destroy(void)
322 {
323 #if defined(_MFE_UTOPIA_)&&defined(_MIPS_PLATFORM_)
324 // MsOS_ReleaseSemaphore(_MFE_wait_queue);
325 MsOS_DeleteSemaphore(_MFE_wait_queue);
326 #elif !(defined(_MFE_T8_)&&defined(_KERNEL_MODE_))
327 sem_destroy(&_MFE_wait_queue);
328 #endif
329
330 }
331
MDrv_MFE_Sem_Wake_Up(void)332 static void MDrv_MFE_Sem_Wake_Up(void)
333 {
334 #if defined(_MFE_UTOPIA_)&&defined(_MIPS_PLATFORM_)
335 MsOS_ReleaseSemaphore(_MFE_wait_queue);
336 #elif !(defined(_MFE_T8_)&&defined(_KERNEL_MODE_))
337 wake_up(&_MFE_wait_queue);
338 #endif
339
340 }
341
342 static MFE_BOOL MDrv_MFE_CheckEncodeDone(MFE_CONFIG *pConfig);
343
344 // user mode function
345 #if defined(_MFE_T8_) && defined(_MIPS_PLATFORM_)&& !defined(_KERNEL_MODE_)
MDrv_MFE_SetOSRegBase(MFE_U32 MFE_U32RegBaseAddr)346 void MDrv_MFE_SetOSRegBase( MFE_U32 MFE_U32RegBaseAddr )
347 {
348 MHAL_MFE_InitRegBase( (MFE_U32)MFE_U32RegBaseAddr );
349 }
350 #endif
351
352 //////////////////////////////////////////////////////////////////////////
353 // Kernel driver specific
354 //////////////////////////////////////////////////////////////////////////
355
356 #if defined(_MFE_T8_)&&defined(_KERNEL_MODE_)
357
MDrv_MFE_Open(struct inode * inode,struct file * filp)358 S32 MDrv_MFE_Open(struct inode *inode, struct file *filp)
359 {
360 return 0;
361
362 }
363
MDrv_MFE_Release(struct inode * inode,struct file * filp)364 S32 MDrv_MFE_Release(struct inode *inode, struct file *filp)
365 {
366 // free_irq(E_IRQ_MFE, NULL)
367
368 return 0;
369 }
370
MDrv_MFE__mmap(struct file * filp,struct vm_area_struct * vma)371 S32 MDrv_MFE__mmap(struct file *filp, struct vm_area_struct *vma)
372 {
373 return 0;
374 }
375
MDrv_MFE_poll(struct file * filp,poll_table * wait)376 static unsigned int MDrv_MFE_poll(struct file *filp, poll_table *wait)
377 {
378 unsigned int ret;
379 // ms_dprintk(DRV_L4, "MDrv_MFE_poll is invoked 0x%x\n", &_MFE_wait_queue);
380 poll_wait(filp, &_MFE_wait_queue, wait);
381 // ms_dprintk(DRV_L4, "MDrv_MFE_poll is waken up %d\n", _MFE_U32MFEEvent);
382 spin_lock(&_spinlock);
383 ret = _MFE_U32MFEEvent ? POLLIN : 0;
384 ms_dprintk(DRV_L4, "leave MDrv_MFE_poll, %d %d\n", ret, _MFE_U32MFEEvent);
385 spin_unlock(&_spinlock);
386 return ret;// | POLLPRI;
387 }
388
MDrv_MFE_ModuleInit(void)389 static int __init MDrv_MFE_ModuleInit(void)
390 {
391 dev_t devno;
392 int result;
393 ms_dprintk(DRV_L4, "in MDrv_MFE_ModuleInit\n");
394 devno = MKDEV(MDRV_MAJOR_MFE, MDRV_MINOR_MFE);
395 result = register_chrdev_region(devno, 1, MDRV_NAME_MFE);
396 if ( result < 0)
397 {
398 ms_dprintk(DRV_L4, KERN_WARNING "MFE: can't get major %d\n", MDRV_MAJOR_MFE);
399 return result;
400 }
401 g_MFE_Dev.cdev.owner = THIS_MODULE;
402 g_MFE_Dev.cdev.kobj.name = MDRV_NAME_MFE;
403 g_MFE_Dev.cdev.ops = &MFE_Fops;
404 cdev_init(&(g_MFE_Dev.cdev), &MFE_Fops);
405 result = cdev_add (&(g_MFE_Dev.cdev), devno, 1);
406 /* Fail gracefully if need be */
407 if (result) {
408 ms_dprintk(DRV_L4, KERN_NOTICE "Error add MFE device");
409 }
410 spin_lock_init(&_spinlock);
411 init_waitqueue_head(&_MFE_wait_queue);
412 return 0;
413 }
414
MDrv_MFE_ModuleExit(void)415 static void __exit MDrv_MFE_ModuleExit(void)
416 {
417 cdev_del(&g_MFE_Dev.cdev);
418 unregister_chrdev_region(MKDEV(MDRV_MAJOR_MFE, MDRV_MINOR_MFE), 1);
419 }
420
421 module_init(MDrv_MFE_ModuleInit);
422 module_exit(MDrv_MFE_ModuleExit);
423
424 //ken LGE
425 MODULE_AUTHOR("MSTAR");
426 MODULE_DESCRIPTION("MFE driver");
427 MODULE_LICENSE("MSTAR");
428
429 #endif //#if defined(_MFE_T8_)&&defined(_KERNEL_MODE_)
430
431
432
433 //////////////////////////////////////////////////////////////////////////
434 // ioctl API's
435 //////////////////////////////////////////////////////////////////////////
436
MDrv_MFE_ENC_Continue(MFE_CONFIG * pConfig)437 static void MDrv_MFE_ENC_Continue(MFE_CONFIG *pConfig)
438 {
439 MFE_ASSERT(outbitsbuf[pConfig->nOBufIndex].used_size==0);
440 ms_dprintk(DRV_L3, "Continue with buf[%d]\n",(unsigned int) pConfig->nOBufIndex);
441 MHal_MFE_set_outbitsbuf(&outbitsbuf[pConfig->nOBufIndex]);
442 encode_state = WAIT_FRAME_DONE;
443 }
444
445
MDrv_MFE_clear_bitsbuf(MFE_CONFIG * pConfig,MFE_U32 clear_num)446 static void MDrv_MFE_clear_bitsbuf(MFE_CONFIG *pConfig, MFE_U32 clear_num)
447 {
448
449 ms_dprintk(DRV_L3, "clear rbits_index: %d state=%d\n", rbits_index, encode_state);
450 ms_dprintk(DRV_L1,"clear_num = %d\n",(unsigned int)clear_num );
451 hw_status = GETBITS_NOT_READY;
452
453 spin_lock(&_spinlock);
454 MFE_ASSERT(clear_num==1);
455 ms_dprintk(DRV_L3, "clear rbits_index: %d state=%d\n", rbits_index, encode_state);
456
457 outbitsbuf[rbits_index].used_size = 0;
458 rbits_index = MFE_MUX((rbits_index+1)==pConfig->ctxBufInfo.m_nOutBuffer, 0, rbits_index+1);
459
460 spin_unlock(&_spinlock);
461 if (encode_state==WAIT_AVAIL_BITSBUF)
462 MDrv_MFE_ENC_Continue(pConfig);
463
464 }
465
MDrv_MFE_GetDispOrder(MFE_CONFIG * pConfig,GOPINFO * pGopInfo,MFE_U32 * pDispOrder)466 static int MDrv_MFE_GetDispOrder(MFE_CONFIG *pConfig, GOPINFO *pGopInfo, MFE_U32 *pDispOrder)
467 {
468
469
470 if (!pDispOrder) {
471 ms_dprintk(DRV_L4, "[Error] MDrv_MFE_GetDispOrder: pDispOrder is NULL pointer.\n");
472 return 0;
473 }
474 mfeSetVopType(pConfig, pGopInfo);
475 *pDispOrder = pGopInfo->nDispOrder;
476
477 ms_dprintk(DRV_L4, "MDrv_MFE_GetDispOrder: Enc=%d Disp=%d\n", (unsigned int)pGopInfo->nCodingOrder, (unsigned int)*pDispOrder);
478 return 1;
479 }
480
481
482 // Consumer of copybits2file()
MDrv_MFE_getbits(BITSFRAME_INFO * bits_info)483 static int MDrv_MFE_getbits(BITSFRAME_INFO *bits_info)
484 {
485 int i=0;
486 int index;
487 int num_of_buffers = gpMfeConfig->ctxBufInfo.m_nOutBuffer;
488 ms_dprintk(DRV_L3, "MDrv_MFE_getbits...\n");
489 #if defined(_MFE_T8_)&&defined(_KERNEL_MODE_)
490 // Kernel mode will sleep in MDrv_MFE_poll
491 #else
492 // MDrv_MFE_Sem_Wait(MSOS_WAIT_FOREVER);
493 if(MDrv_MFE_Sem_Wait(300000)==FALSE) {
494 ms_dprintk(DRV_L3, "MDrv_MFE_Sem_Wait...fail!!\n");
495 return 1;
496 }
497 MDrv_MFE_CheckEncodeDone(gpMfeConfig);
498 #endif
499
500 spin_lock(&_spinlock);
501 index = rbits_index;
502 // Now we only copy one buffer
503 if (_MFE_U32MFEEvent!=0) {
504 bits_info[i].miuAddress = bitsframe[index].miuAddress;
505 bits_info[i].miuPointer = bitsframe[index].miuPointer;
506 bits_info[i].size = bitsframe[index].size;
507 bits_info[i].status = bitsframe[index].status;
508 bits_info[i].voptype = bitsframe[index].voptype;
509 bits_info[i].is_more_bits = 1;
510 bits_info[i].IVOP_address= bitsframe[index].IVOP_address;
511 _MFE_U32MFEEvent ^= (1<<index);
512 index = MFE_MUX((index+1)==num_of_buffers, 0, index+1);
513 i++;
514 if (i>num_of_buffers) {
515 ms_dprintk(DRV_L1, "MDrv_MFE_getbits error!! use too many bits buffer\n");
516 }
517 }
518
519 bits_info[i-1].is_more_bits = 0;
520 spin_unlock(&_spinlock);
521
522 ms_dprintk(DRV_L3, "Leave MDrv_MFE_getbits.\n");
523 return 0;
524 }
525
526
527 #if defined(_UDMA_)||defined(_FPGA_)
DMAGetFile(char * tmpname,DWORD start,DWORD size,int type,char * Buffer)528 MFE_U32 DMAGetFile(char *tmpname, DWORD start, DWORD size, int type, char *Buffer)
529 {
530 #if defined(_UDMA_) || defined(_HIF_)
531 FPGA_MIUReadFile(tmpname, start, size, type, Buffer);
532 #elif defined(_TRACE32_CMM_)
533 fprintf(fp_script, "B::DATA.SAVE.BINARY %s 0x%08X--0x%08X\n", tmpname,
534 addr_phy2log(start), addr_phy2log(start+size));
535 #endif
536 return TRUE;
537 }
538
DMAPutMem(char * from_ptr,int size,MFE_U32 to_addr,int type)539 int DMAPutMem(char *from_ptr, int size, MFE_U32 to_addr, int type)
540 {
541 #if defined(_UDMA_) || defined(_HIF_)
542 FPGA_MIUWrite(from_ptr, size, to_addr, type);
543 #elif defined(_AEON_PLATFORM_)
544 memcpy((char *)addr_phy2log(to_addr), from_ptr, size);
545 #elif defined(_TRACE32_CMM_)
546 //????
547 #else
548 memcpy((char *)to_addr, from_ptr, size);
549 #endif
550 return 0;
551 }
552 #endif //#if defined(_UDMA_)||defined(_FPGA_)
553
554 #ifdef CRC_CHECK
printf_CRC(int order,unsigned int size,unsigned char * crc)555 static void printf_CRC(int order,unsigned int size, unsigned char* crc)
556 {
557
558 ms_dprintk(DRV_L4, "Frame#%d size = 0x%x CRC = %02x%02x %02x%02x %02x%02x %02x%02x\n",
559 order,size,crc[1],crc[0],crc[3],crc[2],crc[5],crc[4],crc[7],crc[6]);
560
561 }
PrintCRC(MFE_CONFIG * pConfig,MFE_U8 bGetHwCRC,MFE_U8 * addr,int size,MFE_U8 bFrameDone)562 static void PrintCRC(MFE_CONFIG *pConfig, MFE_U8 bGetHwCRC, MFE_U8* addr, int size, MFE_U8 bFrameDone)
563 {
564 MFE_U8 crc[8];
565 int frame_count = (int) pConfig->nCodingOrder;
566 unsigned int BitstreamLen = (unsigned int) MHal_MFE_GetBitstreamEncodedLen();
567 int i;
568 #ifdef _CRC_PATTERN_GEN_
569 unsigned char crc_patt[8];
570 #endif
571
572 // ms_dprintk(DRV_L4, "start PrintCRC, bGetHwCRC = %d\n",bGetHwCRC);
573 if (bGetHwCRC) {
574 MHal_MFE_GetCRC(crc);
575 ms_dprintk(DRV_L2, "[CRC HWRE] ");
576 printf_CRC(frame_count,BitstreamLen,crc);
577
578 CRC_ACC_HW_Generator(&gCRC_AllFrames, crc);
579 ms_dprintk(DRV_L2, "[ACC CRC] ");
580 printf_CRC(frame_count,BitstreamLen,gCRC_AllFrames.CRCValue);
581
582 #ifdef _CRC_PATTERN_GEN_
583 for(i=0;i<8;i++)
584 crc_patt[i] = pConfig->CModel_pattern[8*pConfig->nCodingOrder+i];
585
586 for(i=0;i<8;i++){
587 if(crc[i] !=crc_patt[i]){
588 ms_dprintk(DRV_L2, "_CRC_PATTERN_GEN_ check error!\n");
589 ms_dprintk(DRV_L2, "[CRC PAT] ");
590 printf_CRC(frame_count,BitstreamLen,crc_patt);
591 }
592 }
593 ms_dprintk(DRV_L2, "_CRC_PATTERN_GEN_ HW check OK!\n");
594 #endif
595 }
596 else {
597 unsigned char* crc_dram;
598 gCRC_DramBitstream.pBuf = addr;
599 gCRC_DramBitstream.nBufSize = size;
600 gCRC_DramBitstream.bIsLast = bFrameDone ? 1 : 0;
601 CRC_Generator(&gCRC_DramBitstream);
602 ms_dprintk(DRV_L2, "[CRC DRAM] ");
603 printf_CRC((int)pConfig->nCodingOrder, (unsigned int)size,gCRC_DramBitstream.CRCValue);
604
605 //compare with HW CRC
606 MHal_MFE_GetCRC(crc);
607 crc_dram = (unsigned char*)(gCRC_DramBitstream.CRCValue);
608 for(i=0;i<8;i++){
609 if(crc[i] !=crc_dram[i] ){
610 ms_dprintk(DRV_L2, "_CRC_PATTERN_GEN_ check error!\n");
611 // ms_dprintk(DRV_L2, "[CRC PAT] ");
612 // printf_CRC(frame_count,BitstreamLen,crc_patt);
613 }
614 }
615 // ms_dprintk(DRV_L2, "_CRC_PATTERN_GEN_ HW check OK!\n");
616
617 // get_CRC_ACC_CRC(&gCRC_AllFrames, &gCRC_DramBitstream);
618 // ms_dprintk(DRV_L2, "[ACC CRC] ");
619 // printf_CRC((int)pConfig->nCodingOrder, (unsigned int)size,gCRC_AllFrames.CRCValue);
620
621 }
622 // ms_dprintk(DRV_L4, "end PrintCRC, bGetHwCRC = %d\n",bGetHwCRC);
623 }
624 #endif
625
mdrvMFE_EncodeVOP_End(MFE_CONFIG * pConfig)626 static int mdrvMFE_EncodeVOP_End(MFE_CONFIG *pConfig)
627 {
628 switch (pConfig->nCodecType) {
629 case REG_ENC_MODE_MPG4:
630 case REG_ENC_MODE_H263:
631 mfeM4VE_UpdateFrame(pConfig);
632 break;
633 case REG_ENC_MODE_H264:
634 mfeH264_UpdateFrame(pConfig);
635 break;
636 case REG_ENC_MODE_JPEG:
637 MFE_ASSERT(0);
638 break;
639 }
640
641 #ifdef CRC_CHECK
642 PrintCRC(pConfig, 1, NULL, 0, 1);
643 #endif
644
645 ms_dprintk(DRV_L4, "encode one frame end\n");
646 return 0;
647 }
648
get_hw_encode_done_info(MFE_U32 start)649 static MFE_U32 get_hw_encode_done_info(MFE_U32 start)
650 {
651 MFE_U16 u16Reg1, u16Reg2;
652 MFE_U32 hwlen;
653 MFE_U32 wptr;
654 MFE_U32 size;
655 // Final frame bit count -> byte count
656 ReadRegMFE(0x42, &u16Reg1);
657 ReadRegMFE(0x43, &u16Reg2);
658 //ms_dprintk(DRV_L4, "u16Reg2 = 0x%x, u16Reg1 = 0x%x\n", u16Reg2, u16Reg1);
659 hwlen = (((u16Reg2)<<16) | u16Reg1)>>3;
660 ms_dprintk(DRV_L1, "copybits2file():HW counter total bytes = 0x%x\n",(unsigned int) hwlen);
661
662 // The last outbuf filled-size
663 ReadRegMFE(0x44, &u16Reg1);
664 ReadRegMFE(0x45, &u16Reg2);
665 wptr = ((u16Reg2<<16) | u16Reg1)<<3;
666 ms_dprintk(DRV_L4, "copybits2file():bspobuf write pointer (8 byte unit) wptr = 0x%x\n",(unsigned int) wptr);
667 size = wptr - start + ((hwlen&7)?(hwlen&7):8);
668 if (size<=0)
669 ms_dprintk(DRV_L4, "[Error] copybits2file(): size %d<0. start=0x%x wptr=0x%x hwlen=0x%x\n",
670 (unsigned int)size,(unsigned int) start,(unsigned int) wptr,(unsigned int) hwlen);
671
672 return size;
673 }
674
675 // Supplier of MDrv_MFE_getbits()
copybits2file(MFE_CONFIG * pConfig,MFE_WORD val_1e)676 static MFE_BOOL copybits2file(MFE_CONFIG *pConfig, MFE_WORD val_1e)
677 {
678 MFE_S32 wbits_index;
679 MFE_U8 voptype = pConfig->vopPredType;
680 MFE_U32 Y_start = pConfig->ctxBufInfo.m_nRecYAddr.miuAddress;
681 MFE_U32 start = 0;
682 MFE_S32 size = 0;
683 MFE_S32 bFrameDone = CHECK_IRQ_STATUS(val_1e, IRQ_FRAME_DONE);
684 MFE_S32 bBufFull = CHECK_IRQ_STATUS(val_1e, IRQ_BSPOBUF_FULL); // Output buffer full.
685 MFE_S32 bImgFull = CHECK_IRQ_STATUS(val_1e, IRQ_IMG_BUF_FULL); // Input buffer full. Only when JPEG row-mode.
686
687 start = outbitsbuf[pConfig->nOBufIndex].start_addr;
688
689 if (bFrameDone) {
690 ms_dprintk(DRV_L1, "copybits2file(): Frame done.\n");
691 DumpAllReg(); //must define DRV_L5
692 MFE_ASSERT(!bBufFull); // This is guaranteed by HW design.
693
694 size = get_hw_encode_done_info(start);
695 }
696 else if (bBufFull) {
697 ms_dprintk(DRV_L1, "copybits2file(): Buffer full.\n");
698 size = pConfig->ctxBufInfo.m_OutBufferSize;
699 }
700 else if (bImgFull) {
701 start = 0;
702 size = 0;
703 }
704 else //if((bFrameDone | bBufFull | bImgFull) == 0)
705 {
706 ms_dprintk(DRV_L4, "copybits2file(): Error IRQ=0x%x not handled!\n", val_1e);
707 return FALSE;
708 }
709
710 //clear all set irq, need to set before change bitstream buffer
711 wbits_index = pConfig->nOBufIndex;
712 pConfig->nOBufIndex = (pConfig->nOBufIndex+1)%pConfig->ctxBufInfo.m_nOutBuffer; //next outbuf
713 //ms_dprintk(DRV_L4, "OBufIndex=%d, state=%d\n", pConfig->nOBufIndex, encode_state);
714
715
716 if (outbitsbuf[pConfig->nOBufIndex].used_size>0 && (!bFrameDone)) {
717 ms_dprintk(DRV_L1, "MFE encoding bitsbuf full! %d %d\n",(unsigned int) pConfig->nOBufIndex, (int)size);
718 encode_state = WAIT_AVAIL_BITSBUF;
719 } else {
720 if (!bFrameDone) {
721 MHal_MFE_set_outbitsbuf(&outbitsbuf[pConfig->nOBufIndex]);
722 encode_state = WAIT_FRAME_DONE;
723 }
724 }
725
726 MHal_MFE_ClearIRQ(val_1e); // Conrad: Should this be here or above??
727
728 // Output info filling
729 bitsframe[wbits_index].miuAddress = start;
730 bitsframe[wbits_index].miuPointer = (MFE_U32)addr_phy2log(start + MFE_U32MFEMIUOffset);
731 bitsframe[wbits_index].size = size;
732
733 if (bFrameDone)
734 bitsframe[wbits_index].status = BITS_INFO_FRAMEDONE;
735 else if(bBufFull)
736 bitsframe[wbits_index].status = BITS_INFO_BUFFULL;
737 else if (bImgFull)
738 bitsframe[wbits_index].status = BITS_INFO_IMG_BUFFULL;
739 /*
740 if((bFrameDone | bBufFull | bImgFull) == 0) {
741 assert(0);
742 // bitsframe[wbits_index].status = BITS_INFO_UNKNOW;
743 }
744 */
745 bitsframe[wbits_index].voptype = voptype;
746 // For I-VOP Thumbnail
747 if (voptype==I_VOP) {
748 bitsframe[wbits_index].IVOP_address = Y_start;
749 } else {
750 bitsframe[wbits_index].IVOP_address = 0;
751 }
752
753 #ifdef _WIN32
754 //we don't lock on mips, Aeon, ARM because these codes are in ISR in those platforms.
755 spin_lock(&_spinlock);
756 #endif
757 _MFE_U32MFEEvent |= 1<<wbits_index;
758 #ifdef _WIN32
759 spin_unlock(&_spinlock);
760 #endif
761
762
763 // NOTE: When acts as kernel mode, wait up for poll()
764 // When acts as user mode, release semaphore (paired with MDrv_MFE_getbits())
765 //printk("next: 0x%x prev: 0x%x\n", _MFE_wait_queue.task_list.next, _MFE_wait_queue.task_list.prev);
766 if (bFrameDone) {
767 mdrvMFE_EncodeVOP_End(pConfig);
768 #if defined(_MFE_T8_) && defined(_MIPS_PLATFORM_)
769 //MIU MODE, check type(0:BPS,1:MC.2:MV,3:GN)
770 MHal_MFE_Enable_MIU_Protection_Check(TEST_MIU_PROTECTION_MODE,0);
771 #endif
772 encode_state = WAIT_INPUT_FRAME;
773 }
774
775 #if defined(_MFE_T8_) && defined(_MIPS_PLATFORM_) && defined(_KERNEL_MODE_)
776 if (bFrameDone || bBufFull) {
777 //wake_up(&_MFE_wait_queue);
778 MDrv_MFE_Sem_Wake_Up();
779 }
780 #elif defined(_MFE_T8_) && defined(_MIPS_PLATFORM_)
781 if (bFrameDone || bBufFull)
782 return TRUE;
783 else {
784 ms_dprintk(DRV_L1, "[ERROR] CHECK_IRQ_STATUS not bFrameDone or bBufFull.\n");
785 return FALSE;
786 }
787 #endif
788 return TRUE;
789 }
790
MDrv_MFE_CheckEncodeDone(MFE_CONFIG * pConfig)791 static MFE_BOOL MDrv_MFE_CheckEncodeDone(MFE_CONFIG *pConfig)
792 {
793 MFE_U16 val_1e;
794 //MFE_U8 voptype = pConfig->vopPredType;
795 //int sgc_frame_done;
796
797 MHal_MFE_GetIRQ(&val_1e);
798 if (val_1e==0) {
799 ms_dprintk(DRV_L4, "[WARN] CheckEncodeDone() reg1e=0\n");
800 return FALSE;
801 }
802
803 //h1e: [7:0] status of interrupt on CPU side
804 // {2'b0, net_trigger, fs_fail_irq, txip_time_out, bspobuf_full_irq, img_buf_full_irq, marb_bspobuf_ful, frame_done_irq}
805 //sgc_frame_done = CHECK_IRQ_STATUS(val_1e, IRQ_FRAME_DONE);
806 copybits2file(pConfig, val_1e);
807
808 ms_dprintk(DRV_L4, "encode_state: %d\n", encode_state);
809 return TRUE;
810 }
811
812 #ifdef _ENABLE_ISR_
813
814 #if defined(_MFE_T8_) && defined(_MIPS_PLATFORM_)&& defined(_KERNEL_MODE_)
MDrv_MFE_ISR(int irq,void * dev_id)815 static irqreturn_t MDrv_MFE_ISR(int irq, void *dev_id )
816 {
817
818 ms_dprintk(DRV_L1, "\\\\\\\\\\\\\\\\\\\\\\\\\\\nGet in MDrv_MFE_ISR!\n\\\\\\\\\\\\\\\\\\\\\\\\\\\n");
819
820 #ifdef DRV_MFE_TIME_MEASURE
821 MFE_MsOS_PRINT_TIMER();
822 // ms_dprintk(DRV_L6, "[MFE_TIME_ISR] timetick_end = %ld, [%ld] \n",timetick_end,timetick_end-timetick_start);
823 #endif
824 MDrv_MFE_CheckEncodeDone(gpMfeConfig);
825 return IRQ_HANDLED;
826 // cyg_interrupt_unmask(vector); //Unmask the interrup that has been masked in _enc_isr()
827 }
828
MFE_ISR_Enable(MFE_U8 y)829 void MFE_ISR_Enable(MFE_U8 y)
830 {
831 int result;
832 ms_dprintk(DRV_L4, "Enable MFE ISR\n");
833 //enable_irq(E_IRQ_M4VE);
834 result = request_irq(E_IRQ_MFE, MDrv_MFE_ISR, SA_INTERRUPT, "MFE_IRQ", NULL);
835 if(result==1)
836 ms_dprintk(DRV_L1, "ERROR Enable MFE ISR: result = %d\n",result);
837 else if(result==0)
838 ms_dprintk(DRV_L1, "Success Enable MFE ISR: result = %d\n",result);
839 else
840 ms_dprintk(DRV_L1, "ERROR Enable MFE ISR: result = %d(undefine value)\n",result);
841 }
842
843 #elif defined(_MFE_T8_) && defined(_MIPS_PLATFORM_)
844
MFE_ISR_Enable(InterruptNum y)845 static MS_BOOL MFE_ISR_Enable(InterruptNum y)
846 {
847 MS_BOOL ret;
848
849 ms_dprintk(DRV_L4, "Enable MFE ISR\n");
850 ret = MsOS_EnableInterrupt (y);
851
852 return ret;
853 }
854
MFE_ISR_Disable(InterruptNum y)855 static MS_BOOL MFE_ISR_Disable(InterruptNum y)
856 {
857 ms_dprintk(DRV_L1, "Disable MFE ISR\n");
858 return MsOS_DisableInterrupt (y);
859 }
860
MDrv_MFE_ISR(InterruptNum eIntNum)861 static void MDrv_MFE_ISR(InterruptNum eIntNum)
862 {
863 // char temp[30];
864 // char real[30];
865
866 ms_dprintk(DRV_L4, "\n\n\nget in MDrv_MFE_ISR\n\n\n");
867 // ms_dprintk(TIME_L1, "[Time] get in MDrv_M4VE_ISR %d\n",(unsigned int) MsOS_GetSystemTime());
868
869 //MFE_ISR_Disable(eIntNum);
870 MDrv_MFE_Sem_Wake_Up();
871
872 //move to MDrv_MFE_getbits(). ISR should not be used so much cpu time.
873 //MDrv_MFE_CheckEncodeDone(gpMfeConfig);
874 //MFE_ISR_Enable (eIntNum);
875 hw_status = GETBITS_READY;
876 }
877
MFE_ISR_Attach(InterruptNum y,InterruptCb pIntCb)878 static MS_BOOL MFE_ISR_Attach(InterruptNum y,InterruptCb pIntCb)
879 {
880 ms_dprintk(DRV_L1, "Attach MFE ISR\n");
881 return MsOS_AttachInterrupt(y,pIntCb);
882
883 }
MFE_ISR_Detach(InterruptNum y)884 static MS_BOOL MFE_ISR_Detach(InterruptNum y)
885 {
886 ms_dprintk(DRV_L1, "Detach MFE ISR\n");
887 return MsOS_DetachInterrupt(y);
888 }
889
890 #elif defined(_WIN32)
891 // Simulate interrupts by one thread
MDrv_MFE_ISR(void * dev_id)892 static void* MDrv_MFE_ISR( void *dev_id )
893 {
894 #if !defined(_FPGA_)
895 MFE_U32 nOutBufEndAddr;
896 MFE_U32 nFrameBits = 0;
897 #endif
898 U16 val_1e = 0;
899
900 ms_dprintk(DRV_L4, "get in MDrv_MFE_ISR\n");
901 srand(1000);
902 while(1) {
903 Sleep(100);
904 if (encode_state==WAIT_FRAME_DONE) {
905 #if defined(_FPGA_)
906 MHal_MFE_GetIRQ(&val_1e);
907 if (val_1e)
908 MDrv_MFE_CheckEncodeDone(gpMfeConfig);
909 #else
910 if (rand()%4) { //buffer full
911 nOutBufEndAddr = ((outbitsbuf[gMfeConfig.nOBufIndex].start_addr+gpMfeConfig->ctxBufInfo.m_OutBufferSize)>>MIU_SHIFT)-1;
912 nFrameBits += gpMfeConfig->ctxBufInfo.m_OutBufferSize*8;
913 WriteRegMFE(0x1e, (1<<IRQ_BSPOBUF_FULL), "", 0, "");
914 WriteRegMFE(0x44, LOWORD(nOutBufEndAddr), "", 0, "");
915 WriteRegMFE(0x45, HIWORD(nOutBufEndAddr), "", 0, "");
916 }
917 else { //frame done
918 unsigned long temp;
919 temp = rand()%gpMfeConfig->ctxBufInfo.m_OutBufferSize;
920 nOutBufEndAddr = ((outbitsbuf[gMfeConfig.nOBufIndex].start_addr+gpMfeConfig->ctxBufInfo.m_OutBufferSize)>>MIU_SHIFT)-1;
921 nFrameBits += temp*8;
922 WriteRegMFE(0x1e, (U16)((1<<IRQ_FRAME_DONE)/*|((my_temp==(OBUF_SIZE-1))<<IRQ_BSPOBUF_FULL)*/), "", 0, "");
923 WriteRegMFE(0x44, LOWORD(nOutBufEndAddr), "", 0, "");
924 WriteRegMFE(0x45, HIWORD(nOutBufEndAddr), "", 0, "");
925 WriteRegMFE(0x42, LOWORD(nFrameBits), "", 0, "");
926 WriteRegMFE(0x43, HIWORD(nFrameBits), "", 0, "");
927 nFrameBits = 0;
928 }
929 MDrv_MFE_CheckEncodeDone(gpMfeConfig);
930 #endif
931 }
932 }
933
934 return 0;//IRQ_HANDLED;
935 // cyg_interrupt_unmask(vector); //Unmask the interrupt that has been masked in _enc_isr()
936 }
937
MFE_ISR_Enable(MFE_U8 y)938 void MFE_ISR_Enable(MFE_U8 y)
939 {
940 //int irq;
941 pthread_t thread_info;
942 pthread_attr_t thrattr;
943 struct sched_param thrsched;
944
945 pthread_attr_init(&thrattr);
946 pthread_attr_setdetachstate(&thrattr, PTHREAD_CREATE_JOINABLE);
947 pthread_attr_setinheritsched(&thrattr, PTHREAD_EXPLICIT_SCHED);
948 pthread_attr_setschedpolicy(&thrattr, SCHED_RR);
949 pthread_attr_getschedparam(&thrattr, &thrsched);
950 thrsched.sched_priority = 80;
951 pthread_attr_setschedparam(&thrattr, &thrsched);
952 pthread_attr_getschedparam(&thrattr, &thrsched);
953 if (0 != pthread_create(&thread_info, &thrattr, MDrv_MFE_ISR, NULL)) {
954 ms_dprintk(DRV_L4, "Mhal MFE ISR create thread error\n");
955 }
956 }
957
958 #endif // Platforms
959 #endif //_ENABLE_ISR
960
961
msAPI_MFE_EncodeVOP(MFE_CONFIG * pConfig,GOPINFO * pGopInfo)962 void msAPI_MFE_EncodeVOP(MFE_CONFIG *pConfig, GOPINFO* pGopInfo)
963 {
964 // MHal_MFE_SetCLKCTL();
965
966 ms_dprintk(DRV_L1, "msAPI_MFE_EncodeVOP : %d(I/P/B)\n", pConfig->vopPredType);
967
968 // Call underlying encoding routine
969 #if defined(_FPGA_)
970 {
971 MEMMAP_t *pAddr = &pConfig->ctxBufInfo.m_nCurYAddr;
972 ms_dprintk(DRV_L4, "[UMDA] Put CurY/C: LogAddr=0x%08x --> PhyAddr=0x%08x\n", pAddr->miuPointer, pAddr->miuAddress);
973 DMAPutMem(pAddr->miuPointer, pConfig->nBufWidth*pConfig->nBufHeight*3/2, pAddr->miuAddress, 0);
974 }
975 #endif
976
977 switch (pConfig->nCodecType) {
978 case REG_ENC_MODE_MPG4:
979 case REG_ENC_MODE_H263:
980 mfeM4VE_EncodeFrame(pConfig, pGopInfo);
981 break;
982 case REG_ENC_MODE_H264:
983 mfeH264_EncodeFrame(pConfig, pGopInfo);
984 break;
985 case REG_ENC_MODE_JPEG:
986 MFE_ASSERT(0);
987 break;
988 }
989 encode_state = WAIT_FRAME_DONE;
990
991 #ifdef DRV_MFE_TIME_MEASURE
992 MFE_MsOS_START_TIMER();
993 // timetick_start = jiffies; //MDrv_SYS_GetSyetemTime();
994 // ms_dprintk(DRV_L6, "[MFE_TIME_STR] timetick_str = %ld\n",timetick_start);
995 //ftime(&tp1);
996 #endif
997
998 ms_dprintk(DRV_L4, "In msAPI_MFE_EncodeVOP() After encode_state = WAIT_FRAME_DONE\n");
999 }
1000
1001 #if defined(_MAIN_TEST_)
mdrvLoadTestCasePre(MFE_CONFIG * pConfig)1002 void mdrvLoadTestCasePre(MFE_CONFIG *pConfig)
1003 {
1004
1005 if (pConfig->nCodecType==0) { // MPEG-4
1006 if (pConfig->test_case_num==0) {
1007 pConfig->bQuantType = 0;
1008 }
1009 else if (pConfig->test_case_num==1) {
1010 pConfig->bQuantType = 0;
1011 pConfig->nVPSizeInBits = 12000;
1012 }
1013 else if (pConfig->test_case_num==2) {
1014 pConfig->bQuantType = 1;
1015 }
1016 else if (pConfig->test_case_num==3) {
1017 pConfig->bQuantType = 1;
1018 }
1019 else if (pConfig->test_case_num==4) {
1020 pConfig->bQuantType = 1;
1021 }
1022 else if (pConfig->test_case_num==5) {
1023 pConfig->bQuantType = 0;
1024 }
1025 else if (pConfig->test_case_num==99) {
1026 pConfig->bQuantType = 1;
1027 }
1028 else
1029 MFE_ASSERT(0);
1030 }
1031 }
mdrvLoadTestCasePost(MFE_CONFIG * pConfig)1032 void mdrvLoadTestCasePost(MFE_CONFIG *pConfig)
1033 {
1034 if (pConfig->nCodecType==0) { // MPEG-4
1035 M4VEINFO* pInfo = &pConfig->ctxM4veInfo;
1036 if (pConfig->test_case_num==1) {
1037 pInfo->iSearchRangeForward = 16;
1038 if (pInfo->SEARCH_RANGE_Y<=16 && pInfo->iSearchRangeForward<=16)
1039 pInfo->iFCode = 1;
1040 else
1041 pInfo->iFCode = 2;
1042 }
1043 }
1044
1045 if (pConfig->nCodecType==2) { // H264
1046 H264INFO* pInfo = &pConfig->ctxH264Info;
1047 if (pConfig->test_case_num==1) {
1048 pInfo->InterSearch[0][BLOCK16x8] = 0;
1049 pInfo->InterSearch[0][BLOCK8x16] = 0;
1050 pInfo->InterSearch[0][BLOCK8x4] = 0;
1051 pInfo->InterSearch[0][BLOCK4x8] = 0;
1052 pInfo->InterSearch[0][BLOCK4x4] = 0;
1053 }
1054 else if (pConfig->test_case_num==2) {
1055 int nTotalMBs = (pConfig->nBufWidth>>4) * (pConfig->nBufHeight>>4);
1056 pInfo->nMaxP8x8Count = nTotalMBs * /*input->p8x8_percentage*/10 / 100;
1057 pInfo->nMaxP8x8Count = (pInfo->nMaxP8x8Count>>4)<<4;
1058 if (pInfo->nMaxP8x8Count<16) // HW minimal unit is 16
1059 pInfo->nMaxP8x8Count = 16;
1060 if (pInfo->nMaxP8x8Count>63*16) // HW reg 6 bits
1061 pInfo->nMaxP8x8Count = 63*16;
1062 }
1063 else if (pConfig->test_case_num==3) {
1064 pInfo->iSearchRangeForward = 16;
1065 }
1066 else if (pConfig->test_case_num==4) {
1067 pInfo->iSearchRangeForward = 16;
1068 pInfo->num_ref_frames = 1;
1069 pInfo->InterSearch[0][0] = 0; // PSKIP
1070 pInfo->InterSearch[0][BLOCK16x8] = 0;
1071 pInfo->InterSearch[0][BLOCK8x16] = 0;
1072 pInfo->InterSearch[0][BLOCK8x4] = 0;
1073 pInfo->InterSearch[0][BLOCK4x8] = 0;
1074 pInfo->InterSearch[0][BLOCK4x4] = 0;
1075 pInfo->ieap_last_mode = 2;
1076 }
1077 }
1078 }
1079 #endif
1080
mfe_open_ISR(void)1081 static MFE_BOOL mfe_open_ISR(void)
1082 {
1083
1084 #if defined(_MFE_T8_)&&defined(_MIPS_PLATFORM_)&&defined(_KERNEL_MODE_)
1085 ms_dprintk(DRV_L4, "attach ISR %d\n", attach_ISR);
1086 if (attach_ISR) {
1087 MFE_ISR_Enable(1);
1088 attach_ISR=0;
1089 }
1090 #elif defined(_MFE_T8_)&&defined(_MIPS_PLATFORM_)
1091 if (attach_ISR) {
1092 if(MFE_ISR_Attach((InterruptNum)E_INT_IRQ_MFE,MDrv_MFE_ISR)==FALSE)
1093 ms_dprintk(DRV_L1, "MFE_ISR_Attach Fail\n");
1094
1095 if(MFE_ISR_Enable((InterruptNum)E_INT_IRQ_MFE)==FALSE)
1096 ms_dprintk(DRV_L1, "MFE_ISR_Enable Fail\n");
1097 attach_ISR=0;
1098 }
1099 #else
1100 ms_dprintk(DRV_L4, "attach ISR %d\n", attach_ISR);
1101 if (attach_ISR) {
1102 MFE_ISR_Enable(1);
1103 attach_ISR=0;
1104 }
1105 #endif
1106
1107 return TRUE;
1108 }
mfe_close_ISR(void)1109 static MFE_BOOL mfe_close_ISR(void)
1110 {
1111
1112 MFE_BOOL CloseISRret= TRUE;
1113 #if defined(_MIPS_PLATFORM_) && defined(_MFE_T8_)&& defined(_KERNEL_MODE_)&&defined(_ENABLE_ISR_)
1114
1115 ms_dprintk(DRV_L4, "In mdrv_MFE_Finish, free irq.\n");
1116 free_irq(E_IRQ_MFE, NULL);
1117 attach_ISR=1;
1118
1119 #elif defined(_MIPS_PLATFORM_) && defined(_MFE_T8_)&&defined(_ENABLE_ISR_)
1120 if(MFE_ISR_Detach(E_INT_IRQ_MFE)==FALSE)
1121 CloseISRret = FALSE;
1122 if(MFE_ISR_Disable(E_INT_IRQ_MFE)==FALSE)
1123 CloseISRret = FALSE;
1124 #endif
1125
1126 return CloseISRret;
1127
1128 }
1129
MDrv_MFE_Init(MFE_CONFIG * pConfig)1130 static void MDrv_MFE_Init(MFE_CONFIG *pConfig)
1131 {
1132 int i;
1133
1134 ms_dprintk(DRV_L4, "In MDrv_MFE_Init..CodecType=%d\n",pConfig->nCodecType);
1135
1136 hw_status = GETBITS_NOT_READY;
1137
1138 #if defined(_MAIN_TEST_)
1139 mdrvLoadTestCasePre(pConfig);
1140 #endif
1141 switch (pConfig->nCodecType) {
1142 case REG_ENC_MODE_MPG4:
1143 case REG_ENC_MODE_H263:
1144 mfeM4VE_Init(pConfig);
1145 break;
1146 case REG_ENC_MODE_H264:
1147 mfeH264_Init(pConfig);
1148 break;
1149 case REG_ENC_MODE_JPEG:
1150 MFE_ASSERT(0);
1151 break;
1152 }
1153 #if defined(_MAIN_TEST_)
1154 mdrvLoadTestCasePost(pConfig);
1155 #endif
1156
1157 ms_dprintk(DRV_L4, "In MDrv_MFE_Init..Before PowerOFF\n");
1158 MHal_MFE_PowerOff(0,MFEClockLevel);
1159
1160 MMAPInit((MFE_U32)pConfig->dram_base, (MFE_U32)pConfig->dram_size, (MFE_U32*)&pConfig->dram_ptr);
1161
1162 #ifdef _FPGA_
1163 //reg_scan(reg_m4ve_mask, 0x80, WriteRegM4VE, ReadRegM4VE);
1164 while (FPGA_Connect() == 0) {
1165 ms_dprintk(DRV_L4, "FPGA Connection Fail!! Retry.....\n");
1166 }
1167 ms_dprintk(DRV_L4, "FPGA Connection Success!! \n");
1168 #endif
1169
1170 encode_state = WAIT_INPUT_FRAME; //init encode_state
1171 MHal_MFE_ResetReg();
1172 //DumpAllReg();
1173
1174 switch (pConfig->nCodecType) {
1175 case REG_ENC_MODE_MPG4:
1176 case REG_ENC_MODE_H263:
1177 m4veAllocDRAM(pConfig);
1178 break;
1179 case REG_ENC_MODE_H264:
1180 h264AllocDRAM(pConfig);
1181 break;
1182 case REG_ENC_MODE_JPEG:
1183 MFE_ASSERT(0);
1184 break;
1185 }
1186
1187 for (i=0; i<pConfig->ctxBufInfo.m_nOutBuffer; i++) {
1188 outbitsbuf[i].start_addr = pConfig->ctxBufInfo.m_nOutBufAddr[i].miuAddress;
1189 outbitsbuf[i].end_addr = pConfig->ctxBufInfo.m_nOutBufAddr[i].miuAddress+pConfig->ctxBufInfo.m_OutBufferSize;
1190 outbitsbuf[i].used_size = 0;
1191 ms_dprintk(DRV_L4, "Obuf index %d: PhyAddr=%08x\n", i,(unsigned int) outbitsbuf[i].start_addr);
1192 }
1193 pConfig->nOBufIndex = 0;
1194
1195 #ifdef _ENABLE_ISR_
1196 attach_ISR = 1;
1197 mfe_open_ISR();
1198 #endif
1199
1200
1201 MHal_MFE_ClearIRQ(0x3f);
1202
1203 #ifdef CRC_CHECK
1204 CRC_Init(&gCRC_AllFrames);
1205 #endif
1206
1207 //Sleep(400);
1208 #ifdef _TRACE32_CMM_
1209 M4VE_SCRIPT(fprintf(fp_script, "B::wait.1000ms\n"));
1210 #endif
1211
1212 }
1213
1214
MDrv_MFE_ENC_OneFrame(MFE_U32 YUV_addr)1215 static int MDrv_MFE_ENC_OneFrame(MFE_U32 YUV_addr)
1216 {
1217 int i;
1218 MEMMAP_t cur_frame, cur_frame_C;
1219 cur_frame_C.size=0;
1220 cur_frame.size=0;
1221 encode_state = WRITE_MFE_REG;
1222
1223 #ifdef CRC_CHECK
1224 #if defined(_MFE_T8_)&&defined(CHECK_OUTPUT_FROM_DRAM)
1225 CRC_Init(&gCRC_AllFrames);
1226 #endif
1227 CRC_Init(&gCRC_DramBitstream);
1228 #endif
1229
1230 for (i=0; i<gpMfeConfig->ctxBufInfo.m_nOutBuffer; i++) {
1231 MFE_ASSERT(outbitsbuf[i].used_size==0);
1232 outbitsbuf[i].used_size = 0;
1233 }
1234
1235 ms_dprintk(ADP_L1, "start to encode frame #%d(Enc) #%d(Disp)\n", (unsigned int)gpGopInfo->nCodingOrder, (unsigned int)gpGopInfo->nDispOrder);
1236
1237 cur_frame.miuAddress = YUV_addr;
1238 cur_frame.miuPointer = (MFE_U8*)addr_phy2log(YUV_addr + MFE_U32MFEMIUOffset);
1239
1240 cur_frame_C.miuAddress = cur_frame.miuAddress + gpMfeConfig->nBufWidth*gpMfeConfig->nBufHeight;
1241 cur_frame_C.miuPointer = (MFE_U8*)addr_phy2log(cur_frame_C.miuAddress + MFE_U32MFEMIUOffset);
1242
1243 gpMfeConfig->ctxBufInfo.m_nCurYAddr = cur_frame;
1244 gpMfeConfig->ctxBufInfo.m_nCurCAddr = cur_frame_C;
1245
1246 ms_dprintk(DRV_L4, "cur_frame: (miuAddress)0x%x (miuPointer)0x%x\n", (unsigned int)cur_frame.miuAddress, (unsigned int)cur_frame.miuPointer);
1247
1248 msAPI_MFE_EncodeVOP(gpMfeConfig, gpGopInfo);
1249
1250 gpGopInfo->nCodingOrder++;
1251 return 0;
1252 }
1253
1254
MDrv_MFE_Finish(void)1255 static int MDrv_MFE_Finish(void)
1256 {
1257
1258 #if !(defined(_MFE_T8_)&&defined(_KERNEL_MODE_))
1259 MDrv_MFE_Sem_Destroy();
1260 pthread_mutex_destroy(&_spinlock);
1261 #endif
1262
1263 mfe_close_ISR();
1264
1265 #ifdef WIN32
1266 sd_close(sd_sw_cfg1);
1267 sd_close(sd_sw_cfg3);
1268 #endif
1269 MHal_MFE_PowerOff(1,MFEClockLevel);
1270
1271 return 0;
1272 }
1273
MDrv_MFE_SetMIUOffset(MFE_U32 MFE_U32MIUOffset)1274 static void MDrv_MFE_SetMIUOffset( MFE_U32 MFE_U32MIUOffset )
1275 {
1276 ms_dprintk(DRV_L4, "MFE_U32MFEMIUOffset= 0x%x\n",(unsigned int)(MFE_U32MIUOffset));
1277 MFE_U32MFEMIUOffset = MFE_U32MIUOffset;
1278 }
1279
1280 // Output: Fill 16bit byte-length into pOutBuf[0] (LSB) and pOutBuf[1] (MSB)
1281 // Then following pOutBuf+2 is the byte stream of video headers.
MDrv_MFE_GetConfigBytes(MFE_CONFIG * pConfig,MFE_U8 * pOutBuf)1282 static void MDrv_MFE_GetConfigBytes(MFE_CONFIG *pConfig, MFE_U8* pOutBuf)
1283 {
1284 OutStream* pStream = NULL;
1285 MFE_U8* pBuf = NULL;
1286 int nSize = 0;
1287
1288 if (pOutBuf==NULL || pConfig==NULL)
1289 return;
1290
1291 pStream = &pConfig->m_OutStream;
1292 pBuf = pOutBuf;
1293
1294 switch (pConfig->nCodecType) {
1295 case REG_ENC_MODE_MPG4:
1296 nSize = codeM4vConfigHeaders(pConfig);
1297 break;
1298 case REG_ENC_MODE_H264:
1299 nSize = codeH264ConfigHeaders(pConfig);
1300 break;
1301 case REG_ENC_MODE_H263:
1302 case REG_ENC_MODE_JPEG:
1303 pBuf[0] = 0;
1304 pBuf[1] = 0;
1305 return;
1306 }
1307
1308 pBuf[0] = nSize&0xFF;
1309 pBuf[1] = (nSize>>8)&0xFF;
1310 pBuf += 2;
1311 MFE_ASSERT(pStream->m_nByteCount < 65535);
1312 memcpy(pBuf, pStream->m_pbFrameBuffer, pStream->m_nByteCount);
1313
1314 }
1315
1316
MDrv_MFE_Check_Status(MFE_U32 * in_status)1317 static void MDrv_MFE_Check_Status(MFE_U32* in_status)
1318 {
1319 *in_status = hw_status;
1320 }
1321
1322 #if defined(_MFE_T8_)&&defined(_KERNEL_MODE_)
MDrv_MFE_Ioctl(struct inode * inode,struct file * filp,unsigned int cmd,unsigned long arg)1323 int MDrv_MFE_Ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg)
1324 #else
1325 int MDrv_MFE_Ioctl(MFE_S32 MFE_fd, unsigned int cmd, unsigned long arg)
1326 #endif
1327 {
1328 PVR_Info *pappPVR_Info;
1329 BITSFRAME_INFO *bits_info;
1330
1331 #if defined(_MFE_T8_)&&defined(_KERNEL_MODE_)
1332 PROBE_IO_ENTRY(MDRV_MAJOR_MFE, _IOC_NR(cmd));
1333 #endif
1334
1335 switch(cmd)
1336 {
1337 case MFE_IOC_INIT:
1338 {
1339 ms_dprintk(DRV_L1, "[IOCTL] MFE_IOC_INIT\n");
1340
1341
1342 #if !(defined(_MFE_T8_)&&defined(_KERNEL_MODE_))
1343 MDrv_MFE_Sem_Init();
1344 pthread_mutex_init(&_spinlock, NULL);
1345 #endif
1346 #ifdef WIN32
1347 init_handle();
1348 sd_open(sd_sw_cfg1, "sw_cfg1_drv.txt");
1349 sd_open(sd_sw_cfg3, "sw_cfg3_drv.txt");
1350 #endif
1351 pappPVR_Info = (PVR_Info *)arg;
1352 rbits_index = 0;
1353 gpGopInfo->nCodingOrder = 0;
1354 _MFE_U32MFEEvent = 0;
1355
1356 memset(&gMfeConfig, 0, sizeof(MFE_CONFIG));
1357
1358 ms_dprintk(DRV_L4, "in MDrv_MFE.c W=%d H=%d\n", pappPVR_Info->width, pappPVR_Info->height);
1359 gMfeConfig.nCodecType = pappPVR_Info->nCodecType;
1360 gMfeConfig.nDispWidth = pappPVR_Info->nDispWidth;
1361 gMfeConfig.nDispHeight = pappPVR_Info->nDispHeight;
1362 gMfeConfig.nBufWidth = pappPVR_Info->nBufWidth;
1363 gMfeConfig.nBufHeight = pappPVR_Info->nBufHeight;
1364 gMfeConfig.dram_base = (MFE_U8*)pappPVR_Info->BitsBuffStart;
1365 gMfeConfig.dram_size = pappPVR_Info->BitsBuffSize;
1366 gMfeConfig.bInterlace = pappPVR_Info->bInterlace;
1367 gMfeConfig.nPbetweenI = pappPVR_Info->nPbetweenI;
1368 gMfeConfig.nBbetweenP = pappPVR_Info->nBbetweenP;
1369 gMfeConfig.FrameRatex100 = pappPVR_Info->FrameRatex100;
1370 gMfeConfig.nBitrate = pappPVR_Info->nBitrate;
1371 gMfeConfig.test_case_format = pappPVR_Info->test_case_format;
1372 gMfeConfig.test_case_num = pappPVR_Info->test_case_num;
1373 gMfeConfig.nP_is_infinite = pappPVR_Info->nP_is_infinite;
1374 gMfeConfig.ctxBufInfo.m_nOutBuffer = pappPVR_Info->nOutBuffer;
1375 gMfeConfig.ctxBufInfo.m_OutBufferSize = pappPVR_Info->OutBufferSize;
1376 memcpy(gMfeConfig.CModel_pattern, pappPVR_Info->CModel_pattern,20*8);
1377
1378 MDrv_MFE_Init(gpMfeConfig);
1379
1380 }
1381 break;
1382 case MFE_IOC_ENC_ONEFRAME:
1383 {
1384 if(MFE_ISR_Enable((InterruptNum)E_INT_IRQ_MFE)==FALSE)
1385 ms_dprintk(DRV_L1, "MFE_ISR_Enable Fail\n");
1386
1387 MDrv_MFE_ENC_OneFrame(arg);
1388 }
1389 break;
1390 case MFE_IOC_GET_DISPORDER:
1391 {
1392 ms_dprintk(DRV_L1, "[IOCTL] MFE_IOC_GET_DISPORDER\n");
1393 MDrv_MFE_GetDispOrder(gpMfeConfig, gpGopInfo, (MFE_U32*)arg);
1394 }
1395 break;
1396 case MFE_IOC_GETBITS:
1397 {
1398 ms_dprintk(DRV_L1, "[IOCTL] MFE_IOC_GETBITS\n");
1399 bits_info = (BITSFRAME_INFO *)arg;
1400 return MDrv_MFE_getbits(bits_info);
1401 }
1402 break;
1403 case MFE_IOC_SETBITRATE:
1404 {
1405 ms_dprintk(DRV_L1, "[IOCTL] MFE_IOC_SETBITRATE\n");
1406 pappPVR_Info = (PVR_Info *)arg;
1407 gMfeConfig.nBitrate = pappPVR_Info->nBitrate;
1408 ms_dprintk(DRV_L2, "[IOCTL] MFE_IOC_SETBITRATE =%d\n",gMfeConfig.nBitrate);
1409 }
1410 break;
1411 case MFE_IOC_RESET_BITRATE:
1412 {
1413 ms_dprintk(DRV_L1, "[IOCTL] MFE_IOC_RESET_BITRATE\n");
1414 pappPVR_Info = (PVR_Info *)arg;
1415 gMfeConfig.nBitrate = pappPVR_Info->nBitrate;
1416 MfeDrvRateControlInit(gpMfeConfig);
1417 ms_dprintk(DRV_L2, "[IOCTL] MFE_IOC_RESET_BITRATE =%d\n",gMfeConfig.nBitrate);
1418 }
1419 break;
1420 case MFE_IOC_RESET_FRAMERATE:
1421 {
1422 ms_dprintk(DRV_L1, "[IOCTL] MFE_IOC_RESET_FRAMERATE\n");
1423 pappPVR_Info = (PVR_Info *)arg;
1424 gMfeConfig.FrameRatex100 = pappPVR_Info->FrameRatex100;
1425 MfeDrvRateControlInit(gpMfeConfig);
1426 ms_dprintk(DRV_L2, "[IOCTL] MFE_IOC_RESET_FRAMERATE =%d\n",gMfeConfig.FrameRatex100);
1427 }
1428 break;
1429 case MFE_IOC_RESET_BITRATE_AND_FRAMERATE:
1430 {
1431 ms_dprintk(DRV_L1, "[IOCTL] MFE_IOC_RESET_BITRATE_AND_FRAMERATE\n");
1432 pappPVR_Info = (PVR_Info *)arg;
1433 gMfeConfig.FrameRatex100 = pappPVR_Info->FrameRatex100;
1434 gMfeConfig.nBitrate = pappPVR_Info->nBitrate;
1435 MfeDrvRateControlInit(gpMfeConfig);
1436 ms_dprintk(DRV_L2, "[IOCTL] MFE_IOC_RESET_BITRATE =%d,FRAMERATE=%d\n",
1437 gMfeConfig.nBitrate,gMfeConfig.FrameRatex100);
1438 }
1439 break;
1440 case MFE_IOC_CLEAR_BITSBUF:
1441 {
1442 ms_dprintk(DRV_L1, "[IOCTL] MFE_IOC_CLEAR_BITSBUF\n");
1443 MDrv_MFE_clear_bitsbuf(gpMfeConfig, arg);
1444 }
1445 break;
1446 case MFE_IOC_FINISH:
1447 {
1448 ms_dprintk(DRV_L1, "[IOCTL] MFE_IOC_FINISH\n");
1449 MDrv_MFE_Finish();
1450 }
1451 break;
1452 case MFE_IOC_SET_FORCEDI: // no implement
1453 {
1454 ms_dprintk(DRV_L1, "ioctl: MDRV: M4VE_IOC_SET_FORCEDI\n");
1455 g_bForceIframe = TRUE;
1456 }
1457 break;
1458 case MFE_IOC_SET_MIU_OFFSET:
1459 {
1460 ms_dprintk(DRV_L1, "[IOCTL] MFE_IOC_SET_MIU_OFFSET\n");
1461 MDrv_MFE_SetMIUOffset(arg);
1462 }
1463 break;
1464 case MFE_IOC_POWEROFF:
1465 {
1466 POWERON_t *tmp_Info;
1467 tmp_Info = (POWERON_t *)arg;
1468 if((tmp_Info->clock_level >>2) == 0 )
1469 MFEClockLevel = (MFE_U32)tmp_Info->clock_level ;
1470 else{
1471 ms_dprintk(DRV_L1, "[IOCTL] MFE clock level must be 0,1,2 or 3..default is 2.\n");
1472 MFEClockLevel = 2;
1473 }
1474 ms_dprintk(DRV_L1, "[IOCTL] MFE_IOC_POWEROFF, clock level= %d\n",tmp_Info->clock_level);
1475 MHal_MFE_PowerOff((MFE_U32)tmp_Info->is_off,(MFE_U32)tmp_Info->clock_level);
1476 }
1477 break;
1478 case MFE_IOC_GET_VOL:
1479 {
1480 MFE_U8* pBuf = (MFE_U8*)arg;
1481 ms_dprintk(DRV_L1, "[IOCTL] MFE_IOC_GET_VOL\n");
1482 MDrv_MFE_GetConfigBytes(gpMfeConfig, pBuf);
1483 }
1484 break;
1485 case MFE_IOC_CHECK_STATUS:
1486 {
1487 MDrv_MFE_Check_Status((MFE_U32*)arg);
1488 }
1489 break;
1490 case MFE_IOC_SET_RIU_BASE:
1491 {
1492 #if defined(_MFE_T8_) && defined(_MIPS_PLATFORM_)&& !defined(_KERNEL_MODE_)
1493 ms_dprintk(DRV_L1, "[IOCTL] MFE_IOC_SET_RIU_BASE 0x%x\n",(unsigned int)arg);
1494 MDrv_MFE_SetOSRegBase(arg);
1495 #else
1496 ms_dprintk(DRV_L1, "[IOCTL] MFE_IOC_SET_RIU_BASE only use for utopia.\n");
1497 return 1;
1498 #endif
1499 }
1500 break;
1501 default:
1502 ms_dprintk(DRV_L1, "[IOCTL] MFE receive non-defined Ioctl\n");
1503 break;
1504 }
1505
1506 #if defined(_MFE_T8_)&&defined(_KERNEL_MODE_)
1507 PROBE_IO_EXIT(MDRV_MAJOR_MFE, _IOC_NR(cmd));
1508 #endif
1509
1510 return 0;
1511 }
1512
1513
1514