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93 ///////////////////////////////////////////////////////////////////////////////
94
95 ///////////////////////////////////////////////////////////////////////////////////////////////////
96 ///
97 /// file drvTSP2.c
98 /// @brief Transport Stream Processer (TSP) Driver Interface
99 /// @author MStar Semiconductor,Inc.
100 /// @attention
101 /// All TSP DDI are not allowed to use in any interrupt context other than TSP ISR and Callback
102 ///////////////////////////////////////////////////////////////////////////////////////////////////
103
104 // Common Definition
105 #include "MsCommon.h"
106 #include "MsVersion.h"
107 #include "tsp2_msos.h"
108 #include "tsp2_nos.h"
109 #include "ULog.h"
110
111 #ifdef MSOS_TYPE_LINUX_KERNEL
112 #include <linux/sched.h>
113 #include <linux/string.h>
114 #include <linux/delay.h>
115 #include <linux/spinlock.h>
116 #else
117 #include "string.h"
118 #endif
119
120 #ifdef SECURE_PVR_ENABLE
121 #include "halCHIP.h"
122 #include "../../drv/mbx/apiMBX_St.h"
123 #include "../../drv/mbx/apiMBX.h"
124 #include "../drv/sys/tee_client_api.h"
125 #include "drvSYS.h"
126 #endif
127
128 #if defined(MSOS_TYPE_LINUX)
129 #include <sys/ioctl.h>
130 #include <unistd.h>
131 #include <fcntl.h> // O_RDWR
132 #include "mdrv_firmware_io.h"
133 #endif
134
135 #include "drvMMIO.h"
136
137 #if defined(OTV_ENABLE)
138 #include "drvOTV.h"
139 #endif
140
141 #include "drvTSP2.h"
142
143 // Internal Definition
144 #include "asmCPU.h"
145 #include "regTSP.h"
146 #include "halTSP.h"
147 #include "halCHIP.h"
148
149 #include "drvSEM.h"
150
151
152 //-------------------------------------------------------------------------------------------------
153 // Driver Compiler Options
154 //-------------------------------------------------------------------------------------------------
155 #define SWITCH_TSP_UART 0
156
157 //-------------------------------------------------------------------------------------------------
158 // Local Defines
159 //-------------------------------------------------------------------------------------------------
160
161
162 #define FWTSP_CHECK_CODE "<FWTSP>"
163
164 // Blocking events
165 #define TSP_SetEvent(eventid, flag) ({ MS_BOOL bRet = TSP_OS_EventSet(eventid, (flag)); (bRet == TRUE)? TRUE : FALSE; })
166 #define TSP_GetEvent(eventid, events, flag, opt, timeout) ({ MS_BOOL bRet = TSP_OS_EventGet(eventid, (flag), (events), (opt), (timeout)); (bRet == TRUE)? TRUE : FALSE; })
167
168 // Filter event flags
169 #define TSP_FLAG_SetSecRdy(fltid) ({ MS_BOOL bRet = TSP_OS_EventSet(_s32SecRdyFlags[fltid>>5], (1<<(fltid&0x1F))); (bRet == TRUE)? TRUE : FALSE; })
170 #define TSP_FLAG_GetSecRdy(fltid, events, opt) ({ MS_BOOL bRet = TSP_OS_EventGet(_s32SecRdyFlags[fltid>>5], (1<<(fltid&0x1F)), (events), (opt), 0); (bRet == TRUE)? TRUE : FALSE; })
171 #define TSP_FLAG_ModeSecRdy(idx, mask,events, opt) ({ MS_BOOL bRet = TSP_OS_EventGet(_s32SecRdyFlags[idx], mask, (events), (opt), 0); (bRet == TRUE)? TRUE : FALSE; })
172
173 #define TSP_FLAG_SetCrcErr(fltid) ({ MS_BOOL bRet = TSP_OS_EventSet(_s32CrcErrFlags[fltid>>5], (1<<(fltid&0x1F))); (bRet == TRUE)? TRUE : FALSE; })
174 #define TSP_FLAG_GetCrcErr(fltid, events, opt) ({ MS_BOOL bRet = TSP_OS_EventGet(_s32CrcErrFlags[fltid>>5], (1<<(fltid&0x1F)), (events), (opt), 0); (bRet == TRUE)? TRUE : FALSE; })
175 #define TSP_FLAG_ModeCrcErr(idx,mask ,events, opt) ({ MS_BOOL bRet = TSP_OS_EventGet(_s32CrcErrFlags[idx], mask, (events), (opt), 0); (bRet == TRUE)? TRUE : FALSE; })
176
177 #define TSP_FLAG_SetSecOvf(fltid) ({ MS_BOOL bRet = TSP_OS_EventSet(_s32SecOvfFlags[fltid>>5], (1<<(fltid&0x1F))); (bRet == TRUE)? TRUE : FALSE; })
178 #define TSP_FLAG_GetSecOvf(fltid, events, opt) ({ MS_BOOL bRet = TSP_OS_EventGet(_s32SecOvfFlags[fltid>>5], (1<<(fltid&0x1F)), (events), (opt), 0); (bRet == TRUE)? TRUE : FALSE; })
179 #define TSP_FLAG_ModeSecOvf(idx,mask ,events, opt) ({ MS_BOOL bRet = TSP_OS_EventGet(_s32SecOvfFlags[idx], mask, (events), (opt), 0); (bRet == TRUE)? TRUE : FALSE; })
180
181 #define TSP_FLAG_SetFltDis(fltid) ({ MS_BOOL bRet = TSP_OS_EventSet(_s32FltDisFlags[fltid>>5], (1<<(fltid&0x1F))); (bRet == TRUE)? TRUE : FALSE; })
182 #define TSP_FLAG_GetFltDis(fltid, events, opt) ({ MS_BOOL bRet = TSP_OS_EventGet(_s32FltDisFlags[fltid>>5], (1<<(fltid&0x1F)), (events), (opt), 0); (bRet == TRUE)? TRUE : FALSE; })
183 #define TSP_FLAG_ModeFltDis(idx, mask,events, opt) ({ MS_BOOL bRet = TSP_OS_EventGet(_s32FltDisFlags[idx], mask, (events), (opt), 0); (bRet == TRUE)? TRUE : FALSE; })
184
185 #define TSP_FLAG_FREE_TIMEOUT 8
186 #define TSP_FLAG_SetFree(fltid) ({ MS_BOOL bRet = TSP_OS_EventSet(_s32FreeFlags[fltid>>5], (1<<(fltid&0x1F))); (bRet == TRUE)? TRUE : FALSE; })
187 #define TSP_FLAG_GetFree(fltid, events, opt) ({ MS_BOOL bRet = TSP_OS_EventGet(_s32FreeFlags[fltid>>5], (1<<(fltid&0x1F)), (events), (opt), 0); (bRet == TRUE)? TRUE : FALSE; })
188 #define TSP_FLAG_ModeFree(idx, mask,events, opt) ({ MS_BOOL bRet = TSP_OS_EventGet(_s32FreeFlags[idx], mask, (events), (opt), 0); (bRet == TRUE)? TRUE : FALSE; })
189 #define TSP_FLAG_SetDone(fltid) ({ MS_BOOL bRet = TSP_OS_EventSet(_s32DoneFlags[fltid>>5], (1<<(fltid&0x1F))); (bRet == TRUE)? TRUE : FALSE; })
190 #define TSP_FLAG_GetDone(fltid, events, opt) ({ MS_BOOL bRet = TSP_OS_EventGet(_s32DoneFlags[fltid>>5], (1<<(fltid&0x1F)), (events), (opt), TSP_FLAG_FREE_TIMEOUT); (bRet == TRUE)? TRUE : FALSE; })
191
192 #define TSP_FLAG_SetModeFlags(fltid) { _s32ModeFlags[fltid>>5] |= (1<<(fltid&0x1F)) ;}
193 #define TSP_FLAG_GetModeFlags(idx ,flags) { flags = _s32ModeFlags[idx] ; }
194 #define TSP_FLAG_ClrModeFlags(fltid) { _s32ModeFlags[fltid>>5] &= (~(1<<(fltid&0x1F))); }
195
196 #define TSP_FLAG_SetOvfRst(fltid) (_s32OvfRstFlags[fltid>>5] |= (1<<(fltid&0x1F)))
197 #define TSP_FLAG_GetOvfRst(fltid) ((_s32OvfRstFlags[fltid>>5] & (1<<(fltid&0x1F)))?TRUE:FALSE )
198 #define TSP_FLAG_ClrOvfRst(fltid) (_s32OvfRstFlags[fltid>>5] &= (~(1<<(fltid&0x1F))))
199
200 // for mutiple process using, record which filter is enabled by this process
201 #define _TSP_SetSecNotifyId(fltid) (_u32SecNotifyId[(fltid>>5)] |= (1 << (fltid&0x1F)))
202 #define _TSP_RemoveSecNotifyId(fltid) (_u32SecNotifyId[(fltid>>5)] &= ~(1 << (fltid&0x1F)))
203 #define _TSP_ChkSecNotifyId(fltid) (_u32SecNotifyId[(fltid>>5)] & (1 << (fltid&0x1F)))
204
205 // for mutiple process using, record which pvr engine is enabled by this process
206 #define _TSP_SetPvrNotifyId(fltid) (_u32PvrNotifyId[(fltid>>5)] |= (1 << (fltid&0x1F)))
207 #define _TSP_RemovePvrNotifyId(fltid) (_u32PvrNotifyId[(fltid>>5)] &= ~(1 << (fltid&0x1F)))
208 #define _TSP_ChkPvrNotifyId(fltid) (_u32PvrNotifyId[(fltid>>5)] & (1 << (fltid&0x1F)))
209
210 // for mutiple process using, record which hw pcr is enabled by this process
211 #define _TSP_SetHwPcrNotifyId(fltid) (_u32HwPcrNotifyId[(fltid>>5)] |= (1 << (fltid&0x1F)))
212 #define _TSP_RemoveHwPcrNotifyId(fltid) (_u32HwPcrNotifyId[(fltid>>5)] &= ~(1 << (fltid&0x1F)))
213 #define _TSP_ChkHwPcrNotifyId(fltid) (_u32HwPcrNotifyId[(fltid>>5)] & (1 << (fltid&0x1F)))
214
215 #define TSP_ENTRY() if (!TSP_OS_MutexObtain(_ptsp_res->_s32MutexId, TSP_OS_MUTEX_TIMEOUT)) \
216 { \
217 _ptsp_res->_tspInfo.LastErr = E_TSP_FAIL_FUNCTION; \
218 return E_TSP_FAIL_FUNCTION; \
219 } \
220 TSP_LOCK(); \
221
222
223
224 #define TSP_RETURN(_ret) TSP_UNLOCK(); \
225 TSP_OS_MutexRelease(_ptsp_res->_s32MutexId); \
226 if (_ret != E_TSP_OK) { _ptsp_res->_tspInfo.LastErr = _ret; } \
227 return _ret; // Should be optimized by compiler
228
229 // @TODO: Jerry
230 // Review and check the rule of LOCK
231 #define TSP_LOCK() TSP_OS_MutexObtain(_ptsp_res->_s32LockId, TSP_OS_MUTEX_TIMEOUT); \
232 MDrv_SEM_Lock(E_SEM_CA , MSOS_WAIT_FOREVER)
233 // if you got compile error for E_SEM_CA, you should update your drvSEM
234 // to CL#817352 CL provide by johnson.chen
235 #define TSP_UNLOCK() MDrv_SEM_Unlock(E_SEM_CA); \
236 TSP_OS_MutexRelease(_ptsp_res->_s32LockId)
237 #ifdef MSOS_TYPE_LINUX_KERNEL
238 #define _TSP_INT_LOCK() spin_lock_irqsave(&_ptsp_res->_s32IntRegMutexId, _ptsp_res->_IntRegFlags)
239 #define _TSP_INT_UNLOCK() spin_unlock_irqrestore(&_ptsp_res->_s32IntRegMutexId,_ptsp_res->_IntRegFlags)
240 #else
241 #define _TSP_INT_LOCK() TSP_OS_MutexObtain(_ptsp_res->_s32IntRegMutexId, TSP_OS_MUTEX_TIMEOUT)
242 #define _TSP_INT_UNLOCK() TSP_OS_MutexRelease(_ptsp_res->_s32IntRegMutexId)
243 #endif
244
245 #define TSP_PVR_ENTRY() if (!TSP_OS_MutexObtain(_ptsp_res->_s32PvrMutexId, TSP_OS_MUTEX_TIMEOUT)) \
246 { \
247 _ptsp_res->_tspInfo.LastErr = E_TSP_FAIL_FUNCTION; \
248 return E_TSP_FAIL_FUNCTION; \
249 }
250
251 #define TSP_PVR_RETURN(_ret) TSP_OS_MutexRelease(_ptsp_res->_s32PvrMutexId); \
252 if (_ret != E_TSP_OK) { _ptsp_res->_tspInfo.LastErr = _ret; } \
253 return _ret; // Should be optimized by compiler
254
255 #define TSP_FQ_NUM_CHECK_RET(idx) if( (MS_U32)idx >= (MS_U32)TSP_FQ_NUM ) \
256 { printf("[TSP][FQ][ERR] FQ Engine [%uld] not exist ! \n", idx); \
257 return 0; }
258
259 #define TSP_FLT2BUF_NULL 0xFFFFFFFF
260 #define TSP_BUF2FLT_NULL TSP_FLT2BUF_NULL
261
262 #define TSP_CHECK(_b, _f, _a...) { if (!(_b)) { TSP_OS_Print("[TSP_ASSERT]"); TSP_OS_Print(_f, ##_a); return E_TSP_FAIL;} }
263 #define TSP_CHECK_UNLOCK(_b, _f, _a...) { if (!(_b)) { TSP_OS_Print("[TSP_ASSERT]"); TSP_OS_Print(_f, ##_a); TSP_UNLOCK(); return E_TSP_FAIL; } }
264 #define TSP_RES_ALLOC_STC_CHECK(u32StcEng) { \
265 if((_ptsp_res->_bIsStcEverAlloc == TRUE) && (_ptsp_res->_stTspStcState[u32StcEng].bUsed == FALSE)) \
266 { \
267 TSP_OS_Print("[TSP_ERROR][%s][%d]: Mix old & new STC resource allocation scheme !!\n", __FUNCTION__, __LINE__); \
268 } \
269 }
270
271 #define TSP_RES_ALLOC_TSPPATH_CHECK(PhyTspPath) { \
272 if((_ptsp_res->_bIsTspPathEverAlloc == TRUE) && (_ptsp_res->_stTspPathState[PhyTspPath].bUsed == FALSE)) \
273 { \
274 TSP_OS_Print("[TSP_ERROR][%s][%d]: Mix old & new TSP Path resource allocation scheme !!\n", __FUNCTION__, __LINE__); \
275 } \
276 }
277
278 #define TSP_PCRFLT_GET_ID(NUM) (_tspFltIdMap.u32PcrFltId_Start + (NUM))
279
280
281 #define TSP_DBG(_l, _f, _a...) { if (_u32DbgLevel >= (_l)) { TSP_OS_Print("[TSP_DBG]"); TSP_OS_Print(_f, ##_a); } }
282
283 #ifdef MS_DEBUG
284 #define TSP_DBG_TASK() { _ptsp_res->_tspInfo.u32TaskLine = __LINE__; }
285 #else
286 #define TSP_DBG_TASK() { }
287 #endif
288
289
290 #ifdef MSOS_TYPE_LINUX_KERNEL
291 #define DEMUX_EVENT_DATA_DISCARDED (0x00000001U)
292 #define DEMUX_EVENT_CRC_FAILED (0x00000010U)
293 #endif
294
295 #define TSP_NEED_SEC_FILTER(FltType) (E_TSP_FLT_USER_SEC == (FltType & E_TSP_FLT_USER_MASK)) || \
296 (E_TSP_FLT_USER_PES == (FltType & E_TSP_FLT_USER_MASK)) || \
297 (E_TSP_FLT_USER_PKT == (FltType & E_TSP_FLT_USER_MASK)) || \
298 (E_TSP_FLT_USER_PCR == (FltType & E_TSP_FLT_USER_MASK)) || \
299 (E_TSP_FLT_USER_TTX == (FltType & E_TSP_FLT_USER_MASK))
300
301 #define TSP_POLLING_TASK_DELAY 50
302
303 #define DRVTSP_MAX_PROCESS_NUM (10)
304
305 #ifdef MSOS_TYPE_LINUX_KERNEL
306 #define current get_current()
307 #endif
308
309 //-------------------------------------------------------------------------------------------------
310 // Local Structures
311 //-------------------------------------------------------------------------------------------------
312 //----------------
313 //For Tee
314 //----------------
315 #ifdef SECURE_PVR_ENABLE
316 typedef enum
317 {
318 E_TSP_TEE_TO_REE_MBX_MSG_NULL,
319 E_TSP_TEE_TO_REE_MBX_ACK_MSG_INVALID,
320 E_TSP_TEE_TO_REE_MBX_ACK_MSG_NO_TEE,
321 E_TSP_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS,
322 E_TSP_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL
323 } TSP_TEE_TO_REE_MBX_ACK_TYPE;
324 #endif
325
326 typedef struct DLL_PACKED _TSP_Info
327 {
328 MS_BOOL bSWInit;
329 MS_BOOL bISRTaskEn;
330 TSP_SW_Status Status;
331 TSP_Result LastErr;
332
333 MS_U32 Pid[TSP_PIDFLT_NUM_ALL-1];
334 EN_TSP_Id OwnerId [TSP_PIDFLT_NUM_ALL-1];
335 TSP_FltState FltState[TSP_PIDFLT_NUM_ALL-1];
336 TSP_FltType FltType [TSP_PIDFLT_NUM_ALL-1];
337 MS_U32 Flt2Buf [TSP_PIDFLT_NUM];
338
339 TSP_FltMode FltMode [TSP_SECFLT_NUM];
340 TSP_Event FltEvent [TSP_SECFLT_NUM];
341 P_TSP_Callback FltCallback[TSP_SECFLT_NUM];
342 #if !defined (__aarch64__)
343 MS_U32 u32AlignDummy[TSP_SECFLT_NUM]; //align size for MI init share mem size check fail
344 #endif
345
346 TSP_FltState BufState[TSP_SECBUF_NUM]; // @TODO: FltState, SecFltState?
347 MS_U32 Buf2Flt [TSP_SECBUF_NUM];
348
349 TSP_InitParam Param;
350
351 // Legacy
352 MS_BOOL bSuspend;
353 // Debug information
354 MS_U32 u32TaskLine;
355
356 MS_U8 MulFlt2Buf[TSP_SECFLT_NUM];
357
358 MS_S32 s32TspEvtId[TSP_SECFLT_NUM];
359 } TSP_Info;
360
361 typedef struct
362 {
363 MS_U32 u32StcOffset;
364 MS_BOOL bAdd;
365 }STC_Offset;
366
367 typedef struct
368 {
369 MS_BOOL bEnable;
370 MS_BOOL bUpdateOnce;
371 }STC_UpdateCtrl;
372
373 typedef struct _DrvTSP_Stc_State
374 {
375 MS_U32 u32PcrFltId;
376 MS_BOOL bUsed;
377 }DrvTSP_Stc_State;
378
379 typedef struct
380 {
381 MS_BOOL bUsed;
382 } DrvTSP_Path_State;
383
384 typedef struct
385 {
386 // all pid filter ids
387 MS_U32 u32PidFltIdAll;
388 // section filter , section buffer
389 MS_U32 u32SecFltId_Start, u32SecFltId_End;
390 MS_U32 u32SecBufId_Start, u32SecBufId_End;
391 // pid filter
392 MS_U32 u32PidFltId_Start, u32PidFltId_End;
393 // PCR filter
394 MS_U32 u32PcrFltId_Start, u32PcrFltId_End;
395 // REC filter idx
396 MS_U32 u32RecFltIdx;
397 } DrvTSP_FltIdMap;
398
399 #ifdef DMX_UTOPIA_2K
400 typedef struct _DrvTSP_KMode_ProcEvtIdTbl
401 {
402 #ifdef MSOS_TYPE_LINUX_KERNEL
403 pid_t tgid;
404 #endif
405
406 MS_S32 s32TspEvtId;
407 }DrvTSP_KMode_ProcEvtIdTbl;
408 #endif
409
410 typedef struct DLL_PACKED _TSP_RESOURCE_PRIVATE
411 {
412 MS_S32 _s32TaskId;
413 MS_S32 _s32MutexId;
414 MS_S32 _s32LockId;
415 #ifdef MSOS_TYPE_LINUX_KERNEL
416 spinlock_t _s32IntRegMutexId;
417 unsigned long _IntRegFlags;
418 #else
419 MS_S32 _s32IntRegMutexId;
420 #endif
421 MS_S32 _s32PvrMutexId;
422
423 TSP_Info _tspInfo;
424 #if defined(__LEGACY__)
425 TSP_Event _PvrEvtNotify;
426 P_TSP_Callback _PvrCallback;
427 #if !defined (__aarch64__)
428 MS_U32 u32AlignDummy; //align size for MI init share mem size check fail
429 #endif
430 MS_S32 _s32PvrEvtId;
431 #endif
432
433 MS_U8 _u8_ResetPcr[STC_ENG_NUM];
434 MS_U32 _u32_PrevStcBase[STC_ENG_NUM];
435 MS_U32 _u32_PrevPllControl[STC_ENG_NUM];
436 STC_Offset _u32_StcOffset[STC_ENG_NUM];
437 STC_UpdateCtrl _u32_StcUpdateCtrl[STC_ENG_NUM];
438 DrvTSP_Stc_State _stTspStcState[STC_ENG_NUM];
439 MS_BOOL _bIsStcEverAlloc;
440 DrvTSP_Path_State _stTspPathState[TSP_TSIF_NUM];
441 MS_BOOL _bIsTspPathEverAlloc;
442
443 MS_U32 _Current_PVR;
444
445 //[NOTE][Eddie]
446 // Since STB and TV architecture are different, STB have to emulate TV behavior to avoid
447 // Live/File collision of PLAYBACK channel.
448 TSP_FltType _Current_Live;
449
450 //for dummy record filter compatibility
451 MS_U32 u32RecFltBufId;
452 MS_U32 u32RecFltPID;
453 DrvTSP_TsIf_Set TsIf_Src[TSP_TSIF_NUM];
454 #ifdef SECURE_PVR_ENABLE
455 SYS_TEEINFO _teemode;
456 DrvTSP_SecureBuf _stSecBuf;
457 #endif
458
459 MS_U32 _u32StcAdjustUnit;
460
461 }TSP_RESOURCE_PRIVATE;
462
463 static MS_S32 _s32EventId = -1;
464 static MS_S32 _s32CrcErrFlags[(TSP_SECFLT_NUM+31)>>5] = { [0 ... (((TSP_SECFLT_NUM+31)>>5)-1)] = -1 };
465 static MS_S32 _s32SecOvfFlags[(TSP_SECFLT_NUM+31)>>5] = { [0 ... (((TSP_SECFLT_NUM+31)>>5)-1)] = -1 };
466 static MS_S32 _s32SecRdyFlags[(TSP_SECFLT_NUM+31)>>5] = { [0 ... (((TSP_SECFLT_NUM+31)>>5)-1)] = -1 };
467 static MS_S32 _s32FltDisFlags[(TSP_SECFLT_NUM+31)>>5] = { [0 ... (((TSP_SECFLT_NUM+31)>>5)-1)] = -1 };
468 static MS_S32 _s32FreeFlags [(TSP_SECFLT_NUM+31)>>5] = { [0 ... (((TSP_SECFLT_NUM+31)>>5)-1)] = -1 };
469 static MS_S32 _s32DoneFlags [(TSP_SECFLT_NUM+31)>>5] = { [0 ... (((TSP_SECFLT_NUM+31)>>5)-1)] = -1 };
470
471 static MS_S32 _s32ModeFlags[(TSP_SECFLT_NUM+31)>>5] = { [0 ... (((TSP_SECFLT_NUM+31)>>5)-1)] = -1 };
472 static MS_S32 _s32OvfRstFlags[(TSP_SECFLT_NUM+31)>>5] = { [0 ... (((TSP_SECFLT_NUM+31)>>5)-1)] = -1 };
473
474 static MS_U32 _u32SecNotifyId[(TSP_SECFLT_NUM+31)>>5] = { [0 ... (((TSP_SECFLT_NUM+31)>>5)-1)] = 0 }; //for ISR processing
475 static MS_U32 _u32PvrNotifyId[(TSP_PVR_IF_NUM+31)>>5] = { [0 ... (((TSP_PVR_IF_NUM+31)>>5)-1)] = 0 };
476 static MS_U32 _u32HwPcrNotifyId[(TSP_PCRFLT_NUM+31)>>5] = { [0 ... (((TSP_PCRFLT_NUM+31)>>5)-1)] = 0 };
477
478 //-------------------------------------------------------------------------------------------------
479 // Global Variables
480 //-------------------------------------------------------------------------------------------------
481 #ifndef TSP_UTOPIA_20
482 static TSP_RESOURCE_PRIVATE _tsp_res = {
483 ._s32TaskId = -1,
484 ._s32MutexId = -1,
485 ._s32LockId = -1,
486 #ifdef MSOS_TYPE_LINUX_KERNEL
487 ._s32IntRegMutexId = __SPIN_LOCK_UNLOCKED(_s32IntRegMutexId),
488 ._IntRegFlags = 0,
489 #else
490 ._s32IntRegMutexId = -1,
491 #endif
492 ._s32PvrMutexId = -1,
493
494 ._tspInfo = {
495 .bSWInit = FALSE,
496 .bISRTaskEn = FALSE,
497 .LastErr = E_TSP_OK,
498 .bSuspend = FALSE,
499 .u32TaskLine = 0,
500 },
501
502 #if defined(__LEGACY__)
503 ._PvrEvtNotify = E_TSP_EVENT_DATA_IDLE,
504 ._PvrCallback = NULL,
505 ._s32PvrEvtId = -1,
506 #endif
507
508 ._u8_ResetPcr = {[0 ... (STC_ENG_NUM-1)] = 3},
509 ._u32_PrevStcBase = {[0 ... (STC_ENG_NUM-1)] = 0},
510 ._u32_PrevPllControl = {[0 ... (STC_ENG_NUM-1)] = 0},
511 ._u32_StcOffset = {[0 ... (STC_ENG_NUM-1)] = {0,TRUE}},
512 ._u32_StcUpdateCtrl = {[0 ... (STC_ENG_NUM-1)] = {TRUE,FALSE}},
513 ._stTspStcState = {[0 ... (STC_ENG_NUM-1)] = {0xFFFFFFFF, FALSE}},
514
515 ._bIsStcEverAlloc = FALSE,
516 ._stTspPathState = {[0 ... (TSP_TSIF_NUM-1)] = {FALSE}},
517 ._bIsTspPathEverAlloc = FALSE,
518
519 ._Current_PVR = 0,
520 ._Current_Live = E_TSP_FLT_SRC_LIVE0,
521 .u32RecFltBufId = TSP_SECFLT_SECBUF_MAX,
522 .u32RecFltPID = TSP_PID_NULL,
523 .TsIf_Src = {[0 ... (TSP_TSIF_NUM-1)] = {E_TSP_TS_INVALID,FALSE,TRUE,TRUE}},
524 #ifdef SECURE_PVR_ENABLE
525 ._teemode = {.OsType = SYS_TEEINFO_OSTYPE_NOTEE},
526 ._stSecBuf = { 0, 0, 0, 0},
527 #endif
528 ._u32StcAdjustUnit = 100,
529 };
530
531 static TSP_RESOURCE_PRIVATE* _ptsp_res = &_tsp_res;
532 #else
533 static TSP_RESOURCE_PRIVATE* _ptsp_res = NULL;
534 #endif
535
536 static DrvTSP_FltIdMap _tspFltIdMap ={
537 .u32SecFltId_Start = TSP_SECFLT_START_ID,
538 .u32SecFltId_End = TSP_SECFLT_END_ID,
539 .u32SecBufId_Start = TSP_SECBUF_START_ID,
540 .u32SecBufId_End = TSP_SECBUF_END_ID,
541 .u32PidFltId_Start = TSP_PIDFLT_START_ID,
542 .u32PidFltId_End = TSP_PIDFLT_END_ID,
543 .u32PcrFltId_Start = TSP_PCRFLT_START_ID,
544 .u32PcrFltId_End = TSP_PCRFLT_END_ID,
545 .u32RecFltIdx = TSP_RECFLT_IDX,
546 };
547
548
549
550 //-------------------------------------------------------------------------------------------------
551 // Local Variables
552 //-------------------------------------------------------------------------------------------------
553
554 static MSIF_Version _drv_tsp_version = {
555 .DDI = { TSP_DRV_VERSION, },
556 };
557
558 static TSP_DbgLevel _u32DbgLevel = E_TSP_DBG_MUST;
559
560 MS_U32 _u32IntNum = E_INT_IRQ_TSP2HK;
561
562 #ifdef MSOS_TYPE_LINUX_KERNEL
563 wait_queue_head_t tsp_wq_head[TSP_SECFLT_NUM];
564 static MS_U32 _u32SecEvent[TSP_SECFLT_NUM];
565 #endif // MSOS_TYPE_LINUX_KERNEL
566
567 static MS_BOOL _bBankInit = FALSE;
568
569 static MS_BOOL _s32_IsrTaskReturn = FALSE;
570
571 static MS_BOOL _bIsFltMapped;
572
573 #ifdef MSOS_TYPE_LINUX_KERNEL
574 static DrvTSP_KMode_ProcEvtIdTbl _stKModePrcEvtTbl[DRVTSP_MAX_PROCESS_NUM];
575 static MS_U32 _u32KPrcEvtTblUseFlag = 0; //bit control for event table used
576 #endif
577
578 //----- For optee ------------------
579 #ifdef SECURE_PVR_ENABLE
580 #define MSTAR_UPA_DMXTA_UUID {0x7a7c8b61, 0x5d74, 0x4b6c, {0xb2, 0xa9, 0x92, 0xe4, 0x9c, 0xe8, 0x66, 0xbd} }
581 #define SYS_TEEC_OPERATION_INITIALIZER { 0 }
582
583 static const char optee_dmx[] = "opteearmtz00";
584 char *_dmx_device = (char *)optee_dmx;
585 TEEC_Context dmx_mstar_teec_ctx;
586 TEEC_Session dmx_session = { 0 };
587 TEEC_UUID dmx_uuid = MSTAR_UPA_DMXTA_UUID;
588 TEEC_Operation dmx_op = SYS_TEEC_OPERATION_INITIALIZER;
589 #endif //SECURE_PVR_ENABLE
590
591 //For Optee
592 #ifdef SECURE_PVR_ENABLE
593 extern MS_U32 MDrv_SYS_TEEC_InitializeContext(const char *name, TEEC_Context *context);
594 extern MS_U32 MDrv_SYS_TEEC_Open(TEEC_Context *context, TEEC_Session *session, const TEEC_UUID *destination, MS_U32 connection_method, const void *connection_data, TEEC_Operation *operation, MS_U32 *error_origin);
595 extern MS_U32 MDrv_SYS_TEEC_InvokeCmd(TEEC_Session *session, MS_U32 cmd_id, TEEC_Operation *operation, MS_U32 *error_origin);
596 extern void MDrv_SYS_TEEC_Close(TEEC_Session *session);
597 extern void MDrv_SYS_TEEC_FinalizeContext(TEEC_Context *context);
598 #endif
599
600 //-------------------------------------------------------------------------------------------------
601 // Debug Functions
602 //-------------------------------------------------------------------------------------------------
603
MDrv_TSP_FLT_DropEnable(MS_BOOL bSet)604 TSP_Result MDrv_TSP_FLT_DropEnable(MS_BOOL bSet)
605 {
606 TSP_ENTRY();
607 HAL_TSP_SecFlt_DropEnable(bSet);
608 TSP_RETURN(E_TSP_OK);
609 }
610
611 //-------------------------------------------------------------------------------------------------
612 // Local Functions
613 //-------------------------------------------------------------------------------------------------
614 static TSP_Result _MDrv_FltAllocForRec(MS_U32 u32Eng, TSP_SRC_SEQ eEngSrc, MS_U32 *pu32FltId);
615 static TSP_Result _MDrv_FltFreeForRec(MS_U32 u32FltId);
616 static TSP_Result _MDrv_FltSetPIDForRec(MS_U32 u32FltId, MS_U32 u32PID);
617 static TSP_Result _MDrv_FltGetPIDForRec(MS_U32 u32FltId, MS_U32* pu32PID);
618 static TSP_Result _MDrv_FltEnableForRec(MS_U32 u32FltId, MS_BOOL bEnable);
619 static TSP_Result _MDrv_PVR_Eng_SetBuffer(MS_U32 u32Eng, MS_PHYADDR u32Start0, MS_PHYADDR u32Start1, MS_U32 u32Size0, MS_U32 u32Size1);
620 static TSP_Result _MDrv_PVR_Eng_Start(MS_U32 u32Eng, TSP_DRV_PVR_RecMode eRecMode, MS_BOOL bStart) ;
621 static TSP_Result _MDrv_PVR_Eng_Pause(MS_U32 u32Eng, MS_BOOL bPause);
622 static TSP_Result _MDrv_PVR_Eng_GetWriteAddr(MS_U32 u32Eng, MS_PHY *pu32WriteAddr) ;
623 static TSP_Result _MDrv_PVR_Eng_Notify(MS_U32 u32Eng, TSP_Event eEvents, P_TSP_Callback pfCallback) ;
624 static TSP_Result _MDrv_PVR_Eng_SetPacketMode(MS_U32 u32Eng, MS_BOOL bSet);
625 static TSP_Result _MDrv_PVR_Eng_TimeStampSetRecordStamp(MS_U32 u32Eng, MS_U32 u32Stamp);
626 static TSP_Result _MDrv_PVR_Eng_TimeStampGetRecordStamp(MS_U32 u32Eng, MS_U32* u32Stamp);
627 static void _MDrv_TSP_FLT_ResetFltId(void);
628 /*
629 static void _TSP_CMDQ_Init(void)
630 {
631 while (HAL_TSP_CMDQ_Count()); // wait command finish
632 }
633 */
634 // Switch Uart to TSP Fw, function works only when fw support uart functionality
635 // Compile Fwtsp.c with UART_ENABLE in chip.h
636
637 #if SWITCH_TSP_UART
_TSP_Switch_Uart(void)638 static void _TSP_Switch_Uart(void)
639 {
640 MS_U32 u32Base = 0 ,u32Size;
641 MS_U16 u16Temp;
642
643 TSP_DBG(E_TSP_DBG_MUST,"Switch Uart to TSP firmware !!\n");
644
645 MDrv_MMIO_GetBASE( &u32Base, &u32Size, MS_MODULE_CHIPTOP );
646 TSP_DBG(E_TSP_DBG_MUST,"ChipTop MMIO base = %08lX \n",u32Base);
647
648 if(u32Base)
649 {
650 u16Temp = READ_WORD((u32Base + 0x1EA6*2));
651 TSP_DBG(E_TSP_DBG_MUST,"ChipTop Uart setting = %x \n",u16Temp);
652 u16Temp = ((u16Temp & 0xFFF0) | 0x3 );
653 WRITE_WORD((u32Base + 0x1EA6*2),u16Temp);
654 }
655 else
656 {
657 TSP_DBG(E_TSP_DBG_MUST,"MMIO ChipTOP GetBase Fail\n");
658 }
659
660 }
661 #endif
662
_TSP_InitResource(TSP_RESOURCE_PRIVATE * presource)663 static MS_BOOL _TSP_InitResource(TSP_RESOURCE_PRIVATE* presource)
664 {
665 MS_U32 u32ii = 0;
666
667 if(presource == NULL)
668 {
669 TSP_DBG(E_TSP_DBG_MUST,"Utopia2 Resource address is NULL!\n");
670 return FALSE;
671 }
672
673 presource->_s32TaskId = -1;
674 presource->_s32MutexId = -1;
675 presource->_s32LockId = -1;
676 #ifdef MSOS_TYPE_LINUX_KERNEL
677 spin_lock_init(&presource->_s32IntRegMutexId);
678 #else
679 presource->_s32IntRegMutexId = -1;
680 #endif
681 presource->_s32PvrMutexId = -1;
682
683 presource->_tspInfo.bSWInit = FALSE;
684 presource->_tspInfo.bISRTaskEn = FALSE;
685 presource->_tspInfo.LastErr = E_TSP_OK;
686 presource->_tspInfo.bSuspend = FALSE;
687 presource->_tspInfo.u32TaskLine = 0;
688
689 #if defined(__LEGACY__)
690 presource->_PvrEvtNotify = E_TSP_EVENT_DATA_IDLE;
691 presource->_PvrCallback = NULL;
692 presource->_s32PvrEvtId = -1;
693 #endif
694
695 for(u32ii = 0; u32ii < STC_ENG_NUM; u32ii++)
696 {
697 presource->_u8_ResetPcr[u32ii] = 3;
698 presource->_u32_PrevStcBase[u32ii] = 0;
699 presource->_u32_PrevPllControl[u32ii] = 0;
700
701 presource->_stTspStcState[u32ii].u32PcrFltId = 0xFFFFFFFF;
702 presource->_stTspStcState[u32ii].bUsed = FALSE;
703 }
704
705 presource->_bIsStcEverAlloc = FALSE;
706
707 for(u32ii = 0; u32ii < TSP_TSIF_NUM; u32ii++)
708 {
709 presource->_stTspPathState[u32ii].bUsed = FALSE;
710 }
711
712 presource->_bIsTspPathEverAlloc = FALSE;
713
714 presource->_Current_PVR = 0;
715 presource->_Current_Live = E_TSP_FLT_SRC_LIVE0;
716
717 for(u32ii = 0; u32ii < TSP_TSIF_NUM; u32ii++)
718 {
719 presource->TsIf_Src[u32ii].ePad = E_TSP_TS_INVALID;
720 presource->TsIf_Src[u32ii].bClkInv = FALSE;
721 presource->TsIf_Src[u32ii].bExtSync = TRUE;
722 presource->TsIf_Src[u32ii].bParallel = TRUE;
723 }
724
725 #ifdef SECURE_PVR_ENABLE
726 presource->_teemode.OsType = SYS_TEEINFO_OSTYPE_NOTEE;
727 presource->_stSecBuf.u32BufId = 0;
728 presource->_stSecBuf.u32BufOpt = 0;
729 presource->_stSecBuf.u32BufSize = 0;
730 presource->_stSecBuf.phyBufAddr = 0;
731 #endif
732
733 presource->_u32StcAdjustUnit = 100;
734 _MDrv_TSP_FLT_ResetFltId();
735
736 return TRUE;
737
738 }
739
740 #ifdef SECURE_PVR_ENABLE
741 //For REE, HK cowork with Tee by mailbox
742
743 MS_BOOL _bTSPMbxInitFlag = 0;
744 MS_U8 _u8TSPMbxMsgClass = 0;
745 MBX_Msg _TSPReeToTeeMbxMsg;
746 MBX_Msg _TSPTeeToReeMbxMsg;
747
_TSP_REE_MbxParamToBufParam(MBX_Msg * pMsg,MS_U32 * pu32BufAddr,MS_U32 * pu32Size)748 MS_BOOL _TSP_REE_MbxParamToBufParam(MBX_Msg *pMsg, MS_U32* pu32BufAddr, MS_U32* pu32Size)
749 {
750 MS_U32 u32addr = 0;
751
752 if(pMsg->u8ParameterCount < 9)
753 return FALSE;
754
755 *pu32Size = ((MS_U32)pMsg->u8Parameters[0]) & 0xFFUL;
756 *pu32Size += ((((MS_U32)pMsg->u8Parameters[1]) << 8UL) & 0xFF00UL);
757 *pu32Size += ((((MS_U32)pMsg->u8Parameters[2]) << 16UL) & 0xFF0000UL);
758 *pu32Size += ((((MS_U32)pMsg->u8Parameters[3]) << 24UL) & 0xFF000000UL);
759 u32addr = ((MS_U32)pMsg->u8Parameters[4]) & 0xFFUL;
760 u32addr += ((((MS_U32)pMsg->u8Parameters[5]) << 8UL) & 0xFF00UL);
761 u32addr += (((MS_U32)pMsg->u8Parameters[6] << 16UL) & 0xFF0000UL);
762 u32addr += (((MS_U32)pMsg->u8Parameters[7] << 24UL) & 0xFF000000UL);
763 _miu_offset_to_phy(pMsg->u8Parameters[8], u32addr, *pu32BufAddr);
764
765 return TRUE;
766 }
767
_TSP_REE_RegisterMBX(void)768 MS_BOOL _TSP_REE_RegisterMBX(void)
769 {
770 MS_U8 ClassNum = 0;
771 MBX_Result result = E_MBX_ERR_NOT_INITIALIZED;
772 MS_U32 u32StartTime = 0;
773 const MS_U32 u32RetryTimeOutMs = 3000;
774
775 result = MApi_MBX_Init(E_MBX_CPU_MIPS,E_MBX_ROLE_HK,1000);
776 if (( E_MBX_SUCCESS != result) && ( E_MBX_ERR_SLOT_AREADY_OPENNED != result ))
777 {
778 TSP_DBG(E_TSP_DBG_ERROR, "DMX_REE MApi_MBX_Init fail\n");
779 return FALSE;
780 }
781 else
782 {
783 MApi_MBX_Enable(TRUE);
784 }
785
786 u32StartTime = MsOS_GetSystemTime();
787 while((MsOS_GetSystemTime() - u32StartTime) < u32RetryTimeOutMs)
788 {
789 result = MApi_MBX_QueryDynamicClass(E_MBX_CPU_MIPS_VPE1, "DMX_TEE", (MS_U8 *)&ClassNum);
790 if(result == E_MBX_SUCCESS)
791 break;
792 MsOS_DelayTask(100);
793 };
794
795 if(result != E_MBX_SUCCESS)
796 {
797 TSP_DBG(E_TSP_DBG_ERROR, "DMX_REE MApi_MBX_QueryDynamicClass fail\n");
798 return FALSE;
799 }
800
801 result = MApi_MBX_RegisterMSG(ClassNum, 10);
802 if (( E_MBX_SUCCESS != result) && ( E_MBX_ERR_SLOT_AREADY_OPENNED != result ))
803 {
804 TSP_DBG(E_TSP_DBG_ERROR, "%s fail\n",__FUNCTION__);
805 return FALSE;
806 }
807 else
808 {
809 _bTSPMbxInitFlag = TRUE;
810 _u8TSPMbxMsgClass = ClassNum;
811 return TRUE;
812 }
813 }
814
_TSP_Ree_SendMBXMsg(TSP_REE_TO_TEE_CMD_TYPE msg_type,void * param)815 MS_BOOL _TSP_Ree_SendMBXMsg(TSP_REE_TO_TEE_CMD_TYPE msg_type, void* param)
816 {
817 MBX_Result result = E_MBX_UNKNOW_ERROR;
818 DrvTSP_SecureBuf *pstSecBuf = (DrvTSP_SecureBuf*)param;
819 MS_U8 u8Id = 0;
820 MS_U32 u32Addr = 0, u32Size = 0;
821 MS_U32 u32Offset = 0;
822 MS_U8 u8MiuSel = 0;
823 MS_U8 u8Opt = 0;
824 MS_U32 u32StartTime = MsOS_GetSystemTime();
825 MS_U32 u32Timeout = 2000;
826 const MS_U32 u32TotTimeout = 6000;
827 const MS_U32 u32RevMsgTimeout = 2000;
828
829 if (_bTSPMbxInitFlag == FALSE)
830 {
831 return FALSE;
832 }
833
834 //retry mbx msg sending, if sending fail
835 u32StartTime = MsOS_GetSystemTime();
836 while((MsOS_GetSystemTime() - u32StartTime) < u32TotTimeout)
837 {
838 _TSPReeToTeeMbxMsg.eRoleID = E_MBX_CPU_MIPS_VPE1;
839 _TSPReeToTeeMbxMsg.u8Ctrl = 0;
840 _TSPReeToTeeMbxMsg.eMsgType = E_MBX_MSG_TYPE_INSTANT;
841 _TSPReeToTeeMbxMsg.u8MsgClass = _u8TSPMbxMsgClass;
842 _TSPReeToTeeMbxMsg.u8Index = msg_type;
843
844 switch(msg_type)
845 {
846 case E_DRVTSP_REE_TO_TEE_CMD_FW_LoadCode:
847 u8Id = (MS_U8)(pstSecBuf->u32BufId);
848 _TSPReeToTeeMbxMsg.u8Parameters[0] = u8Id;
849 _TSPReeToTeeMbxMsg.u8ParameterCount = 1;
850 break;
851 case E_DRVTSP_REE_TO_TEE_CMD_SET_VqBuf:
852 break;
853 case E_DRVTSP_REE_TO_TEE_CMD_SET_PvrBuf:
854 if(pstSecBuf == 0)
855 {
856 MS_DEBUG_MSG(TSP_DBG("[%s][%d] Parameter pointer of PVR buffer is 0!!!!\n",__FUNCTION__, __LINE__));
857 return FALSE;
858 }
859 u8Id = (MS_U8)(pstSecBuf->u32BufId);
860 u8Opt = (MS_U8)(pstSecBuf->u32BufOpt);
861 _TSPReeToTeeMbxMsg.u8Parameters[0] = u8Id;
862 _TSPReeToTeeMbxMsg.u8Parameters[1] = u8Opt;
863 _TSPReeToTeeMbxMsg.u8ParameterCount = 2;
864 break;
865 case E_DRVTSP_REE_TO_TEE_CMD_SET_FileinBuf:
866 if(pstSecBuf == 0)
867 {
868 MS_DEBUG_MSG(TSP_DBG("[%s][%d] Parameter pointer of Filein buffer is 0!!!!\n",__FUNCTION__, __LINE__));
869 return FALSE;
870 }
871 u8Id = (MS_U8)(pstSecBuf->u32BufId);
872 u8Opt = (MS_U8)(pstSecBuf->u32BufOpt);
873 u32Addr = (MS_U32)(pstSecBuf->phyBufAddr);
874 u32Size = pstSecBuf->u32BufSize;
875 _phy_to_miu_offset(u8MiuSel, u32Offset, u32Addr);
876 _TSPReeToTeeMbxMsg.u8Parameters[0] = (MS_U8)(u32Size & 0xFFUL);
877 _TSPReeToTeeMbxMsg.u8Parameters[1] = (MS_U8)((u32Size & 0xFF00UL) >> 8UL);
878 _TSPReeToTeeMbxMsg.u8Parameters[2] = (MS_U8)((u32Size & 0xFF0000UL) >> 16UL);
879 _TSPReeToTeeMbxMsg.u8Parameters[3] = (MS_U8)((u32Size & 0xFF000000UL) >> 24UL);
880 _TSPReeToTeeMbxMsg.u8Parameters[4] = (MS_U8)(u32Offset & 0xFFUL);
881 _TSPReeToTeeMbxMsg.u8Parameters[5] = (MS_U8)((u32Offset & 0xFF00UL) >> 8UL);
882 _TSPReeToTeeMbxMsg.u8Parameters[6] = (MS_U8)((u32Offset & 0xFF0000UL) >> 16UL);
883 _TSPReeToTeeMbxMsg.u8Parameters[7] = (MS_U8)((u32Offset & 0xFF000000UL) >> 24UL);
884 _TSPReeToTeeMbxMsg.u8Parameters[8] = u8MiuSel;
885 _TSPReeToTeeMbxMsg.u8Parameters[9] = u8Id;
886 _TSPReeToTeeMbxMsg.u8ParameterCount = 10;
887 break;
888 case E_DRVTSP_REE_TO_TEE_CMD_GET_PvrWPtr:
889 _TSPReeToTeeMbxMsg.u8Parameters[0] = (MS_U8)(pstSecBuf->u32BufId);
890 _TSPReeToTeeMbxMsg.u8ParameterCount = 1;
891 break;
892
893 default:
894 MS_DEBUG_MSG(TSP_DBG("[%s] Tee cmd not support\n",__FUNCTION__));
895 return FALSE;
896 }
897
898 result = MApi_MBX_SendMsg(&_TSPReeToTeeMbxMsg);
899 if (E_MBX_SUCCESS != result)
900 {
901 MsOS_DelayTask(100);
902 continue;
903 }
904
905 // Receive Reply ACK from TEE side.
906 memset(&_TSPTeeToReeMbxMsg, 0, sizeof(MBX_Msg));
907
908 _TSPTeeToReeMbxMsg.u8MsgClass = _u8TSPMbxMsgClass;
909
910 #if 0 // marked temperarily, wait kernel team to fix MApi_MBX_RecvMsg.
911 if(E_MBX_SUCCESS != MApi_MBX_RecvMsg(TEE_MBX_MSG_CLASS, &(TEE_TO_REE_MBX_MSG), 20, MBX_CHECK_INSTANT_MSG))
912 {
913 VPU_MSG_ERR("VDEC get Secure world ACK fail\n");
914 return E_TSP_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
915 }
916 else
917 #else
918 do
919 {
920 result = MApi_MBX_RecvMsg(_u8TSPMbxMsgClass, &_TSPTeeToReeMbxMsg, u32RevMsgTimeout, MBX_CHECK_INSTANT_MSG);
921 u32Timeout -= u32RevMsgTimeout;
922 } while((E_MBX_SUCCESS != result) && (u32Timeout > 0));
923 #endif
924
925 if((result == E_MBX_SUCCESS) && (_TSPTeeToReeMbxMsg.u8Index == E_TSP_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS))
926 {
927 break;
928 }
929
930 MsOS_DelayTask(100);
931
932 }
933
934 //parsing return data
935 if((result == E_MBX_SUCCESS) && (_TSPTeeToReeMbxMsg.u8Index == E_TSP_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS))
936 {
937 switch(msg_type)
938 {
939 case E_DRVTSP_REE_TO_TEE_CMD_SET_PvrBuf:
940 pstSecBuf->phyBufAddr = 0;
941 pstSecBuf->u32BufSize = 0;
942 _TSP_REE_MbxParamToBufParam(&_TSPTeeToReeMbxMsg, &u32Addr, &u32Size);
943 pstSecBuf->phyBufAddr = ((MS_PHY)u32Addr) & 0xFFFFFFFFUL;
944 pstSecBuf->u32BufSize = u32Size;
945 break;
946 case E_DRVTSP_REE_TO_TEE_CMD_GET_PvrWPtr:
947 pstSecBuf->phyBufAddr = 0;
948 if(_TSPTeeToReeMbxMsg.u8ParameterCount < 5)
949 {
950 return FALSE;
951 }
952 u32Addr = ((MS_U32)_TSPTeeToReeMbxMsg.u8Parameters[1]) & 0xFFUL;
953 u32Addr += ((((MS_U32)_TSPTeeToReeMbxMsg.u8Parameters[2]) << 8UL) & 0xFF00UL);
954 u32Addr += ((((MS_U32)_TSPTeeToReeMbxMsg.u8Parameters[3]) << 16UL) & 0xFF0000UL);
955 u32Addr += ((((MS_U32)_TSPTeeToReeMbxMsg.u8Parameters[4]) << 24UL) & 0xFF000000UL);
956 _miu_offset_to_phy(_TSPTeeToReeMbxMsg.u8Parameters[0], u32Offset, u32Addr);
957 pstSecBuf->phyBufAddr = ((MS_PHY)u32Addr) & 0xFFFFFFFFUL;
958 break;
959 default:
960 break;
961 }
962
963 return TRUE;
964 }
965
966 //printf("[%s][%d] timeout!\n",__FUNCTION__,__LINE__);
967
968 return FALSE;
969 }
970
971 #endif //SECURE_PVR_ENABLE
972
_TSP_DrvHal_PadMapping(TSP_TSPad eTSPad)973 static TSP_TS_PAD _TSP_DrvHal_PadMapping(TSP_TSPad eTSPad)
974 {
975 switch (eTSPad)
976 {
977 case E_TSP_TS_PAD0:
978 return E_TSP_TS_PAD_EXT0;
979 case E_TSP_TS_PAD1:
980 return E_TSP_TS_PAD_EXT1;
981 case E_TSP_TS_PAD2:
982 return E_TSP_TS_PAD_EXT2;
983 case E_TSP_TS_PAD3:
984 return E_TSP_TS_PAD_EXT3;
985 case E_TSP_TS_PAD4:
986 return E_TSP_TS_PAD_EXT4;
987 case E_TSP_TS_PAD5:
988 return E_TSP_TS_PAD_EXT5;
989 case E_TSP_TS_PAD6:
990 return E_TSP_TS_PAD_EXT6;
991 case E_TSP_TS_PAD7:
992 return E_TSP_TS_PAD_EXT7;
993 case E_TSP_TS_PAD0_3WIRE:
994 return HAL_TSP_3WirePadMapping(0);
995 case E_TSP_TS_PAD1_3WIRE:
996 return HAL_TSP_3WirePadMapping(1);
997 case E_TSP_TS_PAD2_3WIRE:
998 return HAL_TSP_3WirePadMapping(2);
999 case E_TSP_TS_PAD3_3WIRE:
1000 return HAL_TSP_3WirePadMapping(3);
1001 case E_TSP_TS_PAD4_3WIRE:
1002 return HAL_TSP_3WirePadMapping(4);
1003 case E_TSP_TS_PAD5_3WIRE:
1004 return HAL_TSP_3WirePadMapping(5);
1005 case E_TSP_TS_PAD6_3WIRE:
1006 return HAL_TSP_3WirePadMapping(6);
1007 case E_TSP_TS_PAD7_3WIRE:
1008 return HAL_TSP_3WirePadMapping(7);
1009 case E_TSP_TS_DEMOD0:
1010 return E_TSP_TS_PAD_INTER0;
1011 case E_TSP_TS_DEMOD1:
1012 return E_TSP_TS_PAD_INTER1;
1013 case E_TSP_TS_PAD_TSO0:
1014 return E_TSP_TS_PAD_TSOUT0;
1015 case E_TSP_TS_PAD_TSO1:
1016 return E_TSP_TS_PAD_TSOUT1;
1017 #ifdef TSIO_ENABLE
1018 case E_TSP_TS_PAD_TSIO0:
1019 return E_TSP_TS_PAD_TSIOOUT0;
1020 #endif
1021
1022 default:
1023 return E_TSP_TS_PAD_INVALID;
1024 }
1025 }
1026
_TSP_DrvHal_TSIFMapping(TSP_TSIF eTSIF)1027 static TSP_HAL_TSIF _TSP_DrvHal_TSIFMapping(TSP_TSIF eTSIF)
1028 {
1029 switch(eTSIF)
1030 {
1031 case E_TSP_TSIF_0:
1032 return E_TSP_HAL_TSIF_0;
1033 case E_TSP_TSIF_1:
1034 return E_TSP_HAL_TSIF_1;
1035 case E_TSP_TSIF_2:
1036 return E_TSP_HAL_TSIF_2;
1037 case E_TSP_TSIF_3:
1038 return E_TSP_HAL_TSIF_3;
1039 case E_TSP_TSIF_4:
1040 return E_TSP_HAL_TSIF_4;
1041 case E_TSP_TSIF_5:
1042 return E_TSP_HAL_TSIF_5;
1043 case E_TSP_TSIF_6:
1044 return E_TSP_HAL_TSIF_6;
1045 case E_TSP_TSIF_PVR0:
1046 return E_TSP_HAL_TSIF_PVR0;
1047 case E_TSP_TSIF_PVR1:
1048 return E_TSP_HAL_TSIF_PVR1;
1049 case E_TSP_TSIF_PVR2:
1050 return E_TSP_HAL_TSIF_PVR2;
1051 case E_TSP_TSIF_PVR3:
1052 return E_TSP_HAL_TSIF_PVR3;
1053 default:
1054 return E_TSP_HAL_TSIF_INVALID;
1055 }
1056 }
1057
_TSP_DrvHal_FltSrcMapping(MS_U32 u32FltSrc)1058 TSP_PIDFLT_SRC _TSP_DrvHal_FltSrcMapping(MS_U32 u32FltSrc)
1059 {
1060 TSP_PIDFLT_SRC ePidFltSrc = E_TSP_PIDFLT_INVALID;
1061
1062 switch(u32FltSrc)
1063 {
1064 case E_TSP_FLT_SRC_LIVE0:
1065 ePidFltSrc = E_TSP_PIDFLT_LIVE0;
1066 break;
1067 case E_TSP_FLT_SRC_LIVE1:
1068 ePidFltSrc = E_TSP_PIDFLT_LIVE1;
1069 break;
1070 case E_TSP_FLT_SRC_LIVE2:
1071 ePidFltSrc = E_TSP_PIDFLT_LIVE2;
1072 break;
1073 case E_TSP_FLT_SRC_LIVE3:
1074 ePidFltSrc = E_TSP_PIDFLT_LIVE3;
1075 break;
1076 case E_TSP_FLT_SRC_FILE0:
1077 ePidFltSrc = E_TSP_PIDFLT_FILE0;
1078 break;
1079 case E_TSP_FLT_SRC_FILE1:
1080 ePidFltSrc = E_TSP_PIDFLT_FILE1;
1081 break;
1082 case E_TSP_FLT_SRC_FILE2:
1083 ePidFltSrc = E_TSP_PIDFLT_FILE2;
1084 break;
1085 case E_TSP_FLT_SRC_FILE3:
1086 ePidFltSrc = E_TSP_PIDFLT_FILE3;
1087 break;
1088 case E_TSP_FLT_SRC_LIVE4:
1089 case E_TSP_FLT_SRC_FILE4:
1090 ePidFltSrc = E_TSP_PIDFLT_LIVE4;
1091 break;
1092 case E_TSP_FLT_SRC_LIVE5:
1093 case E_TSP_FLT_SRC_FILE5:
1094 ePidFltSrc = E_TSP_PIDFLT_LIVE5;
1095 break;
1096 case E_TSP_FLT_SRC_LIVE6:
1097 case E_TSP_FLT_SRC_FILE6:
1098 ePidFltSrc = E_TSP_PIDFLT_LIVE6;
1099 break;
1100 default:
1101 TSP_DBG(E_TSP_DBG_WARNING, "[%04d] Filter input source is not assigned !! \n", __LINE__);
1102 ePidFltSrc = E_TSP_PIDFLT_LIVE0;
1103 break;
1104 }
1105
1106 return ePidFltSrc;
1107 }
1108
MDrv_TSP_FIFO_SourceSelect(TSP_TSId eTspTSid,TSP_FileMode eFifoType)1109 TSP_Result MDrv_TSP_FIFO_SourceSelect(TSP_TSId eTspTSid, TSP_FileMode eFifoType)
1110 {
1111 TSP_ENTRY();
1112
1113 TSP_DST_SEQ eTspDstSeq = E_TSP_DST_INVALID;
1114 TSP_SRC_SEQ eTspSrcSeq = E_TSP_SRC_INVALID;
1115
1116 switch (eFifoType)
1117 {
1118 case E_TSP_FILE_2_AUDIO:
1119 eTspDstSeq = E_TSP_DST_FIFO_AUDIO;
1120 break;
1121 case E_TSP_FILE_2_AUDIO2:
1122 eTspDstSeq = E_TSP_DST_FIFO_AUDIO2;
1123 break;
1124 case E_TSP_FILE_2_AUDIO3:
1125 eTspDstSeq = E_TSP_DST_FIFO_AUDIO3;
1126 break;
1127 case E_TSP_FILE_2_AUDIO4:
1128 eTspDstSeq = E_TSP_DST_FIFO_AUDIO4;
1129 break;
1130 case E_TSP_FILE_2_AUDIO5:
1131 eTspDstSeq = E_TSP_DST_FIFO_AUDIO5;
1132 break;
1133 case E_TSP_FILE_2_AUDIO6:
1134 eTspDstSeq = E_TSP_DST_FIFO_AUDIO6;
1135 break;
1136 case E_TSP_FILE_2_VIDEO:
1137 eTspDstSeq = E_TSP_DST_FIFO_VIDEO;
1138 break;
1139 case E_TSP_FILE_2_VIDEO3D:
1140 eTspDstSeq = E_TSP_DST_FIFO_VIDEO3D;
1141 break;
1142 case E_TSP_FILE_2_VIDEO3:
1143 eTspDstSeq = E_TSP_DST_FIFO_VIDEO3;
1144 break;
1145 case E_TSP_FILE_2_VIDEO4:
1146 eTspDstSeq = E_TSP_DST_FIFO_VIDEO4;
1147 break;
1148 case E_TSP_FILE_2_VIDEO5:
1149 eTspDstSeq = E_TSP_DST_FIFO_VIDEO5;
1150 break;
1151 case E_TSP_FILE_2_VIDEO6:
1152 eTspDstSeq = E_TSP_DST_FIFO_VIDEO6;
1153 break;
1154 case E_TSP_FILE_2_VIDEO7:
1155 eTspDstSeq = E_TSP_DST_FIFO_VIDEO7;
1156 break;
1157 case E_TSP_FILE_2_VIDEO8:
1158 eTspDstSeq = E_TSP_DST_FIFO_VIDEO8;
1159 break;
1160 default:
1161 TSP_OS_Print("[TSP Error][%04d] INVALID FIFO TYPE\n",__LINE__);
1162 TSP_RETURN(E_TSP_FAIL_INVALID);
1163 }
1164
1165 switch (eTspTSid)
1166 {
1167 case E_TSP_TSID_TSIF0:
1168 eTspSrcSeq = E_TSP_SRC_PKTDMX0;
1169 break;
1170 case E_TSP_TSID_TSIF1:
1171 eTspSrcSeq = E_TSP_SRC_PKTDMX1;
1172 break;
1173 case E_TSP_TSID_TSIF2:
1174 eTspSrcSeq = E_TSP_SRC_PKTDMX3;
1175 break;
1176 case E_TSP_TSID_TSIF3:
1177 eTspSrcSeq = E_TSP_SRC_PKTDMX4;
1178 break;
1179 case E_TSP_TSID_MMFI0:
1180 eTspSrcSeq = E_TSP_SRC_MMFI0;
1181 break;
1182 case E_TSP_TSID_MMFI1:
1183 eTspSrcSeq = E_TSP_SRC_MMFI1;
1184 break;
1185 default:
1186 TSP_OS_Print("[TSP Error][%04d] INVALID PKDMX SRC\n",__LINE__);
1187 TSP_RETURN(E_TSP_FAIL_INVALID);
1188 }
1189
1190 HAL_TSP_FIFO_SetSrc(eTspDstSeq, eTspSrcSeq);
1191
1192 if((eTspTSid == E_TSP_TSID_MMFI0) || (eTspTSid == E_TSP_TSID_MMFI1))
1193 {
1194 HAL_TSP_FIFO_BlockDis(eTspDstSeq, FALSE);
1195 }
1196 else
1197 {
1198 HAL_TSP_FIFO_BlockDis(eTspDstSeq, TRUE);
1199 }
1200
1201 TSP_RETURN(E_TSP_OK);
1202 }
1203
1204
_TSP_DrvHal_FltType2DstMapping(TSP_FltType eFltType)1205 static TSP_DST_SEQ _TSP_DrvHal_FltType2DstMapping(TSP_FltType eFltType)
1206 {
1207 TSP_DST_SEQ eRetDst = E_TSP_DST_INVALID;
1208
1209 switch(eFltType)
1210 {
1211 case E_TSP_FLT_FIFO_VIDEO ... E_TSP_FLT_FIFO_VIDEO8:
1212 eRetDst= (TSP_DST_SEQ)(E_TSP_DST_FIFO_VIDEO + (eFltType - E_TSP_FLT_FIFO_VIDEO));
1213 break;
1214 case E_TSP_FLT_FIFO_AUDIO ... E_TSP_FLT_FIFO_AUDIO6:
1215 eRetDst = (TSP_DST_SEQ)(E_TSP_DST_FIFO_AUDIO + (eFltType - E_TSP_FLT_FIFO_AUDIO));
1216 break;
1217 default:
1218 TSP_DBG(E_TSP_DBG_MUST, "[ERROR][%s][%d] UnSupport Flt Type!\n", __FUNCTION__, __LINE__);
1219 break;
1220 }
1221
1222 return eRetDst;
1223 }
1224
1225
1226 //-------------------------------------------------------------------------------------------------
1227 /// Reset audio/video fifo
1228 /// @param bReset \b IN 0->1:reset, 1->0:activate
1229 /// @return TSP_Result
1230 /// @note
1231 /// 0->1 reset, 1->0 activate
1232 //-------------------------------------------------------------------------------------------------
MDrv_TSP_FIFO_Reset(TSP_FltType eFltType,MS_BOOL bReset)1233 TSP_Result MDrv_TSP_FIFO_Reset(TSP_FltType eFltType, MS_BOOL bReset)
1234 {
1235 TSP_ENTRY();
1236
1237 TSP_DST_SEQ eDst = _TSP_DrvHal_FltType2DstMapping(eFltType);
1238
1239 HAL_TSP_FIFO_Reset(eDst, bReset);
1240
1241 TSP_RETURN(E_TSP_OK);
1242 }
1243
1244
MDrv_TSP_FIFO_BlockEnable(TSP_FltType eFltType,MS_BOOL bDisable)1245 TSP_Result MDrv_TSP_FIFO_BlockEnable(TSP_FltType eFltType, MS_BOOL bDisable)
1246 {
1247 TSP_ENTRY();
1248
1249 TSP_DST_SEQ eDst = _TSP_DrvHal_FltType2DstMapping(eFltType);
1250
1251 HAL_TSP_FIFO_BlockDis(eDst, bDisable);
1252
1253 TSP_RETURN(E_TSP_OK);
1254 }
1255
1256
1257 //-------------------------------------------------------------------------------------------------
1258 /// Reset audio/video fifo
1259 /// @param u32Level \b OUT 0:0-25%, 1:25-50%, 2:50-75%, 3:75-100%, 0xFFFFFFFF:N/A
1260 /// @return TSP_Result
1261 /// @note
1262 /// 0->1 reset, 1->0 activate
1263 //-------------------------------------------------------------------------------------------------
MDrv_TSP_FIFO_GetStatus(TSP_FltType eFltType,MS_U32 * pu32Level)1264 TSP_Result MDrv_TSP_FIFO_GetStatus(TSP_FltType eFltType, MS_U32 *pu32Level)
1265 {
1266 TSP_ENTRY();
1267
1268 eFltType &= E_TSP_FLT_FIFO_MASK;
1269
1270 TSP_DST_SEQ eDst = _TSP_DrvHal_FltType2DstMapping(eFltType);
1271
1272 *pu32Level = HAL_TSP_FIFO_GetStatus(eDst);
1273 if (*pu32Level == HAL_TSP_RET_NULL)
1274 {
1275 TSP_RETURN(E_TSP_FAIL);
1276 }
1277
1278 TSP_RETURN(E_TSP_OK);
1279 }
1280
MDrv_TSP_FIFO_Overflow_Status(TSP_FltType eFltType,MS_BOOL * pbOverflow)1281 TSP_Result MDrv_TSP_FIFO_Overflow_Status(TSP_FltType eFltType, MS_BOOL *pbOverflow)
1282 {
1283 *pbOverflow = FALSE;
1284
1285 TSP_ENTRY();
1286 *pbOverflow = HAL_TSP_FIFO_Overflow(eFltType);
1287 TSP_RETURN(E_TSP_OK);
1288 }
1289
MDrv_TSP_AU_BD_Mode_Enable(MS_BOOL bEnable)1290 TSP_Result MDrv_TSP_AU_BD_Mode_Enable(MS_BOOL bEnable)
1291 {
1292 TSP_ENTRY();
1293
1294 HAL_TSP_BD_AUD_En(0, bEnable);
1295
1296 TSP_RETURN(E_TSP_OK);
1297 }
1298
_TSP_Path_Alloc(DRV_TSP_PATH_TYPE eResType,MS_U32 * pu32PathId)1299 static TSP_Result _TSP_Path_Alloc(DRV_TSP_PATH_TYPE eResType, MS_U32 *pu32PathId)
1300 {
1301 if( (eResType == E_DRV_TSP_PATH_LIVE) || (eResType == E_DRV_TSP_PATH_FILE) )
1302 {
1303 TSP_TSIF eTSIF = E_TSP_TSIF_INVALID;
1304 MS_U32 u32PhyTspPath = 0;
1305
1306 *pu32PathId = (MS_U32)-1;
1307 for(eTSIF = E_TSP_TSIF_0; eTSIF < TSP_TSIF_NUM; eTSIF++)
1308 {
1309 //@Note: Currently, TSP_TSIF for live-in & TSP HW path are 1-1 mapping, and
1310 // TSP_TSIF for file-in & TSP HW path are also 1-1 mapping
1311 TSP_HAL_TSIF eHalTSIF = _TSP_DrvHal_TSIFMapping(eTSIF);
1312 u32PhyTspPath = HAL_TSP_TsifMapping(eHalTSIF, (eResType == E_DRV_TSP_PATH_FILE));
1313
1314 if(_ptsp_res->_stTspPathState[u32PhyTspPath].bUsed == FALSE)
1315 {
1316 _ptsp_res->_stTspPathState[u32PhyTspPath].bUsed = TRUE;
1317 *pu32PathId = (MS_U32) eTSIF;
1318 return E_TSP_OK;
1319 }
1320 }
1321 }
1322
1323 return E_TSP_FAIL;
1324 }
1325
_TSP_Path_Free(DRV_TSP_PATH_TYPE eResType,TSP_TSIF ePath)1326 static TSP_Result _TSP_Path_Free(DRV_TSP_PATH_TYPE eResType, TSP_TSIF ePath)
1327 {
1328 if( (eResType == E_DRV_TSP_PATH_LIVE) || (eResType == E_DRV_TSP_PATH_FILE) )
1329 {
1330 MS_U32 u32PhyTspPath = 0;
1331
1332 TSP_HAL_TSIF eHalTSIF = _TSP_DrvHal_TSIFMapping(ePath);
1333 u32PhyTspPath = HAL_TSP_TsifMapping(eHalTSIF, (eResType == E_DRV_TSP_PATH_FILE));
1334
1335 if(_ptsp_res->_stTspPathState[u32PhyTspPath].bUsed == FALSE)
1336 return E_TSP_FAIL;
1337
1338 _ptsp_res->_stTspPathState[u32PhyTspPath].bUsed = FALSE;
1339 return E_TSP_OK;
1340 }
1341
1342 return E_TSP_FAIL;
1343 }
1344
_TSP_STC_Alloc(MS_U32 * pu32EngId)1345 static TSP_Result _TSP_STC_Alloc(MS_U32 *pu32EngId)
1346 {
1347 MS_U32 i;
1348 *pu32EngId = 0xFFFFFFFF;
1349
1350 for(i = 0; i < STC_ENG_NUM; i++)
1351 {
1352 if(_ptsp_res->_stTspStcState[i].bUsed == FALSE)
1353 {
1354 _ptsp_res->_stTspStcState[i].bUsed = TRUE;
1355 *pu32EngId = i;
1356 break;
1357 }
1358 }
1359
1360 if(*pu32EngId == 0xFFFFFFFF)
1361 return E_TSP_FAIL;
1362
1363 return E_TSP_OK;
1364 }
1365
_TSP_STC_Free(MS_U32 u32EngId)1366 static TSP_Result _TSP_STC_Free(MS_U32 u32EngId)
1367 {
1368 if(_ptsp_res->_stTspStcState[u32EngId].bUsed == FALSE)
1369 return E_TSP_FAIL;
1370
1371 _ptsp_res->_stTspStcState[u32EngId].bUsed = FALSE;
1372 _ptsp_res->_stTspStcState[u32EngId].u32PcrFltId = 0xFFFFFFFF;
1373
1374 return E_TSP_OK;
1375 }
1376
_TSP_STC_SetPcrFlt(MS_U32 u32EngId,MS_U32 u32PcrFltId)1377 static TSP_Result _TSP_STC_SetPcrFlt(MS_U32 u32EngId, MS_U32 u32PcrFltId)
1378 {
1379 _ptsp_res->_stTspStcState[u32EngId].u32PcrFltId = u32PcrFltId;
1380
1381 return E_TSP_OK;
1382 }
1383
_TSP_PcrId_To_StcId(MS_U32 u32PcrFltId,MS_U32 * pu32EngId)1384 static TSP_Result _TSP_PcrId_To_StcId(MS_U32 u32PcrFltId,MS_U32 *pu32EngId)
1385 {
1386 MS_U32 i;
1387
1388 *pu32EngId = 0xFFFFFFFF;
1389
1390 for(i = 0; i < STC_ENG_NUM; i++)
1391 {
1392 if((_ptsp_res->_stTspStcState[i].u32PcrFltId == u32PcrFltId)
1393 && (_ptsp_res->_stTspStcState[i].bUsed == TRUE))
1394 {
1395 *pu32EngId = i;
1396 return E_TSP_OK;
1397 }
1398 }
1399
1400 return E_TSP_FAIL;
1401 }
1402
1403 // initilize or reset the FLT to be initial state
1404 // PID and ctrls are clear
_TSP_FLT_Init(MS_U32 u32FltId)1405 static void _TSP_FLT_Init(MS_U32 u32FltId)
1406 {
1407 static MS_U8 u8Mask[TSP_FILTER_DEPTH] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1408 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
1409 static MS_U8 u8NMask[TSP_FILTER_DEPTH] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
1410 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
1411 #if HW_PCRFLT_ENABLE
1412
1413 if ((_ptsp_res->_tspInfo.FltType[u32FltId]& E_TSP_FLT_USER_MASK)== E_TSP_FLT_USER_PCR)
1414 {
1415 MS_U32 Pcr_H, Pcr;
1416 MS_U32 u32PcrId;
1417
1418 if ((u32FltId >= TSP_PCRFLT_GET_ID(0)) && (u32FltId <= HAL_TSP_PCRFLT_GET_ID(TSP_PCRFLT_NUM - 1)))
1419 {
1420 u32PcrId = u32FltId - _tspFltIdMap.u32PcrFltId_Start;
1421
1422 HAL_TSP_PcrFlt_SetPid(u32PcrId, TSP_PID_NULL);
1423 HAL_TSP_PcrFlt_SetSrc(u32PcrId, E_TSP_PCR_SRC_INVALID);
1424 #ifdef MERGE_STR_SUPPORT
1425 HAL_TSP_PcrFlt_SetSrcId(u32PcrId, (E_TSP_FLT_SRCID_0 & E_TSP_FLT_SRCID_MASK) >> E_TSP_FLT_SRCID_SHIFT);
1426 #endif // end MERGE_STR_SUPPORT
1427 HAL_TSP_PcrFlt_Enable(u32PcrId, FALSE);
1428 HAL_TSP_PcrFlt_ClearInt(u32PcrId);
1429 HAL_TSP_INT_Disable(HAL_TSP_PcrFlt_GetIntMask(u32PcrId));
1430
1431 //always read PCR after PCR interrupt has been disabled or cleared to avoid that interrupt's not trggering again.
1432 HAL_TSP_PcrFlt_GetPcr(u32PcrId, &Pcr_H, &Pcr);
1433 }
1434 else
1435 {
1436 TSP_DBG(E_TSP_DBG_MUST,"[%s][%d] Incorrect PCR filter ID !!\n",__FUNCTION__,__LINE__);
1437 return;
1438 }
1439 }
1440 else
1441
1442 #endif
1443 {
1444 HAL_TSP_PidFlt_SetPid(u32FltId, TSP_PID_NULL);
1445 HAL_TSP_PidFlt_SetFltIn(u32FltId, TSP_PIDFLT_TSIF_MAX); // default MAX
1446 HAL_TSP_PidFlt_SetFltOut(u32FltId, TSP_PIDFLT_OUT_NONE);
1447 HAL_TSP_PidFlt_SetSecFlt(u32FltId, u32FltId); // PIDFLT <-> SECFLT
1448
1449 _ptsp_res->_tspInfo.Flt2Buf[u32FltId] = TSP_FLT2BUF_NULL;
1450 }
1451
1452 _ptsp_res->_tspInfo.Pid[u32FltId] = TSP_PID_NULL ;
1453 _ptsp_res->_tspInfo.FltState[u32FltId] = E_TSP_FLT_STATE_FREE;
1454 _ptsp_res->_tspInfo.OwnerId[u32FltId] = E_TSP_ID_NULL;
1455
1456 // @NOTE section filters may be less than PID filters
1457 if(u32FltId < _tspFltIdMap.u32SecFltId_End)
1458 {
1459 REG_SecFlt * pSecFlt = &(_REGSec->Flt[u32FltId]);
1460
1461 HAL_TSP_SecFlt_ClrCtrl(pSecFlt);
1462 HAL_TSP_SecFlt_SelSecBuf(pSecFlt, TSP_SECFLT_SECBUF_MAX); // default MAX
1463 HAL_TSP_SecFlt_SetMask(pSecFlt, u8Mask);
1464 HAL_TSP_SecFlt_SetNMask(pSecFlt, u8NMask);
1465 HAL_TSP_SecFlt_SetType(pSecFlt, TSP_SECFLT_USER_NULL); // default SECTION
1466
1467 _ptsp_res->_tspInfo.FltMode[u32FltId] = E_TSP_FLT_MODE_CONTI;
1468 _ptsp_res->_tspInfo.FltEvent[u32FltId] = E_TSP_EVENT_DATA_IDLE;
1469 _ptsp_res->_tspInfo.FltCallback[u32FltId] = NULL;
1470 }
1471
1472 }
1473
_TSP_FLT_Free(MS_U32 u32FltId)1474 static void _TSP_FLT_Free(MS_U32 u32FltId)
1475 {
1476 if (_tspFltIdMap.u32SecFltId_End > u32FltId)
1477 {
1478 HAL_TSP_SecFlt_Free(&(_REGSec->Flt[u32FltId]));
1479 TSP_FLAG_ClrModeFlags(u32FltId);
1480 }
1481
1482 _ptsp_res->_tspInfo.OwnerId[u32FltId] = E_TSP_ID_NULL;
1483 _ptsp_res->_tspInfo.FltState[u32FltId] = E_TSP_FLT_STATE_FREE;
1484 _ptsp_res->_tspInfo.FltType[u32FltId] = E_TSP_FLT_USER_NULL;
1485
1486 }
1487
1488 // Disable FLT output (SEC, AUD, VID)
1489 // NOTE: other bypass route to ECM/EMM/REC/etc. is not disable.
_TSP_FLT_Disable(MS_U32 u32FltId)1490 static void _TSP_FLT_Disable(MS_U32 u32FltId)
1491 {
1492 #if 1
1493
1494 #if HW_PCRFLT_ENABLE
1495
1496 if ((_ptsp_res->_tspInfo.FltType[u32FltId]& E_TSP_FLT_USER_MASK)== E_TSP_FLT_USER_PCR)
1497 {
1498 MS_U32 Pcr_H, Pcr;
1499 MS_U32 u32PcrId;
1500
1501 if ((u32FltId >= TSP_PCRFLT_GET_ID(0)) && (u32FltId <= HAL_TSP_PCRFLT_GET_ID(TSP_PCRFLT_NUM - 1)))
1502 {
1503 u32PcrId = u32FltId - _tspFltIdMap.u32PcrFltId_Start;
1504
1505 //HAL_TSP_PcrFlt_SetSrc(u32PcrId, E_TSP_PCR_SRC_INVALID);
1506 HAL_TSP_PcrFlt_Enable(u32PcrId, FALSE);
1507
1508 HAL_TSP_PcrFlt_ClearInt(u32PcrId);
1509 HAL_TSP_INT_Disable(HAL_TSP_PcrFlt_GetIntMask(u32PcrId));
1510
1511 //always read PCR after PCR interrupt has been disabled or cleared to avoid that interrupt's not trggering again.
1512 HAL_TSP_PcrFlt_GetPcr(u32PcrId, &Pcr_H, &Pcr);
1513 }
1514 else
1515 {
1516 TSP_DBG(E_TSP_DBG_MUST,"[%s][%d] Incorrect PCR filter ID !!\n",__FUNCTION__,__LINE__);
1517 return;
1518 }
1519 }
1520 else
1521
1522 #endif
1523 {
1524 HAL_TSP_PidFlt_SetFltOut(u32FltId, TSP_PIDFLT_OUT_NONE); //@FIXME do we have to clear pvr and section out at this function?
1525 }
1526
1527 _ptsp_res->_tspInfo.FltState[u32FltId] &= (TSP_FltState)(~E_TSP_FLT_STATE_ENABLE);
1528
1529 #else
1530 HAL_TSP_PidFlt_SetFltOut(&(_REGPid->Flt[u32FltId]), TSP_PIDFLT_OUT_NULL);
1531 if ((_ptsp_res->_tspInfo.FltType[u32FltId]& E_TSP_FLT_USER_MASK)== E_TSP_FLT_USER_PCR)
1532 {
1533 HAL_TSP_SecFlt_PcrReset(&(_REGSec->Flt[u32FltId]));
1534 HAL_TSP_PCRFlt_SetPid(0x1FFF,false);
1535 HAL_TSP_PCRFlt_ClearInt();
1536 HAL_TSP_INT_Disable(TSP_HWINT2_PCR_UPD << 8 );
1537 }
1538 _ptsp_res->_tspInfo.FltState[u32FltId] &= (TSP_FltState)(~E_TSP_FLT_STATE_ENABLE);
1539 #endif
1540
1541
1542 /*
1543 //[Note] Delay for VQ flush, open it if necessary.
1544 #if defined (MSOS_TYPE_LINUX_KERNEL)
1545 mdelay(5);
1546 #elif defined (MSOS_TYPE_ECOS) || defined(MSOS_TYPE_UCOS)
1547 #else
1548 MsOS_DelayTask(5);
1549 #endif
1550 */
1551
1552 }
1553
1554
_TSP_SEC_Init(MS_U32 u32BufId)1555 static void _TSP_SEC_Init(MS_U32 u32BufId)
1556 {
1557 _ptsp_res->_tspInfo.MulFlt2Buf[u32BufId] = 0 ; // Multi Filter to buffer count.
1558 _ptsp_res->_tspInfo.Buf2Flt[u32BufId] = TSP_BUF2FLT_NULL;
1559 HAL_TSP_SecBuf_SetBuf(&(_REGBuf->Buf[u32BufId]), 0, 0);
1560 HAL_TSP_SecBuf_Reset(&(_REGBuf->Buf[u32BufId]));
1561 }
1562
1563
_TSP_SEC_Free(MS_U32 u32BufId)1564 static void _TSP_SEC_Free(MS_U32 u32BufId)
1565 {
1566 HAL_TSP_SecBuf_Free(&(_REGBuf->Buf[u32BufId]));
1567 _TSP_RemoveSecNotifyId(u32BufId);
1568 _ptsp_res->_tspInfo.BufState[u32BufId] = E_TSP_FLT_STATE_FREE;
1569 }
1570
_TSP_PROC_CrcErr(MS_U32 u32FltId,TSP_Event * pEvent)1571 static TSP_Result _TSP_PROC_CrcErr(MS_U32 u32FltId, TSP_Event *pEvent)
1572 {
1573 static TSP_EventMsg msg;
1574 MS_U32 flags; // dummy
1575
1576 TSP_FLAG_GetCrcErr(u32FltId, &flags, TSP_OS_EVENT_OR_CLEAR); // if TSP not enable
1577
1578 if (pEvent)
1579 {
1580 if ((_ptsp_res->_tspInfo.FltMode[u32FltId] & E_TSP_FLT_MODE_CRCCHK) ||
1581 (_ptsp_res->_tspInfo.FltMode[u32FltId] & E_TSP_FLT_MODE_AUTO_CRCCHK))
1582 {
1583 *pEvent = (TSP_Event) E_TSP_EVENT_SEC_CRCERROR;
1584 }
1585 }
1586 else
1587 {
1588 if (!(_ptsp_res->_tspInfo.FltState[u32FltId] & E_TSP_FLT_STATE_ENABLE)) // if TSP not enable
1589 {
1590 return E_TSP_FAIL;
1591 }
1592 if ((_ptsp_res->_tspInfo.FltEvent[u32FltId] & E_TSP_EVENT_SEC_CRCERROR) &&
1593 (_ptsp_res->_tspInfo.FltCallback[u32FltId]) )
1594 {
1595 msg.FltInfo = (_ptsp_res->_tspInfo.OwnerId[u32FltId] << TSP_MSG_ENGID_SHFT) | (u32FltId << TSP_MSG_FLTID_SHFT);
1596 TSP_DBG_TASK();
1597 _ptsp_res->_tspInfo.FltCallback[u32FltId](E_TSP_EVENT_SEC_CRCERROR, &msg);
1598 TSP_DBG_TASK();
1599 }
1600 }
1601
1602 return E_TSP_OK;
1603 }
1604
1605
1606
1607
_TSP_PROC_SecOvf(MS_U32 u32FltId,TSP_Event * pEvent)1608 static TSP_Result _TSP_PROC_SecOvf(MS_U32 u32FltId, TSP_Event *pEvent)
1609 {
1610 static TSP_EventMsg msg;
1611 MS_U32 flags; // dummy
1612
1613 //(POLL) Check any possible filter should be disabled
1614 //(TASK) Check only overflowed filter and to disable
1615 TSP_LOCK(); //{
1616 if (HAL_TSP_PidFlt_GetFltOutput(&(_REGPid1->Flt[u32FltId])) & TSP_PIDFLT_OUT_SECFLT)
1617 {
1618 _TSP_FLT_Disable(u32FltId);
1619 }
1620 TSP_FLAG_SetOvfRst(u32FltId);
1621 TSP_UNLOCK(); //}
1622
1623 TSP_FLAG_GetFltDis(u32FltId, &flags, TSP_OS_EVENT_OR_CLEAR);
1624 //[Eddie]Clear Event at Filter Enable , Try to avoid redundant Overflow event.
1625 // Driver will not call overflow call back until previous overflow have been serverd(Reset Buffer)
1626 //TSP_FLAG_GetSecOvf(u32FltId, &flags, TSP_OS_EVENT_OR_CLEAR);
1627
1628
1629 if (pEvent ) // MDrv_TSP_Proc -> _TSP_Poll_Proc
1630 {
1631 *pEvent = (MS_U32)E_TSP_EVENT_BUF_OVERFLOW;
1632 }
1633 else
1634 {
1635 // required event callback
1636 if ( (_ptsp_res->_tspInfo.FltEvent[u32FltId] & E_TSP_EVENT_BUF_OVERFLOW) &&
1637 (_ptsp_res->_tspInfo.FltCallback[u32FltId]) )
1638 {
1639 msg.FltInfo = (_ptsp_res->_tspInfo.OwnerId[u32FltId] << TSP_MSG_ENGID_SHFT) | (u32FltId << TSP_MSG_FLTID_SHFT);
1640
1641 TSP_DBG_TASK();
1642 _ptsp_res->_tspInfo.FltCallback[u32FltId](E_TSP_EVENT_BUF_OVERFLOW, &msg);
1643 TSP_DBG_TASK();
1644 }
1645 }
1646
1647 return E_TSP_OK;
1648 }
1649
1650
MDrv_TSP_SEC_Update(MS_U32 u32SecFltId)1651 void MDrv_TSP_SEC_Update( MS_U32 u32SecFltId)
1652 {
1653 TSP_FLAG_SetSecRdy(u32SecFltId);
1654 }
1655
1656
_TSP_PROC_SecRdy(MS_U32 u32FltId,TSP_Event * pEvent)1657 static TSP_Result _TSP_PROC_SecRdy(MS_U32 u32FltId, TSP_Event *pEvent)
1658 {
1659 static TSP_EventMsg msg;
1660
1661 MS_U16 bufid;
1662 MS_BOOL data;
1663 MS_U32 flags;
1664
1665 /*
1666 if (E_TSP_EVENT_CB_POLL == u32CbOpt)
1667 {
1668 TSP_GetEvent(u32Events, TSP_EVENT_SECTION_POLL, TSP_OS_EVENT_OR_CLEAR, 0);
1669 }
1670 else
1671 {
1672 }
1673 */
1674
1675 TSP_FLAG_GetSecRdy(u32FltId, &flags, TSP_OS_EVENT_OR_CLEAR); // clear for next incoming
1676
1677 TSP_LOCK();
1678 bufid = HAL_TSP_SecFlt_GetSecBuf(&(_REGSec->Flt[u32FltId]));
1679
1680 #if 1
1681 if ((_ptsp_res->_tspInfo.FltState[u32FltId] == E_TSP_FLT_STATE_FREE) || (bufid != _ptsp_res->_tspInfo.Flt2Buf[u32FltId]))
1682 {
1683 for(flags = 0 ; flags < 10 ; flags ++)
1684 TSP_OS_Print("[TSP Error][%04d] u32FltId:%u eFltType:%08X Pid:%08X, FltStatus = %08X ,Mode = %08X , Event =%08X , AllMode= %08X ,Pevent = %08X,HwBufId %d != tspInfo Bufid %d\n",
1685 __LINE__,
1686 (unsigned int)u32FltId,
1687 (unsigned int)(_ptsp_res->_tspInfo.FltType[u32FltId]),
1688 (unsigned int)_ptsp_res->_tspInfo.Pid[u32FltId],
1689 (unsigned int)(_ptsp_res->_tspInfo.FltState[u32FltId]),
1690 (unsigned int)(_ptsp_res->_tspInfo.FltMode[u32FltId]),
1691 (unsigned int)(_ptsp_res->_tspInfo.FltEvent[u32FltId]),
1692 (unsigned int)_s32ModeFlags[u32FltId],
1693 (unsigned int)*pEvent,
1694 bufid,
1695 (unsigned int)_ptsp_res->_tspInfo.Flt2Buf[u32FltId]);
1696 //while(1);
1697 TSP_UNLOCK();
1698
1699 return E_TSP_FAIL;
1700 }
1701
1702 #else
1703
1704 TSP_CHECK_UNLOCK(bufid == _ptsp_res->_tspInfo.Flt2Buf[u32FltId], "[TSP Error][%04d] u32FltId:%u eFltType:%08X Pid:%08X, FltStatus = %08X ,Mode = %08X , Event =%08X , AllMode= %08lX ,Pevent = %08lX,HwBufId %ld != tspInfo Bufid %ld\n",
1705 __LINE__,
1706 (unsigned int)u32FltId,
1707 (unsigned int)(_ptsp_res->_tspInfo.FltType[u32FltId]),
1708 (unsigned int)_ptsp_res->_tspInfo.Pid[u32FltId],
1709 (unsigned int)(_ptsp_res->_tspInfo.FltState[u32FltId]),
1710 (unsigned int)(_ptsp_res->_tspInfo.FltMode[u32FltId]),
1711 (unsigned int)(_ptsp_res->_tspInfo.FltEvent[u32FltId]),
1712 (MS_U32)_s32ModeFlags,
1713 (MS_U32)pEvent,
1714 (MS_U32)bufid,
1715 _ptsp_res->_tspInfo.Flt2Buf[u32FltId]);
1716 #endif
1717
1718 data = (HAL_TSP_SecBuf_GetRead(&(_REGBuf->Buf[bufid])) != HAL_TSP_SecBuf_GetWrite(&(_REGBuf->Buf[bufid]))) ? TRUE : FALSE;
1719 TSP_UNLOCK();
1720
1721
1722 if (data)
1723 {
1724 if (pEvent) // POLL mode
1725 {
1726 *pEvent = (TSP_Event)E_TSP_EVENT_DATA_READY;
1727 // if TSP not enable
1728 if (TSP_FLAG_GetSecOvf(u32FltId,&flags,TSP_OS_EVENT_OR)||TSP_FLAG_GetCrcErr(u32FltId,&flags,TSP_OS_EVENT_OR))
1729 {
1730 return E_TSP_FAIL;
1731 }
1732 }
1733 else
1734 {
1735 if (!(_ptsp_res->_tspInfo.FltState[u32FltId] & E_TSP_FLT_STATE_ENABLE)) // if TSP not enable
1736 {
1737 return E_TSP_FAIL;
1738 }
1739 if ((_ptsp_res->_tspInfo.FltEvent[u32FltId] & E_TSP_EVENT_DATA_READY) &&
1740 (_ptsp_res->_tspInfo.FltCallback[u32FltId]) )
1741 {
1742 msg.FltInfo = (_ptsp_res->_tspInfo.OwnerId[u32FltId] << TSP_MSG_ENGID_SHFT) | (u32FltId << TSP_MSG_FLTID_SHFT);
1743
1744 TSP_DBG_TASK();
1745 _ptsp_res->_tspInfo.FltCallback[u32FltId](E_TSP_EVENT_DATA_READY, &msg);
1746 TSP_DBG_TASK();
1747 }
1748 }
1749 }
1750
1751 //(POLL) Check any possible filter should be disabled
1752 //(TASK) Check only one-shot filter and to disable
1753 if (TSP_FLAG_GetFltDis(u32FltId, &flags, TSP_OS_EVENT_OR_CLEAR))
1754 {
1755 TSP_LOCK();
1756 _TSP_FLT_Disable(u32FltId);
1757 TSP_UNLOCK();
1758 }
1759
1760 if (data)
1761 {
1762 return E_TSP_OK;
1763 }
1764 return E_TSP_FAIL; // no data valid || not enable
1765 }
1766
_TSP_Proc_Pvr(MS_U32 u32Events,MS_U32 u32CbOpt)1767 static void _TSP_Proc_Pvr(MS_U32 u32Events, MS_U32 u32CbOpt)
1768 {
1769 TSP_DBG(E_TSP_DBG_MUST, "%s Wait implementation\n", __FUNCTION__);
1770 }
1771
_TSP_ISR_Proc(MS_U32 u32Events)1772 static void _TSP_ISR_Proc(MS_U32 u32Events)
1773 {
1774 MS_U32 fltid = TSP_SECFLT_NUM, flags = 0,ModeMask,dummy,BaseFlt;
1775 int i;
1776
1777 TSP_DBG_TASK();
1778
1779 #if __LEGACY__
1780 if ( (TSP_EVENT_PVR0_RDY_POLL | TSP_EVENT_PVR1_RDY_POLL) & u32Events)
1781 {
1782 _TSP_Proc_Pvr(u32Events, E_TSP_EVENT_CB_AUTO);
1783 }
1784 #endif
1785
1786
1787 // @NOTE: Jerry
1788 //
1789 // WATCH OUT!!
1790 // It has many issues before due to race condition between TSP_TASK and USER_TASK dealing with FLT_FREE
1791 // Please pay more attention on it
1792 //
1793 // Check all freeing filters
1794 if (u32Events & TSP_EVENT_FREEFLT)
1795 {
1796 for (i = 0; i < ((TSP_SECFLT_NUM+31)>>5); i++)
1797 {
1798 // Add to FREE list
1799 TSP_FLAG_GetModeFlags(i, ModeMask); // get CB mode Filter Mask
1800 TSP_FLAG_ModeFree(i, ModeMask,&flags, TSP_OS_EVENT_OR_CLEAR);
1801 while (flags)
1802 {
1803 BaseFlt = MAsm_CPU_GetTrailOne(flags);
1804 fltid = BaseFlt + (i<<5);
1805 TSP_LOCK();
1806 _TSP_FLT_Disable(fltid); // disable output
1807 TSP_UNLOCK();
1808 flags &= ~(1 << BaseFlt);
1809 TSP_FLAG_SetDone(fltid);
1810
1811 // Clear other filter activities
1812 TSP_FLAG_GetFltDis(fltid, &dummy, TSP_OS_EVENT_OR_CLEAR);
1813 TSP_FLAG_GetSecOvf(fltid, &dummy, TSP_OS_EVENT_OR_CLEAR);
1814 TSP_FLAG_GetSecRdy(fltid, &dummy, TSP_OS_EVENT_OR_CLEAR);
1815 }
1816 }
1817 }
1818
1819 MsOS_DelayTask(1);
1820 // Check all section avaiable filters
1821 if (u32Events & TSP_EVENT_SECTION)
1822 {
1823 // @TODO Jerry
1824 // Is it necessary to balance every filter priority even the event process is at TASK?
1825
1826 for (i = 0; i < ((TSP_SECFLT_NUM+31)>>5); i++)
1827 {
1828 TSP_FLAG_GetModeFlags(i, ModeMask); // get CB mode Filter Mask
1829 TSP_FLAG_ModeCrcErr(i, ModeMask,&flags, TSP_OS_EVENT_OR);
1830 while (flags)
1831 {
1832 //(POLL) Check any possible filter should be disabled
1833 //(TASK) Check only one-shot filter and to disable
1834 BaseFlt = MAsm_CPU_GetTrailOne(flags);
1835 fltid = BaseFlt + (i<<5);
1836
1837 // cause we serve free event before section rdy
1838 if ((_ptsp_res->_tspInfo.FltState[fltid] != E_TSP_FLT_STATE_FREE) && (_ptsp_res->_tspInfo.FltState[fltid] != E_TSP_FLT_STATE_ISR_FREE))
1839 {
1840 _TSP_PROC_CrcErr(fltid, NULL); // Pass events directly to callback
1841 }
1842 flags &= ~(1 << BaseFlt);
1843 }
1844
1845 TSP_FLAG_ModeSecRdy(i, ModeMask,&flags, TSP_OS_EVENT_OR);
1846 while (flags)
1847 {
1848 //(POLL) Check any possible filter should be disabled
1849 //(TASK) Check only one-shot filter and to disable
1850 BaseFlt = MAsm_CPU_GetTrailOne(flags);
1851 fltid = BaseFlt + (i<<5);
1852
1853 // cause we serve free event before section rdy
1854 if ((_ptsp_res->_tspInfo.FltState[fltid] != E_TSP_FLT_STATE_FREE) && (_ptsp_res->_tspInfo.FltState[fltid] != E_TSP_FLT_STATE_ISR_FREE))
1855 {
1856 _TSP_PROC_SecRdy(fltid, NULL); // Pass events directly to callback
1857 }
1858 flags &= ~(1 << BaseFlt);
1859 }
1860 TSP_FLAG_ModeSecOvf(i, ModeMask,&flags, TSP_OS_EVENT_OR);
1861 while (flags)
1862 {
1863 //(POLL) Check any possible filter should be disabled
1864 //(TASK) Check only overflowed filter and to disable
1865 BaseFlt = MAsm_CPU_GetTrailOne(flags);
1866 fltid = BaseFlt + (i<<5);
1867
1868 //if (_ptsp_res->_tspInfo.FltState[fltid] != E_TSP_FLT_STATE_FREE )
1869 if ((_ptsp_res->_tspInfo.FltState[fltid] != E_TSP_FLT_STATE_FREE) &&
1870 (_ptsp_res->_tspInfo.FltState[fltid] != E_TSP_FLT_STATE_ISR_FREE) &&
1871 (!TSP_FLAG_GetOvfRst(fltid)))
1872 {
1873 //TSP_OS_Print("TSP_FLT_OVFLOW [%ld] , Buf = %ld ,PID = %04lX \n",fltid, _ptsp_res->_tspInfo.Flt2Buf[fltid], _ptsp_res->_tspInfo.Pid[fltid]);
1874 _TSP_PROC_SecOvf(fltid, NULL); // Pass events directly to callback
1875 }
1876 flags &= ~(1 << BaseFlt );
1877 // Clear other filter activities
1878 TSP_FLAG_GetSecRdy(fltid, &dummy, TSP_OS_EVENT_OR_CLEAR); // Clear section ready also
1879 }
1880 MsOS_DelayTask(1);
1881 }
1882 }
1883
1884
1885 if (u32Events & TSP_EVENT_DISABLEFLT)//Disable Polling mode filter,CB mode filter disable at SecRdy or SecOvf
1886 {
1887 for (i = 0; i < ((TSP_SECFLT_NUM+31)>>5); i++)
1888 {
1889 TSP_FLAG_GetModeFlags(i, ModeMask); // get CB mode Filter Mask
1890 TSP_FLAG_ModeFltDis(i,~ModeMask, &flags ,TSP_OS_EVENT_OR_CLEAR); // Polling mode
1891 while (flags)
1892 {
1893 BaseFlt = MAsm_CPU_GetTrailOne(flags);
1894 fltid = BaseFlt + (i<<5);
1895 if (TSP_FLAG_GetFltDis(fltid, &dummy, TSP_OS_EVENT_OR_CLEAR))
1896 {
1897 TSP_LOCK();
1898 _TSP_FLT_Disable(fltid); // disable output
1899 TSP_UNLOCK();
1900 }
1901 flags &= ~(1 << BaseFlt);
1902 }
1903 }
1904 }
1905
1906 MsOS_DelayTask(1);
1907
1908
1909 }
1910
1911
_TSP_ISR_Task(void)1912 static void _TSP_ISR_Task(void)
1913 {
1914 MS_U32 events = 0;
1915
1916 while (_ptsp_res->_tspInfo.bISRTaskEn)
1917 {
1918 // @NOTE Jerry
1919 // Clear task events directly in case there has any incoming event before _TSP_ISR_Proc to clear
1920 TSP_GetEvent(_s32EventId, &events, TSP_TASK_EVENTS, TSP_OS_EVENT_OR_CLEAR, MSOS_WAIT_FOREVER);
1921
1922 if(events & TSP_EVENT_TASKEND)
1923 {
1924 break;
1925 }
1926
1927 _TSP_ISR_Proc(events);
1928 }
1929
1930 _s32_IsrTaskReturn = TRUE;
1931 }
1932
1933 #ifdef MSOS_TYPE_LINUX_KERNEL
_TSP_ISR(int irq,void * dev_id)1934 static irqreturn_t _TSP_ISR(int irq, void *dev_id)
1935 #else
1936 static void _TSP_ISR(void)
1937 #endif
1938 {
1939 MS_U32 hw_int;
1940 MS_U32 sw_int;
1941 MS_U32 Pcr_H, Pcr, Stc_H = 0, Stc = 0, u32Diff;
1942 MS_U32 i = 0;
1943
1944 _TSP_INT_LOCK();
1945 hw_int = HAL_TSP_INT_GetHW();
1946 //@TODO Need to check why call clr twice will cause one of pcr not work
1947 sw_int = HAL_TSP_INT_GetSW();
1948 _TSP_INT_UNLOCK();
1949
1950 #if __LEGACY__
1951 // Richard: @FIXME: do we need to detect all the int
1952 if (hw_int & TSP_HWINT_PVR)
1953 {
1954 if(_TSP_ChkPvrNotifyId(0))
1955 {
1956 TSP_SetEvent(_ptsp_res->_s32PvrEvtId, hw_int & TSP_HWINT_PVR); // Trigger task
1957 }
1958 else
1959 {
1960 hw_int &= ~TSP_HWINT_PVR;
1961 }
1962 }
1963 #endif
1964
1965 #if defined(OTV_ENABLE)
1966
1967 if ( hw_int & (TSP_HWINT2_OTV) )
1968 {
1969 MS_U32 u32OTV_Eng;
1970 MS_BOOL bInterrupted;
1971
1972 //TSP_DBG(E_TSP_DBG_TRACK, "[%s][%04d] ____TSP_OTV_ISR____ \n", __FUNCTION__, __LINE__);
1973
1974 for( u32OTV_Eng=0; u32OTV_Eng<TSP_OTVENG_NUM; u32OTV_Eng++)
1975 {
1976 if( MDrv_OTV_HWINT_Get(u32OTV_Eng, E_DRVOTV_HWINT_EVENT, &bInterrupted) )
1977 {
1978 if(bInterrupted)
1979 {
1980 MDrv_OTV_ISR(u32OTV_Eng, E_DRVOTV_HWINT_EVENT);
1981 MDrv_OTV_HWINT_Clear(u32OTV_Eng, E_DRVOTV_HWINT_EVENT);
1982 }
1983 }
1984
1985 if( MDrv_OTV_HWINT_Get(u32OTV_Eng, E_DRVOTV_HWINT_TIMER, &bInterrupted) )
1986 {
1987 if(bInterrupted)
1988 {
1989 MDrv_OTV_ISR(u32OTV_Eng, E_DRVOTV_HWINT_TIMER);
1990 MDrv_OTV_HWINT_Clear(u32OTV_Eng, E_DRVOTV_HWINT_TIMER);
1991 }
1992 }
1993
1994 }
1995
1996 // clear OTV HW Interrrupt
1997 HAL_TSP_INT_ClrHW(TSP_HWINT2_OTV);
1998
1999 }
2000 else
2001 {
2002 hw_int &= ~TSP_HWINT2_OTV;
2003 }
2004
2005 #endif
2006
2007
2008 /******************PCR INT*********************/
2009
2010 MS_U32 u32PcrDstSTC = 0;
2011 MS_U32 u32HwPcrIntMask = 0x0;
2012
2013
2014 #define STC_SYNTH_DEFAULT 0x28000000 // @F_TODO do we have to seperate 27M and 90K clk mode? plz define this value to right place...
2015
2016 for(i = 0; i < STC_ENG_NUM; i++)
2017 {
2018 u32HwPcrIntMask = HAL_TSP_PcrFlt_GetIntMask(i);
2019
2020 if (_TSP_ChkHwPcrNotifyId(i) && (hw_int & u32HwPcrIntMask))
2021 {
2022 _TSP_PcrId_To_StcId(TSP_PCRFLT_GET_ID(i), &u32PcrDstSTC);
2023
2024 _TSP_INT_LOCK();
2025 HAL_TSP_PcrFlt_ClearInt(i);
2026 _TSP_INT_UNLOCK();
2027
2028 //always read PCR after PCR interrupt has been disabled or cleared to avoid that interrupt's not trggering again.
2029 HAL_TSP_PcrFlt_GetPcr(i, &Pcr_H, &Pcr);
2030
2031 MS_U32 u32STC_Add_Offset = ( _ptsp_res->_u32_StcOffset[i].bAdd == TRUE) ? (Pcr + _ptsp_res->_u32_StcOffset[i].u32StcOffset) : (Pcr - _ptsp_res->_u32_StcOffset[i].u32StcOffset);
2032
2033 if(_ptsp_res->_u8_ResetPcr[i]>=2)
2034 {
2035 if(_ptsp_res->_u8_ResetPcr[i] == 3)
2036 {
2037 HAL_TSP_SetSTCSynth(u32PcrDstSTC, STC_SYNTH_DEFAULT);
2038 }
2039 //HAL_TSP_CMDQ_SetSTC(Pcr_H,Pcr);
2040
2041 if(_ptsp_res->_u32_StcUpdateCtrl[i].bEnable == TRUE)
2042 {
2043 HAL_TSP_STC64_Set(u32PcrDstSTC, Pcr_H,u32STC_Add_Offset);
2044
2045 if(_ptsp_res->_u32_StcUpdateCtrl[i].bUpdateOnce == TRUE)
2046 {
2047 _ptsp_res->_u32_StcUpdateCtrl[i].bEnable = FALSE;
2048 _ptsp_res->_u32_StcUpdateCtrl[i].bUpdateOnce = FALSE;
2049 }
2050 }
2051
2052 _ptsp_res->_u8_ResetPcr[i] = 0;
2053 _ptsp_res->_u32_PrevStcBase[i] = u32STC_Add_Offset;
2054 HAL_TSP_GetSTCSynth(u32PcrDstSTC, &_ptsp_res->_u32_PrevPllControl[i]);
2055 }
2056
2057 //HAL_TSP_CMDQ_GetSTC(&Stc_H, &Stc);
2058 HAL_TSP_STC64_Get(u32PcrDstSTC, &Stc_H, &Stc);
2059 if(( Stc - _ptsp_res->_u32_PrevStcBase[i]) > 0x4000)
2060 {
2061 //ULOGD("TSP", "STC_DIFF = %08X ==== \n\n",Stc - _ptsp_res->_u32_PrevStcBase);
2062 _ptsp_res->_u32_PrevStcBase[i] = Stc;
2063
2064 if(_ptsp_res->_u32_PrevStcBase[i] > u32STC_Add_Offset) // faster then PCR comming
2065 {
2066 u32Diff = _ptsp_res->_u32_PrevStcBase[i] - u32STC_Add_Offset;
2067 if( u32Diff <= 0x02) //pretty close
2068 {
2069 _ptsp_res->_u8_ResetPcr[i] = 0;
2070 }
2071 else if( u32Diff < 0x1000)
2072 {
2073 _ptsp_res->_u32_PrevPllControl[i] += ((u32Diff) >> 3 ); //now = error x alpha + prev
2074 HAL_TSP_SetSTCSynth(u32PcrDstSTC, _ptsp_res->_u32_PrevPllControl[i] + ((u32Diff)>>6)); //out = now + error x beta
2075 _ptsp_res->_u8_ResetPcr[i] = 0;
2076 //ULOGD("TSP", "======== Set STC CONTROL <++> %08X PCR/Diff = %08X/%08X \n",_ptsp_res->_u32_PrevPllControl[i] + ((_ptsp_res->_u32_PrevStcBase[i] - u32STC_Add_Offset)>>6),u32STC_Add_Offset,_ptsp_res->_u32_PrevStcBase[i]-u32STC_Add_Offset);
2077 }
2078 else
2079 {
2080 _ptsp_res->_u8_ResetPcr[i]++;
2081 }
2082 }
2083 else // slower or equal
2084 {
2085 u32Diff = u32STC_Add_Offset - _ptsp_res->_u32_PrevStcBase[i];
2086 if(( u32Diff) <= 0x02)
2087 {
2088 _ptsp_res->_u8_ResetPcr[i] = 0;
2089 }
2090 else if((u32Diff) < 0x1000)
2091 {
2092 _ptsp_res->_u32_PrevPllControl[i]-=((u32Diff)>> 3); //now = error x alpha + prev
2093 HAL_TSP_SetSTCSynth(u32PcrDstSTC, _ptsp_res->_u32_PrevPllControl[i] - (( u32Diff )>> 6)); //out = now + error x beta
2094 _ptsp_res->_u8_ResetPcr[i] = 0;
2095 //ULOGD("TSP", "======== Set STC CONTROL <--> %08X PCR/Diff = %08X/%08X \n",_ptsp_res->_u32_PrevPllControl[i] - ((u32STC_Add_Offset - _ptsp_res->_u32_PrevStcBase[i] )>>6),u32STC_Add_Offset,u32STC_Add_Offset-_ptsp_res->_u32_PrevStcBase[i] );
2096 }
2097 else
2098 {
2099 _ptsp_res->_u8_ResetPcr[i]++;
2100 }
2101 }
2102 }
2103 }// end pcr
2104 else
2105 {
2106 hw_int &=( ~u32HwPcrIntMask);
2107 }
2108 }
2109
2110 /**********************************************/
2111
2112
2113 if (sw_int & TSP_SWINT_CTRL_FIRE)
2114 {
2115 //MS_U32 engid;
2116 MS_U32 fltid;
2117 MS_U32 status;
2118 //REG_SecFlt* pFilter;
2119 MS_U32 dummy;
2120
2121 //engid = (sw_int & TSP_SWINT_INFO_ENG_MASK) >> TSP_SWINT_INFO_ENG_SHFT;
2122 fltid = (sw_int & TSP_SWINT_INFO_SEC_MASK) >> TSP_SWINT_INFO_SEC_SHFT;
2123 status = (sw_int & TSP_SWINT_STATUS_CMD_MASK) >> TSP_SWINT_STATUS_CMD_SHFT;
2124 //pFilter = &(_REGSec->Flt[fltid]);
2125
2126 if(_ptsp_res->_tspInfo.BufState[fltid] == E_TSP_FLT_STATE_FREE)
2127 {
2128 goto CLEAR_INT;;
2129 }
2130
2131 if(_TSP_ChkSecNotifyId(fltid) == FALSE)
2132 {
2133 sw_int &= ~TSP_SWINT_CTRL_FIRE;
2134 hw_int &= ~TSP_HWINT_TSP_SW_INT_EN;
2135 status = 0;
2136 }
2137 else
2138 {
2139 _s32EventId = _ptsp_res->_tspInfo.s32TspEvtId[fltid];
2140 }
2141
2142 switch (status)
2143 {
2144
2145 case TSP_SWINT_STATUS_SEC_RDY_CRCERR: // CRC error But accept section ;
2146 //When there's no CRC in the section & E_TSP_FLT_MODE_AUTO_CRCCHK is used,
2147 //don't report CRC error
2148 if(!(_ptsp_res->_tspInfo.FltMode[fltid] & E_TSP_FLT_MODE_AUTO_CRCCHK))
2149 case TSP_SWINT_STATUS_SEC_CRCERR: // Filter Didn't check CRC and Section Rdy
2150 {
2151 TSP_FLAG_SetCrcErr(fltid); // Set section event flag
2152 }
2153
2154 if (E_TSP_EVENT_CB_AUTO == (_ptsp_res->_tspInfo.FltEvent[fltid] & E_TSP_EVENT_CB_MASK))
2155 {
2156 TSP_SetEvent(_s32EventId, TSP_EVENT_SECTION); // Wake task up
2157 }
2158 #ifdef MSOS_TYPE_LINUX_KERNEL
2159 // TSP_OS_Print("%s[%04d]: 0x%08X\n", __FILE__, __LINE__, status);
2160 MDrv_TSP_SEC_SetEvent(fltid, DEMUX_EVENT_CRC_FAILED);
2161 wake_up_interruptible(&(tsp_wq_head[fltid]));
2162 #endif
2163
2164 if (TSP_SWINT_STATUS_SEC_CRCERR == status)
2165 break;
2166
2167 case TSP_SWINT_STATUS_SEC_RDY:
2168
2169 if ( (E_TSP_FLT_USER_MASK & _ptsp_res->_tspInfo.FltType[fltid]) &&
2170 (E_TSP_FLT_MODE_ONESHOT & _ptsp_res->_tspInfo.FltMode[fltid]))
2171 {
2172 TSP_FLAG_SetFltDis(fltid); // Set section event flag
2173 if (E_TSP_EVENT_CB_POLL == (_ptsp_res->_tspInfo.FltEvent[fltid] & E_TSP_EVENT_CB_MASK))
2174 TSP_SetEvent(_s32EventId, TSP_EVENT_DISABLEFLT);
2175 }
2176
2177 // During over-night test, we have got section ready interrupt from non-section filter.
2178 // The interrupt is illegal, and will cause TSP ASSERT "HwBufId != tspInfo Bufid" in _TSP_PROC_SecRdy.
2179 // Since the root cause was not found yet, we add a patch here to reject the non-section filter interrupt.
2180 if(((_ptsp_res->_tspInfo.FltType[fltid] & E_TSP_FLT_USER_MASK) == 0) || ((_ptsp_res->_tspInfo.FltState[fltid] & E_TSP_FLT_STATE_ENABLE) == 0) )
2181 {
2182 break;
2183 }
2184
2185 TSP_FLAG_SetSecRdy(fltid); // Set section event flag
2186 // @NOTE Jerry
2187 // It's set by user and ALL section filters should be the same beucase the TASK will race with POLL
2188 // Since it's for backward compatible, it's not revised at this time and may be remove in the future.
2189 if (E_TSP_EVENT_CB_AUTO == (_ptsp_res->_tspInfo.FltEvent[fltid] & E_TSP_EVENT_CB_MASK))
2190 {
2191 TSP_SetEvent(_s32EventId, TSP_EVENT_SECTION); // Wake task up
2192 }
2193 else if (E_TSP_EVENT_CB_POLL == (_ptsp_res->_tspInfo.FltEvent[fltid] & E_TSP_EVENT_CB_MASK))
2194 {
2195 TSP_SetEvent(_s32EventId, TSP_EVENT_SECTION_POLL); // Set POLL flags
2196
2197 }
2198
2199 #ifdef MSOS_TYPE_LINUX_KERNEL
2200 wake_up_interruptible(&(tsp_wq_head[fltid]));
2201 #endif
2202 break;
2203
2204 case TSP_SWINT_STATUS_BUF_OVFLOW:
2205 if (!(TSP_FLAG_GetSecOvf(fltid, &dummy, TSP_OS_EVENT_OR))) // ignore redundant overflow
2206 {
2207 //TSP_ISR_Print("TSP_SWINT_STATUS_PKT_OVFLOW , Flt = %ld, Buf = %ld , PID= %04lX\n",fltid,_ptsp_res->_tspInfo.Flt2Buf[fltid],_ptsp_res->_tspInfo.Pid[fltid]);
2208 if ( (E_TSP_FLT_USER_MASK & _ptsp_res->_tspInfo.FltType[fltid]) )
2209 {
2210 TSP_FLAG_SetFltDis(fltid); // Set section event flag
2211 if (E_TSP_EVENT_CB_POLL == (_ptsp_res->_tspInfo.FltEvent[fltid] & E_TSP_EVENT_CB_MASK))
2212 TSP_SetEvent(_s32EventId, TSP_EVENT_DISABLEFLT);
2213
2214 }
2215
2216 TSP_FLAG_SetSecOvf(fltid); // Set section event flag
2217 if (E_TSP_EVENT_CB_AUTO == (_ptsp_res->_tspInfo.FltEvent[fltid] & E_TSP_EVENT_CB_MASK))
2218 {
2219 TSP_SetEvent(_s32EventId, TSP_EVENT_SECTION); // Wake task up
2220 }
2221 else if (E_TSP_EVENT_CB_POLL == (_ptsp_res->_tspInfo.FltEvent[fltid] & E_TSP_EVENT_CB_MASK))
2222 {
2223 TSP_SetEvent(_s32EventId, TSP_EVENT_SECTION_POLL); // Set POLL flags
2224 }
2225 }
2226
2227 #ifdef MSOS_TYPE_LINUX_KERNEL
2228 MDrv_TSP_SEC_SetEvent(fltid, DEMUX_EVENT_DATA_DISCARDED);
2229 wake_up_interruptible(&(tsp_wq_head[fltid]));
2230 #endif
2231 break;
2232
2233 case TSP_SWINT_STATUS_PKT_OVRUN:
2234 TSP_ISR_Print("TSP_SWINT_STATUS_PKT_OVRUN [%d] \n",(unsigned int)fltid);
2235 break;
2236
2237 case TSP_SWINT_STATUS_SEC_ERROR:
2238 case TSP_SWINT_STATUS_DEBUG:
2239 //[ISR print]
2240 // TSP_OS_Print("%s[%04d]: 0x%08X\n", __FILE__, __LINE__, status);
2241 break;
2242
2243 default:
2244 //[ISR print]
2245 // TSP_OS_Print(OSAL_TSP_Print("Unknown TSP interrupt %d\n", u32EngId));
2246 break;
2247 }
2248 }
2249
2250 CLEAR_INT:
2251
2252 _TSP_INT_LOCK();
2253 if(hw_int)
2254 {
2255 HAL_TSP_INT_ClrHW(TSP_HWINT_ALL); // @F_TODO: it's changed from U4 make sure we clr them all
2256 //HAL_TSP_INT_ClrHW(hw_int >> 8); // @F_TODO: it's changed from U4 make sure we clr them all
2257 }
2258 if(sw_int)
2259 {
2260 HAL_TSP_INT_ClrSW();
2261 }
2262 _TSP_INT_UNLOCK();
2263
2264 TSP_OS_IntEnable();
2265
2266 #ifdef MSOS_TYPE_LINUX_KERNEL
2267 return IRQ_HANDLED;
2268 #endif
2269 }
2270
2271
_TSP_POLL_Proc(MS_U32 u32Events,MS_U32 u32FltId,TSP_Event * pEvent)2272 static void _TSP_POLL_Proc(MS_U32 u32Events, MS_U32 u32FltId, TSP_Event *pEvent)
2273 {
2274 MS_U32 flags; // dummy
2275 // int i;
2276
2277 #if __LEGACY__
2278 if ( (TSP_EVENT_PVR0_RDY_POLL | TSP_EVENT_PVR1_RDY_POLL) & u32Events )
2279 {
2280 _TSP_Proc_Pvr(u32Events, E_TSP_EVENT_CB_POLL);
2281 }
2282 #endif
2283
2284 /* [Eddie] Disable filter at ISR_Task
2285 // Check any possible filter should be disabled (POLL)
2286 for (i = 0; i < TSP_PIDFLT_NUM; i++)
2287 {
2288 if (TSP_FLAG_GetFltDis(i, &flags, TSP_OS_EVENT_OR_CLEAR))
2289 {
2290 TSP_LOCK();
2291 _TSP_FLT_Disable(i);
2292 TSP_UNLOCK();
2293 }
2294 }
2295 */
2296 if (TSP_FLAG_GetFltDis(u32FltId, &flags, TSP_OS_EVENT_OR_CLEAR))
2297 {
2298 TSP_LOCK();
2299 _TSP_FLT_Disable(u32FltId);
2300 TSP_UNLOCK();
2301 }
2302
2303 // Process singl specified filter
2304
2305 // @FIXME: Jerry
2306 // Check the behavior between ISR_Proc and _Poll_Proc
2307 // Why isn't _Proc_SecOvf first than _Proc_SecRdy as _ISR_Proc
2308
2309 if ((_ptsp_res->_tspInfo.FltState[u32FltId] != E_TSP_FLT_STATE_FREE) && (_ptsp_res->_tspInfo.FltState[u32FltId] != E_TSP_FLT_STATE_ISR_FREE))
2310 {
2311 *pEvent = E_TSP_EVENT_DATA_IDLE;
2312 if (E_TSP_FAIL == _TSP_PROC_SecRdy(u32FltId, pEvent))
2313 {
2314 if (TSP_FLAG_GetSecOvf(u32FltId, &flags, TSP_OS_EVENT_OR)) // @FIXME: clear events at Proc_SecOvf?
2315 {
2316 _TSP_PROC_SecOvf(u32FltId, pEvent);
2317 }
2318 else if (TSP_FLAG_GetCrcErr(u32FltId, &flags, TSP_OS_EVENT_OR)) // @Note: Priority Overflow > CRCError > SecRdy
2319 {
2320 _TSP_PROC_CrcErr(u32FltId, pEvent);
2321 }
2322 }
2323 }
2324 }
2325
2326
_TSP_HW_ResetState(void)2327 static void _TSP_HW_ResetState(void)
2328 {
2329 MS_U32 fltid;
2330
2331 for (fltid = 0; fltid < (TSP_PIDFLT_NUM_ALL-1); fltid++)
2332 {
2333 _TSP_FLT_Disable(fltid);
2334 _TSP_FLT_Init(fltid); // state => FREE
2335 _TSP_FLT_Free(fltid);
2336 }
2337
2338 for (fltid = 0; fltid < TSP_SECBUF_END_ID; fltid++)
2339 {
2340 _TSP_SEC_Init(fltid); // state => FREE
2341 _TSP_SEC_Free(fltid);
2342 }
2343 }
2344
2345
_TSP_SW_ResetState(void)2346 static void _TSP_SW_ResetState(void)
2347 {
2348 MS_U32 fltid;
2349
2350 for (fltid = 0; fltid < TSP_SECFLT_END_ID; fltid++)
2351 {
2352 _ptsp_res->_tspInfo.BufState[fltid] = E_TSP_FLT_STATE_NA;
2353 _ptsp_res->_tspInfo.FltMode[fltid] = E_TSP_FLT_MODE_CONTI;
2354 _ptsp_res->_tspInfo.FltEvent[fltid] = E_TSP_EVENT_DATA_IDLE;
2355 _ptsp_res->_tspInfo.FltCallback[fltid] = NULL;
2356 _ptsp_res->_tspInfo.s32TspEvtId[fltid] = -1;
2357 }
2358
2359 for (fltid = 0; fltid < (TSP_PIDFLT_NUM_ALL - 1); fltid++)
2360 {
2361 _ptsp_res->_tspInfo.Pid[fltid] = TSP_PID_NULL;
2362 _ptsp_res->_tspInfo.FltState[fltid] = E_TSP_FLT_STATE_NA;
2363 _ptsp_res->_tspInfo.FltType[fltid] = E_TSP_FLT_USER_NULL;
2364 }
2365
2366 }
2367
_TSP_Init(MS_BOOL bResetSW,MS_BOOL bRestoreHW)2368 static TSP_Result _TSP_Init(MS_BOOL bResetSW, MS_BOOL bRestoreHW)
2369 {
2370 int i;
2371
2372 //Disable CPU to prevent cpu enable by other module before tsp_init.
2373 HAL_TSP_CPU(0);
2374 HAL_TSP_Power(1);//@F_TODO not implement yet disable unused clk in TSP compare with K2
2375
2376 // Diable interrupt
2377 HAL_TSP_INT_Disable(TSP_HWINT_ALL|(TSP_HWINT2_ALL<<8)|(TSP_HWINT3_ALL<<16));//@F_TODO need to check what it really disabled.... 0x6c????
2378
2379 // IntDisable
2380 // IntDetach
2381 TSP_OS_IntDisable();
2382 TSP_OS_IntDetach();
2383
2384 //@F_TODO DISABLE tsif 0~3
2385 for (i = 0; i < TSP_TSIF_NUM; i++)
2386 {
2387 HAL_TSP_SetTSIF(i, E_TSP_TSIF_DIS, FALSE);
2388 }
2389
2390 //HAL_TSP_HW_Lock_Init();//@NOTE HW LOCK is a mechenism to use regiter to protect register modify race between HK and TSP CPU
2391
2392 HAL_TSP_Reset(1);
2393 HAL_TSP_Reset(0); // indirect access activated, WB reset, CMDQ reset
2394 // HAL_TSP_HWPatch();
2395
2396 HAL_TSP_INT_ClrSW();
2397 HAL_TSP_INT_ClrHW(TSP_HWINT_ALL|(TSP_HWINT2_ALL<<8)|(TSP_HWINT3_ALL<<16)); // @F_TODO: need to check this step with Stephen for which interrup to clear
2398
2399 #ifdef MERGE_STR_SUPPORT
2400 HAL_TSP_PktConverter_Init();
2401 #endif
2402
2403 HAL_TSP_HwPatch(); // @F_TODO no source yet
2404 //HAL_TSP_SetCAPath(TSP_CA_ROUTE_EN | TSP_CA_OUT_EN | TSP_CA_FLOWCTRL_EN);
2405
2406 /*
2407 // XXX: Jericho: temp solution to prevent TSP write memory
2408 HAL_TSP_CPU_WProtect(TRUE, 0, 0);
2409 */
2410
2411 if (bResetSW)
2412 {
2413 _TSP_SW_ResetState();
2414 }
2415
2416 if (bRestoreHW)
2417 {
2418 HAL_TSP_RestoreFltState();
2419 }
2420 else
2421 {
2422 _TSP_HW_ResetState();
2423 }
2424
2425 #ifndef SECURE_PVR_ENABLE
2426 if (TRUE != HAL_TSP_SetVQ(_ptsp_res->_tspInfo.Param.phyVQAddr, _ptsp_res->_tspInfo.Param.u32VQSize))
2427 {
2428 TSP_DBG(E_TSP_DBG_MUST, "TSP VQ is not aligned\n");
2429 return E_TSP_FAIL;
2430 }
2431 #else
2432 _ptsp_res->_stSecBuf.u32BufId = 0;
2433 _ptsp_res->_stSecBuf.u32BufOpt = 0;
2434 _ptsp_res->_stSecBuf.u32BufSize = _ptsp_res->_tspInfo.Param.u32VQSize;
2435 _ptsp_res->_stSecBuf.phyBufAddr = _ptsp_res->_tspInfo.Param.phyVQAddr;
2436 //printf("[%s][%d] u32BufId %d, opte %d , bufsize %x, addr %x \n", __FUNCTION__, __LINE__, (int)_ptsp_res->_stSecBuf.u32BufId,
2437 // (int)_ptsp_res->_stSecBuf.u32BufOpt, (int)_ptsp_res->_stSecBuf.u32BufSize, (int)_ptsp_res->_stSecBuf.phyBufAddr);
2438 if(MDrv_TSP_Ree_SendTeeCmd(E_DRVTSP_REE_TO_TEE_CMD_SET_VqBuf, (void*)(&(_ptsp_res->_stSecBuf)), sizeof(DrvTSP_SecureBuf)) != E_TSP_OK)
2439 {
2440 TSP_DBG(E_TSP_DBG_MUST, "[MDRV TSP][%06d] Set VQ buf fail!\n", __LINE__);
2441 return E_TSP_FAIL;
2442 }
2443 HAL_TSP_VQ_Enable(TRUE);
2444 #endif //SECURE_PVR_ENABLE
2445
2446 #ifdef SECURE_PVR_ENABLE //load fwtsp.dat from Tee
2447 _ptsp_res->_stSecBuf.u32BufId = 0;
2448 _ptsp_res->_stSecBuf.u32BufOpt = 0;
2449 _ptsp_res->_stSecBuf.u32BufSize = _ptsp_res->_tspInfo.Param.u32FWSize;
2450 _ptsp_res->_stSecBuf.phyBufAddr = _ptsp_res->_tspInfo.Param.phyFWAddr;
2451 //printf("[%s][%d] u32BufId %d, opte %d , bufsize %x, addr %x \n", __FUNCTION__, __LINE__, (int)_ptsp_res->_stSecBuf.u32BufId,
2452 // (int)_ptsp_res->_stSecBuf.u32BufOpt, (int)_ptsp_res->_stSecBuf.u32BufSize, (int)_ptsp_res->_stSecBuf.phyBufAddr);
2453 if(MDrv_TSP_Ree_SendTeeCmd(E_DRVTSP_REE_TO_TEE_CMD_FW_LoadCode, (void*)(&(_ptsp_res->_stSecBuf)), sizeof(DrvTSP_SecureBuf)) != E_TSP_OK)
2454 {
2455 return E_TSP_FAIL;
2456 }
2457 #endif
2458
2459 if (TRUE != HAL_TSP_LoadFW(_ptsp_res->_tspInfo.Param.phyFWAddr, _ptsp_res->_tspInfo.Param.u32FWSize))
2460 {
2461 TSP_DBG(E_TSP_DBG_MUST, "TSP firmware is not aligned\n");
2462 return E_TSP_FAIL;
2463 }
2464
2465 HAL_TSP_CPU(1);
2466 #if defined (MSOS_TYPE_LINUX_KERNEL)
2467 mdelay(3);
2468 #else
2469 MsOS_DelayTask(3);
2470 #endif
2471
2472 while (FALSE == HAL_TSP_HCMD_Alive())
2473 {
2474 TSP_OS_Print("Reset TSP CPU fail, Retry.\n");
2475 HAL_TSP_CPU(0);
2476 #ifdef SECURE_PVR_ENABLE //load fwtsp.dat from Tee
2477 if(MDrv_TSP_Ree_SendTeeCmd(E_DRVTSP_REE_TO_TEE_CMD_FW_LoadCode, (void*)(&(_ptsp_res->_stSecBuf)), sizeof(DrvTSP_SecureBuf)) != E_TSP_OK)
2478 {
2479 return E_TSP_FAIL;
2480 }
2481 #endif
2482 HAL_TSP_LoadFW(_ptsp_res->_tspInfo.Param.phyFWAddr, _ptsp_res->_tspInfo.Param.u32FWSize);
2483 HAL_TSP_CPU(1);
2484 #if defined (MSOS_TYPE_LINUX_KERNEL)
2485 mdelay(3);
2486 #else
2487 MsOS_DelayTask(3);
2488 #endif
2489 }
2490 TSP_OS_Print("Reset TSP CPU Success.\n");
2491 TSP_OS_Print(">> FwVersion:%08X , Date:%08X \n",(unsigned int)HAL_TSP_HCMD_GetInfo(INFO_FW_VERSION),(unsigned int)HAL_TSP_HCMD_GetInfo(INFO_FW_DATE));
2492
2493 #ifdef SECURE_PVR_ENABLE
2494 _ptsp_res->_stSecBuf.u32BufId = 0xFF;
2495 _ptsp_res->_stSecBuf.u32BufOpt = 0;
2496 _ptsp_res->_stSecBuf.u32BufSize = 0;
2497 _ptsp_res->_stSecBuf.phyBufAddr = 0;
2498 if(MDrv_TSP_Ree_SendTeeCmd(E_DRVTSP_REE_TO_TEE_CMD_FW_LoadCode, (void*)(&(_ptsp_res->_stSecBuf)), sizeof(DrvTSP_SecureBuf)) != E_TSP_OK)
2499 {
2500 return E_TSP_FAIL;
2501 }
2502 #endif
2503
2504 HAL_TSP_INT_ClrSW();
2505 HAL_TSP_INT_ClrHW(TSP_HWINT_ALL|(TSP_HWINT2_ALL<<8)|(TSP_HWINT3_ALL<<16)); // @FIXME : it's changed from U4 we need to make sure kaiser is not chaged
2506
2507 // Implicity MDrv_TSP_Reset()
2508 #if 1
2509 for(i=0; i<TSP_TSIF_NUM; i++)
2510 {
2511 switch(i)
2512 {
2513 case TSP_TSIF0:
2514 HAL_TSP_Filein_ByteDelay(E_FILEENG_TSIF0, 0x0A, TRUE); //@FIXME why use 0xA
2515 break;
2516 case TSP_TSIF1:
2517 HAL_TSP_Filein_ByteDelay(E_FILEENG_TSIF1, 0x0A, TRUE); //@FIXME why use 0xA
2518 break;
2519 case TSP_TSIF2:
2520 HAL_TSP_Filein_ByteDelay(E_FILEENG_TSIF2, 0x0A, TRUE); //@FIXME why use 0xA
2521 break;
2522 case TSP_TSIF3:
2523 HAL_TSP_Filein_ByteDelay(E_FILEENG_TSIF3, 0x0A, TRUE); //@FIXME why use 0xA
2524 break;
2525 }
2526 }
2527 #else
2528 HAL_TSP_File_SetDelay(0x0A); // Set TsDma delay, //jyliu.tsp, how come the value?
2529 #endif
2530
2531 // STC control by TSP need indirect R/W enable
2532 HAL_TSP_STC_Init();
2533 // HAL_TSP_SetSTCSynth(STC_SYNTH_DEFAULT); // @NOTE this is done in HAL_TSP_STC_Init
2534
2535
2536 TSP_OS_IntAttach((void*)_TSP_ISR);
2537 TSP_OS_IntEnable();
2538
2539 // [URANUS] Richard: Refine the interrupt selection later.
2540 HAL_TSP_INT_Enable(TSP_HWINT_ALL|(TSP_HWINT2_ALL<<8)|(TSP_HWINT3_ALL<<16)); // Enable TSP hardware interrupt
2541
2542 if (_ptsp_res->_tspInfo.bSWInit)
2543 {
2544 return E_TSP_OK;
2545 }
2546
2547 #if defined(__LEGACY__)
2548 _ptsp_res->_PvrEvtNotify = E_TSP_EVENT_DATA_IDLE;
2549 _ptsp_res->_PvrCallback = NULL;
2550 #endif
2551
2552 _ptsp_res->_s32MutexId = TSP_OS_MutexCreate((MS_U8*)"TSP_Mutex"); // MsOS_CreateMutex(E_MSOS_FIFO, "TSP_Mutex");
2553 _ptsp_res->_s32LockId = TSP_OS_MutexCreate((MS_U8*)"TSP_Ind_Mutex"); // MsOS_CreateMutex(E_MSOS_FIFO, "TSP_Mutex");
2554 #ifndef MSOS_TYPE_LINUX_KERNEL
2555 _ptsp_res->_s32IntRegMutexId = TSP_OS_MutexCreate((MS_U8*)"TSP_Int_Mutex");
2556 #endif
2557 _ptsp_res->_s32PvrMutexId = TSP_OS_MutexCreate((MS_U8*)"TSP_Pvr_Mutex"); // MsOS_CreateMutex(E_MSOS_FIFO, "TSP_Pvr_Mutex");
2558 #ifndef MSOS_TYPE_LINUX_KERNEL
2559 _s32EventId = TSP_OS_EventCreate((MS_U8*)"TSP_Event"); // MsOS_CreateEventGroup("TSP_Event");
2560 #endif
2561
2562 _ptsp_res->_tspInfo.bISRTaskEn = TRUE;
2563 #ifndef MSOS_TYPE_LINUX_KERNEL
2564 // we dont create driver task in kernel mode, thus related checking should be remove too.
2565 _ptsp_res->_s32TaskId = TSP_OS_TaskCreate(_TSP_ISR_Task, (MS_U8*)"TSP_ISR_Task");
2566
2567 if ( _ptsp_res->_s32TaskId == -1 )
2568 {
2569 return E_TSP_FAIL;
2570 }
2571 #endif
2572
2573 #ifndef MSOS_TYPE_LINUX_KERNEL
2574 if ( (_ptsp_res->_s32MutexId == -1) || (_ptsp_res->_s32LockId == -1) || (_ptsp_res->_s32PvrMutexId == -1) || (_s32EventId == -1) )
2575 #else
2576 if ( (_ptsp_res->_s32MutexId == -1) || (_ptsp_res->_s32LockId == -1) || (_ptsp_res->_s32PvrMutexId == -1))
2577 #endif
2578 {
2579 return E_TSP_FAIL;
2580 }
2581
2582 for (i = 0; i < ((TSP_SECFLT_NUM+31)>>5); i++)
2583 {
2584 _s32SecRdyFlags[i] = TSP_OS_EventCreate((MS_U8*)"TSP_SecRdy");
2585 if(_s32SecRdyFlags[i] == -1)
2586 { TSP_DBG(E_TSP_DBG_ERROR, "[%04d] Create _s32SecRdyFlags[%d] failed", __LINE__, i); }
2587
2588 _s32CrcErrFlags[i] = TSP_OS_EventCreate((MS_U8*)"TSP_CrcErr");
2589 if(_s32CrcErrFlags[i] == -1)
2590 { TSP_DBG(E_TSP_DBG_ERROR, "[%04d] Create _s32CrcErrFlags[%d] failed", __LINE__, i); }
2591
2592 _s32SecOvfFlags[i] = TSP_OS_EventCreate((MS_U8*)"TSP_SecOvf");
2593 if(_s32SecOvfFlags[i] == -1)
2594 { TSP_DBG(E_TSP_DBG_ERROR, "[%04d] Create _s32SecOvfFlags[%d] failed", __LINE__, i); }
2595
2596 _s32FltDisFlags[i] = TSP_OS_EventCreate((MS_U8*)"TSP_FltDis");
2597 if(_s32FltDisFlags[i] == -1)
2598 { TSP_DBG(E_TSP_DBG_ERROR, "[%04d] Create _s32FltDisFlags[%d] failed", __LINE__, i); }
2599
2600 _s32FreeFlags[i] = TSP_OS_EventCreate((MS_U8*)"TSP_FltFree");
2601 if(_s32FreeFlags[i] == -1)
2602 { TSP_DBG(E_TSP_DBG_ERROR, "[%04d] Create _s32FreeFlags[%d] failed", __LINE__, i); }
2603
2604 _s32DoneFlags[i] = TSP_OS_EventCreate((MS_U8*)"TSP_FltDone");
2605 if(_s32DoneFlags[i] == -1)
2606 { TSP_DBG(E_TSP_DBG_ERROR, "[%04d] Create _s32DoneFlags[%d] failed", __LINE__, i); }
2607
2608 _s32OvfRstFlags[i]= 0 ;
2609 _s32ModeFlags[i] = 0 ;
2610
2611 _u32SecNotifyId[i] = 0;
2612
2613 }
2614
2615 _ptsp_res->_tspInfo.Status = E_TSP_SW_INIT;
2616 _ptsp_res->_tspInfo.bSWInit = TRUE;
2617 _ptsp_res->_tspInfo.LastErr = E_TSP_OK;
2618
2619 // Default Live Path as TSIF0
2620 _ptsp_res->_Current_Live = E_TSP_FLT_SRC_LIVE0;
2621 _ptsp_res->_Current_PVR = 0 ;
2622
2623 #ifdef MSOS_TYPE_LINUX_KERNEL
2624 for (i = 0; i < TSP_SECFLT_END_ID; i++)
2625 {
2626 init_waitqueue_head(&tsp_wq_head[i]);
2627 }
2628 memset(_u32SecEvent, 0, sizeof(_u32SecEvent));
2629
2630 if(_u32KPrcEvtTblUseFlag == 0)
2631 {
2632 for (i= 0; i< DRVTSP_MAX_PROCESS_NUM; i++)
2633 {
2634 _stKModePrcEvtTbl[i].tgid = 0;
2635 _stKModePrcEvtTbl[i].s32TspEvtId = -1;
2636 }
2637 }
2638 #endif
2639
2640 return E_TSP_OK;
2641
2642 }
2643
2644
_TSP_Exit(void)2645 static void _TSP_Exit(void)
2646 {
2647 MS_U32 i;
2648 MS_U32 Pcr_H, Pcr;
2649
2650 HAL_TSP_INT_Disable(TSP_HWINT_ALL|(TSP_HWINT2_ALL<<8)|(TSP_HWINT3_ALL<<16));
2651
2652 //always read PCR after PCR interrupt has been disabled or cleared to avoid that interrupt's not trggering again.
2653 for (i = 0; i < TSP_PCRFLT_NUM; i++)
2654 {
2655 HAL_TSP_PcrFlt_GetPcr(i, &Pcr_H, &Pcr);
2656 }
2657
2658 TSP_OS_IntDisable();
2659 TSP_OS_IntDetach();
2660
2661 for (i = 0; i < TSP_TSIF_NUM; i++) //@FIXME is this enough?
2662 {
2663 HAL_TSP_SetTSIF(i, E_TSP_TSIF_DIS, FALSE);
2664 }
2665 HAL_TSP_CPU(0);
2666 HAL_TSP_Reset(1);
2667 HAL_TSP_Power(0);
2668 }
2669
_TSP_SW_Exit(void)2670 static void _TSP_SW_Exit(void)
2671 {
2672 int i;
2673
2674 if(_ptsp_res->_s32TaskId != -1)
2675 {
2676 while(!_s32_IsrTaskReturn)
2677 {
2678 TSP_SetEvent(_s32EventId, TSP_EVENT_TASKEND);
2679
2680 #if defined (MSOS_TYPE_LINUX_KERNEL)
2681 mdelay(TSP_POLLING_TASK_DELAY);
2682 #else
2683 MsOS_DelayTask(TSP_POLLING_TASK_DELAY);
2684 #endif
2685 }
2686 _s32_IsrTaskReturn = FALSE;
2687
2688 _ptsp_res->_s32TaskId = -1;
2689 _ptsp_res->_tspInfo.bISRTaskEn = FALSE;
2690 }
2691
2692 if(_ptsp_res->_s32MutexId != -1)
2693 {
2694 TSP_OS_MutexRelease(_ptsp_res->_s32MutexId);
2695 TSP_OS_MutexDelete(_ptsp_res->_s32MutexId);
2696 _ptsp_res->_s32MutexId = -1;
2697 }
2698 if(_ptsp_res->_s32LockId != -1)
2699 {
2700 TSP_OS_MutexRelease(_ptsp_res->_s32LockId);
2701 TSP_OS_MutexDelete(_ptsp_res->_s32LockId);
2702 _ptsp_res->_s32LockId = -1;
2703 }
2704 #ifdef MSOS_TYPE_LINUX_KERNEL
2705 spin_lock_init(&_ptsp_res->_s32IntRegMutexId);
2706 #else
2707 if(_ptsp_res->_s32IntRegMutexId != -1)
2708 {
2709 TSP_OS_MutexRelease(_ptsp_res->_s32IntRegMutexId);
2710 TSP_OS_MutexDelete(_ptsp_res->_s32IntRegMutexId);
2711 _ptsp_res->_s32IntRegMutexId = -1;
2712 }
2713 #endif
2714 if(_ptsp_res->_s32PvrMutexId != -1)
2715 {
2716 TSP_OS_MutexRelease(_ptsp_res->_s32PvrMutexId);
2717 TSP_OS_MutexDelete(_ptsp_res->_s32PvrMutexId);
2718 _ptsp_res->_s32PvrMutexId = -1;
2719 }
2720
2721 #ifndef MSOS_TYPE_LINUX_KERNEL
2722 if(_s32EventId != -1)
2723 {
2724 TSP_OS_EventDelete(_s32EventId);
2725 _s32EventId = -1;
2726 }
2727 #endif
2728
2729 for (i = 0; i < ((TSP_SECFLT_NUM+31)>>5); i++)
2730 {
2731 if(_s32SecRdyFlags[i] != -1)
2732 {
2733 TSP_OS_EventDelete(_s32SecRdyFlags[i]);
2734 _s32SecRdyFlags[i] = -1;
2735 }
2736 if(_s32CrcErrFlags[i] != -1)
2737 {
2738 TSP_OS_EventDelete(_s32CrcErrFlags[i]);
2739 _s32CrcErrFlags[i] = -1;
2740 }
2741 if(_s32SecOvfFlags[i] != -1)
2742 {
2743 TSP_OS_EventDelete(_s32SecOvfFlags[i]);
2744 _s32SecOvfFlags[i] = -1;
2745 }
2746 if(_s32FltDisFlags[i] != -1)
2747 {
2748 TSP_OS_EventDelete(_s32FltDisFlags[i]);
2749 _s32FltDisFlags[i] = -1;
2750 }
2751 if(_s32FreeFlags[i] != -1)
2752 {
2753 TSP_OS_EventDelete(_s32FreeFlags[i]);
2754 _s32FreeFlags[i] = -1;
2755 }
2756 if(_s32DoneFlags[i] != -1)
2757 {
2758 TSP_OS_EventDelete(_s32DoneFlags[i]);
2759 _s32DoneFlags[i] = -1;
2760 }
2761 }
2762 _MDrv_TSP_FLT_ResetFltId();
2763
2764 #ifdef SECURE_PVR_ENABLE
2765 MDrv_TSP_Ree_TeeCmdSystem_Exit();
2766 #endif
2767
2768 _ptsp_res->_tspInfo.bSWInit = FALSE;
2769 }
2770
_TSP_Drv_DmxFlow2PVREng_Mapping(DRV_TSP_FLOW DmxFlow)2771 static MS_U32 _TSP_Drv_DmxFlow2PVREng_Mapping(DRV_TSP_FLOW DmxFlow)
2772 {
2773 switch (DmxFlow)
2774 {
2775 case E_DRV_TSP_FLOW_PVR0:
2776 return 0;
2777 break;
2778 case E_DRV_TSP_FLOW_PVR1:
2779 return 1;
2780 break;
2781 case E_DRV_TSP_FLOW_PVR2:
2782 return 2;
2783 break;
2784 case E_DRV_TSP_FLOW_PVR3:
2785 return 3;
2786 break;
2787 default:
2788 return 0xFFFFFFFF;
2789 break;
2790 }
2791 }
2792
2793 //-------------------------------------------------------------------------------------------------
2794 // Global Functions
2795 //-------------------------------------------------------------------------------------------------
2796
2797 //-------------------------------------------------------------------------------------------------
2798 /// Initialize lib resource API
2799 /// @param pu32ResMemAddr \b IN: Pointer to store resource memory address
2800 /// @return TSP_Result
2801 /// @note
2802 //-------------------------------------------------------------------------------------------------
MDrv_TSP_InitLibResource(void * pu32ResMemAddr)2803 TSP_Result MDrv_TSP_InitLibResource(void *pu32ResMemAddr)
2804 {
2805 TSP_CHECK((pu32ResMemAddr != 0),
2806 "[TSP_ERROR][%s][%06d] pointer is NULL!\n", __FUNCTION__, __LINE__);
2807
2808 MS_VIRT u32Base;
2809 MS_PHY u32Size;
2810
2811 _ptsp_res = (TSP_RESOURCE_PRIVATE*)pu32ResMemAddr;
2812
2813 // For multi-process use case, driver will direct return to avoid re-init HW again on api layer thus the second process will not set bank.
2814 // And the parameter on hal layer is static (ex:bank base), so the bank base on the second process will be NULL.
2815 // We need to avoid this case thus we set bank again on initLibResource function.
2816 if(_ptsp_res->_tspInfo.bSWInit != TRUE)
2817 {
2818 if(_TSP_InitResource(_ptsp_res) == FALSE)
2819 return E_TSP_FAIL;
2820 }
2821 else
2822 {
2823 if(_bBankInit == FALSE)
2824 {
2825 MDrv_MMIO_Init();
2826 if (FALSE == MDrv_MMIO_GetBASE(&u32Base, &u32Size, MS_MODULE_HW))
2827 {
2828 TSP_OS_Print("Get MS_MODULE_PM fail\n");
2829 MS_ASSERT(0);
2830 }
2831 HAL_TSP_SetBank(u32Base);
2832 _bBankInit = TRUE;
2833 }
2834 }
2835
2836 return E_TSP_OK;
2837 }
2838
2839 //-------------------------------------------------------------------------------------------------
2840 /// Initialize TSP driver and TSP engine
2841 /// @return TSP_Result
2842 /// @note
2843 /// It should be called before calling any other TSP DDI functions.
2844 /// Driver task is in @ref E_TASK_PRI_SYS level.
2845 //-------------------------------------------------------------------------------------------------
MDrv_TSP_Init(TSP_InitParam * pParam)2846 TSP_Result MDrv_TSP_Init(TSP_InitParam *pParam)
2847 {
2848 MS_VIRT u32Base;
2849 MS_PHY u32Size;
2850 MS_U32 *u32Check;
2851 TSP_Result ret;
2852
2853 #ifdef SECURE_PVR_ENABLE
2854 if(MDrv_TSP_Ree_TeeCmdSystem_Init() == E_TSP_FAIL)
2855 {
2856 MS_DEBUG_MSG(TSP_DBG ("[%s] Register Mailbox failed!\n", __FUNCTION__));
2857 return E_TSP_FAIL;
2858 }
2859 #endif //SECURE_PVR_ENABLE
2860
2861 // MDrv_DSCMB_Init(); // sometimes good/bad // random
2862 MDrv_MMIO_Init();
2863 #if 1
2864 if (FALSE == MDrv_MMIO_GetBASE(&u32Base, &u32Size, MS_MODULE_HW))
2865 {
2866 TSP_OS_Print("Get MS_MODULE_PM fail\n");
2867 MS_ASSERT(0);
2868 }
2869 HAL_TSP_SetBank(u32Base);
2870
2871 TSP_DBG(E_TSP_DBG_INFO, "MMIO(MS_MODULE_PM) 0x%08x\n", u32Base);
2872 #else
2873 if (FALSE == MDrv_MMIO_GetBASE(&u32Base, &u32Size, MS_MODULE_TSP))
2874 {
2875 TSP_OS_Print("Get MS_MODULE_TSP fail\n");
2876 MS_ASSERT(0);
2877 }
2878 HAL_TSP_RegMap(u32Base);
2879 TSP_DBG(E_TSP_DBG_INFO, "MMIO(MS_MODULE_TSP) 0x%08lx\n", u32Base);
2880
2881 if (FALSE == MDrv_MMIO_GetBASE(&u32Base, &u32Size, MS_MODULE_HW))
2882 {
2883 TSP_OS_Print("Get MS_MODULE_HW fail\n");
2884 MS_ASSERT(0);
2885 }
2886 // MDrv_DSCMB_Init(); // sometimes good/bad // random
2887 HAL_TSP_HW_RegMap(u32Base);
2888 TSP_DBG(E_TSP_DBG_INFO, "MMIO(MS_MODULE_HW) 0x%08lx\n", u32Base);
2889
2890
2891 if (FALSE == MDrv_MMIO_GetBASE(&u32Base, &u32Size, MS_MODULE_PM))
2892 {
2893 TSP_OS_Print("Get MS_MODULE_PM fail\n");
2894 MS_ASSERT(0);
2895 }
2896 HAL_TSP_PM_RegMap(u32Base);
2897 TSP_DBG(E_TSP_DBG_INFO, "MMIO(MS_MODULE_PM) 0x%08lx\n", u32Base);
2898 #endif
2899
2900 TSP_DBG(E_TSP_DBG_MUST, "************************ Start TSP_Init ************************\n");
2901
2902
2903
2904 u32Check = (MS_U32*)MsOS_PA2KSEG1(pParam->phyFWAddr);
2905
2906 if (strcmp((char*)u32Check,FWTSP_CHECK_CODE) != 0 )
2907 {
2908 TSP_OS_Print("**** [TSP Firmware] Check Fail ****\n");
2909 }
2910 TSP_OS_Print(" %s : ",(char*)u32Check);
2911
2912 memcpy(&(_ptsp_res->_tspInfo.Param), pParam, sizeof(TSP_InitParam));
2913 if (E_TSP_OK != (ret = _TSP_Init(TRUE, FALSE)))
2914 {
2915 TSP_DBG(E_TSP_DBG_MUST, "************************ TSP [FAIL] ************************\n");
2916 return ret;
2917 }
2918 // MDrv_DSCMB_Init(); // bad
2919
2920 TSP_DBG(E_TSP_DBG_MUST, "************************* End TSP_Init *************************\n");
2921
2922
2923 //[NOTE] Switch Uart0 port to TSP
2924 #if SWITCH_TSP_UART
2925 _TSP_Switch_Uart();
2926 #endif
2927
2928 return E_TSP_OK;
2929 }
2930
2931
2932
2933
2934
2935 //-------------------------------------------------------------------------------------------------
2936 /// Close TSP driver and reset software/register state
2937 /// @return TSP_Result
2938 /// @note
2939 //-------------------------------------------------------------------------------------------------
MDrv_TSP_Exit(void)2940 TSP_Result MDrv_TSP_Exit(void)
2941 {
2942 TSP_DBG(E_TSP_DBG_TRACK , "%s\n", __FUNCTION__);
2943
2944 MS_PHY u32Size=0;
2945 MS_VIRT u32Base=0;
2946 MS_BOOL bEnterEntry = FALSE;
2947 MS_U32 i = 0;
2948
2949 TSP_DBG(E_TSP_DBG_MUST, "============[%s] TSP Exit Start ==============\n",__FUNCTION__);
2950
2951 if (_ptsp_res->_s32MutexId != -1 )
2952 {
2953 TSP_ENTRY();
2954 bEnterEntry = TRUE;
2955 }
2956
2957 #ifndef MSOS_TYPE_LINUX_KERNEL
2958 if (_ptsp_res->_s32IntRegMutexId != -1 )
2959 {
2960 _TSP_INT_LOCK();
2961 }
2962 #endif
2963
2964 if (_ptsp_res->_s32PvrMutexId != -1 )
2965 {
2966 TSP_PVR_ENTRY();
2967 }
2968
2969
2970 if (FALSE == MDrv_MMIO_GetBASE(&u32Base, &u32Size, MS_MODULE_HW))
2971 {
2972 TSP_OS_Print("Get MS_MODULE_PM fail\n");
2973 MS_ASSERT(0);
2974 }
2975 HAL_TSP_SetBank(u32Base);
2976 TSP_DBG(E_TSP_DBG_INFO, "MMIO(MS_MODULE_PM) 0x" MPRI_VIRT "\n", u32Base);
2977
2978
2979 if (!HAL_TSP_HCMD_Alive())
2980 {
2981
2982 MS_U32 Pcr_H, Pcr;
2983
2984 HAL_TSP_Power(1);
2985
2986 HAL_TSP_INT_Disable(TSP_HWINT_ALL|(TSP_HWINT2_ALL<<8)|(TSP_HWINT3_ALL<<16));
2987
2988 //always read PCR after PCR interrupt has been disabled or cleared to avoid that interrupt's not trggering again.
2989 for (i = 0; i < TSP_PCRFLT_NUM; i++)
2990 {
2991 HAL_TSP_PcrFlt_GetPcr(i, &Pcr_H, &Pcr);
2992 }
2993 //HAL_TSP_HW_Lock_Init(); //@F_TODO HW lock is a mechanism we use to avoid race between HK and TSP CPU for those register like filter disable and stc but we dont need that anymore
2994
2995 HAL_TSP_Reset(1);
2996 HAL_TSP_Reset(0); // indirect access activated, WB reset, CMDQ reset
2997 }
2998 _ptsp_res->_tspInfo.Status = E_TSP_SW_EXIT;
2999
3000 // SW driver state
3001 _TSP_SW_ResetState();
3002 // HW filter state
3003 _TSP_HW_ResetState();
3004
3005 _TSP_Exit();
3006 _TSP_SW_Exit();
3007
3008 if ( TRUE == bEnterEntry )
3009 {
3010 MDrv_SEM_Unlock(E_SEM_CA);
3011 }
3012
3013 TSP_DBG(E_TSP_DBG_MUST, "============[%s] TSP Exit End ============\n",__FUNCTION__);
3014
3015 return E_TSP_OK;
3016 }
3017
3018
3019 //-------------------------------------------------------------------------------------------------
3020 /// Poweroff TSP driver and TSP engine
3021 /// @return TSP_Result
3022 /// @note
3023 //-------------------------------------------------------------------------------------------------
MDrv_TSP_PowerOff(void)3024 TSP_Result MDrv_TSP_PowerOff(void)
3025 {
3026 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
3027
3028 TSP_ENTRY();
3029
3030 _ptsp_res->_tspInfo.Status = E_TSP_SW_POWEROFF;
3031
3032 _TSP_Exit();
3033 _TSP_SW_Exit();
3034 MDrv_SEM_Unlock(E_SEM_CA);
3035
3036 return E_TSP_OK;
3037 }
3038
3039
3040 ///[RESERVED]
MDrv_TSP_Reset(void)3041 TSP_Result MDrv_TSP_Reset(void)
3042 {
3043 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
3044
3045 if(_ptsp_res->_tspInfo.bSWInit != TRUE)
3046 {
3047 TSP_DBG(E_TSP_DBG_MUST, "[%s][%d] Please call MDrv_TSP_Init() first\n", __FUNCTION__, __LINE__);
3048 return E_TSP_FAIL;
3049 }
3050
3051 TSP_ENTRY();
3052
3053 _TSP_Init(TRUE, FALSE);
3054
3055 TSP_RETURN(E_TSP_OK);
3056
3057 }
3058
3059
3060 //[RESERVED]
MDrv_TSP_Suspend(void)3061 TSP_Result MDrv_TSP_Suspend(void)
3062 {
3063 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
3064
3065 TSP_ENTRY();
3066
3067 _ptsp_res->_tspInfo.Status = E_TSP_SW_SUSPEND;
3068
3069 HAL_TSP_SaveFltState();
3070
3071 _TSP_Exit();
3072 _TSP_SW_Exit();
3073
3074 _ptsp_res->_tspInfo.bSuspend = TRUE;
3075
3076 TSP_RETURN(E_TSP_OK);
3077 }
3078
3079
3080 //[RESERVED]
MDrv_TSP_Resume(MS_U32 u32FWAddr,MS_U32 u32FWSize)3081 TSP_Result MDrv_TSP_Resume(MS_U32 u32FWAddr, MS_U32 u32FWSize)
3082 {
3083 TSP_Result ret;
3084
3085 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
3086
3087 // we can't operate TSP register before power on
3088 // HAL_TSP_Reset(1);
3089 // HAL_TSP_Reset(0);
3090 // HAL_TSP_HwPatch();
3091 // MsOS_DelayTask(500);
3092
3093 _ptsp_res->_tspInfo.Status = E_TSP_SW_RESUME;
3094 _ptsp_res->_tspInfo.bSuspend = FALSE;
3095 _ptsp_res->_tspInfo.Param.phyFWAddr = u32FWAddr;
3096 _ptsp_res->_tspInfo.Param.u32FWSize = u32FWSize;
3097
3098 ret = _TSP_Init(FALSE, TRUE);
3099
3100 return ret;
3101 }
3102
MDrv_TSP_PVR_SetFlowSource(MS_U32 u32Eng,MS_U32 u32PvrSrc)3103 TSP_Result MDrv_TSP_PVR_SetFlowSource(MS_U32 u32Eng, MS_U32 u32PvrSrc)
3104 {
3105 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
3106 TSP_ENTRY();
3107
3108 MS_U32 u32FltSrc = E_TSP_FLT_SRC_MASK & u32PvrSrc;
3109 TSP_PIDFLT_SRC ePidFltSrc = _TSP_DrvHal_FltSrcMapping(u32FltSrc);
3110 MS_U32 u32Tid = HAL_TSP_FltSrc2PktDmx_Mapping(ePidFltSrc);
3111
3112 TSP_RES_ALLOC_TSPPATH_CHECK(u32Tid);
3113
3114 if (E_TSP_PVR_PVRENG_END > u32Eng) // PVR Eng
3115 {
3116 HAL_PVR_Init(u32Eng, u32Tid);
3117 }
3118 else
3119 {
3120 TSP_DBG(E_TSP_DBG_MUST, "[ERROR][%s][%d]Incorrect Engine type!\n",__FUNCTION__,__LINE__);
3121 }
3122
3123 TSP_RETURN(E_TSP_OK);
3124 }
3125
MDrv_TSP_SetFlowSource(DRV_TSP_FLOW DmxFlow,TSP_TSId eTid)3126 TSP_Result MDrv_TSP_SetFlowSource(DRV_TSP_FLOW DmxFlow, TSP_TSId eTid)
3127 {
3128 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
3129 TSP_ENTRY();
3130
3131 // @F_TODO add another layer for adaption, concider for flexibility
3132 // @NOTE PVR has no source mmfi take care
3133 // @NOTE setting FIFO SRC is moved to MDrv_TSP_FLT_Enable()
3134 // @NOTE because setting flowset playback may be for record...
3135 if ( (DmxFlow == E_DRV_TSP_FLOW_PLAYBACK0) || (DmxFlow == E_DRV_TSP_FLOW_PLAYBACK1)
3136 || (DmxFlow == E_DRV_TSP_FLOW_PLAYBACK2) || (DmxFlow == E_DRV_TSP_FLOW_PLAYBACK3)
3137 || (DmxFlow == E_DRV_TSP_FLOW_PLAYBACK4) || (DmxFlow == E_DRV_TSP_FLOW_PLAYBACK5)
3138 || (DmxFlow == E_DRV_TSP_FLOW_PLAYBACK6) )
3139 {
3140 /*
3141 if (DmxFlow == E_DRV_TSP_FLOW_PLAYBACK0)
3142 {
3143 HAL_TSP_FIFO_SetSrc(E_TSP_DST_FIFO_AUDIO, eTid); //@FIXME change pktdmx id don't use drv.h enum as parameter to hal layer
3144 HAL_TSP_FIFO_SetSrc(E_TSP_DST_FIFO_VIDEO, eTid);
3145 }
3146 else if (DmxFlow == E_DRV_TSP_FLOW_PLAYBACK1)
3147 {
3148 HAL_TSP_FIFO_SetSrc(E_TSP_DST_FIFO_AUDIO2 , eTid); //@FIXME change pktdmx id don't use drv.h enum as parameter to hal layer
3149 HAL_TSP_FIFO_SetSrc(E_TSP_DST_FIFO_VIDEO3D, eTid);
3150 }
3151 */
3152 TSP_RETURN(E_TSP_OK);
3153 }
3154 else if ((DmxFlow == E_DRV_TSP_FLOW_PVR0) || (DmxFlow == E_DRV_TSP_FLOW_PVR1) || (DmxFlow == E_DRV_TSP_FLOW_PVR2) || (DmxFlow == E_DRV_TSP_FLOW_PVR3))
3155 {
3156 MS_U32 u32pktDmxId = (MS_U32)eTid;
3157 MS_U32 u32Eng = _TSP_Drv_DmxFlow2PVREng_Mapping(DmxFlow);
3158 TSP_SRC_SEQ ePktDmx = HAL_TSP_Eng2PktDmx_Mapping(u32Eng);
3159 switch(ePktDmx)
3160 {
3161 case E_TSP_SRC_PKTDMX0:
3162 u32pktDmxId = 0;
3163 break;
3164 case E_TSP_SRC_PKTDMX1:
3165 u32pktDmxId = 1;
3166 break;
3167 case E_TSP_SRC_PKTDMX2:
3168 u32pktDmxId = 2;
3169 break;
3170 case E_TSP_SRC_PKTDMX3:
3171 u32pktDmxId = 3;
3172 break;
3173 case E_TSP_SRC_PKTDMX4:
3174 u32pktDmxId = 4;
3175 break;
3176 case E_TSP_SRC_PKTDMX5:
3177 u32pktDmxId = 5;
3178 break;
3179 default:
3180 u32pktDmxId = 0;
3181 TSP_DBG(E_TSP_DBG_MUST, "[TSP_ERR][%s][%d] Wrong PktDmx type!!!\n",__FUNCTION__,__LINE__);
3182 break;
3183 }
3184
3185 if (E_TSP_PVR_PVRENG_END > u32Eng) // PVR Eng
3186 {
3187 HAL_PVR_Init(u32Eng, u32pktDmxId);
3188 }
3189 else
3190 {
3191 TSP_DBG(E_TSP_DBG_MUST, "[ERROR][%s][%d]Incorrect Engine type!\n",__FUNCTION__,__LINE__);
3192 }
3193 }
3194 else if ((DmxFlow == E_DRV_TSP_FLOW_TSO0) || (DmxFlow == E_DRV_TSP_FLOW_TSO1))
3195 {
3196 //@F_TODO not implement yet
3197 //@F_TODO remember to change TSO src to pktdmx
3198 TSP_RETURN(E_TSP_FAIL);
3199 }
3200 else
3201 {
3202 // @FIXME add error msg
3203 TSP_RETURN(E_TSP_FAIL);
3204 }
3205
3206
3207 TSP_RETURN(E_TSP_OK);
3208 }
3209
3210 //-------------------------------------------------------------------------------------------------
3211 /// Select ChipTop PAD for ts0 and ts1
3212 /// @param u32EngId \b IN: index of TSP engine [ 0 .. (@ref DRVTSP_ENGINE_NUM-1) ]
3213 /// @param eIf \b IN: TSP TS interface
3214 /// @param pIfSet \b IN: TS interface setting
3215 /// @return TSP_Result
3216 /// @note
3217 /// Uranus: only can select pad0/pad1 to ts0
3218 /// Oberon: can select pad0/pad1 to ts0, pad0/pad1 to ts1.
3219 /// Default setting was pad0->ts0, pad1->ts1.
3220 //-------------------------------------------------------------------------------------------------
MDrv_TSP_SelPad(TSP_TSIF eTSIF,TSP_TSPad eTSPad)3221 TSP_Result MDrv_TSP_SelPad(TSP_TSIF eTSIF, TSP_TSPad eTSPad)
3222 {
3223 TSP_Result ret;
3224 TSP_TS_PAD ePad = E_TSP_TS_PAD_INVALID;
3225 MS_U32 u32TSIF = 0;
3226
3227 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
3228 TSP_ENTRY();
3229
3230 ePad = _TSP_DrvHal_PadMapping(eTSPad);
3231
3232 if((eTSPad >= E_TSP_TS_PAD0_3WIRE) && (eTSPad <= E_TSP_TS_PAD7_3WIRE))
3233 {
3234 HAL_TSP_PAD_3Wire(ePad, TRUE);
3235 }
3236 else
3237 {
3238 HAL_TSP_PAD_3Wire(ePad, FALSE);
3239 }
3240
3241 TSP_HAL_TSIF eHalTSIF = _TSP_DrvHal_TSIFMapping(eTSIF);
3242 u32TSIF = HAL_TSP_TsifMapping(eHalTSIF, FALSE);
3243
3244 TSP_RES_ALLOC_TSPPATH_CHECK(u32TSIF);
3245
3246 if (HAL_TSP_TSIF_SelPad(u32TSIF, ePad))
3247 {
3248 _ptsp_res->TsIf_Src[u32TSIF].ePad= eTSPad;
3249 ret = E_TSP_OK;
3250 }
3251 else
3252 {
3253 ret = E_TSP_FAIL;
3254 }
3255
3256 TSP_RETURN(ret);
3257 }
3258
3259 //-------------------------------------------------------------------------------------------------
3260 ///// Set TSP MUX Clk Invert mode
3261 ///// @param u16TSIF \b IN: TS MUX Index
3262 ///// @param bClkInv \b IN: Clock Invert
3263 ///// @return TSP_Result
3264 ///// @note
3265 ///// Set TSP PAD Clk gen invert if the bClkInv is TRUE
3266 ///// u16TSIF = TSMux0 , TSMux1 ,TSMux2
3267 /////
3268 ///// @sa
3269 ////-------------------------------------------------------------------------------------------------
MDrv_TSP_SelPad_ClkInv(TSP_TSIF eTSIF,MS_BOOL bClkInv)3270 TSP_Result MDrv_TSP_SelPad_ClkInv(TSP_TSIF eTSIF ,MS_BOOL bClkInv)
3271 {
3272 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
3273 TSP_ENTRY();
3274
3275 MS_U32 u32TSIF;
3276 TSP_HAL_TSIF eHalTSIF = _TSP_DrvHal_TSIFMapping(eTSIF);
3277 u32TSIF = HAL_TSP_TsifMapping(eHalTSIF, FALSE);
3278
3279 TSP_RES_ALLOC_TSPPATH_CHECK(u32TSIF);
3280
3281 _ptsp_res->TsIf_Src[u32TSIF].bClkInv = bClkInv;
3282
3283 HAL_TSP_TSIF_SelPad_ClkInv(u32TSIF , bClkInv);
3284
3285 TSP_RETURN(E_TSP_OK);
3286 }
3287
3288 //-------------------------------------------------------------------------------------------------
3289 ///// Set TSP MUX Clk disable mode
3290 ///// @param u16TSIF \b IN: TS MUX Index
3291 ///// @param bClkdis \b IN: Clock Disable
3292 ///// @return TSP_Result
3293 ///// @note
3294 ///// Set TSP PAD Clk gen disabled if the bClkDis is TRUE
3295 ///// u16TSIF = TSMux0 , TSMux1 ,TSMux2
3296 /////
3297 ///// @sa
3298 ////-------------------------------------------------------------------------------------------------
MDrv_TSP_SelPad_ClkDis(TSP_TSIF eTSIF,MS_BOOL bClkDis)3299 TSP_Result MDrv_TSP_SelPad_ClkDis(TSP_TSIF eTSIF ,MS_BOOL bClkDis)
3300 {
3301 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
3302 TSP_ENTRY();
3303
3304 MS_U32 u32TSIF;
3305 TSP_HAL_TSIF eHalTSIF = _TSP_DrvHal_TSIFMapping(eTSIF);
3306 u32TSIF = HAL_TSP_TsifMapping(eHalTSIF, FALSE);
3307
3308 TSP_RES_ALLOC_TSPPATH_CHECK(u32TSIF);
3309
3310 HAL_TSP_TSIF_SelPad_ClkDis(u32TSIF , bClkDis);
3311
3312 TSP_RETURN(E_TSP_OK);
3313 }
3314
3315
MDrv_TSP_TSO_ConfigPad(MS_U32 u32TSOEng,TSP_TSPad eTSPad)3316 TSP_Result MDrv_TSP_TSO_ConfigPad(MS_U32 u32TSOEng, TSP_TSPad eTSPad)
3317 {
3318 TSP_Result eRet = E_TSP_OK;
3319 TSP_TS_PAD ePad = E_TSP_TS_PAD_INVALID;
3320
3321 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
3322 TSP_ENTRY();
3323
3324 HAL_TSO_SetTSOOutMUX(TRUE);
3325
3326 ePad = _TSP_DrvHal_PadMapping(eTSPad);
3327 if(!HAL_TSP_TSO_TSIF_SelPad(u32TSOEng, ePad))
3328 eRet = E_TSP_FAIL;
3329
3330 TSP_RETURN(eRet);
3331 }
3332
3333 //-------------------------------------------------------------------------------------------------
3334 /// Set TSP engine operating mode
3335 /// @param u32EngId \b IN: index of TSP engine [ 0 .. (@ref DRVTSP_ENGINE_NUM-1) ]
3336 /// @param eCtrlMode \b IN: TSP engine operating mode
3337 /// @return TSP_Result
3338 /// @note
3339 /// Only one engine can be set to use memory stream input mode, and all kinds
3340 /// of input are mutually exclusive for each engine.\n
3341 /// Only one engine can output to MAD. The TSP engine which is not selected to
3342 /// MAD can not filter any audio stream, it will block the stream.
3343 /// @sa MDrv_TSP_PidFlt_Alloc, MDrv_TSP_PidFlt_Enable, E_TSP_FLT_TYPE_AUDIO
3344 //-------------------------------------------------------------------------------------------------
MDrv_TSP_SetTSIF(TSP_TSIF eTSIF,TSP_TSIFCfg u32Cfg,MS_BOOL bFileIn)3345 TSP_Result MDrv_TSP_SetTSIF(TSP_TSIF eTSIF, TSP_TSIFCfg u32Cfg, MS_BOOL bFileIn)
3346 {
3347 TSP_Result ret;
3348 TSP_TSIF_CFG cfg = E_TSP_TSIF_CFG_DIS;
3349
3350 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
3351
3352 TSP_ENTRY();
3353
3354 if (u32Cfg & E_TSP_TSIF_EN)
3355 {
3356 cfg |= E_TSP_TSIF_CFG_EN;
3357 }
3358 if (u32Cfg & E_TSP_TSIF_PARL)
3359 {
3360 cfg |= E_TSP_TSIF_CFG_PARA;
3361 }
3362 if (u32Cfg & E_TSP_TSIF_EXTSYNC)
3363 {
3364 cfg |= E_TSP_TSIF_CFG_EXTSYNC;
3365 }
3366 if (u32Cfg & E_TSP_TSIF_CFG_BITSWAP)
3367 {
3368 cfg |= E_TSP_TSIF_CFG_BITSWAP;
3369 }
3370 if (u32Cfg & E_TSP_TSIF_3WIRE)
3371 {
3372 cfg |= E_TSP_TSIF_CFG_3WIRE;
3373 }
3374
3375 TSP_HAL_TSIF eHalTSIF = _TSP_DrvHal_TSIFMapping(eTSIF);
3376 MS_U32 u32TSIF = HAL_TSP_TsifMapping(eHalTSIF, bFileIn);
3377
3378 TSP_RES_ALLOC_TSPPATH_CHECK(u32TSIF);
3379
3380 if(!bFileIn)
3381 {
3382 _ptsp_res->TsIf_Src[u32TSIF].bExtSync = !!(u32Cfg & E_TSP_TSIF_EXTSYNC);
3383 _ptsp_res->TsIf_Src[u32TSIF].bParallel = !!(u32Cfg & E_TSP_TSIF_PARL);
3384 }
3385 #ifdef MERGE_STR_SUPPORT
3386 else
3387 HAL_TSP_Reset_TSIF_MergeSetting(u32TSIF);
3388 #endif
3389 if (HAL_TSP_SetTSIF(u32TSIF, cfg, bFileIn))
3390 {
3391 ret = E_TSP_OK;
3392 }
3393 else
3394 {
3395 ret = E_TSP_FAIL;
3396 }
3397
3398 TSP_RETURN(ret);
3399 }
3400
3401 /*
3402 TSP_Result MDrv_TSP_SetOperateMode(MS_U32 u32EngId, TSP_CtrlMode eCtrlMode) // @FIXME
3403 {
3404 TSP_ENTRY();
3405
3406 if (u32EngId >= TSP_ENGINE_NUM)
3407 {
3408 TSP_RETURN(TSP_FAIL);
3409 }
3410
3411 if ((HAL_TSP_GetCtrlMode() & TSP_CTRL_TSIF0_FILE_EN) ||
3412 (eCtrlMode == E_TSP_CTRL_MODE_MEM))
3413 {
3414 if (!HAL_TSP_CmdQ_IsEmpty())
3415 {
3416 TSP_RETURN(TSP_FAIL);
3417 }
3418 HAL_TSP_CmdQ_TsDma_Reset();
3419 }
3420
3421 switch (eCtrlMode)
3422 {
3423 case E_TSP_CTRL_MODE_TS0:
3424 HAL_TSP_PS_Path_Disable();
3425 HAL_TSP_SetCA(TSP_CA_INPUT_TSIF0_LIVEIN|TSP_CA_OUTPUT_PLAY_LIVE); //|TSP_CA_AVPAUSE);
3426 #if 0
3427 HAL_TSP_DoubleBuf_Disable();
3428 HAL_TSP_SetCtrlMode(TSP_CTRL_CPU_EN | TSP_CTRL_SW_RST, 0);
3429 #else
3430 HAL_TSP_SetTSIF(0, TSP_TSIF0_EN | TSP_TSIFx_EXTSYNC | TSP_TSIFx_PARL, FALSE);
3431 #endif
3432 break;
3433 case E_TSP_CTRL_MODE_TS1:
3434 HAL_TSP_PS_Path_Disable();
3435 HAL_TSP_DoubleBuf_Disable();
3436 HAL_TSP_SetCtrlMode(TSP_CTRL_CPU_EN | TSP_CTRL_SW_RST, 1);
3437 break;
3438 case E_TSP_CTRL_MODE_MEM:
3439 HAL_TSP_PS_Path_Disable();
3440 HAL_TSP_DoubleBuf_En(DOUBLE_BUFFER_SWITCH); // [OBERON]:Enable double buffer, set filein->pinpon livein->single
3441 HAL_TSP_SetCA(TSP_CA_INPUT_TSIF0_FILEIN|TSP_CA_OUTPUT_PLAY_FILE|TSP_CA_AVPAUSE);
3442 HAL_TSP_SetCtrlMode(TSP_CTRL_CPU_EN | TSP_CTRL_SW_RST| TSP_CTRL_TSIF0_FILE_EN, 2);
3443 break;
3444 default:
3445 TSP_RETURN(TSP_FAIL);
3446 break;
3447 }
3448
3449 TSP_RETURN(TSP_OK);
3450
3451 }
3452 */
3453
3454 //-------------------------------------------------------------------------------------------------
3455 // Ask TSP to process section/pvr data for Non-OS driver. Calling this function in OS environment causes nothing
3456 // @OBSOLETED
3457 // @param u32EngId \b IN: index of TSP engine [ 0 .. (@ref DRVTSP_ENGINE_NUM-1) ]
3458 // @param u32FltId \b IN: Which filter id to process. 0xFFFFFFFF means process all filters
3459 // @param u32Timeout \b IN: Max time for TSP to process
3460 // @return TSP_Result
3461 // @note
3462 // It's only for backward compatible
3463 // @seealso
3464 // MDrv_TSP_FLT_SetCallback
3465 //-------------------------------------------------------------------------------------------------
MDrv_TSP_Proc(MS_U32 u32TSPId,MS_U32 u32FltId,TSP_Event * pEvent)3466 TSP_Result MDrv_TSP_Proc(MS_U32 u32TSPId, MS_U32 u32FltId, TSP_Event* pEvent) // for non-OS TSP scheduling
3467 {
3468 MS_U32 events = 0;
3469
3470 TSP_CHECK(_tspFltIdMap.u32PidFltIdAll > u32FltId, "[%04d] Invalid u32FltId %d\n", __LINE__, (unsigned int)u32FltId);
3471
3472 //HAL_TSP_GetCaps(E_TSP_HAL_CAP_TYPE_RECFLT_IDX, &u32RecFltIdx);
3473
3474 if((u32FltId >= _tspFltIdMap.u32PcrFltId_Start) && (u32FltId <= _tspFltIdMap.u32RecFltIdx))
3475 return E_TSP_OK;
3476
3477 TSP_ENTRY();
3478
3479 if (_ptsp_res->_tspInfo.FltState[u32FltId] == E_TSP_FLT_STATE_NA)
3480 {
3481 TSP_RETURN(E_TSP_FAIL);
3482 }
3483
3484 if (E_TSP_EVENT_CB_AUTO == (_ptsp_res->_tspInfo.FltEvent[u32FltId] & E_TSP_EVENT_CB_MASK))
3485 {
3486 TSP_OS_Print("[%s] Flt %d is CallBack Mode Filter, Polling this filter will cause unexpected result !!\n",__FUNCTION__,(unsigned int)u32FltId);
3487 //*pEvent = E_TSP_EVENT_DATA_IDLE ;
3488 //TSP_RETURN(E_TSP_FAIL_NODATA);
3489 }// Driver do not support Callback mode and Polling mode coexistance at the same filter.
3490
3491
3492 // @FIXME Jerry
3493 // For legacy driver compatibility, it call polling and hopes polling will call it back in the same context.
3494 // Does this kind of misbehavior still live?
3495 TSP_UNLOCK();
3496 // @NOTE Jerry
3497 // Clear poll events directly in case there has any incoming event before _TSP_ISR_Proc to clear
3498 TSP_GetEvent(_s32EventId, &events, TSP_POLL_EVENTS, TSP_OS_EVENT_OR_CLEAR, 0);
3499 _TSP_POLL_Proc(events, u32FltId, pEvent);
3500 TSP_LOCK();
3501
3502 if (*pEvent == E_TSP_EVENT_DATA_IDLE )
3503 {
3504 TSP_RETURN(E_TSP_FAIL_NODATA);
3505 }
3506 else
3507 {
3508 TSP_RETURN(E_TSP_OK);
3509 }
3510 }
3511
3512 //-------------------------------------------------------------------------------------------------
3513 /// Allocate TSP Path Id
3514 /// @param eResType \b IN: TSP path type
3515 /// @param pu32PathId \b OUT: TSP path id. If no free path ID, it will be 0xFFFFFFFF and return FAIL.
3516 /// @return TSP_Result
3517 /// @note
3518 //-------------------------------------------------------------------------------------------------
MDrv_TSP_Path_Alloc(DRV_TSP_PATH_TYPE eResType,MS_U32 * pu32PathId)3519 TSP_Result MDrv_TSP_Path_Alloc(DRV_TSP_PATH_TYPE eResType, MS_U32 *pu32PathId)
3520 {
3521 TSP_Result ret = E_TSP_FAIL;
3522
3523 TSP_ENTRY();
3524
3525 ret = _TSP_Path_Alloc(eResType, pu32PathId);
3526
3527 if(ret == E_TSP_OK)
3528 {
3529 if( (eResType == E_DRV_TSP_PATH_LIVE) || (eResType == E_DRV_TSP_PATH_FILE) )
3530 {
3531 _ptsp_res->_bIsTspPathEverAlloc = TRUE;
3532 }
3533 }
3534
3535 TSP_RETURN(ret);
3536 }
3537
3538 //-------------------------------------------------------------------------------------------------
3539 /// Free TSP Path Id
3540 /// @param eResType \b IN: TSP path type
3541 /// @param u32PathId \b IN: TSP path id
3542 /// @return TSP_Result
3543 /// @note
3544 //-------------------------------------------------------------------------------------------------
MDrv_TSP_Path_Free(DRV_TSP_PATH_TYPE eResType,TSP_TSIF ePath)3545 TSP_Result MDrv_TSP_Path_Free(DRV_TSP_PATH_TYPE eResType, TSP_TSIF ePath)
3546 {
3547 TSP_Result ret = E_TSP_FAIL;
3548
3549 TSP_ENTRY();
3550
3551 ret = _TSP_Path_Free(eResType, ePath);
3552
3553 TSP_RETURN(ret);
3554 }
3555
3556 //-------------------------------------------------------------------------------------------------
3557 /// Allocate STC engine.
3558 /// @param pu32EngId \b OUT: STC engine id. If no free STC engine, it will be 0xFFFFFFFF and return FAIL.
3559 /// @return TSP_Result
3560 /// @note
3561 //-------------------------------------------------------------------------------------------------
MDrv_TSP_STC_Alloc(MS_U32 * pu32EngId)3562 TSP_Result MDrv_TSP_STC_Alloc(MS_U32 *pu32EngId)
3563 {
3564 TSP_Result ret;
3565
3566 TSP_ENTRY();
3567
3568 ret = _TSP_STC_Alloc(pu32EngId);
3569
3570 if(ret == E_TSP_OK)
3571 {
3572 _ptsp_res->_bIsStcEverAlloc = TRUE;
3573 }
3574
3575 TSP_RETURN(ret);
3576 }
3577
3578
3579 //-------------------------------------------------------------------------------------------------
3580 /// Free STC engine
3581 /// @param u32EngId \b IN: index of STC engine to be free
3582 /// @return TSP_Result
3583 /// @note
3584 //-------------------------------------------------------------------------------------------------
MDrv_TSP_STC_Free(MS_U32 u32EngId)3585 TSP_Result MDrv_TSP_STC_Free(MS_U32 u32EngId)
3586 {
3587 TSP_Result ret = E_TSP_FAIL;
3588
3589 TSP_ENTRY();
3590
3591 ret = _TSP_STC_Free(u32EngId);
3592
3593 TSP_RETURN(ret);
3594 }
3595
3596 //-------------------------------------------------------------------------------------------------
3597 /// Free STC engine
3598 /// @param u32PcrFltId \b IN: index of PCR PID filter
3599 /// @param pu32EngId \b Out: index of STC engine which u32PcrFltId mapping to
3600 /// @return TSP_Result
3601 /// @note
3602 //-------------------------------------------------------------------------------------------------
MDrv_TSP_PcrId_To_StcId(MS_U32 u32PcrFltId,MS_U32 * pu32EngId)3603 TSP_Result MDrv_TSP_PcrId_To_StcId(MS_U32 u32PcrFltId,MS_U32 *pu32EngId)
3604 {
3605 TSP_Result ret = E_TSP_FAIL;
3606
3607 TSP_ENTRY();
3608
3609 ret = _TSP_PcrId_To_StcId(u32PcrFltId, pu32EngId);
3610
3611 TSP_RETURN(ret);
3612 }
3613
_MDrv_TSP_FLT_RemapFltId(void)3614 void _MDrv_TSP_FLT_RemapFltId(void)
3615 {
3616 TSP_DBG(E_TSP_DBG_TRACK, "[%s][%d]\n", __FUNCTION__, __LINE__);
3617 // 255 for Err Flt
3618 // 254 for REC Flt
3619 // 253 ~ (254 - PCR_NUM) for PCR Flt
3620 // others for Pid Flt/Sec Flt/Sec Buf
3621 _tspFltIdMap.u32PidFltIdAll = 254;
3622
3623 _tspFltIdMap.u32RecFltIdx = 254;
3624 _tspFltIdMap.u32PcrFltId_End = _tspFltIdMap.u32RecFltIdx;
3625 _tspFltIdMap.u32PcrFltId_Start = _tspFltIdMap.u32PcrFltId_End - TSP_PCRFLT_NUM;
3626
3627 _tspFltIdMap.u32PidFltId_End = _tspFltIdMap.u32PcrFltId_Start;
3628
3629 #if (TSP_SECFLT_END_ID > 255)
3630 _tspFltIdMap.u32SecFltId_End = _tspFltIdMap.u32PcrFltId_Start;
3631 _tspFltIdMap.u32SecBufId_End = _tspFltIdMap.u32PcrFltId_Start;
3632 #endif
3633
3634 _tspFltIdMap.u32PidFltId_Start = TSP_PIDFLT_START_ID;
3635 _tspFltIdMap.u32SecFltId_Start = TSP_SECFLT_START_ID;
3636 _tspFltIdMap.u32SecBufId_Start = TSP_SECBUF_START_ID;
3637
3638 }
_MDrv_TSP_FLT_ResetFltId()3639 void _MDrv_TSP_FLT_ResetFltId()
3640 {
3641 TSP_DBG(E_TSP_DBG_TRACK, "[%s][%d]\n", __FUNCTION__, __LINE__);
3642
3643 _tspFltIdMap.u32SecFltId_Start = TSP_SECFLT_START_ID;
3644 _tspFltIdMap.u32SecFltId_End = TSP_SECFLT_END_ID;
3645 _tspFltIdMap.u32SecBufId_Start = TSP_SECBUF_START_ID;
3646 _tspFltIdMap.u32SecBufId_End = TSP_SECBUF_END_ID;
3647 _tspFltIdMap.u32PidFltId_Start = TSP_PIDFLT_START_ID;
3648 _tspFltIdMap.u32PidFltId_End = TSP_PIDFLT_END_ID;
3649 _tspFltIdMap.u32PcrFltId_Start = TSP_PCRFLT_START_ID;
3650 _tspFltIdMap.u32PcrFltId_End = TSP_PCRFLT_END_ID;
3651 _tspFltIdMap.u32RecFltIdx = TSP_RECFLT_IDX;
3652
3653 _tspFltIdMap.u32PidFltIdAll = TSP_PIDFLT_NUM_ALL;
3654
3655
3656
3657 }
3658 //-------------------------------------------------------------------------------------------------
3659 /// Allocate a PID filter of a TSP unit
3660 /// @param u32EngId \b IN: index of TSP engine [ 0 .. (@ref DRVTSP_ENGINE_NUM-1) ]
3661 /// @param eFilterType \b IN: type of PID filter to be allocated
3662 /// @param pu32PidFltId \b OUT: pointer of PID filter id return
3663 /// @return TSP_Result
3664 /// @note
3665 /// These filter types have to select a section filter\n
3666 /// @ref E_TSP_FLT_TYPE_SECTION\n
3667 /// @ref E_TSP_FLT_TYPE_PCR\n
3668 /// @ref E_TSP_FLT_TYPE_PES\n
3669 /// @note
3670 /// These filter types also have to setup section buffer for data output\n
3671 /// @ref E_TSP_FLT_TYPE_SECTION\n
3672 /// @ref E_TSP_FLT_TYPE_PES\n
3673 /// @sa MDrv_TSP_PidFlt_SelSecFlt, MDrv_TSP_SecFlt_SetBuffer
3674 //-------------------------------------------------------------------------------------------------
MDrv_TSP_FLT_Alloc(MS_U32 u32TSPId,TSP_FltType eFltType,MS_U32 * pu32FltId)3675 TSP_Result MDrv_TSP_FLT_Alloc(MS_U32 u32TSPId, TSP_FltType eFltType, MS_U32 *pu32FltId)
3676 {
3677 TSP_DBG(E_TSP_DBG_TRACK, "[%s][%d]\n", __FUNCTION__, __LINE__);
3678 TSP_Result eResult = E_TSP_FAIL;
3679 if(!_bIsFltMapped)
3680 {
3681 MS_U32 u32CapInfo[2] = {0};
3682
3683 HAL_TSP_GetCaps(E_TSP_HAL_CAP_TYPE_RECFLT_IDX, u32CapInfo);
3684 if(u32CapInfo[0] > 0xFF)
3685 {
3686 _MDrv_TSP_FLT_RemapFltId();
3687 }
3688 _bIsFltMapped = TRUE;
3689 }
3690
3691 eResult = MDrv_TSP_FLT_Alloc_Common(u32TSPId, eFltType, pu32FltId);
3692
3693 if( eResult != E_TSP_OK)
3694 {
3695 return E_TSP_FAIL;
3696 }
3697 return E_TSP_OK;
3698 }
3699
MDrv_TSP_FLT_Alloc_Ex(MS_U32 u32TSPId,TSP_FltType eFltType,MS_U32 * pu32FltId)3700 TSP_Result MDrv_TSP_FLT_Alloc_Ex(MS_U32 u32TSPId, TSP_FltType eFltType, MS_U32 *pu32FltId)
3701 {
3702 TSP_DBG(E_TSP_DBG_TRACK, "[%s][%d]\n", __FUNCTION__, __LINE__);
3703 TSP_Result eResult = E_TSP_FAIL;
3704 eResult = MDrv_TSP_FLT_Alloc_Common(u32TSPId, eFltType, pu32FltId);
3705 if( eResult != E_TSP_OK)
3706 {
3707 return E_TSP_FAIL;
3708 }
3709 return E_TSP_OK;
3710
3711 }
3712
MDrv_TSP_FLT_Alloc_Common(MS_U32 u32TSPId,TSP_FltType eFltType,MS_U32 * pu32FltId)3713 TSP_Result MDrv_TSP_FLT_Alloc_Common(MS_U32 u32TSPId, TSP_FltType eFltType, MS_U32 *pu32FltId)
3714 {
3715 TSP_DBG(E_TSP_DBG_TRACK, "[%s][%d]\n", __FUNCTION__, __LINE__);
3716 //We do nothing when create dmx flt to record
3717 if( E_TSP_FLT_FIFO_REC == (eFltType & E_TSP_FLT_FIFO_MASK) )
3718 {
3719 MS_U32 u32CapInfo[2] = {0};
3720
3721 HAL_TSP_GetCaps(E_TSP_HAL_CAP_TYPE_RECFLT_IDX, u32CapInfo);
3722 *pu32FltId = u32CapInfo[0];
3723 return E_TSP_OK;
3724 }
3725
3726 REG_SecFlt * pSecFlt=0;
3727 MS_U32 type;
3728 int start_id, end_id, i;
3729 MS_U32 u32StcEng = 0xFFFFFFFF;
3730
3731 TSP_ENTRY();
3732
3733 *pu32FltId = 0xFFFFFFFF;
3734
3735 if ( E_TSP_FLT_USER_PCR == (eFltType & E_TSP_FLT_USER_MASK) )
3736 {
3737 if(_TSP_STC_Alloc(&u32StcEng) == FALSE)
3738 {
3739 TSP_DBG(E_TSP_DBG_ERROR, "[%04d] No free STC !!\n", __LINE__);
3740 TSP_RETURN(E_TSP_FAIL);
3741 }
3742
3743 start_id = _tspFltIdMap.u32PcrFltId_Start;
3744 end_id = _tspFltIdMap.u32PcrFltId_End;
3745 }
3746 else if( (E_TSP_FLT_USER_SEC == (eFltType & E_TSP_FLT_USER_MASK)) ||
3747 (E_TSP_FLT_USER_PES == (eFltType & E_TSP_FLT_USER_MASK)) ||
3748 (E_TSP_FLT_USER_PKT == (eFltType & E_TSP_FLT_USER_MASK)) ||
3749 (E_TSP_FLT_USER_TTX == (eFltType & E_TSP_FLT_USER_MASK)) )
3750 {
3751 start_id = _tspFltIdMap.u32SecFltId_Start;
3752 end_id = _tspFltIdMap.u32SecFltId_End;
3753 }
3754 else
3755 {
3756 end_id = _tspFltIdMap.u32PidFltId_End;
3757 #if 0
3758 if (E_TSP_FLT_FLAG_CA & eFltType)
3759 {
3760 start_id = TSP_CAFLT_0;
3761 }
3762 else
3763 {
3764 start_id = 0;
3765 }
3766 #else
3767 start_id = _tspFltIdMap.u32PidFltId_Start;
3768 #endif
3769 }
3770
3771 if(TSP_NEED_SEC_FILTER(eFltType))
3772 {
3773 for (i = start_id; i < end_id; i++) // check which filter is free
3774 {
3775 if (_ptsp_res->_tspInfo.FltState[i] == E_TSP_FLT_STATE_FREE)
3776 {
3777 //if TSP support PCR hardware , we don't use section filter to capture PCR from TS packet
3778 //otherwise , try to allocate it
3779 #if HW_PCRFLT_ENABLE
3780 if(_tspFltIdMap.u32PcrFltId_Start <= start_id)
3781 {
3782 break;
3783 }
3784 #endif
3785 pSecFlt = &(_REGSec->Flt[i]);
3786 if (HAL_TSP_SecFlt_TryAlloc(pSecFlt, (MS_U16)u32TSPId))
3787 {
3788 break;
3789 }
3790 }
3791 }
3792 if (i >= end_id)
3793 {
3794 TSP_DBG(E_TSP_DBG_ERROR, "[%04d] No free fitler found 0x%02x\n", __LINE__, (MS_U32)i);
3795 TSP_RETURN(E_TSP_FAIL);
3796 }
3797
3798 #ifdef MSOS_TYPE_LINUX_KERNEL
3799 MS_U32 u32ii;
3800
3801 for(u32ii = 0; u32ii < DRVTSP_MAX_PROCESS_NUM; u32ii++)
3802 {
3803 if(_u32KPrcEvtTblUseFlag & (1 << u32ii))
3804 {
3805 if(_stKModePrcEvtTbl[u32ii].tgid == current->tgid)
3806 {
3807 _ptsp_res->_tspInfo.s32TspEvtId[i] = _stKModePrcEvtTbl[u32ii].s32TspEvtId;
3808 break;
3809 }
3810 }
3811 }
3812 #else
3813 _ptsp_res->_tspInfo.s32TspEvtId[i] = _s32EventId;
3814 #endif
3815 }
3816 else
3817 {
3818 for (i = end_id - 1; i >= start_id; i--) // check which filter is free, allocate from back
3819 if (_ptsp_res->_tspInfo.FltState[i] == E_TSP_FLT_STATE_FREE)
3820 break;
3821 //when section filters are less than PID filters
3822 #if (TSP_SECFLT_END_ID != TSP_PIDFLT_REC_NUM) // for coverity
3823 if ((i < _tspFltIdMap.u32SecFltId_End) && (_tspFltIdMap.u32SecFltId_End < _tspFltIdMap.u32PidFltId_End))
3824 #else
3825 if (i < _tspFltIdMap.u32SecFltId_End)
3826 #endif
3827 {
3828 TSP_DBG(E_TSP_DBG_ERROR, "[%04d] Warning, PID filter 0x%02x for section is allocated for non-section usage. \n", __LINE__, (MS_U32)i);
3829 }
3830 if (i < start_id)
3831 {
3832 TSP_DBG(E_TSP_DBG_ERROR, "[%04d] No free fitler found 0x%02x\n", __LINE__, (MS_U32)i);
3833 TSP_RETURN(E_TSP_FAIL);
3834 }
3835 }
3836
3837
3838 //[NOTE] Referace the comment of definition of _ptsp_res->_Current_Live.
3839 #if 0 //@F_TODO do we have to support this here?
3840 if ((eFltType & E_TSP_FLT_SRC_TSIF0) && (_ptsp_res->_Current_Live != E_TSP_FLT_SRC_TSIF0)) // if current live not @ playback channel
3841 {
3842 if (FALSE == (E_TSP_FLT_FIFO_MASK & eFltType )) // For A/V/PCR are always belone to channel playback.
3843 {
3844 eFltType = (eFltType & ~E_TSP_FLT_SRC_MASK) | _ptsp_res->_Current_Live ;
3845 }
3846 }
3847 #endif
3848
3849 _ptsp_res->_tspInfo.FltType[i] = eFltType;
3850
3851 _TSP_FLT_Init(i);
3852
3853 if ( E_TSP_FLT_USER_PCR == (eFltType & E_TSP_FLT_USER_MASK) )
3854 {
3855 _TSP_STC_SetPcrFlt(u32StcEng, (MS_U32)i);
3856 }
3857
3858 _ptsp_res->_tspInfo.FltState[i] = E_TSP_FLT_STATE_ALLOC;
3859 _ptsp_res->_tspInfo.OwnerId[i] = (EN_TSP_Id)u32TSPId;
3860
3861 // Select FLT in
3862 //pPidFlt = &(_REGPid->Flt[i]);
3863
3864 MS_U32 u32FltSrc = E_TSP_FLT_SRC_MASK & eFltType;
3865 TSP_PIDFLT_SRC eTspPidSrc = _TSP_DrvHal_FltSrcMapping(u32FltSrc);
3866 MS_U32 u32PktDmx = HAL_TSP_FltSrc2PktDmx_Mapping(eTspPidSrc);
3867
3868 TSP_RES_ALLOC_TSPPATH_CHECK(u32PktDmx);
3869
3870 //if TSP support PCR hardware , we don't use section filter to capture PCR from TS packet
3871 //otherwise , set source paket demux of section filter
3872 #if HW_PCRFLT_ENABLE
3873 if(E_TSP_FLT_USER_PCR != (eFltType & E_TSP_FLT_USER_MASK))
3874 #endif
3875 HAL_TSP_PidFlt_SetFltIn(i,u32PktDmx);
3876
3877 #ifdef MERGE_STR_SUPPORT
3878 {
3879 MS_U32 u32SrcId = (eFltType & E_TSP_FLT_SRCID_MASK) >> E_TSP_FLT_SRCID_SHIFT;
3880
3881 if(u32SrcId >= TSP_MERGESTREAM_NUM)
3882 {
3883 TSP_DBG(E_TSP_DBG_MUST,"[%s][%d] Stream index out of range!!\n",__FUNCTION__,__LINE__);
3884 }
3885
3886 #if HW_PCRFLT_ENABLE
3887 if(E_TSP_FLT_USER_PCR == (eFltType & E_TSP_FLT_USER_MASK))
3888 {
3889 if ((i >= HAL_TSP_PCRFLT_GET_ID(0)) && (i <= HAL_TSP_PCRFLT_GET_ID(TSP_PCRFLT_NUM - 1)))
3890 {
3891 MS_U32 u32PcrId = i - _tspFltIdMap.u32PcrFltId_Start;;
3892
3893 HAL_TSP_PcrFlt_SetSrcId(u32PcrId, u32SrcId);
3894 }
3895 }
3896 else
3897 #endif // end HW_PCRFLT_ENABLE
3898 {
3899 HAL_TSP_PidFlt_SetSrcID(i,u32SrcId);
3900 }
3901 }
3902 #endif // end MERGE_STR_SUPPORT
3903
3904
3905 // Select FLT out
3906 // MDrv_TSP_FLT_Enable
3907
3908 // Set FLT_USR Type
3909 type = E_TSP_FLT_USER_MASK & _ptsp_res->_tspInfo.FltType[i];
3910 if (type)
3911 {
3912 switch (type)
3913 {
3914 case E_TSP_FLT_USER_SEC:
3915 case E_TSP_FLT_USER_PES:
3916 case E_TSP_FLT_USER_PKT:
3917 case E_TSP_FLT_USER_TTX:
3918 HAL_TSP_SecFlt_SetType(pSecFlt, type >> E_TSP_FLT_USER_SHFT);
3919 break;
3920 case E_TSP_FLT_USER_PCR:
3921 //if TSP support PCR hardware , we don't use section filter to capture PCR from TS packet
3922 //otherwise , set operation type of section filter to PCR
3923 #if !HW_PCRFLT_ENABLE
3924 HAL_TSP_SecFlt_SetType(pSecFlt, type >> E_TSP_FLT_USER_SHFT);
3925 #endif
3926 break;
3927 // Non-SECFLT allocated : PIDFLT & special FLT only
3928 case E_TSP_FLT_USER_EMM:
3929 case E_TSP_FLT_USER_ECM:
3930 // select no section type;
3931 HAL_TSP_SecFlt_SetType(pSecFlt, 0);
3932 break;
3933 #if defined(__LEGACY__)
3934 case E_TSP_FLT_USER_OAD:
3935 #endif
3936 default:
3937 TSP_DBG(E_TSP_DBG_WARNING, "[%04d] Unsupport FlType = %x\n", __LINE__, type);
3938 HAL_TSP_SecFlt_SetType(pSecFlt, 0);
3939 break;
3940 }
3941 }
3942
3943 *pu32FltId = i;
3944 TSP_RETURN(E_TSP_OK);
3945 }
3946
3947
3948 //-------------------------------------------------------------------------------------------------
3949 /// Free a PID filter of a TSP unit
3950 /// @param u32EngId \b IN: index of TSP engine [ 0 .. (@ref DRVTSP_ENGINE_NUM-1) ]
3951 /// @param u32PidFltId \b IN: index of PID filter to be free
3952 /// @return TSP_Result
3953 //-------------------------------------------------------------------------------------------------
MDrv_TSP_FLT_Free(MS_U32 u32FltId)3954 TSP_Result MDrv_TSP_FLT_Free(MS_U32 u32FltId)
3955 {
3956 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
3957 TSP_CHECK(_tspFltIdMap.u32PidFltIdAll > u32FltId, "[%04d] Invalid u32FltId %d\n", __LINE__, (unsigned int)u32FltId);
3958 //We do nothing when create dmx flt to record
3959 //HAL_TSP_GetCaps(E_TSP_HAL_CAP_TYPE_RECFLT_IDX, &u32RecFltIdx);
3960 if(u32FltId == _tspFltIdMap.u32RecFltIdx)
3961 return E_TSP_OK;
3962
3963 MS_U32 flags;
3964 // NO Blocking check in blocking TSP_FLT_Free
3965 // TSP_ENTRY();
3966
3967 if (E_TSP_FLT_STATE_FREE == _ptsp_res->_tspInfo.FltState[u32FltId])
3968 {
3969 TSP_DBG(E_TSP_DBG_FAIL, "[%04d] Invalid Filter\n", __LINE__);
3970 return E_TSP_OK ;
3971 }
3972
3973 // The conditon is used to distinguish the u32FltId is section filter or not.
3974 // Here we free all filter type except section filter, including stream filters, PCR filters, etc.
3975 // Free non-section filter do not call _TSP_FLT_Free
3976 if(u32FltId >= _tspFltIdMap.u32SecFltId_End)
3977 {
3978 TSP_LOCK();
3979 _TSP_FLT_Disable(u32FltId); // disable output
3980 _TSP_FLT_Init(u32FltId); // reset pid & status
3981
3982 if ((_ptsp_res->_tspInfo.FltType[u32FltId]& E_TSP_FLT_USER_MASK)== E_TSP_FLT_USER_PCR)
3983 {
3984 MS_U32 u32STCEng;
3985
3986 if(_TSP_PcrId_To_StcId(u32FltId, &u32STCEng) == E_TSP_OK)
3987 {
3988 _TSP_STC_Free(u32STCEng);
3989 }
3990 }
3991
3992 _ptsp_res->_tspInfo.OwnerId[u32FltId] = E_TSP_ID_NULL;
3993 _ptsp_res->_tspInfo.FltState[u32FltId] = E_TSP_FLT_STATE_FREE;
3994 _ptsp_res->_tspInfo.FltType[u32FltId] = E_TSP_FLT_USER_NULL;
3995 _ptsp_res->_tspInfo.s32TspEvtId[u32FltId] = -1;
3996 TSP_UNLOCK();
3997 return E_TSP_OK ;
3998 }
3999
4000 // Free section filter need to call _TSP_FLT_Free
4001 if (E_TSP_EVENT_CB_POLL == (_ptsp_res->_tspInfo.FltEvent[u32FltId] & E_TSP_EVENT_CB_MASK))
4002 {
4003 TSP_LOCK();
4004 _TSP_FLT_Disable(u32FltId); // disable output
4005 _TSP_FLT_Init(u32FltId); // reset pid & status
4006 _TSP_FLT_Free(u32FltId);
4007 TSP_UNLOCK();
4008 TSP_FLAG_GetFltDis(u32FltId, &flags, TSP_OS_EVENT_OR_CLEAR);
4009 TSP_FLAG_GetSecOvf(u32FltId, &flags, TSP_OS_EVENT_OR_CLEAR);
4010 TSP_FLAG_GetSecRdy(u32FltId, &flags, TSP_OS_EVENT_OR_CLEAR);
4011
4012 }
4013 else if (E_TSP_EVENT_CB_AUTO == (_ptsp_res->_tspInfo.FltEvent[u32FltId] & E_TSP_EVENT_CB_MASK))
4014 {
4015 if (_ptsp_res->_tspInfo.FltState[u32FltId] == E_TSP_FLT_STATE_ISR_FREE)
4016 {
4017 // it's freeing
4018 }
4019 else
4020 {
4021 TSP_LOCK();
4022 _ptsp_res->_tspInfo.FltState[u32FltId] = E_TSP_FLT_STATE_ISR_FREE;
4023 TSP_UNLOCK();
4024
4025 // Add to FREE list
4026 TSP_FLAG_SetFree(u32FltId);
4027 }
4028 // Wakeup Task
4029 TSP_SetEvent(_ptsp_res->_tspInfo.s32TspEvtId[u32FltId], TSP_EVENT_FREEFLT);
4030
4031 //Since MApi_DMX_Close() already has a mechanism to wait free done without continuously blocking the mutex.
4032 //Here we only return the result of free event is finished or not to MApi_DMX_Close().
4033 if (FALSE == TSP_FLAG_GetDone(u32FltId, &flags, TSP_OS_EVENT_OR_CLEAR))
4034 {
4035 return E_TSP_FAIL;
4036 }
4037
4038 //To avoid the filter being allocated during ISR free process,
4039 //_TSP_FLT_Init and _TSP_FLT_Free are moved from ISR free process to here.
4040 //During the ISR free process, we use E_TSP_FLT_STATE_ISR_FREE instead of E_TSP_FLT_STATE_FREE to indicate a freeing filter.
4041 TSP_LOCK();
4042 _TSP_FLT_Init(u32FltId); // reset pid & status
4043 _TSP_FLT_Free(u32FltId);
4044 TSP_UNLOCK();
4045 }
4046 else
4047 {
4048 TSP_DBG(E_TSP_DBG_MUST,"[DMX_ERR][%s][%d] Free flt error!\n", __FUNCTION__,__LINE__);
4049 }
4050
4051
4052 // NO Blocking check in blocking TSP_FLT_Free
4053 // TSP_RETURN(E_TSP_OK);
4054 return E_TSP_OK;
4055 }
4056
4057
4058 //-------------------------------------------------------------------------------------------------
4059 /// Select section filter of PID filter
4060 /// @param u32EngId \b IN: index of TSP engine [ 0 .. (@ref DRVTSP_ENGINE_NUM-1) ]
4061 /// @param u32PidFltId \b IN: index of PID filter\n
4062 /// @param u32SecFltId \b IN: index of section filter
4063 /// @return TSP_Result
4064 /// @note
4065 /// The PID filter and section filter pair is one-to-one mapping. User has to
4066 /// allocate other PID filters if user have more than one section filter for same
4067 /// PID packet.\n
4068 /// @sa MDrv_TSP_PidFlt_Alloc
4069 //-------------------------------------------------------------------------------------------------
MDrv_TSP_FLT_SelSEC(MS_U32 u32FltId,MS_U32 u32BufId)4070 TSP_Result MDrv_TSP_FLT_SelSEC(MS_U32 u32FltId, MS_U32 u32BufId)
4071 {
4072 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
4073 TSP_CHECK(_tspFltIdMap.u32PidFltIdAll > u32FltId, "[%04d] Invalid u32FltId %d\n", __LINE__, (unsigned int)u32FltId);
4074
4075 //HAL_TSP_GetCaps(E_TSP_HAL_CAP_TYPE_RECFLT_IDX, &u32RecFltIdx);
4076 if(u32FltId == _tspFltIdMap.u32RecFltIdx)
4077 {
4078 _ptsp_res->u32RecFltBufId = u32BufId;
4079 return E_TSP_OK;
4080 }
4081
4082 TSP_ENTRY();
4083 if ( (E_TSP_FLT_STATE_FREE == _ptsp_res->_tspInfo.FltState[u32FltId]) ||
4084 (E_TSP_FLT_USER_PCR == (_ptsp_res->_tspInfo.FltType[u32FltId] & E_TSP_FLT_USER_MASK)) )
4085 {
4086 TSP_DBG(E_TSP_DBG_FAIL, "[%04d] Invalid Filter\n", __LINE__);
4087 TSP_RETURN(E_TSP_FAIL_INVALID);
4088 }
4089
4090 HAL_TSP_SecFlt_SelSecBuf(&(_REGSec->Flt[u32FltId]), u32BufId);
4091
4092 _ptsp_res->_tspInfo.Flt2Buf[u32FltId] = u32BufId;
4093
4094 _ptsp_res->_tspInfo.MulFlt2Buf[u32BufId] += 1;
4095
4096 _ptsp_res->_tspInfo.Buf2Flt[u32BufId] = u32FltId;
4097 //ULOGD("TSP", "[%s] MulFlt2Buf %ld = %d \n",__FUNCTION__ ,u32BufId ,_ptsp_res->_tspInfo.MulFlt2Buf[u32BufId]);
4098
4099 TSP_RETURN(E_TSP_OK);
4100 }
4101
4102
4103 ///RESERVED
MDrv_TSP_FLT_GetSEC(MS_U32 u32FltId,MS_U32 * pu32BufId)4104 TSP_Result MDrv_TSP_FLT_GetSEC(MS_U32 u32FltId, MS_U32 *pu32BufId)
4105 {
4106 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
4107 TSP_CHECK(_tspFltIdMap.u32PidFltIdAll > u32FltId, "[%04d] Invalid u32FltId %d\n", __LINE__, (unsigned int)u32FltId);
4108
4109 //HAL_TSP_GetCaps(E_TSP_HAL_CAP_TYPE_RECFLT_IDX, &u32RecFltIdx);
4110 if(u32FltId == _tspFltIdMap.u32RecFltIdx)
4111 {
4112 *pu32BufId = _ptsp_res->u32RecFltBufId;
4113 return E_TSP_OK;
4114 }
4115
4116 TSP_ENTRY();
4117 if ( (E_TSP_FLT_STATE_FREE == _ptsp_res->_tspInfo.FltState[u32FltId]) ||
4118 (E_TSP_FLT_USER_PCR == (_ptsp_res->_tspInfo.FltType[u32FltId] & E_TSP_FLT_USER_MASK)) )
4119 {
4120 TSP_DBG(E_TSP_DBG_FAIL, "[%04d] Invalid Filter\n", __LINE__);
4121 TSP_RETURN(E_TSP_FAIL_INVALID);
4122 }
4123
4124 //u32BufId = _ptsp_res->_tspInfo.Flt2Buf[u32Fltid];
4125 *pu32BufId = (MS_U32)HAL_TSP_SecFlt_GetSecBuf(&(_REGSec->Flt[u32FltId]));
4126
4127 TSP_RETURN(E_TSP_OK);
4128 }
4129 ///RESERVED
4130
MDrv_TSP_FLT_SetPCRSrc(MS_U32 u32FltId,MS_U32 u32PCRSrc)4131 TSP_Result MDrv_TSP_FLT_SetPCRSrc(MS_U32 u32FltId,MS_U32 u32PCRSrc)
4132 {
4133 // @TODO need to take care PCR SRC from MM here
4134 MS_U32 u32FltSrc = E_TSP_FLT_SRC_MASK & u32PCRSrc;
4135 TSP_PIDFLT_SRC ePidFltSrc = _TSP_DrvHal_FltSrcMapping(u32FltSrc);
4136 TSP_PCR_SRC ePcrSrc = HAL_TSP_FltSrc2PCRSrc_Mapping(ePidFltSrc);
4137
4138 TSP_ENTRY();
4139
4140 if ((u32FltId >= TSP_PCRFLT_GET_ID(0)) && (u32FltId <= TSP_PCRFLT_GET_ID(TSP_PCRFLT_NUM - 1)))
4141 {
4142 HAL_TSP_PcrFlt_SetSrc((u32FltId - _tspFltIdMap.u32PcrFltId_Start), ePcrSrc);
4143 TSP_RETURN(E_TSP_OK);
4144 }
4145 else
4146 {
4147 TSP_RETURN(E_TSP_FAIL);
4148 }
4149 }
4150
MDrv_TSP_FLT_SetFltRushPass(MS_U32 u32FltId,MS_U8 u8Enable)4151 TSP_Result MDrv_TSP_FLT_SetFltRushPass(MS_U32 u32FltId, MS_U8 u8Enable)
4152 {
4153 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
4154 TSP_CHECK(_tspFltIdMap.u32PidFltIdAll > u32FltId, "[%04d] Invalid u32FltId %d\n", __LINE__, (unsigned int)u32FltId);
4155
4156 //HAL_TSP_GetCaps(E_TSP_HAL_CAP_TYPE_RECFLT_IDX, &u32RecFltIdx);
4157 if(u32FltId == _tspFltIdMap.u32RecFltIdx)
4158 return E_TSP_OK;
4159
4160 TSP_ENTRY();
4161 if ( (E_TSP_FLT_STATE_FREE == _ptsp_res->_tspInfo.FltState[u32FltId]) ||
4162 (E_TSP_FLT_USER_PCR == (_ptsp_res->_tspInfo.FltType[u32FltId] & E_TSP_FLT_USER_MASK)) )
4163 {
4164 TSP_DBG(E_TSP_DBG_FAIL, "[%04d] Invalid Filter\n", __LINE__);
4165 TSP_RETURN(E_TSP_FAIL_INVALID);
4166 }
4167
4168 HAL_TSP_PidFlt_SetFltRushPass(u32FltId, u8Enable);
4169
4170 TSP_RETURN(E_TSP_OK);
4171 }
4172
4173 //-------------------------------------------------------------------------------------------------
4174 /// Set PID to a PID filter
4175 /// @param u32EngId \b IN: index of TSP engine [ 0 .. (@ref DRVTSP_ENGINE_NUM-1) ]
4176 /// @param u32PidFltId \b IN: index of PID filter to be set
4177 /// @param u32PID \b IN: PID value
4178 /// @return TSP_Result
4179 //-------------------------------------------------------------------------------------------------
MDrv_TSP_FLT_SetPID(MS_U32 u32FltId,MS_U32 u32PID)4180 TSP_Result MDrv_TSP_FLT_SetPID(MS_U32 u32FltId, MS_U32 u32PID)
4181 {
4182 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
4183 TSP_CHECK(_tspFltIdMap.u32PidFltIdAll > u32FltId, "[%04d] Invalid u32FltId %d\n", __LINE__, (unsigned int)u32FltId);
4184
4185 //HAL_TSP_GetCaps(E_TSP_HAL_CAP_TYPE_RECFLT_IDX ,&u32RecFltIdx);
4186 if(u32FltId == _tspFltIdMap.u32RecFltIdx)
4187 {
4188 _ptsp_res->u32RecFltPID = u32PID;
4189 return E_TSP_OK;
4190 }
4191
4192 TSP_ENTRY();
4193 if (E_TSP_FLT_STATE_FREE == _ptsp_res->_tspInfo.FltState[u32FltId])
4194 {
4195 TSP_DBG(E_TSP_DBG_FAIL, "[%04d] Invalid Filter\n", __LINE__);
4196 TSP_RETURN(E_TSP_FAIL_INVALID);
4197 }
4198
4199 _ptsp_res->_tspInfo.Pid[u32FltId] = u32PID ;
4200
4201 if(u32FltId < _tspFltIdMap.u32PidFltId_End)
4202 {
4203 HAL_TSP_PidFlt_SetPid(u32FltId, u32PID);
4204 }
4205
4206 if ((_ptsp_res->_tspInfo.FltType[u32FltId]& E_TSP_FLT_USER_MASK) == E_TSP_FLT_USER_PCR )
4207 {
4208 TSP_DBG(E_TSP_DBG_MUST, "Set PCR FLT=%d PID = %8X \n\n",(unsigned int)u32FltId,(unsigned int)u32PID);
4209
4210 if ((u32FltId >= TSP_PCRFLT_GET_ID(0)) && (u32FltId <= TSP_PCRFLT_GET_ID(TSP_PCRFLT_NUM - 1)))
4211 {
4212 HAL_TSP_PcrFlt_SetPid((u32FltId - _tspFltIdMap.u32PcrFltId_Start), u32PID);
4213 //HAL_TSP_PcrFlt_Enable((u32FltId - TSP_PCRFLT_START_ID), TRUE);
4214 }
4215 else
4216 {
4217 TSP_DBG(E_TSP_DBG_MUST, "[%s][%d] Incorrect PCR filter ID !!\n",__FUNCTION__,__LINE__);
4218 }
4219 }
4220
4221 TSP_RETURN(E_TSP_OK);
4222 }
4223
4224
4225 ///RESERVED
MDrv_TSP_FLT_GetPID(MS_U32 u32FltId,MS_U32 * pu32PID)4226 TSP_Result MDrv_TSP_FLT_GetPID(MS_U32 u32FltId, MS_U32 *pu32PID)
4227 {
4228 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
4229 TSP_CHECK(_tspFltIdMap.u32PidFltIdAll > u32FltId, "[%04d] Invalid u32FltId %d\n", __LINE__, (unsigned int)u32FltId);
4230
4231 // HAL_TSP_GetCaps(E_TSP_HAL_CAP_TYPE_RECFLT_IDX, &u32RecFltIdx);
4232 if(u32FltId == _tspFltIdMap.u32RecFltIdx)
4233 {
4234 *pu32PID = _ptsp_res->u32RecFltPID;
4235 return E_TSP_OK;
4236 }
4237
4238 TSP_ENTRY();
4239 if (E_TSP_FLT_STATE_FREE == _ptsp_res->_tspInfo.FltState[u32FltId])
4240 {
4241 TSP_DBG(E_TSP_DBG_FAIL, "[%04d] Invalid Filter\n", __LINE__);
4242 TSP_RETURN(E_TSP_FAIL_INVALID);
4243 }
4244 else
4245 {
4246 #if HW_PCRFLT_ENABLE
4247 if((_ptsp_res->_tspInfo.FltType[u32FltId]& E_TSP_FLT_USER_MASK) == E_TSP_FLT_USER_PCR)
4248 {
4249 if ((u32FltId >= HAL_TSP_PCRFLT_GET_ID(0)) && (u32FltId <= HAL_TSP_PCRFLT_GET_ID(TSP_PCRFLT_NUM - 1)))
4250 {
4251 *pu32PID = HAL_TSP_PcrFlt_GetPid(u32FltId - _tspFltIdMap.u32PcrFltId_Start);
4252 }
4253 }
4254 else
4255 #endif
4256 {
4257 *pu32PID = HAL_TSP_PidFlt_GetPid(&(_REGPid0->Flt[u32FltId]));
4258 }
4259 }
4260
4261 if (_ptsp_res->_tspInfo.Pid[u32FltId] != *pu32PID)
4262 TSP_OS_Print("[%s] Sw/Hw conflict => Pid Value mismatch \n",__FUNCTION__);
4263
4264 TSP_RETURN(E_TSP_OK);
4265 }
4266
4267 ///RESERVED
4268
4269
4270 //-------------------------------------------------------------------------------------------------
4271 // Set section filtering mode
4272 // @param u32EngId \b IN: index of TSP engine [ 0 .. (@ref DRVTSP_ENGINE_NUM-1) ]
4273 // @param u32SecFltId \b IN: section filter of TSP to be free
4274 // @param eSecFltMode \b IN: continue/one-shot mode of section filter
4275 // @return TSP_Result
4276 // @attention
4277 // One-shot filter has the disadvantage of interrupt lost becuase it stops filter, a timeout
4278 // to check filter status is better for usage.
4279 //-------------------------------------------------------------------------------------------------
MDrv_TSP_FLT_SetMode(MS_U32 u32FltId,TSP_FltMode eFltMode)4280 TSP_Result MDrv_TSP_FLT_SetMode(MS_U32 u32FltId, TSP_FltMode eFltMode)
4281 {
4282 MS_U32 uMode = 0;
4283
4284 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
4285 TSP_CHECK(_tspFltIdMap.u32SecFltId_End > u32FltId, "[%04d] Invalid u32FltId %d\n", __LINE__, (unsigned int)u32FltId);
4286
4287 TSP_ENTRY();
4288 if (E_TSP_FLT_STATE_FREE == _ptsp_res->_tspInfo.FltState[u32FltId])
4289 {
4290 TSP_DBG(E_TSP_DBG_FAIL, "[%04d] Invalid Filter\n", __LINE__);
4291 TSP_RETURN(E_TSP_FAIL_INVALID);
4292 }
4293
4294 if((eFltMode & E_TSP_FLT_MODE_CRCCHK) && (eFltMode & E_TSP_FLT_MODE_AUTO_CRCCHK))
4295 {
4296 TSP_DBG(E_TSP_DBG_WARNING, "[%04d] E_TSP_FLT_MODE_CRCCHK and E_TSP_FLT_MODE_AUTO_CRCCHK can't be set together. \n", __LINE__);
4297 TSP_RETURN(E_TSP_FAIL_INVALID);
4298 }
4299
4300 if (eFltMode & E_TSP_FLT_MODE_ONESHOT)
4301 {
4302 uMode |= TSP_SECFLT_MODE_ONESHOT;
4303 }
4304
4305 if (eFltMode & E_TSP_FLT_MODE_CRCCHK)
4306 {
4307 uMode |= TSP_SECFLT_MODE_CRCCHK;
4308 }
4309
4310 if (eFltMode & E_TSP_FLT_MODE_AUTO_CRCCHK)
4311 HAL_TSP_SecFlt_SetAutoCRCChk(&(_REGSec->Flt[u32FltId]), TRUE);
4312 else
4313 HAL_TSP_SecFlt_SetAutoCRCChk(&(_REGSec->Flt[u32FltId]), FALSE);
4314
4315 _ptsp_res->_tspInfo.FltMode[u32FltId] = eFltMode;
4316
4317 HAL_TSP_SecFlt_SetMode(&(_REGSec->Flt[u32FltId]), uMode);
4318
4319 TSP_RETURN(E_TSP_OK);
4320 }
4321
4322
4323 //-------------------------------------------------------------------------------------------------
4324 /// Set Match/Mask filter pattern of section filter
4325 /// @param u32EngId \b IN: index of TSP engine [ 0 .. (@ref DRVTSP_ENGINE_NUM-1) ]
4326 /// @param u32SecFltId \b IN: index of filter to be set pattern
4327 /// @param pu8Match \b IN: pointer of filter pattern (in @ref DRVTSP_FILTER_DEPTH bytes)
4328 /// @param pu8Mask \b IN: pointer of pattern bitmask (in @ref DRVTSP_FILTER_DEPTH bytes)
4329 /// @param bNotMatch \b IN: negative the result of comparion of filter
4330 /// @return TSP_Result
4331 /// note: match mask -- must set 0 to be compare (customer request)
4332 /// not match mask -- must set 1 to compare
4333 //-------------------------------------------------------------------------------------------------
MDrv_TSP_FLT_SetMatch(MS_U32 u32FltId,MS_U8 * pu8Match,MS_U8 * pu8Mask,MS_U8 * pu8NMask)4334 TSP_Result MDrv_TSP_FLT_SetMatch(MS_U32 u32FltId, MS_U8 *pu8Match, MS_U8 *pu8Mask, MS_U8 *pu8NMask)
4335 {
4336 static MS_U8 mask[TSP_FILTER_DEPTH];
4337 int i;
4338
4339 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
4340
4341 TSP_CHECK(_tspFltIdMap.u32SecFltId_End > u32FltId, "[%04d] Invalid u32FltId %d\n", __LINE__, (unsigned int)u32FltId);
4342
4343 TSP_CHECK(pu8Match, "[%04d] Invalid Match Pointer\n", __LINE__);
4344 TSP_CHECK(pu8Mask, "[%04d] Invalid Mask Pointer\n", __LINE__);
4345 TSP_CHECK(pu8NMask, "[%04d] Invalid NMask Pointer\n", __LINE__);
4346
4347 TSP_ENTRY();
4348 if (E_TSP_FLT_STATE_FREE == _ptsp_res->_tspInfo.FltState[u32FltId])
4349 {
4350 TSP_DBG(E_TSP_DBG_FAIL, "[%04d] Invalid Filter\n", __LINE__);
4351 TSP_RETURN(E_TSP_FAIL_INVALID);
4352 }
4353
4354 for (i = 0 ; i < TSP_FILTER_DEPTH ; i++)
4355 { // invert the mask for HW specified
4356 //*((MS_U32*)(mask+(i<<2))) = ~(*((MS_U32*)(pu8Mask+(i<<2))));
4357 mask[i] = ~pu8Mask[i];
4358 }
4359
4360 HAL_TSP_SecFlt_SetMask (&(_REGSec->Flt[u32FltId]), mask);
4361 HAL_TSP_SecFlt_SetMatch(&(_REGSec->Flt[u32FltId]), pu8Match);
4362 HAL_TSP_SecFlt_SetNMask(&(_REGSec->Flt[u32FltId]), pu8NMask);
4363
4364 TSP_RETURN(E_TSP_OK);
4365 }
4366
4367
4368 //-------------------------------------------------------------------------------------------------
4369 /// Subscribe event notification callback function for specified section filter
4370 /// @param u32EngId \b IN: index of TSP engine [ 0 .. (@ref DRVTSP_ENGINE_NUM-1) ]
4371 /// @param u32SecFltId \b IN: index of section buffer
4372 /// @param eEvents \b IN: events need to be subscribed\n
4373 /// @ref E_TSP_EVENT_DATA_READY\n
4374 /// @ref E_TSP_EVENT_BUF_OVERFLOW
4375 /// @param pfCallback \b IN: callback function (NULL to disable)
4376 /// @return TSP_Result
4377 /// @note
4378 /// This function register a callback function for a section filter to TSP.
4379 /// TSP calls callback function each time when data is ready in section buffer.\n
4380 /// Data ready of section filter:\n
4381 /// @ref E_TSP_FLT_TYPE_SECTION : a section ready\n
4382 /// @ref E_TSP_FLT_TYPE_PES : PES packet ready or received data over than request size.
4383 /// @sa MDrv_TSP_SecFlt_SetReqCount
4384 /// @attention
4385 /// Callback function resides in OS TSP interrupt context, it recommends
4386 /// that callback function should not take too much time to block the system.
4387 //-------------------------------------------------------------------------------------------------
MDrv_TSP_FLT_SetCallback(MS_U32 u32FltId,TSP_Event eEvents,P_TSP_Callback pfCallback)4388 TSP_Result MDrv_TSP_FLT_SetCallback(MS_U32 u32FltId, TSP_Event eEvents, P_TSP_Callback pfCallback)
4389 {
4390 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
4391
4392 TSP_CHECK(_tspFltIdMap.u32SecFltId_End > u32FltId, "[%04d] Invalid u32FltId %d\n", __LINE__, (unsigned int)u32FltId);
4393
4394 TSP_ENTRY();
4395
4396 if ((eEvents & (E_TSP_EVENT_DATA_READY | E_TSP_EVENT_BUF_OVERFLOW)) == 0)
4397 {
4398 TSP_RETURN(E_TSP_FAIL_PARAMETER);
4399 }
4400
4401 _ptsp_res->_tspInfo.FltEvent[u32FltId] = eEvents;
4402 _ptsp_res->_tspInfo.FltCallback[u32FltId] = pfCallback;
4403
4404 if (E_TSP_EVENT_CB_AUTO == (_ptsp_res->_tspInfo.FltEvent[u32FltId] & E_TSP_EVENT_CB_MASK))
4405 {
4406 TSP_FLAG_SetModeFlags(u32FltId);
4407 }
4408
4409 TSP_RETURN(E_TSP_OK);
4410 }
4411
_MDrv_TSP_FLT_Enable(MS_U32 u32FltId,MS_BOOL bEnable)4412 TSP_Result _MDrv_TSP_FLT_Enable(MS_U32 u32FltId, MS_BOOL bEnable)
4413 {
4414 REG_SecFlt * pSecFlt = NULL;
4415 REG_SecBuf * pSecBuf = NULL;
4416 MS_U32 type;
4417 TSP_PIDFLT_SRC ePidFltSrc = E_TSP_PIDFLT_INVALID;
4418 MS_U32 u32Src, u32PvrLutDest = 0;
4419 MS_U16 u16BufId = 0;
4420 MS_U32 dummy;
4421
4422 // Enable PVR I Frame LUT.
4423 if( E_TSP_DST_IFRAME_LUT & _ptsp_res->_tspInfo.FltType[u32FltId])
4424 u32PvrLutDest = TSP_PIDFLT_OUT_LUT;
4425
4426 //HAL_TSP_GetCaps(E_TSP_HAL_CAP_TYPE_RECFLT_IDX, &u32RecFltIdx);
4427 if(u32FltId == _tspFltIdMap.u32RecFltIdx)
4428 return E_TSP_OK;
4429
4430 if(u32FltId < _tspFltIdMap.u32SecFltId_End)
4431 {
4432 TSP_FLAG_GetFltDis(u32FltId, &dummy, TSP_OS_EVENT_OR_CLEAR);
4433
4434 if (bEnable) //clear all filter event.
4435 {
4436 // MsOS_DelayTask(1); //[Note] For VQ flush,
4437 TSP_FLAG_GetSecRdy(u32FltId, &dummy, TSP_OS_EVENT_OR_CLEAR);
4438 TSP_FLAG_GetSecOvf(u32FltId, &dummy, TSP_OS_EVENT_OR_CLEAR);
4439 TSP_FLAG_GetCrcErr(u32FltId, &dummy, TSP_OS_EVENT_OR_CLEAR);
4440 TSP_FLAG_GetFltDis(u32FltId, &dummy, TSP_OS_EVENT_OR_CLEAR);
4441 TSP_FLAG_ClrOvfRst(u32FltId);
4442 }
4443 }
4444
4445
4446
4447 if (E_TSP_FLT_STATE_FREE == _ptsp_res->_tspInfo.FltState[u32FltId])
4448 {
4449 TSP_DBG(E_TSP_DBG_FAIL, "[%04d] Invalid Filter\n", __LINE__);
4450 return E_TSP_FAIL_INVALID;
4451 }
4452
4453 // TSP_FLT_Disable
4454 if (!bEnable)
4455 {
4456 if (_ptsp_res->_tspInfo.FltState[u32FltId] & E_TSP_FLT_STATE_ENABLE) // if enable
4457 {
4458 _TSP_FLT_Disable(u32FltId);
4459 }
4460 // TSP_DBG(E_TSP_DBG_FAIL, "[TSP_WARNNING][%04d] Enable an active PidFlt %d\n", __LINE__, u32FltId);
4461
4462 return E_TSP_OK;
4463 }
4464
4465 // TSP_FLT_Enable
4466 //connect avfifo to pid flt~
4467 u32Src = E_TSP_FLT_SRC_MASK & _ptsp_res->_tspInfo.FltType[u32FltId];
4468 ePidFltSrc = _TSP_DrvHal_FltSrcMapping(u32Src);
4469 u32Src = HAL_TSP_FltSrc2PktDmx_Mapping(ePidFltSrc);
4470
4471 TSP_RES_ALLOC_TSPPATH_CHECK(u32Src);
4472
4473 type = E_TSP_FLT_FIFO_MASK & _ptsp_res->_tspInfo.FltType[u32FltId];
4474
4475 if (type)
4476 {
4477 switch (type)
4478 {
4479 case E_TSP_FLT_FIFO_VIDEO ... E_TSP_FLT_FIFO_VIDEO8:
4480 HAL_TSP_FIFO_SetSrc((TSP_DST_SEQ)(E_TSP_DST_FIFO_VIDEO + (type - E_TSP_FLT_FIFO_VIDEO)), u32Src);
4481 HAL_TSP_PidFlt_SetFltOut(u32FltId, HAL_TSP_PidFltDstMapping(E_TSP_PIDFLT_DST_VIDEO, (type - E_TSP_FLT_FIFO_VIDEO)));
4482 break;
4483 case E_TSP_FLT_FIFO_AUDIO ... E_TSP_FLT_FIFO_AUDIO6:
4484 HAL_TSP_FIFO_SetSrc((TSP_DST_SEQ)(E_TSP_DST_FIFO_AUDIO + (type - E_TSP_FLT_FIFO_AUDIO)), u32Src);
4485 HAL_TSP_PidFlt_SetFltOut(u32FltId, HAL_TSP_PidFltDstMapping(E_TSP_PIDFLT_DST_AUDIO, (type - E_TSP_FLT_FIFO_AUDIO)));
4486 break;
4487 case E_TSP_FLT_FIFO_REC:
4488 // @F_TODO for old style. we might have to check the filter source and it's destination
4489 break;
4490 case E_TSP_FLT_FIFO_PVR ... E_TSP_FLT_FIFO_PVR9:
4491 HAL_TSP_PidFlt_SetFltOut(u32FltId, HAL_TSP_PidFltDstMapping(E_TSP_PIDFLT_DST_PVR, (type - E_TSP_FLT_FIFO_PVR)) | u32PvrLutDest);
4492 break;
4493
4494 default:
4495 // TSP_DBG(E_TSP_DBG_MUST, "[%04d] Wrong Destination type : %d!\n", __LINE__, type);
4496 // TSP_RETURN(E_TSP_FAIL);
4497 break;
4498 }
4499 }
4500 else
4501 {
4502 type = E_TSP_FLT_USER_MASK & _ptsp_res->_tspInfo.FltType[u32FltId];
4503 if (type)
4504 {
4505 #if 0// defined(__LEGACY__) we don't need this in kaiser we have bit to set for pvr eng
4506 if (E_TSP_FLT_FIFO_PVR == type) // @FIXME WHY??????????
4507 {
4508 TSP_DBG(0, "[%04d] Bad PidFltId %ld\n", __LINE__, u32FltId);
4509 }
4510 else
4511 #endif
4512 if(u32FltId < _tspFltIdMap.u32SecFltId_End)
4513 {
4514 pSecFlt = &(_REGSec->Flt[u32FltId]);
4515 u16BufId = HAL_TSP_SecFlt_GetSecBuf(pSecFlt);
4516 pSecBuf = &(_REGBuf->Buf[u16BufId]);
4517 }
4518
4519 //TSP_DBG(0, "[%04d] SecBufId = %d\n", __LINE__, u16BufId);
4520
4521 switch (type)
4522 {
4523 case E_TSP_FLT_USER_SEC:
4524 case E_TSP_FLT_USER_PES:
4525 case E_TSP_FLT_USER_PKT:
4526 case E_TSP_FLT_USER_TTX:
4527 if (_ptsp_res->_tspInfo.Flt2Buf[u32FltId] == TSP_FLT2BUF_NULL)
4528 {
4529 return E_TSP_FAIL_FUNCTION;
4530 }
4531 if(_ptsp_res->_tspInfo.MulFlt2Buf[u16BufId] == 1) // single filter and single buffer
4532 {
4533 HAL_TSP_SecBuf_Reset(pSecBuf);
4534 }
4535 if (E_TSP_EVENT_CB_POLL == (_ptsp_res->_tspInfo.FltEvent[u32FltId] & E_TSP_EVENT_CB_MASK))
4536 {
4537 #ifdef MSOS_TYPE_LINUX_KERNEL
4538 HAL_TSP_HCMD_SecRdyInt_Disable(u32FltId,FALSE);
4539 #else
4540 HAL_TSP_HCMD_SecRdyInt_Disable(u32FltId,TRUE);
4541 #endif
4542 }
4543 else // E_TSP_EVENT_CB_AUTO
4544 {
4545 HAL_TSP_HCMD_SecRdyInt_Disable(u32FltId,FALSE);
4546 }
4547
4548 HAL_TSP_SecFlt_ResetState(pSecFlt);
4549 HAL_TSP_SecFlt_ResetRmnCnt(pSecFlt);
4550 HAL_TSP_PidFlt_SetFltOut(u32FltId, TSP_PIDFLT_OUT_SECFLT);
4551 break;
4552 case E_TSP_FLT_USER_EMM: // @NOTE LEGACY
4553 case E_TSP_FLT_USER_ECM:
4554 HAL_TSP_PidFlt_SetFltOut(u32FltId, TSP_PIDFLT_OUT_NONE);
4555 break;
4556
4557 case E_TSP_FLT_USER_PCR:
4558 #if HW_PCRFLT_ENABLE
4559
4560 if ((u32FltId >= HAL_TSP_PCRFLT_GET_ID(0)) && (u32FltId <= HAL_TSP_PCRFLT_GET_ID(TSP_PCRFLT_NUM - 1)))
4561 {
4562 MS_U32 u32PcrId = u32FltId - _tspFltIdMap.u32PcrFltId_Start;
4563 MS_U32 u32PcrUpdateEndEn = HAL_TSP_PcrFlt_GetIntMask(u32PcrId);
4564
4565 _TSP_SetHwPcrNotifyId(u32PcrId);
4566 _ptsp_res->_u8_ResetPcr[u32PcrId] = 3;
4567 _ptsp_res->_u32_PrevStcBase[u32PcrId] = 0;
4568 _ptsp_res->_u32_PrevPllControl[u32PcrId] = 0;
4569 _ptsp_res->_u32_StcOffset[u32PcrId].u32StcOffset = 0;
4570 _ptsp_res->_u32_StcOffset[u32PcrId].bAdd = TRUE;
4571 _ptsp_res->_u32_StcUpdateCtrl[u32PcrId].bEnable = TRUE;
4572 _ptsp_res->_u32_StcUpdateCtrl[u32PcrId].bUpdateOnce = FALSE;
4573 HAL_TSP_PcrFlt_Enable(u32PcrId, TRUE);
4574 HAL_TSP_INT_Enable(u32PcrUpdateEndEn);
4575 }
4576 else
4577 {
4578 TSP_DBG(E_TSP_DBG_MUST, "[%s][%d] Incorrect PCR filter ID !!\n", __FUNCTION__, __LINE__);
4579 return E_TSP_FAIL;
4580 }
4581
4582 #else // @F_TODO i think we do not have to support SW PCR update anymore
4583 HAL_TSP_SecFlt_ResetState(pSecFlt);
4584 HAL_TSP_PidFlt_SetFltOut(u32FltId, TSP_PIDFLT_OUT_SECFLT| TSP_PIDFLT_OUT_SECAF); //@NOTE what is SECAF for???? SECAF is for those who has adaption field packet usecase: SWPCR
4585 #endif
4586 break;
4587 default:
4588 TSP_DBG(E_TSP_DBG_MUST, "[%04d] Unsupport FlType = %x\n", __LINE__, _ptsp_res->_tspInfo.FltType[u32FltId]);
4589 return E_TSP_FAIL;
4590 break;
4591 }
4592 }
4593 }
4594
4595 _ptsp_res->_tspInfo.FltState[u32FltId] |= E_TSP_FLT_STATE_ENABLE;
4596 return E_TSP_OK;
4597 }
4598
4599
4600 //-------------------------------------------------------------------------------------------------
4601 /// Enable PID filter
4602 /// @param u32EngId \b IN: index of TSP engine [ 0 .. (@ref DRVTSP_ENGINE_NUM-1) ]
4603 /// @param u32PidFltId \b IN: index of filter to be enable
4604 /// @param bEnable \b IN: TRUE(enable), FALSE(disable)
4605 /// @return TSP_Result
4606 /// @note
4607 /// When PID filter enable, the section buffer pointer will be reset to buffer start address,
4608 /// overflow condition will be resolved if exist.
4609 //-------------------------------------------------------------------------------------------------
MDrv_TSP_FLT_Enable(MS_U32 u32FltId,MS_BOOL bEnable)4610 TSP_Result MDrv_TSP_FLT_Enable(MS_U32 u32FltId, MS_BOOL bEnable)
4611 {
4612 TSP_Result eResult;
4613
4614 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
4615 TSP_CHECK(_tspFltIdMap.u32PidFltIdAll > u32FltId, "[%04d] Invalid u32FltId %d\n", __LINE__, (unsigned int)u32FltId);
4616
4617 TSP_ENTRY();
4618
4619 eResult = _MDrv_TSP_FLT_Enable(u32FltId, bEnable);
4620
4621 TSP_RETURN(eResult);
4622 }
4623
4624
4625 //[RESERVED] obsoleted
MDrv_TSP_FLT_SetOwner(MS_U32 u32EngId,MS_U32 u32FltStart,MS_U32 u32FltEnd,MS_BOOL bOwner)4626 TSP_Result MDrv_TSP_FLT_SetOwner(MS_U32 u32EngId, MS_U32 u32FltStart, MS_U32 u32FltEnd, MS_BOOL bOwner)
4627 {
4628 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
4629 return E_TSP_FAIL_NOT_SUPPORTED;
4630 }
4631
4632
4633 //[RESERVED] obsoleted
MDrv_TSP_FLT_ChkOwner(MS_U32 u32EngId,MS_U32 u32FltId)4634 TSP_Result MDrv_TSP_FLT_ChkOwner(MS_U32 u32EngId, MS_U32 u32FltId)
4635 {
4636 TSP_ENTRY();
4637
4638 if (_ptsp_res->_tspInfo.FltState[u32FltId] & E_TSP_FLT_STATE_ALLOC)
4639 {
4640 if (_ptsp_res->_tspInfo.OwnerId[u32FltId] == u32EngId)
4641 {
4642 TSP_RETURN(E_TSP_OK);
4643 }
4644 else
4645 {
4646 TSP_RETURN(E_TSP_FAIL);
4647 }
4648 }
4649 else
4650 {
4651 TSP_RETURN(E_TSP_FAIL_INVALID);
4652 }
4653 }
4654
4655
4656 //-------------------------------------------------------------------------------------------------
4657 /// Get current PID filter status
4658 /// @param u32EngId \b IN: index of TSP engine [ 0 .. (@ref DRVTSP_ENGINE_NUM-1) ]
4659 /// @param u32PidFltId \b IN: index of PID filter
4660 /// @param peState \b OUT: current ORed state flag of PID filter\n
4661 /// E_TSP_FLT_STATE_ALLOC\n
4662 /// E_TSP_FLT_STATE_ENABLE\n
4663 /// E_TSP_FLT_STATE_SCRAMBLED (last TS scrambling control status)
4664 /// @return TSP_Result
4665 //-------------------------------------------------------------------------------------------------
MDrv_TSP_FLT_GetState(MS_U32 u32FltId,TSP_FltState * pState)4666 TSP_Result MDrv_TSP_FLT_GetState(MS_U32 u32FltId, TSP_FltState *pState)
4667 {
4668 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
4669 TSP_CHECK(_tspFltIdMap.u32PidFltIdAll > u32FltId, "[%04d] Invalid u32FltId %d\n", __LINE__, (unsigned int)u32FltId);
4670 //We do nothing when create dmx flt to record
4671 //HAL_TSP_GetCaps(E_TSP_HAL_CAP_TYPE_RECFLT_IDX, &u32RecFltIdx);
4672 if(u32FltId == _tspFltIdMap.u32RecFltIdx)
4673 {
4674 *pState = E_TSP_FLT_STATE_NA;
4675 return E_TSP_OK;
4676 }
4677
4678 MS_U32 u32BufId;
4679
4680 // ALLOC / FREE / ENABLE
4681 *pState = _ptsp_res->_tspInfo.FltState[u32FltId];
4682
4683 #if 0 // HW remove scramble status register
4684 // Scramble bit status
4685 if (HAL_TSP_GetSCMB((MS_U16)u32FltId))
4686 {
4687 *pState |= E_TSP_FLT_STATE_SCRAMBLED;
4688 }
4689 #endif
4690
4691 // PidFlt Status
4692 switch (_ptsp_res->_tspInfo.FltType[u32FltId])
4693 {
4694 case E_TSP_FLT_FIFO_VIDEO ... E_TSP_FLT_FIFO_VIDEO8:
4695 case E_TSP_FLT_FIFO_AUDIO ... E_TSP_FLT_FIFO_AUDIO6:
4696 break;
4697 case E_TSP_FLT_USER_SEC:
4698 case E_TSP_FLT_USER_PES:
4699 case E_TSP_FLT_USER_PKT:
4700 case E_TSP_FLT_USER_TTX:
4701 u32BufId = HAL_TSP_SecFlt_GetSecBuf(&(_REGSec->Flt[u32FltId]));
4702 if (HAL_TSP_SecFlt_GetState(&(_REGSec->Flt[u32BufId])) & TSP_SECFLT_STATE_OVERFLOW)
4703 {
4704 *pState |= E_TSP_FLT_STATE_OVERFLOW;
4705 }
4706 if (HAL_TSP_SecBuf_GetRead(&(_REGBuf->Buf[u32BufId])) != HAL_TSP_SecBuf_GetWrite(&(_REGBuf->Buf[u32BufId])))
4707 {
4708 *pState |= E_TSP_FLT_STATE_STREAM_AVAIL;
4709 }
4710 break;
4711
4712 case E_TSP_FLT_USER_PCR:
4713 default:
4714 break;
4715 }
4716
4717 return E_TSP_OK;
4718 }
4719
4720
4721 //-------------------------------------------------------------------------------------------------
4722 /// Allocate a section filter of a PID filter
4723 /// @param u32EngId \b IN: index of TSP engine [ 0 .. (@ref DRVTSP_ENGINE_NUM-1) ]
4724 /// @param pu32SecFltId \b OUT: pointer of section filter id return
4725 /// @return TSP_Result
4726 //-------------------------------------------------------------------------------------------------
MDrv_TSP_SEC_Alloc(MS_U32 u32TSPId,MS_U32 * pu32BufId)4727 TSP_Result MDrv_TSP_SEC_Alloc(MS_U32 u32TSPId, MS_U32 *pu32BufId)
4728 {
4729 REG_SecBuf * pSecBuf;
4730 int i;
4731
4732 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
4733
4734 TSP_ENTRY();
4735
4736 *pu32BufId = 0xFFFFFFFF;
4737
4738 for (i = _tspFltIdMap.u32SecBufId_Start; i < _tspFltIdMap.u32SecBufId_End; i++)
4739 {
4740 if (_ptsp_res->_tspInfo.BufState[i] == E_TSP_FLT_STATE_FREE)
4741 {
4742 pSecBuf = &(_REGBuf->Buf[i]);
4743 if (HAL_TSP_SecBuf_TryAlloc(pSecBuf, (MS_U16)u32TSPId))
4744 {
4745 break;
4746 }
4747 }
4748 }
4749 if (i >= _tspFltIdMap.u32SecBufId_End)
4750 {
4751 TSP_DBG(E_TSP_DBG_ERROR, "[%04d] No free buffer found 0x%02x\n", __LINE__, (MS_U32)i);
4752 TSP_RETURN(E_TSP_FAIL);
4753 }
4754
4755 TSP_DBG(E_TSP_DBG_TRACK, "[%04d] SEC_Alloc BUF %d\n", __LINE__, i);
4756
4757 _ptsp_res->_tspInfo.BufState[i] = E_TSP_FLT_STATE_ALLOC;
4758 _TSP_SEC_Init(i);
4759
4760 *pu32BufId = i;
4761 _TSP_SetSecNotifyId(*pu32BufId); //for isr processing checking
4762
4763 TSP_RETURN(E_TSP_OK);
4764 }
4765
4766 //-------------------------------------------------------------------------------------------------
4767 /// Free a section filter of a PID filter
4768 /// @param u32EngId \b IN: index of TSP engine [ 0 .. (@ref DRVTSP_ENGINE_NUM-1) ]
4769 /// @param u32SecFltId \b IN: section filter of TSP to be free
4770 /// @return TSP_Result
4771 //-------------------------------------------------------------------------------------------------
MDrv_TSP_SEC_Free(MS_U32 u32BufId)4772 TSP_Result MDrv_TSP_SEC_Free(MS_U32 u32BufId)
4773 {
4774 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
4775 TSP_CHECK(_tspFltIdMap.u32SecFltId_End > u32BufId, "[%04d] Invalid u32BufId %d\n", __LINE__, (unsigned int)u32BufId);
4776
4777 TSP_ENTRY();
4778 if (_ptsp_res->_tspInfo.MulFlt2Buf[u32BufId] == 1)
4779 {
4780 if (E_TSP_FLT_STATE_FREE == _ptsp_res->_tspInfo.BufState[u32BufId])
4781 {
4782 TSP_DBG(E_TSP_DBG_FAIL, "[%04d] Invalid Buffer\n", __LINE__);
4783 TSP_DBG(E_TSP_DBG_INFO, "[%04d] Invalid Buffer %x, %x\n", __LINE__, u32BufId, _ptsp_res->_tspInfo.BufState[u32BufId]);
4784 TSP_RETURN(E_TSP_FAIL_INVALID);
4785 }
4786
4787 _TSP_SEC_Free(u32BufId);
4788 }
4789 else
4790 {
4791 _ptsp_res->_tspInfo.MulFlt2Buf[u32BufId] -= 1;
4792 }
4793
4794 //ULOGD("TSP", "[%s] MulFlt2Buf %ld = %d ", __FUNCTION__,u32BufId,_ptsp_res->_tspInfo.MulFlt2Buf[u32BufId]);
4795
4796 TSP_RETURN(E_TSP_OK);
4797
4798 }
4799
4800
4801 //-------------------------------------------------------------------------------------------------
4802 /// Set buffer start address and buffer size to section buffer
4803 /// @param u32EngId \b IN: index of TSP engine [ 0 .. (@ref DRVTSP_ENGINE_NUM-1) ]
4804 /// @param u32SecFltId \b IN: index of section buffer to be set
4805 /// @param u32StartAddr \b IN: start address of section buffer
4806 /// @param u32BufSize \b IN: size of section buffer
4807 /// @return TSP_Result
4808 /// @note
4809 /// Buffer start address and buffer size should be 128-bit (16-byte) aligned.\n
4810 /// @sa MDrv_TSP_PidFlt_Alloc
4811 //-------------------------------------------------------------------------------------------------
MDrv_TSP_SEC_SetBuffer(MS_U32 u32BufId,MS_PHYADDR u32Start,MS_U32 u32Size)4812 TSP_Result MDrv_TSP_SEC_SetBuffer(MS_U32 u32BufId, MS_PHYADDR u32Start, MS_U32 u32Size)
4813 {
4814 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
4815 TSP_CHECK(_tspFltIdMap.u32SecFltId_End > u32BufId, "[%04d] Invalid u32BufId %d\n", __LINE__, (unsigned int)u32BufId);
4816
4817 TSP_ENTRY();
4818 if (E_TSP_FLT_STATE_FREE == _ptsp_res->_tspInfo.BufState[u32BufId])
4819 {
4820 TSP_RETURN(E_TSP_FAIL_INVALID);
4821 }
4822
4823 TSP_DBG(E_TSP_DBG_TRACK, "SEC_SetBuffer addr 0x%08x, size 0x%08x\n", u32Start, u32Size);
4824
4825 if (_ptsp_res->_tspInfo.MulFlt2Buf[u32BufId] == 1)
4826 {
4827 HAL_TSP_SecBuf_SetBuf(&(_REGBuf->Buf[u32BufId]), u32Start, u32Size);
4828 }
4829
4830 TSP_RETURN(E_TSP_OK);
4831 }
4832
4833
4834 //-------------------------------------------------------------------------------------------------
4835 /// Reset the section buffer read/write pointer to start address and resolve overflow condition
4836 /// @param u32EngId \b IN: index of TSP engine [ 0 .. (@ref DRVTSP_ENGINE_NUM-1) ]
4837 /// @param u32SecFltId \b IN: index of section buffer to be reset
4838 /// @return TSP_Result
4839 //-------------------------------------------------------------------------------------------------
MDrv_TSP_SEC_Reset(MS_U32 u32BufId)4840 TSP_Result MDrv_TSP_SEC_Reset(MS_U32 u32BufId)
4841 {
4842 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
4843 TSP_CHECK(_tspFltIdMap.u32SecFltId_End > u32BufId, "[%04d] Invalid u32BufId %d\n", __LINE__, (unsigned int)u32BufId);
4844
4845 TSP_ENTRY();
4846 if (E_TSP_FLT_STATE_FREE == _ptsp_res->_tspInfo.BufState[u32BufId])
4847 {
4848 TSP_RETURN(E_TSP_FAIL_INVALID);
4849 }
4850
4851 HAL_TSP_SecBuf_Reset(&(_REGBuf->Buf[u32BufId]));
4852
4853 HAL_TSP_SecFlt_ResetRmnCnt(&(_REGSec->Flt[(_ptsp_res->_tspInfo.Buf2Flt[u32BufId])]));
4854
4855 TSP_RETURN(E_TSP_OK);
4856 }
4857
4858 //-------------------------------------------------------------------------------------------------
4859 ///[RESERVED]
4860 /// Get buffer start address of setction buffer
4861 /// @param u32EngId \b IN: index of TSP engine [ 0 .. (@ref DRVTSP_ENGINE_NUM-1) ]
4862 /// @param u32SecFltId \b IN: index of section buffer
4863 /// @param pu32BufStart \b OUT: pointer of buffer start address return
4864 /// @return TSP_Result
4865 //-------------------------------------------------------------------------------------------------
MDrv_TSP_SEC_GetStart(MS_U32 u32BufId,MS_PHY * pu32Start)4866 TSP_Result MDrv_TSP_SEC_GetStart(MS_U32 u32BufId, MS_PHY *pu32Start)
4867 {
4868 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
4869 TSP_CHECK(_tspFltIdMap.u32SecFltId_End > u32BufId, "[%04d] Invalid u32BufId %d\n", __LINE__, (unsigned int)u32BufId);
4870 TSP_CHECK(pu32Start, "[%04d] NULL pointer\n", __LINE__);
4871
4872 TSP_ENTRY();
4873 if (E_TSP_FLT_STATE_FREE == _ptsp_res->_tspInfo.BufState[u32BufId])
4874 {
4875 TSP_RETURN(E_TSP_FAIL_INVALID);
4876 }
4877
4878 *pu32Start = HAL_TSP_SecBuf_GetStart(&(_REGBuf->Buf[u32BufId]));
4879
4880 TSP_RETURN(E_TSP_OK);
4881 }
4882
4883
4884 //-------------------------------------------------------------------------------------------------
4885 ///[RESERVED]
4886 /// Get buffer size of section buffer
4887 /// @param u32EngId \b IN: index of TSP engine [ 0 .. (@ref DRVTSP_ENGINE_NUM-1) ]
4888 /// @param u32SecFltId \b IN: index of section buffer
4889 /// @param pu32BufSize \b OUT: pointer of buffer size return
4890 /// @return TSP_Result
4891 //-------------------------------------------------------------------------------------------------
MDrv_TSP_SEC_GetSize(MS_U32 u32BufId,MS_U32 * pu32Size)4892 TSP_Result MDrv_TSP_SEC_GetSize(MS_U32 u32BufId, MS_U32 *pu32Size)
4893 {
4894 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
4895 TSP_CHECK(_tspFltIdMap.u32SecFltId_End > u32BufId, "[%04d] Invalid u32BufId %d\n", __LINE__, (unsigned int)u32BufId);
4896 TSP_CHECK(pu32Size, "[%04d] NULL pointer\n", __LINE__);
4897
4898 *pu32Size = 0;
4899
4900 TSP_ENTRY();
4901 if (E_TSP_FLT_STATE_FREE == _ptsp_res->_tspInfo.BufState[u32BufId])
4902 {
4903 TSP_RETURN(E_TSP_FAIL_INVALID);
4904 }
4905
4906 *pu32Size= HAL_TSP_SecBuf_GetEnd(&(_REGBuf->Buf[u32BufId])) - HAL_TSP_SecBuf_GetStart(&(_REGBuf->Buf[u32BufId]));
4907 TSP_RETURN(E_TSP_OK);
4908 }
4909
4910
4911 //-------------------------------------------------------------------------------------------------
4912 /// Get current read address of section buffer
4913 /// @param u32EngId \b IN: index of TSP engine [ 0 .. (@ref DRVTSP_ENGINE_NUM-1) ]
4914 /// @param u32SecFltId \b IN: index of section buffer
4915 /// @param pu32ReadAddr \b OUT: pointer of address return
4916 /// @return TSP_Result
4917 //-------------------------------------------------------------------------------------------------
MDrv_TSP_SEC_GetRead(MS_U32 u32BufId,MS_PHY * pu32Read)4918 TSP_Result MDrv_TSP_SEC_GetRead(MS_U32 u32BufId, MS_PHY *pu32Read)
4919 {
4920 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
4921 TSP_CHECK(_tspFltIdMap.u32SecFltId_End > u32BufId, "[%04d] Invalid u32BufId %d\n", __LINE__, (unsigned int)u32BufId);
4922 TSP_CHECK(pu32Read, "[%04d] NULL pointer\n", __LINE__);
4923
4924 *pu32Read = 0;
4925
4926 TSP_ENTRY();
4927 if (E_TSP_FLT_STATE_FREE == _ptsp_res->_tspInfo.BufState[u32BufId])
4928 {
4929 TSP_RETURN(E_TSP_FAIL_INVALID);
4930 }
4931
4932 *pu32Read= (MS_PHY)HAL_TSP_SecBuf_GetRead(&(_REGBuf->Buf[u32BufId]));
4933 TSP_RETURN(E_TSP_OK);
4934 }
4935
4936
4937 //-------------------------------------------------------------------------------------------------
4938 /// Get current section data write address of section buffer
4939 /// @param u32EngId \b IN: index of TSP engine [ 0 .. (@ref DRVTSP_ENGINE_NUM-1) ]
4940 /// @param u32SecFltId \b IN: index of section buffer
4941 /// @param pu32WriteAddr \b OUT: pointer of address return
4942 /// @return TSP_Result
4943 /// @note
4944 /// User can get current write address to know where is the end of section data
4945 /// received in the section buffer.
4946 //-------------------------------------------------------------------------------------------------
MDrv_TSP_SEC_GetWrite(MS_U32 u32BufId,MS_PHY * pu32Write)4947 TSP_Result MDrv_TSP_SEC_GetWrite(MS_U32 u32BufId, MS_PHY *pu32Write)
4948 {
4949 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
4950 TSP_CHECK(_tspFltIdMap.u32SecFltId_End > u32BufId, "[%04d] Invalid u32BufId %d\n", __LINE__, (unsigned int)u32BufId);
4951 TSP_CHECK(pu32Write, "[%04d] NULL pointer\n", __LINE__);
4952
4953 *pu32Write = 0;
4954
4955 TSP_ENTRY();
4956 if (E_TSP_FLT_STATE_FREE == _ptsp_res->_tspInfo.BufState[u32BufId])
4957 {
4958 TSP_RETURN(E_TSP_FAIL_INVALID);
4959 }
4960
4961 *pu32Write= (MS_PHY)HAL_TSP_SecBuf_GetWrite(&(_REGBuf->Buf[u32BufId]));
4962 TSP_RETURN(E_TSP_OK);
4963 }
4964
4965
4966 //-------------------------------------------------------------------------------------------------
4967 /// Set current read address of section buffer
4968 /// @param u32EngId \b IN: index of TSP engine [ 0 .. (@ref DRVTSP_ENGINE_NUM-1) ]
4969 /// @param u32SecFltId \b IN: index of section buffer
4970 /// @param u32ReadAddr \b IN: address of read pointer
4971 /// @return TSP_Result
4972 /// @note
4973 /// User can update the read address to notify TSP where is the end of section
4974 /// data already read back by user.
4975 //-------------------------------------------------------------------------------------------------
MDrv_TSP_SEC_SetRead(MS_U32 u32BufId,MS_PHY u32Read)4976 TSP_Result MDrv_TSP_SEC_SetRead(MS_U32 u32BufId, MS_PHY u32Read)
4977 {
4978 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
4979 TSP_CHECK(_tspFltIdMap.u32SecFltId_End > u32BufId, "[%04d] Invalid u32BufId %d\n", __LINE__, (unsigned int)u32BufId);
4980
4981 TSP_ENTRY();
4982 if (E_TSP_FLT_STATE_FREE == _ptsp_res->_tspInfo.BufState[u32BufId])
4983 {
4984 TSP_RETURN(E_TSP_FAIL_INVALID);
4985 }
4986
4987 HAL_TSP_SecBuf_SetRead(&(_REGBuf->Buf[u32BufId]), (MS_U32)u32Read);
4988
4989 TSP_RETURN(E_TSP_OK);
4990 }
4991
MDrv_TSP_SECFLT_BurstLen(MS_U32 u32BurstMode)4992 TSP_Result MDrv_TSP_SECFLT_BurstLen(MS_U32 u32BurstMode)
4993 {
4994 TSP_ENTRY();
4995
4996 HAL_TSP_SecFlt_BurstLen(u32BurstMode);
4997
4998 TSP_RETURN(E_TSP_OK);
4999 }
5000
5001 #ifdef MSOS_TYPE_LINUX_KERNEL
MDrv_TSP_SEC_ClrEvent(MS_U32 u32BufId)5002 TSP_Result MDrv_TSP_SEC_ClrEvent(MS_U32 u32BufId)
5003 {
5004 TSP_CHECK(_tspFltIdMap.u32SecFltId_End > u32BufId, "[%04d] Invalid u32BufId %d\n", __LINE__, (unsigned int)u32BufId);
5005 TSP_ENTRY();
5006 _u32SecEvent[u32BufId] = 0;
5007 TSP_RETURN(E_TSP_OK);
5008 }
5009
MDrv_TSP_SEC_GetEvent(MS_U32 u32BufId,MS_U32 * pu32Event)5010 TSP_Result MDrv_TSP_SEC_GetEvent(MS_U32 u32BufId, MS_U32 *pu32Event)
5011 {
5012 TSP_CHECK(_tspFltIdMap.u32SecFltId_End > u32BufId, "[%04d] Invalid u32BufId %d\n", __LINE__, (unsigned int)u32BufId);
5013 TSP_ENTRY();
5014 *pu32Event = _u32SecEvent[u32BufId];
5015 TSP_RETURN(E_TSP_OK);
5016 }
5017
MDrv_TSP_SEC_SetEvent(MS_U32 u32BufId,MS_U32 u32Event)5018 TSP_Result MDrv_TSP_SEC_SetEvent(MS_U32 u32BufId, MS_U32 u32Event)
5019 {
5020 TSP_CHECK(_tspFltIdMap.u32SecFltId_End > u32BufId, "[%04d] Invalid u32BufId %d\n", __LINE__, (unsigned int)u32BufId);
5021 TSP_ENTRY();
5022 _u32SecEvent[u32BufId] |= u32Event;
5023 TSP_RETURN(E_TSP_OK);
5024 }
5025 #endif // MSOS_TYPE_LINUX_KERNEL
5026
5027
5028 //-------------------------------------------------------------------------------------------------
5029 /// Set packet size to TSP file
5030 /// @param PacketMode \b IN: Mode of TSP file packet mode (192, 204, 188)
5031 /// @return TSP_Result
5032 /// @note
5033 //-------------------------------------------------------------------------------------------------
MDrv_TSP_FILE_SetPktMode(TSP_PktMode mode)5034 TSP_Result MDrv_TSP_FILE_SetPktMode(TSP_PktMode mode)
5035 {
5036 TSP_ENTRY();
5037 FILEENG_SEQ eFileEng = HAL_TSP_GetDefaultFileinEng();
5038
5039 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5040
5041 switch (mode)
5042 {
5043 case E_TSP_PKTMODE_188:
5044 HAL_TSP_Filein_PktSize(eFileEng,188);
5045 break;
5046 case E_TSP_PKTMODE_192:
5047 HAL_TSP_Filein_PktSize(eFileEng,192);
5048 break;
5049 case E_TSP_PKTMODE_204:
5050 HAL_TSP_Filein_PktSize(eFileEng,204);
5051 break;
5052 case E_TSP_PKTMODE_130:
5053 HAL_TSP_Filein_PktSize(eFileEng,130);
5054 break;
5055 case E_TSP_PKTMODE_134:
5056 HAL_TSP_Filein_PktSize(eFileEng,134);
5057 break;
5058 default:
5059 break;
5060 }
5061
5062 TSP_RETURN(E_TSP_OK);
5063 }
5064
5065 //-------------------------------------------------------------------------------------------------
5066 /// Set Memory to TSP Stream Input Rate
5067 /// @param u32Div2 \b IN: Divider of M2T stream input rate ([1 .. 31], default 10)
5068 /// @return TSP_Result
5069 /// @note
5070 /// <b>input_rate = stream_rate / (u32Div2 * 2)</b>\n
5071 /// @note
5072 /// It's not recommend to change input rate at run-time, because it conflict with
5073 /// the internal stream synchornization mechanism.
5074 /// @sa MDrv_TSP_GetM2tSlot
5075 //-------------------------------------------------------------------------------------------------
MDrv_TSP_FILE_SetRate(MS_U32 u32Div2)5076 TSP_Result MDrv_TSP_FILE_SetRate(MS_U32 u32Div2)
5077 {
5078 TSP_ENTRY();
5079
5080 //[HW TODO][HW LIMIT]
5081 // TsDma pause can be access by TSP CPU
5082 // TsDma pause it's hard to control because read/write in different register
5083 // When setting TsDma it should be disable interrupt to prevent ISR access
5084 // but it still can't prevent TSP_cpu access at the same time.
5085 //[SW PATCH] Add a special firmware command to lock TSP_cpu DMA pause/resume.
5086 FILEENG_SEQ eFileEng = HAL_TSP_GetDefaultFileinEng();
5087
5088 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5089
5090 TSP_OS_IntDisable();
5091 HAL_TSP_Filein_ByteDelay(eFileEng,u32Div2,TRUE);
5092 TSP_OS_IntEnable();
5093
5094 TSP_RETURN(E_TSP_OK);
5095 }
5096
5097 //-------------------------------------------------------------------------------------------------
5098 /// Memory to TSP stream control : Stream start address
5099 /// @param u32StreamAddr \b IN: pointer of transport stream in memory
5100 /// @return TSP_Result
5101 //-------------------------------------------------------------------------------------------------
MDrv_TSP_FILE_CmdAddr(MS_U32 u32Addr)5102 TSP_Result MDrv_TSP_FILE_CmdAddr(MS_U32 u32Addr)
5103 {
5104 TSP_ENTRY();
5105 FILEENG_SEQ eFileEng = HAL_TSP_GetDefaultFileinEng();
5106 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5107 HAL_TSP_Filein_Addr(eFileEng, u32Addr);
5108 TSP_RETURN(E_TSP_OK);
5109 }
5110
5111 //-------------------------------------------------------------------------------------------------
5112 /// Memory to TSP stream control : Stream data size
5113 /// @param u32StreamSize \b IN: size of transport stream data to be copied
5114 /// @return TSP_Result
5115 // @note u32StreamSize must be larger than 16
5116 //-------------------------------------------------------------------------------------------------
MDrv_TSP_FILE_CmdSize(MS_U32 u32Size)5117 TSP_Result MDrv_TSP_FILE_CmdSize(MS_U32 u32Size)
5118 {
5119 if(u32Size <= 16)
5120 return E_TSP_FAIL;
5121
5122 TSP_ENTRY();
5123 FILEENG_SEQ eFileEng = HAL_TSP_GetDefaultFileinEng();
5124 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5125 HAL_TSP_Filein_Size(eFileEng, u32Size);
5126 TSP_RETURN(E_TSP_OK);
5127 }
5128
5129 //-------------------------------------------------------------------------------------------------
5130 //[Reserved]
5131 // Memory to TSP stream command : Update Stream STC
5132 // @param u32EngId \b IN: index of TSP engine [ 0 .. (@ref DRVTSP_ENGINE_NUM-1) ]
5133 // @param u32STC_32 \b IN: STC[32] for next input stream
5134 // @param u32STC \b IN: STC[31:0] for next input stream
5135 // @return TSP_Result
5136 // @note M2T Command Size: 3
5137 //-------------------------------------------------------------------------------------------------
MDrv_TSP_FILE_CmdSTC(MS_U32 u32EngId,MS_U32 u32STC_H,MS_U32 u32STC)5138 TSP_Result MDrv_TSP_FILE_CmdSTC(MS_U32 u32EngId, MS_U32 u32STC_H, MS_U32 u32STC)
5139 {
5140 TSP_ENTRY();
5141
5142 //[HW TODO][HW LIMIT]
5143 // STC register mapping is different between MCU and CPU.
5144 //HAL_TSP_CMDQ_SetSTC(u32STC_H, u32STC);
5145 //HAL_TSP_SetSTC(u32STC_H, u32STC);
5146 TSP_RES_ALLOC_STC_CHECK(u32EngId);
5147 HAL_TSP_STC33_CmdQSet(u32STC_H, u32STC);
5148
5149 TSP_RETURN(E_TSP_OK);
5150 }
5151
5152
5153
5154 //-------------------------------------------------------------------------------------------------
5155 /// Memory to TSP stream control : Start stream input
5156 /// @param eM2tMode \b IN: input source control of filein
5157 /// @return TSP_Result
5158 /// @note Filein Command Size: 1
5159 /// @sa MDrv_TSP_GetM2tSlot
5160 //-------------------------------------------------------------------------------------------------
MDrv_TSP_FILE_CmdStart(TSP_FileMode mode)5161 TSP_Result MDrv_TSP_FILE_CmdStart(TSP_FileMode mode)
5162 {
5163 TSP_ENTRY();
5164
5165 FILEENG_SEQ eFileEng = HAL_TSP_GetDefaultFileinEng();
5166 MS_BOOL bBypass = TRUE; // Enable PES file-in or not
5167 TSP_DST_SEQ eDst = E_TSP_DST_INVALID;
5168
5169 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5170
5171 for(eDst = E_TSP_DST_FIFO_VIDEO; eDst < E_TSP_DST_INVALID; eDst++)
5172 {
5173 HAL_TSP_FIFO_Bypass(eDst, FALSE); // for bypass clear
5174 }
5175
5176 // @FIXME: Good to assume enum and register definition identical?
5177 switch (mode)
5178 {
5179 case E_TSP_FILE_2_TSP:
5180 bBypass = FALSE;
5181 break;
5182 case E_TSP_FILE_2_VIDEO:
5183 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_VIDEO, TRUE);
5184 HAL_TSP_FIFO_Bypass_Src(eFileEng, E_TSP_DST_FIFO_VIDEO);
5185 break;
5186 case E_TSP_FILE_2_VIDEO3D:
5187 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_VIDEO3D, TRUE);
5188 HAL_TSP_FIFO_Bypass_Src(eFileEng, E_TSP_DST_FIFO_VIDEO3D);
5189 break;
5190 case E_TSP_FILE_2_VIDEO3:
5191 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_VIDEO3, TRUE);
5192 HAL_TSP_FIFO_Bypass_Src(eFileEng, E_TSP_DST_FIFO_VIDEO3);
5193 break;
5194 case E_TSP_FILE_2_VIDEO4:
5195 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_VIDEO4, TRUE);
5196 HAL_TSP_FIFO_Bypass_Src(eFileEng, E_TSP_DST_FIFO_VIDEO4);
5197 break;
5198 case E_TSP_FILE_2_VIDEO5:
5199 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_VIDEO5, TRUE);
5200 HAL_TSP_FIFO_Bypass_Src(eFileEng, E_TSP_DST_FIFO_VIDEO5);
5201 break;
5202 case E_TSP_FILE_2_VIDEO6:
5203 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_VIDEO6, TRUE);
5204 HAL_TSP_FIFO_Bypass_Src(eFileEng, E_TSP_DST_FIFO_VIDEO6);
5205 break;
5206 case E_TSP_FILE_2_VIDEO7:
5207 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_VIDEO7, TRUE);
5208 HAL_TSP_FIFO_Bypass_Src(eFileEng, E_TSP_DST_FIFO_VIDEO7);
5209 break;
5210 case E_TSP_FILE_2_VIDEO8:
5211 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_VIDEO8, TRUE);
5212 HAL_TSP_FIFO_Bypass_Src(eFileEng, E_TSP_DST_FIFO_VIDEO8);
5213 break;
5214 case E_TSP_FILE_2_AUDIO:
5215 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_AUDIO, TRUE);
5216 HAL_TSP_FIFO_Bypass_Src(eFileEng, E_TSP_DST_FIFO_AUDIO);
5217 break;
5218 case E_TSP_FILE_2_AUDIO2:
5219 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_AUDIO2, TRUE);
5220 HAL_TSP_FIFO_Bypass_Src(eFileEng, E_TSP_DST_FIFO_AUDIO2);
5221 break;
5222 case E_TSP_FILE_2_AUDIO3:
5223 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_AUDIO3, TRUE);
5224 HAL_TSP_FIFO_Bypass_Src(eFileEng, E_TSP_DST_FIFO_AUDIO3);
5225 break;
5226 case E_TSP_FILE_2_AUDIO4:
5227 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_AUDIO4, TRUE);
5228 HAL_TSP_FIFO_Bypass_Src(eFileEng, E_TSP_DST_FIFO_AUDIO4);
5229 break;
5230 case E_TSP_FILE_2_AUDIO5:
5231 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_AUDIO5, TRUE);
5232 HAL_TSP_FIFO_Bypass_Src(eFileEng, E_TSP_DST_FIFO_AUDIO5);
5233 break;
5234 case E_TSP_FILE_2_AUDIO6:
5235 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_AUDIO6, TRUE);
5236 HAL_TSP_FIFO_Bypass_Src(eFileEng, E_TSP_DST_FIFO_AUDIO6);
5237 break;
5238 default:
5239 break;
5240 }
5241
5242 HAL_TSP_Filein_Bypass(eFileEng, bBypass);
5243 HAL_TSP_Filein_Start(eFileEng);
5244
5245 TSP_RETURN(E_TSP_OK);
5246 }
5247
5248 //-------------------------------------------------------------------------------------------------
5249 /// Get the number of empty slot of M2T command
5250 /// @param pu32EmptySlot \b OUT: pointer of empty slot count return
5251 /// @return TSP_Result
5252 /// @note
5253 /// M2T is a command queue command, it can be queued by TSP when another M2T command
5254 /// is executing by TSP. The queued commands will be executed by order (FIFO)
5255 /// when previous M2T command execution is finished.
5256 /// @note
5257 /// User should call GetM2TSlot to make sure there is enough empty M2T command slot
5258 /// before sending any M2T command. (Each command has different command size)
5259 /// @sa MDrv_TSP_M2T_SetAddr, MDrv_TSP_M2T_SetSize, MDrv_TSP_M2T_Start,
5260 //[Reserved] MDrv_TSP_M2T_SetSTC
5261 //-------------------------------------------------------------------------------------------------
MDrv_TSP_FILE_GetCmdSlot(MS_U32 * pu32EmptySlot)5262 TSP_Result MDrv_TSP_FILE_GetCmdSlot(MS_U32 *pu32EmptySlot)
5263 {
5264 TSP_ENTRY();
5265 FILEENG_SEQ eFileEng = HAL_TSP_GetDefaultFileinEng();
5266 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5267 *pu32EmptySlot = HAL_TSP_Filein_CmdQSlot(eFileEng);
5268 TSP_RETURN(E_TSP_OK);
5269 }
5270
5271 //-------------------------------------------------------------------------------------------------
5272 /// Reset command queue
5273 /// @return TSP_Result
5274 /// @note
5275 /// SW patch--wait command queue empty
5276 /// wait HW ECO
5277 //-------------------------------------------------------------------------------------------------
MDrv_TSP_FILE_Reset(void)5278 TSP_Result MDrv_TSP_FILE_Reset(void)
5279 {
5280 MS_U32 u32Counter;
5281
5282 TSP_ENTRY();
5283 FILEENG_SEQ eFileEng = HAL_TSP_GetDefaultFileinEng();
5284
5285 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5286
5287 HAL_TSP_Filein_CmdQRst(eFileEng, TRUE);
5288 HAL_TSP_Filein_CmdQRst(eFileEng, FALSE);
5289 HAL_TSP_Filein_Abort(eFileEng, TRUE);
5290 HAL_TSP_Filein_Abort(eFileEng, FALSE);
5291
5292 //reset the last data that hw is excuting --> HW new design
5293 HAL_TSP_Filein_WbFsmRst(eFileEng, TRUE);
5294
5295 for(u32Counter = 0; u32Counter < 100; u32Counter++)
5296 {
5297 if(!HAL_TSP_Filein_Status(eFileEng))
5298 {
5299 break;
5300 }
5301 MsOS_DelayTask(1);
5302 }
5303
5304 HAL_TSP_Filein_WbFsmRst(eFileEng, FALSE);
5305
5306 if(u32Counter == 100)
5307 {
5308 TSP_DBG(E_TSP_DBG_ERROR, "[%s][%d] Wait file in done timeout\n", __FUNCTION__, __LINE__);
5309 TSP_RETURN(E_TSP_FAIL);
5310 }
5311
5312 TSP_RETURN(E_TSP_OK);
5313 }
5314
5315 //-------------------------------------------------------------------------------------------------
5316 /// Memory to TSP stream control : pause stream input
5317 /// @return TSP_Result
5318 //-------------------------------------------------------------------------------------------------
MDrv_TSP_FILE_Pause(void)5319 TSP_Result MDrv_TSP_FILE_Pause(void)
5320 {
5321 TSP_ENTRY();
5322 FILEENG_SEQ eFileEng = HAL_TSP_GetDefaultFileinEng();
5323 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5324 HAL_TSP_File_Pause(eFileEng);
5325 TSP_RETURN(E_TSP_OK);
5326 }
5327
5328 //-------------------------------------------------------------------------------------------------
5329 /// Memory to TSP stream control : resume stream input
5330 /// @return TSP_Result
5331 //-------------------------------------------------------------------------------------------------
MDrv_TSP_FILE_Resume(void)5332 TSP_Result MDrv_TSP_FILE_Resume(void)
5333 {
5334 TSP_ENTRY();
5335 FILEENG_SEQ eFileEng = HAL_TSP_GetDefaultFileinEng();
5336 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5337 HAL_TSP_File_Resume(eFileEng);
5338 TSP_RETURN(E_TSP_OK);
5339 }
5340
MDrv_TSP_FILE_Stop(void)5341 TSP_Result MDrv_TSP_FILE_Stop(void)
5342 {
5343 TSP_ENTRY();
5344 FILEENG_SEQ eFileEng = HAL_TSP_GetDefaultFileinEng();
5345 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5346 HAL_TSP_TSIF_FileEn(eFileEng, FALSE); // data port disable @FIXME in k2 we switch data port only but we close every file setting here will there be side effect?
5347
5348 // @TODO Does it need to call HAL_TSP_FIFO_Bypass() function?
5349 //HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_VIDEO, FALSE); // for clear all bypass setting
5350
5351 TSP_RETURN(E_TSP_OK);
5352 }
5353
5354 //-------------------------------------------------------------------------------------------------
5355 /// Get current file in state
5356 /// @return TSP_M2tStatus
5357 /// @sa MDrv_TSP_GetM2tSlot
5358 //-------------------------------------------------------------------------------------------------
MDrv_TSP_FILE_GetState(TSP_FileState * pState)5359 TSP_Result MDrv_TSP_FILE_GetState(TSP_FileState *pState)
5360 {
5361 TSP_ENTRY();
5362 FILEENG_SEQ eFileEng = HAL_TSP_GetDefaultFileinEng();
5363 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5364 *pState = HAL_TSP_Filein_GetState(eFileEng);
5365 TSP_RETURN(E_TSP_OK);
5366 }
5367
5368 //-------------------------------------------------------------------------------------------------
5369 /// Enable timestamp block scheme
5370 /// @return TSP_Result
5371 /// @note
5372 //-------------------------------------------------------------------------------------------------
MDrv_TSP_File_192BlockScheme_En(MS_BOOL bEnable)5373 TSP_Result MDrv_TSP_File_192BlockScheme_En(MS_BOOL bEnable)
5374 {
5375 TSP_ENTRY();
5376 // HAL_TSP_FileIn_192BlockScheme_En(bEnable);
5377 FILEENG_SEQ eFileEng = HAL_TSP_GetDefaultFileinEng();
5378 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5379 HAL_TSP_Filein_BlockTimeStamp(eFileEng, bEnable); //@F_TODO fix engine problen and make sure they are the same
5380 TSP_RETURN(E_TSP_OK);
5381 }
5382
5383 //-------------------------------------------------------------------------------------------------
5384 /// Setting PS path
5385 /// @param eM2tMode \b IN: input source control of filein
5386 /// @return TSP_Result
5387 //-------------------------------------------------------------------------------------------------
MDrv_TSP_FILE_PS_Path_Enable(TSP_FileMode mode)5388 TSP_Result MDrv_TSP_FILE_PS_Path_Enable(TSP_FileMode mode)
5389 {
5390 TSP_ENTRY();
5391
5392 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_VIDEO, FALSE); // for bypass clear
5393 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_VIDEO3D, FALSE); // for bypass clear
5394 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_VIDEO3, FALSE); // for bypass clear
5395 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_VIDEO4, FALSE); // for bypass clear
5396 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_AUDIO, FALSE); // for bypass clear
5397 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_AUDIO2, FALSE); // for bypass clear
5398 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_AUDIO3, FALSE); // for bypass clear
5399 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_AUDIO4, FALSE); // for bypass clear
5400
5401 switch (mode)
5402 {
5403 case E_TSP_FILE_2_TSP:
5404 break;
5405 case E_TSP_FILE_2_VIDEO:
5406 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_VIDEO, TRUE);
5407 break;
5408 case E_TSP_FILE_2_VIDEO3D:
5409 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_VIDEO3D, TRUE);
5410 break;
5411 case E_TSP_FILE_2_VIDEO3:
5412 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_VIDEO3, TRUE);
5413 break;
5414 case E_TSP_FILE_2_VIDEO4:
5415 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_VIDEO4, TRUE);
5416 break;
5417 case E_TSP_FILE_2_AUDIO:
5418 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_AUDIO, TRUE);
5419 break;
5420 case E_TSP_FILE_2_AUDIO2:
5421 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_AUDIO2, TRUE);
5422 break;
5423 case E_TSP_FILE_2_AUDIO3:
5424 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_AUDIO3, TRUE);
5425 break;
5426 case E_TSP_FILE_2_AUDIO4:
5427 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_AUDIO4, TRUE);
5428 break;
5429 default:
5430 break;
5431 }
5432 TSP_RETURN(E_TSP_OK);
5433 }
5434
5435 // file driver with engine
MDrv_TSP_FILE_Eng_SetPktMode(TSP_FILE_ENG Eng,TSP_PktMode mode)5436 TSP_Result MDrv_TSP_FILE_Eng_SetPktMode(TSP_FILE_ENG Eng, TSP_PktMode mode)
5437 {
5438 TSP_ENTRY();
5439
5440 FILEENG_SEQ eFileEng = E_FILEENG_INVALID;
5441 MS_U32 u32PktSize = 0;
5442 switch (mode)
5443 {
5444 case E_TSP_PKTMODE_188:
5445 u32PktSize = 188;
5446 break;
5447 case E_TSP_PKTMODE_192:
5448 u32PktSize = 192;
5449 break;
5450 case E_TSP_PKTMODE_204:
5451 u32PktSize = 204;
5452 break;
5453 case E_TSP_PKTMODE_130:
5454 u32PktSize = 130;
5455 break;
5456 case E_TSP_PKTMODE_134:
5457 u32PktSize = 134;
5458 break;
5459 default:
5460 TSP_DBG(E_TSP_DBG_MUST, "Invalid File-in Packet Size!\n");
5461 TSP_RETURN(E_TSP_FAIL);
5462 break;
5463 }
5464
5465 eFileEng = HAL_TSP_FilePath2Tsif_Mapping((MS_U32)Eng);
5466
5467 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5468
5469 HAL_TSP_Filein_PktSize(eFileEng, u32PktSize);
5470
5471 TSP_RETURN(E_TSP_OK);
5472 }
5473
5474 #ifdef MERGE_STR_SUPPORT
_TSP_DrvHal_PktConverter_PktModeMapping(TSP_PktMode ePktMode)5475 static TSP_HAL_PKT_MODE _TSP_DrvHal_PktConverter_PktModeMapping(TSP_PktMode ePktMode)
5476 {
5477 TSP_HAL_PKT_MODE eOutPktMode = E_TSP_HAL_PKT_MODE_NORMAL;
5478
5479 switch(ePktMode)
5480 {
5481 case E_TSP_PKTMODE_CIPLUS:
5482 eOutPktMode = E_TSP_HAL_PKT_MODE_CI;
5483 break;
5484 case E_TSP_PKTMODE_ATS:
5485 eOutPktMode = E_TSP_HAL_PKT_MODE_ATS;
5486 break;
5487 case E_TSP_PKTMODE_OPENCABLE:
5488 eOutPktMode = E_TSP_HAL_PKT_MODE_OPEN_CABLE;
5489 break;
5490 case E_TSP_PKTMODE_MXL192:
5491 eOutPktMode = E_TSP_HAL_PKT_MODE_MXL_192;
5492 break;
5493 case E_TSP_PKTMODE_MXL196:
5494 eOutPktMode = E_TSP_HAL_PKT_MODE_MXL_196;
5495 break;
5496 case E_TSP_PKTMODE_MXL200:
5497 eOutPktMode = E_TSP_HAL_PKT_MODE_MXL_200;
5498 break;
5499 default:
5500 TSP_DBG(E_TSP_DBG_MUST, "[%s][%d] Invalid Packet Mode !!\n", __FUNCTION__, __LINE__);
5501 break;
5502 }
5503
5504 return eOutPktMode;
5505 }
5506 #endif
5507
MDrv_TSP_SetPacketMode(TSP_TSIF u32TSIf,TSP_PktMode ePktMode)5508 TSP_Result MDrv_TSP_SetPacketMode(TSP_TSIF u32TSIf, TSP_PktMode ePktMode)
5509 {
5510 #ifdef MERGE_STR_SUPPORT
5511 TSP_ENTRY();
5512
5513 TSP_HAL_TSIF eHalTSIF = _TSP_DrvHal_TSIFMapping(u32TSIf);
5514 MS_U32 u32TSIF = 0;
5515
5516 if((ePktMode >= E_TSP_PKTMODE_LIVEIN_MIN) && (ePktMode <= E_TSP_PKTMODE_LIVEIN_MAX)) // live-in
5517 {
5518 u32TSIF = HAL_TSP_TsifMapping(eHalTSIF, FALSE);
5519
5520 TSP_RES_ALLOC_TSPPATH_CHECK(u32TSIF);
5521
5522 HAL_TSP_PktConverter_PktMode(u32TSIF, _TSP_DrvHal_PktConverter_PktModeMapping(ePktMode));
5523 }
5524
5525 TSP_RETURN(E_TSP_OK);
5526 #else
5527 return E_TSP_FAIL_NOT_SUPPORTED;
5528 #endif
5529 }
5530
MDrv_TSP_FILE_Eng_SetRate(TSP_FILE_ENG Eng,MS_U32 u32Div2)5531 TSP_Result MDrv_TSP_FILE_Eng_SetRate(TSP_FILE_ENG Eng, MS_U32 u32Div2)
5532 {
5533 TSP_ENTRY();
5534
5535 FILEENG_SEQ eFileEng = E_FILEENG_INVALID;
5536
5537 eFileEng = HAL_TSP_FilePath2Tsif_Mapping((MS_U32)Eng);
5538
5539 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5540
5541 //[HW TODO][HW LIMIT]
5542 // TsDma pause can be access by TSP CPU
5543 // TsDma pause it's hard to control because read/write in different register
5544 // When setting TsDma it should be disable interrupt to prevent ISR access
5545 // but it still can't prevent TSP_cpu access at the same time.
5546 //[SW PATCH] Add a special firmware command to lock TSP_cpu DMA pause/resume.
5547 TSP_OS_IntDisable();
5548 HAL_TSP_Filein_ByteDelay(eFileEng, u32Div2, TRUE); //@F_TODO when to set false???
5549 TSP_OS_IntEnable();
5550
5551 TSP_RETURN(E_TSP_OK);
5552 }
5553
MDrv_TSP_FILE_Eng_CmdAddr(TSP_FILE_ENG Eng,MS_U32 u32Addr)5554 TSP_Result MDrv_TSP_FILE_Eng_CmdAddr(TSP_FILE_ENG Eng, MS_U32 u32Addr)
5555 {
5556 TSP_ENTRY();
5557
5558 FILEENG_SEQ eFileEng = E_FILEENG_INVALID;
5559 eFileEng = HAL_TSP_FilePath2Tsif_Mapping((MS_U32)Eng);
5560
5561 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5562
5563 HAL_TSP_Filein_Addr((MS_U32)eFileEng, u32Addr);
5564
5565 TSP_RETURN(E_TSP_OK);
5566 }
5567
MDrv_TSP_FILE_Eng_CmdSize(TSP_FILE_ENG Eng,MS_U32 u32Size)5568 TSP_Result MDrv_TSP_FILE_Eng_CmdSize(TSP_FILE_ENG Eng, MS_U32 u32Size)
5569 {
5570 if(u32Size <= 16)
5571 return E_TSP_FAIL;
5572
5573 TSP_ENTRY();
5574
5575 FILEENG_SEQ eFileEng = E_FILEENG_INVALID;
5576 eFileEng = HAL_TSP_FilePath2Tsif_Mapping((MS_U32)Eng);
5577
5578 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5579
5580 HAL_TSP_Filein_Size(eFileEng, u32Size);
5581 TSP_RETURN(E_TSP_OK);
5582 }
5583
MDrv_TSP_FILE_Eng_CmdSTC(TSP_FILE_ENG Eng,MS_U32 u32EngId,MS_U32 u32STC_H,MS_U32 u32STC)5584 TSP_Result MDrv_TSP_FILE_Eng_CmdSTC(TSP_FILE_ENG Eng, MS_U32 u32EngId, MS_U32 u32STC_H, MS_U32 u32STC)
5585 {
5586 return E_TSP_FAIL_NOT_SUPPORTED;
5587 }
5588
MDrv_TSP_FILE_Eng_CmdStart(TSP_FILE_ENG Eng,TSP_FileMode mode)5589 TSP_Result MDrv_TSP_FILE_Eng_CmdStart(TSP_FILE_ENG Eng, TSP_FileMode mode)
5590 {
5591 TSP_ENTRY();
5592
5593 FILEENG_SEQ eFileEng = HAL_TSP_FilePath2Tsif_Mapping((MS_U32)Eng);
5594
5595 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5596
5597 MS_BOOL bBypass = TRUE; // Enable PES file-in or not
5598 TSP_DST_SEQ eDst = E_TSP_DST_INVALID;
5599
5600 for(eDst = E_TSP_DST_FIFO_VIDEO; eDst < E_TSP_DST_INVALID; eDst++)
5601 {
5602 HAL_TSP_FIFO_Bypass(eDst, FALSE); // for bypass clear
5603 }
5604
5605 switch (mode)
5606 {
5607 case E_TSP_FILE_2_TSP:
5608 bBypass = FALSE;
5609 break;
5610 case E_TSP_FILE_2_VIDEO:
5611 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_VIDEO, TRUE);
5612 HAL_TSP_FIFO_Bypass_Src(eFileEng, E_TSP_DST_FIFO_VIDEO);
5613 break;
5614 case E_TSP_FILE_2_VIDEO3D:
5615 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_VIDEO3D, TRUE);
5616 HAL_TSP_FIFO_Bypass_Src(eFileEng, E_TSP_DST_FIFO_VIDEO3D);
5617 break;
5618 case E_TSP_FILE_2_VIDEO3:
5619 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_VIDEO3, TRUE);
5620 HAL_TSP_FIFO_Bypass_Src(eFileEng, E_TSP_DST_FIFO_VIDEO3);
5621 break;
5622 case E_TSP_FILE_2_VIDEO4:
5623 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_VIDEO4, TRUE);
5624 HAL_TSP_FIFO_Bypass_Src(eFileEng, E_TSP_DST_FIFO_VIDEO4);
5625 break;
5626 case E_TSP_FILE_2_VIDEO5:
5627 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_VIDEO5, TRUE);
5628 HAL_TSP_FIFO_Bypass_Src(eFileEng, E_TSP_DST_FIFO_VIDEO5);
5629 break;
5630 case E_TSP_FILE_2_VIDEO6:
5631 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_VIDEO6, TRUE);
5632 HAL_TSP_FIFO_Bypass_Src(eFileEng, E_TSP_DST_FIFO_VIDEO6);
5633 break;
5634 case E_TSP_FILE_2_VIDEO7:
5635 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_VIDEO7, TRUE);
5636 HAL_TSP_FIFO_Bypass_Src(eFileEng, E_TSP_DST_FIFO_VIDEO7);
5637 break;
5638 case E_TSP_FILE_2_VIDEO8:
5639 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_VIDEO8, TRUE);
5640 HAL_TSP_FIFO_Bypass_Src(eFileEng, E_TSP_DST_FIFO_VIDEO8);
5641 break;
5642 case E_TSP_FILE_2_AUDIO:
5643 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_AUDIO, TRUE);
5644 HAL_TSP_FIFO_Bypass_Src(eFileEng, E_TSP_DST_FIFO_AUDIO);
5645 break;
5646 case E_TSP_FILE_2_AUDIO2:
5647 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_AUDIO2, TRUE);
5648 HAL_TSP_FIFO_Bypass_Src(eFileEng, E_TSP_DST_FIFO_AUDIO2);
5649 break;
5650 case E_TSP_FILE_2_AUDIO3:
5651 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_AUDIO3, TRUE);
5652 HAL_TSP_FIFO_Bypass_Src(eFileEng, E_TSP_DST_FIFO_AUDIO3);
5653 break;
5654 case E_TSP_FILE_2_AUDIO4:
5655 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_AUDIO4, TRUE);
5656 HAL_TSP_FIFO_Bypass_Src(eFileEng, E_TSP_DST_FIFO_AUDIO4);
5657 break;
5658 case E_TSP_FILE_2_AUDIO5:
5659 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_AUDIO5, TRUE);
5660 HAL_TSP_FIFO_Bypass_Src(eFileEng, E_TSP_DST_FIFO_AUDIO5);
5661 break;
5662 case E_TSP_FILE_2_AUDIO6:
5663 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_AUDIO6, TRUE);
5664 HAL_TSP_FIFO_Bypass_Src(eFileEng, E_TSP_DST_FIFO_AUDIO6);
5665 break;
5666 default:
5667 break;
5668 }
5669
5670 HAL_TSP_Filein_Bypass(eFileEng, bBypass);
5671 HAL_TSP_Filein_Start(eFileEng);
5672 TSP_RETURN(E_TSP_OK);
5673 }
5674
MDrv_TSP_FILE_Eng_Stop(TSP_FILE_ENG Eng)5675 TSP_Result MDrv_TSP_FILE_Eng_Stop(TSP_FILE_ENG Eng)
5676 {
5677 TSP_ENTRY();
5678
5679 FILEENG_SEQ eFileEng = E_FILEENG_INVALID;
5680 eFileEng = HAL_TSP_FilePath2Tsif_Mapping((MS_U32)Eng);
5681
5682 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5683
5684 HAL_TSP_TSIF_FileEn(eFileEng, FALSE); // data port disable @FIXME in k2 we switch data port only but we close every file setting here will there be side effect?
5685
5686 // @TODO not completely implement yet
5687 // Fix Path : tsif 0 for video and tsif 1 for video3D
5688 // need to flexible modification in the future
5689 /*
5690 if(eFileEng == E_FILEENG_TSIF0)
5691 {
5692 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_VIDEO, FALSE); // for clear all bypass setting
5693 }
5694 else if(eFileEng == E_FILEENG_TSIF2)
5695 {
5696 HAL_TSP_FIFO_Bypass(E_TSP_DST_FIFO_VIDEO3D, FALSE); // for clear all bypass setting
5697 }
5698 */
5699
5700
5701 TSP_RETURN(E_TSP_OK);
5702 }
5703
MDrv_TSP_FILE_Eng_GetCmdSlot(TSP_FILE_ENG Eng,MS_U32 * pu32EmptySlot)5704 TSP_Result MDrv_TSP_FILE_Eng_GetCmdSlot(TSP_FILE_ENG Eng, MS_U32 *pu32EmptySlot)
5705 {
5706 TSP_ENTRY();
5707
5708 FILEENG_SEQ eFileEng = E_FILEENG_INVALID;
5709 eFileEng = HAL_TSP_FilePath2Tsif_Mapping((MS_U32)Eng);
5710
5711 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5712
5713 *pu32EmptySlot = HAL_TSP_Filein_CmdQSlot(eFileEng);
5714
5715 TSP_RETURN(E_TSP_OK);
5716 }
5717
MDrv_TSP_FILE_Eng_Pause(TSP_FILE_ENG Eng)5718 TSP_Result MDrv_TSP_FILE_Eng_Pause(TSP_FILE_ENG Eng)
5719 {
5720 TSP_ENTRY();
5721
5722 FILEENG_SEQ eFileEng = E_FILEENG_INVALID;
5723
5724 eFileEng = HAL_TSP_FilePath2Tsif_Mapping((MS_U32)Eng);
5725
5726 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5727
5728 if(HAL_TSP_File_Pause(eFileEng))
5729 {
5730 TSP_RETURN(E_TSP_OK);
5731 }
5732 else
5733 {
5734 TSP_RETURN(E_TSP_FAIL);
5735 }
5736 }
5737
MDrv_TSP_FILE_Eng_Resume(TSP_FILE_ENG Eng)5738 TSP_Result MDrv_TSP_FILE_Eng_Resume(TSP_FILE_ENG Eng)
5739 {
5740 TSP_ENTRY();
5741
5742 FILEENG_SEQ eFileEng = E_FILEENG_INVALID;
5743
5744 eFileEng = HAL_TSP_FilePath2Tsif_Mapping((MS_U32)Eng);
5745
5746 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5747
5748 if(HAL_TSP_File_Resume(eFileEng))
5749 {
5750 TSP_RETURN(E_TSP_OK);
5751 }
5752 else
5753 {
5754 TSP_RETURN(E_TSP_FAIL);
5755 }
5756
5757 }
5758
MDrv_TSP_FILE_Eng_GetState(TSP_FILE_ENG Eng,TSP_FileState * pState)5759 TSP_Result MDrv_TSP_FILE_Eng_GetState(TSP_FILE_ENG Eng, TSP_FileState *pState)
5760 {
5761 TSP_ENTRY();
5762
5763 FILEENG_SEQ eFileEng = E_FILEENG_INVALID;
5764 eFileEng = HAL_TSP_FilePath2Tsif_Mapping((MS_U32)Eng);
5765
5766 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5767
5768 *pState = HAL_TSP_Filein_GetState(eFileEng);
5769
5770 TSP_RETURN(E_TSP_OK);
5771 }
5772
MDrv_TSP_FILE_Eng_Reset(TSP_FILE_ENG Eng)5773 TSP_Result MDrv_TSP_FILE_Eng_Reset(TSP_FILE_ENG Eng)
5774 {
5775 MS_U32 u32Counter;
5776
5777 TSP_ENTRY();
5778 FILEENG_SEQ eFileEng = E_FILEENG_INVALID;
5779 eFileEng = HAL_TSP_FilePath2Tsif_Mapping((MS_U32)Eng);
5780
5781 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5782
5783 HAL_TSP_Filein_CmdQRst(eFileEng, TRUE);
5784 HAL_TSP_Filein_CmdQRst(eFileEng, FALSE);
5785 HAL_TSP_Filein_Abort(eFileEng, TRUE);
5786 HAL_TSP_Filein_Abort(eFileEng, FALSE);
5787
5788 //reset the last data that hw is excuting --> HW new design
5789 HAL_TSP_Filein_WbFsmRst(eFileEng, TRUE);
5790
5791 for(u32Counter = 0; u32Counter < 100; u32Counter++)
5792 {
5793 if(!HAL_TSP_Filein_Status(eFileEng))
5794 {
5795 break;
5796 }
5797 MsOS_DelayTask(1);
5798 }
5799
5800 HAL_TSP_Filein_WbFsmRst(eFileEng, FALSE);
5801
5802 if(u32Counter == 100)
5803 {
5804 TSP_DBG(E_TSP_DBG_ERROR, "[%s][%d] Wait file in done timeout\n", __FUNCTION__, __LINE__);
5805 TSP_RETURN(E_TSP_FAIL);
5806 }
5807
5808 TSP_RETURN(E_TSP_OK);
5809 }
5810
MDrv_TSP_FILE_Eng_192BlockScheme_En(TSP_FILE_ENG Eng,MS_BOOL bEnable)5811 TSP_Result MDrv_TSP_FILE_Eng_192BlockScheme_En(TSP_FILE_ENG Eng, MS_BOOL bEnable)
5812 {
5813 TSP_ENTRY();
5814 FILEENG_SEQ eFileEng = E_FILEENG_INVALID;
5815 eFileEng = HAL_TSP_FilePath2Tsif_Mapping((MS_U32)Eng);
5816
5817 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5818
5819 HAL_TSP_Filein_BlockTimeStamp(eFileEng, bEnable);
5820
5821 TSP_RETURN(E_TSP_OK);
5822 }
5823
MDrv_TSP_FILE_Eng_PS_Path_Enable(TSP_FILE_ENG Eng,TSP_FileMode mode)5824 TSP_Result MDrv_TSP_FILE_Eng_PS_Path_Enable(TSP_FILE_ENG Eng, TSP_FileMode mode)
5825 {
5826 return E_TSP_FAIL_NOT_SUPPORTED;
5827 }
5828
MDrv_TSP_FILE_Eng_CmdQFifo_Status(TSP_FILE_ENG Eng,MS_U8 * pu8FifoLevel)5829 TSP_Result MDrv_TSP_FILE_Eng_CmdQFifo_Status(TSP_FILE_ENG Eng, MS_U8 *pu8FifoLevel)
5830 {
5831 TSP_ENTRY();
5832
5833 FILEENG_SEQ eFileEng = HAL_TSP_FilePath2Tsif_Mapping((MS_U32)Eng);
5834
5835 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5836
5837 *pu8FifoLevel = HAL_TSP_Filein_CmdQLv(eFileEng);
5838
5839 TSP_RETURN(E_TSP_OK);
5840 }
5841
MDrv_TSP_FILE_Eng_TimeStampEnablePlaybackStamp(TSP_FILE_ENG Eng,MS_BOOL bEnable)5842 TSP_Result MDrv_TSP_FILE_Eng_TimeStampEnablePlaybackStamp(TSP_FILE_ENG Eng,MS_BOOL bEnable)
5843 {
5844 TSP_ENTRY();
5845
5846 FILEENG_SEQ eFileEng = E_FILEENG_INVALID;
5847 eFileEng = HAL_TSP_FilePath2Tsif_Mapping((MS_U32)Eng);
5848
5849 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5850
5851 HAL_TSP_Filein_PacketMode(eFileEng,bEnable);
5852
5853 TSP_RETURN(E_TSP_OK);
5854 }
5855
MDrv_TSP_FILE_Eng_TimeStampSetPlaybackStamp(TSP_FILE_ENG Eng,MS_U32 u32Stamp)5856 TSP_Result MDrv_TSP_FILE_Eng_TimeStampSetPlaybackStamp(TSP_FILE_ENG Eng, MS_U32 u32Stamp)
5857 {
5858 TSP_ENTRY();
5859
5860 FILEENG_SEQ eFileEng = E_FILEENG_INVALID;
5861 eFileEng = HAL_TSP_FilePath2Tsif_Mapping((MS_U32)Eng);
5862
5863 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5864
5865 HAL_TSP_Filein_SetTimeStamp(eFileEng, u32Stamp);
5866 TSP_RETURN(E_TSP_OK);
5867 }
5868
MDrv_TSP_FILE_Eng_TimeStampSetPlaybackStampClk(TSP_FILE_ENG Eng,TSP_TimeStamp_Clk eClk)5869 TSP_Result MDrv_TSP_FILE_Eng_TimeStampSetPlaybackStampClk(TSP_FILE_ENG Eng, TSP_TimeStamp_Clk eClk)
5870 {
5871 TSP_ENTRY();
5872
5873 FILEENG_SEQ eFileEng = E_FILEENG_INVALID;
5874 eFileEng = HAL_TSP_FilePath2Tsif_Mapping((MS_U32)Eng);
5875
5876 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5877
5878 TSP_HAL_TimeStamp_Clk eTimeStampClk = E_TSP_HAL_TIMESTAMP_CLK_INVALID;
5879
5880 switch(eClk)
5881 {
5882 case E_TSP_TIMESTAMP_CLK_90K:
5883 eTimeStampClk= E_TSP_HAL_TIMESTAMP_CLK_90K;
5884 break;
5885 case E_TSP_TIMESTAMP_CLK_27M:
5886 eTimeStampClk= E_TSP_HAL_TIMESTAMP_CLK_27M;
5887 break;
5888 default:
5889 TSP_DBG(E_TSP_DBG_MUST, "[ERROR][%s][%d] UnSupport TimeStamp Clock!\n",__FUNCTION__,__LINE__);
5890 TSP_RETURN(E_TSP_FAIL_PARAMETER);
5891 }
5892
5893 HAL_TSP_Filein_SetTimeStampClk(eFileEng, eTimeStampClk);
5894
5895 TSP_RETURN(E_TSP_OK);
5896 }
5897
MDrv_TSP_FILE_Eng_TimeStampGetPlaybackStamp(TSP_FILE_ENG Eng,MS_U32 * u32Stamp)5898 TSP_Result MDrv_TSP_FILE_Eng_TimeStampGetPlaybackStamp(TSP_FILE_ENG Eng, MS_U32* u32Stamp)
5899 {
5900 TSP_ENTRY();
5901
5902 FILEENG_SEQ eFileEng = E_FILEENG_INVALID;
5903 eFileEng = HAL_TSP_FilePath2Tsif_Mapping((MS_U32)Eng);
5904
5905 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5906
5907 *u32Stamp = HAL_TSP_Filein_GetTimeStamp(eFileEng);
5908 TSP_RETURN(E_TSP_OK);
5909 }
5910
MDrv_TSP_FILE_Eng_GetFileInTimeStamp(TSP_FILE_ENG Eng,MS_U32 * u32TSLen)5911 TSP_Result MDrv_TSP_FILE_Eng_GetFileInTimeStamp(TSP_FILE_ENG Eng, MS_U32* u32TSLen)
5912 {
5913 TSP_ENTRY();
5914
5915 FILEENG_SEQ eFileEng = E_FILEENG_INVALID;
5916 eFileEng = HAL_TSP_FilePath2Tsif_Mapping((MS_U32)Eng);
5917
5918 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5919
5920 *u32TSLen = HAL_TSP_Filein_PktTimeStamp(eFileEng);
5921 TSP_RETURN(E_TSP_OK);
5922 }
5923
MDrv_TSP_FILE_Eng_GetFileInCurReadAddr(TSP_FILE_ENG Eng,MS_PHY * pu32Addr)5924 TSP_Result MDrv_TSP_FILE_Eng_GetFileInCurReadAddr(TSP_FILE_ENG Eng, MS_PHY *pu32Addr)
5925 {
5926 TSP_ENTRY();
5927
5928 FILEENG_SEQ eFileEng = E_FILEENG_INVALID;
5929 eFileEng = HAL_TSP_FilePath2Tsif_Mapping((MS_U32)Eng);
5930
5931 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5932
5933 HAL_TSP_Filein_GetCurAddr(eFileEng,pu32Addr);
5934
5935 TSP_RETURN(E_TSP_OK);
5936 }
5937
MDrv_TSP_FILE_Eng_MOBF_Enable(TSP_FILE_ENG eEng,MS_BOOL bEnable,MS_U32 u32Key)5938 TSP_Result MDrv_TSP_FILE_Eng_MOBF_Enable(TSP_FILE_ENG eEng, MS_BOOL bEnable, MS_U32 u32Key)
5939 {
5940 TSP_ENTRY();
5941
5942 FILEENG_SEQ eFileEng = E_FILEENG_INVALID;
5943 eFileEng = HAL_TSP_FilePath2Tsif_Mapping((MS_U32)eEng);
5944
5945 TSP_RES_ALLOC_TSPPATH_CHECK(eFileEng);
5946
5947 HAL_TSP_Filein_MOBF_Enable(eFileEng, bEnable, u32Key);
5948
5949 TSP_RETURN(E_TSP_OK);
5950 }
5951
5952 // -------------------------------------------------------------
5953 // Debug table
5954 // -------------------------------------------------------------
5955 #ifdef DEBUG_TABLE_SUPPORT
5956
_TSP_DrvHal_DstMapping(DrvTSP_AVFIFO eDebugFifo)5957 static TSP_DST_SEQ _TSP_DrvHal_DstMapping(DrvTSP_AVFIFO eDebugFifo)
5958 {
5959 TSP_DST_SEQ eRetDst = E_TSP_DST_INVALID;
5960
5961 switch(eDebugFifo)
5962 {
5963 case E_DRVTSP_AVFIFO_VIDEO ... E_DRVTSP_AVFIFO_VIDEO8:
5964 eRetDst= (TSP_DST_SEQ)(E_TSP_DST_FIFO_VIDEO + (eDebugFifo - E_DRVTSP_AVFIFO_VIDEO));
5965 break;
5966 case E_DRVTSP_AVFIFO_AUDIO ... E_DRVTSP_AVFIFO_AUDIOF:
5967 eRetDst = (TSP_DST_SEQ)(E_TSP_DST_FIFO_AUDIO + (eDebugFifo - E_DRVTSP_AVFIFO_AUDIO));
5968 break;
5969 default:
5970 TSP_DBG(E_TSP_DBG_MUST, "[ERROR][%s][%d] UnSupport Debug AV Type!\n",__FUNCTION__,__LINE__);
5971 break;
5972 }
5973
5974 return eRetDst;
5975 }
5976
_TSP_DrvHal_FlowMapping(DrvTSP_Flow eDebugFlow)5977 static TSP_HAL_FLOW _TSP_DrvHal_FlowMapping(DrvTSP_Flow eDebugFlow)
5978 {
5979 TSP_HAL_FLOW eHalFlow = E_TSP_HAL_FLOW_INVALID;
5980
5981 switch(eDebugFlow)
5982 {
5983 case E_DRVTSP_FLOW_LIVE0:
5984 eHalFlow= E_TSP_HAL_FLOW_LIVE0;
5985 break;
5986 case E_DRVTSP_FLOW_LIVE1:
5987 eHalFlow= E_TSP_HAL_FLOW_LIVE1;
5988 break;
5989 case E_DRVTSP_FLOW_LIVE2:
5990 eHalFlow= E_TSP_HAL_FLOW_LIVE2;
5991 break;
5992 case E_DRVTSP_FLOW_LIVE3:
5993 eHalFlow= E_TSP_HAL_FLOW_LIVE3;
5994 break;
5995 case E_DRVTSP_FLOW_FILE0:
5996 eHalFlow= E_TSP_HAL_FLOW_FILE0;
5997 break;
5998 case E_DRVTSP_FLOW_FILE1:
5999 eHalFlow= E_TSP_HAL_FLOW_FILE1;
6000 break;
6001 case E_DRVTSP_FLOW_FILE2:
6002 eHalFlow= E_TSP_HAL_FLOW_FILE2;
6003 break;
6004 case E_DRVTSP_FLOW_FILE3:
6005 eHalFlow= E_TSP_HAL_FLOW_FILE3;
6006 break;
6007 case E_DRVTSP_FLOW_LIVE4:
6008 case E_DRVTSP_FLOW_FILE4:
6009 eHalFlow= E_TSP_HAL_FLOW_LIVE4;
6010 break;
6011 case E_DRVTSP_FLOW_LIVE5:
6012 case E_DRVTSP_FLOW_FILE5:
6013 eHalFlow= E_TSP_HAL_FLOW_LIVE5;
6014 break;
6015 case E_DRVTSP_FLOW_LIVE6:
6016 case E_DRVTSP_FLOW_FILE6:
6017 eHalFlow= E_TSP_HAL_FLOW_LIVE6;
6018 break;
6019 case E_DRVTSP_FLOW_MMFI0:
6020 eHalFlow= E_TSP_HAL_FLOW_MMFI0;
6021 break;
6022 case E_DRVTSP_FLOW_MMFI1:
6023 eHalFlow= E_TSP_HAL_FLOW_MMFI1;
6024 break;
6025 default:
6026 TSP_DBG(E_TSP_DBG_MUST, "[ERROR][%s][%d] UnSupport Debug Flow !\n",__FUNCTION__,__LINE__);
6027 break;
6028 }
6029
6030 return eHalFlow;
6031 }
6032
MDrv_TSP_Get_DisContiCnt(DrvTSP_Debug_Cmd eCmd,DrvTSP_AVFIFO eAvType,DrvTSP_Flow eFlow,MS_U32 * pu32Cnt)6033 TSP_Result MDrv_TSP_Get_DisContiCnt(DrvTSP_Debug_Cmd eCmd, DrvTSP_AVFIFO eAvType, DrvTSP_Flow eFlow, MS_U32 *pu32Cnt)
6034 {
6035 TSP_DST_SEQ eDstType = _TSP_DrvHal_DstMapping(eAvType);
6036 TSP_HAL_FLOW eHalFlow = _TSP_DrvHal_FlowMapping(eFlow);
6037 TSP_SRC_SEQ ePktDmx = HAL_TSP_Debug_Flow2PktDmx_Mapping(eHalFlow);
6038
6039 if(eDstType==E_TSP_DST_INVALID || eHalFlow==E_TSP_HAL_FLOW_INVALID || ePktDmx==E_TSP_SRC_INVALID)
6040 {
6041 return E_TSP_FAIL;
6042 }
6043
6044 TSP_ENTRY();
6045
6046 HAL_TSP_Debug_DropDisPktCnt_Src(eDstType,ePktDmx);
6047 HAL_TSP_Debug_DisPktCnt_Load(eDstType,FALSE,TRUE);
6048 *pu32Cnt = HAL_TSP_Debug_DropDisPktCnt_Get(ePktDmx, FALSE);
6049
6050 switch(eCmd)
6051 {
6052 case E_DRVTSP_DEBUG_CMD_NONE:
6053 case E_DRVTSP_DEBUG_CMD_DISABLE:
6054 break;
6055 case E_DRVTSP_DEBUG_CMD_CLEAR:
6056 HAL_TSP_Debug_ClrSrcSel(ePktDmx);
6057 HAL_TSP_Debug_DisPktCnt_Clear(eDstType);
6058 break;
6059 case E_DRVTSP_DEBUG_CMD_ENABLE:
6060 HAL_TSP_Debug_DisPktCnt_Load(eDstType,TRUE,TRUE);
6061 break;
6062 default:
6063 TSP_DBG(E_TSP_DBG_MUST, "[%s][%d] UnSupported Debug Cmd !!\n",__FUNCTION__,__LINE__);
6064 TSP_RETURN(E_TSP_FAIL);
6065 }
6066
6067 TSP_RETURN(E_TSP_OK);
6068 }
6069
MDrv_TSP_Get_DropPktCnt(DrvTSP_Debug_Cmd eCmd,DrvTSP_AVFIFO eAvType,DrvTSP_Flow eFlow,MS_U32 * pu32Cnt)6070 TSP_Result MDrv_TSP_Get_DropPktCnt(DrvTSP_Debug_Cmd eCmd, DrvTSP_AVFIFO eAvType, DrvTSP_Flow eFlow, MS_U32 *pu32Cnt)
6071 {
6072 TSP_DST_SEQ eDstType = _TSP_DrvHal_DstMapping(eAvType);
6073 TSP_HAL_FLOW eHalFlow = _TSP_DrvHal_FlowMapping(eFlow);
6074 TSP_SRC_SEQ ePktDmx = HAL_TSP_Debug_Flow2PktDmx_Mapping(eHalFlow);
6075
6076 if(eDstType==E_TSP_DST_INVALID || eHalFlow==E_TSP_HAL_FLOW_INVALID || ePktDmx==E_TSP_SRC_INVALID)
6077 {
6078 return E_TSP_FAIL;
6079 }
6080
6081 TSP_ENTRY();
6082
6083 HAL_TSP_Debug_DropDisPktCnt_Src(eDstType,ePktDmx);
6084 HAL_TSP_Debug_DropPktCnt_Load(eDstType, FALSE);
6085 *pu32Cnt = HAL_TSP_Debug_DropDisPktCnt_Get(ePktDmx, TRUE);
6086
6087 switch(eCmd)
6088 {
6089 case E_DRVTSP_DEBUG_CMD_NONE:
6090 case E_DRVTSP_DEBUG_CMD_DISABLE:
6091 break;
6092 case E_DRVTSP_DEBUG_CMD_CLEAR:
6093 HAL_TSP_Debug_ClrSrcSel(ePktDmx);
6094 HAL_TSP_Debug_DropPktCnt_Clear(eDstType);
6095 break;
6096 case E_DRVTSP_DEBUG_CMD_ENABLE:
6097 HAL_TSP_Debug_DropPktCnt_Load(eDstType, TRUE);
6098 break;
6099 default:
6100 TSP_DBG(E_TSP_DBG_MUST, "[%s][%d] UnSupported Debug Cmd !!\n",__FUNCTION__,__LINE__);
6101 TSP_RETURN(E_TSP_FAIL);
6102 }
6103
6104 TSP_RETURN(E_TSP_OK);
6105 }
6106
MDrv_TSP_Get_LockPktCnt(DrvTSP_Debug_Cmd eCmd,DrvTSP_Flow eFlow,MS_U32 * pu32Cnt)6107 TSP_Result MDrv_TSP_Get_LockPktCnt(DrvTSP_Debug_Cmd eCmd, DrvTSP_Flow eFlow, MS_U32 *pu32Cnt)
6108 {
6109 TSP_TSIF eTSIF;
6110
6111 switch(eFlow)
6112 {
6113 case E_DRVTSP_FLOW_LIVE0:
6114 eTSIF = E_TSP_TSIF_0;
6115 break;
6116 case E_DRVTSP_FLOW_LIVE1:
6117 eTSIF = E_TSP_TSIF_1;
6118 break;
6119 case E_DRVTSP_FLOW_LIVE2:
6120 eTSIF = E_TSP_TSIF_2;
6121 break;
6122 case E_DRVTSP_FLOW_LIVE3:
6123 eTSIF = E_TSP_TSIF_3;
6124 break;
6125 case E_DRVTSP_FLOW_LIVE4:
6126 eTSIF = E_TSP_TSIF_4;
6127 break;
6128 case E_DRVTSP_FLOW_LIVE5:
6129 eTSIF = E_TSP_TSIF_5;
6130 break;
6131 case E_DRVTSP_FLOW_LIVE6:
6132 eTSIF = E_TSP_TSIF_6;
6133 break;
6134 default:
6135 TSP_DBG(E_TSP_DBG_MUST, "[%s][%d] UnSupport Debug Flow !!\n",__FUNCTION__,__LINE__);
6136 return E_TSP_FAIL;
6137 }
6138
6139 TSP_HAL_TSIF eHalTSIF = _TSP_DrvHal_TSIFMapping(eTSIF);
6140
6141 if(eHalTSIF==E_TSP_HAL_TSIF_INVALID)
6142 {
6143 return E_TSP_FAIL;
6144 }
6145
6146 MS_U32 u32TSIF = HAL_TSP_TsifMapping(eHalTSIF, FALSE);
6147
6148 TSP_RES_ALLOC_TSPPATH_CHECK(u32TSIF);
6149
6150 TSP_ENTRY();
6151
6152 HAL_TSP_Debug_LockPktCnt_Src(u32TSIF);
6153 HAL_TSP_Debug_LockPktCnt_Load(u32TSIF,FALSE);
6154 *pu32Cnt = HAL_TSP_Debug_LockPktCnt_Get(u32TSIF, TRUE);
6155
6156 switch(eCmd)
6157 {
6158 case E_DRVTSP_DEBUG_CMD_NONE:
6159 case E_DRVTSP_DEBUG_CMD_DISABLE:
6160 break;
6161 case E_DRVTSP_DEBUG_CMD_CLEAR:
6162 HAL_TSP_Debug_LockPktCnt_Clear(u32TSIF);
6163 break;
6164 case E_DRVTSP_DEBUG_CMD_ENABLE:
6165 HAL_TSP_Debug_LockPktCnt_Load(u32TSIF,TRUE);
6166 break;
6167 default:
6168 TSP_DBG(E_TSP_DBG_MUST, "[%s][%d] UnSupported Debug Cmd !!\n",__FUNCTION__,__LINE__);
6169 TSP_RETURN(E_TSP_FAIL);
6170 }
6171
6172 TSP_RETURN(E_TSP_OK);
6173 }
6174
MDrv_TSP_Get_AVPktCnt(DrvTSP_Debug_Cmd eCmd,DrvTSP_AVFIFO eAvType,DrvTSP_Flow eFlow,MS_U32 * pu32Cnt)6175 TSP_Result MDrv_TSP_Get_AVPktCnt(DrvTSP_Debug_Cmd eCmd, DrvTSP_AVFIFO eAvType, DrvTSP_Flow eFlow, MS_U32 *pu32Cnt)
6176 {
6177 TSP_DST_SEQ eDstType = _TSP_DrvHal_DstMapping(eAvType);
6178 TSP_HAL_FLOW eHalFlow = _TSP_DrvHal_FlowMapping(eFlow);
6179 TSP_SRC_SEQ ePktDmx = HAL_TSP_Debug_Flow2PktDmx_Mapping(eHalFlow);
6180
6181 if(eDstType==E_TSP_DST_INVALID || eHalFlow==E_TSP_HAL_FLOW_INVALID || ePktDmx==E_TSP_SRC_INVALID)
6182 {
6183 return E_TSP_FAIL;
6184 }
6185
6186 TSP_ENTRY();
6187
6188 HAL_TSP_Debug_AvPktCnt_Src(eDstType,ePktDmx);
6189 HAL_TSP_Debug_AvPktCnt_Load(eDstType, FALSE);
6190 *pu32Cnt = HAL_TSP_Debug_AvPktCnt_Get(eDstType);
6191
6192 switch(eCmd)
6193 {
6194 case E_DRVTSP_DEBUG_CMD_NONE:
6195 case E_DRVTSP_DEBUG_CMD_DISABLE:
6196 break;
6197 case E_DRVTSP_DEBUG_CMD_CLEAR:
6198 HAL_TSP_Debug_ClrSrcSel(ePktDmx);
6199 HAL_TSP_Debug_AvPktCnt_Clear(eDstType);
6200 break;
6201 case E_DRVTSP_DEBUG_CMD_ENABLE:
6202 HAL_TSP_Debug_AvPktCnt_Load(eDstType, TRUE);
6203 break;
6204 default:
6205 TSP_DBG(E_TSP_DBG_MUST, "[%s][%d] UnSupported Debug Cmd !!\n",__FUNCTION__,__LINE__);
6206 TSP_RETURN(E_TSP_FAIL);
6207 }
6208
6209 TSP_RETURN(E_TSP_OK);
6210
6211 }
6212
6213 #if 0
6214 TSP_Result MDrv_TSP_Get_ErrPktCnt(DrvTSP_ErrPktCnt_info* tspInfo, MS_U32* pu32Cnt)
6215 {
6216 MS_U32 u32SrcPath = 0;
6217
6218 switch(tspInfo->TspTsif)
6219 {
6220 case E_DRVTSP_DEBUG_TSIF_TS0:
6221 u32SrcPath = 0;
6222 break;
6223 case E_DRVTSP_DEBUG_TSIF_TS1:
6224 u32SrcPath = 1;
6225 break;
6226 case E_DRVTSP_DEBUG_TSIF_TS2:
6227 u32SrcPath = 2;
6228 break;
6229 case E_DRVTSP_DEBUG_TSIF_TS3:
6230 u32SrcPath = 3;
6231 break;
6232 default:
6233 break;
6234 }
6235
6236 TSP_ENTRY();
6237
6238 switch(tspInfo->TspCmd)
6239 {
6240 case E_DRVTSP_DEBUG_CMD_NONE:
6241 break;
6242 case E_DRVTSP_DEBUG_CMD_CLEAR:
6243 HAL_TSP_Clr_Src_Set(u32SrcPath);
6244 HAL_TSP_ERRPKTCnt_Clear(u32SrcPath);
6245 break;
6246 case E_DRVTSP_DEBUG_CMD_ENABLE:
6247 case E_DRVTSP_DEBUG_CMD_DISABLE:
6248 HAL_TSP_ERRPKTCnt_Load_En(u32SrcPath,((tspInfo->TspCmd == E_DRVTSP_DEBUG_CMD_ENABLE)? TRUE : FALSE));
6249 break;
6250 default:
6251 ULOGE("TSP", "[%s][%d] operation not support !!\n",__FUNCTION__,__LINE__);
6252 TSP_RETURN(E_TSP_FAIL);
6253 }
6254
6255 HAL_TSP_ERRPKTCnt_Sel(u32SrcPath);
6256 *pu32Cnt = HAL_TSP_ERRPKTCnt_Get();
6257
6258 TSP_RETURN(E_TSP_OK);
6259 }
6260 #endif
6261
6262 #endif
6263
6264
6265 //-------------------------------------------------------------------------------------------------
6266 ///Set or Get merge stream sync byte
6267 /// @param eIf \b IN: Eunm value of TSP TSIF selection
6268 /// @param u8StrId \b IN: Stream index
6269 /// @param pu8SyncByte \b IN: Pointer to store sync byte of merege streams
6270 /// @param bSet \b IN: TRUE to setting data or FALSE to getting table
6271 /// @return DRVTSP_OK - Success
6272 /// @return DRVTSP_FAIL - Failure
6273 /// @note: Currently, maxmum number is 8, and don't call this API when stream processing is started
6274 //-------------------------------------------------------------------------------------------------
MDrv_TSP_MStr_SyncByte(DrvTSP_If eTsIf,MS_U8 u8StrId,MS_U8 * pu8SyncByte,MS_BOOL bSet)6275 TSP_Result MDrv_TSP_MStr_SyncByte(DrvTSP_If eTsIf, MS_U8 u8StrId, MS_U8* pu8SyncByte, MS_BOOL bSet)
6276 {
6277 #ifdef MERGE_STR_SUPPORT
6278 MS_U8 u8Path = 0;
6279
6280 if(u8StrId >= TSP_MERGESTREAM_NUM)
6281 {
6282 TSP_DBG(E_TSP_DBG_MUST, "[%s][%d] Stream index out of range !!\n",__FUNCTION__,__LINE__);
6283 return E_TSP_FAIL;
6284 }
6285 TSP_HAL_TSIF eHalTSIF = MDrv_TSP_TsifMapping(eTsIf);
6286 u8Path = HAL_TSP_TsifMapping(eHalTSIF, FALSE);
6287
6288 TSP_RES_ALLOC_TSPPATH_CHECK(u8Path);
6289
6290 TSP_ENTRY();
6291
6292 if(HAL_TSP_PktConverter_SetSyncByte(u8Path, u8StrId, pu8SyncByte, bSet) == FALSE)
6293 {
6294 TSP_RETURN(E_TSP_FAIL);
6295 }
6296
6297 TSP_RETURN(E_TSP_OK);
6298
6299 #else
6300 return E_TSP_FAIL_NOT_SUPPORTED;
6301 #endif
6302 }
6303
6304
6305 //-------------------------------------------------------------------------------------------------
6306 /// Get current system time clock (STC) of TSP
6307 /// @param u32EngId \b IN: index of TSP engine [ 0 .. (@ref DRVTSP_ENGINE_NUM-1) ]
6308 /// @param pu32STC_32 \b OUT: pointer of STC[32] return
6309 /// @param pu32STC \b OUT: pointer of STC[31:0] return
6310 /// @return TSP_Result
6311 //-------------------------------------------------------------------------------------------------
MDrv_TSP_GetSTC(MS_U32 u32EngId,MS_U32 * pu32STC_H,MS_U32 * pu32STC)6312 TSP_Result MDrv_TSP_GetSTC(MS_U32 u32EngId, MS_U32 *pu32STC_H, MS_U32 *pu32STC)
6313 {
6314 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
6315 TSP_CHECK(pu32STC_H, "[%04d] NULL pointer\n", __LINE__);
6316 TSP_CHECK(pu32STC, "[%04d] NULL pointer\n", __LINE__);
6317
6318 TSP_ENTRY();
6319
6320 TSP_RES_ALLOC_STC_CHECK(u32EngId);
6321 //HAL_TSP_CMDQ_GetSTC(pu32STC_H, pu32STC);
6322 //HAL_TSP_GetSTC(pu32STC_H, pu32STC);
6323 HAL_TSP_STC33_CmdQGet(pu32STC_H, pu32STC);
6324
6325 TSP_RETURN(E_TSP_OK);
6326 }
6327
6328
6329 //-------------------------------------------------------------------------------------------------
6330 /// Get PRC of TSP
6331 /// @param u32EngId \b IN: index of TSP engine [ 0 .. (@ref DRVTSP_ENGINE_NUM-1) ]
6332 /// @param pu32Pcr_32 \b OUT: pointer of STC[32] return
6333 /// @param pu32Pcr \b OUT: pointer of STC[31:0] return
6334 /// @return TSP_Result
6335 //-------------------------------------------------------------------------------------------------
MDrv_TSP_GetPCR(MS_U32 u32EngId,MS_U32 * pu32PCR_H,MS_U32 * pu32PCR)6336 TSP_Result MDrv_TSP_GetPCR(MS_U32 u32EngId, MS_U32 *pu32PCR_H, MS_U32 *pu32PCR)
6337 {
6338 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
6339 TSP_CHECK(pu32PCR_H, "[%04d] NULL pointer\n", __LINE__);
6340 TSP_CHECK(pu32PCR, "[%04d] NULL pointer\n", __LINE__);
6341
6342 TSP_ENTRY();
6343
6344 HAL_TSP_PcrFlt_GetPcr(u32EngId, pu32PCR_H, pu32PCR);
6345
6346 TSP_RETURN(E_TSP_OK);
6347 }
6348
6349
6350 //-------------------------------------------------------------------------------------------------
6351 /// Get TSP driver version
6352 /// @param <IN> \b const MS_U8 **pVerString :
6353 /// @param <RET> \b : when get ok, return the pointer to the driver version
6354 //-------------------------------------------------------------------------------------------------
MDrv_TSP_GetLibVer(const MSIF_Version ** ppVersion)6355 TSP_Result MDrv_TSP_GetLibVer(const MSIF_Version **ppVersion)
6356 {
6357 // No mutex check, it can be called before Init
6358 if (!ppVersion)
6359 {
6360 return E_TSP_FAIL;
6361 }
6362
6363 *ppVersion = &_drv_tsp_version;
6364
6365 return E_TSP_OK;
6366 }
6367
6368
MDrv_TSP_GetStatus(TSP_HW_Status * HW_Status,TSP_SW_Status * SW_Status)6369 TSP_Result MDrv_TSP_GetStatus(TSP_HW_Status *HW_Status, TSP_SW_Status *SW_Status)
6370 {
6371 TSP_ENTRY();
6372 if (HAL_TSP_HCMD_Alive())
6373 {
6374 *HW_Status = E_TSP_HW_ALIVE;
6375 }
6376 else
6377 {
6378 *HW_Status = E_TSP_HW_DEALIVE;
6379 }
6380 *SW_Status = _ptsp_res->_tspInfo.Status;
6381
6382 TSP_RETURN(E_TSP_OK);
6383 }
6384
MDrv_TSP_GetFWVER(MS_U32 * u32FWVer)6385 TSP_Result MDrv_TSP_GetFWVER(MS_U32* u32FWVer)
6386 {
6387 TSP_ENTRY();
6388 *u32FWVer = HAL_TSP_HCMD_GetInfo(INFO_FW_VERSION);
6389 TSP_RETURN(E_TSP_OK);
6390 }
6391
6392 //@F_TODO api layer throw a enum that we don't have. check u8IfUID
MDrv_TSP_GetTSIFStatus(TSP_TSIF eTSIF,TSP_TSPad * ePad,MS_BOOL * pbClkInv,MS_BOOL * pbExtSyc,MS_BOOL * pbParl)6393 TSP_Result MDrv_TSP_GetTSIFStatus(TSP_TSIF eTSIF, TSP_TSPad* ePad, MS_BOOL* pbClkInv, MS_BOOL* pbExtSyc, MS_BOOL* pbParl)
6394 {
6395 TSP_Result Res = E_TSP_OK;
6396 MS_U32 u32TSIF;
6397 TSP_HAL_TSIF eHalTSIF = _TSP_DrvHal_TSIFMapping(eTSIF);
6398 //if live-in and file-in of a DmxFlow map to diff TSIF, return the status of the live-in one
6399 u32TSIF = HAL_TSP_TsifMapping(eHalTSIF, FALSE);
6400
6401 TSP_RES_ALLOC_TSPPATH_CHECK(u32TSIF);
6402
6403 *ePad = _ptsp_res->TsIf_Src[u32TSIF].ePad;
6404 *pbClkInv = _ptsp_res->TsIf_Src[u32TSIF].bClkInv;
6405 *pbExtSyc = _ptsp_res->TsIf_Src[u32TSIF].bExtSync;
6406 *pbParl = _ptsp_res->TsIf_Src[u32TSIF].bParallel;
6407
6408 return Res;
6409 }
6410
6411 //--------------------------------------------------------------------------------------------------
6412 /// Get command queue fifo level
6413 /// @param pu8FifoLevel \b OUT: fifo level, 0~3
6414 /// @return TSP_Result
6415 /// @note
6416 //--------------------------------------------------------------------------------------------------
MDrv_TSP_CmdQFifo_Status(MS_U8 * pu8FifoLevel)6417 TSP_Result MDrv_TSP_CmdQFifo_Status(MS_U8 *pu8FifoLevel)
6418 {
6419 TSP_ENTRY();
6420 FILEENG_SEQ eFileEng = HAL_TSP_GetDefaultFileinEng();
6421 *pu8FifoLevel = HAL_TSP_Filein_CmdQLv(eFileEng);
6422 TSP_RETURN(E_TSP_OK);
6423 }
6424
MDrv_TSP_SetDbgLevel(TSP_DbgLevel DbgLevel)6425 TSP_Result MDrv_TSP_SetDbgLevel(TSP_DbgLevel DbgLevel)
6426 {
6427 _u32DbgLevel = DbgLevel;
6428 return E_TSP_OK;
6429 }
6430
_TSP_DrvHal_CapsMapping(TSP_Caps eCap)6431 static TSP_HAL_CAP_TYPE _TSP_DrvHal_CapsMapping(TSP_Caps eCap)
6432 {
6433 TSP_HAL_CAP_TYPE eRetCapType = E_TSP_HAL_CAP_VAL_NULL;
6434
6435 switch(eCap)
6436 {
6437 case E_TSP_CAP_PIDFLT_NUM:
6438 eRetCapType = E_TSP_HAL_CAP_TYPE_PIDFLT_NUM;
6439 break;
6440 case E_TSP_CAP_SECFLT_NUM:
6441 eRetCapType = E_TSP_HAL_CAP_TYPE_SECFLT_NUM;
6442 break;
6443 case E_TSP_CAP_SECBUF_NUM:
6444 eRetCapType = E_TSP_HAL_CAP_TYPE_SECBUF_NUM;
6445 break;
6446 case E_TSP_CAP_RECENG_NUM:
6447 eRetCapType = E_TSP_HAL_CAP_TYPE_RECENG_NUM;
6448 break;
6449 case E_TSP_CAP_RECFLT_NUM:
6450 eRetCapType = E_TSP_HAL_CAP_TYPE_RECFLT_NUM;
6451 break;
6452 case E_TSP_CAP_MMFI_AUDIO_FILTER_NUM:
6453 eRetCapType = E_TSP_HAL_CAP_TYPE_MMFI_AUDIO_FILTER_NUM;
6454 break;
6455 case E_TSP_CAP_MMFI_V3D_FILTER_NUM:
6456 eRetCapType = E_TSP_HAL_CAP_TYPE_MMFI_V3D_FILTER_NUM;
6457 break;
6458 case E_TSP_CAP_TSIF_NUM:
6459 eRetCapType = E_TSP_HAL_CAP_TYPE_TSIF_NUM;
6460 break;
6461 case E_TSP_CAP_DEMOD_NUM:
6462 eRetCapType = E_TSP_HAL_CAP_TYPE_DEMOD_NUM;
6463 break;
6464 case E_TSP_CAP_TSPAD_NUM:
6465 eRetCapType = E_TSP_HAL_CAP_TYPE_TSPAD_NUM;
6466 break;
6467 case E_TSP_CAP_VQ_NUM:
6468 eRetCapType = E_TSP_HAL_CAP_TYPE_VQ_NUM;
6469 break;
6470 case E_TSP_CAP_CAFLT_NUM:
6471 eRetCapType = E_TSP_HAL_CAP_TYPE_CAFLT_NUM;
6472 break;
6473 case E_TSP_CAP_FW_ALIGN:
6474 eRetCapType = E_TSP_HAL_CAP_TYPE_FW_ALIGN;
6475 break;
6476 case E_TSP_CAP_VQ_ALIGN:
6477 eRetCapType = E_TSP_HAL_CAP_TYPE_VQ_ALIGN;
6478 break;
6479 case E_TSP_CAP_VQ_PITCH:
6480 eRetCapType = E_TSP_HAL_CAP_TYPE_VQ_PITCH;
6481 break;
6482 case E_TSP_CAP_SECBUF_ALIGN:
6483 eRetCapType = E_TSP_HAL_CAP_TYPE_SECBUF_ALIGN;
6484 break;
6485 case E_TSP_CAP_PVR_ALIGN:
6486 eRetCapType = E_TSP_HAL_CAP_TYPE_PVR_ALIGN;
6487 break;
6488 case E_TSP_CAP_HW_TYPE:
6489 eRetCapType = E_TSP_HAL_CAP_TYPE_HW_TYPE;
6490 break;
6491 case E_TSP_CAP_VFIFO_NUM:
6492 eRetCapType = E_TSP_HAL_CAP_VAL_VFIFO_NUM;
6493 break;
6494 case E_TSP_CAP_AFIFO_NUM:
6495 eRetCapType = E_TSP_HAL_CAP_TYPE_AFIFO_NUM;
6496 break;
6497 case E_TSP_CAP_HWPCR_SUPPORT:
6498 eRetCapType = E_TSP_HAL_CAP_TYPE_HWPCR_SUPPORT;
6499 break;
6500 case E_TSP_CAP_PCRFLT_START_IDX:
6501 eRetCapType = E_TSP_HAL_CAP_TYPE_PCRFLT_START_IDX;
6502 break;
6503 case E_TSP_CAP_FIQ_NUM:
6504 eRetCapType = E_TSP_HAL_CAP_FIQ_NUM;
6505 break;
6506 case E_TSP_CAP_RECFLT_IDX:
6507 eRetCapType = E_TSP_HAL_CAP_TYPE_RECFLT_IDX;
6508 break;
6509 case E_TSP_CAP_FW_BUF_SIZE:
6510 eRetCapType = E_TSP_HAL_CAP_FW_BUF_SIZE;
6511 break;
6512 case E_TSP_CAP_FW_BUF_RANGE:
6513 eRetCapType = E_TSP_HAL_CAP_FW_BUF_RANGE;
6514 break;
6515 case E_TSP_CAP_VQ_BUF_RANGE:
6516 eRetCapType = E_TSP_HAL_CAP_VQ_BUF_RANGE;
6517 break;
6518 case E_TSP_CAP_SEC_BUF_RANGE:
6519 eRetCapType = E_TSP_HAL_CAP_SEC_BUF_RANGE;
6520 break;
6521 default:
6522 TSP_DBG(E_TSP_DBG_MUST, "[%s][%d] Not support !!\n",__FUNCTION__,__LINE__);
6523 break;
6524 }
6525
6526 return eRetCapType;
6527 }
6528
6529 //-------------------------------------------------------------------------------------------------
6530 /// Query CAPs and get it's information
6531 /// @return TSP_Result
6532 //-------------------------------------------------------------------------------------------------
MDrv_TSP_GetCaps(TSP_Caps eCap,MS_U32 * pu32CapInfo)6533 TSP_Result MDrv_TSP_GetCaps(TSP_Caps eCap, MS_U32 *pu32CapInfo)
6534 {
6535 TSP_HAL_CAP_TYPE _eCap;
6536
6537 if (eCap >= E_TSP_CAP_NULL)
6538 {
6539 return E_TSP_FAIL;
6540 }
6541
6542 if(eCap == E_TSP_CAP_RESOURCE_SIZE)
6543 {
6544 *pu32CapInfo = sizeof(TSP_RESOURCE_PRIVATE);
6545 return E_TSP_OK;
6546 }
6547
6548 _eCap = _TSP_DrvHal_CapsMapping(eCap);
6549 if(_eCap == E_TSP_HAL_CAP_TYPE_NULL) //Not support
6550 {
6551 return E_TSP_FAIL;
6552 }
6553
6554 switch(_eCap)
6555 {
6556 case E_TSP_HAL_CAP_TYPE_PIDFLT_NUM:
6557 *pu32CapInfo = (_tspFltIdMap.u32PcrFltId_End - _tspFltIdMap.u32PidFltId_Start);
6558 return E_TSP_OK;
6559 case E_TSP_HAL_CAP_TYPE_SECFLT_NUM:
6560 *pu32CapInfo = (_tspFltIdMap.u32SecFltId_End - _tspFltIdMap.u32SecFltId_Start);
6561 return E_TSP_OK;
6562 case E_TSP_HAL_CAP_TYPE_SECBUF_NUM:
6563 *pu32CapInfo = (_tspFltIdMap.u32SecBufId_End - _tspFltIdMap.u32SecBufId_Start);
6564 return E_TSP_OK;
6565 case E_TSP_HAL_CAP_TYPE_RECFLT_NUM:
6566 *pu32CapInfo = _tspFltIdMap.u32PidFltId_End;
6567 return E_TSP_OK;
6568 case E_TSP_HAL_CAP_TYPE_CAFLT_NUM:
6569 *pu32CapInfo = (_tspFltIdMap.u32PidFltId_End - _tspFltIdMap.u32PidFltId_Start);
6570 return E_TSP_OK;
6571 case E_TSP_HAL_CAP_TYPE_PCRFLT_START_IDX:
6572 *pu32CapInfo = _tspFltIdMap.u32PcrFltId_Start;
6573 return E_TSP_OK;
6574 case E_TSP_HAL_CAP_TYPE_RECFLT_IDX:
6575 *pu32CapInfo = _tspFltIdMap.u32RecFltIdx;
6576 return E_TSP_OK;
6577 default:
6578 return (HAL_TSP_GetCaps(_eCap, pu32CapInfo) == FALSE)? E_TSP_FAIL : E_TSP_OK;
6579 }
6580
6581 }
6582
MDrv_TSP_GetFileInTimeStamp(MS_U32 * u32TSLen)6583 TSP_Result MDrv_TSP_GetFileInTimeStamp(MS_U32* u32TSLen)
6584 {
6585 TSP_ENTRY();
6586 FILEENG_SEQ eFileEng = HAL_TSP_GetDefaultFileinEng();
6587 *u32TSLen = HAL_TSP_Filein_PktTimeStamp(eFileEng);
6588 TSP_RETURN(E_TSP_OK);
6589 }
6590
6591 //-------------------------------------------------------------------------------------------------
6592 /// Get Last General Error Return Code
6593 /// @return TSP_Result
6594 /// @note
6595 /// Last error return code is reset after calling this function.
6596 //-------------------------------------------------------------------------------------------------
MDrv_TSP_GetLastErr(void)6597 TSP_Result MDrv_TSP_GetLastErr(void)
6598 {
6599 TSP_Result ret;
6600 ret = (TSP_Result) _ptsp_res->_tspInfo.LastErr;
6601 _ptsp_res->_tspInfo.LastErr = E_TSP_OK;
6602 return ret;
6603 }
6604
MDRV_TSP_FAIL_NOT_SUPPORTED(void)6605 TSP_Result MDRV_TSP_FAIL_NOT_SUPPORTED(void)
6606 {
6607 return E_TSP_FAIL_NOT_SUPPORTED;
6608 }
6609
6610
6611 //[RESERVED]
MDrv_TSP_Alive(MS_U32 u32EngId)6612 TSP_Result MDrv_TSP_Alive(MS_U32 u32EngId)
6613 {
6614 TSP_ENTRY();
6615 if (HAL_TSP_HCMD_Alive())
6616 {
6617 TSP_RETURN(E_TSP_OK);
6618 }
6619 else
6620 {
6621 TSP_RETURN(E_TSP_FAIL);
6622 }
6623 }
6624
6625
6626 //[RESERVED]
MDrv_TSP_DBG_GetDBGStatus(MS_U32 u32Sel,MS_U32 * u32Status)6627 TSP_Result MDrv_TSP_DBG_GetDBGStatus(MS_U32 u32Sel, MS_U32* u32Status)
6628 {
6629 TSP_ENTRY();
6630
6631 // *u32Status = HAL_TSP_GetDBGStatus((MS_U16)u32Sel);//@F_TODO not implement yet
6632
6633 TSP_RETURN(E_TSP_OK);
6634 }
6635
6636
6637 //[RESERVED]
MDrv_TSP_DBG_TaskLine(void)6638 MS_U32 MDrv_TSP_DBG_TaskLine(void)
6639 {
6640 return _ptsp_res->_tspInfo.u32TaskLine;
6641 }
6642
6643
6644 //[RESERVED]
MDrv_TSP_DBG_FltInfo(MS_U32 u32FltId,MS_U32 u32BufId)6645 TSP_Result MDrv_TSP_DBG_FltInfo(MS_U32 u32FltId, MS_U32 u32BufId)
6646 {
6647 TSP_ENTRY();
6648
6649 // HAL_TSP_DBG_DumpFlt((MS_U16)u32FltId, (MS_U16)u32BufId); //@F_TODO not implement yet
6650
6651 TSP_RETURN(E_TSP_OK);
6652 }
6653
MDrv_TSP_PVR_Eng_FltAlloc(MS_U32 u32Eng,MS_U32 * pu32FltId)6654 TSP_Result MDrv_TSP_PVR_Eng_FltAlloc(MS_U32 u32Eng, MS_U32 *pu32FltId)
6655 {
6656 TSP_PVR_ENTRY();
6657 MS_U32 ret = E_TSP_FAIL;
6658
6659 TSP_SRC_SEQ eEngSrc = E_TSP_SRC_INVALID;
6660 if (E_TSP_PVR_PVRENG_END > u32Eng) // PVR Eng
6661 {
6662 HAL_PVR_GetEngSrc(u32Eng, &eEngSrc);
6663 ret = _MDrv_FltAllocForRec(u32Eng, eEngSrc, pu32FltId);
6664 }
6665 else
6666 {
6667 TSP_DBG(E_TSP_DBG_MUST, "[ERROR][%s][%d]Incorrect Engine type!\n",__FUNCTION__,__LINE__);
6668 }
6669
6670 TSP_PVR_RETURN(ret);
6671 }
6672
MDrv_TSP_PVR_Eng_FltFree(MS_U32 u32Eng,MS_U32 u32FltId)6673 TSP_Result MDrv_TSP_PVR_Eng_FltFree(MS_U32 u32Eng, MS_U32 u32FltId)
6674 {
6675 if (E_TSP_PVR_PVRENG_END > u32Eng) // PVR Eng
6676 {
6677 _MDrv_FltFreeForRec(u32FltId);
6678 }
6679 else
6680 {
6681 TSP_DBG(E_TSP_DBG_MUST, "[ERROR][%s][%d]Incorrect Engine type!\n",__FUNCTION__,__LINE__);
6682 }
6683 return E_TSP_OK;
6684 }
6685
MDrv_TSP_PVR_Eng_FltSetPID(MS_U32 u32Eng,MS_U32 u32FltId,MS_U32 u32PID)6686 TSP_Result MDrv_TSP_PVR_Eng_FltSetPID(MS_U32 u32Eng, MS_U32 u32FltId, MS_U32 u32PID)
6687 {
6688 if (E_TSP_PVR_PVRENG_END > u32Eng) // PVR Eng
6689 {
6690 _MDrv_FltSetPIDForRec(u32FltId, u32PID);
6691 }
6692 else
6693 {
6694 TSP_DBG(E_TSP_DBG_MUST, "[ERROR][%s][%d]Incorrect Engine type!\n",__FUNCTION__,__LINE__);
6695 }
6696
6697 return E_TSP_OK;
6698 }
6699
MDrv_TSP_PVR_Eng_FltEnable(MS_U32 u32Eng,MS_U32 u32FltId,MS_BOOL bEnable)6700 TSP_Result MDrv_TSP_PVR_Eng_FltEnable(MS_U32 u32Eng, MS_U32 u32FltId, MS_BOOL bEnable)
6701 {
6702 if (E_TSP_PVR_PVRENG_END > u32Eng) // PVR Eng
6703 {
6704 _MDrv_FltEnableForRec(u32FltId, bEnable);
6705 }
6706 else
6707 {
6708 TSP_DBG(E_TSP_DBG_MUST, "[ERROR][%s][%d]Incorrect Engine type!\n",__FUNCTION__,__LINE__);
6709 }
6710
6711 return E_TSP_OK;
6712 }
6713
MDrv_TSP_PVR_Eng_FltGetPID(MS_U32 u32Eng,MS_U32 u32FltId,MS_U32 * u32PID)6714 TSP_Result MDrv_TSP_PVR_Eng_FltGetPID(MS_U32 u32Eng, MS_U32 u32FltId, MS_U32* u32PID)
6715 {
6716 if (E_TSP_PVR_PVRENG_END > u32Eng) // PVR Eng
6717 {
6718 _MDrv_FltGetPIDForRec(u32FltId, u32PID);
6719 }
6720 else
6721 {
6722 TSP_DBG(E_TSP_DBG_MUST, "[ERROR][%s][%d]Incorrect Engine type!\n",__FUNCTION__,__LINE__);
6723 }
6724
6725 return E_TSP_OK;
6726 }
6727
MDrv_TSP_PVR_Eng_SetBuffer(MS_U32 u32Eng,MS_PHYADDR u32Start0,MS_PHYADDR u32Start1,MS_U32 u32Size0,MS_U32 u32Size1)6728 TSP_Result MDrv_TSP_PVR_Eng_SetBuffer(MS_U32 u32Eng, MS_PHYADDR u32Start0, MS_PHYADDR u32Start1, MS_U32 u32Size0, MS_U32 u32Size1)
6729 {
6730 if (E_TSP_PVR_PVRENG_END > u32Eng) // PVR Eng
6731 {
6732 _MDrv_PVR_Eng_SetBuffer(u32Eng, u32Start0, u32Start1, u32Size0, u32Size1);
6733 }
6734 else
6735 {
6736 TSP_DBG(E_TSP_DBG_MUST, "[ERROR][%s][%d]Incorrect Engine type!\n",__FUNCTION__,__LINE__);
6737 }
6738
6739 return E_TSP_OK;
6740 }
6741
MDrv_TSP_PVR_Eng_Start(MS_U32 u32Eng,MS_BOOL bPvrAll,MS_BOOL bStart)6742 TSP_Result MDrv_TSP_PVR_Eng_Start(MS_U32 u32Eng, MS_BOOL bPvrAll, MS_BOOL bStart)
6743 {
6744 if (E_TSP_PVR_PVRENG_END > u32Eng) // PVR Eng
6745 {
6746 if(bPvrAll)
6747 _MDrv_PVR_Eng_Start(u32Eng, E_TSP_DRV_PVR_RecMode_ALL, bStart);
6748 else
6749 _MDrv_PVR_Eng_Start(u32Eng, E_TSP_DRV_PVR_RecMode_PID, bStart);
6750 }
6751 else
6752 {
6753 TSP_DBG(E_TSP_DBG_MUST, "[ERROR][%s][%d]Incorrect Engine type!\n",__FUNCTION__,__LINE__);
6754 }
6755
6756 return E_TSP_OK;
6757 }
6758
MDrv_TSP_PVR_Eng_Pause(MS_U32 u32Eng,MS_BOOL bPause)6759 TSP_Result MDrv_TSP_PVR_Eng_Pause(MS_U32 u32Eng, MS_BOOL bPause)
6760 {
6761 if (E_TSP_PVR_PVRENG_END > u32Eng) // PVR Eng
6762 {
6763 _MDrv_PVR_Eng_Pause(u32Eng, bPause);
6764 }
6765 else
6766 {
6767 TSP_DBG(E_TSP_DBG_MUST, "[ERROR][%s][%d]Incorrect Engine type!\n",__FUNCTION__,__LINE__);
6768 }
6769
6770 return E_TSP_OK;
6771 }
6772
MDrv_TSP_PVR_Eng_GetWriteAddr(MS_U32 u32Eng,MS_PHY * pu32WriteAddr)6773 TSP_Result MDrv_TSP_PVR_Eng_GetWriteAddr(MS_U32 u32Eng, MS_PHY *pu32WriteAddr)
6774 {
6775 if (E_TSP_PVR_PVRENG_END > u32Eng) // PVR Eng
6776 {
6777 _MDrv_PVR_Eng_GetWriteAddr(u32Eng, pu32WriteAddr);
6778 }
6779 else
6780 {
6781 TSP_DBG(E_TSP_DBG_MUST, "[ERROR][%s][%d]Incorrect Engine type!\n",__FUNCTION__,__LINE__);
6782 }
6783
6784 return E_TSP_OK;
6785 }
6786
MDrv_TSP_PVR_Eng_Notify(MS_U32 u32Eng,TSP_Event eEvents,P_TSP_Callback pfCallback)6787 TSP_Result MDrv_TSP_PVR_Eng_Notify(MS_U32 u32Eng, TSP_Event eEvents, P_TSP_Callback pfCallback)
6788 {
6789 if (E_TSP_PVR_PVRENG_END > u32Eng) // PVR Eng
6790 {
6791 _MDrv_PVR_Eng_Notify(u32Eng, eEvents, pfCallback);
6792 }
6793 else
6794 {
6795 TSP_DBG(E_TSP_DBG_MUST, "[ERROR][%s][%d]Incorrect Engine type!\n",__FUNCTION__,__LINE__);
6796 }
6797
6798 return E_TSP_OK;
6799 }
6800
MDrv_TSP_PVR_Eng_SetPacketMode(MS_U32 u32Eng,MS_BOOL bSet)6801 TSP_Result MDrv_TSP_PVR_Eng_SetPacketMode(MS_U32 u32Eng, MS_BOOL bSet)
6802 {
6803 if (E_TSP_PVR_PVRENG_END > u32Eng) // PVR Eng
6804 {
6805 _MDrv_PVR_Eng_SetPacketMode(u32Eng, bSet);
6806 }
6807 else
6808 {
6809 TSP_DBG(E_TSP_DBG_MUST, "[ERROR][%s][%d]Incorrect Engine type!\n",__FUNCTION__,__LINE__);
6810 }
6811
6812 return E_TSP_OK;
6813 }
6814
MDrv_TSP_PVR_Eng_TimeStampSetRecordStamp(MS_U32 u32Eng,MS_U32 u32Stamp)6815 TSP_Result MDrv_TSP_PVR_Eng_TimeStampSetRecordStamp(MS_U32 u32Eng, MS_U32 u32Stamp)
6816 {
6817 if (E_TSP_PVR_PVRENG_END > u32Eng) // PVR Eng
6818 {
6819 _MDrv_PVR_Eng_TimeStampSetRecordStamp(u32Eng, u32Stamp);
6820 }
6821 else
6822 {
6823 TSP_DBG(E_TSP_DBG_MUST, "[ERROR][%s][%d]Incorrect Engine type!\n",__FUNCTION__,__LINE__);
6824 }
6825
6826 return E_TSP_OK;
6827 }
6828
MDrv_TSP_PVR_Eng_TimeStampGetRecordStamp(MS_U32 u32Eng,MS_U32 * u32Stamp)6829 TSP_Result MDrv_TSP_PVR_Eng_TimeStampGetRecordStamp(MS_U32 u32Eng, MS_U32* u32Stamp)
6830 {
6831 if (E_TSP_PVR_PVRENG_END > u32Eng) // PVR Eng
6832 {
6833 _MDrv_PVR_Eng_TimeStampGetRecordStamp(u32Eng, u32Stamp);
6834 }
6835 else
6836 {
6837 TSP_DBG(E_TSP_DBG_MUST, "[ERROR][%s][%d]Incorrect Engine type!\n",__FUNCTION__,__LINE__);
6838 }
6839
6840 return E_TSP_OK;
6841 }
6842
MDrv_TSP_PVR_Eng_SetCaMode(MS_U32 u32EngId,MS_U16 u16CaMode,MS_BOOL bSpsEnable)6843 TSP_Result MDrv_TSP_PVR_Eng_SetCaMode(MS_U32 u32EngId, MS_U16 u16CaMode, MS_BOOL bSpsEnable)
6844 {
6845 TSP_ENTRY();
6846
6847 if(HAL_TSP_CAPVR_SPSEnable(u32EngId, u16CaMode, bSpsEnable))
6848 {
6849 TSP_RETURN(E_TSP_OK);
6850 }
6851 else
6852 {
6853 TSP_RETURN(E_TSP_OK);
6854 }
6855 }
6856
MDrv_TSP_PVR_Eng_MOBF_Enable(MS_U32 u32Eng,MS_BOOL bEnable,MS_U32 u32Key)6857 TSP_Result MDrv_TSP_PVR_Eng_MOBF_Enable(MS_U32 u32Eng, MS_BOOL bEnable, MS_U32 u32Key)
6858 {
6859 TSP_ENTRY();
6860
6861 if (E_TSP_PVR_PVRENG_END > u32Eng) // PVR Eng
6862 {
6863 HAL_PVR_MOBF_Enable(u32Eng, bEnable, u32Key);
6864 }
6865 else
6866 {
6867 TSP_DBG(E_TSP_DBG_MUST, "[ERROR][%s][%d]Incorrect Engine type!\n",__FUNCTION__,__LINE__);
6868 }
6869
6870 TSP_RETURN(E_TSP_OK);
6871 }
6872
_MDrv_FltAllocForRec(MS_U32 u32Eng,TSP_SRC_SEQ eEngSrc,MS_U32 * pu32FltId)6873 static TSP_Result _MDrv_FltAllocForRec(MS_U32 u32Eng, TSP_SRC_SEQ eEngSrc, MS_U32 *pu32FltId)
6874 {
6875 TSP_PIDFLT_SRC ePidFltSrc = HAL_TSP_PktDmx2FltSrc_Mapping(eEngSrc);
6876 TSP_FltType eTspFltSrcType = E_TSP_FLT_SRC_LIVE0;
6877 TSP_FltType eTspFltDstType = E_TSP_FLT_FIFO_PVR0;
6878
6879 switch (ePidFltSrc)
6880 {
6881 case E_TSP_PIDFLT_LIVE0:
6882 eTspFltSrcType = E_TSP_FLT_SRC_LIVE0;
6883 break;
6884 case E_TSP_PIDFLT_LIVE1:
6885 eTspFltSrcType = E_TSP_FLT_SRC_LIVE1;
6886 break;
6887 case E_TSP_PIDFLT_LIVE2:
6888 eTspFltSrcType = E_TSP_FLT_SRC_LIVE2;
6889 break;
6890 case E_TSP_PIDFLT_LIVE3:
6891 eTspFltSrcType = E_TSP_FLT_SRC_LIVE3;
6892 break;
6893 case E_TSP_PIDFLT_FILE0:
6894 eTspFltSrcType = E_TSP_FLT_SRC_FILE0;
6895 break;
6896 case E_TSP_PIDFLT_FILE1:
6897 eTspFltSrcType = E_TSP_FLT_SRC_FILE1;
6898 break;
6899 case E_TSP_PIDFLT_FILE2:
6900 eTspFltSrcType = E_TSP_FLT_SRC_FILE2;
6901 break;
6902 case E_TSP_PIDFLT_FILE3:
6903 eTspFltSrcType = E_TSP_FLT_SRC_FILE3;
6904 break;
6905 case E_TSP_PIDFLT_LIVE4:
6906 case E_TSP_PIDFLT_FILE4:
6907 eTspFltSrcType = E_TSP_FLT_SRC_LIVE4;
6908 break;
6909 case E_TSP_PIDFLT_LIVE5:
6910 case E_TSP_PIDFLT_FILE5:
6911 eTspFltSrcType = E_TSP_FLT_SRC_LIVE5;
6912 break;
6913 case E_TSP_PIDFLT_LIVE6:
6914 case E_TSP_PIDFLT_FILE6:
6915 eTspFltSrcType = E_TSP_FLT_SRC_LIVE6;
6916 break;
6917 default:
6918 break;
6919 }
6920
6921 if(u32Eng < TSP_PVRENG_NUM)
6922 {
6923 eTspFltDstType = E_TSP_FLT_FIFO_PVR0 + u32Eng;
6924 }
6925
6926 if (E_TSP_OK != MDrv_TSP_FLT_Alloc(0, (eTspFltSrcType | eTspFltDstType), pu32FltId))
6927 {
6928 return E_TSP_FAIL;
6929 }
6930
6931 return E_TSP_OK;
6932 }
6933
_MDrv_FltFreeForRec(MS_U32 u32FltId)6934 static TSP_Result _MDrv_FltFreeForRec(MS_U32 u32FltId)
6935 {
6936 TSP_PVR_ENTRY();
6937
6938 //@NOTE shouldn't we modify sw flt status here? No, since it's maitain in fle_enable and flt_free
6939 MDrv_TSP_FLT_Enable( u32FltId, FALSE);
6940 MDrv_TSP_FLT_SetPID( u32FltId, TSP_PID_NULL);
6941 MDrv_TSP_FLT_Free( u32FltId);
6942
6943 TSP_PVR_RETURN(E_TSP_OK);
6944 }
6945
_MDrv_FltSetPIDForRec(MS_U32 u32FltId,MS_U32 u32PID)6946 static TSP_Result _MDrv_FltSetPIDForRec(MS_U32 u32FltId, MS_U32 u32PID)
6947 {
6948 TSP_PVR_ENTRY();
6949 MDrv_TSP_FLT_SetPID( u32FltId, u32PID);
6950 TSP_PVR_RETURN(E_TSP_OK);
6951 }
6952
_MDrv_FltGetPIDForRec(MS_U32 u32FltId,MS_U32 * pu32PID)6953 static TSP_Result _MDrv_FltGetPIDForRec(MS_U32 u32FltId, MS_U32* pu32PID)
6954 {
6955 TSP_PVR_ENTRY();
6956 MDrv_TSP_FLT_GetPID(u32FltId, pu32PID);
6957 TSP_PVR_RETURN(E_TSP_OK);
6958 }
6959
_MDrv_FltEnableForRec(MS_U32 u32FltId,MS_BOOL bEnable)6960 static TSP_Result _MDrv_FltEnableForRec(MS_U32 u32FltId, MS_BOOL bEnable)
6961 {
6962 TSP_PVR_ENTRY();
6963 MDrv_TSP_FLT_Enable( u32FltId, bEnable);
6964 TSP_PVR_RETURN(E_TSP_OK);
6965 }
6966
_MDrv_PVR_Eng_SetBuffer(MS_U32 u32Eng,MS_PHYADDR u32Start0,MS_PHYADDR u32Start1,MS_U32 u32Size0,MS_U32 u32Size1)6967 static TSP_Result _MDrv_PVR_Eng_SetBuffer(MS_U32 u32Eng, MS_PHYADDR u32Start0, MS_PHYADDR u32Start1, MS_U32 u32Size0, MS_U32 u32Size1)
6968 {
6969 TSP_PVR_ENTRY();
6970 HAL_PVR_SetStr2Miu_StartAddr(u32Eng, u32Start0, u32Start1);
6971 HAL_PVR_SetStr2Miu_MidAddr(u32Eng, u32Start0 + u32Size0 , u32Start1 + u32Size1 );
6972 HAL_PVR_SetStr2Miu_EndAddr(u32Eng, u32Start0 + u32Size0 , u32Start1 + u32Size1 );
6973 TSP_PVR_RETURN(E_TSP_OK);
6974 }
6975
_MDrv_PVR_Eng_Start(MS_U32 u32Eng,TSP_DRV_PVR_RecMode eRecMode,MS_BOOL bStart)6976 static TSP_Result _MDrv_PVR_Eng_Start(MS_U32 u32Eng, TSP_DRV_PVR_RecMode eRecMode, MS_BOOL bStart)
6977 {
6978 TSP_PVR_ENTRY();
6979
6980 if (!bStart)
6981 {
6982 HAL_PVR_Stop(u32Eng);
6983 }
6984 else
6985 {
6986 switch (eRecMode)
6987 {
6988 case E_TSP_DRV_PVR_RecMode_PID:
6989 {
6990 HAL_PVR_RecPid(u32Eng , TRUE);
6991 break;
6992 }
6993 case E_TSP_DRV_PVR_RecMode_ALL:
6994 {
6995 HAL_PVR_RecPid(u32Eng , FALSE);
6996 break;
6997 }
6998 default :
6999 break;
7000 }
7001 HAL_PVR_Start(u32Eng);
7002 }
7003
7004 TSP_PVR_RETURN(E_TSP_OK);
7005 }
7006
_MDrv_PVR_Eng_Pause(MS_U32 u32Eng,MS_BOOL bPause)7007 static TSP_Result _MDrv_PVR_Eng_Pause(MS_U32 u32Eng, MS_BOOL bPause)
7008 {
7009 TSP_PVR_ENTRY();
7010 HAL_PVR_Pause(u32Eng, bPause);
7011 TSP_PVR_RETURN(E_TSP_OK);
7012 }
7013
_MDrv_PVR_Eng_GetWriteAddr(MS_U32 u32Eng,MS_PHY * pu32WriteAddr)7014 static TSP_Result _MDrv_PVR_Eng_GetWriteAddr(MS_U32 u32Eng, MS_PHY *pu32WriteAddr)
7015 {
7016 TSP_PVR_ENTRY();
7017 *pu32WriteAddr = HAL_PVR_GetWritePtr(u32Eng);
7018 TSP_PVR_RETURN(E_TSP_OK);
7019 }
7020
_MDrv_PVR_Eng_Notify(MS_U32 u32Eng,TSP_Event eEvents,P_TSP_Callback pfCallback)7021 static TSP_Result _MDrv_PVR_Eng_Notify(MS_U32 u32Eng, TSP_Event eEvents, P_TSP_Callback pfCallback)
7022 {
7023 #if 0
7024 if(pfCallback)
7025 {
7026 _TSP_SetPvrNotifyId(u32Eng);
7027 }
7028 else
7029 {
7030 _TSP_RemovePvrNotifyId;
7031 }
7032 #endif
7033
7034 return E_TSP_FAIL_NOT_SUPPORTED;
7035 }
7036
_MDrv_PVR_Eng_SetPacketMode(MS_U32 u32Eng,MS_BOOL bSet)7037 static TSP_Result _MDrv_PVR_Eng_SetPacketMode(MS_U32 u32Eng, MS_BOOL bSet)
7038 {
7039 TSP_PVR_ENTRY();
7040 HAL_PVR_SetStrPacketMode(u32Eng, bSet);
7041 TSP_PVR_RETURN(E_TSP_OK);
7042 }
7043
_MDrv_PVR_Eng_TimeStampSetRecordStamp(MS_U32 u32Eng,MS_U32 u32Stamp)7044 static TSP_Result _MDrv_PVR_Eng_TimeStampSetRecordStamp(MS_U32 u32Eng, MS_U32 u32Stamp)
7045 {
7046 TSP_PVR_ENTRY();
7047 HAL_PVR_SetPVRTimeStamp(u32Eng, u32Stamp);
7048 TSP_PVR_RETURN(E_TSP_OK);
7049 }
7050
_MDrv_PVR_Eng_TimeStampGetRecordStamp(MS_U32 u32Eng,MS_U32 * u32Stamp)7051 static TSP_Result _MDrv_PVR_Eng_TimeStampGetRecordStamp(MS_U32 u32Eng, MS_U32* u32Stamp)
7052 {
7053 TSP_PVR_ENTRY();
7054 *u32Stamp = HAL_PVR_GetPVRTimeStamp(u32Eng);
7055 TSP_PVR_RETURN(E_TSP_OK);
7056 }
7057
MDrv_TSP_PVR_TimeStampSetPlaybackStamp(MS_U32 u32Stamp)7058 TSP_Result MDrv_TSP_PVR_TimeStampSetPlaybackStamp(MS_U32 u32Stamp)
7059 {
7060 TSP_PVR_ENTRY();
7061 FILEENG_SEQ eFileEng = HAL_TSP_GetDefaultFileinEng();
7062 HAL_TSP_Filein_SetTimeStamp(eFileEng, u32Stamp);
7063 TSP_PVR_RETURN(E_TSP_OK);
7064 }
7065
MDrv_TSP_PVR_TimeStampGetPlaybackStamp(MS_U32 * u32Stamp)7066 TSP_Result MDrv_TSP_PVR_TimeStampGetPlaybackStamp(MS_U32* u32Stamp)
7067 {
7068 TSP_PVR_ENTRY();
7069 FILEENG_SEQ eFileEng = HAL_TSP_GetDefaultFileinEng();
7070 *u32Stamp = HAL_TSP_Filein_GetTimeStamp(eFileEng);
7071 TSP_PVR_RETURN(E_TSP_OK);
7072 }
7073
MDrv_TSP_PVR_TimeStamp(MS_BOOL bEnable)7074 TSP_Result MDrv_TSP_PVR_TimeStamp(MS_BOOL bEnable)
7075 {
7076 TSP_PVR_ENTRY();
7077 HAL_PVR_SetStrPacketMode(0,bEnable);
7078 TSP_PVR_RETURN(E_TSP_OK);
7079 }
7080
7081 //-------------------------------------------------------------------------------------------------
7082 /// Enable remove duplicate A/V packets
7083 /// @param bEnable \b IN: Enable or Disable
7084 /// @return TSP_Result
7085 /// @note
7086 //-------------------------------------------------------------------------------------------------
MDrv_TSP_RemoveDupAVPkt(MS_BOOL bEnable)7087 TSP_Result MDrv_TSP_RemoveDupAVPkt(MS_BOOL bEnable)
7088 {
7089 TSP_ENTRY();
7090 HAL_TSP_PktDmx_RmDupAVPkt(bEnable);
7091 TSP_RETURN(E_TSP_OK);
7092 }
7093
7094 //-------------------------------------------------------------------------------------------------
7095 /// Enable or Disable to remove audio,or vedio error packets.
7096 /// @param bEnable \b IN: Enable or Disable
7097 /// @return TSP_Result
7098 /// @note
7099 //-------------------------------------------------------------------------------------------------
MDrv_TSP_TEI_RemoveErrorPkt(TSP_DRV_TEI_RmPktType eDrvPktType,MS_BOOL bEnable)7100 TSP_Result MDrv_TSP_TEI_RemoveErrorPkt(TSP_DRV_TEI_RmPktType eDrvPktType, MS_BOOL bEnable)
7101 {
7102 TSP_ENTRY();
7103
7104 TSP_HAL_TEI_RmPktType eHalPktType = E_TSP_HAL_TEI_REMOVE_AUDIO_PKT;
7105
7106 switch ( eDrvPktType )
7107 {
7108 case E_TSP_DRV_TEI_REMOVE_AUDIO_PKT:
7109 eHalPktType = E_TSP_HAL_TEI_REMOVE_AUDIO_PKT;
7110 break;
7111 case E_TSP_DRV_TEI_REMOVE_VIDEO_PKT:
7112 eHalPktType = E_TSP_HAL_TEI_REMOVE_VIDEO_PKT;
7113 break;
7114 default:
7115 TSP_DBG(E_TSP_DBG_WARNING, "[%04d] Unsupport PktType = %u\n", __LINE__, (MS_U32) eDrvPktType);
7116 TSP_RETURN(E_TSP_FAIL);
7117 }
7118
7119 HAL_TSP_TEI_RemoveErrorPkt(eHalPktType, bEnable);
7120
7121 TSP_RETURN(E_TSP_OK);
7122 }
7123
7124
7125 #ifdef STC64_SUPPORT
7126 //-------------------------------------------------------------------------------------------------
7127 /// Enable or Disable STC64 bit mode. Defalut is STC33 mode.
7128 /// @param bEnable \b IN: STC64 system time mode enable
7129 /// @return TSP_Result
7130 /// @note
7131 //-------------------------------------------------------------------------------------------------
MDrv_TSP_STC64_Mode_Enable(MS_BOOL bEnable)7132 TSP_Result MDrv_TSP_STC64_Mode_Enable(MS_BOOL bEnable)
7133 {
7134 TSP_ENTRY();
7135 // HAL_TSP_STC64_Mode_En(bEnable); // @F_TODO not implement yet do we have to enable this in kaiser?
7136 TSP_RETURN(E_TSP_OK);
7137 }
7138
7139 //-------------------------------------------------------------------------------------------------
7140 //[Reserved]
7141 // Memory to TSP stream command : Update Stream STC64
7142 // @param u32EngId \b IN: index of TSP engine [ 0 .. (@ref DRVTSP_ENGINE_NUM-1) ]
7143 // @param u32STC_32 \b IN: STC[63:32] for next input stream
7144 // @param u32STC \b IN: STC[31:0] for next input stream
7145 // @return TSP_Result
7146 // @note M2T Command Size: 3
7147 //-------------------------------------------------------------------------------------------------
MDrv_TSP_SetSTC64(MS_U32 u32EngId,MS_U32 u32STC_32,MS_U32 u32STC)7148 TSP_Result MDrv_TSP_SetSTC64(MS_U32 u32EngId, MS_U32 u32STC_32, MS_U32 u32STC)
7149 {
7150 TSP_ENTRY();
7151
7152 TSP_RES_ALLOC_STC_CHECK(u32EngId);
7153 HAL_TSP_STC64_Set(u32EngId, u32STC_32, u32STC);
7154
7155 TSP_RETURN(E_TSP_OK);
7156 }
7157
7158 //-------------------------------------------------------------------------------------------------
7159 /// Set STC control
7160 /// @param u8Eng \b IN: STC Engine ID
7161 /// @param u8Opt \b IN: STC update control options
7162 /// 0x00 -> Update STC by TSP FW (driver)
7163 /// 0x01 -> Update STC by HK (Set by AP)
7164 /// 0x02 -> Update STC Once by driver when PCR reset
7165 /// @note
7166 //-------------------------------------------------------------------------------------------------
MDrv_TSP_STC_UpdateCtrl(MS_U8 u8Eng,MS_U8 u8Mode)7167 TSP_Result MDrv_TSP_STC_UpdateCtrl(MS_U8 u8Eng, MS_U8 u8Mode)
7168 {
7169 TSP_ENTRY();
7170
7171 TSP_RES_ALLOC_STC_CHECK(u8Eng);
7172 if (u8Mode ==0x00)
7173 {
7174 _ptsp_res->_u32_StcUpdateCtrl[u8Eng].bEnable = TRUE;
7175 _ptsp_res->_u32_StcUpdateCtrl[u8Eng].bUpdateOnce = FALSE;
7176 TSP_RETURN(E_TSP_OK);
7177 }
7178 else if( u8Mode ==0x01)
7179 {
7180 _ptsp_res->_u32_StcUpdateCtrl[u8Eng].bEnable = FALSE;
7181 _ptsp_res->_u32_StcUpdateCtrl[u8Eng].bUpdateOnce = FALSE;
7182 TSP_RETURN(E_TSP_OK);
7183 }
7184 else if( u8Mode ==0x02)
7185 {
7186 _ptsp_res->_u32_StcUpdateCtrl[u8Eng].bEnable = TRUE;
7187 _ptsp_res->_u32_StcUpdateCtrl[u8Eng].bUpdateOnce = TRUE;
7188 TSP_RETURN(E_TSP_OK);
7189 }
7190
7191 TSP_RETURN(E_TSP_FAIL);
7192 }
7193
MDrv_TSP_SetSTCOffset(MS_U32 u32EngId,MS_U32 u32Offset,MS_BOOL bAdd)7194 TSP_Result MDrv_TSP_SetSTCOffset(MS_U32 u32EngId, MS_U32 u32Offset, MS_BOOL bAdd)
7195 {
7196 TSP_ENTRY();
7197
7198 TSP_RES_ALLOC_STC_CHECK(u32EngId);
7199 _ptsp_res->_u32_StcOffset[u32EngId].u32StcOffset = u32Offset;
7200 _ptsp_res->_u32_StcOffset[u32EngId].bAdd= bAdd;
7201
7202 TSP_RETURN (E_TSP_OK);
7203 }
7204
7205 //-------------------------------------------------------------------------------------------------
7206 /// Get current system time clock (STC64) of TSP
7207 /// @param u32EngId \b IN: index of TSP engine [ 0 .. (@ref DRVTSP_ENGINE_NUM-1) ]
7208 /// @param pu32STC_32 \b OUT: pointer of STC[32:63] return
7209 /// @param pu32STC \b OUT: pointer of STC[31:0] return
7210 /// @return TSP_Result
7211 //-------------------------------------------------------------------------------------------------
MDrv_TSP_GetSTC64(MS_U32 u32EngId,MS_U32 * pu32STC_32,MS_U32 * pu32STC)7212 TSP_Result MDrv_TSP_GetSTC64(MS_U32 u32EngId, MS_U32 *pu32STC_32, MS_U32 *pu32STC)
7213 {
7214 TSP_ENTRY();
7215 TSP_RES_ALLOC_STC_CHECK(u32EngId);
7216
7217 HAL_TSP_STC64_Get(u32EngId, pu32STC_32, pu32STC);
7218
7219 TSP_RETURN(E_TSP_OK);
7220 }
7221
7222 #endif
7223
7224 //-------------------------------------------------------------------------------------------------
7225 /// STC Clock Rate Adjust (27MHz clock)
7226 /// @param u32EngId \b IN: STC engine ID
7227 /// @param bUpClk \b IN: If TRUE, Clk will be faster, and if FALSE, Clk will be slower
7228 /// @param u32Percentage \b IN: The percentage of STC clock ratio
7229 /// @return TSP_Result
7230 /// @note
7231 /// StcClk = (InClk * (2^27) /Stc_CW) * 3.2
7232 /// Stc_CW = Stc_CW_Def / P
7233 //-------------------------------------------------------------------------------------------------
MDrv_TSP_STCClk_Adjust(MS_U32 u32EngId,MS_BOOL bUpClk,MS_U32 u32Percentage)7234 TSP_Result MDrv_TSP_STCClk_Adjust(MS_U32 u32EngId, MS_BOOL bUpClk, MS_U32 u32Percentage)
7235 {
7236 if(u32Percentage == 0)
7237 {
7238 return E_TSP_FAIL;
7239 }
7240
7241 MS_U64 u64CW_New = 0;
7242
7243 TSP_ENTRY();
7244
7245 u64CW_New = (((MS_U64)STC_SYNTH_DEFAULT) & 0xFFFFFFFFUL) * (((MS_U64)_ptsp_res->_u32StcAdjustUnit) & 0xFFFFFFFFUL) / (((MS_U64)u32Percentage) & 0xFFFFFFFFUL);
7246
7247 //ULOGD("TSP", "[%s](%d, %d, %d) CW %d\n", __FUNCTION__, (unsigned int)u32EngId, (unsigned int)bUpClk, (unsigned int)u32Percentage, (unsigned int)u64CW_New);
7248 HAL_TSP_SetSTCSynth(u32EngId, (MS_U32)u64CW_New);
7249
7250 TSP_RETURN(E_TSP_OK);
7251 }
7252
7253
7254
_TSP_FLT_SrcSwitch(TSP_FltType SrcFlow,TSP_FltType TgtFlow)7255 TSP_Result _TSP_FLT_SrcSwitch(TSP_FltType SrcFlow ,TSP_FltType TgtFlow)
7256 {
7257 MS_U32 i ;//,dummy;
7258
7259 // Define check policy for filters //
7260 #define CHECK_FILTER_PROPERTY(_idx_) ((_ptsp_res->_tspInfo.FltType[_idx_] & SrcFlow)\
7261 && (_ptsp_res->_tspInfo.FltState[_idx_] & E_TSP_FLT_STATE_ALLOC) \
7262 && (_ptsp_res->_tspInfo.FltState[_idx_] != E_TSP_FLT_STATE_NA) \
7263 && (FALSE ==(_ptsp_res->_tspInfo.FltType[_idx_] & E_TSP_FLT_FIFO_MASK ))\
7264 && (E_TSP_FLT_USER_PCR != (_ptsp_res->_tspInfo.FltType[_idx_]& E_TSP_FLT_USER_MASK )))
7265
7266
7267 //ULOGD("TSP", "Src Flow = %08lX -- TgtFlow = %08lx \n",SrcFlow,TgtFlow);
7268 #if 0 // @FIXME seeems we dont need this
7269 if (TgtFlow & E_TSP_FLT_SRC_FILE )
7270 {
7271 TSP_OS_Print("[%s] Target Flow Error , Flow = %08lx \n",__FUNCTION__,TgtFlow);
7272 return E_TSP_FAIL;
7273 }
7274 #endif
7275
7276 // Stop all target source Filter
7277 for ( i = 0 ; i < _tspFltIdMap.u32PidFltId_End ; i ++)
7278 {
7279 if (CHECK_FILTER_PROPERTY(i))
7280 {
7281 TSP_LOCK();
7282 HAL_TSP_PidFlt_SetFltOut(i, TSP_PIDFLT_OUT_NONE);
7283 TSP_UNLOCK();
7284 }
7285 }
7286
7287 // wait for all Task solved
7288 MsOS_DelayTask(100);
7289
7290
7291 for ( i = 0 ; i < _tspFltIdMap.u32PidFltId_End ; i ++)
7292 {
7293 if (CHECK_FILTER_PROPERTY(i))
7294 {
7295
7296 TSP_LOCK();
7297 // Setting new Filter input source.
7298
7299 // @TODO not review and implement yet: check everthing
7300 #if 0
7301 if (TgtFlow & E_TSP_FLT_SRC_LIVE0)
7302 {
7303 HAL_TSP_PidFlt_SetFltIn(i, TSP_PIDFLT_TSIF0);
7304 }
7305 else if (TgtFlow & E_TSP_FLT_SRC_TSIF1)
7306 {
7307 HAL_TSP_PidFlt_SetFltIn(i, TSP_PIDFLT_TSIF1);
7308 }
7309 else if (TgtFlow & E_TSP_FLT_SRC_TSIF2)
7310 {
7311 HAL_TSP_PidFlt_SetFltIn(i, TSP_PIDFLT_TSIF2);
7312 }
7313 else
7314 {
7315 TSP_OS_Print("[%s][%d]Error in target source = %lx \n",__FUNCTION__,__LINE__,TgtFlow);
7316 }
7317 #endif
7318
7319 _ptsp_res->_tspInfo.FltType[i] = (_ptsp_res->_tspInfo.FltType[i] & ~E_TSP_FLT_SRC_MASK) | TgtFlow ;
7320 TSP_UNLOCK();
7321
7322 // Restart Running Filter
7323 if (_ptsp_res->_tspInfo.FltState[i] & E_TSP_FLT_STATE_ENABLE)
7324 {
7325 MDrv_TSP_FLT_Enable( i , TRUE );
7326 }
7327 }
7328 }
7329
7330 TSP_LOCK();
7331 if (SrcFlow == _ptsp_res->_Current_Live)
7332 {
7333 _ptsp_res->_Current_Live = TgtFlow & E_TSP_FLT_SRC_MASK;
7334 }
7335 TSP_UNLOCK();
7336
7337 return (E_TSP_OK);
7338
7339 #undef CHECK_FILTER_PROPERTY
7340
7341 }
7342
MDrv_TSP_FLT_LiveSrcSwitch(TSP_FltType TgtFlow)7343 TSP_Result MDrv_TSP_FLT_LiveSrcSwitch(TSP_FltType TgtFlow)
7344 {
7345 //TSP_OS_Print("[%s][%d]\n",__FUNCTION__,__LINE__);
7346
7347 TSP_Result ret = E_TSP_FAIL;
7348
7349 if ((TgtFlow&E_TSP_FLT_SRC_MASK ) == _ptsp_res->_Current_Live)
7350 {
7351 return E_TSP_FAIL;
7352 }
7353
7354 ret = _TSP_FLT_SrcSwitch(_ptsp_res->_Current_Live, TgtFlow);
7355
7356 return ret;
7357 }
7358
7359
MDrv_TSP_FLT_ChangeSource(MS_U32 u32FltId,TSP_FltType eTSPFltTypeSrc)7360 TSP_Result MDrv_TSP_FLT_ChangeSource(MS_U32 u32FltId, TSP_FltType eTSPFltTypeSrc)
7361 {
7362 TSP_CHECK(_tspFltIdMap.u32PidFltIdAll > u32FltId, "[%04d] Invalid u32FltId %d\n", __LINE__, (unsigned int)u32FltId);
7363
7364 // HAL_TSP_GetCaps(E_TSP_HAL_CAP_TYPE_RECFLT_IDX, &u32RecFltIdx);
7365 if(u32FltId == _tspFltIdMap.u32RecFltIdx)
7366 return E_TSP_OK;
7367
7368 TSP_ENTRY();
7369
7370 if ((_ptsp_res->_tspInfo.FltType[u32FltId]& E_TSP_FLT_USER_MASK)== E_TSP_FLT_USER_PCR)
7371 {
7372 //stop hw pcr
7373 if ((u32FltId >= TSP_PCRFLT_GET_ID(0)) && (u32FltId <= HAL_TSP_PCRFLT_GET_ID(TSP_PCRFLT_NUM - 1)))
7374 {
7375 HAL_TSP_PcrFlt_Enable(u32FltId - _tspFltIdMap.u32PcrFltId_Start, FALSE);
7376 }
7377 else
7378 {
7379 TSP_DBG(E_TSP_DBG_MUST, "[%s][%d] Incorrect PCR filter ID !!\n",__FUNCTION__,__LINE__);
7380 }
7381 }
7382 else
7383 {
7384 //stop pid flts
7385 HAL_TSP_PidFlt_SetFltOut(u32FltId, TSP_PIDFLT_OUT_NONE); // stop filter
7386 }
7387
7388 // wait for all Task solved
7389 MsOS_DelayTask(20);
7390
7391 MS_U32 u32FltSrc = E_TSP_FLT_SRC_MASK & eTSPFltTypeSrc;
7392 TSP_PIDFLT_SRC eTspPidSrc = _TSP_DrvHal_FltSrcMapping(u32FltSrc);
7393
7394 if ((_ptsp_res->_tspInfo.FltType[u32FltId]& E_TSP_FLT_USER_MASK)== E_TSP_FLT_USER_PCR)
7395 {
7396 //change hw pcr src
7397 if ((u32FltId >= HAL_TSP_PCRFLT_GET_ID(0)) && (u32FltId <= HAL_TSP_PCRFLT_GET_ID(TSP_PCRFLT_NUM - 1)))
7398 {
7399 TSP_PCR_SRC ePcrSrc = HAL_TSP_FltSrc2PCRSrc_Mapping(eTspPidSrc);
7400
7401 TSP_RES_ALLOC_TSPPATH_CHECK(ePcrSrc);
7402
7403 HAL_TSP_PcrFlt_SetSrc(u32FltId - _tspFltIdMap.u32PcrFltId_Start, ePcrSrc);
7404 }
7405 else
7406 {
7407 TSP_DBG(E_TSP_DBG_MUST, "[%s][%d] Incorrect PCR filter ID !!\n",__FUNCTION__,__LINE__);
7408 }
7409 }
7410 else
7411 {
7412 //change pid flt src
7413 MS_U32 u32PktDmx = HAL_TSP_FltSrc2PktDmx_Mapping(eTspPidSrc);
7414
7415 TSP_RES_ALLOC_TSPPATH_CHECK(u32PktDmx);
7416
7417 HAL_TSP_PidFlt_SetFltIn(u32FltId,u32PktDmx);
7418 }
7419
7420 _ptsp_res->_tspInfo.FltType[u32FltId] = (_ptsp_res->_tspInfo.FltType[u32FltId] & ~E_TSP_FLT_SRC_MASK) | eTSPFltTypeSrc ;
7421
7422 if (_ptsp_res->_tspInfo.FltState[u32FltId] & E_TSP_FLT_STATE_ENABLE)
7423 {
7424 _MDrv_TSP_FLT_Enable( u32FltId, TRUE );
7425 }
7426
7427 TSP_RETURN(E_TSP_OK);
7428 }
7429
MDrv_TSP_PARL_BitOrderSwap(MS_U16 u16TSIF,MS_BOOL bInvert)7430 TSP_Result MDrv_TSP_PARL_BitOrderSwap(MS_U16 u16TSIF, MS_BOOL bInvert)
7431 {
7432 TSP_RES_ALLOC_TSPPATH_CHECK(u16TSIF);
7433
7434 TSP_ENTRY();
7435 HAL_TSP_TSIF_BitSwap(u16TSIF, bInvert); //@F_TODO check if this is the same with `HAL_TSP_SetDataSwap'
7436 TSP_RETURN(E_TSP_OK);
7437 }
7438
MDrv_TSP_FQ_FltNullPkt(MS_U32 u32FQEng,MS_BOOL bFltNull)7439 TSP_Result MDrv_TSP_FQ_FltNullPkt(MS_U32 u32FQEng, MS_BOOL bFltNull)
7440 {
7441 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
7442
7443 MS_U32 u32MapingFQEng = HAL_TSP_Tsif2Fq_Mapping(u32FQEng);
7444 TSP_FQ_NUM_CHECK_RET(u32MapingFQEng);
7445
7446 TSP_Result ret;
7447
7448 TSP_ENTRY();
7449
7450 ret = HAL_TSP_FQ_FLT_NULL_PKT(u32MapingFQEng, bFltNull);
7451
7452 if(ret==FALSE)
7453 {
7454 TSP_RETURN(E_TSP_FAIL_NOT_SUPPORTED);
7455 }
7456 else
7457 {
7458 TSP_RETURN(E_TSP_OK);
7459 }
7460 }
7461
MDrv_TSP_FQ_SetMuxSwitch(MS_U32 u32FQEng,DrvFQ_SrcIf eTsSrc)7462 TSP_Result MDrv_TSP_FQ_SetMuxSwitch(MS_U32 u32FQEng, DrvFQ_SrcIf eTsSrc)
7463 {
7464 TSP_DBG(E_TSP_DBG_TRACK, "%s\n", __FUNCTION__);
7465 MS_U32 u32FQSrc = 0;
7466
7467 TSP_FQ_NUM_CHECK_RET(u32FQEng);
7468
7469 TSP_ENTRY();
7470
7471 switch(eTsSrc)
7472 {
7473 case E_DRVFQ_SRC_TSIF0:
7474 u32FQSrc = 0;
7475 break;
7476 case E_DRVFQ_SRC_TSIF1:
7477 u32FQSrc = 1;
7478 break;
7479 case E_DRVFQ_SRC_TSIF2:
7480 u32FQSrc = 2;
7481 break;
7482 case E_DRVFQ_SRC_TSIF3:
7483 u32FQSrc = 3;
7484 break;
7485 case E_DRVFQ_SRC_TSIFFI:
7486 u32FQSrc = 7;
7487 break;
7488 case E_DRVFQ_SRC_DEFAULT:
7489 u32FQSrc = HAL_TSP_Tsif2Fq_Mapping(u32FQEng);
7490 break;
7491 default:
7492 TSP_RETURN(E_TSP_FAIL_PARAMETER);
7493 }
7494
7495 if(!HAL_TSP_FQ_SetMuxSwitch(u32FQEng,u32FQSrc))
7496 {
7497 TSP_RETURN(E_TSP_FAIL);
7498 }
7499 else
7500 {
7501 TSP_RETURN(E_TSP_OK);
7502 }
7503 }
7504
MDrv_TSP_FQ_GetMuxSwitch(MS_U32 u32FQEng,DrvFQ_SrcIf * peTsSrc)7505 TSP_Result MDrv_TSP_FQ_GetMuxSwitch(MS_U32 u32FQEng, DrvFQ_SrcIf* peTsSrc)
7506 {
7507 MS_U32 u32FQSrc = E_DRVFQ_SRC_DEFAULT;
7508
7509 TSP_FQ_NUM_CHECK_RET(u32FQEng);
7510
7511 TSP_ENTRY();
7512
7513 u32FQSrc = HAL_TSP_FQ_GetMuxSwitch(u32FQEng);
7514
7515 switch(u32FQSrc)
7516 {
7517 case 0:
7518 *peTsSrc = E_DRVFQ_SRC_TSIF0;
7519 break;
7520 case 1:
7521 *peTsSrc = E_DRVFQ_SRC_TSIF1;
7522 break;
7523 case 2:
7524 *peTsSrc = E_DRVFQ_SRC_TSIF2;
7525 break;
7526 case 3:
7527 *peTsSrc = E_DRVFQ_SRC_TSIF3;
7528 break;
7529 case 7:
7530 *peTsSrc = E_DRVFQ_SRC_TSIFFI;
7531 break;
7532 default:
7533 *peTsSrc = E_DRVFQ_SRC_DEFAULT;
7534 TSP_RETURN(E_TSP_FAIL);
7535 }
7536
7537 TSP_RETURN(E_TSP_OK);
7538 }
7539
7540
MDrv_TSP_CMD_Run(MS_U32 u32Cmd,MS_U32 u32Config0,MS_U32 u32Config1,void * pData)7541 TSP_Result MDrv_TSP_CMD_Run(MS_U32 u32Cmd, MS_U32 u32Config0, MS_U32 u32Config1 ,void *pData)
7542 {
7543
7544 if(u32Cmd == DRV_DMX_CMD_STC_ADJUST_UNIT)
7545 {
7546 _ptsp_res->_u32StcAdjustUnit = u32Config0;
7547 return (E_TSP_OK);
7548 }
7549
7550 if(HAL_TSP_CMD_Run(u32Cmd, u32Config0, u32Config1,pData))
7551 return (E_TSP_OK);
7552 else
7553 return (E_TSP_FAIL);
7554 }
7555
MDrv_TSP_DSCMB_Functionality(TSP_DSCMB_FuncCMD eCmd,MS_U32 u32Config0,MS_U32 u32Config1,void * pData)7556 TSP_Result MDrv_TSP_DSCMB_Functionality(TSP_DSCMB_FuncCMD eCmd, MS_U32 u32Config0, MS_U32 u32Config1 ,void *pData)
7557 {//this func should only be called by DSCMB driver to do DSCMB functionality, and maintained by DSCMB owner
7558 //the mutex _s32MutexId is utilized to avoid race condition between DSCMB & TSP accessing shared registers
7559 TSP_ENTRY();
7560
7561 switch(eCmd)
7562 {
7563 default:
7564 break;
7565 }
7566
7567 TSP_RETURN(E_TSP_OK);
7568 }
7569
7570
MDrv_TSP_Flt_GetScmbSts(TSP_FltType eFltType,MS_U32 u32FltGroupId,MS_U32 PidFltId,MS_U32 * pu32ScmbSts)7571 TSP_Result MDrv_TSP_Flt_GetScmbSts(TSP_FltType eFltType, MS_U32 u32FltGroupId, MS_U32 PidFltId, MS_U32 *pu32ScmbSts)
7572 {
7573 TSP_CHECK(_tspFltIdMap.u32PidFltId_End > PidFltId, "[%04d] Invalid u32FltId %d\n", __LINE__, (unsigned int)PidFltId);
7574
7575 TSP_ENTRY();
7576
7577 MS_U32 u32FltSrc = E_TSP_FLT_SRC_MASK & eFltType;
7578 TSP_PIDFLT_SRC eTspPidSrc = _TSP_DrvHal_FltSrcMapping(u32FltSrc);
7579 MS_U32 u32PktDmx = HAL_TSP_FltSrc2PktDmx_Mapping(eTspPidSrc);
7580
7581 TSP_RES_ALLOC_TSPPATH_CHECK(u32PktDmx);
7582
7583 if( HAL_DSCMB_GetStatus( u32PktDmx, u32FltGroupId, PidFltId, pu32ScmbSts) )
7584 {
7585 TSP_RETURN(E_TSP_OK);
7586 }
7587 else
7588 {
7589 TSP_RETURN(E_TSP_FAIL);
7590 }
7591 }
7592
MDrv_TSP_DropScmbPkt(TSP_FltType eFilterType,MS_BOOL bEnable)7593 TSP_Result MDrv_TSP_DropScmbPkt(TSP_FltType eFilterType, MS_BOOL bEnable)
7594 {
7595 TSP_DST_SEQ eDst = _TSP_DrvHal_FltType2DstMapping(eFilterType);
7596
7597 TSP_ENTRY();
7598
7599 HAL_TSP_FIFO_Skip_Scrmb(eDst, bEnable);
7600
7601 TSP_RETURN(E_TSP_OK);
7602 }
7603
MDrv_TSP_TsifMapping(TSP_TSIF eTSIF)7604 TSP_TSIF MDrv_TSP_TsifMapping(TSP_TSIF eTSIF)
7605 {
7606 TSP_HAL_TSIF eHalTSIF = _TSP_DrvHal_TSIFMapping(eTSIF);
7607 MS_U32 u32TSIF = HAL_TSP_TsifMapping(eHalTSIF,FALSE);
7608
7609 switch(u32TSIF)
7610 {
7611 case TSP_TSIF0:
7612 return E_TSP_TSIF_0;
7613 case TSP_TSIF1:
7614 return E_TSP_TSIF_1;
7615 case TSP_TSIF2:
7616 return E_TSP_TSIF_2;
7617 case TSP_TSIF3:
7618 return E_TSP_TSIF_3;
7619 case TSP_TSIF4:
7620 return E_TSP_TSIF_4;
7621 case TSP_TSIF5:
7622 return E_TSP_TSIF_5;
7623 case TSP_TSIF6:
7624 return E_TSP_TSIF_6;
7625 default:
7626 TSP_DBG(E_TSP_DBG_WARNING, "[%04d] TSIF %u is wrong !! \n", __LINE__, u32TSIF);
7627 return E_TSP_TSIF_0;
7628 }
7629 }
7630
MDrv_TSP_WriteProtect_Enable(MS_BOOL bEnable,MS_PHY * pphyStartAddr,MS_PHY * pphyEndAddr)7631 TSP_Result MDrv_TSP_WriteProtect_Enable(MS_BOOL bEnable, MS_PHY *pphyStartAddr, MS_PHY *pphyEndAddr)
7632 {
7633 TSP_ENTRY();
7634
7635 // SEC #0 , #1
7636 HAL_TSP_SEC_Address_Protect(0, pphyEndAddr[0], pphyStartAddr[0]);
7637 HAL_TSP_SEC_Address_Protect(1, pphyEndAddr[1], pphyStartAddr[1]);
7638 HAL_TSP_SEC_Address_Protect_En(bEnable);
7639
7640 // PVR #1 ~ #3
7641 HAL_TSP_PVR_Address_Protect(0, pphyEndAddr[2], pphyStartAddr[2]);
7642 HAL_TSP_PVR_Address_Protect_En(0,bEnable);
7643 HAL_TSP_PVR_Address_Protect(1, pphyEndAddr[3], pphyStartAddr[3]);
7644 HAL_TSP_PVR_Address_Protect_En(1,bEnable);
7645 HAL_TSP_PVR_Address_Protect(2, pphyEndAddr[4], pphyStartAddr[4]);
7646 HAL_TSP_PVR_Address_Protect_En(2,bEnable);
7647
7648 TSP_RETURN(E_TSP_OK);
7649 }
7650
MDrv_TSP_OrzWriteProtect_Enable(MS_BOOL bEnable,MS_PHY phyStartAddr,MS_PHY phyEndAddr)7651 TSP_Result MDrv_TSP_OrzWriteProtect_Enable(MS_BOOL bEnable, MS_PHY phyStartAddr, MS_PHY phyEndAddr)
7652 {
7653 TSP_ENTRY();
7654
7655 HAL_TSP_OR_Address_Protect(phyEndAddr, phyStartAddr);
7656 HAL_TSP_OR_Address_Protect_En(bEnable);
7657
7658 TSP_RETURN(E_TSP_OK);
7659 }
7660
7661 //for kernel mode multiple process support, create eventid of callback thread of user mode in fitst time
7662 #ifdef MSOS_TYPE_LINUX_KERNEL
7663 static char tspevt_name[] = "tspevt";
7664 #endif
MDrv_TSP_Create_IoSignal(DrvTSP_IoSignal * pstIoSignal)7665 TSP_Result MDrv_TSP_Create_IoSignal(DrvTSP_IoSignal *pstIoSignal)
7666 {
7667 #ifdef MSOS_TYPE_LINUX_KERNEL
7668 MS_U32 u32ii = 0;
7669
7670 for(u32ii = 0; u32ii < TSP_MAX_PVRSIGFLAG_NUM; u32ii++)
7671 {
7672 pstIoSignal->u32PvrBufFullFlag[u32ii] = 0;
7673 }
7674 for(u32ii = 0; u32ii < TSP_MAX_SIGFLAG_NUM; u32ii++)
7675 {
7676 pstIoSignal->u32SecRdyFlag[u32ii] = 0;
7677 pstIoSignal->u32SecOvfFlag[u32ii] = 0;
7678 }
7679
7680 if(pstIoSignal->s32KerModeTspEvtId == -1)
7681 {
7682 if((pstIoSignal->s32KerModeTspEvtId = TSP_OS_EventCreate((MS_U8*)tspevt_name)) != -1)
7683 {
7684 for(u32ii = 0; u32ii < DRVTSP_MAX_PROCESS_NUM; u32ii++)
7685 {
7686 if((_u32KPrcEvtTblUseFlag & (1 << u32ii)) == 0)
7687 {
7688 pstIoSignal->u32TblIndex = u32ii;
7689 _stKModePrcEvtTbl[u32ii].tgid = current->tgid;
7690 _stKModePrcEvtTbl[u32ii].s32TspEvtId = pstIoSignal->s32KerModeTspEvtId;
7691 _u32KPrcEvtTblUseFlag |= (1 << u32ii);
7692 break;
7693 }
7694 }
7695
7696 //printf("[%s][%d] _u32KPrcEvtTblUseFlag %x , s32TspEvtId %x \n", __FUNCTION__, __LINE__, (int)_u32KPrcEvtTblUseFlag, (int)pstIoSignal->s32KerModeTspEvtId);
7697
7698 return E_TSP_OK;
7699 }
7700 else
7701 {
7702 return E_TSP_FAIL;
7703 }
7704 }
7705
7706 return E_TSP_OK;
7707 #else
7708 return E_TSP_FAIL_NOT_SUPPORTED;
7709 #endif
7710 }
7711
7712 // Send free event to end user mode callback thread, and delete event id
MDrv_TSP_Close_IoSignal(DrvTSP_IoSignal * pstIoSignal)7713 TSP_Result MDrv_TSP_Close_IoSignal(DrvTSP_IoSignal *pstIoSignal)
7714 {
7715 #ifdef MSOS_TYPE_LINUX_KERNEL
7716
7717 MS_U32 u32ii = 0;
7718
7719 pstIoSignal->s32KerModeTspEvtId = -1;
7720 for(u32ii = 0; u32ii < DRVTSP_MAX_PROCESS_NUM; u32ii++)
7721 {
7722 if((_u32KPrcEvtTblUseFlag & (1 << u32ii)) != 0)
7723 {
7724 if(_stKModePrcEvtTbl[u32ii].tgid == current->tgid)
7725 {
7726 pstIoSignal->s32KerModeTspEvtId = _stKModePrcEvtTbl[u32ii].s32TspEvtId;
7727 break;
7728 }
7729 }
7730 }
7731 if(pstIoSignal->s32KerModeTspEvtId == -1)
7732 return E_TSP_FAIL;
7733
7734 //printf("%s][%d] s32KerModeTspEvtId %x\n", __FUNCTION__, __LINE__, (int)pstIoSignal->s32KerModeTspEvtId);
7735
7736 TSP_SetEvent(pstIoSignal->s32KerModeTspEvtId, TSP_EVENT_TASKEND);
7737
7738 //to free CB process task, so send one event
7739 MsOS_DelayTask(3);
7740
7741 while(_s32_IsrTaskReturn != TRUE)
7742 {
7743 TSP_SetEvent(pstIoSignal->s32KerModeTspEvtId, TSP_EVENT_TASKEND);
7744 MsOS_DelayTask(3);
7745 }
7746
7747 while(TSP_OS_EventDelete(pstIoSignal->s32KerModeTspEvtId) == FALSE)
7748 {
7749 TSP_SetEvent(pstIoSignal->s32KerModeTspEvtId, TSP_EVENT_TASKEND);
7750 printf("Waiting for evet deleting... \n");
7751 MsOS_DelayTask(3);
7752 }
7753 pstIoSignal->s32KerModeTspEvtId = -1;
7754
7755 _u32KPrcEvtTblUseFlag &= ~(1 << u32ii);
7756 _stKModePrcEvtTbl[u32ii].s32TspEvtId = -1;
7757 _stKModePrcEvtTbl[u32ii].tgid = 0;
7758
7759 #endif
7760
7761 return E_TSP_OK;
7762 }
7763
MDrv_TSP_Wait_IoSignal(DrvTSP_IoSignal * pstIoSignal)7764 TSP_Result MDrv_TSP_Wait_IoSignal(DrvTSP_IoSignal *pstIoSignal)
7765 {
7766 #ifdef MSOS_TYPE_LINUX_KERNEL
7767 MS_U8 u8Index;
7768 MS_S32 s32Ret = 0;
7769 MS_U32 u32Event = 0;
7770
7771 for(u8Index = 0; u8Index < TSP_MAX_PVRSIGFLAG_NUM; ++u8Index)
7772 {
7773 pstIoSignal->u32PvrBufFullFlag[u8Index] = 0;
7774 }
7775
7776 for(u8Index = 0; u8Index < TSP_MAX_SIGFLAG_NUM; ++u8Index)
7777 {
7778 pstIoSignal->u32SecRdyFlag[u8Index] = 0;
7779 pstIoSignal->u32SecOvfFlag[u8Index] = 0;
7780 pstIoSignal->u32SecCrcErrFlag[u8Index] = 0;
7781 }
7782
7783 #if 1
7784 if((s32Ret = MsOS_WaitEvent_Interrupt(pstIoSignal->s32KerModeTspEvtId, TSP_TASK_EVENTS, &u32Event, E_OR_CLEAR, MSOS_WAIT_FOREVER)) <= 0)
7785 {
7786 pstIoSignal->u32TspEvt = 0;
7787
7788 if(s32Ret < 0) // -ERESTARTSYS
7789 {
7790 return E_TSP_FAIL_FUNCTION;
7791 }
7792 else
7793 {
7794 return E_TSP_FAIL;
7795 }
7796 }
7797 #else
7798 s32Ret = TSP_GetEvent(_s32EventId, &u32Event, TSP_TASK_EVENTS, E_OR_CLEAR, MSOS_WAIT_FOREVER);
7799 if((u32Event & TSP_TASK_EVENTS) == 0)
7800 {
7801 return E_TSP_FAIL;
7802 }
7803 #endif
7804
7805 if(u32Event & TSP_EVENT_TASKEND)
7806 {
7807 _s32_IsrTaskReturn = TRUE;
7808 }
7809
7810 pstIoSignal->u32TspEvt = u32Event;
7811 #endif
7812
7813 return E_TSP_OK;
7814 }
7815
MDrv_TSP_Proc_IoSignal(DrvTSP_IoSignal * pstIoSignal)7816 TSP_Result MDrv_TSP_Proc_IoSignal(DrvTSP_IoSignal *pstIoSignal)
7817 {
7818 #ifdef MSOS_TYPE_LINUX_KERNEL
7819 MS_U32 fltid, flags = 0, ModeMask, dummy, BaseFlt;
7820 MS_U16 i, u16BufId;
7821 MS_BOOL bData;
7822
7823 if(pstIoSignal->u32TspEvt & TSP_EVENT_FREEFLT)
7824 {
7825 for (i = 0; i < ((TSP_SECFLT_NUM+31)>>5); i++)
7826 {
7827 // Add to FREE list
7828 TSP_FLAG_GetModeFlags(i, ModeMask); // get CB mode Filter Mask
7829 TSP_FLAG_ModeFree(i, ModeMask,&flags, TSP_OS_EVENT_OR_CLEAR);
7830
7831 while (flags)
7832 {
7833 BaseFlt = MAsm_CPU_GetTrailOne(flags);
7834 fltid = BaseFlt + (i<<5);
7835 TSP_LOCK();
7836 _TSP_FLT_Disable(fltid); // disable output
7837 TSP_UNLOCK();
7838 flags &= ~(1 << BaseFlt);
7839 TSP_FLAG_SetDone(fltid);
7840
7841 // Clear other filter activities
7842 TSP_FLAG_GetFltDis(fltid, &dummy, TSP_OS_EVENT_OR_CLEAR);
7843 TSP_FLAG_GetSecOvf(fltid, &dummy, TSP_OS_EVENT_OR_CLEAR);
7844 TSP_FLAG_GetSecRdy(fltid, &dummy, TSP_OS_EVENT_OR_CLEAR);
7845 }
7846 }
7847 }
7848
7849 MsOS_DelayTask(1);
7850
7851 // Check all section avaiable filters
7852 if (pstIoSignal->u32TspEvt & TSP_EVENT_SECTION)
7853 {
7854 for (i = 0; i < ((TSP_SECFLT_NUM+31)>>5); i++)
7855 {
7856 TSP_FLAG_GetModeFlags(i, ModeMask); // get CB mode Filter Mask
7857
7858 TSP_FLAG_ModeCrcErr(i, ModeMask,&flags, TSP_OS_EVENT_OR_CLEAR);
7859 while (flags)
7860 {
7861 //(POLL) Check any possible filter should be disabled
7862 //(TASK) Check only one-shot filter and to disable
7863 BaseFlt = MAsm_CPU_GetTrailOne(flags);
7864 fltid = BaseFlt + (i<<5);
7865
7866 // cause we serve free event before section rdy
7867 if ((_ptsp_res->_tspInfo.FltState[fltid] != E_TSP_FLT_STATE_FREE) && (_ptsp_res->_tspInfo.FltState[fltid] != E_TSP_FLT_STATE_ISR_FREE))
7868 {
7869 if ((_ptsp_res->_tspInfo.FltState[fltid] & E_TSP_FLT_STATE_ENABLE) &&
7870 (_ptsp_res->_tspInfo.FltEvent[fltid] & E_TSP_EVENT_SEC_CRCERROR) &&
7871 (_ptsp_res->_tspInfo.FltCallback[fltid]))
7872 {
7873 pstIoSignal->u32SecCrcErrFlag[i] |= (1UL << (BaseFlt & 0x1FUL));
7874 }
7875
7876 }
7877 flags &= ~(1 << BaseFlt);
7878 }
7879
7880 TSP_FLAG_ModeSecRdy(i, ModeMask,&flags, TSP_OS_EVENT_OR_CLEAR);
7881 while (flags)
7882 {
7883 //(POLL) Check any possible filter should be disabled
7884 //(TASK) Check only one-shot filter and to disable
7885 BaseFlt = MAsm_CPU_GetTrailOne(flags);
7886 fltid = BaseFlt + (i<<5);
7887
7888 // cause we serve free event before section rdy
7889 if ((_ptsp_res->_tspInfo.FltState[fltid] != E_TSP_FLT_STATE_FREE) && (_ptsp_res->_tspInfo.FltState[fltid] != E_TSP_FLT_STATE_ISR_FREE))
7890 {
7891 TSP_LOCK();
7892 u16BufId = HAL_TSP_SecFlt_GetSecBuf(&(_REGSec->Flt[fltid]));
7893 bData = (HAL_TSP_SecBuf_GetRead(&(_REGBuf->Buf[u16BufId])) != HAL_TSP_SecBuf_GetWrite(&(_REGBuf->Buf[u16BufId]))) ? TRUE : FALSE;
7894 TSP_UNLOCK();
7895
7896 if(bData)
7897 {
7898 if ((_ptsp_res->_tspInfo.FltState[fltid] & E_TSP_FLT_STATE_ENABLE) &&
7899 (_ptsp_res->_tspInfo.FltEvent[fltid] & E_TSP_EVENT_DATA_READY) &&
7900 (_ptsp_res->_tspInfo.FltCallback[fltid]))
7901 {
7902 pstIoSignal->u32SecRdyFlag[i] |= (1UL << (BaseFlt & 0x1FUL));
7903 }
7904
7905 }
7906
7907 if (TSP_FLAG_GetFltDis(fltid, &dummy, TSP_OS_EVENT_OR_CLEAR))
7908 {
7909 TSP_LOCK();
7910 _TSP_FLT_Disable(fltid);
7911 TSP_UNLOCK();
7912 }
7913 }
7914 flags &= ~(1 << BaseFlt);
7915 }
7916
7917 TSP_FLAG_ModeSecOvf(i, ModeMask,&flags, TSP_OS_EVENT_OR_CLEAR);
7918 while (flags)
7919 {
7920 //(POLL) Check any possible filter should be disabled
7921 //(TASK) Check only overflowed filter and to disable
7922 BaseFlt = MAsm_CPU_GetTrailOne(flags);
7923 fltid = BaseFlt + (i<<5);
7924
7925 if ((_ptsp_res->_tspInfo.FltState[fltid] != E_TSP_FLT_STATE_FREE) &&
7926 (_ptsp_res->_tspInfo.FltState[fltid] != E_TSP_FLT_STATE_ISR_FREE) &&
7927 (!TSP_FLAG_GetOvfRst(fltid)))
7928 {
7929 TSP_LOCK();
7930 if (HAL_TSP_PidFlt_GetFltOutput(&(_REGPid1->Flt[fltid])) & TSP_PIDFLT_OUT_SECFLT)
7931 {
7932 _TSP_FLT_Disable(fltid);
7933 }
7934 TSP_FLAG_SetOvfRst(fltid);
7935 TSP_UNLOCK();
7936
7937 TSP_FLAG_GetFltDis(fltid, &dummy, TSP_OS_EVENT_OR_CLEAR);
7938
7939 if ((_ptsp_res->_tspInfo.FltEvent[fltid] & E_TSP_EVENT_BUF_OVERFLOW) &&
7940 (_ptsp_res->_tspInfo.FltCallback[fltid]))
7941 {
7942 pstIoSignal->u32SecOvfFlag[i] |= (1UL << (BaseFlt & 0x1FUL));
7943 }
7944 }
7945 flags &= ~(1 << BaseFlt);
7946 // Clear other filter activities
7947 TSP_FLAG_GetSecRdy(fltid, &dummy, TSP_OS_EVENT_OR_CLEAR); // Clear section ready also
7948 }
7949
7950 MsOS_DelayTask(1);
7951 }
7952 }
7953
7954 MsOS_DelayTask(1);
7955
7956 if (pstIoSignal->u32TspEvt & TSP_EVENT_DISABLEFLT) //Disable Polling mode filter,CB mode filter disable at SecRdy or SecOvf
7957 {
7958 for (i = 0; i < ((TSP_SECFLT_NUM+31)>>5); i++)
7959 {
7960 TSP_FLAG_GetModeFlags(i, ModeMask); // get CB mode Filter Mask
7961 TSP_FLAG_ModeFltDis(i,~ModeMask, &flags ,TSP_OS_EVENT_OR_CLEAR); // Polling mode
7962 while (flags)
7963 {
7964 BaseFlt = MAsm_CPU_GetTrailOne(flags);
7965 fltid = BaseFlt + (i<<5);
7966 if (TSP_FLAG_GetFltDis(fltid, &dummy, TSP_OS_EVENT_OR_CLEAR))
7967 {
7968 TSP_LOCK();
7969 _TSP_FLT_Disable(fltid); // disable output
7970 TSP_UNLOCK();
7971 }
7972 flags &= ~(1 << BaseFlt);
7973 }
7974 }
7975 }
7976
7977 #endif
7978
7979 return E_TSP_OK;
7980 }
7981
7982 #ifdef SECURE_PVR_ENABLE
7983
MDrv_TSP_Ree_TeeCmdSystem_Init()7984 TSP_Result MDrv_TSP_Ree_TeeCmdSystem_Init()
7985 {
7986 MDrv_SYS_ReadKernelCmdLine();
7987 MDrv_SYS_GetTEEInfo(&_ptsp_res->_teemode);
7988 //printf("[%s][%d] _teemode %x \n", __FUNCTION__, __LINE__, (int)_ptsp_res->_teemode.OsType);
7989
7990 //_ptsp_res->_teemode.OsType = SYS_TEEINFO_OSTYPE_OPTEE;
7991 if(_ptsp_res->_teemode.OsType == SYS_TEEINFO_OSTYPE_NUTTX)
7992 {
7993 if(_TSP_REE_RegisterMBX() == FALSE)
7994 {
7995 MS_DEBUG_MSG(TSP_DBG ("[%s] Register Mailbox failed!\n", __FUNCTION__));
7996 return E_TSP_FAIL;
7997 }
7998 }
7999
8000 return E_TSP_OK;
8001 }
8002
MDrv_TSP_Ree_TeeCmdSystem_Exit()8003 TSP_Result MDrv_TSP_Ree_TeeCmdSystem_Exit()
8004 {
8005 _bTSPMbxInitFlag = FALSE;
8006 _u8TSPMbxMsgClass = 0;
8007
8008 return E_TSP_OK;
8009 }
8010
MDrv_TSP_Ree_SendTeeCmd(TSP_REE_TO_TEE_CMD_TYPE cmd_type,void * param,size_t datasize)8011 TSP_Result MDrv_TSP_Ree_SendTeeCmd(TSP_REE_TO_TEE_CMD_TYPE cmd_type, void* param, size_t datasize)
8012 {
8013
8014 if(_ptsp_res->_teemode.OsType == SYS_TEEINFO_OSTYPE_NUTTX)
8015 {
8016 if(_TSP_Ree_SendMBXMsg(cmd_type, param) == TRUE)
8017 return E_TSP_OK;
8018 else
8019 return E_TSP_FAIL;
8020 }
8021 else if(_ptsp_res->_teemode.OsType == SYS_TEEINFO_OSTYPE_OPTEE)
8022 {
8023 unsigned int ret, ret_orig= 0;
8024
8025 if ((ret = MDrv_SYS_TEEC_InitializeContext(_dmx_device, &dmx_mstar_teec_ctx)) != TEEC_SUCCESS)
8026 {
8027 printf("%s %d: Init Context failed, err code: %x\n",__FUNCTION__,__LINE__, (int)ret);
8028 return E_TSP_FAIL;
8029 }
8030 if ((ret = MDrv_SYS_TEEC_Open(&dmx_mstar_teec_ctx, &dmx_session, &dmx_uuid, TEEC_LOGIN_PUBLIC, NULL, NULL, &ret_orig)) != TEEC_SUCCESS)
8031 {
8032 printf("%s %d: TEEC Open session failed, err code: %x\n",__FUNCTION__,__LINE__, (int)ret);
8033 return E_TSP_FAIL;
8034 }
8035
8036 if(datasize == 0)
8037 {
8038 dmx_op.paramTypes = TEEC_PARAM_TYPES(TEEC_NONE, TEEC_NONE,TEEC_NONE, TEEC_NONE);
8039 }
8040 else
8041 {
8042 dmx_op.params[0].tmpref.buffer = param;
8043 dmx_op.params[0].tmpref.size = datasize;
8044 dmx_op.paramTypes = TEEC_PARAM_TYPES(TEEC_MEMREF_TEMP_INOUT, TEEC_NONE, TEEC_NONE, TEEC_NONE);
8045 }
8046
8047 if ((ret = MDrv_SYS_TEEC_InvokeCmd(&dmx_session, cmd_type, &dmx_op, &ret_orig)) != TEEC_SUCCESS)
8048 {
8049 printf("%s %d: TEEC Invoke command failed, err code: %x\n",__FUNCTION__,__LINE__, (int)ret);
8050 }
8051 MDrv_SYS_TEEC_Close(&dmx_session);
8052 MDrv_SYS_TEEC_FinalizeContext(&dmx_mstar_teec_ctx);
8053 if(ret == TEEC_SUCCESS)
8054 {
8055 return E_TSP_OK;
8056 }
8057 }
8058
8059 return E_TSP_FAIL;
8060 }
8061
8062 #endif //SECURE_PVR_ENABLE
8063