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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ///////////////////////////////////////////////////////////////////////////////////////////////////
96 /// file Mdrv_sc_display.c
97 /// @brief Driver Interface
98 /// @author MStar Semiconductor Inc.
99 ///////////////////////////////////////////////////////////////////////////////////////////////////
100
101 //-------------------------------------------------------------------------------------------------
102 // Include Files
103 //-------------------------------------------------------------------------------------------------
104 #ifdef MSOS_TYPE_LINUX_KERNEL
105 #include <asm/div64.h>
106 #else
107 #define do_div(x,y) ((x)/=(y))
108 #endif
109
110 // Common Definition
111 #ifdef MSOS_TYPE_LINUX_KERNEL
112 #include <linux/string.h>
113 #else
114 #include <string.h>
115 #endif
116 #include "MsCommon.h"
117 #include "MsIRQ.h"
118 #include "MsOS.h"
119 #include "mhal_xc_chip_config.h"
120 #include "utopia.h"
121 #include "utopia_dapi.h"
122 // Internal Definition
123 #include "drvXC_IOPort.h"
124 #include "xc_Analog_Reg.h"
125 #include "xc_hwreg_utility2.h"
126 #include "apiXC.h"
127 #include "apiXC_Adc.h"
128 #include "apiXC_Auto.h"
129 #include "drv_sc_display.h"
130 #include "drv_sc_isr.h"
131 #include "apiXC_PCMonitor.h"
132 #include "apiXC_ModeParse.h"
133 #include "drvXC_HDMI_if.h"
134 #include "mvideo_context.h"
135 #include "drv_sc_ip.h"
136 #if (LD_ENABLE==1)
137 #include "mdrv_ld.h"
138 #include "mdrv_ldalgo.h"
139 #endif
140 #include "mdrv_sc_3d.h"
141 #include "drv_sc_menuload.h"
142 #include "drvXC_ADC_Internal.h"
143 #include "mhal_sc.h"
144 #if FRC_INSIDE
145 #include "mdrv_frc.h"
146 #include "mhal_frc.h"
147 #endif
148 #include "XC_private.h"
149 #include "apiXC_v2.h"
150 #include "drv_sc_scaling.h"
151 #include "mdrv_sc_3d.h"
152 #include "mhal_ip.h"
153 #include "apiXC_DWIN.h"
154 #include "drv_sc_DIP_scaling.h"
155 #include "mhal_dip.h"
156 #include "halCHIP.h"
157 #include "mhal_menuload.h"
158 #include "drvXC_HDMI_Internal.h"
159 #include "drvSYS.h"
160 #if (defined MSOS_TYPE_LINUX) || (defined ANDROID)
161 #include <sys/ioctl.h>
162 #include <unistd.h>
163 #include <fcntl.h> // O_RDWR
164 #endif
165 #include "mdrv_xc_io.h"
166 #include "mdrv_sc_dynamicscaling.h"
167 //-------------------------------------------------------------------------------------------------
168 // Driver Compiler Options
169 //-------------------------------------------------------------------------------------------------
170
171
172 //-------------------------------------------------------------------------------------------------
173 // Local Defines
174 //-------------------------------------------------------------------------------------------------
175
176 #define VERIFY_DISPLAY_FPGA 0
177 #define PHASE_DIFF_LIMIT 0xFFFFUL
178 #ifdef UFO_XC_AUTO_DOWNLOAD
179 #define AUTO_DOWNLOAD_HDR_IN_KERNEL
180 #define AUTO_DOWNLOAD_XVYCC_IN_KERNEL
181 #endif
182
183 MS_U32 _u32ZorderMLoadCmd[MS_MLOAD_MAX_CMD_CNT];
184 MS_U16 _u16ZorderMLoadMsk[MS_MLOAD_MAX_CMD_CNT];
185 MS_U16 _u16ZorderMLoadVal[MS_MLOAD_MAX_CMD_CNT];
186 MS_U16 _u16ZorderMLoadCmdCnt = 0;
187 MS_BOOL _bZorderMLoadEn = FALSE;
188 //#ifdef ENABLE_SPREADMODE
189 //MS_BOOL _bSpreandEnable = FALSE;
190 //#endif
191
192 // for high accurate input VFreq case, to avoid reconfig Vtt/Htt
193 #define CHANGE_VTT_TOLERANCE 5
194 #define CHANGE_HTT_TOLERANCE 10
195
196 #define MINMUN_V_BACKPORCH 4
197 #define IsFSCDisplayWindowEnable() (pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFSCEnabled == TRUE)
198 //-----------------------------------------------------------------------------
199 // below definitions are for FSM FPLL
200 //-----------------------------------------------------------------------------
201 typedef enum
202 {
203 EN_OUTPUT_TIMING_CHG_DCLK = 0,
204 EN_OUTPUT_TIMING_HTOTAL = 1,
205 EN_OUTPUT_TIMING_VTOTAL = 2,
206 } EN_OUTPUT_TIMING_ADJUST_MODE;
207
208 #define FPLL_FSM_STABLE_TIME (10000) // if exceed this stable time, the FPLL FSM will re-init
209 #define FPLL_PRD_MAX (0xFFFF) // Max PRD value
210 #define FPLL_PHASE_VAR_LIMIT (0x10) // If phase error variation exceed this, means un-stable
211 #define FPLL_PRD_THRESHOLD (0x100) // The PRD must be smaller than this value to indicate almost finished PRD lock
212 #define FPLL_PRD_VAR_LIMIT (0x10) // If PRD variation exceed this, means un-stable
213 #define FPLL_PHASE_MAX (0xFFFF) // Max PHASE value
214 #define FPLL_PHASE_DIFF_MAX (0x4000) // Max PHASE diff value
215 #define FPLL_PRD_STABLE_COUNT 0x06
216 #define FPLL_SWITCH_LOCKVFREQ_TIME (500) // if exceed this stable time, the FPLL would switch to LockVfreq mode
217
218 #define GATE_PHASELIMIT 0x3000
219
220 #define FPLL_STEP_LIMIT_FOR_ADJUST_SET 0x100 //step limit when adjusting SET
221
222 // FPLL
223 #define IVS_OVS_MAX_DIFF 0x1000UL // before calculate 2nd SET, will check if IVS/OVS diff too big to verify the LPLL SET accuracy
224 #define IVS_VAR_LIMIT 0x10 // before calculate 2nd SET, the IVS should be very stable, if the variable exceed this, it's un-stable and not cal. 2nd SET
225 #define VD_HSYNC_LOCKED BIT(14)
226
227 //Timing
228 #define VFREQ_DIFF_TOLERANCE 10 //Value to distinguish two Vfreq(x10Hz)
229
230 #define PHASE_LOCK_EN 0
231
232 #ifdef MAXIM_ATV_LOCK_PHASE_PATCH
233 #define ENABLE_LOCK_IVS_OVS_FOR_ATV 0
234 #else
235 #define ENABLE_LOCK_IVS_OVS_FOR_ATV 1
236 #endif
237
238 #define SLOWLY_MOVE_STEPS (1)
239
240 #define VTT_OFFSET_FOR_PHASE_LOCK 8
241 #define DEFAULT_IP_VSYNC_PERIOD (20)
242
243 #define V_PERIOD_DIFF_TOLERANCE 10
244 //-------------------------------------------------------------------------------------------------
245 // Local Structurs
246 //-------------------------------------------------------------------------------------------------
247
248 //-------------------------------------------------------------------------------------------------
249 // Global Variables
250 //-------------------------------------------------------------------------------------------------
251
252 //-------------------------------------------------------------------------------------------------
253 // Local Variables
254 //-------------------------------------------------------------------------------------------------
255 static SC_FRC_SETTING sFRC_Tbl_Default[MAX_FRC_TABLE_INDEX] =
256 {
257 {0, 160, 0, 1, 4, MS_FRC_1_4},
258 {160, 210, 0, 1, 3, MS_FRC_1_3},
259 {210, 245, 0, 2, 5, MS_FRC_2_5}, // 24 to 48 {210, 245, 1, 2, MS_FRC_1_2}
260 {245, 260, 0, 1, 2, MS_FRC_1_2},
261 {260, 400, 0, 1, 2, MS_FRC_1_2},
262 {470, 490, 0, 4, 5, MS_FRC_4_5},
263 {400, 510, 0, 1, 1, MS_FRC_1_1},
264 {510, 0xFFFF, 0, 1, 1, MS_FRC_1_1},
265 };
266
267 static void (*_fpPQSetFPLLThreshMode)(MS_U8) = NULL;
268
269 #ifdef UFO_XC_HDR
270 #if (UFO_XC_HDR_VERSION == 2)
271 #if (defined MSOS_TYPE_LINUX) || (defined ANDROID)
272 MS_S32 _s32FdScaler = -1;
273 #endif
274 #endif
275 #endif
276 //-------------------------------------------------------------------------------------------------
277 // Debug Functions
278 //-------------------------------------------------------------------------------------------------
279
280
281 //-------------------------------------------------------------------------------------------------
282 // Local Functions
283 //-------------------------------------------------------------------------------------------------
284 MS_U16 MDrv_SC_FBL_Calc_Vtt(void *pInstance, XC_SetTiming_Info *pTimingInfo, SCALER_WIN eWindow);
285 MS_U16 MDrv_SC_VFreq_Select(void *pInstance, MS_U16 u16AutoVFreq);
286
287 // Output Dclk and Loop DIV : Ref from PNL driver. It is easy to maintain if XC and PNL use same function.
288 MS_U32 MDrv_PNL_CalculateLPLLSETbyDClk(void *pInstance, MS_U64 ldHz, MS_BOOL bHighAccurate);
289 MS_U8 MHal_PNL_Get_Loop_DIV(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz);
290 MS_U16 MHal_PNL_Get_LPLL_LoopGain(void *pInstance, MS_U8 eLPLL_Mode, MS_U8 eLPLL_Type, MS_U64 ldHz);
291 #if LOCK_FREQ_ONLY_WITHOUT_LOCK_PHASE
292 static void _MApi_XC_FPLL_EnableLcokFreqOnly(void *pInstance,MS_BOOL bEnable);
293 #endif
294 static MS_BOOL _MDrv_SC_IsOutVFreValid(void *pInstance, MS_U16 u16OutputVFreq, MS_U16 u16Delta);
295
296 #ifdef PATCH_TCON_BRING_UP
297 const char* MDrv_PNL_GetName(void);
298 #endif
299
300 //-------------------------------------------------------------------------------------------------
301 // Global Functions
302 //-------------------------------------------------------------------------------------------------
303
304 #if (defined(MSOS_TYPE_LINUX_KERNEL) && defined(CONFIG_MSTAR_XC_HDR_SUPPORT))
305 extern MS_BOOL MDrv_XC_SetHDRWindow(ST_KDRV_XC_WINDOW_INFO *pstWindowInfo);
306 extern MS_BOOL MDrv_XC_SetInputSourceType(EN_KDRV_XC_INPUT_SOURCE_TYPE enInputSourceType);
307 extern MS_BOOL MDrv_XC_SetColorFormat(EN_KDRV_XC_HDR_COLOR_FORMAT enColorFormat);
308 extern MS_BOOL MDrv_XC_SetShareMemInfo(ST_KDRV_XC_SHARE_MEMORY_INFO *pstShmemInfo);
309 extern MS_BOOL MDrv_XC_Set3DLutInfo(ST_KDRV_XC_3DLUT_INFO *pst3DLutInfo);
310 extern MS_BOOL MDrv_XC_SetHDRType(EN_KDRV_XC_HDR_TYPE enHDRType);
311 extern MS_BOOL MDrv_XC_EnableHDR(MS_BOOL bEnableHDR);
312 extern MS_BOOL MDrv_XC_ConfigAutoDownload(ST_KDRV_XC_AUTODOWNLOAD_CONFIG_INFO *pstConfigInfo);
313 extern MS_BOOL MDrv_XC_WriteAutoDownload(ST_KDRV_XC_AUTODOWNLOAD_DATA_INFO *pstDataInfo);
314 extern MS_BOOL MDrv_XC_FireAutoDownload(EN_KDRV_XC_AUTODOWNLOAD_CLIENT enClient);
315 extern MS_BOOL KDrv_XC_GetAutoDownloadCaps(ST_KDRV_XC_AUTODOWNLOAD_CLIENT_SUPPORTED_CAPS *pstAutoDownlaodCaps);
316 extern MS_BOOL MDrv_XC_GetHDRType(EN_KDRV_XC_HDR_TYPE *penHDRType);
317 extern MS_BOOL MDrv_XC_CFDControl(ST_KDRV_XC_CFD_CONTROL_INFO *pstKdrvCFDCtrlInfo);
318 extern MS_BOOL KDrv_XC_SetSWDRInfo(ST_KDRV_XC_SWDR_INFO* pstKdrvXcSwdrInfo);
319 extern MS_BOOL KDrv_XC_GetSWDRInfo(ST_KDRV_XC_SWDR_INFO* pstKdrvXcSwdrInfo);
320 #endif
321
322 //-----------------------------------------------------------------------------
323 // screen
324 //-----------------------------------------------------------------------------
MDrv_SC_Set_BLSK(void * pInstance,MS_BOOL bEnable)325 void MDrv_SC_Set_BLSK(void *pInstance, MS_BOOL bEnable)
326 {
327 if(MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED)
328 Hal_SC_set_blsk_burst(pInstance, bEnable);
329 else
330 Hal_SC_set_blsk(pInstance, bEnable);
331 }
332
MDrv_SC_GenerateBlackVideoForBothWin(void * pInstance,MS_BOOL bEnable)333 void MDrv_SC_GenerateBlackVideoForBothWin(void *pInstance, MS_BOOL bEnable)
334 {
335 if ( MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED )
336 Hal_SC_set_main_sub_black_screen_burst(pInstance, bEnable);
337 else
338 Hal_SC_set_main_sub_black_screen(pInstance, bEnable);
339 }
340
MDrv_SC_GetCurrentFRCTable(SC_FRC_SETTING * pstFRCTable)341 void MDrv_SC_GetCurrentFRCTable(SC_FRC_SETTING* pstFRCTable)
342 {
343 if(pstFRCTable == NULL)
344 return;
345
346 memcpy(pstFRCTable, sFRC_Tbl_Default, sizeof(sFRC_Tbl_Default));
347 }
348
_MDrv_SC_IsOutVFreValid(void * pInstance,MS_U16 u16OutputVFreq,MS_U16 u16Delta)349 MS_BOOL _MDrv_SC_IsOutVFreValid(void *pInstance, MS_U16 u16OutputVFreq, MS_U16 u16Delta)
350 {
351 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
352 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
353 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
354 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
355 return (((u16OutputVFreq >= 500 - u16Delta) && (u16OutputVFreq <= 500 + u16Delta)) ||
356 ((u16OutputVFreq >= 600 - u16Delta) && (u16OutputVFreq <= 600 + u16Delta)) ||
357 ((u16OutputVFreq >= 300- u16Delta) && (u16OutputVFreq <= 300 + u16Delta)) ||
358 ((u16OutputVFreq >= 240- u16Delta) && (u16OutputVFreq <= 250 + u16Delta)) ||
359 ((((u16OutputVFreq >= 1000- 2*u16Delta) && (u16OutputVFreq <= 1000 + 2*u16Delta))||
360 ((u16OutputVFreq >= 1200- 2*u16Delta) && (u16OutputVFreq <= 1200 + 2*u16Delta)))&&
361 ((pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq == 1000)||
362 (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq == 1200))));
363 }
364
365 #ifdef UFO_XC_SETBLACKVIDEOBYMODE
366 /******************************************************************************/
367 ///enable/diable output black pattern by mode
368 ///@param bEnable \b IN
369 ///- False:Disable
370 ///- TRUE :enable
371 /// @param eWindow \b IN: which window we are going to set
372 /// @param eMode \b IN: which black video mode we are going to use
373 /******************************************************************************/
MDrv_SC_GenerateBlackVideoByMode(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow,EN_XC_BLACK_VIDEO_MODE eMode)374 E_APIXC_ReturnValue MDrv_SC_GenerateBlackVideoByMode(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow, EN_XC_BLACK_VIDEO_MODE eMode)
375 {
376 E_APIXC_ReturnValue eRet = E_APIXC_RET_FAIL;
377
378 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW, "SC GenerateBlackVideo enable = %d,ewindow = %d\n", bEnable,eWindow);
379
380 if(eWindow == MAIN_WINDOW)
381 {
382 if(MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED)
383 eRet = Hal_SC_set_main_black_screen_by_mode_burst(pInstance, bEnable, eMode);
384 else
385 eRet = Hal_SC_set_main_black_screen_by_mode(pInstance, bEnable, eMode);
386 }
387 else
388 {
389 if(MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED)
390 eRet = Hal_SC_set_sub_blue_screen_by_mode_burst(pInstance, bEnable, DISABLE, eMode);
391 else
392 eRet = Hal_SC_set_sub_blue_screen_by_mode(pInstance, bEnable, DISABLE, eMode);
393 }
394
395 return eRet;
396 }
397 #endif
_notify_kernel(MS_BOOL bEnable)398 void _notify_kernel(MS_BOOL bEnable)
399 {
400 #if (defined MSOS_TYPE_LINUX) || (defined ANDROID)
401 if(0 > _s32FdScaler)
402 {
403 _s32FdScaler = open("/dev/scaler", O_RDWR);
404
405 if(0 > _s32FdScaler)
406 {
407 printf("Scaler device not opened!!!!\n");
408 return ;
409 }
410 }
411 #endif
412
413 ST_KDRV_XC_CFD_CONTROL_INFO stXCCfdControlInfo;
414 ST_KDRV_XC_CFD_UPDATE_STATUS stXCCfdUpdateStatus;
415 memset(&stXCCfdControlInfo, 0, sizeof(ST_KDRV_XC_CFD_CONTROL_INFO));
416 memset(&stXCCfdUpdateStatus, 0, sizeof(stXCCfdUpdateStatus));
417 stXCCfdControlInfo.enCtrlType = E_KDRV_XC_CFD_CTRL_UPDATE_STATUS;
418 if(bEnable)
419 stXCCfdUpdateStatus.enCFD_status = E_KDRV_XC_CFD_STATUS_SYNC_GEN_BLACK_SCREEN_ENABLE;
420 else
421 stXCCfdUpdateStatus.enCFD_status = E_KDRV_XC_CFD_STATUS_SYNC_GEN_BLACK_SCREEN_DISABLE;
422
423 stXCCfdControlInfo.pParam = &stXCCfdUpdateStatus;
424 stXCCfdControlInfo.u32ParamLen = sizeof(stXCCfdUpdateStatus);
425 stXCCfdControlInfo.u16ErrCode = 0;
426 #if (defined MSOS_TYPE_LINUX) || (defined ANDROID)
427 if (ioctl(_s32FdScaler, MDRV_XC_IOC_CFDCONCTRL, &stXCCfdControlInfo))
428 {
429 printf("MDRV_XC_IOC_CFDCONCTRL fail!!!!\n");
430 }
431 #endif
432 }
433 /******************************************************************************/
434 ///enable/diable output black pattern
435 ///@param bEnable \b IN
436 ///- False:Disable
437 ///- TRUE :enable
438 /******************************************************************************/
MDrv_SC_GenerateBlackVideo(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)439 void MDrv_SC_GenerateBlackVideo(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
440 {
441 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
442 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
443 //MS_U8 u8Bank;
444 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW, "SC%d GenerateBlackVideo enable = %d,ewindow = %d\n", psXCInstPri->u32DeviceID,bEnable,eWindow);
445 //u8Bank = MDrv_ReadByte(BK_SELECT_00);
446 EN_MUTE_TYPE eMuteType = E_MAIN_WINDOW_MUTE;
447 switch(eWindow)
448 {
449 case MAIN_WINDOW:
450 eMuteType = E_MAIN_WINDOW_MUTE;
451 break;
452 case SUB_WINDOW:
453 eMuteType = E_SUB_WINDOW_MUTE;
454 break;
455 default:
456 break;
457 }
458 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
459 if(psXCInstPri->u32DeviceID == 0)
460 #else
461 if(eWindow == MAIN_WINDOW)
462 #endif
463 {
464 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
465 if(eWindow == MAIN_WINDOW)
466 #endif
467 {
468 if((MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED) && (!MDrv_SC_GetForceWrite(eMuteType)) && (!MDrv_SC_GetForceWrite(E_PANEL_MUTE)))
469 Hal_SC_set_main_black_screen_burst(pInstance, bEnable);
470 else
471 Hal_SC_set_main_black_screen(pInstance, bEnable);
472 _notify_kernel(bEnable);
473 }
474 }
475 else
476 {
477 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB //follow HW_DESIGN_4K2K_VER = 6 rule
478 if(eWindow == MAIN_WINDOW)
479 {
480 if((MDrv_XC_MLoad_GetStatus(g_pDevice0Instance) == E_MLOAD_ENABLED) && (!MDrv_SC_GetSkipWaitVsync(g_pDevice0Instance, eWindow)))
481 Hal_SC_set_sub_blue_screen_burst(g_pDevice0Instance, bEnable, DISABLE);
482 else
483 Hal_SC_set_sub_blue_screen(g_pDevice0Instance, bEnable, DISABLE);
484 }
485 #else
486 if((MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED) && (!MDrv_SC_GetForceWrite(eMuteType)) && (!MDrv_SC_GetForceWrite(E_PANEL_MUTE)))
487 Hal_SC_set_sub_blue_screen_burst(pInstance, bEnable, DISABLE);
488 else
489 Hal_SC_set_sub_blue_screen(pInstance, bEnable, DISABLE);
490 #endif
491 }
492
493 #if VERIFY_DISPLAY_FPGA
494
495 //u8Bank = MDrv_ReadByte(BK_SELECT_00);
496 //----- enable IP signal for FPLL ---//
497 //MDrv_WriteByte(BK_SELECT_00, REG_BANK_IP1F2);
498 //MDrv_WriteRegBit(H_BK_IP1F2(0x03), 1, BIT(7));
499 //MDrv_WriteRegBit(H_BK_IP1F2(0x03), 1, BIT(3));
500 //MDrv_WriteByte(BK_SELECT_00, u8Bank);
501
502
503
504 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_03_L, 0x8000, BIT(15));
505 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_03_L, 0x0800, BIT(11));
506
507 //--- set LVDS format ----//
508 #ifdef SUPPORT_MOD_ADBANK_SEPARATE
509
510 #else
511 MOD_W2BYTEMSK(REG_MOD_BK00_40_L, 0x002C, 0x00FF); // set LVDS format
512 MOD_W2BYTEMSK(REG_MOD_BK00_4B_L, 0x0000, 0x00FF); // set LVDS format
513 MOD_W2BYTEMSK(REG_MOD_BK00_78_L, 0x007E, 0x00FF); // set LVDS driving
514 #endif
515 #endif
516 //--- restore bank select ---//
517
518 //MDrv_WriteByte(BK_SELECT_00, u8Bank);
519
520 }
521
MDrv_XC_SetDispWindowColor(void * pInstance,MS_U8 u8Color,SCALER_WIN eWindow)522 void MDrv_XC_SetDispWindowColor(void *pInstance, MS_U8 u8Color, SCALER_WIN eWindow)
523 {
524 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
525 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
526 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
527 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
528 pXCResourcePrivate->stdrvXC_MVideo_Context.g_u8DispWindowColor_Suspend[eWindow] = u8Color;
529 Hal_SC_set_nosignal_color(pInstance, u8Color,eWindow);
530 }
531
532 //-------------------------------------------------------------------------------------------------
533 /// set display window color
534 /// @param u8Color \b IN: the color to set
535 /// @param eWindow \b IN: which window we are going to set
536 //-------------------------------------------------------------------------------------------------
MApi_XC_SetDispWindowColor_U2(void * pInstance,MS_U8 u8Color,SCALER_WIN eWindow)537 void MApi_XC_SetDispWindowColor_U2(void* pInstance, MS_U8 u8Color, SCALER_WIN eWindow)
538 {
539 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
540 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
541 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
542 _XC_ENTRY(pInstance);
543 MDrv_XC_SetDispWindowColor(pInstance, u8Color, eWindow);
544 _XC_RETURN(pInstance);
545 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
546 }
547
MApi_XC_SetDispWindowColor(MS_U8 u8Color,SCALER_WIN eWindow)548 void MApi_XC_SetDispWindowColor(MS_U8 u8Color, SCALER_WIN eWindow)
549 {
550 if (pu32XCInst == NULL)
551 {
552 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
553 return;
554 }
555
556 stXC_SET_DISPLAY_WINDOW_COLOR XCArgs;
557 XCArgs.u8Color = u8Color;
558 XCArgs.eWindow = eWindow;
559 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_DISPLAY_WINDOW_COLOR, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
560 {
561 printf("Obtain XC engine fail\n");
562 return;
563 }
564 else
565 {
566 return;
567 }
568 }
569
570 //get the greatest common divisor
MDrv_SC_GCD(MS_U16 m,MS_U16 n)571 MS_U16 MDrv_SC_GCD(MS_U16 m, MS_U16 n)
572 {
573 MS_U16 m_cup, n_cup, res;
574
575 m_cup = m;
576 n_cup = n;
577 res = m_cup % n_cup;
578 while (res != 0)
579 {
580 m_cup = n_cup;
581 n_cup = res;
582 res = m_cup % n_cup;
583 }
584
585 return n_cup;
586 }
587
MDrv_SC_Handle_Special_FRCTbl(void * pInstance,MS_U16 u16DefaultVFreq,MS_U16 u16InputVFreq,SCALER_WIN eWindow)588 void MDrv_SC_Handle_Special_FRCTbl(void *pInstance, MS_U16 u16DefaultVFreq, MS_U16 u16InputVFreq, SCALER_WIN eWindow)
589 {
590 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
591 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
592 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
593 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
594 MS_U8 u8Ratio = 0;
595 MS_U16 u16FRCType=0;
596 #ifndef DISABLE_3D_FUNCTION
597 MS_BOOL bIsOutput48hz = (!pXCResourcePrivate->stdrvXC_Display._bUseCustomFRCTable) && MDrv_SC_3D_IsOutputVfreq48hz(pInstance, eWindow, u16InputVFreq);
598 #else
599 MS_BOOL bIsOutput48hz = FALSE;
600 #endif
601
602 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "@@@ bIsOutput48hz = %s\n",bIsOutput48hz?"TRUE":"FALSE")
603 memcpy(pXCResourcePrivate->stdrvXC_Display.sFRC_Tbl, sFRC_Tbl_Default, sizeof(sFRC_Tbl_Default));
604
605 // for muji 4k 0.5k@240 case
606 // AP send correct FRC in/out table, so no need to modify by u8Ratio
607 if(u16DefaultVFreq > 1800)
608 {
609 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "=====> @@@ 4k 0.5k@240 u16DefaultVFreq = %d\n",u16DefaultVFreq)
610 u8Ratio = 1;
611 }
612 //when the panel is 120hz default vfreq, the FRC table should be double the ratio.
613 //eg. input:30, original x2 out:60, but for 120hz panel, we should x4 out:120.
614 // the multiple is from x2 to x4
615 else if(u16DefaultVFreq > 900)
616 {
617 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_FRC_INSIDE_240HZ)
618 {
619 if((u16InputVFreq > 235) && (u16InputVFreq <= 245))
620 {
621 u8Ratio = 5;
622 }
623 else
624 {
625 u8Ratio = 4;
626 }
627 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "FRC table FRC_OUT x4 for 240 hz panel output\n")
628 }
629 else
630 {
631 u8Ratio = 2;
632 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "FRC table FRC_OUT x2 for 120 hz panel output\n")
633 }
634 }
635 else
636 {
637 u8Ratio = 1;
638 }
639 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "u16DefaultVFreq=%u, u8Ratio = %u\n", u16DefaultVFreq, u8Ratio) ;
640
641 for(u16FRCType = 0; u16FRCType < sizeof(pXCResourcePrivate->stdrvXC_Display.sFRC_Tbl)/sizeof(SC_FRC_SETTING); u16FRCType++)
642 {
643 // 24Hz -> 48Hz
644 if (bIsOutput48hz &&((u16DefaultVFreq == 600)
645 || (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_FRC_INSIDE_240HZ)))
646 {
647 // check FRC, and modify FRC table.
648 if((u16InputVFreq > pXCResourcePrivate->stdrvXC_Display.sFRC_Tbl[u16FRCType].u16LowerBound) &&
649 (u16InputVFreq <= pXCResourcePrivate->stdrvXC_Display.sFRC_Tbl[u16FRCType].u16HigherBound))
650 {
651 pXCResourcePrivate->stdrvXC_Display.sFRC_Tbl[u16FRCType].u8FRC_In = 1;
652 pXCResourcePrivate->stdrvXC_Display.sFRC_Tbl[u16FRCType].u8FRC_Out = 2;
653 pXCResourcePrivate->stdrvXC_Display.sFRC_Tbl[u16FRCType].eFRC_Type= MS_FRC_1_2;
654 }
655 }
656
657 if (u16DefaultVFreq > 900)
658 {
659 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_FRC_INSIDE_240HZ)
660 {
661 if(((u16InputVFreq > 235)
662 && (u16InputVFreq <= 245))
663 ||((u16InputVFreq > 290)
664 && (u16InputVFreq <= 310)))
665 {
666 pXCResourcePrivate->stdrvXC_Display.sFRC_Tbl[u16FRCType].u8FRC_In = 1;
667 pXCResourcePrivate->stdrvXC_Display.sFRC_Tbl[u16FRCType].u8FRC_Out = 2;
668 pXCResourcePrivate->stdrvXC_Display.sFRC_Tbl[u16FRCType].eFRC_Type= MS_FRC_1_2;
669 }
670 }
671 }
672
673 pXCResourcePrivate->stdrvXC_Display.sFRC_Tbl[u16FRCType].u8FRC_Out *= u8Ratio;
674 }
675
676 }
677 //-----------------------------------------------------------------------------
678 // frame rate convert
679 //-----------------------------------------------------------------------------
680
MApi_XC_CustomizeFRCTable_U2(void * pInstance,SC_FRC_SETTING * stFRCTable)681 E_APIXC_ReturnValue MApi_XC_CustomizeFRCTable_U2(void* pInstance, SC_FRC_SETTING* stFRCTable)
682 {
683 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
684 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
685 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
686
687 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
688 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
689 if (stFRCTable == NULL )
690 {
691 SC_FRC_SETTING sFRC_Tbl_Temp[MAX_FRC_TABLE_INDEX] =
692 {
693 {0, 160, 0, 1, 4, MS_FRC_1_4},
694 {160, 210, 0, 1, 3, MS_FRC_1_3},
695 {210, 245, 0, 2, 5, MS_FRC_2_5},
696 {245, 260, 0, 1, 2, MS_FRC_1_2},
697 {260, 400, 0, 1, 2, MS_FRC_1_2},
698 {400, 510, 0, 1, 1, MS_FRC_1_1},
699 {510, 0xFFFF, 0, 1, 1, MS_FRC_1_1},
700 };
701 pXCResourcePrivate->stdrvXC_Display._bUseCustomFRCTable = FALSE;
702 memcpy( sFRC_Tbl_Default, sFRC_Tbl_Temp , sizeof(sFRC_Tbl_Default) );
703 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING,"Attention! default frc table is using!\n");
704 }
705 else
706 {
707 MS_U8 u8Index = 0;
708 for(u8Index=0;u8Index<MAX_FRC_TABLE_INDEX;u8Index++) // calculate the counts of customer frc table
709 {
710 if((stFRCTable[u8Index]).u16HigherBound == 0xFFFF) // 0xFFFF was found
711 break;
712 }
713 if((stFRCTable[u8Index]).u16HigherBound != 0xFFFF) // 0xFFFF was not found
714 {
715 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING,"Warning! custom frc table is invalid(the last row should define a range of vfreq up to 0xFFFF), using the default table instead!!\n");
716 }
717 else
718 {
719 pXCResourcePrivate->stdrvXC_Display._bUseCustomFRCTable = TRUE;
720 memcpy( sFRC_Tbl_Default, stFRCTable, MIN((sizeof(sFRC_Tbl_Default)),(sizeof(SC_FRC_SETTING)*(u8Index+1))) );
721 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING,"Attention! custom frc table is using!\n");
722 }
723 }
724 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
725 return E_APIXC_RET_OK;
726 }
727
MApi_XC_CustomizeFRCTable(SC_FRC_SETTING * stFRCTable)728 E_APIXC_ReturnValue MApi_XC_CustomizeFRCTable(SC_FRC_SETTING* stFRCTable)
729 {
730 if (pu32XCInst == NULL)
731 {
732 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
733 return E_APIXC_RET_FAIL;
734 }
735
736 stXC_SET_CUSTOMIZE_FRC_TABLE XCArgs;
737 XCArgs.stFRCTable = stFRCTable;
738 XCArgs.eReturnValue = E_APIXC_RET_FAIL;
739
740 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_CUSTOMIZE_FRC_TABLE, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
741 {
742 printf("Obtain XC engine fail\n");
743 return E_APIXC_RET_FAIL;
744 }
745 else
746 {
747 return XCArgs.eReturnValue;
748 }
749 }
750
751 //-------------------------------------------------------------------------------------------------
752 /// Register PQ Set FPLL thresh mode WR bank mapping function.
753 /// @param fpXCCB \b IN: function pointer of PQ set FPLL thresh mode WR bank mapping
754 //-------------------------------------------------------------------------------------------------
MApi_XC_RegisterPQSetFPLLThreshMode_U2(void * pInstance,void (* fpPQCB)(MS_U8 u8PQWin))755 void MApi_XC_RegisterPQSetFPLLThreshMode_U2(void* pInstance, void (*fpPQCB)(MS_U8 u8PQWin))
756 {
757 _fpPQSetFPLLThreshMode = fpPQCB;
758 }
759
MApi_XC_RegisterPQSetFPLLThreshMode(void (* fpPQCB)(MS_U8 u8PQWin))760 void MApi_XC_RegisterPQSetFPLLThreshMode(void (*fpPQCB)(MS_U8 u8PQWin))
761 {
762 if (pu32XCInst == NULL)
763 {
764 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
765 return;
766 }
767
768 stXC_SET_REGISTER_PQ_FPLL_THRESH_MODE XCArgs;
769 XCArgs.fpPQCB = fpPQCB;
770
771 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_REGISTER_PQ_FPLL_THRESH_MODE, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
772 {
773 printf("Obtain XC engine fail\n");
774 return;
775 }
776 else
777 {
778 return;
779 }
780 }
781
782 #ifdef ENABLE_SPREADMODE
_MApi_XC_FPLL_EnableSpreadMode(void * pInstance,EN_FPLL_SPREAD_MODE eSpreadMode)783 void _MApi_XC_FPLL_EnableSpreadMode(void *pInstance, EN_FPLL_SPREAD_MODE eSpreadMode)
784 {
785 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
786 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
787
788 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
789 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
790 if(eSpreadMode!=FPLL_SPREAD_MODE_NONE)
791 {
792 MS_U32 u32Spreadmodetemp=0;
793 MS_U8 u8FrameIndiv=0;
794 MS_U8 u8FrameOutdiv=0;
795
796 if(eSpreadMode==FPLL_SPREAD_MODE_1_2)
797 {
798 u8FrameIndiv=1;
799 u8FrameOutdiv=2;
800 }
801 else if(eSpreadMode==FPLL_SPREAD_MODE_2_5)
802 {
803 u8FrameIndiv=2;
804 u8FrameOutdiv=5;
805 }
806 else if(eSpreadMode==FPLL_SPREAD_MODE_3_5)
807 {
808 u8FrameIndiv=3;
809 u8FrameOutdiv=5;
810 }
811 else if(eSpreadMode==FPLL_SPREAD_MODE_4_5)
812 {
813 u8FrameIndiv=4;
814 u8FrameOutdiv=5;
815 }
816 else if(eSpreadMode==FPLL_SPREAD_MODE_5_6)
817 {
818 u8FrameIndiv=5;
819 u8FrameOutdiv=6;
820 }
821 else if(eSpreadMode==FPLL_SPREAD_MODE_5_12)
822 {
823 u8FrameIndiv=5;
824 u8FrameOutdiv=12;
825 }
826 else if(eSpreadMode==FPLL_SPREAD_MODE_12_25)
827 {
828 u8FrameIndiv=12;
829 u8FrameOutdiv=25;
830 }
831 else if(eSpreadMode==FPLL_SPREAD_MODE_24_25)
832 {
833 u8FrameIndiv=24;
834 u8FrameOutdiv=25;
835 }
836
837 MsOS_DelayTask(50);
838 u32Spreadmodetemp= (SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_28_L) + 1) * (SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_1F_L)) * u8FrameIndiv / u8FrameOutdiv ;
839 W2BYTEMSK(L_BK_LPLL(0x7E), BIT(15), BIT(15)); //open sprend mode
840 W2BYTEMSK(L_BK_LPLL(0x7A), u8FrameOutdiv-1 , 0x00FF);
841 W2BYTEMSK(L_BK_LPLL(0x19), u32Spreadmodetemp, 0xFFFF);
842 W2BYTEMSK(L_BK_LPLL(0x1A), u32Spreadmodetemp>>16, 0xFFFF);
843 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "SpreadMode: u8FrameIndiv = %d, u8FrameOutdiv = %d\n",u8FrameIndiv,u8FrameOutdiv);
844 pXCResourcePrivate->stdrvXC_MVideo_Context.g_bSpreandEnable=TRUE;
845
846 }
847 else
848 {
849 W2BYTEMSK(L_BK_LPLL(0x7E), 0 , BIT(15)); //close sprend mode
850 W2BYTEMSK(L_BK_LPLL(0x7A), 0, 0x00FF);
851 W2BYTEMSK(L_BK_LPLL(0x19), 0, 0xFFFF);
852 W2BYTEMSK(L_BK_LPLL(0x1A), 0, 0xFFFF);
853 pXCResourcePrivate->stdrvXC_MVideo_Context.g_bSpreandEnable=FALSE;
854 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "Close spread mode\n");
855 }
856
857 }
858 #endif
859
860
MDrv_SC_Cal_FRC_Output_Vfreq(void * pInstance,MS_U16 u16InputVFreq,MS_U16 u16DefaultVFreq,MS_BOOL bFBL,MS_U8 * u8FrcIn,MS_U8 * u8FrcOut,MS_BOOL * bSetFrameLock,MS_U8 u8Lpll_bank,SCALER_WIN eWindow)861 MS_U16 MDrv_SC_Cal_FRC_Output_Vfreq(void *pInstance, MS_U16 u16InputVFreq,
862 MS_U16 u16DefaultVFreq,
863 MS_BOOL bFBL,
864 MS_U8 *u8FrcIn,
865 MS_U8 *u8FrcOut,
866 MS_BOOL *bSetFrameLock,
867 MS_U8 u8Lpll_bank,
868 SCALER_WIN eWindow)
869 {
870 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
871 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
872 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
873 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
874 MS_U16 u16OutputVFreq = u16InputVFreq;
875 #ifndef DISABLE_3D_FUNCTION
876 MS_BOOL bIsOutput48hz = (!pXCResourcePrivate->stdrvXC_Display._bUseCustomFRCTable) && MDrv_SC_3D_IsOutputVfreq48hz(pInstance, eWindow, u16InputVFreq);
877 #else
878 MS_BOOL bIsOutput48hz = FALSE;
879 #endif
880 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING,"u16DefaultVFreq = %d, u16InputVFreq =%d\n",
881 u16DefaultVFreq, u16InputVFreq);
882
883 MDrv_SC_Handle_Special_FRCTbl(pInstance, u16DefaultVFreq, u16InputVFreq, eWindow);
884
885 if (!bFBL)
886 {
887 MS_U16 u16FRCType=0;
888 for(u16FRCType = 0; u16FRCType < (sizeof(pXCResourcePrivate->stdrvXC_Display.sFRC_Tbl)/sizeof(SC_FRC_SETTING)); u16FRCType++)
889 {
890 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING,
891 "InputV = %d, Tbl[%d] = (%d, %d)(%d, %d)\n", u16InputVFreq, u16FRCType,
892 pXCResourcePrivate->stdrvXC_Display.sFRC_Tbl[u16FRCType].u16LowerBound,
893 pXCResourcePrivate->stdrvXC_Display.sFRC_Tbl[u16FRCType].u16HigherBound,
894 pXCResourcePrivate->stdrvXC_Display.sFRC_Tbl[u16FRCType].u8FRC_In,
895 pXCResourcePrivate->stdrvXC_Display.sFRC_Tbl[u16FRCType].u8FRC_Out) ;
896
897 // check FRC
898 if((u16InputVFreq > pXCResourcePrivate->stdrvXC_Display.sFRC_Tbl[u16FRCType].u16LowerBound) &&
899 (u16InputVFreq <= pXCResourcePrivate->stdrvXC_Display.sFRC_Tbl[u16FRCType].u16HigherBound))
900 {
901 break;
902 }
903 }
904
905 MS_ASSERT(u16FRCType <= sizeof(pXCResourcePrivate->stdrvXC_Display.sFRC_Tbl)/sizeof(SC_FRC_SETTING));
906
907 if(u16FRCType >= (sizeof(pXCResourcePrivate->stdrvXC_Display.sFRC_Tbl)/sizeof(SC_FRC_SETTING)))
908 {
909 u16FRCType = (sizeof(pXCResourcePrivate->stdrvXC_Display.sFRC_Tbl)/sizeof(SC_FRC_SETTING))-1;
910 }
911
912 // Add this condition to avoid the divider is 0
913 if(pXCResourcePrivate->stdrvXC_Display.sFRC_Tbl[u16FRCType].u8FRC_In == 0)
914 {
915 pXCResourcePrivate->stdrvXC_Display.sFRC_Tbl[u16FRCType].u8FRC_In = 1;
916 }
917
918 // Set output V
919 if(u16FRCType < sizeof(pXCResourcePrivate->stdrvXC_Display.sFRC_Tbl)/sizeof(SC_FRC_SETTING))
920 {
921 u16OutputVFreq = u16InputVFreq * pXCResourcePrivate->stdrvXC_Display.sFRC_Tbl[u16FRCType].u8FRC_Out
922 / pXCResourcePrivate->stdrvXC_Display.sFRC_Tbl[u16FRCType].u8FRC_In;
923
924 *u8FrcIn = pXCResourcePrivate->stdrvXC_Display.sFRC_Tbl[u16FRCType].u8FRC_In;
925 *u8FrcOut = pXCResourcePrivate->stdrvXC_Display.sFRC_Tbl[u16FRCType].u8FRC_Out;
926
927 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "u16DefaultVFreq=%d,u8FrcOut = %d, u16OutputVFreq = %d\n", u16DefaultVFreq, *u8FrcOut, u16OutputVFreq) ;
928
929 /// for Default Vfreq = 100/120Hz
930 if((u16DefaultVFreq > 900)&&(u16DefaultVFreq < 1100))
931 {
932 if(u16OutputVFreq > 1100)
933 {
934 u16OutputVFreq/=2;
935 *u8FrcOut/=2;
936 }
937 }
938 else if((u16DefaultVFreq > 1100)&&(u16DefaultVFreq < 1300))
939 {
940 if(u16OutputVFreq > 1300)
941 {
942 u16OutputVFreq/=2;
943 *u8FrcOut/=2;
944 }
945 }
946 }
947 else
948 {
949 u16OutputVFreq = 0;
950 *u8FrcIn = 1;
951 *u8FrcOut = 1;
952 }
953 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "u16DefaultVFreq=%d,u8FrcOut = %d, u16OutputVFreq = %d\n", u16DefaultVFreq, *u8FrcOut, u16OutputVFreq) ;
954
955 #if FRC_INSIDE
956 // For 4K2K 2nd FRC used!!!
957 if ((1 == u8Lpll_bank) &&
958 (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HTotal> 3000) &&
959 (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VTotal > 2000) &&
960 (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq > 500))
961 {
962 if (pXCResourcePrivate->stdrvXC_MVideo_Context.enFRC_CurrentInputTiming == E_XC_FRC_InputTiming_4K2K)
963 {
964 if (u16InputVFreq >= 320)
965 {
966 u16OutputVFreq = u16InputVFreq/2;
967 *u8FrcIn = 2;
968 *u8FrcOut = 1;
969 }
970 else
971 {
972 u16OutputVFreq = u16InputVFreq;
973 *u8FrcIn = 1;
974 *u8FrcOut = 1;
975 }
976 }
977
978 }
979 #endif
980 }
981 else
982 {
983 *u8FrcIn = 1;
984 *u8FrcOut = 1;
985 }
986
987 LPLL_BK_STORE;
988 if(u8Lpll_bank)
989 LPLL_BK_SWITCH(0x01);
990 else
991 LPLL_BK_SWITCH(0x00);
992
993 // 4K1K FRC 120Hz output case
994 if ((pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_FRC_INSIDE_4K1K_120HZ) && (0 == u8Lpll_bank))
995 {
996 if ((u16InputVFreq >= 235) && (u16InputVFreq <= 245))
997 {
998 *u8FrcIn = 1;
999 *u8FrcOut = 5;
1000 }
1001 else
1002 {
1003 *u8FrcOut = *u8FrcOut*2;
1004 }
1005 }
1006
1007 // 60->120 or 50->100
1008 if((u16DefaultVFreq == 1200)||(u16DefaultVFreq == 1000))
1009 {
1010 if(((u16InputVFreq >= 1180) && (u16InputVFreq <= 1220))||
1011 ((u16InputVFreq >= 980) && (u16InputVFreq <= 1020)))
1012 {
1013 if(bIsOutput48hz)
1014 {
1015 *u8FrcIn = 1;
1016 *u8FrcOut = 5;
1017 }
1018 else
1019 {
1020 *u8FrcIn = 1;
1021 *u8FrcOut = 2;
1022 }
1023 }
1024
1025 }
1026
1027 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_FRC_INSIDE_4K_HALFK_240HZ)
1028 {
1029 // Napoli 4K 0.5K FRC 240Hz output case
1030 if (0 == u8Lpll_bank)
1031 *u8FrcOut = *u8FrcOut*4;
1032
1033 }
1034 #if (HW_DESIGN_4K2K_VER != 6) // for manhattan, only 1 LPLL
1035 #ifndef DISABLE_3D_FUNCTION
1036 else if((pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.bFRC)
1037 &&((u16DefaultVFreq == 600)||(u16DefaultVFreq == 500))
1038 &&(MDrv_XC_Get_3D_Output_Mode(pInstance) == E_XC_3D_OUTPUT_FRAME_ALTERNATIVE))
1039 {
1040 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_FRC_INSIDE_240HZ)
1041 {
1042 if(bIsOutput48hz)
1043 {
1044 *u8FrcIn = 1;
1045 *u8FrcOut = 2;
1046 }
1047 }
1048 else
1049 {
1050 *u8FrcIn = 1;
1051 *u8FrcOut = 2;
1052 }
1053 }
1054 #endif
1055 #endif
1056 #ifdef FA_1920X540_OUTPUT
1057 else
1058 if((!pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.bFRC)&&
1059 ((MDrv_XC_Get_3D_Input_Mode(pInstance, MAIN_WINDOW) == E_XC_3D_INPUT_SIDE_BY_SIDE_HALF)||
1060 (MDrv_XC_Get_3D_Input_Mode(pInstance, MAIN_WINDOW) == E_XC_3D_INPUT_TOP_BOTTOM)||
1061 (MDrv_XC_Get_3D_Input_Mode(pInstance, MAIN_WINDOW) == E_XC_3D_INPUT_FIELD_ALTERNATIVE))&&
1062 (MDrv_XC_Get_3D_Output_Mode(pInstance) == E_XC_3D_OUTPUT_FRAME_ALTERNATIVE))
1063 {
1064 *u8FrcIn = 1;
1065 *u8FrcOut = 2;
1066 }
1067 #endif
1068 #ifdef TBP_1920X2160_OUTPUT
1069 else if((!pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.bFRC)&&
1070 ((gSrcInfo[MAIN_WINDOW].stCapWin.height == DOUBLEHD_1080X2P_VSIZE)||
1071 (gSrcInfo[MAIN_WINDOW].stCapWin.height == DOUBLEHD_1080X2I_VSIZE))&&
1072 (MDrv_XC_Get_3D_Input_Mode(pInstance, MAIN_WINDOW) == E_XC_3D_INPUT_FRAME_PACKING)&&
1073 (MDrv_XC_Get_3D_Output_Mode(pInstance) == E_XC_3D_OUTPUT_TOP_BOTTOM))
1074 {
1075 *u8FrcIn = 1;
1076 *u8FrcOut = 1;
1077 }
1078 #endif
1079 #if (HW_DESIGN_4K2K_VER == 6) // for maserati 4K2K@120Hz case
1080 else if((pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.bFRC)
1081 && IsVBY1_16LANE((MS_U8)(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type)))
1082 {
1083 *u8FrcOut = *u8FrcOut*2;
1084 }
1085 #endif
1086
1087 if((pXCResourcePrivate->stdrvXC_Display._bForceFreerun)
1088 &&(pXCResourcePrivate->stdrvXC_Display._ForceVFreq == VFREQ_FROM_SRC))
1089 {
1090 if((u16DefaultVFreq == 300) &&
1091 (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HTotal> 3000) &&
1092 (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VTotal > 2000))
1093 {
1094 *u8FrcIn = 2;
1095 *u8FrcOut = 1;
1096 }
1097 else
1098 {
1099 *u8FrcIn = 1;
1100 *u8FrcOut = 1;
1101 }
1102 }
1103 pXCResourcePrivate->stdrvXC_Display.g_u8FrcIn = *u8FrcIn;
1104 pXCResourcePrivate->stdrvXC_Display.g_u8FrcOut = *u8FrcOut;
1105 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "u16DefaultVFreq=%d,Final u8FrcIn = %d,u8FrcOut = %d, u16OutputVFreq = %d\n", u16DefaultVFreq, *u8FrcIn,*u8FrcOut, u16OutputVFreq) ;
1106 #ifdef ENABLE_SPREADMODE
1107 if(MHal_XC_IsSupportSpreadMode(pInstance))
1108 {
1109 if(!(MDrv_XC_FPLL_IsSupportLockFreqOnly(pInstance))
1110 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6)) // for maserati 4K2K@120Hz case, not use spread mode
1111 && !((pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.bFRC)
1112 && IsVBY1_16LANE((MS_U8)(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type)))
1113 #endif
1114 )
1115 {
1116 if((*u8FrcIn==1) && (*u8FrcOut==2))
1117 {
1118 _MApi_XC_FPLL_EnableSpreadMode(pInstance,FPLL_SPREAD_MODE_1_2);
1119 }
1120 else if((*u8FrcIn==2) && (*u8FrcOut==5))
1121 {
1122 _MApi_XC_FPLL_EnableSpreadMode(pInstance,FPLL_SPREAD_MODE_2_5);
1123 }
1124 else if((*u8FrcIn==3) && (*u8FrcOut==5))
1125 {
1126 _MApi_XC_FPLL_EnableSpreadMode(pInstance,FPLL_SPREAD_MODE_3_5);
1127 }
1128 else if((*u8FrcIn==4) && (*u8FrcOut==5))
1129 {
1130 _MApi_XC_FPLL_EnableSpreadMode(pInstance,FPLL_SPREAD_MODE_4_5);
1131 }
1132 else if((*u8FrcIn==5) && (*u8FrcOut==6))
1133 {
1134 // 5:6 case have not implement
1135 // _MApi_XC_FPLL_EnableSpreadMode(pInstance,FPLL_SPREAD_MODE_5_6);
1136 _MApi_XC_FPLL_EnableSpreadMode(pInstance,FPLL_SPREAD_MODE_NONE);
1137 }
1138 else if((*u8FrcIn==5) && (*u8FrcOut==12))
1139 {
1140 _MApi_XC_FPLL_EnableSpreadMode(pInstance,FPLL_SPREAD_MODE_5_12); //2
1141 }
1142 else if((*u8FrcIn==12) && (*u8FrcOut==25))
1143 {
1144 _MApi_XC_FPLL_EnableSpreadMode(pInstance,FPLL_SPREAD_MODE_12_25); //2
1145 }
1146 else if((*u8FrcIn==24) && (*u8FrcOut==25))
1147 {
1148 _MApi_XC_FPLL_EnableSpreadMode(pInstance,FPLL_SPREAD_MODE_24_25);
1149 }
1150 else
1151 {
1152 _MApi_XC_FPLL_EnableSpreadMode(pInstance,FPLL_SPREAD_MODE_NONE); //close spread mode for other source
1153 }
1154
1155 }
1156 else
1157 {
1158 _MApi_XC_FPLL_EnableSpreadMode(pInstance,FPLL_SPREAD_MODE_NONE); //close spread mode for lockFreqOnlymod
1159 }
1160 }
1161 #endif
1162
1163 //extend frc bit for lpll 0
1164 if(u8Lpll_bank == 0)
1165 {
1166 MS_U8 u8FrcOutTmp = *u8FrcOut;
1167 #ifdef ENABLE_SPREADMODE
1168 if(MHal_XC_IsSupportSpreadMode(pInstance))
1169 {
1170 // 5:6 case have not implement
1171 if (!(MDrv_XC_FPLL_IsSupportLockFreqOnly(pInstance)) && (((*u8FrcIn==1) && (*u8FrcOut==2)) || ((*u8FrcIn==2) && (*u8FrcOut==5)) || ((*u8FrcIn==3) && (*u8FrcOut==5))|| ((*u8FrcIn==4) && (*u8FrcOut==5))/*|| ((*u8FrcIn==5) && (*u8FrcOut==6))*/|| ((*u8FrcIn==5) && (*u8FrcOut==12))|| ((*u8FrcIn==12) && (*u8FrcOut==25))|| ((*u8FrcIn==24) && (*u8FrcOut==25)))
1172 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6)) // for maserati 4K2K@120Hz case, not use spread mode
1173 && !((pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.bFRC)
1174 && IsVBY1_16LANE((MS_U8)(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type)))
1175 #endif
1176 )
1177 {
1178 u8FrcOutTmp=1;
1179 }
1180 }
1181 #endif
1182 #ifdef SUPPORT_FPLL_DOUBLE_OVS
1183 // for muji U02, 4K 0.5K@240Hz case, there is new bit 0x3C[11] to control from 5:24 to 5:48
1184 if (MDrv_ReadByte(REG_CHIP_REVISION) >= 1)
1185 {
1186 if(u8FrcOutTmp > 32)
1187 {
1188 u8FrcOutTmp = u8FrcOutTmp/2;
1189 MDrv_Write2ByteMask(L_BK_LPLL(0x3C), 0, BIT(11));
1190 }
1191 else
1192 {
1193 MDrv_Write2ByteMask(L_BK_LPLL(0x3C), BIT(11), BIT(11));
1194 }
1195 }
1196 #endif
1197 MDrv_WriteByte(H_BK_LPLL(0x0C), (((u8FrcOutTmp-1)&0xF) << 4) | ((*u8FrcIn-1)&0xF));
1198 MDrv_WriteByte(L_BK_LPLL(0x0E), (((u8FrcOutTmp-1)>>4) << 4) | ((*u8FrcIn-1)>>4));
1199 }
1200 else
1201 {
1202 MDrv_WriteByte(H_BK_LPLL(0x0C), ((*u8FrcOut-1) << 4) | (*u8FrcIn-1));
1203 }
1204 LPLL_BK_RESTORE;
1205
1206 //for force case
1207 if (pXCResourcePrivate->stdrvXC_Display._bForceFreerun)
1208 {
1209 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "force free run\n") ;
1210 if(pXCResourcePrivate->stdrvXC_Display._ForceVFreq == VFREQ_FROM_SRC)
1211 u16OutputVFreq = MDrv_SC_VFreq_Select(pInstance, u16InputVFreq);
1212 else
1213 u16OutputVFreq = MDrv_SC_VFreq_Select(pInstance, u16OutputVFreq);
1214
1215 MDrv_WriteByte(H_BK_LPLL(0x0C), 0x00); //clear FRC before set freerun (fps_in:fps_out = 1:1)
1216 MDrv_WriteByte(L_BK_LPLL(0x0E), 0x00);
1217
1218 *bSetFrameLock = FALSE;
1219 }
1220 //for normal case
1221 else if (_MDrv_SC_IsOutVFreValid(pInstance, u16OutputVFreq, 10)
1222 #if (HW_DESIGN_3D_VER == 4)
1223 // for FRC FPP-FA 1280x1470@60/SBSH-FA/TBP-FA
1224 // for FRC FPP-FA 1280x1470@50/SBSH-FA/TBP-FA
1225 ||((((u16OutputVFreq >= 1180) && (u16OutputVFreq <= 1220))
1226 ||((u16OutputVFreq >= 980) && (u16OutputVFreq <= 1020))
1227 ||((u16OutputVFreq >= 2380) && (u16OutputVFreq <= 2420)))
1228 && ((u16DefaultVFreq == 600)||(u16DefaultVFreq == 500))
1229 && (MDrv_XC_Get_3D_Output_Mode(pInstance) == E_XC_3D_OUTPUT_FRAME_ALTERNATIVE))
1230 || ((u16OutputVFreq >= 1980) && (u16OutputVFreq <= 2020))
1231 || ((u16OutputVFreq >= 2380) && (u16OutputVFreq <= 2420))
1232
1233 #endif
1234 || ((pXCResourcePrivate->stdrvXC_Display._bUseCustomFRCTable)
1235 && _MDrv_SC_IsOutVFreValid(pInstance, u16OutputVFreq, 25))
1236 || (bIsOutput48hz && (u16OutputVFreq >= 460) && (u16OutputVFreq <= 490))
1237 // For 4K2K 2nd FRC used!!
1238 || ((u16DefaultVFreq == 300)
1239 && (1 == u8Lpll_bank)
1240 && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HTotal> 3000)
1241 && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VTotal > 2000)
1242 && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq > 500)
1243 && (((u16OutputVFreq >= 490) && (u16OutputVFreq <= 510)) ||
1244 ((u16OutputVFreq >= 590) && (u16OutputVFreq <= 610)) ||
1245 ((u16OutputVFreq >= 290) && (u16OutputVFreq <= 310)) ||
1246 ((u16OutputVFreq >= 230) && (u16OutputVFreq <= 260))))
1247 // For Muji 4K 0.5K case
1248 || ((((u16OutputVFreq >= 1980) && (u16OutputVFreq <= 2020))||
1249 ((u16OutputVFreq >= 2380) && (u16OutputVFreq <= 2420)))&&
1250 ((u16DefaultVFreq == 2000)||(u16DefaultVFreq == 2400))))
1251 {
1252 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "Frame Lock = True\n");
1253 //u16OutputVFreq = _MDrv_SC_RefineVFreq(MAIN_WINDOW, u16InputVFreq, u16OutputVFreq);
1254 *bSetFrameLock = TRUE;
1255 }
1256 //abnormal case
1257 else
1258 {
1259 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "Free Run\n");
1260 // For FRC panel and freerun at specific framerate
1261 if(u16DefaultVFreq > 900)
1262 {
1263 u16OutputVFreq = 1200;
1264 }
1265 else if(((u16OutputVFreq >= 480) && (u16OutputVFreq < 490))
1266 || ((u16OutputVFreq > 510) && (u16OutputVFreq <= 520)))
1267 {
1268 u16OutputVFreq = 500; //for better quality
1269 }
1270 else
1271 {
1272 // Free run at panel default timing.
1273 u16OutputVFreq = u16DefaultVFreq;
1274 }
1275 *bSetFrameLock = FALSE;
1276 }
1277
1278 #if (HW_DESIGN_HDMITX_VER == 1 || HW_DESIGN_HDMITX_VER == 2)
1279 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_B & E_XC_INIT_MISC_B_HDMITX_ENABLE)
1280 {
1281 if(u16OutputVFreq >= 595 && u16OutputVFreq < 605)
1282 u16OutputVFreq = 600;
1283 else if(u16OutputVFreq >= 495 && u16OutputVFreq < 505)
1284 u16OutputVFreq = 500;
1285 else if(u16OutputVFreq >= 295 && u16OutputVFreq < 305)
1286 u16OutputVFreq = 300;
1287 else if(u16OutputVFreq >= 245 && u16OutputVFreq < 255)
1288 u16OutputVFreq = 250;
1289 else if(u16OutputVFreq >= 235 && u16OutputVFreq < 245)
1290 u16OutputVFreq = 240;
1291 }
1292 #endif
1293
1294 return u16OutputVFreq;
1295 }
1296
1297
1298 //-----------------------------------------------------------------------------
1299 // LPLL
1300 //-----------------------------------------------------------------------------
MDrv_SC_set_fpll(void * pInstance,MS_BOOL bEnable,MS_BOOL bEnablePhaseLock,MS_U8 u8Lpll_bank)1301 void MDrv_SC_set_fpll(void *pInstance, MS_BOOL bEnable, MS_BOOL bEnablePhaseLock, MS_U8 u8Lpll_bank)
1302 {
1303 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
1304 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
1305 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
1306 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
1307
1308 MS_U32 u32OrigLPLL = 0;
1309 #if(!PHASE_LOCK_EN)
1310 bEnablePhaseLock = 0;
1311 #endif
1312 // store bank
1313 LPLL_BK_STORE;
1314 // switch bank
1315 if(u8Lpll_bank)
1316 LPLL_BK_SWITCH(0x01);
1317 else
1318 LPLL_BK_SWITCH(0x00);
1319
1320 u32OrigLPLL = MDrv_Read4Byte(L_BK_LPLL(0x0F));
1321
1322 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "MDrv_SC_set_fpll(%u,%u)\n", bEnable, bEnablePhaseLock) ;
1323 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "u32OrigLPLL = %tx\n", (ptrdiff_t)u32OrigLPLL) ;
1324
1325 if(bEnable)
1326 {
1327 MDrv_Write2ByteMask(L_BK_LPLL(0x0C), BIT(3), BIT(3));
1328 if(u8Lpll_bank==1)
1329 {
1330 //printf("1111\n\n");
1331 MDrv_Write2ByteMask(L_BK_LPLL(0x7F), 0x00, BIT(8));
1332 }
1333 }
1334 else
1335 {
1336 if(u8Lpll_bank==1)
1337 {
1338 //printf("2222\n\n");
1339 MDrv_Write2ByteMask(L_BK_LPLL(0x7F), BIT(8), BIT(8));
1340 }
1341 MDrv_Write2ByteMask(L_BK_LPLL(0x0C), 0x00, BIT(3));
1342 }
1343 MDrv_Write2ByteMask(L_BK_LPLL(0x0C), bEnablePhaseLock << 6, BIT(6));
1344
1345 #if (HW_DESIGN_HDMITX_VER == 1 || HW_DESIGN_HDMITX_VER == 2) //for Maxim HDMITX and Maserati + Raptor, to make u32OrigLPLL change smoothly
1346 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_B & E_XC_INIT_MISC_B_HDMITX_ENABLE)
1347 {
1348 MS_U32 u32CurrentLockLPLL = MDrv_Read4Byte(L_BK_LPLL(0x28));
1349 MDrv_Write3Byte(L_BK_LPLL(0x0F), u32CurrentLockLPLL);
1350 while(abs(u32OrigLPLL - u32CurrentLockLPLL) > FPLL_STEP_LIMIT_FOR_ADJUST_SET)
1351 {
1352 if(u32CurrentLockLPLL > u32OrigLPLL)
1353 {
1354 u32CurrentLockLPLL -= FPLL_STEP_LIMIT_FOR_ADJUST_SET;
1355 }
1356 else
1357 {
1358 u32CurrentLockLPLL += FPLL_STEP_LIMIT_FOR_ADJUST_SET;
1359 }
1360 MsOS_DelayTask(1);
1361 MDrv_Write3Byte(L_BK_LPLL(0x0F), u32CurrentLockLPLL);
1362 }
1363 }
1364 #endif
1365
1366 // !!Initial set have to re-update again to force LPLL free run at initial state or
1367 // lock from initial set!!
1368 MDrv_Write3Byte(L_BK_LPLL(0x0F), u32OrigLPLL);
1369 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "u32OrigLPLL = %tx, L_BK_LPLL(0x0F) = %tx\n", (ptrdiff_t)u32OrigLPLL, (ptrdiff_t)MDrv_Read4Byte(L_BK_LPLL(0x0F))) ;
1370
1371 #if LOCK_FREQ_ONLY_WITHOUT_LOCK_PHASE
1372 if(u8Lpll_bank == 0)
1373 {
1374 MS_BOOL bLockEn = FALSE;
1375 if(MDrv_XC_FPLL_IsSupportLockFreqOnly(pInstance) == TRUE)
1376 bLockEn = bEnable;
1377 if(bLockEn && (!IsSrcTypeDigitalVD(gSrcInfo[MAIN_WINDOW].enInputSourceType)))
1378 {
1379 bLockEn = TRUE;
1380 }
1381 else
1382 {
1383 bLockEn = FALSE;
1384 }
1385 _MApi_XC_FPLL_EnableLcokFreqOnly(pInstance,bLockEn);
1386 }
1387 #endif
1388
1389 // restore bank
1390 LPLL_BK_RESTORE;
1391
1392
1393 }
1394
MDrv_SC_clear_lpll(void * pInstance)1395 void MDrv_SC_clear_lpll(void *pInstance)
1396 {
1397 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
1398 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
1399 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_0F_L, 0x40, BIT(6));
1400 }
1401
MDrv_SC_monitor_lpll(void * pInstance)1402 void MDrv_SC_monitor_lpll(void *pInstance)
1403 {
1404 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
1405 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
1406 MS_U16 u16Tmp;
1407 //MS_U8 u8Bank;
1408
1409 u16Tmp = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_0F_L);
1410
1411 if (u16Tmp & BIT(6))
1412 {
1413 //MDrv_WriteByte(L_BK_IP1F2(0x0F), u8Tmp & ~(BIT(6)));
1414 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_0F_L, u16Tmp & ~(BIT(6)));
1415 }
1416
1417 }
1418
MDrv_SC_adjust_output_htt_vtt(MS_U16 * u16Htt,MS_U16 * u16Vtt,MS_U32 u32HighAccurateInputVFreq,MS_U16 u16DefaultHtt,MS_U16 u16DefaultVtt,MS_U16 u16DefaultVFreq,MS_BOOL bChangeVtt)1419 static void MDrv_SC_adjust_output_htt_vtt(MS_U16 *u16Htt, MS_U16 *u16Vtt,
1420 MS_U32 u32HighAccurateInputVFreq,
1421 MS_U16 u16DefaultHtt,
1422 MS_U16 u16DefaultVtt,
1423 MS_U16 u16DefaultVFreq,
1424 MS_BOOL bChangeVtt)
1425 {
1426 MS_U64 u64DCLK;
1427 u64DCLK = ((MS_U64)u16DefaultHtt) * u16DefaultVtt * u16DefaultVFreq;///10;
1428 do_div(u64DCLK,10);
1429 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING,
1430 "default Htt=%u, Vtt=%u, VFreq=%u, dclk=%u\n",
1431 u16DefaultHtt,
1432 u16DefaultVtt,
1433 u16DefaultVFreq, (unsigned int)u64DCLK);
1434
1435 if(u32HighAccurateInputVFreq == 0)
1436 {
1437 return;
1438 }
1439 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "1.Htt=%u, Vtt=%u, VFreq=%u, dclk=%u\n",
1440 *u16Htt, *u16Vtt, (unsigned int)(u32HighAccurateInputVFreq/100) ,(unsigned int)(((MS_U32)(*u16Htt)) * (*u16Vtt) * (u32HighAccurateInputVFreq/100)/10));
1441
1442 if ((u32HighAccurateInputVFreq/100) != u16DefaultVFreq)
1443 {
1444 if (bChangeVtt)
1445 {
1446 u64DCLK = u64DCLK*10 + (u32HighAccurateInputVFreq * (*u16Htt)/100)/2;
1447 do_div(u64DCLK,(u32HighAccurateInputVFreq * (*u16Htt)/100));
1448 //*u16Vtt = (u64DCLK*10 + (u16VFreq * (*u16Htt))/2) / (u16VFreq * (*u16Htt));
1449 *u16Vtt = (MS_U16)u64DCLK;
1450 }
1451 else
1452 {
1453 u64DCLK = u64DCLK*10 + (u32HighAccurateInputVFreq * (*u16Vtt)/100)/2;
1454 do_div(u64DCLK,(u32HighAccurateInputVFreq * (*u16Vtt)/100));
1455 *u16Htt = (MS_U16)u64DCLK;
1456 //*u16Htt = (u64DCLK*10 + (u32HighAccurateInputVFreq * (*u16Vtt)/100)/2) / (u32HighAccurateInputVFreq * (*u16Vtt)/100);
1457 }
1458 }
1459
1460 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "2.Adjusted Htt=%u, Vtt=%u, VFreq=%u, dclk=%u\n",
1461 *u16Htt, *u16Vtt, (unsigned int)(u32HighAccurateInputVFreq/100), (unsigned int)(((MS_U32)(*u16Htt)) * (*u16Vtt) * (u32HighAccurateInputVFreq/100)/10));
1462
1463 }
1464
MDrv_SC_set_fastlpll(void * pInstance,MS_BOOL bEn)1465 void MDrv_SC_set_fastlpll(void *pInstance, MS_BOOL bEn)
1466 {
1467 MDrv_WriteRegBit(H_BK_LPLL(0x1E), bEn, 0x20); //Enable/Disable Fast LPLL
1468 }
1469
MDrv_SC_get_fastlpll(void * pInstance)1470 MS_BOOL MDrv_SC_get_fastlpll(void *pInstance)
1471 {
1472 return MDrv_ReadRegBit(H_BK_LPLL(0x1E), 0x20); //Enable/Disable FBL
1473 }
MApi_XC_SetOutputAdjustSetting_U2(void * pInstance,XC_OUTPUT_TIMING_ADJUST_SETTING * stAdjSetting)1474 E_APIXC_ReturnValue MApi_XC_SetOutputAdjustSetting_U2(void* pInstance, XC_OUTPUT_TIMING_ADJUST_SETTING *stAdjSetting)
1475 {
1476 XC_PANEL_INFO_EX stPanelInfoEx;
1477 if (stAdjSetting==NULL)
1478 {
1479 return E_APIXC_RET_FAIL;
1480 }
1481
1482 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
1483 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
1484
1485 memset(&stPanelInfoEx, 0, sizeof(XC_PANEL_INFO_EX));
1486 stPanelInfoEx.bVttDelayValid = TRUE;
1487 stPanelInfoEx.u16HttDelay = stAdjSetting->u16VTotal_Delay;
1488 stPanelInfoEx.bVttStepsValid = TRUE;
1489 stPanelInfoEx.u16HttSteps = stAdjSetting->u16VTotal_Step;
1490 stPanelInfoEx.bHttDelayValid = TRUE;
1491 stPanelInfoEx.u16VttDelay = stAdjSetting->u16HTotal_Delay;
1492 stPanelInfoEx.bHttStepsValid = TRUE;
1493 stPanelInfoEx.u16VttSteps= stAdjSetting->u16HTotal_Step;
1494 stPanelInfoEx.bDclkDelayValid = TRUE;
1495 stPanelInfoEx.u16DclkDelay = stAdjSetting->u16Dclk_Delay;
1496 stPanelInfoEx.bDclkStepsValid = TRUE;
1497 stPanelInfoEx.u16DclkSteps= stAdjSetting->u16Dclk_Step;
1498 stPanelInfoEx.u32PanelInfoEx_Version = PANEL_INFO_EX_VERSION;
1499 stPanelInfoEx.u16PanelInfoEX_Length = sizeof(XC_PANEL_INFO_EX);
1500 //Step setting for change to 50hz
1501 stPanelInfoEx.u16VFreq = 500;
1502 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
1503 if(MDrv_XC_SetExPanelInfo(pInstance, TRUE, &stPanelInfoEx) == FALSE)
1504 {
1505 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
1506 return E_APIXC_RET_FAIL;
1507 }
1508 //Step setting for change to 60hz
1509 stPanelInfoEx.u16VFreq = 600;
1510 if(MDrv_XC_SetExPanelInfo(pInstance, TRUE, &stPanelInfoEx) == FALSE)
1511 {
1512 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
1513 return E_APIXC_RET_FAIL;
1514 }
1515 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
1516 return E_APIXC_RET_OK;
1517 }
1518
MApi_XC_SetOutputAdjustSetting(XC_OUTPUT_TIMING_ADJUST_SETTING * stAdjSetting)1519 E_APIXC_ReturnValue MApi_XC_SetOutputAdjustSetting(XC_OUTPUT_TIMING_ADJUST_SETTING *stAdjSetting)
1520 {
1521 if (pu32XCInst == NULL)
1522 {
1523 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
1524 return E_APIXC_RET_FAIL;
1525 }
1526
1527 stXC_SET_OUTPUT_ADJUST_SETTING XCArgs;
1528 XCArgs.stAdjSetting = stAdjSetting;
1529 XCArgs.eReturnValue = E_APIXC_RET_FAIL;
1530
1531 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_OUTPUT_ADJUST_SETTING, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
1532 {
1533 printf("Obtain XC engine fail\n");
1534 return E_APIXC_RET_FAIL;
1535 }
1536 else
1537 {
1538 return XCArgs.eReturnValue;
1539 }
1540 }
1541
MApi_XC_Set_CustomerSyncInfo_U2(void * pInstance,MS_U16 u16FrontPorch,MS_U16 u16SyncWidth,MS_U16 u16OutputVfreq)1542 MS_BOOL MApi_XC_Set_CustomerSyncInfo_U2(void* pInstance, MS_U16 u16FrontPorch, MS_U16 u16SyncWidth, MS_U16 u16OutputVfreq)
1543 {
1544 XC_PANEL_INFO_EX stPanelInfoEx;
1545 MS_U16 u16Vtt;
1546 MS_BOOL bReturn = FALSE;
1547 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
1548 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
1549 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
1550
1551 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
1552 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
1553 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.enPnl_Out_Timing_Mode != E_XC_PNL_CHG_VTOTAL)
1554 {
1555 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
1556 return bReturn;
1557 }
1558 if(u16OutputVfreq == pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq)
1559 {
1560 u16Vtt = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VTotal;
1561 }
1562 else
1563 {
1564 u16Vtt = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VTotal*pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq/u16OutputVfreq;
1565 }
1566 memset(&stPanelInfoEx, 0, sizeof(XC_PANEL_INFO_EX));
1567 stPanelInfoEx.bVSyncBackPorchValid = TRUE;
1568 stPanelInfoEx.bVSyncWidthValid = TRUE;
1569 stPanelInfoEx.u16VSyncBackPorch = u16Vtt - pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height - u16FrontPorch - u16SyncWidth;
1570 stPanelInfoEx.u16VSyncWidth = u16SyncWidth;
1571 stPanelInfoEx.u16VFreq = u16OutputVfreq;
1572 stPanelInfoEx.u32PanelInfoEx_Version = PANEL_INFO_EX_VERSION;
1573 stPanelInfoEx.u16PanelInfoEX_Length = sizeof(XC_PANEL_INFO_EX);
1574
1575 bReturn = MDrv_XC_SetExPanelInfo(pInstance, TRUE, &stPanelInfoEx);
1576 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
1577 return bReturn;
1578 }
1579
MApi_XC_Set_CustomerSyncInfo(MS_U16 u16FrontPorch,MS_U16 u16SyncWidth,MS_U16 u16OutputVfreq)1580 MS_BOOL MApi_XC_Set_CustomerSyncInfo(MS_U16 u16FrontPorch, MS_U16 u16SyncWidth, MS_U16 u16OutputVfreq)
1581 {
1582 if (pu32XCInst == NULL)
1583 {
1584 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
1585 return FALSE;
1586 }
1587
1588 stXC_SET_CUSTOMER_SYNC_INFO XCArgs;
1589 XCArgs.u16FrontPorch = u16FrontPorch;
1590 XCArgs.u16SyncWidth = u16SyncWidth;
1591 XCArgs.u16OutputVfreq = u16OutputVfreq;
1592 XCArgs.bReturnValue = FALSE;
1593
1594 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_CUSTOMER_SYNC_INFO, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
1595 {
1596 printf("Obtain XC engine fail\n");
1597 return FALSE;
1598 }
1599 else
1600 {
1601 return XCArgs.bReturnValue;
1602 }
1603 }
1604
1605 /*
1606 Only for adjusting.
1607 E_XC_PNL_CHG_DCLK,
1608 E_XC_PNL_CHG_HTOTAL,
1609 E_XC_PNL_CHG_VTOTAL
1610 Adjust different type of output timing paramete base on Step/Delay and Ratio to u16Target_Value
1611 */
1612 #define MIN_STEP_VALUE 10
1613 #define MIN_DIFF_VALUE_FOR_STEPCHANGE 50
_MDrv_XC_SetHttVtt_Steply(void * pInstance,EN_OUTPUT_TIMING_ADJUST_MODE AdjustMode,MS_U16 u16Target_Value,MS_U16 u16UserStep,MS_U16 u16UserDelay)1614 static E_APIXC_ReturnValue _MDrv_XC_SetHttVtt_Steply(void *pInstance, EN_OUTPUT_TIMING_ADJUST_MODE AdjustMode,MS_U16 u16Target_Value,
1615 MS_U16 u16UserStep, MS_U16 u16UserDelay)
1616 {
1617 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
1618 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
1619 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
1620 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
1621 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
1622 //follow HW_DESIGN_4K2K_VER = 6 rule
1623 if (psXCInstPri->u32DeviceID != 0)
1624 {
1625 return E_APIXC_RET_OK;
1626 }
1627 #endif
1628 MS_U16 u16Step, u16Temp, u16Old_Value = 0;
1629 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "SetHttVtt Steply: Mode=%u, Value=%u, Step=%u, Delay=%u\n", AdjustMode, u16Target_Value, u16UserStep, u16UserDelay)
1630 if (u16UserStep > 1 && AdjustMode != EN_OUTPUT_TIMING_CHG_DCLK)
1631 {
1632 if (AdjustMode==EN_OUTPUT_TIMING_VTOTAL)
1633 {
1634 #if defined(PATCH_HW_VTT_LIMITATION)
1635 if(MDrv_ReadByte(REG_CHIP_REVISION) < HW_VTT_LIMITATION_CHIPREV)
1636 {
1637 u16Old_Value = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_36_L, VOP_VTT_MASK)+1;
1638 }
1639 else
1640 #endif
1641 {
1642 u16Old_Value = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0D_L)+1;
1643 }
1644 }
1645 else if (AdjustMode==EN_OUTPUT_TIMING_HTOTAL)
1646 {
1647 u16Old_Value = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0C_L)+1;
1648 }
1649 else
1650 {
1651 u16Old_Value = 0;
1652 }
1653 u16Temp = abs(u16Target_Value - u16Old_Value);
1654 u16Step = (u16Temp + u16UserStep - 1)/u16UserStep;
1655 if(u16Temp < MIN_DIFF_VALUE_FOR_STEPCHANGE)
1656 {
1657 //If the difference or stepvalue is too small, take it as one step to save time
1658 //Add this to prevent 60HZ FBL to 60HZ FB step change
1659 u16Step = u16Temp;
1660 u16UserStep = 1;
1661 }
1662 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "Step start from %u\n", u16Old_Value)
1663
1664 if ( u16Old_Value >= u16Target_Value )
1665 {
1666 while(u16Old_Value > u16Target_Value + u16Step)
1667 {
1668 u16Old_Value -= u16Step;
1669 if (AdjustMode==EN_OUTPUT_TIMING_VTOTAL)
1670 {
1671 if ((MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED) && (!MDrv_SC_GetForceWrite(E_PANEL_MUTE)) )
1672 {
1673 #if defined(PATCH_HW_VTT_LIMITATION)
1674 if(MDrv_ReadByte(REG_CHIP_REVISION) < HW_VTT_LIMITATION_CHIPREV)
1675 {
1676 _MLOAD_ENTRY(pInstance);
1677 MHal_XC_SetVopVttByBK68(pInstance, (u16Old_Value - 1)&VOP_VTT_MASK, 1);
1678 _MLOAD_RETURN(pInstance);
1679 MDrv_XC_WaitOutputVSync(pInstance, 1, 50, MAIN_WINDOW);
1680 }
1681 else
1682 #endif
1683 {
1684 _MLOAD_ENTRY(pInstance);
1685 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0D_L,(u16Old_Value - 1)&VOP_VTT_MASK, VOP_VTT_MASK );
1686 MDrv_XC_MLoad_Fire(pInstance, TRUE);
1687 _MLOAD_RETURN(pInstance);
1688 }
1689 }
1690 else
1691 {
1692 #if defined(PATCH_HW_VTT_LIMITATION)
1693 if(MDrv_ReadByte(REG_CHIP_REVISION) < HW_VTT_LIMITATION_CHIPREV)
1694 {
1695 MHal_XC_SetVopVttByBK68(pInstance, (u16Old_Value - 1)&VOP_VTT_MASK, 0);
1696 MDrv_XC_WaitOutputVSync(pInstance, 1, 50, MAIN_WINDOW);
1697 }
1698 else
1699 #endif
1700 {
1701 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0D_L,(u16Old_Value - 1)&VOP_VTT_MASK);
1702 }
1703 }
1704 }
1705 else if (AdjustMode==EN_OUTPUT_TIMING_HTOTAL)
1706 {
1707 if ((MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED) && (!MDrv_SC_GetForceWrite(E_PANEL_MUTE)) )
1708 {
1709 _MLOAD_ENTRY(pInstance);
1710 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0C_L,(u16Old_Value - 1), VOP_HTT_MASK );
1711 MDrv_XC_MLoad_Fire(pInstance, TRUE);
1712 _MLOAD_RETURN(pInstance);
1713 }
1714 else
1715 {
1716 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0C_L,(u16Old_Value - 1));
1717 }
1718 }
1719 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, " -> %u", (u16Old_Value - 1));
1720 MsOS_DelayTask(u16UserDelay);
1721 }
1722 }
1723 else
1724 {
1725 while(u16Old_Value < u16Target_Value - u16Step)
1726 {
1727 u16Old_Value += u16Step;
1728 if (AdjustMode==EN_OUTPUT_TIMING_VTOTAL)
1729 {
1730 if ((MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED) && (!MDrv_SC_GetForceWrite(E_PANEL_MUTE)) )
1731 {
1732 #if defined(PATCH_HW_VTT_LIMITATION)
1733 if(MDrv_ReadByte(REG_CHIP_REVISION) < HW_VTT_LIMITATION_CHIPREV)
1734 {
1735 _MLOAD_ENTRY(pInstance);
1736 MHal_XC_SetVopVttByBK68(pInstance, (u16Old_Value - 1)&VOP_VTT_MASK, 1);
1737 _MLOAD_RETURN(pInstance);
1738 MDrv_XC_WaitOutputVSync(pInstance, 1, 50, MAIN_WINDOW);
1739 }
1740 else
1741 #endif
1742 {
1743 _MLOAD_ENTRY(pInstance);
1744 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0D_L,(u16Old_Value - 1)&VOP_VTT_MASK, VOP_VTT_MASK );
1745 MDrv_XC_MLoad_Fire(pInstance, TRUE);
1746 _MLOAD_RETURN(pInstance);
1747 }
1748 }
1749 else
1750 {
1751 #if defined(PATCH_HW_VTT_LIMITATION)
1752 if(MDrv_ReadByte(REG_CHIP_REVISION) < HW_VTT_LIMITATION_CHIPREV)
1753 {
1754 MHal_XC_SetVopVttByBK68(pInstance, (u16Old_Value - 1)&VOP_VTT_MASK, 0);
1755 MDrv_XC_WaitOutputVSync(pInstance, 1, 50, MAIN_WINDOW);
1756 }
1757 else
1758 #endif
1759 {
1760 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0D_L,(u16Old_Value - 1)&VOP_VTT_MASK);
1761 }
1762 }
1763 }
1764 else if (AdjustMode==EN_OUTPUT_TIMING_HTOTAL)
1765 {
1766 if ((MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED) && (!MDrv_SC_GetForceWrite(E_PANEL_MUTE)) )
1767 {
1768 _MLOAD_ENTRY(pInstance);
1769 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0C_L,(u16Old_Value - 1), VOP_HTT_MASK );
1770 MDrv_XC_MLoad_Fire(pInstance, TRUE);
1771 _MLOAD_RETURN(pInstance);
1772 }
1773 else
1774 {
1775 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0C_L,(u16Old_Value - 1));
1776 }
1777 }
1778 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, " -> %u", (u16Old_Value - 1));
1779 MsOS_DelayTask(u16UserDelay);
1780 }
1781 }
1782 }
1783
1784 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, " -> %u\n", (u16Target_Value-1));
1785 if (AdjustMode==EN_OUTPUT_TIMING_VTOTAL)
1786 {
1787 if ((MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED) && (!MDrv_SC_GetForceWrite(E_PANEL_MUTE)) )
1788 {
1789 #if defined(PATCH_HW_VTT_LIMITATION)
1790 if(MDrv_ReadByte(REG_CHIP_REVISION) < HW_VTT_LIMITATION_CHIPREV)
1791 {
1792 _MLOAD_ENTRY(pInstance);
1793
1794 #if (HW_DESIGN_HDMITX_VER == 1)//Maserati +Raptor HDMITX case
1795 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_B & E_XC_INIT_MISC_B_HDMITX_ENABLE)
1796 {
1797 MS_U8 u8delaycnt = 1;
1798 MS_U16 u16delaytime =0;
1799
1800 if(u16Target_Value > 2500)
1801 u16delaytime = 1000*u8delaycnt/50;
1802 else
1803 u16delaytime = 1000*u8delaycnt/60;
1804
1805 // Update changed VTT to inform Raptor
1806 MDrv_XC_WaitOutputVSync(pInstance, 1, 50, MAIN_WINDOW);
1807 MOD_W2BYTEMSK(REG_MOD_BK00_65_L,u16Target_Value,0x1FFF);
1808 MsOS_DelayTask(u16delaytime);
1809
1810 MHal_XC_SetVopVttByBK68(pInstance, (u16Target_Value - 1)&VOP_VTT_MASK, 0);
1811 _MLOAD_RETURN(pInstance);
1812 }
1813 else
1814 #endif
1815 {
1816 MHal_XC_SetVopVttByBK68(pInstance, (u16Target_Value - 1)&VOP_VTT_MASK, 1);
1817 _MLOAD_RETURN(pInstance);
1818 MDrv_XC_WaitOutputVSync(pInstance, 1, 50, MAIN_WINDOW);
1819 }
1820 }
1821 else
1822 #endif
1823 {
1824 _MLOAD_ENTRY(pInstance);
1825 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0D_L, (u16Target_Value-1)&VOP_VTT_MASK, VOP_VTT_MASK);
1826 _MLOAD_RETURN(pInstance);
1827 }
1828 }
1829 else
1830 {
1831 #if defined(PATCH_HW_VTT_LIMITATION)
1832 if(MDrv_ReadByte(REG_CHIP_REVISION) < HW_VTT_LIMITATION_CHIPREV)
1833 {
1834 #if (HW_DESIGN_HDMITX_VER == 1)//Maserati +Raptor HDMITX case
1835 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_B & E_XC_INIT_MISC_B_HDMITX_ENABLE)
1836 {
1837 // Update changed VTT to inform Raptor
1838 MOD_W2BYTEMSK(REG_MOD_BK00_65_L,u16Target_Value,0x1FFF);
1839 MDrv_XC_WaitOutputVSync(pInstance, 1, 50, MAIN_WINDOW);
1840 MHal_XC_SetVopVttByBK68(pInstance, (u16Target_Value - 1)&VOP_VTT_MASK, 0);
1841 }
1842 else
1843 #endif
1844 {
1845 MHal_XC_SetVopVttByBK68(pInstance, (u16Target_Value - 1)&VOP_VTT_MASK, 0);
1846 MDrv_XC_WaitOutputVSync(pInstance, 1, 50, MAIN_WINDOW);
1847 }
1848 }
1849 else
1850 #endif
1851 {
1852 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0D_L, (u16Target_Value-1)&VOP_VTT_MASK);
1853 }
1854 }
1855 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
1856 if(MDrv_XC_MLoad_GetStatus(g_pDevice1Instance) == E_MLOAD_ENABLED)
1857 {
1858 _MLOAD_ENTRY(g_pDevice1Instance);
1859 MDrv_XC_MLoad_WriteCmd(g_pDevice1Instance, REG_SC_BK10_0D_L,VOP_VTT_MASK, VOP_VTT_MASK );
1860 _MLOAD_RETURN(g_pDevice1Instance);
1861 }
1862 else
1863 {
1864 SC_W2BYTE(1, REG_SC_BK10_0D_L,VOP_VTT_MASK);
1865 }
1866 #endif
1867
1868 }
1869 else if (AdjustMode==EN_OUTPUT_TIMING_HTOTAL)
1870 {
1871 if ((MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED) && (!MDrv_SC_GetForceWrite(E_PANEL_MUTE)) )
1872 {
1873 _MLOAD_ENTRY(pInstance);
1874 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0C_L,u16Target_Value-1, VOP_HTT_MASK );
1875 _MLOAD_RETURN(pInstance);
1876 }
1877 else
1878 {
1879 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0C_L,u16Target_Value-1);
1880 }
1881 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
1882 if(MDrv_XC_MLoad_GetStatus(g_pDevice1Instance) == E_MLOAD_ENABLED)
1883 {
1884 _MLOAD_ENTRY(g_pDevice1Instance);
1885 MDrv_XC_MLoad_WriteCmd(g_pDevice1Instance, REG_SC_BK10_0C_L,(u16Target_Value/2 - 1), VOP_HTT_MASK );
1886 _MLOAD_RETURN(g_pDevice1Instance);
1887 }
1888 else
1889 {
1890 SC_W2BYTE(1, REG_SC_BK10_0C_L,(u16Target_Value/2 - 1));
1891 }
1892 #endif
1893 }
1894 else
1895 {
1896 //Todo: Adjust Dclk
1897 return E_APIXC_RET_FAIL;
1898 }
1899
1900 return E_APIXC_RET_OK;
1901 }
1902
1903 //-------------------------------------------------------------------------------------------------
1904 /// Set the FPLL mode:
1905 /// @param bTrue \b IN: True: FSM mode, False: Non FSM mode
1906 //-------------------------------------------------------------------------------------------------
MDrv_XC_FPLLCusReset(void * pInstance)1907 void MDrv_XC_FPLLCusReset(void *pInstance)
1908 {
1909 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
1910 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
1911 if(0)//(psXCInstPri->u32DeviceID > E_XC_DEVICE0)
1912 {
1913 printf("[%s] Not support for device id %td\n",__FUNCTION__,(ptrdiff_t)psXCInstPri->u32DeviceID);
1914 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING,"MDrv_XC_FPLLCusReset() -> Not support for device id %td\n", (ptrdiff_t)psXCInstPri->u32DeviceID);
1915 return;
1916 }
1917 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
1918 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
1919 int i;
1920 for (i = 0; i < E_FPLL_FLAG_MAX; i++)
1921 {
1922 pXCResourcePrivate->stdrvXC_Display._bFpllCusFlag[i] = FALSE;
1923 pXCResourcePrivate->stdrvXC_Display._u32FpllCusData[i] = 0;
1924 }
1925 }
1926
1927 //-------------------------------------------------------------------------------------------------
1928 /// Set the custmer FPLL parameters(You can just call this function once when system init for testing)
1929 /// @param eMode:Enable/disable customer setting \b IN: @ref EN_FPLL_MODE
1930 /// @param eFlag:The specified FPLL parameter type which to be modified \b IN: @ref EN_FPLL_FLAG
1931 /// @param eFlag:The value to set \b IN: @ref MS_U32
1932 /// Note: the setting will take effect after running of function MApi_XC_SetPanelTiming
1933 //-------------------------------------------------------------------------------------------------
MApi_XC_FPLLCustomerMode_U2(void * pInstance,EN_FPLL_MODE eMode,EN_FPLL_FLAG eFlag,MS_U32 u32Data)1934 void MApi_XC_FPLLCustomerMode_U2(void* pInstance, EN_FPLL_MODE eMode, EN_FPLL_FLAG eFlag, MS_U32 u32Data)
1935 {
1936 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
1937 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
1938 if(0)//(psXCInstPri->u32DeviceID > E_XC_DEVICE0)
1939 {
1940 printf("[%s] Not support for device id %td\n",__FUNCTION__,(ptrdiff_t)psXCInstPri->u32DeviceID);
1941 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING,"MApi_XC_EX_FPLLCustomerMode() -> Not support for device id %td\n", (ptrdiff_t)psXCInstPri->u32DeviceID);
1942 return;
1943 }
1944
1945 if (eMode >= E_FPLL_MODE_MAX)
1946 {
1947 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING,"Wrong Fpll Mode selected!\n");
1948 return;
1949 }
1950
1951 if (eFlag >= E_FPLL_FLAG_MAX)
1952 {
1953 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING,"Wrong Fpll Flag!\n");
1954 return;
1955 }
1956 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
1957
1958 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
1959 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
1960 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING,"Fpll Customer Mode: eMode=0x%x, eFlag=0x%x, u32Data=0x%tx\n", eMode, eFlag, (ptrdiff_t)u32Data);
1961 if (eMode == E_FPLL_MODE_DISABLE_ALL)
1962 {
1963 MDrv_XC_FPLLCusReset(pInstance);
1964 }
1965 else if (eMode == E_FPLL_MODE_DISABLE)
1966 {
1967 pXCResourcePrivate->stdrvXC_Display._bFpllCusFlag[eFlag] = FALSE;
1968 }
1969 else
1970 {
1971 pXCResourcePrivate->stdrvXC_Display._bFpllCusFlag[eFlag] = TRUE;
1972 pXCResourcePrivate->stdrvXC_Display._u32FpllCusData[eFlag] = u32Data;
1973 }
1974 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
1975 }
1976
MApi_XC_FPLLCustomerMode(EN_FPLL_MODE eMode,EN_FPLL_FLAG eFlag,MS_U32 u32Data)1977 void MApi_XC_FPLLCustomerMode(EN_FPLL_MODE eMode, EN_FPLL_FLAG eFlag, MS_U32 u32Data)
1978 {
1979 if (pu32XCInst == NULL)
1980 {
1981 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
1982 return;
1983 }
1984
1985 stXC_SET_FPLL_CUSTOMERMODE XCArgs;
1986 XCArgs.eMode = eMode;
1987 XCArgs.eFlag = eFlag;
1988 XCArgs.u32Data = u32Data;
1989
1990 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_FPLL_CUSTOMERMODE, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
1991 {
1992 printf("Obtain XC engine fail\n");
1993 return;
1994 }
1995 else
1996 {
1997 return;
1998 }
1999 }
2000
2001 //For debug purpose only
MApi_XC_FPLLDbgMode(EN_FPLL_DBG_MODE DbgMode,EN_FPLL_DBG_FLAG DbgFlag,MS_U32 u32Data)2002 void MApi_XC_FPLLDbgMode(EN_FPLL_DBG_MODE DbgMode, EN_FPLL_DBG_FLAG DbgFlag, MS_U32 u32Data)
2003 {
2004 MApi_XC_FPLLCustomerMode((EN_FPLL_MODE)DbgMode, (EN_FPLL_FLAG)DbgFlag, u32Data);
2005 }
2006
2007 //-------------------------------------------------------------------------------------------------
2008 // This function will force freerun in MDrv_Scaler_SetPanelTiming(),
2009 // otherwise MDrv_Scaler_SetPanelTiming() will decide to do framelock or not by itself.
2010 //
2011 // Note: this function is difference with MDrv_SC_set_fpll() which is used to
2012 // unlock framelock after MDrv_Scaler_SetPanelTiming().
2013 // But this function is used to affect MDrv_Scaler_SetPanelTiming()'s behavior.
2014 //-------------------------------------------------------------------------------------------------
MApi_SC_ForceFreerun_U2(void * pInstance,MS_BOOL bEnable)2015 void MApi_SC_ForceFreerun_U2(void* pInstance, MS_BOOL bEnable)
2016 {
2017 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2018 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2019 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
2020
2021 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
2022 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
2023 pXCResourcePrivate->stdrvXC_Display._bForceFreerun = bEnable;
2024 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING,"MApi_SC_ForceFreerun = %u\n", bEnable);
2025 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
2026
2027 }
2028
MApi_SC_ForceFreerun(MS_BOOL bEnable)2029 void MApi_SC_ForceFreerun(MS_BOOL bEnable)
2030 {
2031 if (pu32XCInst == NULL)
2032 {
2033 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
2034 return;
2035 }
2036
2037 stXC_SET_FORCE_FREERUN XCArgs;
2038 XCArgs.bEnable = bEnable;
2039
2040 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_FORCE_FREERUN, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
2041 {
2042 printf("Obtain XC engine fail\n");
2043 return;
2044 }
2045 else
2046 {
2047 return;
2048 }
2049 }
2050
2051 //-------------------------------------------------------------------------------------------------
2052 // This function will return the force freerun state
2053 //-------------------------------------------------------------------------------------------------
MDrv_SC_IsForceFreerun(void * pInstance)2054 MS_BOOL MDrv_SC_IsForceFreerun(void *pInstance)
2055 {
2056 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2057 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2058 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
2059 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
2060 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING,"MDrv_SC_IsForceFreerun = %u\n", pXCResourcePrivate->stdrvXC_Display._bForceFreerun);
2061 return pXCResourcePrivate->stdrvXC_Display._bForceFreerun;
2062 }
2063
MApi_SC_IsForceFreerun_U2(void * pInstance)2064 MS_BOOL MApi_SC_IsForceFreerun_U2(void* pInstance)
2065 {
2066 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2067 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2068 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
2069 MS_BOOL bReturn = MDrv_SC_IsForceFreerun(pInstance);
2070 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
2071 return bReturn;
2072 }
2073
MApi_SC_IsForceFreerun(void)2074 MS_BOOL MApi_SC_IsForceFreerun(void)
2075 {
2076 if (pu32XCInst == NULL)
2077 {
2078 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
2079 return FALSE;
2080 }
2081
2082 stXC_CHECK_FORCE_FREERUN XCArgs;
2083 XCArgs.bReturnValue = FALSE;
2084
2085 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_CHECK_FORCE_FREERUN, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
2086 {
2087 printf("Obtain XC engine fail\n");
2088 return FALSE;
2089 }
2090 else
2091 {
2092 return XCArgs.bReturnValue;
2093 }
2094 }
2095
MApi_SC_SetFreerunVFreq_U2(void * pInstance,E_VFREQ_SEL VFreq)2096 void MApi_SC_SetFreerunVFreq_U2(void* pInstance, E_VFREQ_SEL VFreq)
2097 {
2098 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2099 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2100 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
2101
2102 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
2103 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
2104 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING,"MApi_SC_SetFreerunVFreq = %u\n", VFreq);
2105 pXCResourcePrivate->stdrvXC_Display._ForceVFreq = VFreq;
2106 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
2107 }
2108
MApi_SC_SetFreerunVFreq(E_VFREQ_SEL VFreq)2109 void MApi_SC_SetFreerunVFreq(E_VFREQ_SEL VFreq)
2110 {
2111 if (pu32XCInst == NULL)
2112 {
2113 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
2114 return;
2115 }
2116
2117 stXC_SET_FREERUN_FREQ XCArgs;
2118 XCArgs.VFreq = VFreq;
2119
2120 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_FREERUN_FREQ, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
2121 {
2122 printf("Obtain XC engine fail\n");
2123 return;
2124 }
2125 else
2126 {
2127 return;
2128 }
2129 }
2130
MDrv_SC_VFreq_Select(void * pInstance,MS_U16 u16AutoVFreq)2131 MS_U16 MDrv_SC_VFreq_Select(void *pInstance, MS_U16 u16AutoVFreq)
2132 {
2133 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2134 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2135 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
2136 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
2137 if(pXCResourcePrivate->stdrvXC_Display._ForceVFreq == VFREQ_50HZ)
2138 {
2139 return 500;
2140 }
2141 else if(pXCResourcePrivate->stdrvXC_Display._ForceVFreq == VFREQ_60HZ)
2142 {
2143 return 600;
2144 }
2145 else if(pXCResourcePrivate->stdrvXC_Display._ForceVFreq == VFREQ_FROM_SRC)
2146 {
2147 return u16AutoVFreq;
2148 }
2149 else if (pXCResourcePrivate->stdrvXC_Display._ForceVFreq == VFREQ_FROM_PANEL)
2150 {
2151 return pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq;
2152 }
2153 else
2154 {
2155 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "MDrv_SC_VFreq_Select(): wrong Vfreq_SEL input, use default logic!!");
2156 return u16AutoVFreq;
2157 }
2158 }
2159 //-------------------------------------------------------------------------------------------------
2160 // This function will Get the exact ext_panel info structure for input vfreq
2161 // IN:
2162 // pPanelInfoEx: ext-panel info for return,
2163 // if u16VFreq=0, pPanelInfoEx= next address to save new panel info
2164 // else return the panel info pointer of "VFreq"
2165 // u16VFreq: the request vfreq for getting ext-panel info
2166 // Return:
2167 // TRUE: Success, FALSE: FAIL
2168 //-------------------------------------------------------------------------------------------------
_MDrv_XC_GetExPanelInfo(void * pInstance,XC_PANEL_INFO_EX ** ppPanelInfoEx,MS_U16 u16VFreq)2169 static MS_BOOL _MDrv_XC_GetExPanelInfo(void *pInstance, XC_PANEL_INFO_EX **ppPanelInfoEx, MS_U16 u16VFreq)
2170 {
2171 MS_BOOL bRet = FALSE;
2172 MS_U8 i;
2173 *ppPanelInfoEx = NULL;
2174 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2175 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2176 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
2177 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
2178 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "u16VFreq=%u\n", u16VFreq)
2179
2180 for(i=0; i<PANEL_INFO_EX_NUM; i++)
2181 {
2182 if(u16VFreq == 0)
2183 {
2184 //Get next available place for store
2185 if(gSrcInfo[MAIN_WINDOW].Status2.stPanelInfoEx[i].u32PanelInfoEx_Version == 0)
2186 {
2187 bRet = TRUE;
2188 *ppPanelInfoEx = &gSrcInfo[MAIN_WINDOW].Status2.stPanelInfoEx[i];
2189 break;
2190 }
2191 }
2192 else
2193 {
2194 //Get ex panel info of specified "u16VFreq"
2195 if((gSrcInfo[MAIN_WINDOW].Status2.stPanelInfoEx[i].u32PanelInfoEx_Version != 0) &&
2196 (abs(gSrcInfo[MAIN_WINDOW].Status2.stPanelInfoEx[i].u16VFreq - u16VFreq) <= VFREQ_DIFF_TOLERANCE) )
2197 {
2198 bRet = TRUE;
2199 *ppPanelInfoEx = &gSrcInfo[MAIN_WINDOW].Status2.stPanelInfoEx[i];
2200 break;
2201 }
2202 }
2203 }
2204 //XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "Get ExPanelInfo u16VFreq=%u, pPanelInfoEx=0x%x, bRet=%u\n", u16VFreq, (MS_U32)*ppPanelInfoEx, bRet);
2205 return bRet;
2206 }
2207
2208 //-------------------------------------------------------------------------------------------------
2209 /// Set external panel info for output
2210 /// Currently, only support setting of two different vfreqs at same time
2211 /// @param bEnable \b IN: TRUE: Enable this XC_PANEL_INFO_EX, FALSE: Disable this XC_PANEL_INFO_EX
2212 /// @param pPanelInfoEx \b IN: The extern panel information to set @ref XC_PANEL_INFO_EX
2213 /// @return @ref MS_BOOL TRUE: Success, FALSE: Failed
2214 /// Note: the setting will take effect after running of function MApi_XC_SetPanelTiming
2215 //-------------------------------------------------------------------------------------------------
MDrv_XC_SetExPanelInfo(void * pInstance,MS_BOOL bEnable,XC_PANEL_INFO_EX * pPanelInfoEx)2216 MS_BOOL MDrv_XC_SetExPanelInfo(void *pInstance, MS_BOOL bEnable, XC_PANEL_INFO_EX *pPanelInfoEx)
2217 {
2218 MS_BOOL bRet = TRUE;
2219 XC_PANEL_INFO_EX *pPnlInfoEx = NULL;
2220 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2221 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2222 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
2223 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
2224 if(NULL == pPanelInfoEx || pPanelInfoEx->u32PanelInfoEx_Version < 2)
2225 {
2226 //We consider compatible operation from version2 , so reject the info init when version invalid
2227 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "MApi_XC_EnablePanelInfo: Version or pPanelInfoEx is Invalid!!")
2228 bRet = FALSE;
2229 }
2230 if(bRet)
2231 {
2232 MS_U16 u16VFreq = pPanelInfoEx->u16VFreq;
2233 MS_U16 u16Length = (pPanelInfoEx->u16PanelInfoEX_Length > sizeof(XC_PANEL_INFO_EX)) ? \
2234 sizeof(XC_PANEL_INFO_EX) : pPanelInfoEx->u16PanelInfoEX_Length;
2235 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "MDrv_XC_SetExPanelInfo: bEnable=%u, u16VFreq=%u\n", bEnable, u16VFreq)
2236 if(bEnable)
2237 {
2238 bRet = _MDrv_XC_GetExPanelInfo(pInstance, &pPnlInfoEx, 0);
2239 if(bRet && pPnlInfoEx != NULL)
2240 {
2241 //There are still space to store this info, so copy it
2242 memcpy(pPnlInfoEx, pPanelInfoEx, u16Length);
2243 }
2244 }
2245 else
2246 {
2247 if(u16VFreq == PANEL_INFO_EX_INVALID_ALL)
2248 {
2249 //Clear all info in ex panel info structure
2250 memset(gSrcInfo[MAIN_WINDOW].Status2.stPanelInfoEx, 0, (sizeof(XC_PANEL_INFO_EX))*PANEL_INFO_EX_NUM);
2251 }
2252 else
2253 {
2254 //Clear ex panel info structure of specified "VFreq"
2255 bRet = _MDrv_XC_GetExPanelInfo(pInstance, &pPnlInfoEx, u16VFreq);
2256 if(bRet && pPnlInfoEx != NULL)
2257 {
2258 memset(pPnlInfoEx, 0, sizeof(XC_PANEL_INFO_EX));
2259 }
2260 }
2261 }
2262 }
2263 //XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "MDrv_XC_SetExPanelInfo Exit: bRet=%u, pPnlInfoEx=%x\n", bRet, (MS_U32)pPnlInfoEx)
2264 return bRet;
2265 }
2266
MApi_XC_SetExPanelInfo_U2(void * pInstance,MS_BOOL bEnable,XC_PANEL_INFO_EX * pPanelInfoEx)2267 MS_BOOL MApi_XC_SetExPanelInfo_U2(void* pInstance, MS_BOOL bEnable, XC_PANEL_INFO_EX *pPanelInfoEx)
2268 {
2269 MS_BOOL bReturn = FALSE;
2270 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2271 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2272 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
2273 bReturn = MDrv_XC_SetExPanelInfo(pInstance, bEnable, pPanelInfoEx);
2274 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
2275 return bReturn;
2276 }
MApi_XC_SetExPanelInfo(MS_BOOL bEnable,XC_PANEL_INFO_EX * pPanelInfoEx)2277 MS_BOOL MApi_XC_SetExPanelInfo(MS_BOOL bEnable, XC_PANEL_INFO_EX *pPanelInfoEx)
2278 {
2279 if (pu32XCInst == NULL)
2280 {
2281 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
2282 return FALSE;
2283 }
2284
2285 stXC_SET_EXPANEL_INFO XCArgs;
2286 XCArgs.bEnable = bEnable;
2287 XCArgs.pPanelInfoEx = pPanelInfoEx;
2288 XCArgs.bReturnValue = FALSE;
2289
2290 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_EXPANEL_INFO, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
2291 {
2292 printf("Obtain XC engine fail\n");
2293 return FALSE;
2294 }
2295 else
2296 {
2297 return XCArgs.bReturnValue;
2298 }
2299 }
2300
_MDrv_Scaler_SetIGainPGain(void * pInstance,MS_U8 u8FRC_Out,MS_U16 u16FRC_VFreq,SCALER_WIN eWindow)2301 static void _MDrv_Scaler_SetIGainPGain(void *pInstance, MS_U8 u8FRC_Out, MS_U16 u16FRC_VFreq, SCALER_WIN eWindow)
2302 {
2303 // MS_U8 i,u8Vco,u8LGain2 = 1,u8LGain1=1;
2304 MS_U8 u8Vco, u8LGain1=1;
2305 MS_U64 u64dclk=0;
2306 MS_U8 u8GainI, u8GainP;
2307 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2308 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2309 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
2310 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
2311 MS_U16 u16HTotal = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HTotal;
2312 MS_U16 u16VTotal = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VTotal;
2313
2314 //check parameter valid, avoiding the diving zero failure
2315 if(0 == u8FRC_Out)
2316 {
2317 u8FRC_Out = 1;
2318 }
2319 //=================================================
2320 // FPLL I/P gain setting
2321 //
2322 // MM * 524288*loop_gain
2323 // i_gain = ---------------------------
2324 // 8 * Htt * Vtt * (Ovs + 1 ) * Vco
2325 //
2326 // MM = MPLL / Xtal = 216 / 12(MHz) = 18
2327 // loop_gain = 2^(reg_loop_gain_1st) * loop_gain_2nd
2328 // loop_gain_2nd = loop_gain_2nd == 0 ? 1 : reg_loop_gain_2nd;
2329 // Vco = LVDS == Dual mode ? 7 : 3.5;
2330 // p_gain = i_gain *2;
2331 // i_gain = 2^(reg_i_gain-5)
2332 // p_gain = 2^(reg_p_gain-5)
2333 // reg_loop_gain_1st = BK_0x3101[1:0]
2334 // loop_gain_2nd = BK_0x3101[15:8]
2335 // Dual mode = BK_0x3103[8]
2336 // Ovs = BK_0x310C[15:12]
2337 // reg_i_gain = BK_0x310B[11:8]
2338 // reg_p_gain = BK_0x310B[15:12]
2339 //--------------------------------------------------------
2340 u64dclk = ((MS_U64)u16VTotal)*u16HTotal*u16FRC_VFreq;
2341
2342 u8LGain1 = MHal_PNL_Get_LPLL_LoopGain(pInstance, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u8LPLL_Mode
2343 , pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type
2344 , u64dclk);
2345
2346 u8Vco = MHal_PNL_Get_Loop_DIV(pInstance, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u8LPLL_Mode
2347 , pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type
2348 , u64dclk);
2349
2350 // MM = MPLL / Xtal = (LVDS_MPLL_CLOCK_MHZ*1000000UL) /g_XC_InitData.u32XTAL_Clock
2351
2352 MHal_XC_Calc_IGainPGain(pInstance, &u8GainI
2353 , &u8GainP
2354 , pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.u32XTAL_Clock
2355 , u8LGain1, u8Vco, u16HTotal, u16VTotal, u8FRC_Out);
2356
2357 #ifdef UFO_XC_FB_LEVEL
2358 if(((gSrcInfo[eWindow].eFBLevel == E_XC_FB_LEVEL_FBL)
2359 || (gSrcInfo[eWindow].eFBLevel == E_XC_FB_LEVEL_RFBL_DI))
2360 && !gSrcInfo[eWindow].Status2.bMVOPHSKMode
2361 )
2362 #else
2363 if ((gSrcInfo[eWindow].bFBL || gSrcInfo[eWindow].bR_FBL) && !gSrcInfo[eWindow].Status2.bMVOPHSKMode)
2364 #endif
2365 {
2366 u8GainP += 2;
2367 u8GainI += 2;
2368 }
2369
2370 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
2371 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFRCEnabled)
2372 {
2373 if(IsVBY1_16LANE((MS_U8)(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type)))
2374 {
2375 }
2376 else
2377 {
2378 u8GainP += 2;
2379 u8GainI += 2;
2380 }
2381 }
2382 #endif
2383
2384 if (pXCResourcePrivate->stdrvXC_Display._bFpllCusFlag[E_FPLL_FLAG_IGAIN])
2385 {
2386 u8GainI = (MS_U8)pXCResourcePrivate->stdrvXC_Display._u32FpllCusData[E_FPLL_FLAG_IGAIN];
2387 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "user forces REG_IGain= 0x%X (%u)\n", u8GainI, u8GainI);
2388 }
2389 if (pXCResourcePrivate->stdrvXC_Display._bFpllCusFlag[E_FPLL_FLAG_PGAIN])
2390 {
2391 u8GainP = (MS_U8)pXCResourcePrivate->stdrvXC_Display._u32FpllCusData[E_FPLL_FLAG_PGAIN];
2392 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "user forces REG_PGain= 0x%X (%u)\n", u8GainP, u8GainP);
2393 }
2394
2395 LPLL_BK_STORE;
2396 #if (HW_DESIGN_HDMITX_VER == 1)//Maserati +Raptor HDMITX case, adjust IGain PGain to coordinate HW timing change limit
2397 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_B & E_XC_INIT_MISC_B_HDMITX_ENABLE)
2398 MDrv_WriteByte(H_BK_LPLL(0x0B), 0x54); //Gain
2399 else
2400 MDrv_WriteByte(H_BK_LPLL(0x0B), (u8GainP<<4)|u8GainI); //Gain
2401 #else
2402 MDrv_WriteByte(H_BK_LPLL(0x0B), (u8GainP<<4)|u8GainI); //Gain
2403 #endif
2404 LPLL_BK_RESTORE;
2405
2406 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "REG_IGain= 0x%X (%u)\n", u8GainI, u8GainI)
2407 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "REG_PGain= 0x%X (%u)\n", u8GainP, u8GainP)
2408 }
2409 //-------------------------------------------------------------------------------------------------
2410 // This function will Set the H or V sync information: SyncStart/end/width
2411 // IN:
2412 // H/V Sync infomation and H/V output total that corresponding to this sync info.
2413 // Return:
2414 // NONE
2415 //-------------------------------------------------------------------------------------------------
_MDrv_XC_SetHVSync(void * pInstance,MS_BOOL bHSync,MS_U16 u16SyncWidth,MS_U16 u16SyncBackPorch,MS_U16 u16HVTotal)2416 static void _MDrv_XC_SetHVSync(void *pInstance, MS_BOOL bHSync, MS_U16 u16SyncWidth, MS_U16 u16SyncBackPorch, MS_U16 u16HVTotal)
2417 {
2418 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2419 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2420 //Change to big one: Change Vtt first to avoid changed vsync end > old vtt
2421 MS_U16 u16Temp;
2422 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "bHSync=%u, SyncWidth=%u, SyncBackPorch=%u, Total=%u\n",
2423 bHSync, u16SyncWidth, u16SyncBackPorch, u16HVTotal)
2424 if(bHSync)
2425 {
2426 if ((MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED) && (!MDrv_SC_GetForceWrite(E_PANEL_MUTE)) )
2427 {
2428 _MLOAD_ENTRY(pInstance);
2429 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2430 if (psXCInstPri->u32DeviceID == 0)
2431 #endif
2432 {
2433 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_04_L, u16SyncWidth + u16SyncBackPorch, VOP_DE_HSTART_MASK); // output HDE start
2434 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2435 MDrv_XC_MLoad_WriteCmd(g_pDevice1Instance, REG_SC_BK10_04_L, (u16SyncWidth + u16SyncBackPorch)/2, VOP_DE_HSTART_MASK); // output HDE start
2436 #endif
2437 }
2438 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_01_L, u16SyncWidth-1, 0xFF); // output Hsync Width
2439 _MLOAD_RETURN(pInstance);
2440 }
2441 else
2442 {
2443 u16Temp = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_01_L, 0xFF);//Old Hsync Width
2444 if(u16Temp > u16SyncWidth-1)
2445 {
2446 //Change to small one
2447 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_01_L, u16SyncWidth-1, 0xFF); // output HDE start
2448 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2449 if (psXCInstPri->u32DeviceID == 0)
2450 #endif
2451 {
2452 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_04_L, u16SyncWidth + u16SyncBackPorch, VOP_DE_HSTART_MASK);
2453 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2454 SC_W2BYTEMSK(1, REG_SC_BK10_04_L, (u16SyncWidth + u16SyncBackPorch)/2, VOP_DE_HSTART_MASK);
2455 #endif
2456 }
2457 }
2458 else
2459 {
2460 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2461 if (psXCInstPri->u32DeviceID == 0)
2462 #endif
2463 {
2464 //Change to big one
2465 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_04_L, u16SyncWidth + u16SyncBackPorch, VOP_DE_HSTART_MASK);
2466 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
2467 SC_W2BYTEMSK(1, REG_SC_BK10_04_L, (u16SyncWidth + u16SyncBackPorch)/2, VOP_DE_HSTART_MASK);
2468 #endif
2469 }
2470 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_01_L, u16SyncWidth-1, 0xFF);
2471 }
2472 }
2473 }
2474 else
2475 {
2476 #if FRC_INSIDE
2477 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
2478 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
2479 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_FRC_INSIDE_4K_HALFK_240HZ)
2480 {
2481 u16HVTotal = u16HVTotal/4;
2482 u16SyncBackPorch = u16SyncBackPorch/4;
2483 }
2484 #endif
2485
2486 MS_U16 u16NewVsyncEnd = u16HVTotal-u16SyncBackPorch;
2487 MS_U16 u16VsyncStart = u16NewVsyncEnd - u16SyncWidth;
2488
2489 #ifdef PATCH_TCON_BRING_UP
2490 if((((MS_U8)pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type) == E_XC_PNL_LPLL_EPI28_12P)
2491 && !(strcmp(panelName_UD_VB1_8LANE_DRDEPI,MDrv_PNL_GetName())))
2492 {
2493 u16NewVsyncEnd = VSYNC_END_FOR_UD_VB1_8LANE_DRDEPI;
2494 u16VsyncStart = VSYNC_START_FOR_UD_VB1_8LANE_DRDEPI;
2495 }
2496 #endif
2497
2498 MS_U16 u16NewVsyncStart = (u16VsyncStart & 0x7FF) | ((u16VsyncStart & 0x800) << 1);
2499
2500 #if 0
2501 // Raptor case, swap position of Vsync and DE
2502 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_B & E_XC_INIT_MISC_B_HDMITX_ENABLE)
2503 {
2504 u16VsyncStart = 1;
2505 u16NewVsyncEnd = u16VsyncStart + u16SyncWidth;
2506 u16NewVsyncStart = (u16VsyncStart & 0x7FF) | ((u16VsyncStart & 0x800) << 1);
2507 }
2508 #endif
2509
2510 if ((MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED) && (!MDrv_SC_GetForceWrite(E_PANEL_MUTE)) )
2511 {
2512 _MLOAD_ENTRY(pInstance);
2513 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_02_L, u16NewVsyncStart, 0x17FF); // output Vsync start
2514 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_03_L, u16NewVsyncEnd-1, VOP_VSYNC_END_MASK); // output Vsync end
2515 _MLOAD_RETURN(pInstance);
2516 }
2517 else
2518 {
2519 u16Temp = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_03_L, VOP_VSYNC_END_MASK);//Old Vsync End
2520 if(u16Temp > u16NewVsyncEnd-1)
2521 {
2522 //Change to small one
2523 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_02_L, u16NewVsyncStart, 0x17FF); // output Vsync start
2524 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_03_L, u16NewVsyncEnd-1);
2525 }
2526 else
2527 {
2528 //Change to big one
2529 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_03_L, u16NewVsyncEnd-1);
2530 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_02_L, u16NewVsyncStart, 0x17FF); // output Vsync start
2531 }
2532 }
2533 }
2534 }
2535
2536 //-------------------------------------------------------------------------------------------------
2537 // This function will Enable/Disable manual Vsync Mode
2538 // IN:
2539 // bManualMode: TRUE---Manual Mode, False---Auto Mode
2540 // Return:
2541 // NONE
2542 //-------------------------------------------------------------------------------------------------
_MDrv_XC_SetOutputVSyncMode(void * pInstance,MS_BOOL bManualMode)2543 static void _MDrv_XC_SetOutputVSyncMode(void *pInstance, MS_BOOL bManualMode)
2544 {
2545 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2546 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2547 //Change to big one: Change Vtt first to avoid changed vsync end > old vtt
2548 MS_U16 u16OldVSyncMode = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_10_L) & BIT(15);
2549 if((((MS_U16)bManualMode)<<15) != u16OldVSyncMode)
2550 {
2551 u16OldVSyncMode = (((MS_U16)bManualMode)<<15);
2552 if ((MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED) && (!MDrv_SC_GetForceWrite(E_PANEL_MUTE)) )
2553 {
2554 _MLOAD_ENTRY(pInstance);
2555 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_10_L, u16OldVSyncMode, BIT(15)); // output Vsync start
2556 _MLOAD_RETURN(pInstance);
2557 }
2558 else
2559 {
2560 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_10_L, u16OldVSyncMode, BIT(15)); //Manual output Vsync
2561 }
2562 }
2563 }
2564
MDrv_SC_set_Htt_Vtt(void * pInstance,XC_SetTiming_Info * pTimingInfo,MS_U16 * pu16VFreq,MS_U32 u32HighAccurateInputVFreq,XC_DISPLAYOUT_INFO * pDisplyout_Info,SCALER_WIN eWindow)2565 void MDrv_SC_set_Htt_Vtt(void *pInstance, XC_SetTiming_Info *pTimingInfo, MS_U16 *pu16VFreq,MS_U32 u32HighAccurateInputVFreq, XC_DISPLAYOUT_INFO *pDisplyout_Info, SCALER_WIN eWindow)
2566 {
2567 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2568 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2569 MS_U16 u16OldHtt, u16OldVtt, u16OPHtt,u16VsyncStart, u16VsyncEnd = 0;
2570 MS_U16 u16HSyncWidth, u16HBackPorch, u16VSyncWidth, u16VBackPorch = 0;
2571 MS_BOOL bManualVsyncMode = FALSE;
2572 MS_U16 u16ChangeHttSteps=1,u16ChangeHttDelay=0,u16ChangeVttSteps=CHANGE_VTT_STEPS,u16ChangeVttDelay=CHANGE_VTT_DELAY;
2573 XC_PANEL_INFO_EX *pPanelInfoEx = NULL;
2574 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
2575 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
2576 pDisplyout_Info->u16Htt_out = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultHTotal;
2577 pDisplyout_Info->u16Vtt_out = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVTotal;
2578
2579 MS_U16 u16DEVStart = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart;
2580 MS_U16 u16DEVEnd = u16DEVStart+pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height;
2581 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER < 6))
2582 if(((pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_FRC_INSIDE)
2583 || (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_FRC_INSIDE_60HZ))
2584 &&(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width == 1280)
2585 &&(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height== 720))
2586 {
2587 pDisplyout_Info->u16Htt_out = 2200;
2588 pDisplyout_Info->u16Vtt_out = 1130;
2589 }
2590 #endif
2591
2592 u16HSyncWidth = pXCResourcePrivate->stdrvXC_Display._u16DefaultHSyncWidth;
2593 u16HBackPorch = pXCResourcePrivate->stdrvXC_Display._u16DefaultHSyncBackPorch;
2594 u16VSyncWidth = pXCResourcePrivate->stdrvXC_Display._u16DefaultVSyncWidth;
2595 u16VBackPorch = pXCResourcePrivate->stdrvXC_Display._u16DefaultVSyncBackPorch;
2596
2597 #if defined(PATCH_HW_VTT_LIMITATION)
2598 if(MDrv_ReadByte(REG_CHIP_REVISION) < HW_VTT_LIMITATION_CHIPREV)
2599 {
2600 u16OldVtt = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_36_L, VOP_VTT_MASK)+1;
2601 }
2602 else
2603 #endif
2604 {
2605 u16OldVtt = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_0D_L, VOP_VTT_MASK) + 1;
2606 }
2607 u16OldHtt = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_0C_L, VOP_HTT_MASK) + 1;
2608 u16OPHtt = pDisplyout_Info->u16Htt_out;
2609
2610 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "Default SyncWidth/back porch: H=%u,%u,V=%u,%u, Old Htt/Vtt=%u,%u\n"
2611 , pXCResourcePrivate->stdrvXC_Display._u16DefaultHSyncWidth
2612 , pXCResourcePrivate->stdrvXC_Display._u16DefaultHSyncBackPorch
2613 , pXCResourcePrivate->stdrvXC_Display._u16DefaultVSyncWidth
2614 , pXCResourcePrivate->stdrvXC_Display._u16DefaultVSyncBackPorch
2615 , u16OldHtt, u16OldVtt)
2616 if(_MDrv_XC_GetExPanelInfo(pInstance, &pPanelInfoEx, *pu16VFreq) /*&& pPanelInfoEx != NULL*/)
2617 {
2618 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "PanelInfoEx assigned\n")
2619 if(pPanelInfoEx->bHttDelayValid)
2620 {
2621 u16ChangeHttDelay = pPanelInfoEx->u16HttDelay;
2622 }
2623 if(pPanelInfoEx->bHttStepsValid)
2624 {
2625 u16ChangeHttSteps = pPanelInfoEx->u16HttSteps;
2626 }
2627 if(pPanelInfoEx->bVttDelayValid)
2628 {
2629 u16ChangeVttDelay = pPanelInfoEx->u16VttDelay;
2630 }
2631 if(pPanelInfoEx->bVttStepsValid)
2632 {
2633 u16ChangeVttSteps = pPanelInfoEx->u16VttSteps;
2634 }
2635 }
2636
2637 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "PanelInfoEx: %s, org htt=%u, vtt=%u, vfreq=%u; HighAccurateVFreq=%u; Output Vfreq=%u, Mode=%u\n", (pPanelInfoEx==NULL) ? "NO": "YES",
2638 pDisplyout_Info->u16Htt_out, pDisplyout_Info->u16Vtt_out,
2639 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq,
2640 *pu16VFreq,(unsigned int)u32HighAccurateInputVFreq, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.enPnl_Out_Timing_Mode)
2641
2642 #ifdef UFO_XC_FB_LEVEL
2643 if(((gSrcInfo[eWindow].eFBLevel == E_XC_FB_LEVEL_FBL)
2644 || (gSrcInfo[eWindow].eFBLevel == E_XC_FB_LEVEL_RFBL_DI))
2645 && !gSrcInfo[eWindow].Status2.bMVOPHSKMode
2646 )
2647 #else
2648 if((gSrcInfo[eWindow].bFBL || gSrcInfo[eWindow].bR_FBL) && !gSrcInfo[eWindow].Status2.bMVOPHSKMode)
2649 #endif
2650 {
2651 if(!(pXCResourcePrivate->stdrvXC_Display._bForceFreerun
2652 && (pXCResourcePrivate->stdrvXC_Display._ForceVFreq != VFREQ_FROM_SRC)))
2653 {
2654 //Not Force Free Run@Fixed 50/60 hz, need adjust vtt
2655 //calculate Vtt_out for FBL, Vtt_out = Vtt_in * Vde_out / Vde_in
2656 pDisplyout_Info->u16Vtt_out = MDrv_SC_FBL_Calc_Vtt(pInstance, pTimingInfo, eWindow);
2657 }
2658 }
2659
2660 switch(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.enPnl_Out_Timing_Mode)
2661 {
2662 case E_XC_PNL_CHG_HTOTAL:
2663 if((pPanelInfoEx == NULL) ||
2664 (pPanelInfoEx->bHTotalValid == FALSE))
2665 {
2666 //Change htt, all case can do it
2667 MDrv_SC_adjust_output_htt_vtt(&pDisplyout_Info->u16Htt_out, &pDisplyout_Info->u16Vtt_out,u32HighAccurateInputVFreq,
2668 pDisplyout_Info->u16Htt_out,
2669 pDisplyout_Info->u16Vtt_out,
2670 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq,
2671 FALSE);
2672 }
2673 break;
2674 case E_XC_PNL_CHG_VTOTAL:
2675 if((pPanelInfoEx == NULL) ||
2676 (pPanelInfoEx->bVTotalValid == FALSE))
2677 {
2678 #ifdef UFO_XC_FB_LEVEL
2679 if(((gSrcInfo[eWindow].eFBLevel == E_XC_FB_LEVEL_FBL)
2680 || (gSrcInfo[eWindow].eFBLevel == E_XC_FB_LEVEL_RFBL_DI))
2681 && !gSrcInfo[eWindow].Status2.bMVOPHSKMode
2682 )
2683 #else
2684 if((gSrcInfo[eWindow].bFBL || gSrcInfo[eWindow].bR_FBL) && !gSrcInfo[eWindow].Status2.bMVOPHSKMode)
2685 #endif
2686 {
2687 //FBL+FPLL or FBL+FreeRun@Src can not adjust vtt
2688 if(pXCResourcePrivate->stdrvXC_Display._bForceFreerun
2689 && (pXCResourcePrivate->stdrvXC_Display._ForceVFreq != VFREQ_FROM_SRC))
2690 {
2691 MDrv_SC_adjust_output_htt_vtt(&pDisplyout_Info->u16Htt_out, &pDisplyout_Info->u16Vtt_out,u32HighAccurateInputVFreq,
2692 pDisplyout_Info->u16Htt_out,
2693 pDisplyout_Info->u16Vtt_out,
2694 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq,
2695 TRUE);
2696 }
2697
2698 }
2699 else
2700 {
2701 //Not FBL case, can adjust vtt
2702 MDrv_SC_adjust_output_htt_vtt(&pDisplyout_Info->u16Htt_out, &pDisplyout_Info->u16Vtt_out,u32HighAccurateInputVFreq,
2703 pDisplyout_Info->u16Htt_out,
2704 pDisplyout_Info->u16Vtt_out,
2705 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq,
2706 TRUE);
2707 }
2708 }
2709 break;
2710 case E_XC_PNL_CHG_DCLK:
2711 default:
2712 break;
2713 }
2714
2715 if(pPanelInfoEx != NULL)
2716 {
2717 MS_BOOL bExceeded = FALSE;
2718 if(!pXCResourcePrivate->stdrvXC_Display._bForceFreerun)
2719 {
2720 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "@@@ Set Htt/Vtt By Ex panel\n\n");
2721 if(pPanelInfoEx->bVTotalValid)
2722 {
2723 pDisplyout_Info->u16Vtt_out = pPanelInfoEx->u16VTotal;
2724 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "11: u16Vtt_out=%u\n",pDisplyout_Info->u16Vtt_out);
2725 }
2726
2727 if(pPanelInfoEx->bHTotalValid)
2728 {
2729 pDisplyout_Info->u16Htt_out = pPanelInfoEx->u16HTotal;
2730 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "22: u16Htt_out=%u\n",pDisplyout_Info->u16Htt_out);
2731 }
2732 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "33: u16MaxVTotal = %u, u16MinVTotal = %u, u16MaxHTotal = %u, u16MinHTotal = %u\n",
2733 pPanelInfoEx->u16MaxVTotal, pPanelInfoEx->u16MinVTotal,
2734 pPanelInfoEx->u16MaxHTotal, pPanelInfoEx->u16MinHTotal);
2735
2736 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "44: bMaxVTotalValid = %u, bMinVTotalValid = %u, bMaxHTotalValid = %u, bMinHTotalValid = %u\n",
2737 pPanelInfoEx->bMaxVTotalValid, pPanelInfoEx->bMinVTotalValid,
2738 pPanelInfoEx->bMaxHTotalValid, pPanelInfoEx->bMinHTotalValid);
2739
2740
2741 if(pPanelInfoEx->bMaxVTotalValid && (pDisplyout_Info->u16Vtt_out > pPanelInfoEx->u16MaxVTotal))
2742 {
2743 pDisplyout_Info->u16Vtt_out = pPanelInfoEx->u16MaxVTotal;
2744 bExceeded = TRUE;
2745 }
2746
2747 if(pPanelInfoEx->bMinVTotalValid && (pDisplyout_Info->u16Vtt_out < pPanelInfoEx->u16MinVTotal))
2748 {
2749 pDisplyout_Info->u16Vtt_out = pPanelInfoEx->u16MinVTotal;
2750 bExceeded = TRUE;
2751 }
2752
2753 if(pPanelInfoEx->bMaxHTotalValid && (pDisplyout_Info->u16Htt_out > pPanelInfoEx->u16MaxHTotal))
2754 {
2755 pDisplyout_Info->u16Htt_out = pPanelInfoEx->u16MaxHTotal;
2756 bExceeded = TRUE;
2757 }
2758
2759 if(pPanelInfoEx->bMinHTotalValid && (pDisplyout_Info->u16Htt_out < pPanelInfoEx->u16MinHTotal))
2760 {
2761 pDisplyout_Info->u16Htt_out = pPanelInfoEx->u16MinHTotal;
2762 bExceeded = TRUE;
2763 }
2764
2765 if(bExceeded)
2766 {
2767 printf("ALERT: HTotal or VTotal is out of range, Set to default timing and freerun !!!!!!\n");
2768 pDisplyout_Info->u16Htt_out = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultHTotal;
2769 pDisplyout_Info->u16Vtt_out = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVTotal;
2770 *pu16VFreq = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq;
2771 MDrv_XC_SetFreeRunTiming(pInstance);
2772 }
2773 }
2774 }
2775 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "new htt=%u, vtt=%u, vfreq=%u\n", pDisplyout_Info->u16Htt_out, pDisplyout_Info->u16Vtt_out, *pu16VFreq);
2776 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HTotal = pDisplyout_Info->u16Htt_out;
2777 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VTotal = pDisplyout_Info->u16Vtt_out;
2778
2779 if(pPanelInfoEx != NULL)
2780 {
2781 if(pPanelInfoEx->bHSyncBackPorchValid ||
2782 pPanelInfoEx->bHSyncWidthValid)
2783 {
2784 pXCResourcePrivate->stdrvXC_Display._bHSyncChanged = TRUE;
2785 if(pPanelInfoEx->bHSyncBackPorchValid)
2786 {
2787 u16HBackPorch = pPanelInfoEx->u16HSyncBackPorch;
2788 }
2789 if(pPanelInfoEx->bHSyncWidthValid)
2790 {
2791 u16HSyncWidth = pPanelInfoEx->u16HSyncWidth;
2792 }
2793 }
2794 if(pPanelInfoEx->bVSyncBackPorchValid ||
2795 pPanelInfoEx->bVSyncWidthValid)
2796 {
2797 pXCResourcePrivate->stdrvXC_Display._bVSyncChanged = TRUE;
2798 if(pPanelInfoEx->bVSyncBackPorchValid)
2799 {
2800 u16VBackPorch = pPanelInfoEx->u16VSyncBackPorch;
2801 }
2802 if(pPanelInfoEx->bVSyncWidthValid)
2803 {
2804 u16VSyncWidth = pPanelInfoEx->u16VSyncWidth;
2805 }
2806 }
2807 }
2808 #ifndef PATCH_HW_VTT_LIMITATION
2809 // for high accurate input VFreq case, to avoid reconfig Vtt/Htt
2810 if(abs((MS_S16)pDisplyout_Info->u16Vtt_out - (MS_S16)u16OldVtt) >= CHANGE_VTT_TOLERANCE) // fixme: mantis 1216841
2811 #endif
2812 {
2813 //if Vsync in DE zone then move Vsync to out of DE
2814 //so adjust BackPorch
2815 MS_BOOL bVsynInDE = FALSE;
2816 u16VsyncEnd = pDisplyout_Info->u16Vtt_out - u16VBackPorch;
2817 u16VsyncStart = u16VsyncEnd - u16VSyncWidth;
2818 if(u16VsyncStart < u16DEVEnd)
2819 {
2820 while(u16VsyncStart < u16DEVEnd)
2821 {
2822 u16VBackPorch = u16VBackPorch / 2;
2823 if(u16VBackPorch <= MINMUN_V_BACKPORCH)
2824 {
2825 u16VBackPorch = MINMUN_V_BACKPORCH;
2826 break;
2827 }
2828 u16VsyncEnd = pDisplyout_Info->u16Vtt_out - u16VBackPorch;
2829 u16VsyncStart = u16VsyncEnd - u16VSyncWidth;
2830 }
2831 bVsynInDE = TRUE;
2832 }
2833
2834 if(pDisplyout_Info->u16Vtt_out > u16OldVtt)
2835 {
2836 //Change to big one: Change Vtt first to avoid changed Vsync end > old Vtt
2837 _MDrv_XC_SetHttVtt_Steply(pInstance, EN_OUTPUT_TIMING_VTOTAL, pDisplyout_Info->u16Vtt_out, u16ChangeVttSteps, u16ChangeVttDelay);
2838 if(pXCResourcePrivate->stdrvXC_Display._bVSyncChanged || bVsynInDE)
2839 {
2840 _MDrv_XC_SetHVSync(pInstance, FALSE, u16VSyncWidth, u16VBackPorch, pDisplyout_Info->u16Vtt_out);
2841 }
2842 }
2843 else
2844 {
2845 if(pXCResourcePrivate->stdrvXC_Display._bVSyncChanged || bVsynInDE)
2846 {
2847 _MDrv_XC_SetHVSync(pInstance, FALSE, u16VSyncWidth, u16VBackPorch, pDisplyout_Info->u16Vtt_out);
2848 }
2849 _MDrv_XC_SetHttVtt_Steply(pInstance, EN_OUTPUT_TIMING_VTOTAL, pDisplyout_Info->u16Vtt_out, u16ChangeVttSteps, u16ChangeVttDelay);
2850 }
2851
2852 }
2853
2854 u16OPHtt = pDisplyout_Info->u16Htt_out; //mantis 1100871 u16OPHtt did not update after HTT changed
2855 #if FRC_INSIDE
2856 if ((pDisplyout_Info->u16Htt_out > 3000) && (pDisplyout_Info->u16Vtt_out > 2000) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq > 500))
2857 {
2858 if (pXCResourcePrivate->stdrvXC_MVideo_Context.enFRC_CurrentInputTiming == E_XC_FRC_InputTiming_2K1K)
2859 {
2860 // FHD 50/60 in case, OP timing is 2K2K, Htt is 2K
2861 u16OPHtt = u16OPHtt/2;
2862 }
2863 }
2864 #endif
2865
2866 // for high accurate input VFreq case, to avoid reconfig Vtt/Htt
2867 if(abs((MS_S16)u16OPHtt - (MS_S16)u16OldHtt) > CHANGE_HTT_TOLERANCE)
2868 {
2869 if(u16OPHtt > u16OldHtt)
2870 {
2871 //Change to big one: Change Htt first to avoid changed Hsync end > old Htt
2872 _MDrv_XC_SetHttVtt_Steply(pInstance, EN_OUTPUT_TIMING_HTOTAL, u16OPHtt, u16ChangeHttSteps, u16ChangeHttDelay);
2873 if(pXCResourcePrivate->stdrvXC_Display._bHSyncChanged)
2874 {
2875 _MDrv_XC_SetHVSync(pInstance, TRUE, u16HSyncWidth, u16HBackPorch, pDisplyout_Info->u16Htt_out);
2876 }
2877 }
2878 else
2879 {
2880 if(pXCResourcePrivate->stdrvXC_Display._bHSyncChanged)
2881 {
2882 _MDrv_XC_SetHVSync(pInstance, TRUE, u16HSyncWidth, u16HBackPorch, pDisplyout_Info->u16Htt_out);
2883 }
2884 _MDrv_XC_SetHttVtt_Steply(pInstance, EN_OUTPUT_TIMING_HTOTAL, u16OPHtt, u16ChangeHttSteps, u16ChangeHttDelay);
2885 }
2886 }
2887 if(pXCResourcePrivate->stdrvXC_Display._bHSyncChanged || pXCResourcePrivate->stdrvXC_Display._bVSyncChanged)
2888 {
2889 bManualVsyncMode = TRUE;
2890 _MDrv_XC_SetOutputVSyncMode(pInstance, TRUE);
2891 }
2892 else
2893 {
2894 bManualVsyncMode = FALSE;
2895 _MDrv_XC_SetOutputVSyncMode(pInstance, FALSE);
2896 }
2897 #if (PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB == 0)
2898 if ((!bManualVsyncMode) && (gSrcInfo[SUB_WINDOW].enInputSourceType == INPUT_SOURCE_SCALER_OP))//Temp solution: DE mode not change it
2899 {
2900 //patch for DIP capture in DIP goes with sub_ip/sub_op case, the sub capture window x/y need adjust if OP vtt changes
2901 MS_S16 s16VttDiff = u16OldVtt - pDisplyout_Info->u16Vtt_out;
2902 MS_S16 s16HttDiff = u16OldHtt - pDisplyout_Info->u16Htt_out;
2903 if((MS_S16)(gSrcInfo[SUB_WINDOW].stCapWin.y) >= s16VttDiff)
2904 {
2905 gSrcInfo[SUB_WINDOW].stCapWin.y -= s16VttDiff;
2906 }
2907 if((MS_S16)(gSrcInfo[SUB_WINDOW].stCapWin.x) >= s16HttDiff)
2908 {
2909 gSrcInfo[SUB_WINDOW].stCapWin.x -= s16HttDiff;
2910 }
2911 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "Change CapWin for source OP x/y=%u,%u, H/V Diff=%d,%d\n",
2912 gSrcInfo[SUB_WINDOW].stCapWin.x, gSrcInfo[SUB_WINDOW].stCapWin.y, s16HttDiff, s16VttDiff)
2913 MDrv_XC_SetCaptureWindow(pInstance, &gSrcInfo[SUB_WINDOW].stCapWin,SUB_WINDOW, FALSE);
2914 }
2915 #endif
2916 if ((MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED) && (!MDrv_SC_GetForceWrite(E_PANEL_MUTE)) )
2917 {
2918 _MLOAD_ENTRY(pInstance);
2919 if (!MDrv_XC_MLoad_Fire(pInstance, TRUE))
2920 {
2921 printf("Set Htt/vtt ML Fire Error!!!!\n ");
2922 }
2923 _MLOAD_RETURN(pInstance);
2924 }
2925 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "Htt_out, Vtt_out= %u , %u\n", pDisplyout_Info->u16Htt_out, pDisplyout_Info->u16Vtt_out)
2926
2927 #if (FRC_INSIDE)
2928 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.enPnl_Out_Timing_Mode == E_XC_PNL_CHG_HTOTAL )
2929 {
2930 MDrv_FRC_TGEN_SetHTotal(pInstance, pDisplyout_Info->u16Htt_out);
2931 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "Set Htt_out to TGEN, Htt_out= %u \n", pDisplyout_Info->u16Htt_out)
2932 }
2933 else if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.enPnl_Out_Timing_Mode == E_XC_PNL_CHG_VTOTAL )
2934 {
2935 if(pDisplyout_Info->u16Vtt_out < (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height+42))
2936 {
2937 pDisplyout_Info->u16Vtt_out = (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height+42);
2938 }
2939 MDrv_FRC_TGEN_SetVTotal(pInstance, pDisplyout_Info->u16Vtt_out);
2940 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "Set Vtt_out to TGEN, Vtt_out= %u \n", pDisplyout_Info->u16Vtt_out)
2941 }
2942
2943 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_FRC_INSIDE_240HZ)
2944 {
2945 if ((*pu16VFreq>=2380) && (*pu16VFreq<=2420))
2946 {
2947 MDrv_FRC_TGEN_SetVTotal(pInstance, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVTotal/2);
2948 }
2949 else if ((*pu16VFreq>=1980) && (*pu16VFreq<=2020))
2950 {
2951 MDrv_FRC_TGEN_SetVTotal(pInstance, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVTotal*60/50/2);
2952 }
2953 }
2954 else
2955 {
2956 MDrv_FRC_TGEN_SetVTotal(pInstance, pDisplyout_Info->u16Vtt_out);
2957 }
2958
2959 // 4K2K patch
2960 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
2961
2962 MST_PANEL_INFO_t stFRCPanelInfo;
2963 //XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "@@@ 4K2K panel patch for FRC TGEN\n");
2964
2965 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_B & E_XC_INIT_MISC_B_HDMITX_ENABLE)
2966 {
2967 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.u8PanelHSyncWidth = pXCResourcePrivate->stdrvXC_Display._u16DefaultHSyncWidth;
2968 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.u8PanelHSyncBackPorch = pXCResourcePrivate->stdrvXC_Display._u16DefaultHSyncBackPorch;
2969 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.u8PanelVSyncWidth = pXCResourcePrivate->stdrvXC_Display._u16DefaultVSyncWidth;
2970 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.u8PanelVSyncBackPorch = pXCResourcePrivate->stdrvXC_Display._u16DefaultVSyncBackPorch;
2971 }
2972
2973 MDrv_FRC_PNLInfo_Transform(pInstance, &pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo,&pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc, &stFRCPanelInfo);
2974 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_FRC_INSIDE_4K1K_120HZ)
2975 {
2976 pDisplyout_Info->u16Vtt_out = stFRCPanelInfo.u16VTotal;
2977 }
2978 MDrv_FRC_Tx_SetTgen(pInstance, &stFRCPanelInfo);
2979 #endif
2980
2981 #endif
2982 }
2983
_MDrv_XC_Set_FPLL_Thresh_Mode(void)2984 static void _MDrv_XC_Set_FPLL_Thresh_Mode(void)
2985 {
2986 #if FPLL_THRESH_MODE_SUPPORT
2987 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2988 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2989 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
2990 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
2991 LPLL_BK_STORE;
2992 LPLL_BK_SWITCH(0x00);
2993
2994 #ifdef UFO_XC_FB_LEVEL
2995 if(pXCResourcePrivate->stdrvXC_Display._bFPLL_Thresh_Mode
2996 && ((gSrcInfo[MAIN_WINDOW].eFBLevel == E_XC_FB_LEVEL_FB)
2997 || gSrcInfo[MAIN_WINDOW].Status2.bMVOPHSKMode)
2998 && gSrcInfo[MAIN_WINDOW].bEnableFPLL
2999 )
3000 #else
3001 if (pXCResourcePrivate->stdrvXC_Display._bFPLL_Thresh_Mode
3002 && ( (!(gSrcInfo[MAIN_WINDOW].bFBL || gSrcInfo[MAIN_WINDOW].bR_FBL) ) || gSrcInfo[MAIN_WINDOW].Status2.bMVOPHSKMode) && gSrcInfo[MAIN_WINDOW].bEnableFPLL)
3003 #endif
3004 {
3005 MDrv_Write2Byte(L_BK_LPLL(0x1F), 0x2EE0);
3006 MDrv_WriteRegBit(H_BK_LPLL(0x78), ENABLE, BIT(4));
3007 }
3008 else
3009 {
3010 MDrv_Write2Byte(L_BK_LPLL(0x1F), 0x0080);
3011 MDrv_WriteRegBit(H_BK_LPLL(0x78), DISABLE, BIT(4));
3012 }
3013 LPLL_BK_RESTORE;
3014 #endif
3015 }
3016
_MDrv_XC_PQ_Set_FPLL_Thresh_Mode(void * pInstance)3017 static void _MDrv_XC_PQ_Set_FPLL_Thresh_Mode(void *pInstance)
3018 {
3019 #if FPLL_THRESH_MODE_SUPPORT
3020 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3021 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3022 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
3023 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
3024
3025 #ifdef UFO_XC_FB_LEVEL
3026 if(pXCResourcePrivate->stdrvXC_Display._bFPLL_Thresh_Mode
3027 && ((gSrcInfo[MAIN_WINDOW].eFBLevel == E_XC_FB_LEVEL_FB)
3028 || gSrcInfo[MAIN_WINDOW].Status2.bMVOPHSKMode)
3029 && gSrcInfo[MAIN_WINDOW].bEnableFPLL
3030 )
3031 #else
3032 if (pXCResourcePrivate->stdrvXC_Display._bFPLL_Thresh_Mode
3033 && ( (!(gSrcInfo[MAIN_WINDOW].bFBL || gSrcInfo[MAIN_WINDOW].bR_FBL) ) || gSrcInfo[MAIN_WINDOW].Status2.bMVOPHSKMode) && gSrcInfo[MAIN_WINDOW].bEnableFPLL)
3034 #endif
3035 {
3036 if (_fpPQSetFPLLThreshMode != NULL)
3037 {
3038 _fpPQSetFPLLThreshMode(MAIN_WINDOW);
3039 if (MDrv_XC_Is_SubWindowEanble(pInstance))
3040 {
3041 _fpPQSetFPLLThreshMode(SUB_WINDOW);
3042 }
3043 }
3044 }
3045 #endif
3046 }
3047
MApi_XC_SetOutTimingMode_U2(void * pInstance,E_XC_PNL_OUT_TIMING_MODE enPnl_Out_Timing_Mode)3048 void MApi_XC_SetOutTimingMode_U2(void* pInstance, E_XC_PNL_OUT_TIMING_MODE enPnl_Out_Timing_Mode)
3049 {
3050 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3051 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3052 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
3053
3054 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
3055 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
3056 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.enPnl_Out_Timing_Mode = enPnl_Out_Timing_Mode;
3057 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
3058 }
3059
MApi_XC_SetOutTimingMode(E_XC_PNL_OUT_TIMING_MODE enPnl_Out_Timing_Mode)3060 void MApi_XC_SetOutTimingMode(E_XC_PNL_OUT_TIMING_MODE enPnl_Out_Timing_Mode)
3061 {
3062 if (pu32XCInst == NULL)
3063 {
3064 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
3065 return;
3066 }
3067
3068 stXC_SET_OUTPUT_TIMING_MODE XCArgs;
3069 XCArgs.enPnl_Out_Timing_Mode = enPnl_Out_Timing_Mode;
3070
3071 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_OUTPUT_TIMING_MODE, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
3072 {
3073 printf("Obtain XC engine fail\n");
3074 return;
3075 }
3076 else
3077 {
3078 return;
3079 }
3080 }
3081
MDrv_SC_FBL_Calc_Vtt(void * pInstance,XC_SetTiming_Info * pTimingInfo,SCALER_WIN eWindow)3082 MS_U16 MDrv_SC_FBL_Calc_Vtt(void *pInstance, XC_SetTiming_Info *pTimingInfo, SCALER_WIN eWindow)
3083 {
3084 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3085 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3086 MS_U16 u16Vde_in, u16Vde_out, u16Vtt_in, u16Vtt_out;
3087 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
3088 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
3089 u16Vde_in = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_06_L) & 0x1FFF;
3090
3091 if ((MDrv_SC_Get_DE_Bypass_Mode(pInstance, eWindow)) && (u16Vde_in == 0x1FFF))
3092 {
3093 MS_WINDOW_TYPE stWinType;
3094 memset(&stWinType, 0, sizeof(MS_WINDOW_TYPE));
3095 MDrv_XC_PCMonitor_Get_Dvi_Hdmi_De_Info(pInstance, eWindow, &stWinType);
3096 u16Vde_in = stWinType.height;
3097 }
3098
3099 if(u16Vde_in == 0) // avoid divide by zero.
3100 {
3101 return 0;
3102 }
3103 // Remove storage Port later ( Driver level does not know what storagePort is )
3104 // Merge MVD port and Storage port
3105 if( pTimingInfo->bMVOPSrc)
3106 {
3107 u16Vtt_in = pTimingInfo->u16InputVTotal;//MDrv_Read2Byte(VOP_FRAME_VCOUNT) & 0x7FF;
3108 }
3109 else if(IsSrcTypeAnalog(gSrcInfo[eWindow].enInputSourceType) || IsSrcTypeHDMI(gSrcInfo[eWindow].enInputSourceType))
3110 {
3111 u16Vtt_in = MDrv_XC_PCMonitor_Get_Vtotal(pInstance, eWindow);
3112 }
3113 else
3114 {
3115 u16Vtt_in = Hal_SC_ip_get_verticaltotal(pInstance, MAIN_WINDOW);//MDrv_Read2Byte(L_BK_IP1F2(0x1f)) & MST_V_TOTAL_MASK;
3116 }
3117
3118 //MDrv_WriteByte(BK_SELECT_00, REG_BANK_VOP);
3119 //u16Vde_out = (MDrv_Read2Byte(L_BK_VOP(0x0B))&0x7FF) - (MDrv_Read2Byte(L_BK_VOP(0x0A))&0x7FF) + 1;
3120 u16Vde_out = (SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0B_L)&VOP_DISPLAY_VEND_MASK) - (SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0A_L)&VOP_DISPLAY_VSTART_MASK) + 1;
3121 MS_ASSERT(u16Vde_in);
3122
3123 u16Vtt_out = (MS_U16)(((MS_U32)u16Vtt_in * u16Vde_out + u16Vde_in/2) / u16Vde_in);
3124
3125 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "Vde_in= 0x%X (%u)\n", u16Vde_in, u16Vde_in)
3126 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "Vde_out= 0x%X (%u)\n", u16Vde_out, u16Vde_out)
3127 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "Vtt_in= 0x%X (%u)\n", u16Vtt_in, u16Vtt_in)
3128
3129 return u16Vtt_out;
3130 }
3131
MDrv_SC_Set_LockFreeze_Point(void * pInstance,XC_SetTiming_Info * pTimingInfo,MS_U16 u16Vtt_out,SCALER_WIN eWindow)3132 void MDrv_SC_Set_LockFreeze_Point(void *pInstance, XC_SetTiming_Info *pTimingInfo, MS_U16 u16Vtt_out, SCALER_WIN eWindow)
3133 {
3134 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3135 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3136 MS_U16 u16LockPoint = 0, u16FreezePoint = 0;
3137 MS_BOOL bForceReadBank = FALSE;
3138 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
3139 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
3140 if( !gSrcInfo[eWindow].bFBL)
3141 {
3142 #ifdef UFO_XC_FB_LEVEL
3143 if((gSrcInfo[MAIN_WINDOW].eFBLevel == E_XC_FB_LEVEL_FBL)||(gSrcInfo[MAIN_WINDOW].eFBLevel == E_XC_FB_LEVEL_RFBL_DI))
3144 #else
3145 if(gSrcInfo[eWindow].bR_FBL) //for M10 Reguest FBL mode, it doesn't the same with FBL
3146 #endif
3147 {
3148 u16LockPoint = u16Vtt_out;
3149 u16FreezePoint = u16LockPoint - 2;
3150
3151 // Setip Y lock
3152 #if (HW_DESIGN_4K2K_VER == 6)
3153 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_09_L, 0x5, BITMASK(3:0));
3154 #else
3155 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_09_L, 0x2, BITMASK(3:0));
3156 #endif
3157
3158 #if (HW_DESIGN_4K2K_VER == 4)
3159 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE)
3160 {
3161 gSrcInfo[eWindow].u8DelayLines = 8;
3162 }
3163 else
3164 #endif
3165 #if (HW_DESIGN_4K2K_VER == 6)
3166
3167 // Setup delay line
3168 if((pXCResourcePrivate->stdrvXC_Display._bEnableMCNR[eWindow])
3169 && (!pTimingInfo->bInterlace))
3170 {
3171 gSrcInfo[eWindow].u8DelayLines = 0x10;//rfbl+uc+pmode, need to adjust delay+1
3172 }
3173 else
3174 {
3175 gSrcInfo[eWindow].u8DelayLines = 0xF;
3176 }
3177 #else
3178 // Setup delay line
3179 if((pXCResourcePrivate->stdrvXC_Display._bEnableMCNR[eWindow])
3180 && (!pTimingInfo->bInterlace))
3181 {
3182 gSrcInfo[eWindow].u8DelayLines = 7;//rfbl+uc+pmode, need to adjust delay+1
3183 }
3184 else
3185 {
3186 gSrcInfo[eWindow].u8DelayLines = 6;
3187 }
3188 #endif
3189 bForceReadBank = FALSE;
3190 }
3191 else
3192 {
3193 /* 2010-07-05
3194 * according to the discussion from designer, we have the following formula:
3195 * freeze point = vde_end (reg_value) + 1;
3196 * lock = vde_end(reg_value) + 3;
3197 */
3198 u16FreezePoint = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_07_L) + 1;
3199 u16LockPoint = u16FreezePoint + 2;
3200
3201 // no matter progressive or interlace
3202 // in FB mode we set to 0x5 (originally progressive = 0x3, interlace = 0x4)
3203 // but in Open HDR mode(with MVOP DE mode)
3204 // if we set to 3 or 4 it will be too late for autodownload to work.
3205 // so we change to 5 based upon CC's experiement suggestion.
3206 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_09_L, 0x0C, BITMASK(3:0));
3207
3208 if((gSrcInfo[eWindow].eDeInterlaceMode == MS_DEINT_2DDI_AVG) ||
3209 (gSrcInfo[eWindow].eDeInterlaceMode == MS_DEINT_2DDI_BOB))
3210 {
3211 gSrcInfo[eWindow].u8DelayLines = 1; // 5
3212 }
3213 else
3214 {
3215 gSrcInfo[eWindow].u8DelayLines = 2;
3216 }
3217
3218 //if HV mode with capture size 0x1fff, we need to adjust delay line to 6.
3219 if ((MDrv_XC_GetHdmiSyncMode(pInstance) == HDMI_SYNC_HV) &&
3220 (IsSrcTypeHDMI(gSrcInfo[eWindow].enInputSourceType)) &&
3221 (!pTimingInfo->bInterlace))
3222 {
3223 MS_WINDOW_TYPE stWinType;
3224 memset(&stWinType, 0, sizeof(MS_WINDOW_TYPE));
3225 MDrv_XC_PCMonitor_Get_Dvi_Hdmi_De_Info(pInstance, eWindow, &stWinType);
3226
3227 if(HVMODE_HDE_VALIDATION(stWinType.width))
3228 {
3229 gSrcInfo[eWindow].u8DelayLines = 6;
3230 }
3231 }
3232
3233 bForceReadBank = FALSE;
3234 }
3235 // Setup delay line
3236 Hal_SC_set_delayline(pInstance, gSrcInfo[eWindow].u8DelayLines, eWindow );
3237 }
3238 else
3239 {
3240 //New method for lock point in FBL
3241 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_09_L, 0x2, BITMASK(3:0));
3242
3243 MS_U16 u16Vde_in = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_06_L) & 0x1FFF;
3244
3245 if(pTimingInfo->bInterlace)
3246 {
3247 if (u16Vde_in <= 580)
3248 {
3249 gSrcInfo[eWindow].u8DelayLines = 6;
3250 }
3251 else
3252 {
3253 gSrcInfo[eWindow].u8DelayLines = 7;
3254 }
3255 bForceReadBank = FALSE;
3256 }
3257 else
3258 {
3259 MS_U32 u32VPSDRatio = 0;
3260 if (eWindow == MAIN_WINDOW)
3261 {
3262 u32VPSDRatio = SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_09_L) & 0xFFFFFF;
3263 }
3264 else
3265 {
3266 u32VPSDRatio = SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_29_L) & 0xFFFFFF;
3267 }
3268
3269 if((u32VPSDRatio & 0x3FFFFFL) > 0x100000)
3270 {
3271 //printf("---scaling down----\n");
3272 gSrcInfo[eWindow].u8DelayLines = DELAY_LINE_SC_DOWN;//8;
3273 }
3274 else
3275 {
3276 //printf("----scaling up----\n");
3277 gSrcInfo[eWindow].u8DelayLines = DELAY_LINE_SC_UP;// 7;
3278 }
3279 bForceReadBank = TRUE;
3280 }
3281
3282 if ((MDrv_SC_Get_DE_Bypass_Mode(pInstance, eWindow)) && (u16Vde_in == 0x1FFF))
3283 {
3284 gSrcInfo[eWindow].u8DelayLines = 12;
3285 }
3286
3287 Hal_SC_set_delayline(pInstance, gSrcInfo[eWindow].u8DelayLines, eWindow );
3288
3289 //SC0F_55 = SC10_0D, SC0F_54 = SC0F_55 -2
3290 u16LockPoint = u16Vtt_out;
3291 u16FreezePoint = u16LockPoint - 2;
3292 }
3293
3294 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
3295 MS_U16 u16IvsOvs = MDrv_Read2Byte(L_BK_LPLL(0x0C)) & 0xFF00;
3296 if ((pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFRCEnabled) && // FRC + 4K2K case needs to lock phase, FRC + FHD case use lockVfreq mode
3297 (IS_OUTPUT_4K2K(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height)) &&
3298 (u16IvsOvs == 0x0000))
3299 {
3300 u16LockPoint = u16LockPoint/2;
3301 u16FreezePoint = u16FreezePoint/2;
3302 }
3303 #endif
3304
3305 // Only turn on when FBL (not RFBL) and the signal is progressive mode.
3306 // to force R bank to be at the first frame
3307 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, (bForceReadBank? ((MS_U16)0x8)<<8 : 0), BITMASK(11:8));
3308
3309 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_56_L, BIT(1), BIT(1)); //Using new ovs_ref
3310 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3311 if (psXCInstPri->u32DeviceID == 0)
3312 #endif
3313 {
3314 #if (HW_DESIGN_HDMITX_VER == 1)//Maserati +Raptor HDMITX case
3315 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_B & E_XC_INIT_MISC_B_HDMITX_ENABLE)
3316 {
3317 MS_U32 u32VTT=SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_36_L, VOP_VTT_MASK)+1;
3318 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_55_L, u32VTT/2);
3319 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_54_L, u32VTT/2-1); //FreezePoint = LockPoint-2
3320 }
3321 else
3322 #endif
3323 {
3324 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_55_L, (u16LockPoint-1)&0xFFF);
3325 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_54_L, (u16FreezePoint-1)&0xFFF); //FreezePoint = LockPoint-2
3326 }
3327 }
3328 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "LockPoint= 0x%X (%u)\n", u16LockPoint, u16LockPoint)
3329 }
3330
MApi_XC_SetLockPoint_U2(void * pInstance,MS_U16 u16LockPoint,SCALER_WIN eWindow)3331 void MApi_XC_SetLockPoint_U2(void* pInstance, MS_U16 u16LockPoint, SCALER_WIN eWindow)
3332 {
3333 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3334 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3335 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
3336 _XC_ENTRY(pInstance);
3337 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
3338 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
3339
3340 UNUSED(eWindow);
3341
3342 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_55_L, (u16LockPoint-1)&0x7FF);
3343 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_54_L, (u16LockPoint-2)&0x7FF); //FreezePoint = LockPoint-2
3344
3345 _XC_RETURN(pInstance);
3346 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
3347 }
3348
MApi_XC_SetLockPoint(MS_U16 u16LockPoint,SCALER_WIN eWindow)3349 void MApi_XC_SetLockPoint(MS_U16 u16LockPoint, SCALER_WIN eWindow)
3350 {
3351 if (pu32XCInst == NULL)
3352 {
3353 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
3354 return;
3355 }
3356
3357 stXC_SET_LOCK_POINT XCArgs;
3358 XCArgs.u16LockPoint = u16LockPoint;
3359 XCArgs.eWindow = eWindow;
3360
3361 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_LOCK_POINT, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
3362 {
3363 printf("Obtain XC engine fail\n");
3364 return;
3365 }
3366 else
3367 {
3368 return;
3369 }
3370
3371 }
3372
MDrv_Scaler_SetPhaseLimit(void * pInstance,MS_U8 u8Lpll_bank)3373 void MDrv_Scaler_SetPhaseLimit(void *pInstance, MS_U8 u8Lpll_bank)
3374 {
3375 MS_U16 u16PhaseLimit = PHASE_OFFSET_LIMIT;
3376 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3377 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3378 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
3379 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
3380 //when the dclk max-min value is too small, the panel has hw limitation. we should use
3381 //much safer parameter to do the FPLL
3382 //for now, we only found only AU46_T460hw03v1_HD has this problem.
3383 //So the value:0x0A is coming from AU46_T460hw03v1_HD
3384 if((pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u32MaxSET - pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u32MinSET)
3385 < GATE_PHASELIMIT)
3386 {
3387 u16PhaseLimit = 0x1000;
3388 }
3389 #if (HW_DESIGN_HDMITX_VER == 2)//Maxim inside HDMITX case
3390 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_B & E_XC_INIT_MISC_B_HDMITX_ENABLE)
3391 {
3392 u16PhaseLimit = PHASE_OFFSET_LIMIT_HDMITX;
3393 }
3394 #endif
3395 if (pXCResourcePrivate->stdrvXC_Display._bFpllCusFlag[E_FPLL_FLAG_PHASELIMIT])
3396 {
3397 u16PhaseLimit = (MS_U16)pXCResourcePrivate->stdrvXC_Display._u32FpllCusData[E_FPLL_FLAG_PHASELIMIT];
3398 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "user forces Phase Limit = 0x%X\n", u16PhaseLimit);
3399 }
3400
3401
3402 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "Phase Limit = 0x%X\n", u16PhaseLimit);
3403
3404 LPLL_BK_STORE;
3405 if(u8Lpll_bank)
3406 LPLL_BK_SWITCH(0x01);
3407 else
3408 LPLL_BK_SWITCH(0x00);
3409
3410 MDrv_Write2Byte( L_BK_LPLL(0x0A), u16PhaseLimit);
3411 LPLL_BK_RESTORE;
3412 }
3413
MDrv_Scaler_FastFrameLock(void * pInstance,MS_U16 u16InputVFreq,MS_U16 u16OutputVFreq)3414 void MDrv_Scaler_FastFrameLock(void *pInstance, MS_U16 u16InputVFreq,MS_U16 u16OutputVFreq)
3415 {
3416 MS_U16 u16temp;
3417 MS_BOOL bCnt;
3418
3419 //when calling MApi_XC_SetPanelTiming, input source is disabled
3420 //MApi_XC_DisableInputSource(TRUE, MAIN_WINDOW);
3421 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3422 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3423
3424 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_56_L, 0, BIT(0));
3425 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_56_L, 1, BIT(0));
3426 MDrv_SC_set_fpll(pInstance, ENABLE, DISABLE, 0);//enable FPLL
3427 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "Enable Fast FPLL\n")
3428
3429 u16temp = 0;
3430 bCnt = 0;
3431
3432 while(1)
3433 {
3434 u16temp++;
3435 MsOS_DelayTask(1);
3436 //if(MDrv_ReadByte(H_BK_S_VOP(0x56)) & BIT(7)) // get vcnt freeze status
3437 if(SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_56_H) & BIT(7)) // get vcnt freeze status
3438 {
3439 //need wait vcnt down
3440 bCnt = 1 ;
3441 break;
3442 }
3443 else if(u16temp >((10000/u16OutputVFreq)+2)) // wait at lease one output vsync
3444 {
3445 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_56_L, 0x08, BIT(3)); //SW Reset vcnt freeze
3446 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_56_L, 0x00, BIT(3));
3447 break;
3448 }
3449 }
3450
3451 u16temp = 0;
3452 if(bCnt)
3453 {
3454 //while(MDrv_ReadByte(H_BK_S_VOP(0x56)) & BIT(7))
3455 while(SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_56_H) & BIT(7))
3456 {
3457 u16temp++;
3458 MsOS_DelayTask(1);
3459 if(u16temp > ((10000/u16InputVFreq)+2))
3460 {
3461 //MDrv_WriteRegBit(L_BK_S_VOP(0x56), 1, BIT(3)); //SW Reset vcnt freeze
3462 //MDrv_WriteRegBit(L_BK_S_VOP(0x56), 0, BIT(3));
3463 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_56_L, 0x08, BIT(3)); //SW Reset vcnt freeze
3464 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_56_L, 0x00, BIT(3));
3465 break;
3466 }
3467 }
3468 }
3469
3470 //MDrv_WriteRegBit(L_BK_S_VOP(0x56), 1, BIT(3)); //SW Reset vcnt freeze
3471 //MDrv_WriteRegBit(L_BK_S_VOP(0x56), 0, BIT(3));
3472
3473 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "temp= %u\n", u16temp)
3474 }
3475
MDrv_SC_Set_Output_Dclk_Slowly(void * pInstance,MS_U32 u32PllSet,MS_U32 u32Steps,MS_U32 u32DelayMs,SCALER_WIN eWindow)3476 void MDrv_SC_Set_Output_Dclk_Slowly(void *pInstance, MS_U32 u32PllSet, MS_U32 u32Steps, MS_U32 u32DelayMs, SCALER_WIN eWindow)
3477 {
3478 //slowly move to target
3479 MS_U32 u32PLLStep, u32OrigLPLL = 0;
3480 MS_U8 i;
3481 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3482 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3483 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
3484 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
3485 LPLL_BK_STORE;
3486 LPLL_BK_SWITCH(0x00);
3487 u32OrigLPLL = MDrv_Read4Byte(L_BK_LPLL(0x0F));
3488
3489 u32PllSet = u32PllSet & 0xFFFFFF;
3490
3491 if (pXCResourcePrivate->stdrvXC_Display._bFpllCusFlag[E_FPLL_FLAG_INITSETSTEP]
3492 && pXCResourcePrivate->stdrvXC_Display._u32FpllCusData[E_FPLL_FLAG_INITSETSTEP])
3493 {
3494 u32Steps = pXCResourcePrivate->stdrvXC_Display._u32FpllCusData[E_FPLL_FLAG_INITSETSTEP];
3495 }
3496 if (pXCResourcePrivate->stdrvXC_Display._bFpllCusFlag[E_FPLL_FLAG_INITSETDELAY]
3497 && pXCResourcePrivate->stdrvXC_Display._u32FpllCusData[E_FPLL_FLAG_INITSETDELAY])
3498 {
3499 u32DelayMs = pXCResourcePrivate->stdrvXC_Display._u32FpllCusData[E_FPLL_FLAG_INITSETDELAY];
3500 }
3501
3502 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "SetDCLK: Steps=%tu, DelayMs=%tu\n", (ptrdiff_t)u32Steps, (ptrdiff_t)u32DelayMs);
3503
3504 u32PLLStep = abs(u32PllSet - u32OrigLPLL) / u32Steps;
3505
3506 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.enPnl_Out_Timing_Mode == E_XC_PNL_CHG_DCLK )
3507 {
3508 if(u32PLLStep > (0x50000/u32Steps))
3509 {
3510 for(i=1; i<(u32Steps+1); i++)
3511 {
3512 if(u32DelayMs != 0)
3513 {
3514 MDrv_XC_DelayAndWaitOutVsync(pInstance, u32DelayMs, eWindow); // change output dclk when blanking
3515 }
3516 else
3517 {
3518 if ((MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED) && (!MDrv_SC_GetForceWrite(E_PANEL_MUTE)) )
3519 {
3520 MDrv_XC_wait_output_vsync(pInstance, 2, 50, eWindow); // change output dclk when blanking
3521 }
3522 }
3523 if(u32PllSet > u32OrigLPLL)
3524 {
3525 //add
3526 MDrv_Write3Byte(L_BK_LPLL(0x0F), u32OrigLPLL + (u32PLLStep * i));
3527 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "Slow steps add 0x%tx\n",(ptrdiff_t)(u32OrigLPLL + (u32PLLStep * i)));
3528 }
3529 else
3530 {
3531 //minus
3532 MDrv_Write3Byte(L_BK_LPLL(0x0F), u32OrigLPLL - (u32PLLStep * i));
3533 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "Slow steps minus 0x%tx\n", (ptrdiff_t)(u32OrigLPLL - (u32PLLStep * i)));
3534 }
3535 }
3536 }
3537 else
3538 {
3539 // direct set
3540 if ((MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED) && (!MDrv_SC_GetForceWrite(E_PANEL_MUTE)) )
3541 {
3542 MDrv_XC_wait_output_vsync(pInstance, 1, 50, eWindow); // change output dclk when blanking
3543 }
3544 MDrv_Write3Byte(L_BK_LPLL(0x0F), u32PllSet);
3545 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "Direct set to 0x%tx\n", (ptrdiff_t)u32PllSet);
3546 }
3547 }
3548 else
3549 {
3550 #if 1 //leon test
3551 while(abs(u32PllSet - u32OrigLPLL) > 0x3200)
3552 {
3553 if(u32PllSet > u32OrigLPLL)
3554 {
3555 u32OrigLPLL += 0x3200;
3556 }
3557 else
3558 {
3559 u32OrigLPLL -= 0x3200;
3560 }
3561 MsOS_DelayTask(1);
3562 MDrv_Write3Byte(L_BK_LPLL(0x0F), u32OrigLPLL);
3563 }
3564
3565 MDrv_Write3Byte(L_BK_LPLL(0x0F), u32PllSet);
3566 #else
3567 if(abs(u32PllSet - u32OrigLPLL) < 0x3200)
3568 MDrv_Write3Byte(L_BK_LPLL(0x0F), u32OrigLPLL);
3569 else
3570 MDrv_Write3Byte(L_BK_LPLL(0x0F), u32PllSet);
3571 #endif
3572
3573 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "Direct set to 0x%tx\n", (ptrdiff_t)u32PllSet);
3574 }
3575
3576 LPLL_BK_RESTORE;
3577 }
3578
3579 //-------------------------------------------------------------------------------------------------
3580 /// Get the time for scaler output one frame(Vertical Period)
3581 /// @return @ref MS_U16 return output vertical Period(unit: ms)
3582 //-------------------------------------------------------------------------------------------------
_MDrv_SC_GetOutputVPeriod(void * pInstance)3583 MS_U16 _MDrv_SC_GetOutputVPeriod(void *pInstance)
3584 {
3585 MS_U16 u16VFreq = MDrv_SC_GetOutputVFreqX100(pInstance);
3586 return ((100000+u16VFreq/2)/u16VFreq); //Period = 1000/(vfreq/100)
3587 }
3588
3589 //-----------------------------------------------------------------------------
3590 // below functions are for FSM FPLL
3591 //-----------------------------------------------------------------------------
_MDrv_Scaler_GetAVDStatus(void)3592 static MS_U16 _MDrv_Scaler_GetAVDStatus(void)
3593 {
3594 return Hal_SC_GetAVDStatus();
3595 }
3596
MDrv_Scaler_GetLPLLPhaseOfs(MS_U32 * pu32UpOfs,MS_BOOL * bDir)3597 void MDrv_Scaler_GetLPLLPhaseOfs(MS_U32* pu32UpOfs, MS_BOOL *bDir)
3598 {
3599 LPLL_BK_STORE;
3600 LPLL_BK_SWITCH(0x00);
3601
3602 *pu32UpOfs = (MS_U32)MDrv_Read2Byte(L_BK_LPLL(0x11));
3603 *bDir = MDrv_ReadRegBit(L_BK_LPLL(0x12), BIT(0));
3604 LPLL_BK_RESTORE;
3605 }
3606
MDrv_Scaler_GetLPLLPrdOfs(MS_U32 * pu32UpOfs,MS_BOOL * bDir)3607 void MDrv_Scaler_GetLPLLPrdOfs(MS_U32* pu32UpOfs, MS_BOOL *bDir)
3608 {
3609 LPLL_BK_STORE;
3610 LPLL_BK_SWITCH(0x00);
3611
3612 *pu32UpOfs = (MS_U32)MDrv_Read2Byte(L_BK_LPLL(0x13));
3613 *bDir = MDrv_ReadRegBit(L_BK_LPLL(0x14), BIT(0));
3614 LPLL_BK_RESTORE;
3615 }
3616
3617 //judge whether the fpll is done or not.
MDrv_Scaler_GetFPLLDoneStatus(void * pInstance)3618 MS_BOOL MDrv_Scaler_GetFPLLDoneStatus(void *pInstance)
3619 {
3620 MS_U32 u32PhaseOfs,u32PrdOfs;
3621 MS_BOOL bPhaseDir,bPrdDir;
3622
3623 MDrv_Scaler_GetLPLLPhaseOfs(&u32PhaseOfs,&bPhaseDir);
3624 MDrv_Scaler_GetLPLLPrdOfs(&u32PrdOfs,&bPrdDir);
3625
3626 //printf("Framelock: (%lu,%u,%lu,%u)\n",u32PhaseOfs,bPhaseDir,u32PrdOfs,bPrdDir);
3627 if(MDrv_ReadRegBit(L_BK_LPLL(0x0C), BIT(3)) &&
3628 (u32PhaseOfs <= FPLL_PHASE_VAR_LIMIT) &&
3629 (u32PrdOfs <= FPLL_PRD_VAR_LIMIT))
3630 {
3631 //printf("OK.\n");
3632 return TRUE;
3633 }
3634 else
3635 {
3636 //printf("No.\n");
3637 return FALSE;
3638 }
3639 }
3640
MDrv_Scaler_IsPRDLock(void * pInstance,MS_U16 * u16OrigPrd)3641 MS_BOOL MDrv_Scaler_IsPRDLock(void *pInstance, MS_U16 *u16OrigPrd)
3642 {
3643 MS_U16 u16NewPrd = 0;
3644 MS_U16 u16NewPhase = 0;
3645 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
3646 MS_U32 u32NewPhaseDiff = 0;
3647 #endif
3648 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3649 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3650 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
3651 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
3652 LPLL_BK_STORE;
3653 LPLL_BK_SWITCH(0x00);
3654
3655 u16NewPrd = MDrv_Read2Byte(L_BK_LPLL(0x13));
3656 u16NewPhase = MDrv_Read2Byte(L_BK_LPLL(0x11));
3657 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
3658 u32NewPhaseDiff = MDrv_Read4Byte(L_BK_LPLL(0x3D));
3659 #endif
3660
3661 LPLL_BK_RESTORE;
3662 #if(PHASE_LOCK_EN)
3663 if( (u16NewPhase < (pXCResourcePrivate->stdrvXC_Display._bFpllCusFlag[E_FPLL_FLAG_PHASELIMIT] ? (pXCResourcePrivate->stdrvXC_Display._u32FpllCusData[E_FPLL_FLAG_PHASELIMIT]) : (PHASE_OFFSET_LIMIT)))
3664 && (u16NewPrd < FPLL_PRD_THRESHOLD) && (abs(*u16OrigPrd - u16NewPrd) < FPLL_PRD_VAR_LIMIT))
3665 #else
3666 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
3667 if((pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFRCEnabled && (u32NewPhaseDiff < PHASE_OFFSET_LIMIT)) || // FRC enable case
3668 ((!pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFRCEnabled) && (u16NewPrd < FPLL_PRD_THRESHOLD) && (abs(*u16OrigPrd - u16NewPrd) < FPLL_PRD_VAR_LIMIT))) // non-FRC case
3669 #else
3670 if((u16NewPrd < FPLL_PRD_THRESHOLD) && (abs(*u16OrigPrd - u16NewPrd) < FPLL_PRD_VAR_LIMIT))
3671 #endif
3672 #endif
3673 {
3674 *u16OrigPrd = u16NewPrd;
3675 return TRUE;
3676 }
3677 else
3678 {
3679 *u16OrigPrd = u16NewPrd;
3680 return FALSE;
3681 }
3682 }
3683
MDrv_Scaler_IsPhaseStable(void * pInstance,MS_U16 * u16OrigPhase)3684 MS_BOOL MDrv_Scaler_IsPhaseStable(void *pInstance, MS_U16 *u16OrigPhase)
3685 {
3686 MS_U16 u16NewPhase = 0;
3687 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3688 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3689 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
3690 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
3691 LPLL_BK_STORE;
3692 LPLL_BK_SWITCH(0x00);
3693
3694 u16NewPhase = MDrv_Read2Byte(L_BK_LPLL(0x11));
3695 LPLL_BK_RESTORE;
3696
3697
3698 if( (abs(*u16OrigPhase - u16NewPhase) < FPLL_PHASE_VAR_LIMIT) &&
3699 (u16NewPhase < (pXCResourcePrivate->stdrvXC_Display._bFpllCusFlag[E_FPLL_FLAG_PHASELIMIT] ? (pXCResourcePrivate->stdrvXC_Display._u32FpllCusData[E_FPLL_FLAG_PHASELIMIT]) : (PHASE_OFFSET_LIMIT))) )
3700 {
3701 *u16OrigPhase = u16NewPhase;
3702 return TRUE;
3703 }
3704 else
3705 {
3706 *u16OrigPhase = u16NewPhase;
3707 return FALSE;
3708 }
3709 }
3710
MDrv_Scaler_SetPhaseLock_Thresh(MS_U16 u16Thresh,MS_U8 u8Lpll_bank)3711 void MDrv_Scaler_SetPhaseLock_Thresh(MS_U16 u16Thresh, MS_U8 u8Lpll_bank)
3712 {
3713 LPLL_BK_STORE;
3714 if(u8Lpll_bank)
3715 LPLL_BK_SWITCH(0x01);
3716 else
3717 LPLL_BK_SWITCH(0x00);
3718 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "u16Thresh= %u\n", u16Thresh);
3719 MDrv_Write2ByteMask( L_BK_LPLL(0x05), u16Thresh<<8, 0xF00);
3720 LPLL_BK_RESTORE;
3721 }
3722
_MDrv_SC_FPLL_GetMCNRDelayTime(void * pInstance)3723 static MS_U16 _MDrv_SC_FPLL_GetMCNRDelayTime(void *pInstance)
3724 {
3725 MS_U16 u16DelayCount = 0;
3726 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3727 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3728 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
3729 MS_U32 u32VFreq = 0;
3730 MS_U16 u16IPVsyncPeriod = 0;
3731 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
3732 if(pXCResourcePrivate->stdrvXC_Display._bEnableMCNR[MAIN_WINDOW])
3733 {
3734 u16DelayCount = MDrv_XC_TransFrameNumToFactor(pInstance, gSrcInfo[MAIN_WINDOW].Status2.eFrameStoreNumber,
3735 FALSE, //linear mode
3736 TRUE); //force field packing mode here to get correct time
3737
3738 u32VFreq = MDrv_XC_GetAccurateVFreqx1K(pInstance, MAIN_WINDOW);
3739 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "IP vFreqx1K= %u\n", u32VFreq);
3740 if (u32VFreq != 0)
3741 {
3742 u16IPVsyncPeriod = (MS_U16)((1000000UL + u32VFreq - 1)/u32VFreq);
3743 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "IP sync period = %u ms\n", u16IPVsyncPeriod);
3744 }
3745 else
3746 {
3747 u16IPVsyncPeriod = DEFAULT_IP_VSYNC_PERIOD;
3748 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "!!!!!Warning u32VFreq = 0, Force u16IPVsyncPeriod: %u ms, need check input source.\n", u16IPVsyncPeriod);
3749 }
3750 u16DelayCount *= u16IPVsyncPeriod; //get delay time, uc just support main.
3751 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "MCNR Enable Delay=%u\n", u16DelayCount);
3752 }
3753 return u16DelayCount;
3754 }
3755
_MDrv_SC_FPLL_GetMCNRDelayTime_For_ISR(void * pInstance,MS_U32 u32AccuratePeriod)3756 static MS_U16 _MDrv_SC_FPLL_GetMCNRDelayTime_For_ISR(void *pInstance,MS_U32 u32AccuratePeriod)
3757 {
3758 MS_U16 u16DelayCount = 0;
3759 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3760 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3761 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
3762 MS_U32 u32VFreq = 0;
3763 MS_U16 u16IPVsyncPeriod = 0;
3764 MS_U64 u64XTALClk = 0;
3765
3766 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
3767 if(pXCResourcePrivate->stdrvXC_Display._bEnableMCNR[MAIN_WINDOW])
3768 {
3769 u16DelayCount = MDrv_XC_TransFrameNumToFactor(pInstance, gSrcInfo[MAIN_WINDOW].Status2.eFrameStoreNumber,
3770 FALSE, //linear mode
3771 TRUE); //force field packing mode here to get correct time
3772
3773 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "ip verticalperiod = %tu\n", (ptrdiff_t)u32AccuratePeriod);
3774
3775 if(u32AccuratePeriod != 0)
3776 {
3777 u64XTALClk = (MS_U64)pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.u32XTAL_Clock * 1000;
3778 do_div(u64XTALClk,u32AccuratePeriod);
3779 u32VFreq = (MS_U32)u64XTALClk;
3780 }
3781
3782 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "IP vFreqx1K= %u\n", u32VFreq);
3783 if (u32VFreq != 0)
3784 {
3785 u16IPVsyncPeriod = (MS_U16)((1000000UL + u32VFreq - 1)/u32VFreq);
3786 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "IP sync period = %u ms\n", u16IPVsyncPeriod);
3787 }
3788 else
3789 {
3790 u16IPVsyncPeriod = DEFAULT_IP_VSYNC_PERIOD;
3791 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "!!!!!Warning u32VFreq = 0, Force u16IPVsyncPeriod: %u ms, need check input source.\n", u16IPVsyncPeriod);
3792 }
3793 u16DelayCount *= u16IPVsyncPeriod; //get delay time, uc just support main.
3794 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "MCNR Enable Delay=%u\n", u16DelayCount);
3795 }
3796 return u16DelayCount;
3797 }
3798
MApi_XC_FrameLockCheck_U2(void * pInstance)3799 MS_BOOL MApi_XC_FrameLockCheck_U2(void* pInstance)
3800 {
3801 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3802 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3803 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
3804 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
3805 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
3806 #if FPLL_THRESH_MODE_SUPPORT
3807 #ifdef UFO_XC_FB_LEVEL
3808 if(pXCResourcePrivate->stdrvXC_Display._bFPLL_Thresh_Mode
3809 && ((gSrcInfo[MAIN_WINDOW].eFBLevel == E_XC_FB_LEVEL_FB)
3810 || gSrcInfo[MAIN_WINDOW].Status2.bMVOPHSKMode)
3811 )
3812 #else
3813 if (pXCResourcePrivate->stdrvXC_Display._bFPLL_Thresh_Mode
3814 && ((!(gSrcInfo[MAIN_WINDOW].bFBL || gSrcInfo[MAIN_WINDOW].bR_FBL)) || gSrcInfo[MAIN_WINDOW].Status2.bMVOPHSKMode))
3815 #endif
3816 {
3817 MS_BOOL bFrameLock = FALSE;
3818 LPLL_BK_STORE;
3819 LPLL_BK_SWITCH(0x00);
3820 bFrameLock = (MS_BOOL)(MDrv_ReadRegBit(L_BK_LPLL(0x0C), BIT(3)) >> 3);
3821 LPLL_BK_RESTORE;
3822 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
3823 return bFrameLock;
3824 }
3825 else
3826 #endif
3827 {
3828 //check PRD Lock // check Phase Stable ->check Frame lock
3829 if(pXCResourcePrivate->stdrvXC_Display.u32OutputPhaseStable && pXCResourcePrivate->stdrvXC_Display.u32OutputPRDLock)
3830 {
3831 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
3832 return TRUE;
3833 }
3834 else
3835 {
3836 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
3837 return FALSE;
3838 }
3839 }
3840
3841 }
3842
MApi_XC_FrameLockCheck(void)3843 MS_BOOL MApi_XC_FrameLockCheck(void)
3844 {
3845 if (pu32XCInst == NULL)
3846 {
3847 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
3848 return FALSE;
3849 }
3850
3851 stXC_CHECK_FRAMELOCK XCArgs;
3852 XCArgs.bReturnValue = FALSE;
3853
3854 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_CHECK_FRAMELOCK, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
3855 {
3856 printf("Obtain XC engine fail\n");
3857 return FALSE;
3858 }
3859 else
3860 {
3861 return XCArgs.bReturnValue;
3862 }
3863 }
3864
3865
3866 #define FPLL_ATV_FSM_FREERUN_STABLE_TIME 100
3867 #define FPLL_ATV_FSM_FREQ_STABLE_TIME 10000
3868 #define FPLL_ATV_FREQ_STABLE_COUNT 3
3869
3870 static MS_U32 gu32AtvIvsOvsLockFreqStableCount = 0;
3871
_MApi_XC_FPLL_IsIvsFreqStable(void * pInstance,MS_U32 * pu32VPeriod)3872 static MS_BOOL _MApi_XC_FPLL_IsIvsFreqStable(void *pInstance, MS_U32* pu32VPeriod)
3873 {
3874 static MS_U32 u32PreVPeriod = 0;
3875 MS_U32 u32VPeriodDiff;
3876 MS_U32 u32AccurateVPeriod = HAL_SC_ip_get_verticalperiod(pInstance, MAIN_WINDOW);
3877
3878 if(u32AccurateVPeriod != 0)
3879 {
3880 u32VPeriodDiff = (u32PreVPeriod > u32AccurateVPeriod ? u32PreVPeriod - u32AccurateVPeriod: u32AccurateVPeriod - u32PreVPeriod);
3881 if(u32VPeriodDiff < V_PERIOD_DIFF_TOLERANCE)
3882 {
3883 gu32AtvIvsOvsLockFreqStableCount++;
3884 }
3885 else
3886 {
3887 gu32AtvIvsOvsLockFreqStableCount = 0;
3888 }
3889 u32PreVPeriod = u32AccurateVPeriod;
3890
3891 if(pu32VPeriod != NULL)
3892 {
3893 *pu32VPeriod = u32AccurateVPeriod;
3894 }
3895
3896 if(gu32AtvIvsOvsLockFreqStableCount > FPLL_ATV_FREQ_STABLE_COUNT)
3897 {
3898 return TRUE;
3899 }
3900 }
3901
3902 return FALSE;
3903 }
3904
3905 #if ENABLE_LOCK_IVS_OVS_FOR_ATV
_MApi_XC_FPLL_AdjustOvsVtt(void * pInstance,MS_U32 u32AccurateVPeriod)3906 static void _MApi_XC_FPLL_AdjustOvsVtt(void *pInstance, MS_U32 u32AccurateVPeriod)
3907 {
3908 MS_U16 u16OutVtt, u16OriOutVtt;
3909 MS_U16 u16AccurateVFreq = 0;
3910 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3911 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3912
3913 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
3914
3915 UtopiaResourceGetPrivate(g_pXCResource[E_XC_POOL_ID_INTERNAL_VARIABLE],(void**)(&pXCResourcePrivate));
3916
3917 if(u32AccurateVPeriod != 0)
3918 {
3919 MS_U32 u32OutDiv = ((((MDrv_Read2Byte(L_BK_LPLL(0x0E)) & 0x00F0)>>4)<< 4 )|((MDrv_Read2Byte(L_BK_LPLL(0x0C)) & 0xF000) >> 12)) + 1;
3920 MS_U32 u32InDiv = ((((MDrv_Read2Byte(L_BK_LPLL(0x0E)) & 0x000F)>>0)<< 4 )|((MDrv_Read2Byte(L_BK_LPLL(0x0C)) & 0x0F00) >> 8)) + 1;
3921
3922 #ifdef SUPPORT_FPLL_DOUBLE_OVS
3923 // for muji U02, 4K 0.5K@240Hz case, there is new bit 0x3C[11] to control from 5:24 to 5:48
3924 if (MDrv_ReadByte(REG_CHIP_REVISION) >= 1)
3925 {
3926 if ((MDrv_Read2Byte(L_BK_LPLL(0x3C)) & 0x0800) == 0x0000)
3927 {
3928 u32OutDiv = u32OutDiv *2;
3929 }
3930 }
3931 #endif
3932 //MS_U32 u32AccurateVFreqX1000 = (MS_U32)((MS_U64)pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.u32XTAL_Clock * 1000 / u32AccurateVPeriod)*u32OutDiv/u32InDiv;
3933 // To avoid MS_U64 div in kernel driver
3934 MS_U32 u32tmp_u32XTAL_Clock = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.u32XTAL_Clock;
3935 MS_U32 u32tmp_u32XTAL_Clock_mod = u32tmp_u32XTAL_Clock % u32AccurateVPeriod;
3936 u32tmp_u32XTAL_Clock = u32tmp_u32XTAL_Clock / u32AccurateVPeriod;
3937 u32tmp_u32XTAL_Clock = u32tmp_u32XTAL_Clock * 1000;
3938 u32tmp_u32XTAL_Clock_mod = (u32tmp_u32XTAL_Clock_mod * 1000) / u32AccurateVPeriod;
3939 MS_U32 u32AccurateVFreqX1000 = (u32tmp_u32XTAL_Clock + u32tmp_u32XTAL_Clock_mod)*u32OutDiv/u32InDiv;
3940
3941 u16AccurateVFreq = (MS_U16)(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.u32XTAL_Clock * 100 / u32AccurateVPeriod);
3942 #if defined(PATCH_HW_VTT_LIMITATION)
3943 if(MDrv_ReadByte(REG_CHIP_REVISION) < HW_VTT_LIMITATION_CHIPREV)
3944 {
3945 u16OriOutVtt = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_36_L, VOP_VTT_MASK)+1;
3946 }
3947 else
3948 #endif
3949 {
3950 u16OriOutVtt = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0D_L) + 1;
3951 }
3952 //u16OutVtt = (MS_U16)((MS_U64)u16OriOutVtt * ((u16AccurateVFreq + 50) / 100 * 100) / u16AccurateVFreq);
3953 u16OutVtt = (MS_U16)((MS_U32)u16OriOutVtt * ((u16AccurateVFreq + 50) / 100 * 100 ) / u16AccurateVFreq);
3954
3955 //if(u16OutVtt > u16OriOutVtt - 2 && u16OutVtt < u16OriOutVtt + 2)
3956 {
3957 #if defined(PATCH_HW_VTT_LIMITATION)
3958 if(MDrv_ReadByte(REG_CHIP_REVISION) < HW_VTT_LIMITATION_CHIPREV)
3959 {
3960 #if (HW_DESIGN_HDMITX_VER == 1)//Maserati +Raptor HDMITX case
3961 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_B & E_XC_INIT_MISC_B_HDMITX_ENABLE)
3962 {
3963 MS_U8 u8delaycnt = 1;
3964 MS_U16 u16delaytime =0;
3965
3966 if(u16OutVtt > 2500)
3967 u16delaytime = 1000*u8delaycnt/50;
3968 else
3969 u16delaytime = 1000*u8delaycnt/60;
3970
3971 // Update changed VTT to inform Raptor
3972 MDrv_XC_WaitOutputVSync(pInstance, 1, 50, MAIN_WINDOW);
3973 MOD_W2BYTEMSK(REG_MOD_BK00_65_L,u16OutVtt,0x1FFF);
3974 MsOS_DelayTask(u16delaytime);
3975 }
3976 #endif
3977 MHal_XC_SetVopVttByBK68(pInstance, u16OutVtt - 1, 0);
3978 MDrv_XC_WaitOutputVSync(pInstance, 1, 50, MAIN_WINDOW);
3979 }
3980 else
3981 #endif
3982 {
3983 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0D_L, u16OutVtt - 1);
3984 }
3985 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
3986 if (psXCInstPri->u32DeviceID == 0)
3987 {
3988 SC_W2BYTE(1, REG_SC_BK10_0D_L, VOP_VTT_MASK);
3989 }
3990 #endif
3991 }
3992 #if defined(PATCH_HW_VTT_LIMITATION)
3993 if(MDrv_ReadByte(REG_CHIP_REVISION) < HW_VTT_LIMITATION_CHIPREV)
3994 {
3995 MDrv_SC_set_output_dclk(pInstance, SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0C_L) + 1, SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK68_36_L) + 1, (u16AccurateVFreq + 50) / 100 * 10, u32AccurateVFreqX1000, 0);
3996 }
3997 else
3998 #endif
3999 {
4000 MDrv_SC_set_output_dclk(pInstance, SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0C_L) + 1, SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0D_L) + 1, (u16AccurateVFreq + 50) / 100 * 10, u32AccurateVFreqX1000, 0);
4001 }
4002 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
4003 MHal_FRC_SetYTrig(pInstance, 0x88f, 0x890); //Need to set Y Trig again after adjust vtt
4004 #endif
4005 }
4006 }
4007
4008
_MApi_XC_FPLL_EnableLockIvsOvsMode(void * pInstance,MS_BOOL bEnable)4009 static void _MApi_XC_FPLL_EnableLockIvsOvsMode(void *pInstance, MS_BOOL bEnable)
4010 {
4011 if(bEnable)
4012 {
4013 MDrv_Write2Byte(L_BK_LPLL(0x1F), 0x2EE);
4014 MDrv_Write2ByteMask(L_BK_LPLL(0x78), BIT(12), BIT(12));
4015 gu32AtvIvsOvsLockFreqStableCount = 0;
4016 MDrv_SC_set_fpll(pInstance, DISABLE, DISABLE, 0);
4017 }
4018 else
4019 {
4020 MDrv_Write2Byte(L_BK_LPLL(0x1F), 0);
4021 MDrv_Write2ByteMask(L_BK_LPLL(0x78), 0, BIT(12));
4022 gu32AtvIvsOvsLockFreqStableCount = 0;
4023 MDrv_SC_set_fpll(pInstance, ENABLE, DISABLE, 0);
4024 }
4025 }
4026 #endif
4027
4028 //==============================================================================
4029 #if LOCK_FREQ_ONLY_WITHOUT_LOCK_PHASE
4030
4031 #define MAX_OUT_VTT_INCREASE_VALUE 10
4032 #define MAX_LOCK_VALUE 0x30000
4033 #define DISABLE_LOCK_VALUE 0x200000
4034
_MApi_XC_FPLL_EnableLcokFreqOnly(void * pInstance,MS_BOOL bEnable)4035 static void _MApi_XC_FPLL_EnableLcokFreqOnly(void *pInstance,MS_BOOL bEnable)
4036 {
4037 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4038 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4039
4040 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
4041 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
4042
4043 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "[%s][%d]feature is %x\n",__FUNCTION__, __LINE__, bEnable);
4044 if(bEnable)
4045 {
4046 MDrv_Write2ByteMask(L_BK_LPLL(0x70), BIT(15), BIT(15));
4047 W2BYTEMSK(L_CLKGEN0(0x59), BIT(11), BIT(8) | BIT(10) | BIT(11));
4048 MDrv_Write2Byte(L_BK_LPLL(0x0A), PHASE_OFFSET_LIMIT_FREQ_ONLY);
4049 }
4050 else
4051 {
4052
4053 MDrv_Write2ByteMask(L_BK_LPLL(0x70), 0, BIT(15));
4054 #ifdef ENABLE_SPREADMODE
4055 if(MHal_XC_IsSupportSpreadMode(pInstance) && pXCResourcePrivate->stdrvXC_MVideo_Context.g_bSpreandEnable==TRUE)
4056 {
4057 W2BYTEMSK(L_CLKGEN0(0x59), BIT(11) ,BIT(8) | BIT(10) | BIT(11));//spread mode
4058 }
4059 else
4060 #endif
4061 {
4062 MDrv_Write4Byte(L_BK_LPLL(0x1B), 0);
4063 MDrv_Write4Byte(L_BK_LPLL(0x19), 0);
4064 #if (HW_DESIGN_HDMITX_VER == 1 || HW_DESIGN_HDMITX_VER == 2)//Maserati +Raptor HDMITX || Maxim + inside HDMITX case
4065 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_B & E_XC_INIT_MISC_B_HDMITX_ENABLE)
4066 {
4067 W2BYTEMSK(L_CLKGEN0(0x59), BIT(11), BIT(8) | BIT(10) | BIT(11));
4068 }
4069 else
4070 #endif
4071 {
4072 W2BYTEMSK(L_CLKGEN0(0x59), BIT(8), BIT(8) | BIT(10) | BIT(11));
4073 }
4074 }
4075 }
4076 }
4077
MDrv_XC_FPLL_IsSupportLockFreqOnly(void * pInstance)4078 MS_BOOL MDrv_XC_FPLL_IsSupportLockFreqOnly(void *pInstance)
4079 {
4080 #if HW_SUPPORT_LOCK_FREQ_ONLY_WITHOUT_LOCK_PHASE
4081 //MS_U8 u8FrcIn, u8FrcOut;
4082 //MS_U16 u16FRCType=0;
4083 MS_BOOL bResult = TRUE;
4084
4085 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4086 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4087
4088 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
4089 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
4090
4091 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type == E_XC_PNL_LPLL_LVDS)
4092 {
4093 #ifdef UFO_XC_FB_LEVEL
4094 if(((gSrcInfo[MAIN_WINDOW].eFBLevel == E_XC_FB_LEVEL_FBL)
4095 || (gSrcInfo[MAIN_WINDOW].eFBLevel == E_XC_FB_LEVEL_RFBL_DI))
4096 || pXCResourcePrivate->stdrvXC_Display._bForceFreerun
4097 #else
4098 if((gSrcInfo[MAIN_WINDOW].bFBL || gSrcInfo[MAIN_WINDOW].bR_FBL)|| pXCResourcePrivate->stdrvXC_Display._bForceFreerun
4099 #endif
4100 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
4101 #ifndef HW_SUPPORT_FRC_LOCK_FREQ_ONLY_WITHOUT_LOCK_PHASE
4102 || ((pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFRCEnabled) && // FRC + 4K2K case needs to lock phase, FRC + FHD case use lockVfreq mode
4103 (IS_OUTPUT_4K2K(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height)) &&
4104 ((pXCResourcePrivate->stdrvXC_Display.g_u8FrcIn == 1)&&(pXCResourcePrivate->stdrvXC_Display.g_u8FrcOut == 1))) // For 50/60 case, use loch phase first
4105 #endif
4106 #endif
4107 || (pXCResourcePrivate->stdrvXC_MVideo_Context.g_bEnableLockFreqOnly == FALSE))/*|| gSrcInfo[MAIN_WINDOW].Status2.eMirrorMode */
4108 {
4109 bResult = FALSE;
4110 }
4111 }
4112 else
4113 {
4114 #ifdef UFO_XC_FB_LEVEL
4115 if((((gSrcInfo[MAIN_WINDOW].eFBLevel == E_XC_FB_LEVEL_FBL)
4116 || (gSrcInfo[MAIN_WINDOW].eFBLevel == E_XC_FB_LEVEL_RFBL_DI))
4117 && !gSrcInfo[MAIN_WINDOW].Status2.bMVOPHSKMode)
4118 || pXCResourcePrivate->stdrvXC_Display._bForceFreerun
4119 #else
4120 if(((gSrcInfo[MAIN_WINDOW].bFBL || gSrcInfo[MAIN_WINDOW].bR_FBL) && !gSrcInfo[MAIN_WINDOW].Status2.bMVOPHSKMode ) || pXCResourcePrivate->stdrvXC_Display._bForceFreerun
4121 #endif
4122 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
4123 #ifndef HW_SUPPORT_FRC_LOCK_FREQ_ONLY_WITHOUT_LOCK_PHASE
4124 || ((pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFRCEnabled) && // FRC + VB1 case needs to lock phase, FRC + LVDS case use lockVfreq mode
4125 (IS_OUTPUT_4K2K(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height)) &&
4126 ((pXCResourcePrivate->stdrvXC_Display.g_u8FrcIn == 1)&&(pXCResourcePrivate->stdrvXC_Display.g_u8FrcOut == 1))) // For 50/60 case, use loch phase first
4127 #endif
4128 #endif
4129 || (pXCResourcePrivate->stdrvXC_MVideo_Context.g_bEnableLockFreqOnly == FALSE))/*|| gSrcInfo[MAIN_WINDOW].Status2.eMirrorMode */
4130 {
4131 bResult = FALSE;
4132 }
4133 }
4134
4135 #if ((HW_DESIGN_HDMITX_VER == 1)||(HW_DESIGN_HDMITX_VER == 2))
4136 // Maserati Raptor, USEs lock phase mode.
4137 // For Maxim HDMI Tx, need to lock phase
4138 // Not use LockVfreq mode
4139 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_B & E_XC_INIT_MISC_B_HDMITX_ENABLE)
4140 {
4141 bResult = FALSE;
4142 }
4143 #endif
4144
4145 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "[%s][%d]gSrcInfo[MAIN_WINDOW].bFBL= %x\n",__FUNCTION__, __LINE__ ,gSrcInfo[MAIN_WINDOW].bFBL );
4146 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "[%s][%d]gSrcInfo[MAIN_WINDOW].bR_FBL= %x\n",__FUNCTION__, __LINE__ ,gSrcInfo[MAIN_WINDOW].bR_FBL );
4147 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "[%s][%d]gSrcInfo[MAIN_WINDOW].Status2.eMirrorMode= %x\n",__FUNCTION__, __LINE__ ,gSrcInfo[MAIN_WINDOW].Status2.eMirrorMode);
4148 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "[%s][%d]pXCResourcePrivate->stdrvXC_Display._bForceFreerun= %x\n",__FUNCTION__, __LINE__ ,pXCResourcePrivate->stdrvXC_Display._bForceFreerun);
4149 // XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "[%s][%d]pXCResourcePrivate->stdrvXC_MVideo_Context.g_bEnableLockFreqOnly= %x\n",__FUNCTION__, __LINE__ ,pXCResourcePrivate->stdrvXC_MVideo_Context.g_bEnableLockFreqOnly);
4150
4151 #if 0
4152 else
4153 {
4154 MS_U32 u32InDiv, u32OutDiv;
4155 u32OutDiv = ((MDrv_Read2Byte(L_BK_LPLL(0x0C)) & 0xF000) >> 12) + 1;
4156 u32InDiv = ((MDrv_Read2Byte(L_BK_LPLL(0x0C)) & 0x0F00) >> 8) + 1;
4157
4158 //if(u32OutDiv % u32InDiv != 0) bResult = FALSE;
4159 }
4160 #endif
4161
4162 if(!bResult)
4163 {
4164 MDrv_Write2ByteMask(L_BK_LPLL(0x70), 0, BIT(15));
4165 #ifdef ENABLE_SPREADMODE
4166 if(MHal_XC_IsSupportSpreadMode(pInstance) && pXCResourcePrivate->stdrvXC_MVideo_Context.g_bSpreandEnable==FALSE)
4167 #endif
4168 {
4169 #if ((HW_DESIGN_HDMITX_VER == 1) || (HW_DESIGN_HDMITX_VER == 2))//Maserati +Raptor HDMITX or Maxim + inside HDMITX case
4170 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_B & E_XC_INIT_MISC_B_HDMITX_ENABLE)
4171 {
4172 W2BYTEMSK(L_CLKGEN0(0x59), BIT(11), BIT(8) | BIT(10) | BIT(11));
4173 }
4174 else
4175 #endif
4176 {
4177 W2BYTEMSK(L_CLKGEN0(0x59), BIT(8), BIT(8) | BIT(10) | BIT(11));
4178 }
4179 }
4180 }
4181 else
4182 {
4183 MDrv_Write2Byte(L_BK_LPLL(0x0A), PHASE_OFFSET_LIMIT_FREQ_ONLY);
4184 }
4185
4186 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, " IsSupportLockFreqOnly= %x\n", bResult );
4187
4188 return bResult;
4189
4190 #else
4191
4192 return FALSE;
4193
4194 #endif
4195
4196 }
4197
_MApi_XC_FPLL_CalculateGCD(MS_U32 u32Input,MS_U32 u32Output)4198 static MS_U32 _MApi_XC_FPLL_CalculateGCD(MS_U32 u32Input, MS_U32 u32Output)
4199 {
4200 MS_U32 u32GCD = 1;
4201 while((u32Input !=0) && (u32Output !=0)) // GCD
4202 {
4203 if(u32Input > u32Output)
4204 {
4205 u32GCD = u32Output;
4206 u32Input %= u32Output;
4207 }
4208 else // Temp A < TempB
4209 {
4210 u32GCD = u32Input;
4211 u32Output %= u32Input;
4212 }
4213 //printf("GCD =%u\n", u32GCD);
4214 }
4215
4216 //u32GCD never be 0
4217 return u32GCD;
4218 }
4219
_MApi_XC_FPLL_LockFreqOnly(void * pInstance)4220 static MS_BOOL _MApi_XC_FPLL_LockFreqOnly(void *pInstance)
4221 {
4222 MS_U16 u16OutHtt, u16OutVtt, u16InHtt, u16InVtt;
4223 MS_U32 u32OutputClkDiv, u32InputClkDiv;
4224 MS_U32 u32InDiv, u32OutDiv=0;
4225 MS_U32 u32RealInDiv, u32RealOutDiv=0;
4226 MS_U32 u32GCD = 1;
4227 MS_U8 i;
4228 MS_U32 u32MaxOutVtt =1, u32MaxGCD = 1;
4229
4230 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4231 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4232
4233 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
4234 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
4235
4236 MS_U8 u8LPLL_Type = (MS_U8)pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type;
4237
4238 LPLL_BK_STORE;
4239 LPLL_BK_SWITCH(0x00);
4240
4241 #if (HW_DESIGN_4K2K_VER != 6) // for manhattan, only 1 LPLL
4242 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.bFRC)
4243 {
4244 u16OutHtt = SC_R2BYTE(0, REG_SC_BK46_02_L) + 1;
4245 u16OutVtt = SC_R2BYTE(0, REG_SC_BK46_01_L) + 1;
4246 }
4247 else
4248 #endif
4249 {
4250 u16OutHtt = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0C_L) + 1;
4251 #if defined(PATCH_HW_VTT_LIMITATION)
4252 if(MDrv_ReadByte(REG_CHIP_REVISION) < HW_VTT_LIMITATION_CHIPREV)
4253 {
4254 u16OutVtt = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_36_L, VOP_VTT_MASK)+1;
4255 }
4256 else
4257 #endif
4258 {
4259 u16OutVtt = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0D_L) + 1;
4260 }
4261 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
4262 if (IsVBY1_16LANE(u8LPLL_Type))
4263 {
4264 // maserati mode, get Htt/Vtt from FO tgen
4265 u16OutHtt = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BKCB_02_L) + 1;
4266 u16OutVtt = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BKCB_01_L) + 1;
4267 }
4268 #endif
4269 }
4270
4271 MsOS_DelayTask(50); //leon test , 50ms OK, 20ms ng, 32ms ng, 40ng
4272 u16InHtt = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_28_L) + 1;
4273 u16InVtt = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_1F_L);
4274 u32OutDiv = ((((MDrv_Read2Byte(L_BK_LPLL(0x0E)) & 0x00F0)>>4)<< 4 )|((MDrv_Read2Byte(L_BK_LPLL(0x0C)) & 0xF000) >> 12)) + 1;
4275 u32InDiv = ((((MDrv_Read2Byte(L_BK_LPLL(0x0E)) & 0x000F)>>0)<< 4 )|((MDrv_Read2Byte(L_BK_LPLL(0x0C)) & 0x0F00) >> 8)) + 1;
4276
4277 #ifdef SUPPORT_FPLL_DOUBLE_OVS
4278 // for muji U02, 4K 0.5K@240Hz case, there is new bit 0x3C[11] to control from 5:24 to 5:48
4279 if (MDrv_ReadByte(REG_CHIP_REVISION) >= 1)
4280 {
4281 if ((MDrv_Read2Byte(L_BK_LPLL(0x3C)) & 0x0800) == 0x0000)
4282 {
4283 u32OutDiv = u32OutDiv *2;
4284 }
4285 }
4286 #endif
4287
4288 u32RealInDiv = u32InDiv;
4289 u32RealOutDiv = u32OutDiv;
4290
4291 if(gSrcInfo[MAIN_WINDOW].bInterlace) u32OutDiv*= 2;
4292
4293 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "[%s][%d]u16InHtt=%u, u16InVtt=%u\n",__FUNCTION__, __LINE__, u16InHtt, u16InVtt);
4294 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "[%s][%d]u16OutHtt=%u, u16OutVtt=%u\n",__FUNCTION__, __LINE__, u16OutHtt, u16OutVtt);
4295 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "[%s][%d]u32InDiv =%tu, u32OutDiv=%tu\n",__FUNCTION__, __LINE__, (ptrdiff_t)u32InDiv, (ptrdiff_t)u32OutDiv);
4296 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "[%s][%dgSrcInfo[MAIN_WINDOW].bInterlace=%x, reg_bInterlace=%u\n",__FUNCTION__, __LINE__, gSrcInfo[MAIN_WINDOW].bInterlace, SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_21_L, 0x01));
4297
4298 u32InputClkDiv = u16InHtt * u16InVtt * u32InDiv;
4299 #ifdef SUPPORT_FPLL_REFER_24MXTAL_4P
4300 u32OutputClkDiv = u16OutHtt * u16OutVtt* u32OutDiv/4;
4301 #else
4302
4303 #ifdef SUPPORT_FPLL_REFER_24MXTAL
4304 u32OutputClkDiv = u16OutHtt * u16OutVtt * u32OutDiv/2;
4305 #else
4306 #if (HW_DESIGN_4K2K_VER != 6) // for manhattan, only 1 LPLL
4307 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.bFRC)
4308 {
4309 u32OutputClkDiv = u16OutHtt * u16OutVtt * u32OutDiv/2;
4310 }
4311 else
4312 #endif
4313 {
4314 u32OutputClkDiv = u16OutHtt * u16OutVtt * u32OutDiv;
4315 }
4316 #endif
4317 #endif
4318 if(u32InputClkDiv == 0 || u32OutputClkDiv == 0) return FALSE;
4319
4320 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "[%s][%d]u32InputClkDiv=%tu, u32OutputClkDiv=%tu\n",__FUNCTION__, __LINE__, (ptrdiff_t)u32InputClkDiv, (ptrdiff_t)u32OutputClkDiv);
4321
4322 //u16OutVtt-=5; // scan Vtt from (Vtt-5)~(Vtt+5) for get the better GCD
4323 for(i = 0; i < MAX_OUT_VTT_INCREASE_VALUE; i++)
4324 {
4325 u32InputClkDiv = u16InHtt * u16InVtt * u32InDiv;
4326 #ifdef SUPPORT_FPLL_REFER_24MXTAL_4P
4327 u32OutputClkDiv = u16OutHtt * u16OutVtt* u32OutDiv/4;
4328 #else
4329
4330 #ifdef SUPPORT_FPLL_REFER_24MXTAL
4331 u32OutputClkDiv = u16OutHtt * u16OutVtt * u32OutDiv/2;
4332 #else
4333 #if (HW_DESIGN_4K2K_VER != 6) // for manhattan, only 1 LPLL
4334 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.bFRC)
4335 {
4336 u32OutputClkDiv = u16OutHtt * u16OutVtt * u32OutDiv/2;
4337 }
4338 else
4339 #endif
4340 {
4341 u32OutputClkDiv = u16OutHtt * u16OutVtt * u32OutDiv;
4342 }
4343 #endif
4344 #endif
4345 u32GCD = _MApi_XC_FPLL_CalculateGCD(u32InputClkDiv, u32OutputClkDiv);
4346 if(u32GCD > u32MaxGCD)
4347 {
4348 u32MaxOutVtt = u16OutVtt; // from (Vtt-5)~(Vtt+5)
4349 u32MaxGCD = u32GCD;
4350 }
4351 u16OutVtt++;
4352 }
4353
4354 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "[%s][%d]u16OutVtt=%u, u32MaxOutVtt=%tu\n",__FUNCTION__, __LINE__, u16OutVtt,(ptrdiff_t)u32MaxOutVtt);
4355
4356 // Get HDMI Pixel Repetition
4357 MS_U8 u8CurHDMIPixelRep = 1;
4358
4359 if( gSrcInfo[MAIN_WINDOW].enInputSourceType >= INPUT_SOURCE_HDMI
4360 && gSrcInfo[MAIN_WINDOW].enInputSourceType < INPUT_SOURCE_HDMI_MAX)
4361 {
4362 u8CurHDMIPixelRep = (MDrv_HDMI_avi_infoframe_info(_BYTE_5)& 0x0F)+1;
4363 }
4364
4365 u32InputClkDiv = u16InHtt * u16InVtt * u32InDiv * u8CurHDMIPixelRep;
4366 #ifdef SUPPORT_FPLL_REFER_24MXTAL_4P
4367 u32OutputClkDiv = u16OutHtt * u32MaxOutVtt* u32OutDiv/4;
4368 #else
4369
4370 #ifdef SUPPORT_FPLL_REFER_24MXTAL
4371 u32OutputClkDiv = u16OutHtt * u32MaxOutVtt * u32OutDiv/2;
4372 #else
4373 #if (HW_DESIGN_4K2K_VER != 6) // for manhattan, only 1 LPLL
4374 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.bFRC)
4375 {
4376 u32OutputClkDiv = u16OutHtt * u32MaxOutVtt * u32OutDiv/2;
4377 }
4378 else
4379 #endif
4380 {
4381 u32OutputClkDiv = u16OutHtt * u32MaxOutVtt * u32OutDiv;
4382 }
4383 #endif
4384 #endif
4385
4386 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "[%s][%d]u32InputClkDiv=%tu, u32OutputClkDiv=%tu\n",__FUNCTION__, __LINE__, (ptrdiff_t)u32InputClkDiv, (ptrdiff_t)u32OutputClkDiv);
4387
4388 u32InputClkDiv /= u32MaxGCD;
4389 u32OutputClkDiv /= u32MaxGCD;
4390
4391 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "[%s][%d]u32InputClkDiv=%tu, u32OutputClkDiv=%tu\n",__FUNCTION__, __LINE__, (ptrdiff_t)u32InputClkDiv, (ptrdiff_t)u32OutputClkDiv);
4392
4393 if(u32InputClkDiv > MAX_LOCK_VALUE || u32OutputClkDiv > MAX_LOCK_VALUE)
4394 {
4395 MS_U8 u8GainPI = MDrv_ReadByte(H_BK_LPLL(0x0B));
4396 if(u8GainPI > 0x21)
4397 {
4398 u8GainPI -= 0x11;
4399 MDrv_WriteByte(H_BK_LPLL(0x0B), u8GainPI); //Gain
4400 }
4401 }
4402
4403 if(u32InputClkDiv > DISABLE_LOCK_VALUE || u32OutputClkDiv > DISABLE_LOCK_VALUE)
4404 {
4405 #if LOCK_FREQ_ONLY_WITHOUT_LOCK_PHASE
4406 _MApi_XC_FPLL_EnableLcokFreqOnly(pInstance,FALSE);
4407 #endif
4408 }
4409
4410 //if(u32InputClkDiv < 3000 && u32OutputClkDiv < 3000)
4411 {
4412 if(u32InputClkDiv > u32OutputClkDiv)
4413 { // 0x2000 is experience value provided by HW designer
4414 u32GCD = 0x2000/u32OutputClkDiv + 1;
4415 }
4416 else
4417 {
4418 u32GCD = 0x2000/u32InputClkDiv + 1;
4419 }
4420 u32InputClkDiv *= u32GCD;
4421 u32OutputClkDiv *= u32GCD;
4422 }
4423
4424 u32InputClkDiv -= 1;
4425 u32OutputClkDiv -= 1;
4426
4427 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "[%s][%d]u32InputClkDiv=%tu, u32OutputClkDiv=%tu\n",__FUNCTION__, __LINE__, (ptrdiff_t)u32InputClkDiv, (ptrdiff_t)u32OutputClkDiv);
4428 LPLL_BK_SWITCH(0x00);
4429 MDrv_Write4Byte(L_BK_LPLL(0x1B), u32OutputClkDiv);
4430 MDrv_Write4Byte(L_BK_LPLL(0x19), u32InputClkDiv);
4431
4432 #if (HW_DESIGN_4K2K_VER != 6) // for manhattan, only 1 LPLL
4433 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.bFRC)
4434 {
4435 SC_W2BYTE(0, REG_SC_BK46_01_L, u32MaxOutVtt - 1);
4436 }
4437 else
4438 #endif
4439 {
4440 if(MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED)
4441 {
4442 #if defined(PATCH_HW_VTT_LIMITATION)
4443 if(MDrv_ReadByte(REG_CHIP_REVISION) < HW_VTT_LIMITATION_CHIPREV)
4444 {
4445 _MLOAD_ENTRY(pInstance);
4446 MHal_XC_SetVopVttByBK68(pInstance, u32MaxOutVtt - 1, 1);
4447 _MLOAD_RETURN(pInstance);
4448 MDrv_XC_WaitOutputVSync(pInstance, 1, 50, MAIN_WINDOW);
4449 }
4450 else
4451 #endif
4452 {
4453 _MLOAD_ENTRY(pInstance);
4454
4455 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0D_L, u32MaxOutVtt - 1, 0xFFFF);
4456
4457 MDrv_XC_MLoad_Fire(pInstance, TRUE);
4458
4459 _MLOAD_RETURN(pInstance);
4460 }
4461 }
4462 else
4463 {
4464 #if defined(PATCH_HW_VTT_LIMITATION)
4465 if(MDrv_ReadByte(REG_CHIP_REVISION) < HW_VTT_LIMITATION_CHIPREV)
4466 {
4467 MHal_XC_SetVopVttByBK68(pInstance, u32MaxOutVtt - 1, 0);
4468 MDrv_XC_WaitOutputVSync(pInstance, 1, 50, MAIN_WINDOW);
4469 }
4470 else
4471 #endif
4472 {
4473 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0D_L, u32MaxOutVtt - 1);
4474 }
4475 }
4476 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
4477 if (psXCInstPri->u32DeviceID == 0)
4478 {
4479 SC_W2BYTE(1, REG_SC_BK10_0D_L, VOP_VTT_MASK);
4480 }
4481 #endif
4482
4483 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
4484 if (IsVBY1_16LANE(u8LPLL_Type))
4485 {
4486 // maserati mode, set Vtt to FO tgen
4487 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BKCB_01_L, u32MaxOutVtt -1);
4488 }
4489
4490 MHal_FRC_SetYTrig(pInstance, 0x88f, 0x890); //Need to set Y Trig again after adjust vtt
4491 #endif
4492 }
4493
4494 #if 1
4495 //// after Vtt refactoring, the LPLL set need to re-calculate and update
4496 MS_U64 u64Htt = 0;
4497 MS_U64 u64Vtt = 0;
4498 MS_U32 u32OutputVfreq = gSrcInfo[MAIN_WINDOW].Status2.u16OutputVFreqAfterFRC;
4499
4500
4501 #if (HW_DESIGN_4K2K_VER != 6) // for manhattan, only 1 LPLL
4502 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.bFRC)
4503 {
4504 u64Htt = (MS_U64)SC_R2BYTE(0, REG_SC_BK46_02_L) + 1;
4505 u64Vtt = (MS_U64)SC_R2BYTE(0, REG_SC_BK46_01_L) + 1;
4506 }
4507 else
4508 #endif
4509 {
4510 u64Htt = (MS_U64)SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0C_L) + 1;
4511 #if defined(PATCH_HW_VTT_LIMITATION)
4512 if(MDrv_ReadByte(REG_CHIP_REVISION) < HW_VTT_LIMITATION_CHIPREV)
4513 {
4514 u64Vtt = (MS_U64)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_36_L, VOP_VTT_MASK)+1;
4515 }
4516 else
4517 #endif
4518 {
4519 u64Vtt = (MS_U64)SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0D_L) + 1;
4520 }
4521
4522 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
4523 if (IsVBY1_16LANE(u8LPLL_Type))
4524 {
4525 // maserati mode, get Htt/Vtt from FO tgen
4526 u64Htt = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BKCB_02_L) + 1;
4527 u64Vtt = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BKCB_01_L) + 1;
4528 }
4529 #endif
4530 }
4531
4532
4533 MS_U64 u64DClk = u64Htt * u64Vtt * (MS_U64)u32OutputVfreq;
4534 MS_U32 u32PllSet = MDrv_PNL_CalculateLPLLSETbyDClk(pInstance, u64DClk, FALSE);
4535
4536 MDrv_Write3Byte(L_BK_LPLL(0x0F), u32PllSet);
4537
4538
4539 #if defined (__aarch64__)
4540 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "[%s][%d]u64Htt=%lu, u64Vtt=%lu, u32OutputVfreq =%u\n",
4541 __FUNCTION__, __LINE__, u64Htt, u64Vtt, u32OutputVfreq);
4542 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "[%s][%d]u64DClk=%lu, u32PllSet=0x%x\n",__FUNCTION__, __LINE__, u64DClk, u32PllSet);
4543 #else
4544 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "[%s][%d]u64Htt=%llu, u64Vtt=%llu, u32OutputVfreq =%tu\n",
4545 __FUNCTION__, __LINE__, u64Htt, u64Vtt, (ptrdiff_t)u32OutputVfreq);
4546 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "[%s][%d]u64DClk=%llu, u32PllSet=0x%tx\n",__FUNCTION__, __LINE__, u64DClk, (ptrdiff_t)u32PllSet);
4547 #endif
4548
4549 #endif
4550 LPLL_BK_RESTORE;
4551
4552 return TRUE;
4553 }
4554 #endif // LOCK_FREQ_ONLY_WITHOUT_LOCK_PHASE
4555 //=======================================================
4556 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6)) //Only FRC_INSIDE and HW_DESIGN_4K2K_VER == 6 use this function, for fixing compile warning we use #if here
_MApi_XC_FPLL_AdjustVtt_ForPhaseLock(void * pInstance,MS_BOOL bChange)4557 static void _MApi_XC_FPLL_AdjustVtt_ForPhaseLock(void *pInstance, MS_BOOL bChange)
4558 {
4559 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4560 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4561 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
4562 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
4563 MS_BOOL bPhaseDiffUp = FALSE;
4564 MS_U16 u16NowVtt = 0;
4565 LPLL_BK_STORE;
4566 LPLL_BK_SWITCH(0x00);
4567 bPhaseDiffUp = MDrv_Read2Byte(L_BK_LPLL(0x12)) &0x01;
4568 LPLL_BK_RESTORE;
4569
4570 #if defined(PATCH_HW_VTT_LIMITATION)
4571 if(MDrv_ReadByte(REG_CHIP_REVISION) < HW_VTT_LIMITATION_CHIPREV)
4572 {
4573 u16NowVtt = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_36_L, VOP_VTT_MASK) + 1;
4574 }
4575 else
4576 #endif
4577 {
4578 u16NowVtt = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_0D_L, VOP_VTT_MASK) + 1;
4579 }
4580
4581 if (u16NowVtt < VTT_OFFSET_FOR_PHASE_LOCK)
4582 {
4583 printf("ALERT!!! Vtt too small so not adjust Vtt for phase lcok~~~\n");
4584 return;
4585 }
4586
4587 if (bChange)
4588 {
4589 if (bPhaseDiffUp)
4590 u16NowVtt = u16NowVtt - VTT_OFFSET_FOR_PHASE_LOCK;
4591 else
4592 u16NowVtt = u16NowVtt + VTT_OFFSET_FOR_PHASE_LOCK;
4593 }
4594 else // revert to original Vtt here
4595 {
4596 if (bPhaseDiffUp)
4597 u16NowVtt = u16NowVtt + VTT_OFFSET_FOR_PHASE_LOCK;
4598 else
4599 u16NowVtt = u16NowVtt - VTT_OFFSET_FOR_PHASE_LOCK;
4600 }
4601 #if defined(PATCH_HW_VTT_LIMITATION)
4602 if(MDrv_ReadByte(REG_CHIP_REVISION) < HW_VTT_LIMITATION_CHIPREV)
4603 {
4604 _MLOAD_ENTRY(pInstance);
4605 MHal_XC_SetVopVttByBK68(pInstance, (u16NowVtt - 1)&VOP_VTT_MASK, 1);
4606 _MLOAD_RETURN(pInstance);
4607 MDrv_XC_WaitOutputVSync(pInstance, 1, 50, MAIN_WINDOW);
4608 }
4609 else
4610 #endif
4611 {
4612 _MLOAD_ENTRY(pInstance);
4613 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0D_L,(u16NowVtt - 1)&VOP_VTT_MASK, VOP_VTT_MASK);
4614 MDrv_XC_MLoad_Fire(pInstance, TRUE);
4615 _MLOAD_RETURN(pInstance);
4616 }
4617 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
4618 MHal_FRC_SetYTrig(pInstance, 0x88f, 0x890); //Need to set Y Trig again after adjust vtt
4619 #endif
4620 }
4621
4622 #define LOCK_FREQ_RANGE_PROTECT 3
_MApi_XC_FPLL_LockFreq_Is_SafeRange(void * pInstance)4623 static MS_BOOL _MApi_XC_FPLL_LockFreq_Is_SafeRange(void *pInstance)
4624 {
4625 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4626 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4627 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
4628 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
4629
4630 LPLL_BK_STORE;
4631 LPLL_BK_SWITCH(0x00);
4632 MS_U32 u32PhaseDiff = MDrv_Read4Byte(L_BK_LPLL(0x3D));
4633 MS_U16 u16Limitoffset = MDrv_Read2Byte(L_BK_LPLL(0x0A));
4634 LPLL_BK_RESTORE;
4635
4636 //U16 u16Vtrig= MHal_TGEN_GetVTrigY();
4637 MS_U16 u16Vtotal = 0;
4638 MS_U32 u32OutVfreqx100 = gSrcInfo[MAIN_WINDOW].Status2.u16OutputVFreqAfterFRC *10;
4639 //U16 u16VRefpoint = MHal_TGEN_Get_FpllRefPointY();
4640 MS_U32 u32SafeRangeMin = 0, u32NewSafeRangeMin=0;
4641
4642 #if defined(PATCH_HW_VTT_LIMITATION)
4643 if(MDrv_ReadByte(REG_CHIP_REVISION) < HW_VTT_LIMITATION_CHIPREV)
4644 {
4645 u16Vtotal = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_36_L, VOP_VTT_MASK) + 1;
4646 }
4647 else
4648 #endif
4649 {
4650 u16Vtotal = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_0D_L, VOP_VTT_MASK) + 1;
4651 }
4652 // Conver Phase to line base, phase(Xtal clk)
4653 u32SafeRangeMin = (MS_U64)u16Limitoffset*u16Vtotal*u32OutVfreqx100/(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.u32XTAL_Clock*100) + LOCK_FREQ_RANGE_PROTECT;
4654
4655 if(u32SafeRangeMin > (MS_U16)(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height/2)) // if vtotal = 0.5k, Vref and Vtrigger range will be less than Saferangemin
4656 {
4657 u32NewSafeRangeMin = (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height/2);
4658 }
4659 else
4660 {
4661 u32NewSafeRangeMin = u32SafeRangeMin;
4662 }
4663
4664 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
4665 MS_U16 u16IvsOvs = MDrv_Read2Byte(L_BK_LPLL(0x0C)) & 0xFF00;
4666 if ((pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFRCEnabled) && // FRC + 4K2K case needs to lock phase, FRC + FHD case use lockVfreq mode
4667 (IS_OUTPUT_4K2K(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height)) &&
4668 (u16IvsOvs == 0x0000))
4669 {
4670 u32NewSafeRangeMin = (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height/4);
4671 }
4672 #endif
4673
4674 #if 0 // sync code from ursa, disable first
4675 // Check the Vref and Vtrigger range far enough than saferange or replace the Saferagnemin by the Vref and Vtigger diff
4676 if((U16)diff(u16Vtrig, u16VRefpoint) <= u32NewSafeRangeMin)
4677 {
4678 //printf("u16VRefpoint:%u and u16Vtrig:%u diff less than u32NewSafeRangeMin:%u\r\n ", u16VRefpoint, u16Vtrig, u32NewSafeRangeMin);
4679 if(diff(u16Vtrig, u16VRefpoint) <=LOCK_FREQ_RANGE_PROTECT)
4680 {
4681 //printf("[Warning]Vtrigger and Vref less than 3 line\r\n");
4682 return FALSE;
4683 }
4684 else
4685 {
4686 u32NewSafeRangeMin = diff(u16Vtrig, u16VRefpoint)-LOCK_FREQ_RANGE_PROTECT;
4687 }
4688 }
4689 else if((U16)diff(u16Vtotal,diff(u16Vtrig, u16VRefpoint)) <= u32NewSafeRangeMin)
4690 {
4691 //printf("u16VRefpoint:%u and u16Vtrig:%u diff less than u32NewSafeRangeMin:%u\r\n ", u16VRefpoint, u16Vtrig, u32NewSafeRangeMin);
4692 if(diff(u16Vtotal,diff(u16Vtrig, u16VRefpoint)) <=LOCK_FREQ_RANGE_PROTECT)
4693 {
4694 //printf("[Warning]Vtrigger and Vref less than 3 line\r\n");
4695 return FALSE;
4696 }
4697 else
4698 {
4699 u32NewSafeRangeMin = diff(u16Vtotal,diff(u16Vtrig, u16VRefpoint))-LOCK_FREQ_RANGE_PROTECT;
4700 }
4701 }
4702 #endif
4703
4704 //if(u32NewSafeRangeMin != u32SafeRangeMin) // if the NewSafeRagne change, update the limit offset
4705 {
4706 u16Limitoffset = (MS_U64)u32NewSafeRangeMin*pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.u32XTAL_Clock*100/(u16Vtotal*u32OutVfreqx100); // convert phase diff to Xtal unit
4707 }
4708
4709 if(u32PhaseDiff > u16Limitoffset)
4710 {
4711 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "not safe case, u16PhaseDiff %x u16Limitoffset: %x \r\n ", u32PhaseDiff, u16Limitoffset);
4712 return FALSE;
4713 }
4714 else
4715 {
4716 return TRUE;
4717 }
4718
4719 }
4720 #endif
4721
4722 /*
4723 Frame lock mechanism should be detected here.
4724 msAPI_Scaler_FPLL_FSM wait to lock frame only if the
4725 phase error is small enough.
4726 */
4727
_MApi_XC_FPLL_FSM_ISR(SC_INT_SRC eIntNum,void * pParam)4728 static void _MApi_XC_FPLL_FSM_ISR(SC_INT_SRC eIntNum, void * pParam)
4729 {
4730 void *pInstance = pu32XCInst_private;
4731 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4732 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4733 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
4734 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
4735 MS_U32 u32Ofs;
4736 MS_BOOL Dir ;
4737 MS_U16 u16PhaseLimit;
4738 #if ENABLE_LOCK_IVS_OVS_FOR_ATV
4739 MS_U8 u8LPLL_Type = (MS_U8)pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type;
4740 #endif
4741
4742 #if (!ENABLE_REGISTER_SPREAD)
4743 MS_U8 u8Bank;
4744 #endif
4745 if(eIntNum >= MAX_SC_INT)
4746 {
4747 printf("Interrupt number >= max scaler interrupt number\n");
4748 }
4749 if(pParam == NULL)
4750 {
4751 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING_ISR,"ISR pParam is NULL\n");
4752 }
4753 //printf("FSM looping pXCResourcePrivate->stdrvXC_Display._enFpllFsm = %x\n", pXCResourcePrivate->stdrvXC_Display._enFpllFsm);
4754 switch (pXCResourcePrivate->stdrvXC_Display._enFpllFsm)
4755 {
4756 case FPLL_IDLE_STATE:
4757 // no signal, do nothing
4758 break;
4759
4760 case FPLL_INIT_STATE://dtv special
4761 //wait 2 input vsync for framelock phase error stable
4762 //according our test of 24P video, after enble mvop, need at least 2 input vsync, framelock
4763 //phase error can be stable.
4764 pXCResourcePrivate->stdrvXC_Display.u32OutputPhaseStable = FALSE;
4765 pXCResourcePrivate->stdrvXC_Display.u32OutputPRDLock = FALSE;
4766
4767 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
4768 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.bFRC)
4769 {
4770 Hal_XC_FRC_R2_Set_FPLL_Lockdone(pInstance, FALSE);
4771 }
4772 #endif
4773 if((MsOS_GetSystemTime() - pXCResourcePrivate->stdrvXC_Display.s_u32InputVsyncStart) < pXCResourcePrivate->stdrvXC_Display.s_u32DelayT)
4774 break;
4775
4776 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING_ISR, "[FPLL INIT->PRD]\n")
4777 pXCResourcePrivate->stdrvXC_Display.s_u16OrigPrd = FPLL_PRD_MAX;
4778
4779 #if ENABLE_LOCK_IVS_OVS_FOR_ATV
4780 if (!(IsVBY1_16LANE(u8LPLL_Type)))
4781 _MApi_XC_FPLL_EnableLockIvsOvsMode(pInstance, FALSE);
4782 #endif
4783
4784 #if LOCK_FREQ_ONLY_WITHOUT_LOCK_PHASE
4785 if(MDrv_XC_FPLL_IsSupportLockFreqOnly(pInstance))
4786 {
4787 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_FREQ_ONLY_LOCK_STATE;
4788 }
4789 else
4790 {
4791 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_WAIT_PRD_LOCK_STATE;
4792 }
4793 #else
4794 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_WAIT_PRD_LOCK_STATE;
4795 #endif
4796
4797 pXCResourcePrivate->stdrvXC_Display.s_u32FSMTimer = MsOS_GetSystemTime();
4798 pXCResourcePrivate->stdrvXC_Display._u32MCNRTimer = pXCResourcePrivate->stdrvXC_Display.s_u32FSMTimer;//For MCNR enable counter
4799 //InISR, we can not wait XC entry, because interrupt is higher than xc mutex
4800 #if (!ENABLE_REGISTER_SPREAD)
4801 u8Bank = MDrv_ReadByte(BK_SELECT_00);
4802 #endif
4803 Hal_SC_SetOPWriteOff(pInstance, ENABLE);
4804 #if (!ENABLE_REGISTER_SPREAD)
4805 MDrv_WriteByte(BK_SELECT_00, u8Bank);
4806 #endif
4807 pXCResourcePrivate->stdrvXC_Display._bNeedReloadMCNR = TRUE;
4808 break;
4809 case FPLL_ATV_INIT_STATE://atv special
4810 #if(PHASE_LOCK_EN)
4811 pXCResourcePrivate->stdrvXC_Display.u32OutputPhaseStable = FALSE;
4812 #else
4813 pXCResourcePrivate->stdrvXC_Display.u32OutputPhaseStable = TRUE;
4814 #endif
4815 pXCResourcePrivate->stdrvXC_Display.u32OutputPRDLock = FALSE;
4816 pXCResourcePrivate->stdrvXC_Display.s_u32FSMTimer = MsOS_GetSystemTime();
4817 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_WAIT_IP_STABLE_STATE;
4818 break;
4819
4820 case FPLL_WAIT_IP_STABLE_STATE://atv special
4821
4822 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
4823 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.bFRC)
4824 {
4825 Hal_XC_FRC_R2_Set_FPLL_Lockdone(pInstance, FALSE);
4826 }
4827 #endif
4828
4829 if (_MDrv_Scaler_GetAVDStatus() & VD_HSYNC_LOCKED)
4830 {
4831 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_WAIT_LPLL_OFS_STATE;
4832
4833 #if LOCK_FREQ_ONLY_WITHOUT_LOCK_PHASE
4834 _MApi_XC_FPLL_EnableLcokFreqOnly(pInstance,FALSE);
4835
4836 #if (HW_DESIGN_HDMITX_VER == 1)//Maserati +Raptor HDMITX case
4837 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_B & E_XC_INIT_MISC_B_HDMITX_ENABLE)
4838 {
4839 MDrv_Write2Byte(L_BK_LPLL(0x0A), 0x400);
4840 }
4841 else
4842 #endif
4843 {
4844 MDrv_Write2Byte(L_BK_LPLL(0x0A), PHASE_OFFSET_LIMIT_FREQ_ONLY);
4845 }
4846 #endif
4847
4848 #if ENABLE_LOCK_IVS_OVS_FOR_ATV
4849 if (!(IsVBY1_16LANE(u8LPLL_Type)))
4850 {
4851 _MApi_XC_FPLL_EnableLockIvsOvsMode(pInstance, TRUE);
4852 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_LOCK_ATV_ADJUST_IVS_STATE;
4853 }
4854 #endif
4855
4856 #if (!ENABLE_REGISTER_SPREAD)
4857 u8Bank = MDrv_ReadByte(BK_SELECT_00);
4858 #endif
4859 Hal_SC_SetOPWriteOff(pInstance, ENABLE);
4860 #if (!ENABLE_REGISTER_SPREAD)
4861 MDrv_WriteByte(BK_SELECT_00, u8Bank);
4862 #endif
4863 pXCResourcePrivate->stdrvXC_Display._u32MCNRTimer = MsOS_GetSystemTime();
4864 pXCResourcePrivate->stdrvXC_Display._bNeedReloadMCNR = TRUE;
4865 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING_ISR, "[WAIT IP STABLE] -> [WAIT LPLL OFS]\n")
4866 }
4867 else if(FPLL_FSM_STABLE_TIME < (MsOS_GetSystemTime() - pXCResourcePrivate->stdrvXC_Display.s_u32FSMTimer))
4868 {
4869 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_DEATTACH_ISR_STATE; // force re-start
4870 }
4871 break;
4872
4873 #if LOCK_FREQ_ONLY_WITHOUT_LOCK_PHASE
4874
4875 case FPLL_FREQ_ONLY_LOCK_STATE:
4876 {
4877 _MApi_XC_FPLL_LockFreqOnly(pInstance);
4878 #if 0 //(FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
4879 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFRCEnabled)
4880 {
4881 _MApi_XC_FPLL_AdjustVtt_ForPhaseLock(pInstance, TRUE);
4882 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_FREQ_ONLY_LOCK_WAIT_PHASE_STABLE_STATE;
4883 pXCResourcePrivate->stdrvXC_Display._bNeedReloadMCNR = TRUE;
4884 }
4885 else
4886 #endif
4887 {
4888 //pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_DEATTACH_ISR_STATE;
4889 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_LOCKED_STATE;
4890 pXCResourcePrivate->stdrvXC_Display._bNeedReloadMCNR = TRUE;
4891 }
4892 }
4893 break;
4894
4895 #endif
4896
4897 #if ENABLE_LOCK_IVS_OVS_FOR_ATV
4898 case FPLL_LOCK_ATV_ADJUST_IVS_STATE:
4899 {
4900 MS_U32 u32VPeriod = 0;
4901 if(_MApi_XC_FPLL_IsIvsFreqStable(pInstance, &u32VPeriod))
4902 {
4903 _MApi_XC_FPLL_AdjustOvsVtt(pInstance, u32VPeriod);
4904 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_LOCK_ATV_IVS_OVS_STATE;
4905 pXCResourcePrivate->stdrvXC_Display._u32MCNRTimer = MsOS_GetSystemTime();
4906 }
4907 else if(FPLL_ATV_FSM_FREQ_STABLE_TIME < (MsOS_GetSystemTime() - pXCResourcePrivate->stdrvXC_Display.s_u32FSMTimer))
4908 {
4909 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_LOCK_ATV_IVS_OVS_STATE;
4910 pXCResourcePrivate->stdrvXC_Display._u32MCNRTimer = MsOS_GetSystemTime();
4911 }
4912 }
4913 break;
4914
4915 case FPLL_LOCK_ATV_IVS_OVS_STATE:
4916 {
4917 if(FPLL_ATV_FSM_FREERUN_STABLE_TIME < (MsOS_GetSystemTime() - pXCResourcePrivate->stdrvXC_Display.s_u32FSMTimer))
4918 {
4919 MDrv_SC_set_fpll(pInstance, ENABLE, DISABLE, 0);
4920 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_WAIT_LPLL_OFS_STATE;
4921 pXCResourcePrivate->stdrvXC_Display._u32MCNRTimer = MsOS_GetSystemTime();
4922 }
4923 }
4924 break;
4925 #endif
4926
4927 case FPLL_WAIT_LPLL_OFS_STATE://atv special
4928 // We set PHASE_OFFSET_LIMIT to "limit for lpll phase offset", the "phase dif value" will take
4929 // PHASE_OFFSET_LIMIT+1 as its max value. then we set the gate to PHASE_OFFSET_LIMIT,
4930 // every case the "phase dif value" is smaller or equal to the PHASE_OFFSET_LIMIT,
4931 // we consider the phase is changed to a level, then we can do the adjustment.
4932 MDrv_Scaler_GetLPLLPhaseOfs(&u32Ofs,&Dir);
4933
4934 //u16PhaseLimit = pXCResourcePrivate->stdrvXC_Display._bFpllCusFlag[E_FPLL_FLAG_PHASELIMIT] ? pXCResourcePrivate->stdrvXC_Display._u32FpllCusData[E_FPLL_FLAG_PHASELIMIT] : PHASE_OFFSET_LIMIT;
4935 u16PhaseLimit = MDrv_Read2Byte(L_BK_LPLL(0x0A));
4936 #if (!ENABLE_LOCK_IVS_OVS_FOR_ATV)
4937 if (u32Ofs <= u16PhaseLimit)
4938 {
4939
4940 MDrv_SC_set_fpll(pInstance, ENABLE, DISABLE, 0);
4941 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_VD_LOCKED_STATE;
4942 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING_ISR, "Phase offs go into limit~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n")
4943 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING_ISR, "[WAIT LPLL OFS] -> [VD LOCKED]\n")
4944 }
4945 else if(FPLL_FSM_STABLE_TIME < (MsOS_GetSystemTime() - pXCResourcePrivate->stdrvXC_Display.s_u32FSMTimer))
4946 {
4947 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_DEATTACH_ISR_STATE; // force re-start
4948 }
4949
4950 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING_ISR, "===> Phase Diff=0x%tx, Limit=0x%x\n", (ptrdiff_t)u32Ofs, u16PhaseLimit)
4951 #else
4952 if (IsVBY1_16LANE(u8LPLL_Type))
4953 {
4954 if (u32Ofs <= u16PhaseLimit)
4955 {
4956
4957 MDrv_SC_set_fpll(pInstance, ENABLE, DISABLE, 0);
4958 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_VD_LOCKED_STATE;
4959 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING_ISR, "Phase offs go into limit~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n")
4960 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING_ISR, "[WAIT LPLL OFS] -> [VD LOCKED]\n")
4961 }
4962 else if(FPLL_FSM_STABLE_TIME < (MsOS_GetSystemTime() - pXCResourcePrivate->stdrvXC_Display.s_u32FSMTimer))
4963 {
4964 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_DEATTACH_ISR_STATE; // force re-start
4965 }
4966
4967 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING_ISR, "===> Phase Diff=0x%tx, Limit=0x%x\n", (ptrdiff_t)u32Ofs, u16PhaseLimit)
4968
4969 }
4970 else
4971 {
4972 MDrv_SC_set_fpll(pInstance, ENABLE, DISABLE, 0);
4973 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_VD_LOCKED_STATE;
4974 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING_ISR, "Phase offs go into limit~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n")
4975 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING_ISR, "[WAIT LPLL OFS] -> [VD LOCKED]\n")
4976 }
4977
4978 #endif
4979 break;
4980
4981 case FPLL_VD_LOCKED_STATE://atv special
4982 {
4983 pXCResourcePrivate->stdrvXC_Display.u32OutputPhaseStable = TRUE;
4984 pXCResourcePrivate->stdrvXC_Display.u32OutputPRDLock = TRUE;
4985
4986 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
4987 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.bFRC)
4988 {
4989 Hal_XC_FRC_R2_Set_FPLL_Lockdone(pInstance, TRUE);
4990 }
4991 #endif
4992
4993 if(pXCResourcePrivate->stdrvXC_Display._bNeedReloadMCNR
4994 && pXCResourcePrivate->stdrvXC_Display._bEnableMCNR[MAIN_WINDOW]
4995 && !pXCResourcePrivate->stdrvXC_Display._bForceDisableMCNR)
4996 {
4997 MS_U32 u32VPeriod = 0;
4998 if(_MApi_XC_FPLL_IsIvsFreqStable(pInstance, &u32VPeriod))
4999 {
5000 //Wait some vsync, then turn on MCNR
5001 if(_MDrv_SC_FPLL_GetMCNRDelayTime_For_ISR( pInstance, u32VPeriod) < (MsOS_GetSystemTime() - pXCResourcePrivate->stdrvXC_Display._u32MCNRTimer))
5002 {
5003 if (!pXCResourcePrivate->stdrvXC_Display._bSkipDisableOPWriteOffInFPLL[MAIN_WINDOW])
5004 {
5005 #if (!ENABLE_REGISTER_SPREAD)
5006 u8Bank = MDrv_ReadByte(BK_SELECT_00);
5007 #endif
5008 Hal_SC_SetOPWriteOff(pInstance, !pXCResourcePrivate->stdrvXC_Display._bEnableMCNR[MAIN_WINDOW]);
5009 #if (!ENABLE_REGISTER_SPREAD)
5010 MDrv_WriteByte(BK_SELECT_00, u8Bank);
5011 #endif
5012 }
5013 pXCResourcePrivate->stdrvXC_Display._bNeedReloadMCNR = FALSE;
5014 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_DEATTACH_ISR_STATE;
5015
5016 }
5017 }
5018 }
5019 else
5020 {
5021 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_DEATTACH_ISR_STATE;
5022 }
5023 }
5024 break;
5025
5026 case FPLL_WAIT_PRD_LOCK_STATE://Dtv special
5027 if(MDrv_Scaler_IsPRDLock(pInstance, &pXCResourcePrivate->stdrvXC_Display.s_u16OrigPrd))
5028 {
5029 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING_ISR, "[FPLL PRD locked->Phase]\n")
5030 pXCResourcePrivate->stdrvXC_Display.s_u16OrigPhase = FPLL_PHASE_MAX;
5031 pXCResourcePrivate->stdrvXC_Display.s_u32FSMTimer = MsOS_GetSystemTime();
5032 #if(PHASE_LOCK_EN)
5033 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_WAIT_PHASE_STABLE_STATE;
5034 #else
5035 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_CHECK_FRAME_LOCK_STATE;
5036 #endif
5037 }
5038 else
5039 {
5040 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
5041 // For FRC case, use LPLL lock fisrt, if lock time too long, switch to LockVfreq mode
5042 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFRCEnabled
5043 && (FPLL_SWITCH_LOCKVFREQ_TIME < (MsOS_GetSystemTime() - pXCResourcePrivate->stdrvXC_Display.s_u32FSMTimer))
5044 && _MApi_XC_FPLL_LockFreq_Is_SafeRange(pInstance)
5045 #if ((HW_DESIGN_HDMITX_VER == 1)||(HW_DESIGN_HDMITX_VER == 2)) // For Maserati+Raptor /Maxim HDMI Tx, need to lock phase, not switch to LockVfreq mode
5046 && !(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_B & E_XC_INIT_MISC_B_HDMITX_ENABLE)
5047 #endif
5048 )
5049 {
5050 #ifdef ENABLE_SPREADMODE
5051 if(MHal_XC_IsSupportSpreadMode(pInstance))
5052 {
5053 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_bSpreandEnable==TRUE) //return spreadmode to FREQ_ONLY_LOCK
5054 {
5055 W2BYTEMSK(L_BK_LPLL(0x0C), R2BYTEMSK(L_BK_LPLL(0x7A), 0x000F)<<12, 0xF000);
5056 W2BYTEMSK(L_BK_LPLL(0x0E), R2BYTEMSK(L_BK_LPLL(0x7A), 0x00F0),0x00F0);
5057 }
5058 _MApi_XC_FPLL_EnableSpreadMode(pInstance,FPLL_SPREAD_MODE_NONE);
5059 }
5060 #endif
5061 _MApi_XC_FPLL_EnableLcokFreqOnly(pInstance,TRUE);
5062
5063 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_FREQ_ONLY_LOCK_STATE;
5064 }
5065 #endif
5066
5067 if(FPLL_FSM_STABLE_TIME < (MsOS_GetSystemTime() - pXCResourcePrivate->stdrvXC_Display.s_u32FSMTimer))
5068 {
5069 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_DEATTACH_ISR_STATE; // force re-start
5070 }
5071 }
5072 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING_ISR, "PRD: phase %04x, prd %04x\n", MDrv_Read2Byte(L_BK_LPLL(0x11)), MDrv_Read2Byte(L_BK_LPLL(0x13)))
5073 break;
5074 #if(PHASE_LOCK_EN)
5075 case FPLL_WAIT_PHASE_STABLE_STATE://Dtv special
5076 if(MDrv_Scaler_IsPhaseStable(pInstance, &pXCResourcePrivate->stdrvXC_Display.s_u16OrigPhase))
5077 {
5078
5079 if(MDrv_Scaler_IsPRDLock(pInstance, &pXCResourcePrivate->stdrvXC_Display.s_u16OrigPrd)) // read current PRD again
5080 {
5081 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING_ISR, "[FPLL phase->check Frame lock]\n")
5082 }
5083
5084 MDrv_SC_set_fpll(pInstance, ENABLE, DISABLE, 0);
5085
5086 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING_ISR, "[FPLL phase->check Frame lock]\n")
5087
5088 pXCResourcePrivate->stdrvXC_Display.s_u32FSMTimer = MsOS_GetSystemTime();
5089 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_CHECK_FRAME_LOCK_STATE;
5090 }
5091 else
5092 {
5093 if(FPLL_FSM_STABLE_TIME < (MsOS_GetSystemTime() - pXCResourcePrivate->stdrvXC_Display.s_u32FSMTimer))
5094 {
5095 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_DEATTACH_ISR_STATE; // force re-start
5096 }
5097 }
5098 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING_ISR, "PHS: phase %04x, prd %04x\n", MDrv_Read2Byte(L_BK_LPLL(0x11)), MDrv_Read2Byte(L_BK_LPLL(0x13)))
5099 break;
5100 #endif
5101 case FPLL_CHECK_FRAME_LOCK_STATE://Dtv special
5102 {
5103
5104 //MDrv_Scaler_IsPRDLock(&s_u16OrigPrd); // read current PRD again
5105 //MDrv_Scaler_IsPhaseStable(&s_u16OrigPhase); // read current phase again
5106 if(MDrv_Scaler_IsPRDLock(pInstance, &pXCResourcePrivate->stdrvXC_Display.s_u16OrigPrd))
5107 {
5108 pXCResourcePrivate->stdrvXC_Display.u32OutputPRDLock = TRUE;
5109 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING_ISR, "[FPLL PRD Lock->check Frame lock]\n")
5110 }
5111 #if(PHASE_LOCK_EN)
5112 if(MDrv_Scaler_IsPhaseStable(pInstance, &pXCResourcePrivate->stdrvXC_Display.s_u16OrigPhase))
5113 {
5114 pXCResourcePrivate->stdrvXC_Display.u32OutputPhaseStable = TRUE;
5115 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING_ISR, "[FPLL phase Lock->check Frame lock]\n")
5116 }
5117 #endif
5118 LPLL_BK_STORE;
5119 LPLL_BK_SWITCH(0x00);
5120 #if(PHASE_LOCK_EN)
5121 if((MDrv_Read2Byte(L_BK_LPLL(0x11)) > FPLL_PHASE_VAR_LIMIT) || (MDrv_Read2Byte(L_BK_LPLL(0x13)) > FPLL_PRD_VAR_LIMIT))
5122 #else
5123 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
5124 if((!pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFRCEnabled) && (MDrv_Read2Byte(L_BK_LPLL(0x13)) > FPLL_PRD_VAR_LIMIT))
5125 #else
5126 if((MDrv_Read2Byte(L_BK_LPLL(0x13)) > FPLL_PRD_VAR_LIMIT))
5127 #endif
5128 #endif
5129 {
5130 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING_ISR, "CHK: phase %04x, prd %04x\n", MDrv_Read2Byte(L_BK_LPLL(0x11)), MDrv_Read2Byte(L_BK_LPLL(0x13)))
5131 if(FPLL_FSM_STABLE_TIME < (MsOS_GetSystemTime() - pXCResourcePrivate->stdrvXC_Display.s_u32FSMTimer))
5132 {
5133 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_DEATTACH_ISR_STATE; // force re-start
5134 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING_ISR, "CHK Stable count is outof range, force re-start.\n")
5135 }
5136 }
5137 else
5138 {
5139 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_LOCKED_STATE;
5140 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING_ISR, "Locked, the using SET is %tx\n", (ptrdiff_t)MDrv_Read4Byte(L_BK_LPLL(0x28)))
5141 }
5142 LPLL_BK_RESTORE;
5143 }
5144 break;
5145 case FPLL_FREQ_ONLY_LOCK_WAIT_PHASE_STABLE_STATE://Dtv special
5146 {
5147 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
5148 LPLL_BK_STORE;
5149 LPLL_BK_SWITCH(0x00);
5150 if ((MDrv_Read4Byte(L_BK_LPLL(0x3D)) < FPLL_PHASE_DIFF_MAX))
5151 {
5152 _MApi_XC_FPLL_AdjustVtt_ForPhaseLock(pInstance, FALSE);
5153 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_LOCKED_STATE;
5154 }
5155 LPLL_BK_RESTORE;
5156 #endif
5157 }
5158 break;
5159 case FPLL_LOCKED_STATE://Dtv special
5160 {
5161 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
5162 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.bFRC)
5163 {
5164 Hal_XC_FRC_R2_Set_FPLL_Lockdone(pInstance, TRUE);
5165 }
5166 #endif
5167 if(pXCResourcePrivate->stdrvXC_Display._bNeedReloadMCNR
5168 && pXCResourcePrivate->stdrvXC_Display._bEnableMCNR[MAIN_WINDOW]
5169 && !pXCResourcePrivate->stdrvXC_Display._bForceDisableMCNR)
5170 {
5171 MS_U32 u32VPeriod = 0;
5172 if(_MApi_XC_FPLL_IsIvsFreqStable(pInstance, &u32VPeriod))
5173 {
5174 //Wait some vsync, then turn on MCNR
5175 if(_MDrv_SC_FPLL_GetMCNRDelayTime_For_ISR( pInstance, u32VPeriod) < (MsOS_GetSystemTime() - pXCResourcePrivate->stdrvXC_Display._u32MCNRTimer))
5176 {
5177 if (!pXCResourcePrivate->stdrvXC_Display._bSkipDisableOPWriteOffInFPLL[MAIN_WINDOW])
5178 {
5179 #if (!ENABLE_REGISTER_SPREAD)
5180 u8Bank = MDrv_ReadByte(BK_SELECT_00);
5181 #endif
5182 Hal_SC_SetOPWriteOff(pInstance, !pXCResourcePrivate->stdrvXC_Display._bEnableMCNR[MAIN_WINDOW]);
5183 #if (!ENABLE_REGISTER_SPREAD)
5184 MDrv_WriteByte(BK_SELECT_00, u8Bank);
5185 #endif
5186 }
5187 pXCResourcePrivate->stdrvXC_Display._bNeedReloadMCNR = FALSE;
5188 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_DEATTACH_ISR_STATE;
5189 }
5190 }
5191
5192 }
5193 else
5194 {
5195 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_DEATTACH_ISR_STATE;
5196 }
5197 }
5198 break;
5199
5200 case FPLL_DEATTACH_ISR_STATE:
5201 {
5202 //switch bank back
5203 //MS_BOOL bret;
5204 //u8Bank = MDrv_ReadByte(BK_SELECT_00);
5205 //bret = MDrv_XC_InterruptDeAttachWithoutMutex(SC_INT_VSINT, _MApi_XC_FPLL_FSM_ISR, (void *) &bFPLL_FSM);
5206 //MDrv_WriteByte(BK_SELECT_00, u8Bank);
5207 // If we cannot lock, the bank31_0c will be 0x48, we clear it to 0x08,
5208 // which is the same with the Non-FSM case.
5209
5210 LPLL_BK_STORE;
5211 LPLL_BK_SWITCH(0x00);
5212 MDrv_WriteRegBit(L_BK_LPLL(0x0C), FALSE, BIT(6));
5213 LPLL_BK_RESTORE;
5214 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_IDLE_STATE;
5215 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING_ISR, "FSM ISR: de-attached ISR result=%u, and reset FSM to Idle\n",
5216 MDrv_XC_InterruptDeAttachWithoutMutex(pInstance, SC_INT_VSINT, _MApi_XC_FPLL_FSM_ISR, (void *) &pXCResourcePrivate->stdrvXC_Display.bFPLL_FSM));
5217 }
5218 break;
5219
5220 default:
5221 break;
5222 }
5223 }
5224
_MApi_XC_FPLL_ThreshMode_ISR(SC_INT_SRC eIntNum,void * pParam)5225 static void _MApi_XC_FPLL_ThreshMode_ISR(SC_INT_SRC eIntNum, void *pParam)
5226 {
5227 void *pInstance = pu32XCInst_private;
5228 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5229 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5230 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
5231 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
5232 if(eIntNum >= MAX_SC_INT)
5233 {
5234 printf("Interrupt number >= max scaler interrupt number\n");
5235 }
5236 if(pParam == NULL)
5237 {
5238 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING_ISR,"ISR pParam is NULL\n");
5239 }
5240
5241 switch (pXCResourcePrivate->stdrvXC_Display._enFpllThreshMode)
5242 {
5243 case FPLL_THRESH_MODE_IDLE_STATE:
5244 // no signal, do nothing
5245 break;
5246
5247 case FPLL_THRESH_MODE_LOCKED_STATE:
5248 {
5249 if(pXCResourcePrivate->stdrvXC_Display._bEnableMCNR[MAIN_WINDOW] && !pXCResourcePrivate->stdrvXC_Display._bForceDisableMCNR)
5250 {
5251 MS_U32 u32VPeriod = 0;
5252 if(_MApi_XC_FPLL_IsIvsFreqStable(pInstance, &u32VPeriod))
5253 {
5254 //Wait some vsync, then turn on MCNR
5255 if(_MDrv_SC_FPLL_GetMCNRDelayTime_For_ISR(pInstance,u32VPeriod) < (MsOS_GetSystemTime() - pXCResourcePrivate->stdrvXC_Display._u32MCNRTimer))
5256 {
5257 if (!pXCResourcePrivate->stdrvXC_Display._bSkipDisableOPWriteOffInFPLL[MAIN_WINDOW])
5258 {
5259 Hal_SC_SetOPWriteOff(pInstance, DISABLE);
5260 }
5261 pXCResourcePrivate->stdrvXC_Display._bNeedReloadMCNR = FALSE;
5262 pXCResourcePrivate->stdrvXC_Display._enFpllThreshMode = FPLL_THRESH_MODE_DEATTACH_ISR_STATE;
5263 }
5264 }
5265 }
5266 else
5267 {
5268 pXCResourcePrivate->stdrvXC_Display._enFpllThreshMode = FPLL_THRESH_MODE_DEATTACH_ISR_STATE;
5269 }
5270 }
5271 break;
5272
5273 case FPLL_THRESH_MODE_DEATTACH_ISR_STATE:
5274 {
5275 MDrv_XC_InterruptDeAttachWithoutMutex(pInstance, SC_INT_VSINT, _MApi_XC_FPLL_ThreshMode_ISR, NULL);
5276 pXCResourcePrivate->stdrvXC_Display._enFpllThreshMode = FPLL_THRESH_MODE_IDLE_STATE;
5277 }
5278 break;
5279
5280 default:
5281 break;
5282 }
5283 }
5284
5285 /*
5286 Frame lock mechanism should be detected here.
5287 msAPI_Scaler_FPLL_FSM wait to lock frame only if the
5288 phase error is small enough.
5289 */
msAPI_Scaler_FPLL_FSM_U2(void * pInstance,SCALER_WIN eWindow)5290 void msAPI_Scaler_FPLL_FSM_U2(void* pInstance, SCALER_WIN eWindow)
5291 {
5292 // use _MApi_XC_FPLL_FSM_ISR() now
5293 UNUSED(eWindow);
5294
5295 return;
5296 }
5297
msAPI_Scaler_FPLL_FSM(SCALER_WIN eWindow)5298 void msAPI_Scaler_FPLL_FSM(SCALER_WIN eWindow)
5299 {
5300 if (pu32XCInst == NULL)
5301 {
5302 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
5303 return;
5304 }
5305
5306 stXC_SET_FPLL_FSM XCArgs;
5307 XCArgs.eWindow = eWindow;
5308
5309 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_FPLL_FSM, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
5310 {
5311 printf("Obtain XC engine fail\n");
5312 return;
5313 }
5314 else
5315 {
5316 return;
5317 }
5318 }
5319
MApi_XC_SetPanelTiming_FSM(void * pInstance,XC_SetTiming_Info * pTimingInfo,SCALER_WIN eWindow)5320 void MApi_XC_SetPanelTiming_FSM(void *pInstance, XC_SetTiming_Info *pTimingInfo, SCALER_WIN eWindow)
5321 {
5322 //MS_U8 u8Bank;
5323 MS_U8 u8FRC_In, u8FRC_Out;
5324 MS_U32 u32HighAccurateInputVFreq = 0;
5325 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5326 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5327 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
5328 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
5329 XC_DISPLAYOUT_INFO eDisplyout_Info;
5330 eDisplyout_Info.u16Htt_out = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HTotal;
5331 eDisplyout_Info.u16Vtt_out = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VTotal;
5332
5333 #if (HW_DESIGN_HDMITX_VER == 1)//Maserati +Raptor HDMITX case
5334 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_B & E_XC_INIT_MISC_B_HDMITX_ENABLE)
5335 {
5336 MDrv_WriteByteMask(H_BK_LPLL(0x0D), 0x0, (BIT(1)|BIT(0)));
5337 }
5338 #endif
5339
5340 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER < 6))
5341 if(((pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_FRC_INSIDE)
5342 || (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_FRC_INSIDE_60HZ))
5343 &&(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width == 1280)
5344 &&(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height== 720))
5345 {
5346 eDisplyout_Info.u16Htt_out = 2200;
5347 eDisplyout_Info.u16Vtt_out = 1130;
5348 }
5349 #endif
5350
5351 //calculate the time of 2 input vsync
5352 if(pTimingInfo->u16InputVFreq > 0)
5353 pXCResourcePrivate->stdrvXC_Display.s_u32DelayT = 20000 / pTimingInfo->u16InputVFreq + 20;
5354 else
5355 pXCResourcePrivate->stdrvXC_Display.s_u32DelayT = 1;
5356
5357 MDrv_SC_set_fpll(pInstance, DISABLE, ENABLE, 0);
5358 #if ((HW_DESIGN_4K2K_VER == 6) && FRC_INSIDE)
5359 if((pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_B & E_XC_INIT_MISC_B_HDMITX_FREERUN_UCNR_ENABLE)&&
5360 pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFRCEnabled)
5361 {
5362 Hal_SC_SetOPWriteOff(pInstance, DISABLE);//If enable UC, no need to disable OP Write
5363 }
5364 else
5365 {
5366 Hal_SC_SetOPWriteOff(pInstance, ENABLE);//Disable MCNR first, Enable MCNR when FPLL done
5367 }
5368 #else
5369 Hal_SC_SetOPWriteOff(pInstance, ENABLE);//Disable MCNR first, Enable MCNR when FPLL done
5370 #endif
5371
5372 if(!pXCResourcePrivate->stdrvXC_MVideo._SContext.bEnableFPLLManualDebug)
5373 {
5374 MDrv_Scaler_SetPhaseLimit(pInstance, 0);
5375 }
5376
5377 //MDrv_WriteByte(BK_SELECT_00, REG_BANK_S_VOP);
5378 if (!pTimingInfo->bMVOPSrc)
5379 {
5380 // according to customer side test experience, ATV disable framelock point,
5381 // could get better result.
5382 //MDrv_WriteRegBit(L_BK_S_VOP(0x56), 0, BIT(1));
5383 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_56_L, 0x00 ,BIT(1));
5384 }
5385 else
5386 {
5387 //MDrv_WriteRegBit(L_BK_S_VOP(0x56), 1, BIT(1)); //Using new ovs_ref
5388 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_56_L, 0x02 ,BIT(1));
5389 }
5390
5391 MS_BOOL bTmpFBL = FALSE;
5392 #ifdef UFO_XC_FB_LEVEL
5393 if((gSrcInfo[eWindow].eFBLevel == E_XC_FB_LEVEL_FBL) || (gSrcInfo[eWindow].eFBLevel == E_XC_FB_LEVEL_RFBL_DI))
5394 {
5395 bTmpFBL = FALSE;//FIXME
5396 }
5397 #else
5398 bTmpFBL = gSrcInfo[eWindow].bFBL;
5399 #endif
5400
5401 gSrcInfo[eWindow].Status2.u16OutputVFreqAfterFRC = MDrv_SC_Cal_FRC_Output_Vfreq(pInstance, pTimingInfo->u16InputVFreq,
5402 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq,
5403 bTmpFBL,
5404 &u8FRC_In,
5405 &u8FRC_Out,
5406 &gSrcInfo[eWindow].bEnableFPLL,
5407 0,
5408 eWindow);
5409 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "FSM: _u16OutputVFreqAfterFRC = %u\n", gSrcInfo[eWindow].Status2.u16OutputVFreqAfterFRC );
5410
5411 #ifdef UFO_XC_FB_LEVEL
5412 if((gSrcInfo[eWindow].eFBLevel == E_XC_FB_LEVEL_FBL) || (gSrcInfo[eWindow].eFBLevel == E_XC_FB_LEVEL_RFBL_DI))
5413 {
5414 bTmpFBL = FALSE;
5415 }
5416 #else
5417 bTmpFBL = gSrcInfo[eWindow].bFBL;//FIXME
5418 #endif
5419
5420 if (bTmpFBL)
5421 {
5422 //we don't use FSM flow to do FBL case
5423 MDrv_XC_SetFreeRunTiming(pInstance);
5424 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "---Now it's FBL case, FSM FPLL cannot do it. Just let it freerun.---\n")
5425 }
5426
5427 if (gSrcInfo[eWindow].bEnableFPLL == FALSE)
5428 {
5429 // if free run, we need to use freerun vfrequency instead of direct calculation
5430 pTimingInfo->u32HighAccurateInputVFreq = gSrcInfo[eWindow].Status2.u16OutputVFreqAfterFRC * 100;
5431 u32HighAccurateInputVFreq = pTimingInfo->u32HighAccurateInputVFreq;
5432 }
5433 else
5434 {
5435 u32HighAccurateInputVFreq = pTimingInfo->u32HighAccurateInputVFreq * u8FRC_Out / u8FRC_In;
5436 // 4K1K FRC 120Hz output case
5437 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_FRC_INSIDE_4K1K_120HZ)
5438 {
5439 u32HighAccurateInputVFreq = u32HighAccurateInputVFreq / 2;
5440 }
5441 else if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_FRC_INSIDE_4K_HALFK_240HZ)
5442 {
5443 u32HighAccurateInputVFreq = u32HighAccurateInputVFreq / 4;
5444 }
5445
5446 #if (HW_DESIGN_4K2K_VER == 6) // for maserati 4K2K@120Hz case
5447 if((pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.bFRC)
5448 && IsVBY1_16LANE((MS_U8)(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type)))
5449 {
5450 u32HighAccurateInputVFreq = u32HighAccurateInputVFreq / 2;
5451 }
5452 #endif
5453 }
5454
5455 gSrcInfo[eWindow].Status2.u32HighAccurateOutputVFreqAfterFRC = u32HighAccurateInputVFreq;
5456 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "u32HighAccurateInputVFreq = %tu\n", (ptrdiff_t)u32HighAccurateInputVFreq);
5457
5458 MDrv_SC_set_Htt_Vtt(pInstance, pTimingInfo, &gSrcInfo[eWindow].Status2.u16OutputVFreqAfterFRC,u32HighAccurateInputVFreq , &eDisplyout_Info, eWindow);
5459
5460 //By RD's suggestion, prevent value of lock point is set out of vtt.
5461 //BK68 vtt patch needs to wait for the vtt change works.
5462 #if defined(PATCH_HW_VTT_LIMITATION)
5463 if( (MDrv_ReadByte(REG_CHIP_REVISION) < HW_VTT_LIMITATION_CHIPREV)&&
5464 (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_B & E_XC_INIT_MISC_B_HDMITX_ENABLE))
5465 {
5466 //Check if the tgen output VTT is as expectd.
5467 MS_U8 u8TimeoutCnt=0;
5468 while(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_36_L, VOP_VTT_MASK)
5469 != SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_32_L, VOP_VTT_MASK))
5470 {
5471 MDrv_XC_WaitOutputVSync(pInstance, 1, 50, MAIN_WINDOW);
5472 if(u8TimeoutCnt++ >= 5)
5473 {
5474 break;
5475 }
5476 }
5477 }
5478 #endif
5479
5480 MDrv_SC_Set_LockFreeze_Point(pInstance, pTimingInfo, eDisplyout_Info.u16Vtt_out, eWindow);
5481
5482
5483 MDrv_SC_set_output_dclk(pInstance, eDisplyout_Info.u16Htt_out,
5484 eDisplyout_Info.u16Vtt_out,
5485 gSrcInfo[eWindow].Status2.u16OutputVFreqAfterFRC, u32HighAccurateInputVFreq, eWindow);
5486
5487 _MDrv_Scaler_SetIGainPGain(pInstance, u8FRC_Out, gSrcInfo[eWindow].Status2.u16OutputVFreqAfterFRC, eWindow);
5488
5489 #ifdef FA_1920X540_OUTPUT
5490 if((!pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.bFRC)&&
5491 ((MDrv_XC_Get_3D_Input_Mode(pInstance, MAIN_WINDOW) == E_XC_3D_INPUT_SIDE_BY_SIDE_HALF)||
5492 (MDrv_XC_Get_3D_Input_Mode(pInstance, MAIN_WINDOW) == E_XC_3D_INPUT_TOP_BOTTOM)||
5493 (MDrv_XC_Get_3D_Input_Mode(pInstance, MAIN_WINDOW) == E_XC_3D_INPUT_FIELD_ALTERNATIVE))&&
5494 (MDrv_XC_Get_3D_Output_Mode(pInstance) == E_XC_3D_OUTPUT_FRAME_ALTERNATIVE))
5495 {
5496 #if defined(PATCH_HW_VTT_LIMITATION)
5497 if(MDrv_ReadByte(REG_CHIP_REVISION) < HW_VTT_LIMITATION_CHIPREV)
5498 {
5499 MHal_XC_SetVopVttByBK68(pInstance, (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVTotal/2), 0);
5500 MDrv_XC_WaitOutputVSync(pInstance, 1, 50, MAIN_WINDOW);
5501 }
5502 else
5503 #endif
5504 {
5505 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_0D_L, (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVTotal/2), VOP_VTT_MASK);
5506 }
5507 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5508 if (psXCInstPri->u32DeviceID == 0)
5509 {
5510 SC_W2BYTE(1, REG_SC_BK10_0D_L, VOP_VTT_MASK);
5511 }
5512 #endif
5513 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
5514 MHal_FRC_SetYTrig(pInstance, 0x88f, 0x890); //Need to set Y Trig again after adjust vtt
5515 #endif
5516 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "###g_XC_InitData.stPanelInfo.u16DefaultVTotal=%x\n",pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVTotal/2);
5517 }
5518 #endif
5519 #ifdef TBP_1920X2160_OUTPUT
5520 if((!pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.bFRC)&&
5521 ((gSrcInfo[MAIN_WINDOW].stCapWin.height == DOUBLEHD_1080X2P_VSIZE)||
5522 (gSrcInfo[MAIN_WINDOW].stCapWin.height == DOUBLEHD_1080X2I_VSIZE))&&
5523 (MDrv_XC_Get_3D_Input_Mode(pInstance, MAIN_WINDOW) == E_XC_3D_INPUT_FRAME_PACKING)&&
5524 (MDrv_XC_Get_3D_Output_Mode(pInstance) == E_XC_3D_OUTPUT_TOP_BOTTOM))
5525 {
5526 #if defined(PATCH_HW_VTT_LIMITATION)
5527 if(MDrv_ReadByte(REG_CHIP_REVISION) < HW_VTT_LIMITATION_CHIPREV)
5528 {
5529 MHal_XC_SetVopVttByBK68(pInstance, (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVTotal*2), 0);
5530 MDrv_XC_WaitOutputVSync(pInstance, 1, 50, MAIN_WINDOW);
5531 }
5532 else
5533 #endif
5534 {
5535 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_0D_L, (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVTotal*2), VOP_VTT_MASK);
5536 }
5537 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5538 if (psXCInstPri->u32DeviceID == 0)
5539 {
5540 SC_W2BYTE(1, REG_SC_BK10_0D_L, VOP_VTT_MASK);
5541 }
5542 #endif
5543 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
5544 MHal_FRC_SetYTrig(pInstance, 0x88f, 0x890); //Need to set Y Trig again after adjust vtt
5545 #endif
5546 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "###g_XC_InitData.stPanelInfo.u16DefaultVTotal=%x\n",pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVTotal*2);
5547 }
5548 #endif
5549
5550
5551 /* enable output free-run */
5552 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_1C_L, BIT(8), BIT(8)); //output free run
5553 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5554 //Follow main setting
5555 if (psXCInstPri->u32DeviceID == 0)
5556 {
5557 SC_W2BYTEMSK(1, REG_SC_BK10_1C_L, BIT(8), BIT(8));
5558 }
5559 #endif
5560 _MDrv_XC_Set_FPLL_Thresh_Mode();
5561 if(gSrcInfo[eWindow].bEnableFPLL
5562 #if FRC_INSIDE
5563 || (Hal_XC_Get_Stgen_Lock_Ip_status(pInstance) &&
5564 pXCResourcePrivate->stdrvXC_Display._bForceFreerun)
5565 #endif
5566 )//stgen lock ip under force free run should enable this register bit
5567 {
5568 /* Enable/Disable FrameLock */
5569 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_03_L, BIT(15), BIT(15));
5570 }
5571 else
5572 {
5573 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_03_L, 0, BIT(15));
5574 }
5575
5576 #if (HW_DESIGN_4K2K_VER != 6) // for manhattan, only 1 LPLL
5577 if ( pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.bFRC )
5578 {
5579 MDrv_SC_set_fpll(pInstance, gSrcInfo[eWindow].bEnableFPLL, 0, 0);
5580 }
5581 else
5582 #endif
5583 {
5584 MS_BOOL bEnable = FALSE;
5585 //#if LOCK_FREQ_ONLY_WITHOUT_LOCK_PHASE
5586 bEnable = gSrcInfo[eWindow].bEnableFPLL;
5587 //#endif
5588 MDrv_SC_set_fpll(pInstance, bEnable, gSrcInfo[eWindow].bEnableFPLL, 0);
5589 }
5590
5591 _MDrv_XC_PQ_Set_FPLL_Thresh_Mode(pInstance);
5592
5593 pXCResourcePrivate->stdrvXC_Display.s_u32InputVsyncStart = MsOS_GetSystemTime();
5594
5595 // THIS AREA IS AN EXPERIMENTAL VALUE, so if you encounter anything strange
5596 // tearing, please try to comment these code blocks.
5597 // if
5598 // (1) freerun
5599 // (2) with non-integer frame rate conversion value
5600 // we should consider manually control read bank switch
5601 MS_U16 u16SwitchCnt = 0;
5602 if(gSrcInfo[eWindow].bEnableFPLL == FALSE)
5603 {
5604 if ((u8FRC_In == 5) && (u8FRC_Out == 2))
5605 {
5606 u16SwitchCnt = 5;
5607 MDrv_SC_EnableReadBankSwitchControl(pInstance, ENABLE, u16SwitchCnt, eWindow);
5608 }
5609 else if ((u8FRC_In == 2) && (u8FRC_Out == 1))
5610 {
5611 u16SwitchCnt = 2;
5612 MDrv_SC_EnableReadBankSwitchControl(pInstance, ENABLE, u16SwitchCnt, eWindow);
5613 }
5614 }
5615 else
5616 {
5617 //MDrv_SC_EnableReadBankSwitchControl(pInstance, DISABLE, u16SwitchCnt, eWindow);
5618 }
5619
5620 if(gSrcInfo[eWindow].bEnableFPLL)
5621 {
5622 if(IsSrcTypeDigitalVD(gSrcInfo[eWindow].enInputSourceType))
5623 {
5624 #if LOCK_FREQ_ONLY_WITHOUT_LOCK_PHASE
5625 _MApi_XC_FPLL_EnableLcokFreqOnly(pInstance,FALSE);
5626 #endif
5627 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_ATV_INIT_STATE;
5628 }
5629 else
5630 {
5631 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_INIT_STATE;
5632 }
5633 }
5634 else
5635 {
5636 pXCResourcePrivate->stdrvXC_Display._bNeedReloadMCNR = FALSE;
5637 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_IDLE_STATE;
5638 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "FPLL disabled, reset FSM to Idle\n")
5639 }
5640 }
5641
5642 //////////////////////////////////////////////////////----------------
5643
MApi_XC_SetPanelTiming_NonFSM(void * pInstance,XC_SetTiming_Info * pTimingInfo,SCALER_WIN eWindow)5644 void MApi_XC_SetPanelTiming_NonFSM(void *pInstance, XC_SetTiming_Info *pTimingInfo, SCALER_WIN eWindow)
5645 {
5646 //MS_U8 u8Bank;
5647 MS_U8 u8FRC_In, u8FRC_Out;
5648 MS_U32 u32HighAccurateInputVFreq = 0;
5649 XC_DISPLAYOUT_INFO eDisplyout_Info;
5650 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5651 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5652 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
5653 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
5654 eDisplyout_Info.u16Htt_out = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HTotal;
5655 eDisplyout_Info.u16Vtt_out = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VTotal;
5656 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER < 6))
5657 if(((pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_FRC_INSIDE)
5658 || (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_FRC_INSIDE_60HZ))
5659 &&(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width == 1280)
5660 &&(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height == 720))
5661 {
5662 eDisplyout_Info.u16Htt_out = 2200;
5663 eDisplyout_Info.u16Vtt_out = 1130;
5664 }
5665 #endif
5666
5667 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "bFBL=%u, bMVOPSrc=%u, InputVFreq=%u, InputVtt=%u, bInterlace=%u bFastFL=%u\n",
5668 gSrcInfo[eWindow].bFBL,
5669 pTimingInfo->bMVOPSrc,
5670 pTimingInfo->u16InputVFreq,
5671 pTimingInfo->u16InputVTotal,
5672 pTimingInfo->bInterlace,
5673 pTimingInfo->bFastFrameLock);
5674 Hal_SC_SetOPWriteOff(pu32XCInst, ENABLE);//Disable MCNR first, Enable MCNR when FPLL done
5675 gSrcInfo[eWindow].bFastFrameLock = pTimingInfo->bFastFrameLock;
5676
5677 //u8Bank = MDrv_ReadByte(BK_SELECT_00); // backup first
5678 MDrv_SC_set_fpll(pInstance, DISABLE, ENABLE, 0); // disable FPLL
5679
5680 MDrv_Scaler_SetPhaseLimit(pInstance, 0);
5681
5682 //MDrv_WriteByte(H_BK_LPLL(0x05), 0xF0);
5683 //MDrv_WriteByte(L_BK_LPLL(0x05), 0x22);
5684
5685 #if VERIFY_DISPLAY_FPGA
5686 MDrv_Write3Byte(L_BK_LPLL(0x06), 0x30000);
5687 MDrv_Write3Byte(L_BK_LPLL(0x08), 0x30000);
5688 MDrv_Write2Byte(L_BK_LPLL(0x0A), 0xFFF0); // limit for lpll phase limit offset; set it to speed up frame lock
5689
5690 u8FRC_In = 2;
5691 u8FRC_Out = 5;
5692 gSrcInfo[eWindow].Status2.u16OutputVFreqAfterFRC = pTimingInfo->u16InputVFreq * u8FRC_Out/u8FRC_In;
5693
5694 gSrcInfo[eWindow].bEnableFPLL = TRUE;
5695
5696 #ifdef UFO_XC_FB_LEVEL
5697 if(gSrcInfo[eWindow].eFBLevel == E_XC_FB_LEVEL_FB)//FIXME
5698 #else
5699 if(!gSrcInfo[eWindow].bFBL )
5700 #endif
5701 {
5702 MDrv_WriteByte(H_BK_LPLL(0x0C), ((u8FRC_Out-1) << 4) | (u8FRC_In-1));
5703 }
5704 else
5705 {
5706 // fps_in:fps_out = 1:1 for FBL, only main can use FBL
5707 MDrv_WriteByte(H_BK_LPLL(0x0C), 0x00);
5708 MDrv_WriteByte(L_BK_LPLL(0x0E), 0x00);
5709 }
5710 #else
5711 MS_BOOL bTmpFBL = FALSE;
5712 #ifdef UFO_XC_FB_LEVEL
5713 if((gSrcInfo[eWindow].eFBLevel == E_XC_FB_LEVEL_FBL) || (gSrcInfo[eWindow].eFBLevel == E_XC_FB_LEVEL_RFBL_DI))
5714 {
5715 bTmpFBL = TRUE;
5716 }
5717 #else
5718 bTmpFBL = gSrcInfo[eWindow].bFBL;//FIXME
5719 #endif
5720 gSrcInfo[eWindow].Status2.u16OutputVFreqAfterFRC = MDrv_SC_Cal_FRC_Output_Vfreq(pInstance, pTimingInfo->u16InputVFreq,
5721 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq,
5722 bTmpFBL,
5723 &u8FRC_In,
5724 &u8FRC_Out,
5725 &gSrcInfo[eWindow].bEnableFPLL,
5726 0,
5727 eWindow);
5728 #endif
5729 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "NON-FSM: _u16OutputVFreqAfterFRC = %u\n", gSrcInfo[eWindow].Status2.u16OutputVFreqAfterFRC)
5730 gSrcInfo[eWindow].bDoneFPLL = !gSrcInfo[eWindow].bEnableFPLL; // if enable FPLL, then not done fpll yet
5731
5732 if (gSrcInfo[eWindow].bEnableFPLL == FALSE)
5733 {
5734 // if free run, we need to use freerun vfrequency instead of direct calculation
5735 pTimingInfo->u32HighAccurateInputVFreq = gSrcInfo[eWindow].Status2.u16OutputVFreqAfterFRC * 100;
5736 u32HighAccurateInputVFreq = pTimingInfo->u32HighAccurateInputVFreq;
5737 }
5738 else
5739 {
5740 u32HighAccurateInputVFreq = pTimingInfo->u32HighAccurateInputVFreq * u8FRC_Out / u8FRC_In;
5741 }
5742
5743 gSrcInfo[eWindow].Status2.u32HighAccurateOutputVFreqAfterFRC = u32HighAccurateInputVFreq;
5744 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "u32HighAccurateInputVFreq = %tu\n", (ptrdiff_t)u32HighAccurateInputVFreq);
5745
5746 MDrv_SC_set_Htt_Vtt(pInstance, pTimingInfo, &gSrcInfo[eWindow].Status2.u16OutputVFreqAfterFRC,u32HighAccurateInputVFreq , &eDisplyout_Info, eWindow);
5747
5748 MDrv_SC_Set_LockFreeze_Point(pInstance, pTimingInfo, eDisplyout_Info.u16Vtt_out, eWindow);
5749
5750 MDrv_SC_set_output_dclk(pInstance, eDisplyout_Info.u16Htt_out,
5751 eDisplyout_Info.u16Vtt_out,
5752 gSrcInfo[eWindow].Status2.u16OutputVFreqAfterFRC, 0, eWindow);
5753
5754 _MDrv_Scaler_SetIGainPGain(pInstance, u8FRC_Out, gSrcInfo[eWindow].Status2.u16OutputVFreqAfterFRC, eWindow);
5755 //MDrv_WriteByte(BK_SELECT_00, REG_BANK_VOP);
5756 //MDrv_WriteRegBit(H_BK_VOP(0x1C), 1, BIT(0)); //output free run
5757 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_1C_L, BIT(8), BIT(8)); //output free run
5758 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
5759 //Follow main setting
5760 if (psXCInstPri->u32DeviceID == 0)
5761 {
5762 SC_W2BYTEMSK(1, REG_SC_BK10_1C_L, BIT(8), BIT(8));
5763 }
5764 #endif
5765 _MDrv_XC_Set_FPLL_Thresh_Mode();
5766
5767 if (gSrcInfo[eWindow].bEnableFPLL)
5768 {
5769 //MDrv_WriteByte(BK_SELECT_00, REG_BANK_IP1F2);
5770 //MDrv_WriteRegBit(H_BK_IP1F2(0x03), 1, BIT(7)); //enable frame lock
5771 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_03_L, BIT(15), BIT(15)); //enable frame lock
5772
5773 if (gSrcInfo[eWindow].bFastFrameLock) //MDrv_ReadRegBit(H_BK_LPLL(0x1E), 0x10)
5774 {
5775 MDrv_Scaler_FastFrameLock(pInstance, pTimingInfo->u16InputVFreq, gSrcInfo[eWindow].Status2.u16OutputVFreqAfterFRC);
5776 //MDrv_XC_DisableInputSource(FALSE, MAIN_WINDOW); //enable Input
5777 }
5778 else
5779 {
5780 //MDrv_XC_DisableInputSource(FALSE, MAIN_WINDOW); //enable Input
5781 HAL_SC_EnableFPLL();
5782 }
5783 pXCResourcePrivate->stdrvXC_Display._u32MCNRTimer = MsOS_GetSystemTime();
5784 pXCResourcePrivate->stdrvXC_Display._bNeedReloadMCNR = TRUE;
5785 }
5786 else
5787 {
5788 pXCResourcePrivate->stdrvXC_Display._bNeedReloadMCNR = FALSE;
5789 }
5790 #if FRC_INSIDE
5791 //stgen lock ip under force free run should enable this register bit
5792 if(Hal_XC_Get_Stgen_Lock_Ip_status(pInstance) && pXCResourcePrivate->stdrvXC_Display._bForceFreerun)
5793 {
5794 /* Enable/Disable FrameLock */
5795 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_03_L, BIT(15), BIT(15));
5796 }
5797 #endif
5798 _MDrv_XC_PQ_Set_FPLL_Thresh_Mode(pInstance);
5799
5800 #if 0
5801 u16temp = 0;
5802 while( !(MDrv_ReadByte(H_BK_LPLL(0x2A)) & BIT0) && u16temp<3000 )
5803 {
5804 u16temp++;
5805 MsOS_DelayTask(1);
5806 }
5807 printf("[FPLL Speed]Time= %d\n", msAPI_Timer_DiffTimeFromNow(u32TestTimer));
5808 printf("[FPLL Speed]temp= %d\n", u16temp);
5809 #endif
5810
5811 #if 0
5812 for(u16temp=0; u16temp<20; u16temp++)
5813 {
5814 printf("\n%d\n", u16temp);
5815 printf("[Freeze]Phase dif= 0x%X (%u)\n", MDrv_Read2Byte(L_BK_LPLL(0x11)), MDrv_Read2Byte(L_BK_LPLL(0x11)));
5816 printf("[Freeze]Phase up= 0x%X (%u)\n", MDrv_ReadByte(L_BK_LPLL(0x12)), MDrv_ReadByte(L_BK_LPLL(0x12)));
5817 printf("[Freeze]SET using= 0x%X (%u)\n", MDrv_Read2Byte(L_BK_LPLL(0x28))|(MDrv_ReadByte(L_BK_LPLL(0x29))<<16),
5818 MDrv_Read2Byte(L_BK_LPLL(0x28))|(MDrv_ReadByte(L_BK_LPLL(0x29))<<16));
5819 MsOS_DelayTask((10000/pTimingInfo->u16InputVFreq));
5820 }
5821 #endif
5822 }
5823
5824 #if FRC_INSIDE
MApi_XC_SetFLock(void * pInstance,XC_SetTiming_Info * pTimingInfo,SCALER_WIN eWindow)5825 void MApi_XC_SetFLock(void *pInstance, XC_SetTiming_Info *pTimingInfo, SCALER_WIN eWindow)
5826 {
5827 #if (HW_DESIGN_4K2K_VER == 6)
5828 // For Manhattan, FSC+FRC, 2 TGEN but only 1 LPLL case
5829
5830 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5831 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5832 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
5833 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
5834 MS_U8 u8FRC_In, u8FRC_Out;
5835 MS_U16 u16DefaultVFreq = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq;
5836 MS_U16 u16InputVFreq = pTimingInfo->u16InputVFreq;
5837 MS_U16 u16OutputVfreqAfterFRC = 0;
5838 MS_BOOL bEnableFPLL;
5839 MS_BOOL bTmpFBL = FALSE;
5840
5841 #ifdef UFO_XC_FB_LEVEL
5842 if((gSrcInfo[eWindow].eFBLevel == E_XC_FB_LEVEL_FBL) || (gSrcInfo[eWindow].eFBLevel == E_XC_FB_LEVEL_RFBL_DI))
5843 {
5844 bTmpFBL = TRUE;
5845 }
5846 #else
5847 bTmpFBL = gSrcInfo[eWindow].bFBL;//FIXME
5848 #endif
5849
5850 u16OutputVfreqAfterFRC = MDrv_SC_Cal_FRC_Output_Vfreq(pInstance, u16InputVFreq,
5851 u16DefaultVFreq,
5852 bTmpFBL,
5853 &u8FRC_In,
5854 &u8FRC_Out,
5855 &bEnableFPLL,
5856 0,
5857 eWindow);
5858 gSrcInfo[MAIN_WINDOW].Status2.u16OP1_OutputVFreqAfterFRC = u16OutputVfreqAfterFRC;
5859
5860 //use high accurate output Vfreq, or FRC output timing maybe not accurate for MEMC.
5861 //example input 29.97Hz: FRC output 239Hz calculate by low accurate Vfreq, FRC output 240Hz calculate by high accurate Vfreq
5862 u16OutputVfreqAfterFRC = (MS_U16)((gSrcInfo[eWindow].Status2.u32HighAccurateOutputVFreqAfterFRC+50)/100);
5863
5864 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.u83D_FI_out != E_XC_3D_OUTPUT_FI_MODE_NONE)
5865 {
5866 Hal_XC_FRC_R2_Set_Timing(pInstance, (u16InputVFreq+5)/10, (u16OutputVfreqAfterFRC+5)/10);
5867 }
5868 else
5869 {
5870 #if (HW_DESIGN_HDMITX_VER == 1)//Maserati +Raptor HDMITX case
5871 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_B & E_XC_INIT_MISC_B_HDMITX_ENABLE)
5872 {
5873 Hal_XC_FRC_R2_Set_Timing(pInstance, (u16OutputVfreqAfterFRC+5)/10, (u16OutputVfreqAfterFRC+5)/10);
5874 }
5875 else
5876 #endif
5877 {
5878 Hal_XC_FRC_R2_Set_Timing(pInstance, (u16InputVFreq+5)/10, (u16OutputVfreqAfterFRC+5)/10);
5879 }
5880 }
5881 #else
5882 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5883 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5884 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
5885 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
5886 MS_U8 u8FRC_In, u8FRC_Out;
5887 MS_U16 u16DefaultVFreq = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq;
5888 MS_U16 u16InputVFreq = pTimingInfo->u16InputVFreq;
5889 MS_U16 u16OutputVfreqAfterFRC = 0;
5890
5891 // For error handling
5892 if (u16InputVFreq == 0)
5893 {
5894 if (pXCResourcePrivate->stdrvXC_MVideo_Context.enFRC_CurrentInputTiming == E_XC_FRC_InputTiming_2K1K)
5895 u16InputVFreq = 10;
5896 else
5897 u16InputVFreq = 5;
5898 }
5899
5900 MS_U32 u32DClk;
5901 MS_U32 u32LpllLimitLow=0x10000;
5902 MS_U32 u32LpllLimitHigh=0x10000;
5903 MS_BOOL bEnableFPLL;
5904 MS_U16 u16HTotal = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HTotal;
5905 MS_U16 u16VTotal = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VTotal;
5906
5907 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_FRC_INSIDE)
5908 u16DefaultVFreq = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq / 2;
5909 else if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_FRC_INSIDE_60HZ)
5910 u16DefaultVFreq = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq;
5911
5912 // For 4K2K used
5913 if ((pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_FRC_INSIDE_KEEP_OP_4K2K))
5914 {
5915 u16DefaultVFreq = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq / 2;
5916 }
5917 else if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_FRC_INSIDE_4K_HALFK_240HZ)
5918 {
5919 // Make OP timing 4K x 0.5K x 120Hz
5920 u16DefaultVFreq = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq * 2;
5921 u16VTotal = u16VTotal /4;
5922 }
5923 else if ((u16HTotal > 3000) && (u16VTotal > 2000) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq > 500))
5924 {
5925 if (pXCResourcePrivate->stdrvXC_MVideo_Context.enFRC_CurrentInputTiming == E_XC_FRC_InputTiming_2K1K)
5926 {
5927 // FHD 50/60 in case
5928 u16HTotal = u16HTotal/2;
5929 }
5930 else
5931 {
5932 // 4K2K 24in/30in case
5933 u16DefaultVFreq = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq / 2;
5934 }
5935 }
5936
5937 if(MDrv_XC_Get_3D_Output_Mode(pInstance) == E_XC_3D_OUTPUT_FRAME_ALTERNATIVE)
5938 {
5939 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.u83D_FI_out == E_XC_3D_OUTPUT_FI_960x1080)
5940 {
5941 u16HTotal /= 2;
5942 u16InputVFreq *=2 ;
5943 }
5944 else if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.u83D_FI_out == E_XC_3D_OUTPUT_FI_1920x540)
5945 {
5946 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_FRC_INSIDE_240HZ)
5947 {
5948 u16VTotal = u16VTotal;
5949 u16InputVFreq = u16InputVFreq;
5950 }
5951 else
5952 {
5953 u16VTotal = u16VTotal/2;
5954 u16InputVFreq *=2 ;
5955 }
5956 }
5957 else if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.u83D_FI_out == E_XC_3D_OUTPUT_FI_1280x720)
5958 {
5959 u16InputVFreq *=2 ;
5960 }
5961 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "g_XC_Pnl_Misc.FRCInfo.u83D_FI_out=%u\n",
5962 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.u83D_FI_out);
5963
5964 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "u16HTotal=%u, u16VTotal=%u, u16InputVFreq=%u\n",
5965 u16HTotal, u16VTotal, u16InputVFreq);
5966 }
5967 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "u16HTotal=%u, u16VTotal=%u, u16InputVFreq=%u\n",
5968 u16HTotal, u16VTotal, u16InputVFreq);
5969 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "u16DefaultVFreq=%u, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq=%u\n",
5970 u16DefaultVFreq, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq);
5971
5972
5973 MDrv_SC_set_fpll(pInstance, DISABLE, ENABLE, 1);
5974 MDrv_Scaler_SetPhaseLimit(pInstance, 1);
5975
5976 #ifdef UFO_XC_FB_LEVEL
5977 if((gSrcInfo[eWindow].eFBLevel == E_XC_FB_LEVEL_FBL) || (gSrcInfo[eWindow].eFBLevel == E_XC_FB_LEVEL_RFBL_DI))
5978 {
5979 bTmpFBL = TRUE;
5980 }
5981 #else
5982 bTmpFBL = gSrcInfo[eWindow].bFBL;//FALSE
5983 #endif
5984
5985 u16OutputVfreqAfterFRC = MDrv_SC_Cal_FRC_Output_Vfreq(pInstance, u16InputVFreq,
5986 u16DefaultVFreq,
5987 bTmpFBL,
5988 &u8FRC_In,
5989 &u8FRC_Out,
5990 &bEnableFPLL,
5991 1,
5992 eWindow);
5993 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "@@========\n")
5994 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "SetFlock: u16InputVFreq = %u,u16OutputVfreqAfterFRC = %u\n",
5995 u16InputVFreq, u16OutputVfreqAfterFRC)
5996 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "SetFlock: u8FRC_In = %u,u8FRC_Out = %u, bEnableFPLL=%x\n",
5997 u8FRC_In, u8FRC_Out, bEnableFPLL)
5998
5999 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "@@========\n")
6000
6001
6002 if(MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED)
6003 {
6004 _MLOAD_ENTRY(pInstance);
6005 #if defined(PATCH_HW_VTT_LIMITATION)
6006 if(MDrv_ReadByte(REG_CHIP_REVISION) < HW_VTT_LIMITATION_CHIPREV)
6007 {
6008 MHal_XC_SetVopVttByBK68(pInstance, (u16VTotal - 1)&VOP_VTT_MASK, 1);
6009 _MLOAD_RETURN(pInstance);
6010 MDrv_XC_WaitOutputVSync(pInstance, 1, 50, MAIN_WINDOW);
6011 _MLOAD_ENTRY(pInstance);
6012 }
6013 else
6014 #endif
6015 {
6016 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0D_L,(u16VTotal - 1)&VOP_VTT_MASK, VOP_VTT_MASK);
6017 }
6018 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0C_L,(u16HTotal - 1), VOP_HTT_MASK);
6019 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
6020 //FIX ME:follow HW_DESIGN_4K2K_VER = 6 rule
6021 if (psXCInstPri->u32DeviceID == 0)
6022 {
6023 MDrv_XC_MLoad_WriteCmd(g_pDevice1Instance, REG_SC_BK10_0D_L,VOP_VTT_MASK, VOP_VTT_MASK);
6024 MDrv_XC_MLoad_WriteCmd(g_pDevice1Instance, REG_SC_BK10_0C_L,(u16HTotal/2 - 1), VOP_HTT_MASK);
6025 }
6026 #endif
6027
6028
6029 // 4K2K 60 out case
6030 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_FRC_INSIDE_KEEP_OP_4K2K)
6031 {
6032 // Kepp OP timing as 4K2K, DE for bk10 is 4Kx2K
6033 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_05_L, (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HStart+pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width - 1), VOP_DE_HEND_MASK);
6034 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_07_L, (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart+pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height- 1), VOP_DE_VEND_MASK); // DE V end
6035 }
6036 else if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_FRC_INSIDE_4K_HALFK_240HZ)
6037 {
6038 // Kepp OP timing as 4K 0.5K, DE for bk10 is 4Kx0.5K
6039 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_05_L, (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HStart+pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width - 1), VOP_DE_HEND_MASK);
6040 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_07_L, (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart+pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height/4 - 1), VOP_DE_VEND_MASK); // DE V end
6041 }
6042 else if ((u16VTotal > 2000) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq > 500))
6043 {
6044 //if ((gSrcInfo[eWindow].u16InputVFreq != 0) && (u16InputVFreq > 450))
6045 // The condition above cause H scale problem on both video & OSD with FHD 24/25/30Hz
6046 // We need more restrict & accurate condition to tell the different between UHD & FHD input.
6047 if (pXCResourcePrivate->stdrvXC_MVideo_Context.enFRC_CurrentInputTiming == E_XC_FRC_InputTiming_2K1K)
6048 {
6049 // FHD in, DE for bk10 is 2Kx2K
6050 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_05_L, (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HStart+pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width/2 - 1), VOP_DE_HEND_MASK);
6051 }
6052 else
6053 {
6054 // 4K2K in, DE for bk10 is 4Kx2K
6055 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_05_L, (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HStart+pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width - 1), VOP_DE_HEND_MASK);
6056 }
6057 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_07_L, (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart+pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height- 1), VOP_DE_VEND_MASK); // DE V end
6058 }
6059
6060 MDrv_XC_MLoad_Fire(pInstance, TRUE);
6061 _MLOAD_RETURN(pInstance);
6062 }
6063 else
6064 {
6065 #if defined(PATCH_HW_VTT_LIMITATION)
6066 if(MDrv_ReadByte(REG_CHIP_REVISION) < HW_VTT_LIMITATION_CHIPREV)
6067 {
6068 MHal_XC_SetVopVttByBK68(pInstance, (u16VTotal - 1)&VOP_VTT_MASK, 0);
6069 MDrv_XC_WaitOutputVSync(pInstance, 1, 50, MAIN_WINDOW);
6070 }
6071 else
6072 #endif
6073 {
6074 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0D_L,(u16VTotal - 1)&VOP_VTT_MASK);
6075 }
6076 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0C_L,(u16HTotal - 1));
6077 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
6078 //FIX ME:follow HW_DESIGN_4K2K_VER = 6 rule
6079 if (psXCInstPri->u32DeviceID == 0)
6080 {
6081 SC_W2BYTE(1, REG_SC_BK10_0D_L,VOP_VTT_MASK);
6082 SC_W2BYTE(1, REG_SC_BK10_0C_L,(u16HTotal/2 - 1));
6083 }
6084 #endif
6085
6086 // 4K2K 60 out case
6087 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_FRC_INSIDE_KEEP_OP_4K2K)
6088 {
6089 // Keep OP timing as 4K2K, DE for bk10 is 4Kx2K
6090 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_05_L, (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HStart+pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width - 1));
6091 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_07_L, (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart+pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height- 1));
6092 }
6093 else if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_FRC_INSIDE_4K_HALFK_240HZ)
6094 {
6095 // Kepp OP timing as 4K 0.5K, DE for bk10 is 4Kx0.5K
6096 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_05_L, (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HStart+pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width - 1));
6097 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_07_L, (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart+pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height/4 - 1)); // DE V end
6098 }
6099 else if ((u16VTotal > 2000) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq > 500))
6100 {
6101 if (pXCResourcePrivate->stdrvXC_MVideo_Context.enFRC_CurrentInputTiming == E_XC_FRC_InputTiming_2K1K)
6102 {
6103 // FHD in, DE for bk10 is 2Kx2K
6104 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_05_L, (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HStart+pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width/2 - 1));
6105 }
6106 else
6107 {
6108 // 4K2K in, DE for bk10 is 4Kx2K
6109 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_05_L, (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HStart+pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width - 1));
6110 }
6111 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_07_L, (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart+pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height- 1));
6112 }
6113 }
6114
6115 u32DClk = u16HTotal * u16VTotal * u16OutputVfreqAfterFRC;
6116 if((u16InputVFreq >= 235 )&&(u16InputVFreq <= 245 ))
6117 MDrv_Scaler_SetPhaseLock_Thresh(0x0F, 1);
6118 else
6119 MDrv_Scaler_SetPhaseLock_Thresh(0x02, 1);
6120
6121 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "Output DCLK = %lu\n\n", u32DClk);
6122 _MHal_SC_Flock_Caculate_LPLLSet(u32DClk);
6123 _MHal_SC_Flock_Set_IGainPGain(pInstance, u8FRC_Out, u16OutputVfreqAfterFRC, u16HTotal, u16VTotal);
6124 _MHal_SC_Set_LPLL_Limit(u32LpllLimitHigh, u32LpllLimitLow, 1);
6125
6126 MDrv_SC_set_fpll(pInstance, bEnableFPLL, !bEnableFPLL, 1);
6127
6128 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "Input Freq = %u, After FRC = %u\n\n", u16InputVFreq, u16OutputVfreqAfterFRC);
6129
6130 gSrcInfo[MAIN_WINDOW].Status2.u16OP1_OutputVFreqAfterFRC = u16OutputVfreqAfterFRC;
6131
6132
6133 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.u83D_FI_out != E_XC_3D_OUTPUT_FI_MODE_NONE)
6134 {
6135 Hal_XC_FRC_R2_Set_Timing(pInstance, (u16OutputVfreqAfterFRC+5)/10, (gSrcInfo[MAIN_WINDOW].Status2.u16OutputVFreqAfterFRC+5)/10);
6136 }
6137 else
6138 {
6139 Hal_XC_FRC_R2_Set_Timing(pInstance, (u16OutputVfreqAfterFRC+5)/10, (gSrcInfo[MAIN_WINDOW].Status2.u16OutputVFreqAfterFRC+5)/10);
6140 }
6141 #endif
6142 }
6143
6144 #endif
6145
6146 //-------------------------------------------------------------------------------------------------
6147 /// Set the FPLL mode:
6148 /// @param bTrue \b IN: True: FSM mode, False: Non FSM mode
6149 //-------------------------------------------------------------------------------------------------
6150
MApi_SC_Enable_FPLL_FSM_U2(void * pInstance,MS_BOOL bTrue)6151 void MApi_SC_Enable_FPLL_FSM_U2(void* pInstance, MS_BOOL bTrue)
6152 {
6153 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6154 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6155 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6156
6157 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
6158 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6159 pXCResourcePrivate->stdrvXC_Display._bFSM_FPLL_Setting = bTrue;
6160 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
6161 }
6162
MApi_SC_Enable_FPLL_FSM(MS_BOOL bTrue)6163 void MApi_SC_Enable_FPLL_FSM(MS_BOOL bTrue)
6164 {
6165 if (pu32XCInst == NULL)
6166 {
6167 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
6168 return;
6169 }
6170
6171 stXC_SET_FPLL_FSM_ENABLE XCArgs;
6172 XCArgs.bTrue = bTrue;
6173
6174 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_FPLL_FSM_ENABLE, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
6175 {
6176 printf("Obtain XC engine fail\n");
6177 return;
6178 }
6179 else
6180 {
6181 return;
6182 }
6183 }
6184
6185 //-------------------------------------------------------------------------------------------------
6186 /// Set the FPLL Thresh mode:
6187 /// @param bEnable \b IN: TRUE: Thresh mode, FALSE: Non-Thresh mode
6188 //-------------------------------------------------------------------------------------------------
6189
MApi_XC_Enable_FPLL_Thresh_Mode_U2(void * pInstance,MS_BOOL bEnable)6190 void MApi_XC_Enable_FPLL_Thresh_Mode_U2(void* pInstance, MS_BOOL bEnable)
6191 {
6192 #if FPLL_THRESH_MODE_SUPPORT
6193 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6194 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6195 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6196
6197 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
6198 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6199 pXCResourcePrivate->stdrvXC_Display._bFPLL_Thresh_Mode = bEnable;
6200 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
6201 #endif
6202 }
6203
MApi_XC_Enable_FPLL_Thresh_Mode(MS_BOOL bEnable)6204 void MApi_XC_Enable_FPLL_Thresh_Mode(MS_BOOL bEnable)
6205 {
6206 if (pu32XCInst == NULL)
6207 {
6208 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
6209 return;
6210 }
6211
6212 stXC_SET_FPLL_THRESHMODE XCArgs;
6213 XCArgs.bEnable = bEnable;
6214
6215 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_FPLL_THRESHMODE, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
6216 {
6217 printf("Obtain XC engine fail\n");
6218 return;
6219 }
6220 else
6221 {
6222 return;
6223 }
6224 }
6225
6226 //-------------------------------------------------------------------------------------------------
6227 /// Get the FPLL Thresh mode:
6228 /// @return TRUE: Thresh mode, FALSE: Non-Thresh mode
6229 //-------------------------------------------------------------------------------------------------
MApi_XC_Get_FPLL_Thresh_Mode_U2(void * pInstance)6230 MS_BOOL MApi_XC_Get_FPLL_Thresh_Mode_U2(void* pInstance)
6231 {
6232 #if FPLL_THRESH_MODE_SUPPORT
6233 MS_BOOL bReturn = FALSE;
6234 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6235 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6236 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6237 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
6238 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6239 bReturn = pXCResourcePrivate->stdrvXC_Display._bFPLL_Thresh_Mode;
6240 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
6241 return bReturn;
6242 #else
6243 return FALSE;
6244 #endif
6245 }
6246
MApi_XC_Get_FPLL_Thresh_Mode(void)6247 MS_BOOL MApi_XC_Get_FPLL_Thresh_Mode(void)
6248 {
6249 if (pu32XCInst == NULL)
6250 {
6251 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
6252 return FALSE;
6253 }
6254
6255 stXC_GET_FPLL_THRESHMODE XCArgs;
6256 XCArgs.bReturnValue = FALSE;
6257
6258 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_GET_FPLL_THRESHMODE, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
6259 {
6260 printf("Obtain XC engine fail\n");
6261 return FALSE;
6262 }
6263 else
6264 {
6265 return XCArgs.bReturnValue;
6266 }
6267 }
6268
6269 //-------------------------------------------------------------------------------------------------
6270 /// Setup panel timing (output DCLK)/FRC/FramePLL, and enable input source
6271 /// @param pTimingInfo \b IN: the information of the timing to set @ref XC_SetTiming_Info
6272 //-------------------------------------------------------------------------------------------------
MApi_XC_SetPanelTiming_U2(void * pInstance,XC_SetTiming_Info * pTimingInfo,SCALER_WIN eWindow)6273 void MApi_XC_SetPanelTiming_U2(void* pInstance, XC_SetTiming_Info *pTimingInfo, SCALER_WIN eWindow)
6274 {
6275 #ifdef MSOS_TYPE_LINUX_KERNEL
6276 /*
6277 ** Save setpaneltiming info for str
6278 */
6279 void *pModule;
6280 UtopiaInstanceGetModule(pInstance, &pModule);
6281 XC_REGS_SAVE_AREA *pXCResourceStr = NULL;
6282 UtopiaModuleGetSTRPrivate(pModule, (void**)&pXCResourceStr);
6283 memcpy(&pXCResourceStr->pTimingInfo,pTimingInfo,sizeof(XC_SetTiming_Info));
6284 #endif
6285 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6286 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6287 if(0)//(psXCInstPri->u32DeviceID > E_XC_DEVICE0)
6288 {
6289 printf("MApi_XC_EX_SetPanelTiming() -> Not support for device id %td\n", (ptrdiff_t)psXCInstPri->u32DeviceID);
6290 return;
6291 }
6292 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
6293 _XC_ENTRY(pInstance);
6294
6295 #ifdef ENABLE_4K2K_PATCH
6296 if(MDrv_Read2Byte(L_BK_LPLL(0x10))<= 0x20)
6297 {
6298 _XC_RETURN(pInstance);
6299 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
6300 return;
6301 }
6302 #endif
6303
6304 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6305 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6306 MS_U8 u8LPLL_Type = 0;
6307 u8LPLL_Type =(MS_U8)pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type;
6308
6309 if(pTimingInfo->u32HighAccurateInputVFreq == 0)
6310 {
6311 if(IsSrcTypeDigitalVD(gSrcInfo[eWindow].enInputSourceType))
6312 {
6313 pTimingInfo->u32HighAccurateInputVFreq = MDrv_XC_GetAccurateVFreqx1K(pInstance, eWindow);
6314 }
6315 else if(IsSrcTypeAnalog(gSrcInfo[eWindow].enInputSourceType) || IsSrcTypeHDMI(gSrcInfo[eWindow].enInputSourceType))
6316 {
6317 pTimingInfo->u32HighAccurateInputVFreq = MDrv_XC_PCMonitor_Get_VFreqx1K(pInstance, eWindow);
6318 }
6319 else
6320 {
6321 pTimingInfo->u32HighAccurateInputVFreq = pTimingInfo->u16InputVFreq * 100;
6322 }
6323 }
6324
6325 if(IsSrcTypeAV(pXCResourcePrivate->stdrvXC_MVideo.enOldInputSrc_ForScalerSetSource[eWindow])
6326 ||IsSrcTypeSV(pXCResourcePrivate->stdrvXC_MVideo.enOldInputSrc_ForScalerSetSource[eWindow])
6327 ||IsSrcTypeATV(pXCResourcePrivate->stdrvXC_MVideo.enOldInputSrc_ForScalerSetSource[eWindow])
6328 ||IsSrcTypeScart(pXCResourcePrivate->stdrvXC_MVideo.enOldInputSrc_ForScalerSetSource[eWindow]))
6329 {
6330 if(abs(pTimingInfo->u16InputVFreq - pTimingInfo->u32HighAccurateInputVFreq / 100) > ACCURATE_VFREQ_TOLERANCE_FOR_VD_SOURCE)
6331 {
6332 printf("[%s,%5d]Attention! using u16InputVFreq=%u instead of u32HighAccurateInputVFreq=%tu\n", __FUNCTION__, __LINE__, pTimingInfo->u16InputVFreq, (ptrdiff_t)pTimingInfo->u32HighAccurateInputVFreq);
6333 pTimingInfo->u32HighAccurateInputVFreq = pTimingInfo->u16InputVFreq * 100;
6334 }
6335 }
6336 else
6337 {
6338 if(abs(pTimingInfo->u16InputVFreq - pTimingInfo->u32HighAccurateInputVFreq / 100) > ACCURATE_VFREQ_TOLERANCE)
6339 {
6340 printf("[%s,%5d]Attention! using u16InputVFreq=%u instead of u32HighAccurateInputVFreq=%tu\n", __FUNCTION__, __LINE__, pTimingInfo->u16InputVFreq, (ptrdiff_t)pTimingInfo->u32HighAccurateInputVFreq);
6341 pTimingInfo->u32HighAccurateInputVFreq = pTimingInfo->u16InputVFreq * 100;
6342 }
6343 }
6344
6345 #ifdef UFO_XC_FB_LEVEL
6346 if((pXCResourcePrivate->stdrvXC_Display._bFSM_FPLL_Setting)
6347 && ((gSrcInfo[eWindow].eFBLevel == E_XC_FB_LEVEL_FB)
6348 || gSrcInfo[MAIN_WINDOW].Status2.bMVOPHSKMode)
6349 )
6350 #else
6351 if((pXCResourcePrivate->stdrvXC_Display._bFSM_FPLL_Setting) && (((!gSrcInfo[eWindow].bFBL) && (!gSrcInfo[eWindow].bR_FBL)) || gSrcInfo[MAIN_WINDOW].Status2.bMVOPHSKMode))
6352 #endif
6353 {
6354 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_IDLE_STATE; //FSM will restart, so clear FSM status to idle
6355 pXCResourcePrivate->stdrvXC_Display._bFSM_FPLL_Working = TRUE;
6356 MApi_XC_SetPanelTiming_FSM(pInstance, pTimingInfo, eWindow);
6357 if (!pXCResourcePrivate->stdrvXC_Display._bFPLL_Thresh_Mode)
6358 {
6359 if(gSrcInfo[eWindow].bEnableFPLL)
6360 {
6361 //FSM enable fpll, then enable ISR
6362 if(FALSE == MDrv_XC_InterruptIsAttached(pInstance, SC_INT_VSINT, _MApi_XC_FPLL_FSM_ISR, (void *) &pXCResourcePrivate->stdrvXC_Display.bFPLL_FSM))
6363 {
6364 MDrv_XC_InterruptAttachWithoutMutex(pInstance, SC_INT_VSINT, _MApi_XC_FPLL_FSM_ISR, (void *) &pXCResourcePrivate->stdrvXC_Display.bFPLL_FSM);
6365 }
6366 }
6367 else
6368 {
6369 //FSM disable FPLL, then disable ISR
6370 if(TRUE == MDrv_XC_InterruptIsAttached(pInstance, SC_INT_VSINT, _MApi_XC_FPLL_FSM_ISR, (void *) &pXCResourcePrivate->stdrvXC_Display.bFPLL_FSM))
6371 {
6372 MDrv_XC_InterruptDeAttachWithoutMutex(pInstance, SC_INT_VSINT, _MApi_XC_FPLL_FSM_ISR, (void *) &pXCResourcePrivate->stdrvXC_Display.bFPLL_FSM);
6373 }
6374 }
6375 }
6376 else
6377 {
6378 if(gSrcInfo[eWindow].bEnableFPLL)
6379 {
6380 pXCResourcePrivate->stdrvXC_Display._enFpllThreshMode = FPLL_THRESH_MODE_LOCKED_STATE;
6381 pXCResourcePrivate->stdrvXC_Display._u32MCNRTimer = MsOS_GetSystemTime();
6382 pXCResourcePrivate->stdrvXC_Display._bNeedReloadMCNR = TRUE;
6383 Hal_SC_SetOPWriteOff(pInstance, ENABLE);
6384
6385 //FSM enable fpll, then enable ISR
6386 if(FALSE == MDrv_XC_InterruptIsAttached(pInstance, SC_INT_VSINT, _MApi_XC_FPLL_ThreshMode_ISR, NULL))
6387 {
6388 MDrv_XC_InterruptAttachWithoutMutex(pInstance, SC_INT_VSINT, _MApi_XC_FPLL_ThreshMode_ISR, NULL);
6389 }
6390 }
6391 else
6392 {
6393 //FSM disable FPLL, then disable ISR
6394 if(TRUE == MDrv_XC_InterruptIsAttached(pInstance, SC_INT_VSINT, _MApi_XC_FPLL_ThreshMode_ISR, NULL))
6395 {
6396 MDrv_XC_InterruptDeAttachWithoutMutex(pInstance, SC_INT_VSINT, _MApi_XC_FPLL_ThreshMode_ISR, NULL);
6397 }
6398 }
6399 }
6400 }
6401 else
6402 {
6403 if(pXCResourcePrivate->stdrvXC_Display._bFSM_FPLL_Working &&
6404 (TRUE == MDrv_XC_InterruptIsAttached(pInstance, SC_INT_VSINT, _MApi_XC_FPLL_FSM_ISR, (void *) &pXCResourcePrivate->stdrvXC_Display.bFPLL_FSM)))
6405 {
6406 //State change from FSM to NON-FSM, disable ISR
6407 MDrv_XC_InterruptDeAttachWithoutMutex(pInstance, SC_INT_VSINT, _MApi_XC_FPLL_FSM_ISR, (void *) &pXCResourcePrivate->stdrvXC_Display.bFPLL_FSM);
6408 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_IDLE_STATE;
6409 }
6410 pXCResourcePrivate->stdrvXC_Display._bFSM_FPLL_Working= FALSE;
6411 MApi_XC_SetPanelTiming_NonFSM(pInstance, pTimingInfo, eWindow);
6412 }
6413 #if FRC_INSIDE
6414 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.bFRC)
6415 {
6416 MApi_XC_SetFLock(pInstance, pTimingInfo, eWindow);
6417 }
6418 else
6419 {
6420 gSrcInfo[MAIN_WINDOW].Status2.u16OP1_OutputVFreqAfterFRC = gSrcInfo[MAIN_WINDOW].Status2.u16OutputVFreqAfterFRC;
6421 }
6422
6423 #if (HW_DESIGN_4K2K_VER == 6)
6424 // For Manhattan, FSC+FRC
6425 // 1. load FSC Qmap here
6426 // 2. load FRC 3D table here
6427 // 3. send R2 cmd to FRC
6428 // 4. control FRC clk
6429 // 5. control ODCLK2, composer, and TGEN lock_src
6430 if (eWindow == MAIN_WINDOW)
6431 {
6432 MS_BOOL bUseMenuload = FALSE;
6433 if(MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED)
6434 {
6435 _MLOAD_ENTRY(pInstance);
6436 bUseMenuload = TRUE;
6437 }
6438
6439 // Maserati mode
6440 if (IsVBY1_16LANE(u8LPLL_Type))
6441 {
6442
6443 MS_BOOL bEnable_MEMC = TRUE;
6444 if((gSrcInfo[eWindow].bEnableFPLL && (gSrcInfo[MAIN_WINDOW].stCapWin.height < pTimingInfo->u16InputVTotal))
6445 #if (HW_DESIGN_HDMITX_VER == 1)//Maserati +Raptor HDMITX case , uses lockfromOP
6446 && (!(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_B & E_XC_INIT_MISC_B_HDMITX_ENABLE))
6447 #endif
6448 #ifndef MAXIM_ATV_LOCK_PHASE_PATCH
6449 && (!IsSrcTypeATV(gSrcInfo[eWindow].enInputSourceType)) //atv ip timing may be unstable under some use case,cant sync from ip
6450 #endif
6451 )
6452 {
6453 bEnable_MEMC = TRUE;
6454 }
6455 else
6456 {
6457 bEnable_MEMC = FALSE;
6458 }
6459
6460 if ((pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFSCEnabled) &&(psXCInstPri->u32DeviceID != 1))
6461 {
6462 // case 5: FSC + FRC
6463 MHal_FRC_Set_FSC_DE_Selection(pInstance, E_FRC_FSC_SOURCE_MODE_FDE);
6464
6465 #if 0
6466 if(MDrv_XC_Is_DSForceIndexEnabled(pInstance, MAIN_WINDOW)||MDrv_XC_GetDynamicScalingStatus(pInstance))
6467 {
6468 MHal_FRC_Set_STGEN_ODCLK(pInstance, E_FRC_STGEN_ODCLK_2, bUseMenuload);
6469 }
6470 #endif
6471 if (MHal_FRC_IsFHDToFSC(pInstance, eWindow))
6472 {
6473 // FHD case, ODCLK2 as ODCLK/4
6474 MHal_FRC_Set_STGEN_ODCLK(pInstance, E_FRC_STGEN_ODCLK_4, bUseMenuload);
6475 }
6476 else
6477 {
6478 // 4K 50/60 case, ODLCK2 as ODCLK
6479 MHal_FRC_Set_STGEN_ODCLK(pInstance, E_FRC_STGEN_ODCLK_1, bUseMenuload);
6480 }
6481 //MHal_FRC_Set_Pipe_Delay_Reset(pInstance, ENABLE, bUseMenuload);
6482
6483 // For FSC V12L en control
6484 MHal_FRC_AdjustGOPPosition(pInstance);
6485
6486 if (MHal_FRC_IsFHDToFSC(pInstance, eWindow))
6487 {
6488 MHal_FRC_Set_Pipe_Delay_Value(pInstance, FRC_PIPE_DELAY_HCNT_FSC_FHD, FRC_PIPE_DELAY_VCNT_FSC_FHD);
6489 }
6490 else
6491 {
6492 MHal_FRC_Set_Pipe_Delay_Value(pInstance, FRC_PIPE_DELAY_HCNT_FSC_4K_120Hz, FRC_PIPE_DELAY_VCNT_FSC_4K_120Hz);
6493 }
6494
6495 MHal_FRC_ByPass_Enable(pInstance, FALSE);
6496 MHal_FRC_Set_Composer_User_Mode(pInstance, E_FRC_COMPOSER_SOURCE_MODE_FSC, bUseMenuload);
6497 MHal_FRC_TGEN_Enable_Lock_Source(pInstance, ENABLE, E_FRC_TGEN_LOCK_SOURCE_MODE_FROM_TGEN, bUseMenuload);
6498
6499 }
6500 else
6501 {
6502 // case 4: no FSC + FRC
6503 //MHal_FRC_Set_Pipe_Delay_Reset(pInstance, DISABLE, bUseMenuload);
6504
6505 MHal_FRC_ByPass_Enable(pInstance, FALSE); // enable FRC
6506 MHal_FRC_Set_STGEN_ODCLK(pInstance, E_FRC_STGEN_ODCLK_1, bUseMenuload);
6507
6508 MHal_FRC_Set_Composer_User_Mode(pInstance, E_FRC_COMPOSER_SOURCE_MODE_VIP, bUseMenuload);
6509 MHal_FRC_Set_FSC_DE_Selection(pInstance, E_FRC_FSC_SOURCE_MODE_MDE);
6510 MHal_FRC_TGEN_Enable_Lock_Source(pInstance, DISABLE, E_FRC_TGEN_LOCK_SOURCE_MODE_FROM_TGEN, bUseMenuload);
6511
6512 }
6513 if(bEnable_MEMC)
6514 {
6515 Hal_XC_FRC_R2_Enable_MEMC(pInstance, pXCResourcePrivate->stdrvXC_MVideo_Context.g_u16MEMCLevel);
6516 }
6517 else
6518 {
6519 Hal_XC_FRC_R2_Enable_MEMC(pInstance, MEMC_LEVEL_OFF);
6520 }
6521 }
6522 else // Manhattan mode
6523 if ((pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFSCEnabled) &&(psXCInstPri->u32DeviceID != 1))
6524 {
6525 MS_BOOL bLockFromIP = FALSE;
6526
6527 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFRCEnabled &&
6528 ((gSrcInfo[eWindow].bEnableFPLL
6529 #if FRC_INSIDE
6530 || (IS_OUTPUT_4K1K_120HZ_PANEL() && //4k1k@120 3d stgen lock ip case
6531 (MDrv_XC_Get_3D_Output_Mode(pInstance) != E_XC_3D_OUTPUT_MODE_NONE) &&
6532 pXCResourcePrivate->stdrvXC_Display._bForceFreerun)
6533 #endif
6534 ) && (gSrcInfo[MAIN_WINDOW].stCapWin.height < pTimingInfo->u16InputVTotal))
6535 #if (HW_DESIGN_HDMITX_VER == 1)//Maserati +Raptor HDMITX case , uses lockfromOP
6536 && (!(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_B & E_XC_INIT_MISC_B_HDMITX_ENABLE))
6537 #endif
6538 #ifndef MAXIM_ATV_LOCK_PHASE_PATCH
6539 && (!IsSrcTypeATV(gSrcInfo[eWindow].enInputSourceType)) //atv ip timing may be unstable under some use case,cant sync from ip
6540 #endif
6541 )
6542 {
6543 bLockFromIP = TRUE;
6544 }
6545
6546 // Lock from OP and input Vfreq != output Vfreq, or input Vfeq > Output Vfreq, means it's not 1:1 case, can not enable UC.
6547 if((!bLockFromIP &&
6548 (abs(gSrcInfo[MAIN_WINDOW].u16InputVFreq - pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq) > VFREQ_DIFF_TOLERANCE))
6549 || ((gSrcInfo[MAIN_WINDOW].u16InputVFreq - pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq) > VFREQ_DIFF_TOLERANCE))
6550 {
6551 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK2A_02_L, 0x0 ,BIT(15));//disable UC feature
6552 }
6553
6554 MHal_FRC_Set_FSC_DE_Selection(pInstance, E_FRC_FSC_SOURCE_MODE_FDE);
6555
6556 #if 0
6557 if(MDrv_XC_Is_DSForceIndexEnabled(pInstance, MAIN_WINDOW)||MDrv_XC_GetDynamicScalingStatus(pInstance))
6558 {
6559 MHal_FRC_Set_STGEN_ODCLK(pInstance, E_FRC_STGEN_ODCLK_2, bUseMenuload);
6560 }
6561 #endif
6562 if (MHal_FRC_IsFHDToFSC(pInstance, eWindow))
6563 {
6564 // FHD case, ODCLK2 as ODCLK/4
6565 MHal_FRC_Set_STGEN_ODCLK(pInstance, E_FRC_STGEN_ODCLK_4, bUseMenuload);
6566 }
6567 else if ((gSrcInfo[eWindow].u16InputVFreq < 330) && bLockFromIP
6568 && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq > 450))
6569 {
6570 // 4K 24/25/30 + output 50/60 case, ODCLK2 as ODCLK/2 for power saving
6571 MHal_FRC_Set_STGEN_ODCLK(pInstance, E_FRC_STGEN_ODCLK_2, bUseMenuload);
6572 }
6573 else
6574 {
6575 // 4K 50/60 case, ODLCK2 as ODCLK
6576 //For Raptor output 576p/480p case (Vby1 1 lane), xc odclk divided by N, so the stgen has to follow the same setting.
6577 if( (u8LPLL_Type == E_XC_PNL_LPLL_VBY1_8BIT_1LANE)||(u8LPLL_Type == E_XC_PNL_LPLL_VBY1_10BIT_1LANE))
6578 MHal_FRC_Set_STGEN_ODCLK(pInstance, E_FRC_STGEN_ODCLK_N, bUseMenuload);
6579 else
6580 MHal_FRC_Set_STGEN_ODCLK(pInstance, E_FRC_STGEN_ODCLK_1, bUseMenuload);
6581 }
6582 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFRCEnabled)
6583 {
6584 // case3: FSC+FRC
6585 //MHal_FRC_Set_Pipe_Delay_Reset(pInstance, ENABLE, bUseMenuload);
6586 MHal_FRC_AdjustGOPPosition(pInstance);
6587
6588 #ifdef SUPPORT_FHD_MEMC
6589 if (IS_OUTPUT_FHD(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height))
6590 {
6591 MHal_FRC_Set_Pipe_Delay_Value(pInstance, FRC_PIPE_DELAY_HCNT_FRC_FHD_OUT, FRC_PIPE_DELAY_VCNT_FRC_FHD_OUT);
6592 }
6593 else
6594 #endif
6595 {
6596 #ifdef HW_FRC_PIPE_DELAY_DTV_4K2K_LIMITATION
6597 if(IsSrcTypeDTV(gSrcInfo[eWindow].enInputSourceType)
6598 && !(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_B & E_XC_INIT_MISC_B_HDMITX_ENABLE)
6599 )
6600 {
6601 MHal_FRC_Set_Pipe_Delay_Value(pInstance, FRC_PIPE_DELAY_HCNT_FRC_DTV,FRC_PIPE_DELAY_VCNT_FRC_DTV);
6602 }
6603 else
6604 #endif
6605 {
6606 #if (HW_DESIGN_HDMITX_VER == 1) //Maserati case, fix V pipedelay to 0x1D
6607 MHal_FRC_Set_Pipe_Delay_Value(pInstance, FRC_PIPE_DELAY_HCNT_FSC_FHD, FRC_PIPE_DELAY_VCNT_FSC_FHD);
6608 #else
6609 MHal_FRC_Set_Pipe_Delay_Value(pInstance, FRC_PIPE_DELAY_HCNT_FRC, FRC_PIPE_DELAY_VCNT_FRC);
6610 #endif
6611 }
6612 }
6613
6614 MHal_FRC_ByPass_Enable(pInstance, FALSE);
6615 MHal_FRC_Set_Composer_User_Mode(pInstance, E_FRC_COMPOSER_SOURCE_MODE_FRC, bUseMenuload);
6616
6617 // SW patch for LPLL not locked case:
6618 // at FRC enable case, only FPLL locked can set lock from IP
6619 if (bLockFromIP)
6620 {
6621 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_B & E_XC_INIT_MISC_B_HDMITX_FREERUN_UCNR_ENABLE)
6622 {
6623 pXCResourcePrivate->stdrvXC_MVideo_Context.g_u16MEMCLevel = MEMC_LEVEL_OFF;
6624 }
6625 MHal_FRC_TGEN_Enable_Lock_Source(pInstance, ENABLE, E_FRC_TGEN_LOCK_SOURCE_MODE_FROM_IP, bUseMenuload);
6626 MS_U16 u16MEMCLevel = 0;
6627 #if FRC_INSIDE
6628 /*force free run should off memc*/
6629 if(pXCResourcePrivate->stdrvXC_Display._bForceFreerun)
6630 {
6631 printf("[%s,%5d],force free run should disable memc \n",__FUNCTION__,__LINE__);
6632 u16MEMCLevel = MEMC_LEVEL_OFF;
6633 }
6634 else
6635 #endif
6636 {
6637 u16MEMCLevel = pXCResourcePrivate->stdrvXC_MVideo_Context.g_u16MEMCLevel;
6638 }
6639
6640 if(gSrcInfo[MAIN_WINDOW].bUseYUVSpace)
6641 {
6642 Hal_XC_FRC_R2_Enable_MEMC(pInstance, u16MEMCLevel);
6643 }
6644 else
6645 {
6646 Hal_XC_FRC_R2_Enable_MEMC(pInstance, MEMC_LEVEL_BYPASS);
6647 }
6648 }
6649 else
6650 {
6651 /*when scaler free run,stgen cant lock source for clk is not enough under 4k1k@120hz,4k0.5k@240 3d*/
6652 if((IS_OUTPUT_4K1K_120HZ_PANEL()|| IS_OUTPUT_4K0_5K_240HZ_PANEL())
6653 && (MDrv_XC_Get_3D_Output_Mode(pInstance) != E_XC_3D_OUTPUT_MODE_NONE))
6654 {
6655 MHal_FRC_TGEN_Enable_LockMode(pInstance, DISABLE);
6656 }
6657 else
6658 {
6659 MHal_FRC_TGEN_Enable_Lock_Source(pInstance, ENABLE, E_FRC_TGEN_LOCK_SOURCE_MODE_FROM_TGEN, bUseMenuload);
6660 }
6661 if(gSrcInfo[MAIN_WINDOW].bUseYUVSpace)
6662 {
6663 Hal_XC_FRC_R2_Enable_MEMC(pInstance, MEMC_LEVEL_OFF);
6664 }
6665 else
6666 {
6667 Hal_XC_FRC_R2_Enable_MEMC(pInstance, MEMC_LEVEL_BYPASS);
6668 }
6669 }
6670 }
6671 else
6672 {
6673 // case2: only FSC
6674 //MHal_FRC_Set_Pipe_Delay_Reset(pInstance, ENABLE, bUseMenuload);
6675 MHal_FRC_AdjustGOPPosition(pInstance);
6676
6677 // For RAPTORS case, keep pipe delay value UNCHANGE to avoid video&osd shift.
6678 // Instead, adjust the position of BK68 tgen vsync start/end, mde v start/end, fde v start/end
6679 // Raptor case identified by MISC E_XC_INIT_MISC_B_HDMITX_ENABLE and set by Upper layer.
6680 if( (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_B & E_XC_INIT_MISC_B_HDMITX_ENABLE)
6681 &&(pXCResourcePrivate->stdrvXC_MVideo.gu16HPixelShiftRange == 0)
6682 &&(pXCResourcePrivate->stdrvXC_MVideo.gu16VPixelShiftRange == 0)) //Check if PIXEL FEATURE is NOT enable.
6683 {
6684 MHal_FRC_Set_Pipe_Delay_Value(pInstance, FRC_PIPE_DELAY_HCNT_FSC_FHD, FRC_PIPE_DELAY_VCNT_FSC_FHD);
6685 }
6686 else
6687 {
6688 if (MHal_FRC_IsFHDToFSC(pInstance, eWindow))
6689 {
6690 MHal_FRC_Set_Pipe_Delay_Value(pInstance, FRC_PIPE_DELAY_HCNT_FSC_FHD, FRC_PIPE_DELAY_VCNT_FSC_FHD);
6691 }
6692 else
6693 {
6694 MHal_FRC_Set_Pipe_Delay_Value(pInstance, FRC_PIPE_DELAY_HCNT_FSC_4K, FRC_PIPE_DELAY_VCNT_FSC_4K);
6695 }
6696 }
6697
6698 MHal_FRC_ByPass_Enable(pInstance, TRUE);
6699 MHal_FRC_Set_Composer_User_Mode(pInstance, E_FRC_COMPOSER_SOURCE_MODE_FSC, bUseMenuload);
6700 MHal_FRC_TGEN_Enable_Lock_Source(pInstance, ENABLE, E_FRC_TGEN_LOCK_SOURCE_MODE_FROM_TGEN, bUseMenuload);
6701 }
6702 }
6703 else
6704 {
6705
6706
6707 // case1: no FSC+ no FRC
6708 //MHal_FRC_Set_Pipe_Delay_Reset(pInstance, DISABLE, bUseMenuload);
6709 MHal_FRC_AdjustGOPPosition(pInstance);
6710
6711 MHal_FRC_ByPass_Enable(pInstance, TRUE); // disable FRC
6712 MHal_FRC_Set_STGEN_ODCLK(pInstance, E_FRC_STGEN_ODCLK_1, bUseMenuload);
6713
6714 MHal_FRC_Set_Composer_User_Mode(pInstance, E_FRC_COMPOSER_SOURCE_MODE_VIP, bUseMenuload);
6715 MHal_FRC_Set_FSC_DE_Selection(pInstance, E_FRC_FSC_SOURCE_MODE_MDE);
6716 MHal_FRC_TGEN_Enable_Lock_Source(pInstance, DISABLE, E_FRC_TGEN_LOCK_SOURCE_MODE_FROM_TGEN, bUseMenuload);
6717 }
6718
6719 if(MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED)
6720 {
6721 MDrv_XC_MLoad_Fire(pInstance, TRUE);
6722 _MLOAD_RETURN(pInstance);
6723 }
6724
6725 if(psXCInstPri->u32DeviceID != 1)
6726 {
6727 // Maserati mode
6728 if (IsVBY1_16LANE(u8LPLL_Type))
6729 {
6730 MHal_FRC_Set_Mload_Trig_Mode(pInstance, E_FRC_MLOAD_TRIG_MODE_FROM_OP1); // menuload trig always form stgen
6731 }
6732 else // Manhattan mode
6733 {
6734 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFRCEnabled)
6735 {
6736 MHal_FRC_Set_Mload_Trig_Mode(pInstance, E_FRC_MLOAD_TRIG_MODE_FROM_OP2); // with FRC case, menuload trig form tgen
6737 }
6738 else
6739 {
6740 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFSCEnabled)
6741 {
6742 MHal_FRC_Set_Mload_Trig_Mode(pInstance, E_FRC_MLOAD_TRIG_MODE_FROM_OP1); // no FRC case, menuload trig form stgen
6743 }
6744 else
6745 {
6746 MHal_FRC_Set_Mload_Trig_Mode(pInstance, E_FRC_MLOAD_TRIG_MODE_FROM_OP2); // with FRC case, menuload trig form tgen
6747 }
6748 }
6749 }
6750 }
6751 }
6752 #endif
6753 #else
6754 gSrcInfo[MAIN_WINDOW].Status2.u16OP1_OutputVFreqAfterFRC = gSrcInfo[MAIN_WINDOW].Status2.u16OutputVFreqAfterFRC;
6755 #endif
6756
6757 _XC_RETURN(pInstance);
6758 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
6759 }
6760
MApi_XC_SetPanelTiming(XC_SetTiming_Info * pTimingInfo,SCALER_WIN eWindow)6761 void MApi_XC_SetPanelTiming(XC_SetTiming_Info *pTimingInfo, SCALER_WIN eWindow)
6762 {
6763 if (pu32XCInst == NULL)
6764 {
6765 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
6766 return;
6767 }
6768
6769 stXC_SET_PANEL_TIMING XCArgs;
6770 XCArgs.pTimingInfo = pTimingInfo;
6771 XCArgs.eWindow = eWindow;
6772
6773 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_PANEL_TIMING, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
6774 {
6775 printf("Obtain XC engine fail\n");
6776 return;
6777 }
6778 else
6779 {
6780 return;
6781 }
6782 }
6783
MDrv_XC_SetFrameColor(void * pInstance,MS_U32 u32aRGB)6784 void MDrv_XC_SetFrameColor(void *pInstance, MS_U32 u32aRGB )
6785 {
6786 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6787 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6788 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6789 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6790 pXCResourcePrivate->stdrvXC_MVideo_Context.g_u32FrameColor_Suspend = u32aRGB;
6791 Hal_XC_SetFrameColor(pInstance, u32aRGB);
6792 }
6793
6794 //-------------------------------------------------------------------------------------------------
6795 /// set free run(Disable input chanel) color
6796 /// @param u32aRGB
6797 /// - 0:Black
6798 /// - 1:White
6799 /// - 2:Blue
6800 //-------------------------------------------------------------------------------------------------
MApi_XC_SetFrameColor_U2(void * pInstance,MS_U32 u32aRGB)6801 void MApi_XC_SetFrameColor_U2 ( void* pInstance, MS_U32 u32aRGB )
6802 {
6803 //MS_U8 u8Bank;
6804 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6805 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6806 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
6807
6808 _XC_ENTRY(pInstance);
6809 //u8Bank = MDrv_ReadByte(BK_SELECT_00);
6810 //MDrv_WriteByte(BK_SELECT_00, REG_BANK_VOP);
6811 //MDrv_WriteByte(H_BK_VOP(0x19), (MS_U8) (u32aRGB >> 16)); ///< R
6812 //MDrv_WriteByte(L_BK_VOP(0x1A), (MS_U8) (u32aRGB >> 8)); ///< G
6813 //MDrv_WriteByte(H_BK_VOP(0x1A), (MS_U8) u32aRGB); ///< B
6814 //SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_19_L, (u32aRGB >> 8),0xFF00); ///< R
6815 //SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_1A_L, (u32aRGB >> 8),0x00FF); ///< G
6816 //SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_1A_L, (u32aRGB << 8),0xFF00); ///< B
6817 //MDrv_WriteByte(BK_SELECT_00, u8Bank);
6818 MDrv_XC_SetFrameColor(pInstance, u32aRGB);
6819 _XC_RETURN(pInstance);
6820 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
6821
6822 }
6823
MApi_XC_SetFrameColor(MS_U32 u32aRGB)6824 void MApi_XC_SetFrameColor ( MS_U32 u32aRGB )
6825 {
6826 if (pu32XCInst == NULL)
6827 {
6828 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
6829 return;
6830 }
6831
6832 stXC_SET_FRAME_COLOR XCArgs;
6833 XCArgs.u32aRGB = u32aRGB;
6834
6835 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_FRAME_COLOR, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
6836 {
6837 printf("Obtain XC engine fail\n");
6838 return;
6839 }
6840 else
6841 {
6842 return;
6843 }
6844 }
6845
6846 /******************************************************************************/
6847 ///set free run display window size
6848 /******************************************************************************/
MDrv_SC_set_freerun_window(void * pInstance)6849 void MDrv_SC_set_freerun_window (void *pInstance)
6850 {
6851 //MS_U8 u8Bank;
6852
6853 //u8Bank = MDrv_ReadByte(BK_SELECT_00);
6854 //MDrv_WriteByte(BK_SELECT_00, REG_BANK_VOP);
6855
6856 /*MDrv_Write2Byte(L_BK_VOP(0x08), g_XC_InitData.stPanelInfo.u16HStart); // Image H start
6857 MDrv_Write2Byte(L_BK_VOP(0x09), g_XC_InitData.stPanelInfo.u16HStart + g_XC_InitData.stPanelInfo.u16Width - 1); // Image H end
6858 MDrv_Write2Byte(L_BK_VOP(0x0A), g_XC_InitData.stPanelInfo.u16VStart + g_XC_InitData.stPanelInfo.u16Height - 1); // Image V end
6859 MDrv_Write2Byte(L_BK_VOP(0x0B), g_XC_InitData.stPanelInfo.u16VStart + g_XC_InitData.stPanelInfo.u16Height - 1); // DE V end*/
6860
6861 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6862 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6863
6864 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6865 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6866 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_08_L, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HStart); // Image H start
6867 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_09_L, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HStart + pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width - 1); // Image H end
6868 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0A_L, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart + pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height - 1); // Image V end
6869 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0B_L, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart + pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height - 1); // DE V end*/
6870
6871 //MDrv_WriteByte(BK_SELECT_00, u8Bank);
6872 }
6873
6874 //-----------------------------------------------------------------------------
6875 // frame lock
6876 //-----------------------------------------------------------------------------
MDrv_Scaler_SetFrameLock(void * pInstance,MS_BOOL bSignal)6877 static void MDrv_Scaler_SetFrameLock(void *pInstance, MS_BOOL bSignal)
6878 {
6879 //MS_U8 u8Bank;
6880 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6881 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6882 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6883 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6884 MS_U16 u16OutputVtotal = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVTotal;
6885
6886 MS_BOOL bFramelockEnable = DISABLE;
6887 MS_BOOL bEnFreerunOutput = DISABLE;
6888 MS_BOOL bUseMainFB = TRUE;
6889
6890 MS_BOOL bSetFPLL = DISABLE;
6891
6892 #ifdef UFO_XC_FB_LEVEL
6893 if((gSrcInfo[MAIN_WINDOW].eFBLevel == E_XC_FB_LEVEL_FBL) || (gSrcInfo[MAIN_WINDOW].eFBLevel == E_XC_FB_LEVEL_RFBL_DI))
6894 {
6895 bUseMainFB = FALSE;//FIXME
6896 }
6897 #else
6898 bUseMainFB = !gSrcInfo[MAIN_WINDOW].bFBL;
6899 #endif
6900
6901 //u8Bank = MDrv_ReadByte(BK_SELECT_00);
6902
6903 if (bSignal == FALSE) // No Signal (Pure Freerun Mode)
6904 {
6905 u16OutputVtotal -= 1;
6906 bEnFreerunOutput = ENABLE;
6907 }
6908 else // Have Signal
6909 {
6910 if (bUseMainFB)
6911 {
6912 bSetFPLL = ENABLE;
6913 u16OutputVtotal -= 1;
6914 bEnFreerunOutput = ENABLE;
6915
6916 bFramelockEnable = ENABLE;
6917 }
6918 else
6919 {
6920 bSetFPLL = DISABLE;
6921 u16OutputVtotal -= 1;
6922 bEnFreerunOutput = ENABLE;
6923
6924 bFramelockEnable = DISABLE;
6925 }
6926 }
6927
6928 /* set FPLL */
6929 MDrv_SC_set_fpll(pInstance, bSetFPLL, DISABLE, 0);
6930 #if FRC_INSIDE
6931 #if (HW_DESIGN_4K2K_VER != 6) // For Manhattan, only 1 LPLL
6932 MDrv_SC_set_fpll(pInstance, bSetFPLL, DISABLE, 1);
6933 #endif
6934 #endif
6935
6936 /* enable output free-run */
6937 //MDrv_WriteByte(BK_SELECT_00, REG_BANK_VOP);
6938 //MDrv_WriteByte(H_BK_VOP(0x1C), bEnFreerunOutput);
6939 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_1C_L, bEnFreerunOutput ? BIT(8): 0,BIT(8));
6940 /* Enable/Disable FrameLock */
6941 //MDrv_WriteByte(BK_SELECT_00, REG_BANK_IP1F2);
6942 //MDrv_WriteRegBit(H_BK_IP1F2(0x03), bFramelockEnable, BIT(7));
6943 if(bFramelockEnable
6944 #if FRC_INSIDE
6945 || (Hal_XC_Get_Stgen_Lock_Ip_status(pInstance) &&
6946 pXCResourcePrivate->stdrvXC_Display._bForceFreerun)
6947 #endif
6948 )//stgen lock ip should enable this bit under force free run
6949 {
6950 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_03_L, BIT(15),BIT(15));
6951 }
6952 else
6953 {
6954 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_03_L, 0,BIT(15));
6955 }
6956
6957
6958 //MDrv_WriteByte(BK_SELECT_00, u8Bank);
6959 }
6960
6961 //-------------------------------------------------------------------------------------------------
6962 /// set free run display window timing
6963 //-------------------------------------------------------------------------------------------------
MDrv_XC_SetFreeRunTiming(void * pInstance)6964 void MDrv_XC_SetFreeRunTiming (void* pInstance)
6965 {
6966 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6967 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6968 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6969 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6970 if(pXCResourcePrivate->stdrvXC_Display._bFSM_FPLL_Working &&
6971 (TRUE == MDrv_XC_InterruptIsAttached(pInstance, SC_INT_VSINT, _MApi_XC_FPLL_FSM_ISR, (void *) &pXCResourcePrivate->stdrvXC_Display.bFPLL_FSM)))
6972 {
6973 //FSM, disable FPLL, so disable ISR
6974 MDrv_XC_InterruptDeAttachWithoutMutex(pInstance, SC_INT_VSINT, _MApi_XC_FPLL_FSM_ISR, (void *) &pXCResourcePrivate->stdrvXC_Display.bFPLL_FSM);
6975 pXCResourcePrivate->stdrvXC_Display._enFpllFsm = FPLL_IDLE_STATE;
6976 }
6977
6978 MDrv_WriteByte(H_BK_LPLL(0x0C), 0x00); //clear FRC before set freerun (fps_in:fps_out = 1:1)
6979 MDrv_WriteByte(L_BK_LPLL(0x0E), 0x00);
6980
6981 #if VERIFY_DISPLAY_FPGA //value setting
6982 MDrv_SC_set_output_dclk(pInstance, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HTotal,
6983 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VTotal,
6984 120, eWindow);
6985 #endif
6986 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "SetFreeRunTiming: Disable FPLL and Clear FSM to Idle state\n")
6987 gSrcInfo[MAIN_WINDOW].bEnableFPLL = FALSE;
6988 gSrcInfo[SUB_WINDOW].bEnableFPLL = FALSE;
6989 MDrv_Scaler_SetFrameLock(pInstance, FALSE);
6990
6991 pXCResourcePrivate->stdrvXC_Display.u32OutputPhaseStable = FALSE;
6992 pXCResourcePrivate->stdrvXC_Display.u32OutputPRDLock = FALSE;
6993 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
6994 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.bFRC)
6995 {
6996 Hal_XC_FRC_R2_Set_FPLL_Lockdone(pInstance, FALSE);
6997 }
6998 #endif
6999
7000 switch (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type)
7001 {
7002 case E_XC_PNL_LPLL_DAC_I:
7003 case E_XC_PNL_LPLL_DAC_P:
7004 //MDrv_WriteByteMask(H_BK_VOP(0x10), BIT(7)|BIT(6), 0xFF); // set output vsync manually
7005 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_10_L, BIT(15)|BIT(14), 0xFF00); // set output vsync manually
7006 break;
7007 default:
7008 //MDrv_WriteByteMask(H_BK_VOP(0x10), BIT(6), 0x7F); // set output sync ctl for Freerun
7009 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_10_L, BIT(14), 0x7700); // set output sync ctl for Freerun, bit 11 per RD's suggestion take it to be the default
7010 }
7011
7012 #if ((HW_DESIGN_4K2K_VER == 6) && (FRC_INSIDE))
7013 if ((pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFSCEnabled) &&(psXCInstPri->u32DeviceID != 1))
7014 {
7015 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_bFRCEnabled)
7016 {
7017 if (MHal_FRC_IsFHDToFSC(pInstance, MAIN_WINDOW))
7018 {
7019 // FHD case, ODCLK2 as ODCLK/4
7020 MHal_FRC_Set_STGEN_ODCLK(pInstance, E_FRC_STGEN_ODCLK_4, FALSE);
7021 }
7022 else
7023 {
7024 // 4K 50/60 case, ODLCK2 as ODCLK
7025 MHal_FRC_Set_STGEN_ODCLK(pInstance, E_FRC_STGEN_ODCLK_1, FALSE);
7026 }
7027 /*when scaler free run,stgen cant lock source for clk is not enough under 4k1k@120hz,4k0.5k@240 3d*/
7028 if((IS_OUTPUT_4K1K_120HZ_PANEL() || IS_OUTPUT_4K0_5K_240HZ_PANEL())
7029 && (MDrv_XC_Get_3D_Output_Mode(pInstance) != E_XC_3D_OUTPUT_MODE_NONE))
7030 {
7031 MHal_FRC_TGEN_Enable_LockMode(pInstance, DISABLE);
7032 }
7033 else
7034 {
7035 MHal_FRC_TGEN_Enable_Lock_Source(pInstance, ENABLE, E_FRC_TGEN_LOCK_SOURCE_MODE_FROM_TGEN, FALSE);
7036 }
7037 }
7038 }
7039 #endif
7040
7041 //MDrv_WriteByte(BK_SELECT_00, u8Bank);
7042 }
7043
7044 //-------------------------------------------------------------------------------------------------
7045 /// set free run display window timing
7046 //-------------------------------------------------------------------------------------------------
MApi_XC_SetFreeRunTiming_U2(void * pInstance)7047 void MApi_XC_SetFreeRunTiming_U2 (void* pInstance)
7048 {
7049 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7050 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7051 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
7052 _XC_ENTRY(pInstance);
7053 MDrv_XC_SetFreeRunTiming(pInstance);
7054 _XC_RETURN(pInstance);
7055 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
7056 }
7057
MApi_XC_SetFreeRunTiming(void)7058 void MApi_XC_SetFreeRunTiming (void)
7059 {
7060 if (pu32XCInst == NULL)
7061 {
7062 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
7063 return;
7064 }
7065
7066 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_FREERUN_TIMING, NULL) != UTOPIA_STATUS_SUCCESS)
7067 {
7068 printf("Obtain XC engine fail\n");
7069 return;
7070 }
7071 else
7072 {
7073 return;
7074 }
7075 }
7076
7077 //-------------------------------------------------------------------------------------------------
7078 /// Setup Gamma function ON/OFF
7079 /// @param bEnable \b IN: Enable or Disable
7080 //-------------------------------------------------------------------------------------------------
MApi_XC_SetGammaOnOff_U2(void * pInstance,MS_BOOL bEnable)7081 void MApi_XC_SetGammaOnOff_U2 ( void* pInstance, MS_BOOL bEnable )
7082 {
7083 //MS_U8 u8Bank;
7084 _XC_ENTRY(pInstance);
7085 /*u8Bank = MDrv_ReadByte(BK_SELECT_00);
7086 MDrv_WriteByte(BK_SELECT_00, REG_BANK_VOP);
7087 MDrv_WriteRegBit(L_BK_VOP(0x50), bEnable, BIT(0));
7088 MDrv_WriteByte(BK_SELECT_00, u8Bank);*/
7089 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7090 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7091 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_50_L, bEnable, BIT(0));
7092 _XC_RETURN(pInstance);
7093 }
7094
MApi_XC_SetGammaOnOff(MS_BOOL bEnable)7095 void MApi_XC_SetGammaOnOff ( MS_BOOL bEnable )
7096 {
7097 if (pu32XCInst == NULL)
7098 {
7099 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
7100 return;
7101 }
7102
7103 stXC_SET_GAMMA_ONOFF XCArgs;
7104 XCArgs.bEnable = bEnable;
7105
7106 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_GAMMA_ONOFF, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
7107 {
7108 printf("Obtain XC engine fail\n");
7109 return;
7110 }
7111 else
7112 {
7113 return;
7114 }
7115 }
7116
MDrv_SC_set_output_dclk(void * pInstance,MS_U16 u16Htt,MS_U16 u16Vtt,MS_U16 u16VFreq,MS_U32 u32HighAccurateVFreq,SCALER_WIN eWindow)7117 void MDrv_SC_set_output_dclk(void *pInstance, MS_U16 u16Htt, MS_U16 u16Vtt, MS_U16 u16VFreq, MS_U32 u32HighAccurateVFreq, SCALER_WIN eWindow)
7118 {
7119 MS_U32 u32UpBound, u32LowBound, u32Steps = SLOWLY_MOVE_STEPS, u32DelayMs = 0; //delaytime=0 means wait 2vsync as the old logic
7120 XC_PANEL_INFO_EX *pPanelInfoEx;
7121 MS_U32 u32PllSet = 0, u32HighAccuratePllSet = 0;
7122 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7123 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7124 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7125 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7126 MS_U64 u64DClk = (MS_U64)u16Htt * u16Vtt * u16VFreq;
7127 MS_U64 u64HighAccurateDClk = 0;
7128 MS_U16 u16Htt_out = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HTotal;
7129 MS_U16 u16Vtt_out = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VTotal;
7130 MS_U32 u32DefaultDClk = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultHTotal
7131 * pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVTotal
7132 * pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq;
7133 MS_U32 u32AdjHighAccurateVFreq = u32HighAccurateVFreq;
7134
7135 if (u32HighAccurateVFreq == 0)
7136 {
7137 u32AdjHighAccurateVFreq = (MS_U32)u16VFreq * 100;
7138 }
7139
7140 #if (HW_DESIGN_HDMITX_VER == 2 || HW_DESIGN_HDMITX_VER == 1)
7141 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_B & E_XC_INIT_MISC_B_HDMITX_ENABLE)
7142 {
7143 if(u32AdjHighAccurateVFreq < 61500 && u32AdjHighAccurateVFreq > 59500)
7144 u32AdjHighAccurateVFreq = 60000;
7145 else if(u32AdjHighAccurateVFreq < 50500 && u32AdjHighAccurateVFreq > 49500)
7146 u32AdjHighAccurateVFreq = 50000;
7147 else if(u32AdjHighAccurateVFreq < 30500 && u32AdjHighAccurateVFreq > 29500)
7148 u32AdjHighAccurateVFreq = 30000;
7149 else if(u32AdjHighAccurateVFreq < 24500 && u32AdjHighAccurateVFreq > 23500)
7150 u32AdjHighAccurateVFreq = 24000;
7151 else if(u32AdjHighAccurateVFreq < 25500 && u32AdjHighAccurateVFreq > 24500)
7152 u32AdjHighAccurateVFreq = 25000;
7153 }
7154 #endif
7155
7156 u32DefaultDClk = u16Htt_out * u16Vtt_out * pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq;
7157 pPanelInfoEx = NULL;
7158 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "**** SetOutputDclk u16VFreq=%u ***\n", u16VFreq);
7159 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "**** SetOutputDclk u32AdjHighAccurateVFreq=%tu ***\n", (ptrdiff_t)u32AdjHighAccurateVFreq);
7160 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "DefaultPanelInfo: MinSET = 0x%tx, MaxSET = 0x%tx\n",
7161 (ptrdiff_t)pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u32MinSET,
7162 (ptrdiff_t)pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u32MaxSET);
7163
7164 MS_U32 u32Factor = MHal_SC_Get_LpllSet_Factor(pInstance, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u8LPLL_Mode,
7165 (MS_U8)pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type,u32DefaultDClk);
7166
7167 MS_U32 u32LPLLSet_Div = 1;
7168
7169 #if ((HW_DESIGN_4K2K_VER == 4)||(HW_DESIGN_4K2K_VER == 6))
7170 u32LPLLSet_Div = MHal_SC_Get_LpllSet_Div(pInstance, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u8LPLL_Mode,
7171 (MS_U8)pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type,u32DefaultDClk);
7172 #endif
7173
7174 if (u32LPLLSet_Div == 0)
7175 u32LPLLSet_Div = 1; // To avoid /0 case
7176
7177 u32UpBound = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u32MaxSET * u32Factor / u32LPLLSet_Div;
7178 u32LowBound = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u32MinSET * u32Factor / u32LPLLSet_Div;
7179
7180
7181 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "g_XC_InitData.stPanelInfo.eLPLL_Type.eLPLL_Type=%u, g_XC_InitData.stPanelInfo.eLPLL_Type.eLPLL_Mode=%u\n",
7182 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u8LPLL_Mode)
7183
7184 if((pXCResourcePrivate->stdrvXC_Display._bForceFreerun == FALSE)
7185 && _MDrv_XC_GetExPanelInfo(pInstance, &pPanelInfoEx, u16VFreq) && (pPanelInfoEx != NULL))
7186 {
7187 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "PanelInfoEx assigned\n")
7188 if(pPanelInfoEx->bDClkValid)
7189 {
7190 u64DClk = (MS_U64)pPanelInfoEx->u32DClk*10000; //Dclk hz * 10
7191 if( (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type == E_XC_PNL_LPLL_MINILVDS) ||
7192 (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type == E_XC_PNL_LPLL_ANALOG_MINILVDS) ||
7193 (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type == E_XC_PNL_LPLL_DIGITAL_MINILVDS))
7194 {
7195 u32DefaultDClk = u64DClk; //For minilvds
7196 }
7197 }
7198 //LowBound for MaxCLK, UpBound for MinCLK
7199 if(pPanelInfoEx->bMaxDClkValid)
7200 {
7201 u32LowBound = MDrv_PNL_CalculateLPLLSETbyDClk(pInstance, (MS_U64)pPanelInfoEx->u32MaxDClk*10000, FALSE); //Dclk hz * 10
7202 }
7203 if(pPanelInfoEx->bMinDClkValid)
7204 {
7205 u32UpBound = MDrv_PNL_CalculateLPLLSETbyDClk(pInstance, (MS_U64)pPanelInfoEx->u32MinDClk*10000, FALSE); //Dclk hz * 10
7206 }
7207 if(pPanelInfoEx->bDclkDelayValid)
7208 {
7209 u32DelayMs = (MS_U32)pPanelInfoEx->u16DclkDelay;
7210 }
7211 if(pPanelInfoEx->bDclkStepsValid)
7212 {
7213 u32Steps = (MS_U32)pPanelInfoEx->u16DclkSteps;
7214 }
7215 }
7216
7217 u64HighAccurateDClk = (MS_U64)u32AdjHighAccurateVFreq * u16Htt * u16Vtt;
7218
7219 #if (HW_DESIGN_HDMITX_VER == 2) // For Maxim HDMITx case, handle ODCLK for different color depth
7220 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_B & E_XC_INIT_MISC_B_HDMITX_ENABLE)
7221 {
7222 MS_U16 u16ColorDepthFactor = HDMITX_COLORDEPTH_8BIT_FACTOR;
7223
7224 if (pXCResourcePrivate->stdrvXC_MVideo_Context.enHDMITXColorDepth == E_XC_HDMITX_COLORDEPTH_10BIT)
7225 u16ColorDepthFactor = HDMITX_COLORDEPTH_10BIT_FACTOR;
7226 else if (pXCResourcePrivate->stdrvXC_MVideo_Context.enHDMITXColorDepth == E_XC_HDMITX_COLORDEPTH_12BIT)
7227 u16ColorDepthFactor = HDMITX_COLORDEPTH_12BIT_FACTOR;
7228 else if (pXCResourcePrivate->stdrvXC_MVideo_Context.enHDMITXColorDepth == E_XC_HDMITX_COLORDEPTH_16BIT)
7229 u16ColorDepthFactor = HDMITX_COLORDEPTH_16BIT_FACTOR;
7230
7231 u64DClk = (u64DClk * u16ColorDepthFactor)/HDMITX_COLORDEPTH_DEFAULT_FACTOR;
7232 u64HighAccurateDClk = (u64HighAccurateDClk * u16ColorDepthFactor)/HDMITX_COLORDEPTH_DEFAULT_FACTOR;
7233 }
7234 #endif
7235
7236 #if 0
7237 // No matter what, using high accurate VFreq to generate corresponding high accurate LPLL Set
7238 // is always desirable.
7239 if (!(gSrcInfo[eWindow].bFBL || gSrcInfo[eWindow].bFBL))
7240 {
7241 u32HighAccuratePllSet = MDrv_PNL_CalculateLPLLSETbyDClk(u64HighAccurateDClk, TRUE);
7242 }
7243 else
7244 {
7245 u32PllSet = MDrv_PNL_CalculateLPLLSETbyDClk(u64DClk, FALSE);
7246 }
7247 #else
7248 {
7249 u32PllSet = MDrv_PNL_CalculateLPLLSETbyDClk(pInstance, u64DClk, FALSE);
7250 u32HighAccuratePllSet = MDrv_PNL_CalculateLPLLSETbyDClk(pInstance, u64HighAccurateDClk, TRUE);
7251 }
7252 #endif
7253 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "u32PllSet = 0x%tx, u32UpBound = 0x%tx, u32LowBound = 0x%tx\n", (ptrdiff_t)u32PllSet, (ptrdiff_t)u32UpBound, (ptrdiff_t)u32LowBound)
7254 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "u32HighAccuratePllSet = 0x%tx, u32UpBound = 0x%tx, u32LowBound = 0x%tx\n", (ptrdiff_t)u32HighAccuratePllSet, (ptrdiff_t)u32UpBound, (ptrdiff_t)u32LowBound)
7255 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "User forces Enable=%u, LPLL limit=0x%tx\n"
7256 , pXCResourcePrivate->stdrvXC_Display._bFpllCusFlag[E_FPLL_FLAG_D5D6D7]
7257 , (ptrdiff_t)pXCResourcePrivate->stdrvXC_Display._u32FpllCusData[E_FPLL_FLAG_D5D6D7])
7258 if(pXCResourcePrivate->stdrvXC_Display._bForceFreerun == FALSE)
7259 {
7260 HAL_SC_Set_FPLL_Limit(pInstance, &u32HighAccuratePllSet
7261 , u32LowBound
7262 , u32UpBound
7263 , pXCResourcePrivate->stdrvXC_Display._bFpllCusFlag[E_FPLL_FLAG_D5D6D7]
7264 , pXCResourcePrivate->stdrvXC_Display._u32FpllCusData[E_FPLL_FLAG_D5D6D7]);
7265 }
7266
7267 // just first patch for TCON case
7268 #ifdef UFO_XC_FB_LEVEL
7269 if((pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.enPnl_Out_Timing_Mode == E_XC_PNL_CHG_DCLK)
7270 || ((((gSrcInfo[MAIN_WINDOW].eFBLevel == E_XC_FB_LEVEL_FBL) || (gSrcInfo[MAIN_WINDOW].eFBLevel == E_XC_FB_LEVEL_RFBL_DI))
7271 && !gSrcInfo[MAIN_WINDOW].Status2.bMVOPHSKMode)
7272 && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.enPnl_Out_Timing_Mode == E_XC_PNL_CHG_VTOTAL))
7273 || ((pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type != E_XC_PNL_LPLL_MINILVDS)
7274 && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type != E_XC_PNL_LPLL_ANALOG_MINILVDS)
7275 && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type != E_XC_PNL_LPLL_DIGITAL_MINILVDS))
7276 )
7277 #else
7278 if((pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.enPnl_Out_Timing_Mode == E_XC_PNL_CHG_DCLK) ||
7279 (((gSrcInfo[MAIN_WINDOW].bFBL || gSrcInfo[MAIN_WINDOW].bR_FBL) && !gSrcInfo[MAIN_WINDOW].Status2.bMVOPHSKMode)&&
7280 (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.enPnl_Out_Timing_Mode == E_XC_PNL_CHG_VTOTAL)) ||
7281 ((pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type != E_XC_PNL_LPLL_MINILVDS) &&
7282 (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type != E_XC_PNL_LPLL_ANALOG_MINILVDS) &&
7283 (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.eLPLL_Type != E_XC_PNL_LPLL_DIGITAL_MINILVDS)))
7284 #endif
7285 {
7286 MDrv_SC_Set_Output_Dclk_Slowly(pInstance, u32HighAccuratePllSet, u32Steps, u32DelayMs, eWindow);
7287 #if defined (__aarch64__)
7288 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "**** SetOutputDclk-Normal CLK=%lu, Set=0x%X***\n", u64DClk, (unsigned int)u32HighAccuratePllSet)
7289 #else
7290 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "**** SetOutputDclk-Normal CLK=%llu, Set=0x%X***\n", u64DClk, (unsigned int)u32HighAccuratePllSet)
7291 #endif
7292 }
7293 else
7294 {
7295 u32PllSet = MDrv_PNL_CalculateLPLLSETbyDClk(pInstance, (MS_U64)u32DefaultDClk, FALSE);
7296 MDrv_SC_Set_Output_Dclk_Slowly(pInstance, u32PllSet, u32Steps, u32DelayMs, eWindow);
7297 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "**** SetOutputDclk-MINILVDS CLK=%tu, Set=0x%X***\n", (ptrdiff_t)u32DefaultDClk, (unsigned int)u32PllSet)
7298 }
7299 }
7300
7301 //Obsolte function, do not use it any more
MApi_XC_Get_Current_OutputVFreqX100_U2(void * pInstance)7302 MS_U32 MApi_XC_Get_Current_OutputVFreqX100_U2(void* pInstance)
7303 {
7304 #if 0
7305 MS_U32 u32OutFrameRatex100 = 0; //OutVFreq*100
7306
7307 MS_U32 u32PllSet= 0; // 3BYTE
7308 MS_U16 u16Htt = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_0C_L, VOP_HTT_MASK);
7309 MS_U16 u16Vtt = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_0D_L, VOP_VTT_MASK);
7310 MS_U64 u64tmp = 0;
7311
7312 LPLL_BK_STORE;
7313 LPLL_BK_SWITCH(0x00);
7314 u32PllSet= MDrv_Read4Byte(L_BK_LPLL(0x0F)) & 0xFFFFFF; // 3BYTE
7315 LPLL_BK_RESTORE;
7316 if((g_XC_InitData.stPanelInfo.eLPLL_Type == E_XC_PNL_LPLL_MINILVDS) || (g_XC_InitData.stPanelInfo.eLPLL_Type == E_XC_PNL_LPLL_ANALOG_MINILVDS) || (g_XC_InitData.stPanelInfo.eLPLL_Type == E_XC_PNL_LPLL_DIGITAL_MINILVDS))
7317 {
7318 // u32OutFrameRatex100 = (MS_U32)((((MS_U64)LVDS_MPLL_CLOCK_MHZ * 524288 * 2) *100000000)/((MS_U64)(u16Htt * u16Vtt) * u32PllSet));
7319 //**NOTE! In 2.6.28.9 Linux Kernel does not support 64bit division**
7320 // u32OutFrameRatex100 = (MS_U32)((((MS_U64)(LVDS_MPLL_CLOCK_MHZ * 524288) * 2 * 100000000)/(u16Htt * u16Vtt))/ u32PllSet);
7321 u64tmp = ((MS_U64)LVDS_MPLL_CLOCK_MHZ * 524288 * 2) * 100000000;
7322 do_div(u64tmp,(MS_U64)(u16Htt * u16Vtt));
7323 do_div(u64tmp,(u32PllSet));
7324 u32OutFrameRatex100 = u64tmp;
7325 }
7326 else
7327 {
7328 if( g_XC_InitData.stPanelInfo.u8LPLL_Mode )
7329 {
7330 //u32OutFrameRatex100 = (MS_U32)((((MS_U64)(LVDS_MPLL_CLOCK_MHZ * 524288 * LPLL_LOOPGAIN) * 2 * 100000000)/(u16Htt * u16Vtt * 7))/ u32PllSet);
7331 u64tmp = ((MS_U64)LVDS_MPLL_CLOCK_MHZ * 524288 * LPLL_LOOPGAIN * 2) * 100000000;
7332 do_div(u64tmp,(u16Htt * u16Vtt * 7));
7333 do_div(u64tmp,(u32PllSet));
7334 u32OutFrameRatex100 = u64tmp;
7335
7336 }
7337 else
7338 {
7339 // u32OutFrameRatex100 = (MS_U32)((((MS_U64)(LVDS_MPLL_CLOCK_MHZ * 524288 * LPLL_LOOPGAIN) * 100000000)/(u16Htt * u16Vtt * 7))/ u32PllSet);
7340 u64tmp = ((MS_U64)LVDS_MPLL_CLOCK_MHZ * 524288 * LPLL_LOOPGAIN) * 100000000;
7341 do_div(u64tmp,(u16Htt * u16Vtt * 7));
7342 do_div(u64tmp,(u32PllSet));
7343 u32OutFrameRatex100 = u64tmp;
7344 }
7345 }
7346 return u32OutFrameRatex100;
7347 #else
7348 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7349 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7350 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
7351 MS_U32 u32OutputVFreqX100 = 0;
7352 u32OutputVFreqX100 = MDrv_SC_GetOutputVFreqX100(pInstance);
7353 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
7354 return u32OutputVFreqX100;
7355 #endif
7356 }
7357
MApi_XC_Get_Current_OutputVFreqX100(void)7358 MS_U32 MApi_XC_Get_Current_OutputVFreqX100(void)
7359 {
7360 if (pu32XCInst == NULL)
7361 {
7362 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
7363 return 0;
7364 }
7365
7366 stXC_GET_CURRENT_OUTPUTVFREQX100 XCArgs;
7367 XCArgs.u32ReturnValue = 0;
7368
7369 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_GET_CURRENT_OUTPUTVFREQX100, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
7370 {
7371 printf("Obtain XC engine fail\n");
7372 return 0;
7373 }
7374 else
7375 {
7376 return XCArgs.u32ReturnValue;
7377 }
7378 }
7379
7380
7381 //-------------------------------------------------------------------------------------------------
7382 /// Enable or disable IP auto coast
7383 /// @param bEnable \b IN: Enable or Disable
7384 //-------------------------------------------------------------------------------------------------
MDrv_XC_EnableIPAutoCoast(void * pInstance,MS_BOOL bEnable)7385 void MDrv_XC_EnableIPAutoCoast(void *pInstance, MS_BOOL bEnable)
7386 {
7387 /*MS_U8 u8Bank;
7388 u8Bank = MDrv_ReadByte(BK_SELECT_00);
7389 MDrv_WriteByte(BK_SELECT_00, REG_BANK_IP1F2);
7390 MDrv_WriteRegBit(L_BK_IP1F2(0x0F), bEnable, BIT(7));
7391 MDrv_WriteByte(BK_SELECT_00, u8Bank);*/
7392 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7393 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7394 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_0F_L, bEnable? BIT(7):0, BIT(7));
7395 }
7396
MApi_XC_EnableIPAutoCoast_U2(void * pInstance,MS_BOOL bEnable)7397 void MApi_XC_EnableIPAutoCoast_U2(void* pInstance, MS_BOOL bEnable)
7398 {
7399 _XC_ENTRY(pInstance);
7400 MDrv_XC_EnableIPAutoCoast(pInstance, bEnable);
7401 _XC_RETURN(pInstance);
7402 }
7403
MApi_XC_EnableIPAutoCoast(MS_BOOL bEnable)7404 void MApi_XC_EnableIPAutoCoast(MS_BOOL bEnable)
7405 {
7406 if (pu32XCInst == NULL)
7407 {
7408 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
7409 return;
7410 }
7411
7412 stXC_SET_IPAUTOCOAST XCArgs;
7413 XCArgs.bEnable = bEnable;
7414
7415 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_IPAUTOCOAST, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
7416 {
7417 printf("Obtain XC engine fail\n");
7418 return;
7419 }
7420 else
7421 {
7422 return;
7423 }
7424 }
7425
7426 //-------------------------------------------------------------------------------------------------
7427 /// Enable IP auto coast Debounce
7428 //-------------------------------------------------------------------------------------------------
MApi_XC_EnableIPCoastDebounce_U2(void * pInstance)7429 void MApi_XC_EnableIPCoastDebounce_U2(void* pInstance)
7430 {
7431 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7432 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7433 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7434
7435 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
7436 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7437 pXCResourcePrivate->stdrvXC_Display._bDisableCoastDebounce = 0;
7438 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
7439 }
7440
MApi_XC_EnableIPCoastDebounce(void)7441 void MApi_XC_EnableIPCoastDebounce(void)
7442 {
7443 if (pu32XCInst == NULL)
7444 {
7445 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
7446 return;
7447 }
7448
7449 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_IPCOAST_DEBOUNCE_ENABLE, NULL) != UTOPIA_STATUS_SUCCESS)
7450 {
7451 printf("Obtain XC engine fail\n");
7452 return;
7453 }
7454 else
7455 {
7456 return;
7457 }
7458 }
7459
7460 //-------------------------------------------------------------------------------------------------
7461 /// Clear IP auto coast status
7462 //-------------------------------------------------------------------------------------------------
MApi_XC_ClearIPCoastStatus_U2(void * pInstance)7463 void MApi_XC_ClearIPCoastStatus_U2(void* pInstance)
7464 {
7465 MS_U16 u16Tmp;
7466 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7467 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7468 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7469 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
7470 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7471 _XC_ENTRY(pInstance);
7472
7473 u16Tmp = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_0F_L);
7474 if (u16Tmp & BIT(6))
7475 {
7476 pXCResourcePrivate->stdrvXC_Display._u8CoastClearDebounce++;
7477 //MDrv_WriteByte(L_BK_IP1F2(0x0F), u8Tmp & ~(BIT(6)));
7478 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_0F_L, u16Tmp & ~(BIT(6)));
7479 if(pXCResourcePrivate->stdrvXC_Display._u8CoastClearDebounce>3)
7480 {
7481 if (pXCResourcePrivate->stdrvXC_Display._bDisableCoastDebounce)
7482 {
7483 LPLL_BK_STORE;
7484 LPLL_BK_SWITCH(0x00);
7485 MDrv_WriteRegBit(L_BK_LPLL(0x0C), DISABLE, BIT(3));
7486 LPLL_BK_RESTORE;
7487 }
7488 else
7489 {
7490 MDrv_XC_wait_output_vsync(pInstance, 1, 50, MAIN_WINDOW);
7491 Hal_SC_ip_software_reset(pInstance, REST_IP_F2, MAIN_WINDOW);
7492 //MDrv_WriteByte(L_BK_IP1F2(0x0F), u8Tmp & ~(BIT(6)));
7493 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_0F_L, u16Tmp & ~(BIT(6)));
7494 pXCResourcePrivate->stdrvXC_Display._u8CoastClearDebounce=0;
7495 pXCResourcePrivate->stdrvXC_Display._bDisableCoastDebounce = 1;
7496 }
7497 }
7498 }
7499 else
7500 {
7501 MDrv_WriteRegBit(L_BK_LPLL(0x0C), ENABLE, BIT(3));
7502 pXCResourcePrivate->stdrvXC_Display._u8CoastClearDebounce=0;
7503 }
7504 _XC_RETURN(pInstance);
7505 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
7506
7507 }
7508
MApi_XC_ClearIPCoastStatus(void)7509 void MApi_XC_ClearIPCoastStatus(void)
7510 {
7511 if (pu32XCInst == NULL)
7512 {
7513 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
7514 return;
7515 }
7516
7517 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_CLEAR_IPCOAST_STATUS, NULL) != UTOPIA_STATUS_SUCCESS)
7518 {
7519 printf("Obtain XC engine fail\n");
7520 return;
7521 }
7522 else
7523 {
7524 return;
7525 }
7526 }
7527
7528 //-------------------------------------------------------------------------------------------------
7529 /// Query the capability of scaler about source to Video encoder(VE)
7530 /// @param OutputCapability \b OUT: Which part of scaler can output data to Video Encoder (VE).
7531 ///Check E_XC_SOURCE_TO_VE for capability bit. Take an example, if bit0 of OutputCapability equal to 1,
7532 ///Scaler can output data to ve from its E_XC_IP(IP)
7533 ///@return @ref MS_BOOL True if query success.
7534 //-------------------------------------------------------------------------------------------------
MApi_XC_SupportSourceToVE_U2(void * pInstance,MS_U16 * pOutputCapability)7535 E_APIXC_ReturnValue MApi_XC_SupportSourceToVE_U2(void* pInstance, MS_U16* pOutputCapability)
7536 {
7537 return Hal_SC_support_source_to_ve(pInstance, pOutputCapability);
7538 }
7539
MApi_XC_SupportSourceToVE(MS_U16 * pOutputCapability)7540 E_APIXC_ReturnValue MApi_XC_SupportSourceToVE(MS_U16* pOutputCapability)
7541 {
7542 if (pu32XCInst == NULL)
7543 {
7544 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
7545 return E_APIXC_RET_FAIL;
7546 }
7547
7548 stXC_GET_SUPPORT_SOURCE_TO_VE XCArgs;
7549 XCArgs.pOutputCapability = pOutputCapability;
7550 XCArgs.eReturnValue = E_APIXC_RET_FAIL;
7551
7552 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_GET_SUPPORT_SOURCE_TO_VE, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
7553 {
7554 printf("Obtain XC engine fail\n");
7555 return E_APIXC_RET_FAIL;
7556 }
7557 else
7558 {
7559 return XCArgs.eReturnValue;
7560 }
7561 }
7562
MApi_XC_SetOutputCapture_U2(void * pInstance,MS_BOOL bEnable,E_XC_SOURCE_TO_VE eSourceToVE)7563 E_APIXC_ReturnValue MApi_XC_SetOutputCapture_U2(void* pInstance, MS_BOOL bEnable,E_XC_SOURCE_TO_VE eSourceToVE)
7564 {
7565 E_APIXC_ReturnValue ret;
7566 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7567 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7568 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
7569 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7570 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7571 _XC_ENTRY(pInstance);
7572 ret = Hal_SC_set_output_capture_enable(pInstance, bEnable,eSourceToVE);
7573 if(bEnable)
7574 {
7575 gSrcInfo[MAIN_WINDOW].Status2.eSourceToVE = eSourceToVE;
7576 }
7577 else
7578 {
7579 gSrcInfo[MAIN_WINDOW].Status2.eSourceToVE = E_XC_NONE;
7580 }
7581 _XC_RETURN(pInstance);
7582 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
7583 return ret;
7584 }
7585
MApi_XC_SetOutputCapture(MS_BOOL bEnable,E_XC_SOURCE_TO_VE eSourceToVE)7586 E_APIXC_ReturnValue MApi_XC_SetOutputCapture(MS_BOOL bEnable,E_XC_SOURCE_TO_VE eSourceToVE)
7587 {
7588 if (pu32XCInst == NULL)
7589 {
7590 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
7591 return E_APIXC_RET_FAIL;
7592 }
7593
7594 stXC_SET_OUTPUT_CAPTURE XCArgs;
7595 XCArgs.bEnable = bEnable;
7596 XCArgs.eSourceToVE = eSourceToVE;
7597 XCArgs.eReturnValue = E_APIXC_RET_FAIL;
7598
7599 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_OUTPUT_CAPTURE, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
7600 {
7601 printf("Obtain XC engine fail\n");
7602 return E_APIXC_RET_FAIL;
7603 }
7604 else
7605 {
7606 return XCArgs.eReturnValue;
7607 }
7608 }
7609
MDrv_SC_set_csc(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)7610 void MDrv_SC_set_csc(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow )
7611 {
7612 Hal_SC_set_csc(pInstance, bEnable, eWindow );
7613 }
MApi_XC_SetCsc_U2(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)7614 void MApi_XC_SetCsc_U2( void* pInstance, MS_BOOL bEnable, SCALER_WIN eWindow )
7615 {
7616 MDrv_SC_set_csc(pInstance, bEnable, eWindow );
7617 return ;
7618 }
7619
MApi_XC_SetCsc(MS_BOOL bEnable,SCALER_WIN eWindow)7620 void MApi_XC_SetCsc( MS_BOOL bEnable, SCALER_WIN eWindow )
7621 {
7622 if (pu32XCInst == NULL)
7623 {
7624 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
7625 return;
7626 }
7627
7628 stXC_SET_CSC XCArgs;
7629 XCArgs.bEnable = bEnable;
7630 XCArgs.eWindow = eWindow;
7631
7632 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_CSC, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
7633 {
7634 printf("Obtain XC engine fail\n");
7635 return;
7636 }
7637 else
7638 {
7639 return;
7640 }
7641 }
7642
MDrv_SC_rep_window(void * pInstance,MS_BOOL bEnable,MS_WINDOW_TYPE Win,MS_U8 u8Color)7643 void MDrv_SC_rep_window(void *pInstance, MS_BOOL bEnable,MS_WINDOW_TYPE Win,MS_U8 u8Color)
7644 {
7645 Hal_SC_set_rep_window(pInstance, bEnable,Win.x,Win.y,Win.width,Win.height,u8Color);
7646 }
7647
7648 //-------------------------------------------------------------------------------------------------
7649 /// update display window registers with input window
7650 /// @param eWindow \b IN: Main or sub window
7651 /// @param pdspwin \b IN: window info that will be setted to registers
7652 //-------------------------------------------------------------------------------------------------
MDrv_XC_set_dispwin_to_reg(void * pInstance,SCALER_WIN eWindow,MS_WINDOW_TYPE * pdspwin)7653 void MDrv_XC_set_dispwin_to_reg(void *pInstance, SCALER_WIN eWindow, MS_WINDOW_TYPE *pdspwin)
7654 {
7655 Hal_SC_set_disp_window(pInstance, eWindow, pdspwin);
7656 }
7657
7658 //-------------------------------------------------------------------------------------------------
7659 /// update all window registers with input window(Including DE window, and try use MLOAD)
7660 /// @param pDEWin \b IN: Panel DE window info that will be setted to registers
7661 /// @param pMainWin \b IN: Main display window info that will be setted to registers
7662 /// @param pSubWin \b IN: Sub display window info that will be setted to registers
7663 /// Notes: if one of the pxxWin=NULL, the related window will not be setted
7664 //-------------------------------------------------------------------------------------------------
MDrv_XC_UpdateWindow(void * pInstance,MS_WINDOW_TYPE * pDEWin,MS_WINDOW_TYPE * pMainWin,MS_WINDOW_TYPE * pSubWin,MS_WINDOW_TYPE * pReportWin,MS_WINDOW_TYPE * pNewOSDWin)7665 void MDrv_XC_UpdateWindow(void *pInstance, MS_WINDOW_TYPE *pDEWin, MS_WINDOW_TYPE *pMainWin, MS_WINDOW_TYPE *pSubWin, MS_WINDOW_TYPE *pReportWin, MS_WINDOW_TYPE *pNewOSDWin)
7666 {
7667 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7668 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7669 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
7670 if (psXCInstPri->u32DeviceID == 1)
7671 {
7672 /// not support
7673 return;
7674 }
7675 CHECK_DEVICE1_INSTANCE();
7676 XC_INSTANCE_PRIVATE *psXCInstPri_1 = NULL;
7677 UtopiaInstanceGetPrivate(g_pDevice1Instance, (void**)&psXCInstPri_1);
7678 XC_RESOURCE_PRIVATE* pXCResourcePrivate_1 = NULL;
7679 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri_1->u32DeviceID)],(void**)(&pXCResourcePrivate_1));
7680 #endif
7681 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7682 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7683 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
7684 E_FRC_MLOAD_TRIG_MODE eTrigMode = E_FRC_MLOAD_TRIG_MODE_FROM_OP1;
7685 if(SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK68_5F_L) & BIT(15))
7686 {
7687 eTrigMode = E_FRC_MLOAD_TRIG_MODE_FROM_OP2;
7688 }
7689 else
7690 {
7691 eTrigMode = E_FRC_MLOAD_TRIG_MODE_FROM_OP1;
7692 }
7693
7694 MHal_FRC_Set_Mload_Trig_Mode(pInstance, E_FRC_MLOAD_TRIG_MODE_FROM_OP1);
7695 #endif
7696 if (MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED)
7697 {
7698 _MLOAD_ENTRY(pInstance);
7699 // Panel DE window
7700 if(pDEWin != NULL)
7701 {
7702 //FIX ME:need follow HW_DESIGN_4K2K_VER = 6 rule
7703 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_04_L, pDEWin->x, VOP_DE_HSTART_MASK);
7704 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_05_L, (pDEWin->x+pDEWin->width-1), VOP_DE_HEND_MASK);
7705 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_06_L, pDEWin->y, VOP_DE_VSTART_MASK);
7706 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_07_L, (pDEWin->y+pDEWin->height-1), VOP_DE_VEND_MASK);
7707 memcpy(&(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo), pDEWin, sizeof(MS_WINDOW_TYPE));
7708 memcpy(&(gSrcInfo[MAIN_WINDOW].Status2.stXCPanelDefaultTiming), pDEWin, sizeof(MS_WINDOW_TYPE));
7709 }
7710 // Main Display window
7711 if(pMainWin != NULL)
7712 {
7713 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
7714 if (IsFSCDisplayWindowEnable())
7715 {
7716 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK68_05_L, pMainWin->x, VOP_DISPLAY_HSTART_MASK);
7717 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK68_06_L, (pMainWin->x+pMainWin->width-1), VOP_DISPLAY_HEND_MASK);
7718 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK68_0D_L, pMainWin->y, VOP_DISPLAY_VSTART_MASK);
7719 // HW limit: MDE_Vend > FDE_Vend will cause PostScaling overrun. So fix this location.
7720 // MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK68_0E_L, (pMainWin->y+pMainWin->height-1), VOP_DISPLAY_VEND_MASK);
7721 MS_U16 u16DEVend = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK68_0C_L);
7722 if((pMainWin->y+pMainWin->height-1) >= u16DEVend)
7723 {
7724 //when MDE_Vend > FDE_Vend,use defaut
7725 //MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK68_0E_L, u16DEVend, 0x1FFF);
7726 }
7727 else
7728 {
7729 //if MDE_Vend < FDE_Vend must move MDE Vend to aviod pixshift last V pix repeat
7730 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK68_0E_L, (pMainWin->y+pMainWin->height-1), 0x1FFF);
7731 }
7732 }
7733 else
7734 #endif
7735 {
7736 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_08_L, pMainWin->x, VOP_DISPLAY_HSTART_MASK);
7737 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_09_L, (pMainWin->x+pMainWin->width-1), VOP_DISPLAY_HEND_MASK);
7738 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0A_L, pMainWin->y, VOP_DISPLAY_VSTART_MASK);
7739 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0B_L, (pMainWin->y+pMainWin->height-1), VOP_DISPLAY_VEND_MASK);
7740 }
7741 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
7742 if (IsFSCDisplayWindowEnable() && (MHal_FRC_IsFHDToFSC(pInstance, MAIN_WINDOW)))
7743 {
7744 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW, "FRC_IsFHDToFSC: ByPass chagne global var for DispWin.\n");
7745
7746 }
7747 else
7748 #endif
7749 {
7750 memcpy(&(gSrcInfo[MAIN_WINDOW].stDispWin), pMainWin, sizeof(MS_WINDOW_TYPE));
7751 }
7752 }
7753 // Sub Display window
7754 if(pSubWin != NULL)
7755 {
7756 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_07_L, pSubWin->x, 0x3FFF);
7757 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_08_L, (pSubWin->x+pSubWin->width-1), 0x3FFF);
7758 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_09_L, pSubWin->y, 0x1FFF);
7759 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_0A_L, (pSubWin->y+pSubWin->height-1), 0x1FFF);
7760 memcpy(&(gSrcInfo[SUB_WINDOW].stDispWin), pSubWin, sizeof(MS_WINDOW_TYPE));
7761 }
7762 //Report window
7763 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_bEnableRepWindowForFrameColor && (pReportWin != NULL))
7764 {
7765 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_42_L, pReportWin->x, 0xFFFF);
7766 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_43_L, pReportWin->x+pReportWin->width-2, 0xFFFF);
7767 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_44_L, pReportWin->y, 0xFFFF);
7768 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_45_L, pReportWin->y+pReportWin->height-1, 0xFFFF);
7769 memcpy(&pXCResourcePrivate->stdrvXC_MVideo_Context.g_RepWindow, pReportWin, sizeof(MS_WINDOW_TYPE));
7770 }
7771
7772 // Please add here for GOP ...
7773 if ((SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK2D_10_L, BIT(15))) && (pNewOSDWin != NULL))
7774 {
7775 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK2D_10_L, pNewOSDWin->x, 0xFFFF);
7776 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK2D_11_L, pNewOSDWin->x+pNewOSDWin->width-1, 0xFFFF);
7777 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK2D_12_L, pNewOSDWin->y, 0xFFFF);
7778 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK2D_13_L, pNewOSDWin->y+pNewOSDWin->height-1, 0xFFFF);
7779 }
7780 MDrv_XC_MLoad_Fire(pInstance, TRUE);
7781 _MLOAD_RETURN(pInstance);
7782 }
7783 else
7784 {
7785 // Panel DE window
7786 if(pDEWin != NULL)
7787 {
7788 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_04_L, pDEWin->x);
7789 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_05_L, (pDEWin->x+pDEWin->width-1));
7790 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_06_L, pDEWin->y);
7791 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_07_L, (pDEWin->y+pDEWin->height-1));
7792 memcpy(&(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo), pDEWin, sizeof(MS_WINDOW_TYPE));
7793 memcpy(&(gSrcInfo[MAIN_WINDOW].Status2.stXCPanelDefaultTiming), pDEWin, sizeof(MS_WINDOW_TYPE));
7794 }
7795 // Main Display window
7796 if(pMainWin != NULL)
7797 {
7798 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
7799 if (IsFSCDisplayWindowEnable())
7800 {
7801 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK68_05_L, pMainWin->x);
7802 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK68_06_L, (pMainWin->x+pMainWin->width-1));
7803 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK68_0D_L, pMainWin->y);
7804 // HW limit: MDE_Vend > FDE_Vend will cause PostScaling overrun. So fix this location.
7805 //SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK68_0E_L, (pMainWin->y+pMainWin->height-1));
7806 MS_U16 u16DEVend = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK68_0C_L);
7807 if((pMainWin->y+pMainWin->height-1) >= u16DEVend)
7808 {
7809 //SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK68_0E_L, u16DEVend);
7810 }
7811 else
7812 {
7813 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK68_0E_L, (pMainWin->y+pMainWin->height-1));
7814 }
7815 }
7816 else
7817 #endif
7818 {
7819 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_08_L, pMainWin->x);
7820 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_09_L, (pMainWin->x+pMainWin->width-1));
7821 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0A_L, pMainWin->y);
7822 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0B_L, (pMainWin->y+pMainWin->height-1));
7823 }
7824 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
7825 if (IsFSCDisplayWindowEnable() && (MHal_FRC_IsFHDToFSC(pInstance, MAIN_WINDOW)))
7826 {
7827 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW, "FRC_IsFHDToFSC: ByPass chagne global var for DispWin.\n");
7828
7829 }
7830 else
7831 #endif
7832 {
7833 memcpy(&(gSrcInfo[MAIN_WINDOW].stDispWin), pMainWin, sizeof(MS_WINDOW_TYPE));
7834 }
7835 }
7836 // Sub Display window
7837 if(pSubWin != NULL)
7838 {
7839 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_07_L, pSubWin->x);
7840 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_08_L, (pSubWin->x+pSubWin->width-1));
7841 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_09_L, pSubWin->y);
7842 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_0A_L, (pSubWin->y+pSubWin->height-1));
7843 memcpy(&(gSrcInfo[SUB_WINDOW].stDispWin), pSubWin, sizeof(MS_WINDOW_TYPE));
7844 }
7845 //Report window
7846 if (pReportWin != NULL)
7847 {
7848 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_42_L, pReportWin->x);
7849 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_43_L, pReportWin->x+pReportWin->width-2);
7850 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_44_L, pReportWin->y);
7851 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_45_L, pReportWin->y+pReportWin->height-1);
7852 //Skip enable here, SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_57_L, BIT(8)|BIT(9), BIT(8)|BIT(9)); // Enable display rep window
7853 }
7854
7855 // Please add here for GOP ...
7856 if (pNewOSDWin != NULL)
7857 {
7858 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK2D_10_L, pNewOSDWin->x);
7859 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK2D_11_L, pNewOSDWin->x+pNewOSDWin->width-1);
7860 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK2D_12_L, pNewOSDWin->y);
7861 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK2D_13_L, pNewOSDWin->y+pNewOSDWin->height-1);
7862 }
7863 }
7864 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
7865 //FIX ME:need follow HW_DESIGN_4K2K_VER = 6 rule
7866 if (MDrv_XC_MLoad_GetStatus(g_pDevice1Instance) == E_MLOAD_ENABLED)
7867 {
7868 _MLOAD_ENTRY(g_pDevice1Instance);
7869 // Panel DE window
7870 if(pDEWin != NULL)
7871 {
7872 MDrv_XC_MLoad_WriteCmd(g_pDevice1Instance, REG_SC_BK10_04_L, pDEWin->x, VOP_DE_HSTART_MASK);
7873 MDrv_XC_MLoad_WriteCmd(g_pDevice1Instance, REG_SC_BK10_05_L, (pDEWin->x+pDEWin->width-1), VOP_DE_HEND_MASK);
7874 MDrv_XC_MLoad_WriteCmd(g_pDevice1Instance, REG_SC_BK10_06_L, pDEWin->y, VOP_DE_VSTART_MASK);
7875 MDrv_XC_MLoad_WriteCmd(g_pDevice1Instance, REG_SC_BK10_07_L, (pDEWin->y+pDEWin->height-1), VOP_DE_VEND_MASK);
7876 memcpy(&(pXCResourcePrivate_1->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo), pDEWin, sizeof(MS_WINDOW_TYPE));
7877 memcpy(&(gSrcInfo_1[MAIN_WINDOW].Status2.stXCPanelDefaultTiming), pDEWin, sizeof(MS_WINDOW_TYPE));
7878 }
7879 // Sub Display window
7880 if(pSubWin != NULL)
7881 {
7882 MDrv_XC_MLoad_WriteCmd(g_pDevice1Instance, REG_SC_BK10_08_L, pSubWin->x, VOP_DISPLAY_HSTART_MASK);
7883 MDrv_XC_MLoad_WriteCmd(g_pDevice1Instance, REG_SC_BK10_09_L, (pSubWin->x+pSubWin->width-1), VOP_DISPLAY_HEND_MASK);
7884 MDrv_XC_MLoad_WriteCmd(g_pDevice1Instance, REG_SC_BK10_0A_L, pSubWin->y, VOP_DISPLAY_VSTART_MASK);
7885 MDrv_XC_MLoad_WriteCmd(g_pDevice1Instance, REG_SC_BK10_0B_L, (pSubWin->y+pSubWin->height-1), VOP_DISPLAY_VEND_MASK);
7886 memcpy(&(gSrcInfo_1[MAIN_WINDOW].stDispWin), pSubWin, sizeof(MS_WINDOW_TYPE));
7887 }
7888 //Report window
7889 if (pXCResourcePrivate->stdrvXC_MVideo_Context.g_bEnableRepWindowForFrameColor && (pReportWin != NULL))
7890 {
7891 MDrv_XC_MLoad_WriteCmd(g_pDevice1Instance, REG_SC_BK0F_42_L, pReportWin->x, 0xFFFF);
7892 MDrv_XC_MLoad_WriteCmd(g_pDevice1Instance, REG_SC_BK0F_43_L, pReportWin->x+pReportWin->width-2, 0xFFFF);
7893 MDrv_XC_MLoad_WriteCmd(g_pDevice1Instance, REG_SC_BK0F_44_L, pReportWin->y, 0xFFFF);
7894 MDrv_XC_MLoad_WriteCmd(g_pDevice1Instance, REG_SC_BK0F_45_L, pReportWin->y+pReportWin->height-1, 0xFFFF);
7895 memcpy(&pXCResourcePrivate_1->stdrvXC_MVideo_Context.g_RepWindow, pReportWin, sizeof(MS_WINDOW_TYPE));
7896 }
7897 MDrv_XC_MLoad_Fire(g_pDevice1Instance, TRUE);
7898 _MLOAD_RETURN(g_pDevice1Instance);
7899 }
7900 else
7901 {
7902 // Panel DE window
7903 if(pDEWin != NULL)
7904 {
7905 SC_W2BYTE(psXCInstPri_1->u32DeviceID, REG_SC_BK10_04_L, pDEWin->x);
7906 SC_W2BYTE(psXCInstPri_1->u32DeviceID, REG_SC_BK10_05_L, (pDEWin->x+pDEWin->width-1));
7907 SC_W2BYTE(psXCInstPri_1->u32DeviceID, REG_SC_BK10_06_L, pDEWin->y);
7908 SC_W2BYTE(psXCInstPri_1->u32DeviceID, REG_SC_BK10_07_L, (pDEWin->y+pDEWin->height-1));
7909 memcpy(&(pXCResourcePrivate_1->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo), pDEWin, sizeof(MS_WINDOW_TYPE));
7910 memcpy(&(gSrcInfo_1[MAIN_WINDOW].Status2.stXCPanelDefaultTiming), pDEWin, sizeof(MS_WINDOW_TYPE));
7911 }
7912 // Sub Display window
7913 if(pSubWin != NULL)
7914 {
7915 SC_W2BYTE(psXCInstPri_1->u32DeviceID, REG_SC_BK10_08_L, pSubWin->x);
7916 SC_W2BYTE(psXCInstPri_1->u32DeviceID, REG_SC_BK10_09_L, (pSubWin->x+pSubWin->width-1));
7917 SC_W2BYTE(psXCInstPri_1->u32DeviceID, REG_SC_BK10_0A_L, pSubWin->y);
7918 SC_W2BYTE(psXCInstPri_1->u32DeviceID, REG_SC_BK10_0B_L, (pSubWin->y+pSubWin->height-1));
7919 memcpy(&(gSrcInfo_1[MAIN_WINDOW].stDispWin), pSubWin, sizeof(MS_WINDOW_TYPE));
7920 }
7921 //Report window
7922 if (pReportWin != NULL)
7923 {
7924 SC_W2BYTE(psXCInstPri_1->u32DeviceID, REG_SC_BK0F_42_L, pReportWin->x);
7925 SC_W2BYTE(psXCInstPri_1->u32DeviceID, REG_SC_BK0F_43_L, pReportWin->x+pReportWin->width-2);
7926 SC_W2BYTE(psXCInstPri_1->u32DeviceID, REG_SC_BK0F_44_L, pReportWin->y);
7927 SC_W2BYTE(psXCInstPri_1->u32DeviceID, REG_SC_BK0F_45_L, pReportWin->y+pReportWin->height-1);
7928 }
7929 }
7930 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
7931 MHal_FRC_Set_Mload_Trig_Mode(pInstance, eTrigMode);
7932 #endif
7933 #endif
7934 }
7935
7936 //-------------------------------------------------------------------------------------------------
7937 /// get current display window registers setting
7938 /// @param eWindow \b IN : Main or sub window
7939 /// @param pdspwin \b OUT: Pointer for ouput disp window register
7940 //-------------------------------------------------------------------------------------------------
MDrv_XC_get_dispwin_from_reg(void * pInstance,SCALER_WIN eWindow,MS_WINDOW_TYPE * pdspwin)7941 void MDrv_XC_get_dispwin_from_reg(void *pInstance, SCALER_WIN eWindow, MS_WINDOW_TYPE *pdspwin)
7942 {
7943 Hal_SC_get_disp_window(pInstance, eWindow, pdspwin);
7944 }
7945
7946 //-------------------------------------------------------------------------------------------------
7947 /// Set VOP Gain for Main Window(after 3x3 before Gamma)
7948 /// @param eVop_Channel \b IN: Select VOP R/G/B
7949 /// @param u16Val \b IN: Set value
7950 //-------------------------------------------------------------------------------------------------
MApi_XC_SetPreGammaGain_U2(void * pInstance,SCALER_WIN eWindow,MS_XC_VOP_CHANNEL_t eVop_Channel,MS_U16 u16Val)7951 void MApi_XC_SetPreGammaGain_U2(void* pInstance, SCALER_WIN eWindow, MS_XC_VOP_CHANNEL_t eVop_Channel, MS_U16 u16Val)
7952 {
7953 _XC_ENTRY(pInstance);
7954 HAL_SC_VOP_Set_Contrast_Value(pInstance, eVop_Channel, u16Val, eWindow);
7955 _XC_RETURN(pInstance);
7956 }
7957
MApi_XC_SetPreGammaGain(SCALER_WIN eWindow,MS_XC_VOP_CHANNEL_t eVop_Channel,MS_U16 u16Val)7958 void MApi_XC_SetPreGammaGain(SCALER_WIN eWindow, MS_XC_VOP_CHANNEL_t eVop_Channel, MS_U16 u16Val)
7959 {
7960 if (pu32XCInst == NULL)
7961 {
7962 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
7963 return;
7964 }
7965
7966 stXC_SET_PREGAMMA_GAIN XCArgs;
7967 XCArgs.eWindow = eWindow;
7968 XCArgs.eVop_Channel = eVop_Channel;
7969 XCArgs.u16Val = u16Val;
7970
7971 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_PREGAMMA_GAIN, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
7972 {
7973 printf("Obtain XC engine fail\n");
7974 return;
7975 }
7976 else
7977 {
7978 return;
7979 }
7980 }
7981
7982 //-------------------------------------------------------------------------------------------------
7983 /// Set VOP Offset for Main Window(after 3x3 before Gamma)
7984 /// @param eVop_Channel \b IN: Select VOP R/G/B
7985 /// @param u16Val \b IN: Set value
7986 //-------------------------------------------------------------------------------------------------
MApi_XC_SetPreGammaOffset_U2(void * pInstance,SCALER_WIN eWindow,MS_XC_VOP_CHANNEL_t eVop_Channel,MS_U16 u16Val)7987 void MApi_XC_SetPreGammaOffset_U2(void* pInstance, SCALER_WIN eWindow, MS_XC_VOP_CHANNEL_t eVop_Channel, MS_U16 u16Val)
7988 {
7989 _XC_ENTRY(pInstance);
7990 HAL_SC_VOP_Set_Brightness_Value(pInstance, eVop_Channel, u16Val, eWindow);
7991 _XC_RETURN(pInstance);
7992 }
7993
MApi_XC_SetPreGammaOffset(SCALER_WIN eWindow,MS_XC_VOP_CHANNEL_t eVop_Channel,MS_U16 u16Val)7994 void MApi_XC_SetPreGammaOffset(SCALER_WIN eWindow, MS_XC_VOP_CHANNEL_t eVop_Channel, MS_U16 u16Val)
7995 {
7996 if (pu32XCInst == NULL)
7997 {
7998 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
7999 return;
8000 }
8001
8002 stXC_SET_PREGAMMA_OFFSET XCArgs;
8003 XCArgs.eWindow = eWindow;
8004 XCArgs.eVop_Channel = eVop_Channel;
8005 XCArgs.u16Val = u16Val;
8006
8007 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_PREGAMMA_OFFSET, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
8008 {
8009 printf("Obtain XC engine fail\n");
8010 return;
8011 }
8012 else
8013 {
8014 return;
8015 }
8016 }
8017
8018 //-------------------------------------------------------------------------------------------------
8019 /// Wait FPLL finished
8020 /// @return @ref MS_BOOL indicate FPLL finished or not (frame lock finished or not)
8021 //-------------------------------------------------------------------------------------------------
_MDrv_SC_WaitFPLLDone(void * pInstance)8022 static MS_BOOL _MDrv_SC_WaitFPLLDone(void *pInstance)
8023 {
8024 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8025 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8026 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8027 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8028 if(HAL_SC_WaitFPLLDone(pInstance))
8029 {
8030 if(pXCResourcePrivate->stdrvXC_Display._bNeedReloadMCNR
8031 && pXCResourcePrivate->stdrvXC_Display._bEnableMCNR[MAIN_WINDOW]
8032 && !pXCResourcePrivate->stdrvXC_Display._bForceDisableMCNR)
8033 {
8034 MS_U32 u32timer = MsOS_GetSystemTime() - pXCResourcePrivate->stdrvXC_Display._u32MCNRTimer;
8035 MS_U32 u32DelayTime = (MS_U32)_MDrv_SC_FPLL_GetMCNRDelayTime(pInstance);
8036 if(u32DelayTime > u32timer)
8037 {
8038 MsOS_DelayTask(u32DelayTime-u32timer); //Turn on before 8 vsync
8039 }
8040 if (!pXCResourcePrivate->stdrvXC_Display._bSkipDisableOPWriteOffInFPLL[MAIN_WINDOW])
8041 {
8042 _XC_ENTRY(pInstance);
8043 Hal_SC_SetOPWriteOff(pInstance, !pXCResourcePrivate->stdrvXC_Display._bEnableMCNR[MAIN_WINDOW]);
8044 _XC_RETURN(pInstance);
8045 }
8046 pXCResourcePrivate->stdrvXC_Display._bNeedReloadMCNR = FALSE;
8047 }
8048 return TRUE;
8049 }
8050 else
8051 {
8052 return FALSE;
8053 }
8054 }
8055
8056 //-------------------------------------------------------------------------------------------------
8057 /// Wait FPLL finished
8058 /// @return @ref MS_BOOL indicate FPLL finished or not (frame lock finished or not)
8059 //-------------------------------------------------------------------------------------------------
MApi_XC_WaitFPLLDone_U2(void * pInstance)8060 MS_BOOL MApi_XC_WaitFPLLDone_U2(void* pInstance)
8061 {
8062 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8063 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8064 if(0)//(psXCInstPri->u32DeviceID > E_XC_DEVICE0)
8065 {
8066 printf("[%s] Not support FPLL for device id %td\n",__FUNCTION__,(ptrdiff_t)psXCInstPri->u32DeviceID);
8067 printf("MApi_XC_EX_WaitFPLLDone() -> Not support FPLL for device id %td\n", (ptrdiff_t)psXCInstPri->u32DeviceID);
8068 return FALSE;
8069 }
8070 // we didn't add mutex here because
8071 // in T3, MDrv_SC_WaitFPLLDone() will use ISR
8072 // in U3, MDrv_SC_WaitFPLLDone() won't use ISR and will use mutex in HAL layer
8073 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8074 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
8075 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8076 MS_BOOL bReturn = FALSE;
8077 if(gSrcInfo[MAIN_WINDOW].bEnableFPLL)
8078 {
8079 if(pXCResourcePrivate->stdrvXC_Display._bFSM_FPLL_Working)
8080 {
8081 gSrcInfo[MAIN_WINDOW].bDoneFPLL = TRUE; //FSM framelock open screen directly, no need to wait.
8082 }
8083 else
8084 {
8085 gSrcInfo[MAIN_WINDOW].bDoneFPLL = _MDrv_SC_WaitFPLLDone(pInstance);
8086 }
8087 }
8088 else
8089 {
8090 gSrcInfo[MAIN_WINDOW].bDoneFPLL = FALSE; //Freerun, NO fpll
8091 }
8092 bReturn = gSrcInfo[MAIN_WINDOW].bDoneFPLL;
8093 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
8094
8095 return bReturn;
8096 }
8097
MApi_XC_WaitFPLLDone(void)8098 MS_BOOL MApi_XC_WaitFPLLDone(void)
8099 {
8100 if (pu32XCInst == NULL)
8101 {
8102 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
8103 return FALSE;
8104 }
8105
8106 stXC_GET_WAIT_FPLL_DONE XCArgs;
8107 XCArgs.bReturnValue = FALSE;
8108
8109 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_GET_WAIT_FPLL_DONE, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
8110 {
8111 printf("Obtain XC engine fail\n");
8112 return FALSE;
8113 }
8114 else
8115 {
8116 return XCArgs.bReturnValue;
8117 }
8118 }
8119 //-------------------------------------------------------------------------------------------------
8120 /// Get scaler output vertical frequency
8121 /// @return @ref MS_U16 return output vertical frequency x 100
8122 //-------------------------------------------------------------------------------------------------
MDrv_SC_GetOutputVFreqX100(void * pInstance)8123 MS_U16 MDrv_SC_GetOutputVFreqX100(void *pInstance)
8124 {
8125 MS_U16 u16OutputVFreqAfterFRC = 0;
8126 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8127 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8128 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8129 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8130 #if defined(XC_SUPPORT_FRC_CONVERT) && (XC_SUPPORT_FRC_CONVERT == 0)
8131 u16OutputVFreqAfterFRC = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq*10;
8132 #else
8133 u16OutputVFreqAfterFRC = (MS_U16)((gSrcInfo[MAIN_WINDOW].Status2.u32HighAccurateOutputVFreqAfterFRC+5)/10);
8134 #endif
8135 return u16OutputVFreqAfterFRC;
8136 }
8137
8138 //-------------------------------------------------------------------------------------------------
8139 /// Get OP1 output vertical frequency
8140 /// @return @ref MS_U16 return output vertical frequency x 100
8141 //-------------------------------------------------------------------------------------------------
MDrv_SC_GetOP1OutputVFreqX100(void * pInstance)8142 MS_U16 MDrv_SC_GetOP1OutputVFreqX100(void *pInstance)
8143 {
8144 MS_U16 u16OP1_OutputVFreqAfterFRC = 0;
8145 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8146 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8147 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8148 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8149 #if defined(XC_SUPPORT_FRC_CONVERT) && (XC_SUPPORT_FRC_CONVERT == 0)
8150 u16OP1_OutputVFreqAfterFRC = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq*10;
8151 #else
8152 #if FRC_INSIDE
8153 #if (HW_DESIGN_4K2K_VER != 6) // for manhattan, only 1 LPLL
8154 if(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Pnl_Misc.FRCInfo.bFRC)
8155 {
8156 u16OP1_OutputVFreqAfterFRC = gSrcInfo[MAIN_WINDOW].Status2.u16OP1_OutputVFreqAfterFRC*10;
8157 }
8158 else
8159 #endif
8160 {
8161 u16OP1_OutputVFreqAfterFRC = (MS_U16)((gSrcInfo[MAIN_WINDOW].Status2.u32HighAccurateOutputVFreqAfterFRC+5)/10);
8162 }
8163 #else
8164 u16OP1_OutputVFreqAfterFRC = (MS_U16)((gSrcInfo[MAIN_WINDOW].Status2.u32HighAccurateOutputVFreqAfterFRC+5)/10);
8165 #endif
8166 #endif
8167
8168 return u16OP1_OutputVFreqAfterFRC;
8169 }
8170
8171
8172 //-------------------------------------------------------------------------------------------------
8173 /// Set scaler display line buffer mode
8174 /// @param bEnable \b IN: Select "Enable" to ring buffer mode or "Disable" for line buffer mode
8175 //-------------------------------------------------------------------------------------------------
MDrv_SC_SetDisplay_LineBuffer_Mode(void * pInstance,MS_BOOL bEnable)8176 void MDrv_SC_SetDisplay_LineBuffer_Mode(void *pInstance, MS_BOOL bEnable)
8177 {
8178 HAL_SC_SetDisplay_LineBuffer_Mode(pInstance, bEnable);
8179 }
8180
8181 //-------------------------------------------------------------------------------------------------
8182 /// Set scaler display line buffer Start mode
8183 /// @param bEnable \b IN: Select "Enable" to start at faling edge of Vsync_init or
8184 /// "Disable" for start at advance 1 display line
8185 //-------------------------------------------------------------------------------------------------
MDrv_SC_SetDisplay_Start_Mode(void * pInstance,MS_BOOL bEnable)8186 void MDrv_SC_SetDisplay_Start_Mode(void *pInstance, MS_BOOL bEnable)
8187 {
8188 HAL_SC_SetDisplay_Start_Mode(pInstance, bEnable);
8189 }
8190
MDrv_XC_SetOSD2VEmode(void * pInstance,EN_VOP_SEL_OSD_XC2VE_MUX eVOPSelOSD_MUX)8191 void MDrv_XC_SetOSD2VEmode(void *pInstance, EN_VOP_SEL_OSD_XC2VE_MUX eVOPSelOSD_MUX)
8192 {
8193 Hal_SC_Set_OSD2VE(pInstance, eVOPSelOSD_MUX);
8194 }
8195
MDrv_XC_Check_HNonLinearScaling(void * pInstance)8196 MS_BOOL MDrv_XC_Check_HNonLinearScaling(void* pInstance)
8197 {
8198 return Hal_SC_Check_HNonLinearScaling(pInstance);
8199 }
8200
MApi_XC_Check_HNonLinearScaling_U2(void * pInstance)8201 MS_BOOL MApi_XC_Check_HNonLinearScaling_U2(void* pInstance)
8202 {
8203 MS_BOOL bRet;
8204 _XC_ENTRY(pInstance);
8205 bRet = MDrv_XC_Check_HNonLinearScaling(pInstance);
8206 _XC_RETURN(pInstance);
8207 return bRet;
8208 }
8209
MApi_XC_Check_HNonLinearScaling(void)8210 MS_BOOL MApi_XC_Check_HNonLinearScaling(void)
8211 {
8212 if (pu32XCInst == NULL)
8213 {
8214 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
8215 return FALSE;
8216 }
8217
8218 stXC_CHECK_H_NONLINEAR_SCALING XCArgs;
8219 XCArgs.bReturnValue = FALSE;
8220
8221 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_CHECK_H_NONLINEAR_SCALING, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
8222 {
8223 printf("Obtain XC engine fail\n");
8224 return FALSE;
8225 }
8226 else
8227 {
8228 return XCArgs.bReturnValue;
8229 }
8230 }
8231
MApi_XC_Set_Extra_fetch_adv_line_U2(void * pInstance,MS_U8 u8val)8232 void MApi_XC_Set_Extra_fetch_adv_line_U2(void* pInstance, MS_U8 u8val)
8233 {
8234 _XC_ENTRY(pInstance);
8235 Hal_SC_Set_extra_fetch_line(pInstance, u8val & 0x0F);
8236 Hal_SC_Set_extra_adv_line(pInstance, u8val>>4);
8237 _XC_RETURN(pInstance);
8238 }
8239
MApi_XC_Set_Extra_fetch_adv_line(MS_U8 u8val)8240 void MApi_XC_Set_Extra_fetch_adv_line(MS_U8 u8val)
8241 {
8242 if (pu32XCInst == NULL)
8243 {
8244 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
8245 return;
8246 }
8247
8248 stXC_SET_EXTRA_FETCH_ADV_LINE XCArgs;
8249 XCArgs.u8val = u8val;
8250
8251 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_EXTRA_FETCH_ADV_LINE, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
8252 {
8253 printf("Obtain XC engine fail\n");
8254 return;
8255 }
8256 else
8257 {
8258 return;
8259 }
8260 }
8261
8262 //-------------------------------------------------------------------------------------------------
8263 /// Enable FPLL related settings not by program but by user's setting from TV tool
8264 /// Including PhaseLimit, limitD5D6D7_RK
8265 /// @param bEnable @ref MS_BOOL \b IN: enable or not
8266 //-------------------------------------------------------------------------------------------------
MApi_XC_EnableFpllManualSetting_U2(void * pInstance,MS_BOOL bEnable)8267 void MApi_XC_EnableFpllManualSetting_U2(void* pInstance, MS_BOOL bEnable)
8268 {
8269 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8270 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8271 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8272 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
8273 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8274 pXCResourcePrivate->stdrvXC_MVideo._SContext.bEnableFPLLManualDebug = bEnable;
8275 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
8276 }
8277
MApi_XC_EnableFpllManualSetting(MS_BOOL bEnable)8278 void MApi_XC_EnableFpllManualSetting(MS_BOOL bEnable)
8279 {
8280 if (pu32XCInst == NULL)
8281 {
8282 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
8283 return;
8284 }
8285
8286 stXC_SET_FPLL_MANUAL_SETTING_ENABLE XCArgs;
8287 XCArgs.bEnable = bEnable;
8288
8289 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_FPLL_MANUAL_SETTING_ENABLE, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
8290 {
8291 printf("Obtain XC engine fail\n");
8292 return;
8293 }
8294 else
8295 {
8296 return;
8297 }
8298 }
8299
8300 //--------------------------------------------------------------------------------------------------------------------
8301 /// Test if panel output is ok by changing output DClk, this is to test max range that FPLL can do
8302 /// @param u32FpllSetOffset @ref MS_U32 \b IN: the offset to be add/minus the typical DClk output, unit is SET
8303 /// @param u16TestCnt @ref MS_U16 \b IN: the times to do boundary test
8304 //--------------------------------------------------------------------------------------------------------------------
MApi_XC_FpllBoundaryTest_U2(void * pInstance,MS_U32 u32FpllSetOffset,MS_U16 u16TestCnt)8305 void MApi_XC_FpllBoundaryTest_U2(void* pInstance, MS_U32 u32FpllSetOffset, MS_U16 u16TestCnt)
8306 {
8307 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8308 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8309 MS_U16 i;
8310 MS_U32 u32OrigFpllSet;
8311
8312 if(0)//(psXCInstPri->u32DeviceID > E_XC_DEVICE0)
8313 {
8314 printf("[%s] Not support FPLL for device id %td\n",__FUNCTION__,(ptrdiff_t)psXCInstPri->u32DeviceID);
8315 printf("MApi_XC_EX_EnableFpllBoundaryTest() -> Not support FPLL for device id %td\n",(ptrdiff_t)psXCInstPri->u32DeviceID);
8316 return;
8317 }
8318
8319 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8320 // set to free run
8321 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
8322 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8323 _XC_ENTRY(pInstance);
8324 MDrv_XC_SetFreeRunTiming(pInstance);
8325 _XC_RETURN(pInstance);
8326
8327 // set to default output DClk
8328 printf("MApi_XC_EnableFpllBoundaryTest(0x%tx, %d)\n", (ptrdiff_t)u32FpllSetOffset, u16TestCnt);
8329 printf("MApi_XC_EnableFpllBoundaryTest() -> Default DClk = %d x %d x %d = %td\n",
8330 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultHTotal,
8331 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVTotal,
8332 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq,
8333 (ptrdiff_t)(MDrv_PNL_CalculateLPLLSETbyDClk(pInstance, (MS_U64)
8334 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultHTotal*
8335 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVTotal*
8336 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq, FALSE))
8337 );
8338
8339 MDrv_SC_set_output_dclk(pInstance, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultHTotal,
8340 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVTotal,
8341 pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq, 0, MAIN_WINDOW);
8342 LPLL_BK_STORE;
8343 LPLL_BK_SWITCH(0x00);
8344 u32OrigFpllSet = MDrv_Read4Byte(L_BK_LPLL(0x0F));
8345
8346 printf("MApi_XC_EnableFpllBoundaryTest(): std set = 0x%tx\n", (ptrdiff_t)u32OrigFpllSet);
8347
8348 // do FpllBoundary testst
8349 for(i=0; i<u16TestCnt; i++)
8350 {
8351 MDrv_Write3Byte(L_BK_LPLL(0x0F), u32OrigFpllSet + u32FpllSetOffset);
8352 MsOS_DelayTask(2);
8353 MDrv_Write3Byte(L_BK_LPLL(0x0F), u32OrigFpllSet - u32FpllSetOffset);
8354 MsOS_DelayTask(2);
8355 }
8356 LPLL_BK_RESTORE;
8357 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
8358 }
8359
MApi_XC_FpllBoundaryTest(MS_U32 u32FpllSetOffset,MS_U16 u16TestCnt)8360 void MApi_XC_FpllBoundaryTest(MS_U32 u32FpllSetOffset, MS_U16 u16TestCnt)
8361 {
8362 if (pu32XCInst == NULL)
8363 {
8364 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
8365 return;
8366 }
8367
8368 stXC_SET_FPLL_BOUNDARY_TEST XCArgs;
8369 XCArgs.u32FpllSetOffset = u32FpllSetOffset;
8370 XCArgs.u16TestCnt = u16TestCnt;
8371
8372 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_FPLL_BOUNDARY_TEST, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
8373 {
8374 printf("Obtain XC engine fail\n");
8375 return;
8376 }
8377 else
8378 {
8379 return;
8380 }
8381 }
8382
MApi_XC_SkipOPWriteOffInSetWindow_U2(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)8383 void MApi_XC_SkipOPWriteOffInSetWindow_U2(void* pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
8384 {
8385 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8386 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8387 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8388 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
8389 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8390 pXCResourcePrivate->stdrvXC_Display._abSkipOPWOffInSetWindow[eWindow] = bEnable;
8391 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
8392 }
8393
MApi_XC_SkipOPWriteOffInSetWindow(MS_BOOL bEnable,SCALER_WIN eWindow)8394 void MApi_XC_SkipOPWriteOffInSetWindow(MS_BOOL bEnable, SCALER_WIN eWindow)
8395 {
8396 if (pu32XCInst == NULL)
8397 {
8398 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
8399 return;
8400 }
8401
8402 stXC_SET_SKIP_OPWRITEOFF_IN_SETWINDOW XCArgs;
8403 XCArgs.bEnable = bEnable;
8404 XCArgs.eWindow = eWindow;
8405
8406 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_SKIP_OPWRITEOFF_IN_SETWINDOW, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
8407 {
8408 printf("Obtain XC engine fail\n");
8409 return;
8410 }
8411 else
8412 {
8413 return;
8414 }
8415 }
8416
MDrv_XC_GetSkipOPWriteOffInSetWindow(void * pInstance,SCALER_WIN eWindow)8417 MS_BOOL MDrv_XC_GetSkipOPWriteOffInSetWindow(void *pInstance, SCALER_WIN eWindow)
8418 {
8419 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8420 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8421 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8422 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8423 return pXCResourcePrivate->stdrvXC_Display._abSkipOPWOffInSetWindow[eWindow];
8424 }
8425
MApi_XC_GetSkipOPWriteOffInSetWindow_U2(void * pInstance,SCALER_WIN eWindow)8426 MS_BOOL MApi_XC_GetSkipOPWriteOffInSetWindow_U2(void* pInstance, SCALER_WIN eWindow)
8427 {
8428 MS_BOOL bReturn = FALSE;
8429 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8430 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8431 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
8432 bReturn = MDrv_XC_GetSkipOPWriteOffInSetWindow(pInstance, eWindow);
8433 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
8434 return bReturn;
8435 }
8436
MApi_XC_GetSkipOPWriteOffInSetWindow(SCALER_WIN eWindow)8437 MS_BOOL MApi_XC_GetSkipOPWriteOffInSetWindow(SCALER_WIN eWindow)
8438 {
8439 if (pu32XCInst == NULL)
8440 {
8441 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
8442 return FALSE;
8443 }
8444
8445 stXC_GET_SKIP_OPWRITEOFF_IN_SETWINDOW XCArgs;
8446 XCArgs.eWindow = eWindow;
8447 XCArgs.bReturnValue = FALSE;
8448
8449 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_GET_SKIP_OPWRITEOFF_IN_SETWINDOW, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
8450 {
8451 printf("Obtain XC engine fail\n");
8452 return FALSE;
8453 }
8454 else
8455 {
8456 return XCArgs.bReturnValue;
8457 }
8458 }
8459
MDrv_XC_SetSkipDisableOPWriteOffInFPLL(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)8460 void MDrv_XC_SetSkipDisableOPWriteOffInFPLL(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
8461 {
8462 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8463 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8464 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8465 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8466 pXCResourcePrivate->stdrvXC_Display._bSkipDisableOPWriteOffInFPLL[eWindow] = bEnable;
8467 }
8468
MApi_XC_SetSkipDisableOPWriteOffInFPLL_U2(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)8469 void MApi_XC_SetSkipDisableOPWriteOffInFPLL_U2(void* pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
8470 {
8471 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8472 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8473 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
8474 MDrv_XC_SetSkipDisableOPWriteOffInFPLL(pInstance, bEnable, eWindow);
8475 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
8476 }
8477
MApi_XC_SetSkipDisableOPWriteOffInFPLL(MS_BOOL bEnable,SCALER_WIN eWindow)8478 void MApi_XC_SetSkipDisableOPWriteOffInFPLL(MS_BOOL bEnable, SCALER_WIN eWindow)
8479 {
8480 if (pu32XCInst == NULL)
8481 {
8482 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
8483 return;
8484 }
8485
8486 stXC_SET_SKIP_DISABLE_OPWRITEOFF_IN_FPLL XCArgs;
8487 XCArgs.bEnable = FALSE;
8488 XCArgs.eWindow = eWindow;
8489
8490 if(UtopiaIoctl(pu32XCInst, E_XC_SET_SKIP_DISABLE_OPWRITEOFF_IN_FPLL, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
8491 {
8492 printf("Obtain XC engine fail\n");
8493 return;
8494 }
8495 else
8496 {
8497 return;
8498 }
8499 }
8500
MApi_XC_Set_OPWriteOffEnable_U2(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)8501 void MApi_XC_Set_OPWriteOffEnable_U2(void* pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
8502 {
8503 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8504 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8505 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8506
8507 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
8508 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8509 pXCResourcePrivate->stdrvXC_Display._bEnableMCNR[eWindow] = !bEnable;
8510 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
8511 }
8512
MApi_XC_Set_OPWriteOffEnable(MS_BOOL bEnable,SCALER_WIN eWindow)8513 void MApi_XC_Set_OPWriteOffEnable(MS_BOOL bEnable, SCALER_WIN eWindow)
8514 {
8515 if (pu32XCInst == NULL)
8516 {
8517 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
8518 return;
8519 }
8520
8521 stXC_SET_OPWRITEOFF_ENABLE XCArgs;
8522 XCArgs.bEnable = bEnable;
8523 XCArgs.eWindow = eWindow;
8524
8525 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_OPWRITEOFF_ENABLE, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
8526 {
8527 printf("Obtain XC engine fail\n");
8528 return;
8529 }
8530 else
8531 {
8532 return;
8533 }
8534 }
8535
MApi_XC_Set_OPWriteOffEnableToReg_U2(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)8536 void MApi_XC_Set_OPWriteOffEnableToReg_U2(void* pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
8537 {
8538 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8539 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8540 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8541
8542 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
8543 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8544 pXCResourcePrivate->stdrvXC_Display._bEnableMCNR[eWindow] = !bEnable;
8545 if(!pXCResourcePrivate->stdrvXC_Display._bForceDisableMCNR)
8546 {
8547 _XC_ENTRY(pInstance);
8548 Hal_SC_SetOPWriteOff(pInstance, bEnable);
8549 _XC_RETURN(pInstance);
8550 }
8551 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
8552 }
8553
MApi_XC_Set_OPWriteOffEnableToReg(MS_BOOL bEnable,SCALER_WIN eWindow)8554 void MApi_XC_Set_OPWriteOffEnableToReg(MS_BOOL bEnable, SCALER_WIN eWindow)
8555 {
8556 if (pu32XCInst == NULL)
8557 {
8558 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
8559 return;
8560 }
8561
8562 stXC_SET_OPWRITEOFF_ENABLE_TO_REG XCArgs;
8563 XCArgs.bEnable = bEnable;
8564 XCArgs.eWindow = eWindow;
8565
8566 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_OPWRITEOFF_ENABLE_TO_REG, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
8567 {
8568 printf("Obtain XC engine fail\n");
8569 return;
8570 }
8571 else
8572 {
8573 return;
8574 }
8575 }
8576
MApi_XC_ReLoad_OPWriteOff(void * pInstance)8577 void MApi_XC_ReLoad_OPWriteOff(void *pInstance)
8578 {
8579 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8580 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8581 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8582 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8583 pXCResourcePrivate->stdrvXC_Display._bNeedReloadMCNR = TRUE;
8584 }
8585
8586
8587 // If this function is called, driver will set OPW immediatly.
MApi_XC_ForceSet_OPWriteOffEnable_U2(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)8588 void MApi_XC_ForceSet_OPWriteOffEnable_U2(void* pInstance, MS_BOOL bEnable ,SCALER_WIN eWindow)
8589 {
8590 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8591 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8592 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8593
8594 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
8595 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8596 if (eWindow == MAIN_WINDOW )
8597 {
8598 if (bEnable)
8599 {
8600 _XC_ENTRY(pInstance);
8601 Hal_SC_SetOPWriteOff(pInstance, TRUE);
8602 _XC_RETURN(pInstance);
8603 pXCResourcePrivate->stdrvXC_Display._bForceDisableMCNR = TRUE;
8604 }
8605 else
8606 {
8607 pXCResourcePrivate->stdrvXC_Display._bForceDisableMCNR = FALSE;
8608 }
8609 }
8610 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
8611 }
8612
MApi_XC_ForceSet_OPWriteOffEnable(MS_BOOL bEnable,SCALER_WIN eWindow)8613 void MApi_XC_ForceSet_OPWriteOffEnable(MS_BOOL bEnable ,SCALER_WIN eWindow)
8614 {
8615 if (pu32XCInst == NULL)
8616 {
8617 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
8618 return;
8619 }
8620
8621 stXC_FORCESET_OPWRITEOFF_ENABLE XCArgs;
8622 XCArgs.bEnable = bEnable;
8623 XCArgs.eWindow = eWindow;
8624
8625 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_FORCESET_OPWRITEOFF_ENABLE, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
8626 {
8627 printf("Obtain XC engine fail\n");
8628 return;
8629 }
8630 else
8631 {
8632 return;
8633 }
8634 }
8635
MDrv_XC_Get_OPWriteOffEnable(void * pInstance,SCALER_WIN eWindow)8636 MS_BOOL MDrv_XC_Get_OPWriteOffEnable(void *pInstance, SCALER_WIN eWindow)
8637 {
8638 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8639 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8640 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8641 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8642 return !pXCResourcePrivate->stdrvXC_Display._bEnableMCNR[eWindow];
8643 }
8644
MApi_XC_Get_OPWriteOffEnable_U2(void * pInstance,SCALER_WIN eWindow)8645 MS_BOOL MApi_XC_Get_OPWriteOffEnable_U2(void* pInstance, SCALER_WIN eWindow)
8646 {
8647 MS_BOOL bReturn = FALSE;
8648 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8649 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8650 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
8651 bReturn = MDrv_XC_Get_OPWriteOffEnable(pInstance, eWindow);
8652 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
8653 return bReturn;
8654 }
8655
MApi_XC_Get_OPWriteOffEnable(SCALER_WIN eWindow)8656 MS_BOOL MApi_XC_Get_OPWriteOffEnable(SCALER_WIN eWindow)
8657 {
8658 if (pu32XCInst == NULL)
8659 {
8660 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
8661 return FALSE;
8662 }
8663
8664 stXC_GET_OPWRITEOFF_ENABLE XCArgs;
8665 XCArgs.eWindow = eWindow;
8666 XCArgs.bReturnValue = FALSE;
8667
8668 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_GET_OPWRITEOFF_ENABLE, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
8669 {
8670 printf("Obtain XC engine fail\n");
8671 return FALSE;
8672 }
8673 else
8674 {
8675 return XCArgs.bReturnValue;
8676 }
8677 }
8678
8679 //-------------------------------------------------------------------------------------------------
8680 // This function will store the H or V sync information(SyncStart/end/width) of panel default for XC to use
8681 // Because their is no other place to get them in XC Lib source code
8682 // IN:
8683 // NONE
8684 // Return:
8685 // NONE
8686 //-------------------------------------------------------------------------------------------------
MDrv_XC_GetDefaultHVSyncInfo(void * pInstance)8687 void MDrv_XC_GetDefaultHVSyncInfo(void *pInstance)
8688 {
8689 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8690 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8691 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8692 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8693 //Note: H/V Total, H/V DE End, H/V Syncwidth all need minus 1 when set to register
8694 pXCResourcePrivate->stdrvXC_Display._u16DefaultHSyncWidth = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_01_L, 0xFF) + 1; //HsyncWidth= reg + 1
8695 pXCResourcePrivate->stdrvXC_Display._u16DefaultHSyncBackPorch = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_04_L, VOP_DE_HSTART_MASK) - pXCResourcePrivate->stdrvXC_Display._u16DefaultHSyncWidth;
8696 pXCResourcePrivate->stdrvXC_Display._u16DefaultVSyncWidth = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_03_L, VOP_VSYNC_END_MASK) - ((SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_02_L, 0x1000) >> 1) + SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_02_L, 0x7FF)) + 1;
8697 #if defined(PATCH_HW_VTT_LIMITATION)
8698 if(MDrv_ReadByte(REG_CHIP_REVISION) < HW_VTT_LIMITATION_CHIPREV)
8699 {
8700 pXCResourcePrivate->stdrvXC_Display._u16DefaultVSyncBackPorch = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK68_36_L, VOP_VTT_MASK) - SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_03_L, VOP_VSYNC_END_MASK); //V backPorch= VTT+1-(VsyncEnd+1)
8701 }
8702 else
8703 #endif
8704 {
8705 pXCResourcePrivate->stdrvXC_Display._u16DefaultVSyncBackPorch = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_0D_L, VOP_VTT_MASK) - SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_03_L, VOP_VSYNC_END_MASK); //V backPorch= VTT+1-(VsyncEnd+1)
8706 }
8707 if(SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_10_L) & BIT(15)) //If manual Vsync mode, keep SyncWidth/back porch unchanged when vtt changes
8708 {
8709 pXCResourcePrivate->stdrvXC_Display._bHSyncChanged = TRUE;
8710 pXCResourcePrivate->stdrvXC_Display._bVSyncChanged = TRUE;
8711 }
8712 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "SyncWidth/back porch: V=%u,%u,H=%u,%u\n"
8713 , pXCResourcePrivate->stdrvXC_Display._u16DefaultVSyncWidth
8714 , pXCResourcePrivate->stdrvXC_Display._u16DefaultVSyncBackPorch
8715 , pXCResourcePrivate->stdrvXC_Display._u16DefaultHSyncWidth
8716 , pXCResourcePrivate->stdrvXC_Display._u16DefaultHSyncBackPorch)
8717 }
8718
8719 ///For K1 OSD Layer Switch
MDrv_XC_SetOSDLayer(void * pInstance,E_VOP_OSD_LAYER_SEL eVOPOSDLayer,SCALER_WIN eWindow)8720 E_APIXC_ReturnValue MDrv_XC_SetOSDLayer(void *pInstance, E_VOP_OSD_LAYER_SEL eVOPOSDLayer, SCALER_WIN eWindow)
8721 {
8722 #if (VIDEO_OSD_SWITCH_VER >= 2) // clippers/kano mode
8723 MS_U16 u16RegVal = 0;
8724 switch (eVOPOSDLayer)
8725 {
8726 case E_VOP_LAYER_VIDEO_MUX1_MUX2: // E_VOP_LAYER_VIDEO_MUX1_MUX2_MUX3_MUX4
8727 case E_VOP_LAYER_FRAME_VIDEO_MUX1_MUX2:
8728 case E_VOP_LAYER_FRAME_VIDEO_MUX2_MUX1:
8729 u16RegVal = 0;
8730 break;
8731 case E_VOP_LAYER_FRAME_VIDEO_MUX1_MUX2_MUX3_MUX4:
8732 u16RegVal = 1;
8733 break;
8734 case E_VOP_LAYER_FRAME_MUX2_VIDEO_MUX1:
8735 case E_VOP_LAYER_FRAME_MUX1_VIDEO_MUX2: // E_VOP_LAYER_FRAME_MUX1_VIDEO_MUX2_MUX3_MUX4
8736 u16RegVal = 2;
8737 break;
8738 case E_VOP_LAYER_FRAME_MUX1_MUX2_VIDEO: // E_VOP_LAYER_FRAME_MUX1_MUX2_VIDEO_MUX3_MUX4
8739 case E_VOP_LAYER_FRAME_MUX2_MUX1_VIDEO:
8740 u16RegVal = 3;
8741 break;
8742 case E_VOP_LAYER_FRAME_MUX1_MUX2_MUX3_VIDEO_MUX4:
8743 u16RegVal = 4;
8744 break;
8745 case E_VOP_LAYER_FRAME_MUX1_MUX2_MUX3_MUX4_VIDEO:
8746 u16RegVal = 5;
8747 break;
8748 default:
8749 printf("[%s]Unsupport layer Setting %u, it can't be return by this interface.\n",__FUNCTION__,eVOPOSDLayer);
8750 return E_APIXC_RET_FAIL_INVALID_PARAMETER;
8751 }
8752 #if (VIDEO_OSD_SWITCH_VER == 3)
8753 MS_BOOL bCtrlByGop = (SC_R2BYTEMSK(0, REG_SC_BK2F_36_L, BIT(5))) == BIT(5);
8754 if (bCtrlByGop)
8755 {
8756 Hal_SC_Set_OSDLayer(pInstance, u16RegVal, eWindow);
8757 }
8758 else
8759 #endif
8760 {
8761 SC_W2BYTEMSK(0, REG_SC_BK2F_36_L, u16RegVal, BITMASK(2:0));
8762 }
8763 return E_APIXC_RET_OK;
8764 #else
8765 return Hal_SC_Set_OSDLayer(pInstance, eVOPOSDLayer, eWindow);
8766 #endif
8767 }
8768
MDrv_XC_GetOSDLayer(void * pInstance,SCALER_WIN eWindow)8769 E_VOP_OSD_LAYER_SEL MDrv_XC_GetOSDLayer(void *pInstance, SCALER_WIN eWindow)
8770 {
8771 #if (VIDEO_OSD_SWITCH_VER >= 2) // clippers/kano mode
8772 MS_U16 u16RegVal = 0;
8773 #if (VIDEO_OSD_SWITCH_VER == 3)
8774 MS_BOOL bCtrlByGop = (SC_R2BYTEMSK(0, REG_SC_BK2F_36_L, BIT(5))) == BIT(5);
8775 if (bCtrlByGop)
8776 {
8777 u16RegVal = GOP_R2BYTEMSK(_PK_L_(0x0,0x6A), 0x0007);
8778 }
8779 else
8780 #endif
8781 {
8782 u16RegVal = SC_R2BYTEMSK(0, REG_SC_BK2F_36_L, BITMASK(2:0));
8783 }
8784 E_VOP_OSD_LAYER_SEL enStbLayer = E_VOP_LAYER_RESERVED;
8785 switch (u16RegVal)
8786 {
8787 case 0:
8788 enStbLayer = E_VOP_LAYER_VIDEO_MUX1_MUX2;
8789 break;
8790 case 1:
8791 enStbLayer = E_VOP_LAYER_FRAME_VIDEO_MUX1_MUX2;
8792 break;
8793 case 2:
8794 enStbLayer = E_VOP_LAYER_FRAME_MUX1_VIDEO_MUX2;
8795 break;
8796 case 3:
8797 case 4:
8798 case 5:
8799 enStbLayer = E_VOP_LAYER_FRAME_MUX1_MUX2_VIDEO;
8800 break;
8801 default:
8802 printf("[%s]found wrong layer Setting %u, it can't be return by this interface.\n",__FUNCTION__,u16RegVal);
8803 enStbLayer = E_VOP_LAYER_RESERVED;
8804 break;
8805 }
8806 return enStbLayer;
8807 #else
8808 return Hal_SC_Get_OSDLayer(pInstance, eWindow);
8809 #endif
8810 }
8811
MDrv_XC_SetVideoAlpha(void * pInstance,MS_U8 u8Val,SCALER_WIN eWindow)8812 E_APIXC_ReturnValue MDrv_XC_SetVideoAlpha(void *pInstance, MS_U8 u8Val, SCALER_WIN eWindow)
8813 {
8814 return Hal_SC_Set_VideoAlpha(pInstance, u8Val, eWindow);
8815 }
8816
MDrv_XC_GetVideoAlpha(void * pInstance,MS_U8 * pu8Val,SCALER_WIN eWindow)8817 E_APIXC_ReturnValue MDrv_XC_GetVideoAlpha(void *pInstance, MS_U8 *pu8Val, SCALER_WIN eWindow)
8818 {
8819 return Hal_SC_Get_VideoAlpha(pInstance, pu8Val, eWindow);
8820 }
8821
MDrv_SC_ShiftDisplayWindowDirectly(void * pInstance,MS_S8 s8H,MS_S8 s8V,MS_S8 s8preH,MS_S8 s8preV)8822 E_APIXC_ReturnValue MDrv_SC_ShiftDisplayWindowDirectly(void *pInstance, MS_S8 s8H, MS_S8 s8V, MS_S8 s8preH, MS_S8 s8preV)
8823 {
8824 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8825 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8826 MS_WINDOW_TYPE dsp_main, dsp_sub;
8827 MS_S8 s8dH = s8H - s8preH, s8dV = s8V - s8preV;
8828 MS_U16 u16Data_OSD_hs_st=0, u16Data_OSD_hs_end=0;
8829 MS_U16 u16Data_OSD_vfde_st=0, u16Data_OSD_vfde_end=0;
8830 MS_U8 u8OSD_vdelay = 0;
8831 MS_WINDOW_TYPE RepWindow;
8832 MS_WINDOW_TYPE OSDWindow;
8833 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8834 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8835 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
8836 if (IsFSCDisplayWindowEnable())
8837 {
8838 if((pXCResourcePrivate->stdrvXC_MVideo.gePixelShiftFeature & PIXEL_SHIFT_DO_OVERSCAN) == PIXEL_SHIFT_DO_OVERSCAN)
8839 {
8840 // just do overscan led display window bigger
8841 dsp_main.x = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK68_03_L) - pXCResourcePrivate->stdrvXC_MVideo.gu16HPixelShiftRange / 2;
8842 dsp_main.y = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK68_0B_L) - pXCResourcePrivate->stdrvXC_MVideo.gu16VPixelShiftRange / 2;
8843 }
8844 else
8845 {
8846 dsp_main.x = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK68_03_L);
8847 dsp_main.y = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK68_0B_L);
8848 }
8849 if(MHal_FRC_IsFHDToFSC(pInstance, MAIN_WINDOW))
8850 {
8851 if((pXCResourcePrivate->stdrvXC_MVideo.gePixelShiftFeature & PIXEL_SHIFT_DO_OVERSCAN) == PIXEL_SHIFT_DO_OVERSCAN)
8852 {
8853 //just do overscan led display window bigger
8854 dsp_main.width = (gSrcInfo[MAIN_WINDOW].stDispWin.width - pXCResourcePrivate->stdrvXC_MVideo.gu16HPixelShiftRange)/2 + pXCResourcePrivate->stdrvXC_MVideo.gu16HPixelShiftRange;
8855 dsp_main.height = (gSrcInfo[MAIN_WINDOW].stDispWin.height - pXCResourcePrivate->stdrvXC_MVideo.gu16VPixelShiftRange)/2 + pXCResourcePrivate->stdrvXC_MVideo.gu16VPixelShiftRange;
8856 }
8857 else
8858 {
8859 dsp_main.width = gSrcInfo[MAIN_WINDOW].stDispWin.width/2;
8860 dsp_main.height = gSrcInfo[MAIN_WINDOW].stDispWin.height/2;
8861 }
8862 }
8863 else//4K2k IN FSC
8864 {
8865 dsp_main.width = gSrcInfo[MAIN_WINDOW].stDispWin.width;
8866 dsp_main.height = gSrcInfo[MAIN_WINDOW].stDispWin.height;
8867 }
8868 }
8869 else
8870 #endif
8871 {
8872 memcpy(&dsp_main, &(gSrcInfo[MAIN_WINDOW].stDispWin), sizeof(MS_WINDOW_TYPE));
8873 }
8874 memcpy(&dsp_sub, &(gSrcInfo[SUB_WINDOW].stDispWin), sizeof(MS_WINDOW_TYPE));
8875 // BEWARE OF THE MIRROR CASE
8876
8877 // DISPLAY MAIN WINDOW is controlled here
8878 if ((pXCResourcePrivate->stdrvXC_MVideo.gePixelShiftFeature & PIXEL_SHIFT_MOVE_MAIN_WINDOW) == PIXEL_SHIFT_MOVE_MAIN_WINDOW)
8879 {
8880 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
8881 if (IsFSCDisplayWindowEnable())
8882 {
8883 // FSC 2p mode,so H just can move even
8884 s8H &= ~0x1;
8885 dsp_main.x += s8H;
8886 dsp_main.y += s8V;
8887 }
8888 else
8889 #endif
8890 {
8891 dsp_main.x += s8dH;
8892 dsp_main.y += s8dV;
8893 }
8894 }
8895 #if defined(XC_SUPPORT_2STEP_SCALING)
8896 //2stepscaling is 2p mode,H just can move even
8897 s8H &= ~0x1;
8898 #endif
8899 // DISPLAY SUB WINDOW is controlled here
8900 if ((pXCResourcePrivate->stdrvXC_MVideo.gePixelShiftFeature & PIXEL_SHIFT_MOVE_SUB_WINDOW) == PIXEL_SHIFT_MOVE_SUB_WINDOW)
8901 {
8902 dsp_sub.x += s8dH;
8903 dsp_sub.y += s8dV;
8904 }
8905
8906 // REPORT WINDOW is controlled here
8907 if ((pXCResourcePrivate->stdrvXC_MVideo.gePixelShiftFeature & PIXEL_SHIFT_MOVE_REPORT_WINDOW) == PIXEL_SHIFT_MOVE_REPORT_WINDOW)
8908 {
8909 RepWindow.x = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HStart+ s8H;
8910 RepWindow.width = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width;
8911 RepWindow.y = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart+ s8V;
8912 RepWindow.height = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height;
8913 }
8914
8915 // OSD LAYER is controlled here
8916 if ((pXCResourcePrivate->stdrvXC_MVideo.gePixelShiftFeature & PIXEL_SHIFT_MOVE_OSD_LAYER) == PIXEL_SHIFT_MOVE_OSD_LAYER)
8917 {
8918 if((s8H == 0) && (s8V == 0))
8919 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK2D_10_L, 0, BIT(15));
8920 else
8921 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK2D_10_L, BIT(15), BIT(15));
8922
8923 if (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK2D_10_L, BIT(15)))
8924 {
8925 if (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK19_10_L, BIT(7)))
8926 u8OSD_vdelay +=2;
8927
8928 if (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK18_75_L, BIT(0)))
8929 u8OSD_vdelay +=1;
8930
8931 u16Data_OSD_vfde_st = pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VStart + s8V + u8OSD_vdelay;
8932 u16Data_OSD_vfde_end = u16Data_OSD_vfde_st + pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height;
8933
8934 if( (-1 <= s8H) && (s8H <= (pXCResourcePrivate->stdrvXC_MVideo.gu16HPixelShiftRange/2)) )
8935 {
8936 u16Data_OSD_hs_st = 0;
8937 u16Data_OSD_hs_end = 1 + s8H;
8938 }
8939 else if( (-(pXCResourcePrivate->stdrvXC_MVideo.gu16HPixelShiftRange/2) <= s8H) && (s8H <= -2) )
8940 {
8941 // REG_SC_BK10_0C_L: Expect H total - 1
8942 // REG_SC_BK10_0E_L: Real H total - 1
8943 MS_U16 u16HTotal = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0E_L) + 1;
8944 u16Data_OSD_hs_st = 1;
8945 u16Data_OSD_hs_end = u16HTotal + 1 + s8H;
8946 }
8947 else
8948 {
8949 u16Data_OSD_hs_st = 0;
8950 u16Data_OSD_hs_end = 1;
8951 }
8952 OSDWindow.x = u16Data_OSD_hs_st;
8953 OSDWindow.y = u16Data_OSD_vfde_st;
8954 OSDWindow.width = u16Data_OSD_hs_end + 1 - u16Data_OSD_hs_st;
8955 OSDWindow.width = u16Data_OSD_vfde_end + 1 - u16Data_OSD_vfde_st;
8956 }
8957 }
8958
8959
8960 // finally we can update windows we want.
8961 MDrv_XC_UpdateWindow(pInstance,
8962 NULL, // always don't change DE in pixel shift case
8963 (pXCResourcePrivate->stdrvXC_MVideo.gePixelShiftFeature & PIXEL_SHIFT_MOVE_MAIN_WINDOW) ? &dsp_main : NULL,
8964 (pXCResourcePrivate->stdrvXC_MVideo.gePixelShiftFeature & PIXEL_SHIFT_MOVE_SUB_WINDOW) ? &dsp_sub : NULL,
8965 (pXCResourcePrivate->stdrvXC_MVideo.gePixelShiftFeature & PIXEL_SHIFT_MOVE_REPORT_WINDOW) ? &RepWindow : NULL,
8966 (pXCResourcePrivate->stdrvXC_MVideo.gePixelShiftFeature & PIXEL_SHIFT_MOVE_OSD_LAYER) ? &OSDWindow : NULL);
8967
8968 return E_APIXC_RET_OK;
8969 }
8970
MDrv_XC_Combine_MLoadEn(void * pInstance,MS_BOOL bEn)8971 E_APIXC_ReturnValue MDrv_XC_Combine_MLoadEn(void *pInstance, MS_BOOL bEn)
8972 {
8973
8974 if(bEn == FALSE)
8975 {
8976 if(_u16ZorderMLoadCmdCnt)
8977 {
8978 MApi_XC_MLoad_WriteCmds_And_Fire_U2(pInstance,
8979 &_u32ZorderMLoadCmd[0], &_u16ZorderMLoadVal[0], &_u16ZorderMLoadMsk[0], _u16ZorderMLoadCmdCnt);
8980 _u16ZorderMLoadCmdCnt = 0;
8981 }
8982 }
8983 _bZorderMLoadEn = bEn;
8984 return E_APIXC_RET_OK;
8985 }
8986
8987 #ifdef UFO_XC_ZORDER
MDrv_SC_GetVideoOnOSD(void * pInstance,E_VIDEO_ON_OSD_LAYER * penLayer,SCALER_WIN eWindow)8988 E_APIXC_ReturnValue MDrv_SC_GetVideoOnOSD(void *pInstance, E_VIDEO_ON_OSD_LAYER *penLayer, SCALER_WIN eWindow)
8989 {
8990 if(MDrv_SYS_GetChipType() == E_SYS_CHIP_TV) // TV zorder
8991 {
8992 #if (VIDEO_OSD_SWITCH_VER > 0)
8993 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8994 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8995 MS_U8 u8Layer = 0;
8996 MS_U8 u8Alpha = 0;
8997 MS_BOOL bEnable = FALSE;
8998 MS_U32 u32Addr[] = {REG_SC_BK10_6B_L, REG_SC_BK10_60_L,
8999 REG_SC_BK10_61_L, REG_SC_BK10_62_L,
9000 REG_SC_BK10_1B_L};
9001 MS_U16 u16BlendingModeMask[] = {BIT(5)|BIT(4), BIT(7)|BIT(6),
9002 BIT(9)|BIT(8), BIT(13)|BIT(12),
9003 BIT(15)|BIT(14)};
9004 #if (VIDEO_OSD_SWITCH_VER < 2) // unsupport sub blending
9005 if ((eWindow == SUB_WINDOW) || (psXCInstPri->u32DeviceID == 1))
9006 {
9007 // do nothing
9008 printf("[GetVideoOnOSD] Not support sub window on this chip \n");
9009 return E_APIXC_RET_FAIL_FUN_NOT_SUPPORT;
9010 }
9011 #endif
9012
9013 for (u8Layer = 0; u8Layer < OSD_LAYER_NUM; u8Layer++)
9014 {
9015 if ((MAIN_WINDOW == eWindow) && (psXCInstPri->u32DeviceID == 0))
9016 {
9017 #if (VIDEO_OSD_SWITCH_VER < 2) // ver 1
9018 bEnable = SC_R2BYTEMSK(0, u32Addr[u8Layer], BIT(8)) == BIT(8);
9019 #elif (VIDEO_OSD_SWITCH_VER < 3) // ver 2
9020 bEnable = SC_R2BYTEMSK(0, u32Addr[u8Layer], BIT(8)|BIT(9)) == (BIT(8)|BIT(9));
9021 #endif
9022 }
9023 else
9024 {
9025 bEnable = SC_R2BYTEMSK(0, u32Addr[u8Layer], BIT(8)|BIT(10)) == (BIT(8)|BIT(10));
9026 }
9027 if (!bEnable)
9028 {
9029 break;
9030 }
9031 u8Alpha = SC_R2BYTEMSK(0, u32Addr[u8Layer], BITMASK(7:0));
9032 if ((SC_R2BYTE(0, REG_SC_BK10_23_L) & BIT(5)) || (SC_R2BYTE(0, REG_SC_BK10_1C_L) & BIT(u8Layer)))
9033 {
9034 u8Alpha = 0xFF - u8Alpha;
9035 }
9036 // check mode1. If on, alpha inverse
9037 if ((SC_R2BYTE(0, REG_SC_BK10_5B_L) & u16BlendingModeMask[u8Layer]) == u16BlendingModeMask[u8Layer])
9038 {
9039 u8Alpha = 0xFF - u8Alpha;
9040 }
9041 if (u8Alpha != 0)
9042 {
9043 break;
9044 }
9045 }
9046 *penLayer = (E_VIDEO_ON_OSD_LAYER)u8Layer;
9047 return E_APIXC_RET_OK;
9048 #else
9049 return E_APIXC_RET_FAIL_FUN_NOT_SUPPORT;
9050 #endif
9051 }
9052 else // STB zorder
9053 {
9054 MS_U16 u16RegVal = SC_R2BYTEMSK(0, REG_SC_BK2F_36_L, BITMASK(2:0));;
9055 if (eWindow == SUB_WINDOW)
9056 {
9057 // do nothing
9058 printf("[GetVideoOnOSD] Not support sub window on this chip \n");
9059 return E_APIXC_RET_FAIL_FUN_NOT_SUPPORT;
9060 }
9061 #if (VIDEO_OSD_SWITCH_VER == 1)
9062 E_VOP_OSD_LAYER_SEL enVopOsdLayer ;
9063 enVopOsdLayer = Hal_SC_Get_OSDLayer(pInstance, eWindow);
9064 switch (enVopOsdLayer)
9065 {
9066 case E_VOP_LAYER_VIDEO_MUX1_MUX2 :
9067 case E_VOP_LAYER_FRAME_VIDEO_MUX1_MUX2 :
9068 case E_VOP_LAYER_FRAME_VIDEO_MUX2_MUX1 :
9069 *penLayer = E_VIDEO_ON_OSD_LAYER_0;
9070 break;
9071 case E_VOP_LAYER_FRAME_MUX1_VIDEO_MUX2 :
9072 case E_VOP_LAYER_FRAME_MUX2_VIDEO_MUX1 :
9073 *penLayer = E_VIDEO_ON_OSD_LAYER_1;
9074 break;
9075 case E_VOP_LAYER_FRAME_MUX1_MUX2_VIDEO :
9076 case E_VOP_LAYER_FRAME_MUX2_MUX1_VIDEO :
9077 *penLayer = E_VIDEO_ON_OSD_LAYER_2;
9078 break;
9079 default:
9080 return E_APIXC_RET_FAIL_FUN_NOT_SUPPORT;
9081 }
9082 #endif
9083 #if(VIDEO_OSD_SWITCH_VER >= 2) // clippers mode
9084 switch (u16RegVal) // translate layer to register value
9085 {
9086 case 0x0:
9087 case 0x1:
9088 *penLayer = E_VIDEO_ON_OSD_LAYER_DEAFULT;
9089 break;
9090 case 0x2:
9091 *penLayer = E_VIDEO_ON_OSD_LAYER_0;
9092 break;
9093 case 0x3:
9094 *penLayer = E_VIDEO_ON_OSD_LAYER_1;
9095 break;
9096 case 0x4:
9097 *penLayer = E_VIDEO_ON_OSD_LAYER_2;
9098 break;
9099 case 0x5:
9100 *penLayer = E_VIDEO_ON_OSD_LAYER_3;
9101 break;
9102 default:
9103 return E_APIXC_RET_FAIL;
9104 break;
9105 }
9106 return E_APIXC_RET_OK;
9107 #else
9108 return E_APIXC_RET_FAIL_FUN_NOT_SUPPORT;
9109 #endif
9110 }
9111 }
9112 #endif
9113
MDrv_SC_SetVideoOnOSD(void * pInstance,E_VIDEO_ON_OSD_LAYER enlayer,SCALER_WIN eWindow)9114 E_APIXC_ReturnValue MDrv_SC_SetVideoOnOSD(void *pInstance, E_VIDEO_ON_OSD_LAYER enlayer, SCALER_WIN eWindow)
9115 {
9116 #if (VIDEO_OSD_SWITCH_VER > 0)
9117 if (MDrv_SYS_GetChipType() == E_SYS_CHIP_TV)
9118 {
9119 if ((enlayer >= E_VIDEO_ON_OSD_LAYER_NUM) || (eWindow >= MAX_WINDOW))
9120 {
9121 return E_APIXC_RET_FAIL;
9122 }
9123
9124 switch (enlayer) // enable bleanding layers
9125 {
9126 case E_VIDEO_ON_OSD_LAYER_4:
9127 MDrv_SC_SetOSDLayerAlpha(pInstance, 4, 0);
9128 MDrv_SC_SetOSDLayerBlending(pInstance, 4, TRUE, eWindow);
9129 case E_VIDEO_ON_OSD_LAYER_3:
9130 MDrv_SC_SetOSDLayerAlpha(pInstance, 3, 0);
9131 MDrv_SC_SetOSDLayerBlending(pInstance, 3, TRUE, eWindow);
9132 case E_VIDEO_ON_OSD_LAYER_2:
9133 MDrv_SC_SetOSDLayerAlpha(pInstance, 2, 0);
9134 MDrv_SC_SetOSDLayerBlending(pInstance, 2, TRUE, eWindow);
9135 case E_VIDEO_ON_OSD_LAYER_1:
9136 MDrv_SC_SetOSDLayerAlpha(pInstance, 1, 0);
9137 MDrv_SC_SetOSDLayerBlending(pInstance, 1, TRUE, eWindow);
9138 case E_VIDEO_ON_OSD_LAYER_0:
9139 MDrv_SC_SetOSDLayerAlpha(pInstance, 0, 0);
9140 MDrv_SC_SetOSDLayerBlending(pInstance, 0, TRUE, eWindow);
9141 default:
9142 break;
9143 }
9144 switch (enlayer) // disable bleanding layers
9145 {
9146 default:
9147 MDrv_SC_SetOSDLayerBlending(pInstance, 0, FALSE, eWindow);
9148 case E_VIDEO_ON_OSD_LAYER_0:
9149 MDrv_SC_SetOSDLayerBlending(pInstance, 1, FALSE, eWindow);
9150 case E_VIDEO_ON_OSD_LAYER_1:
9151 MDrv_SC_SetOSDLayerBlending(pInstance, 2, FALSE, eWindow);
9152 case E_VIDEO_ON_OSD_LAYER_2:
9153 MDrv_SC_SetOSDLayerBlending(pInstance, 3, FALSE, eWindow);
9154 case E_VIDEO_ON_OSD_LAYER_3:
9155 MDrv_SC_SetOSDLayerBlending(pInstance, 4, FALSE, eWindow);
9156 case E_VIDEO_ON_OSD_LAYER_4:
9157 break;
9158 }
9159 return E_APIXC_RET_OK;
9160 }
9161 else // BOX zorder
9162 {
9163 MS_U16 u16RegVal = 0;
9164 if ((enlayer >= E_VIDEO_ON_OSD_LAYER_NUM) || (eWindow >= MAX_WINDOW))
9165 {
9166 return E_APIXC_RET_FAIL_INVALID_PARAMETER;
9167 }
9168 if (eWindow == SUB_WINDOW)
9169 {
9170 // do nothing
9171 printf("[SetVideoOnOSD] Not support sub window on this chip \n");
9172 return E_APIXC_RET_FAIL_FUN_NOT_SUPPORT;
9173 }
9174 #if (VIDEO_OSD_SWITCH_VER == 1) // kaiser mode
9175 E_APIXC_ReturnValue eResult = E_APIXC_RET_FAIL;
9176 E_VOP_OSD_LAYER_SEL enVopOsdLayer = Hal_SC_Get_OSDLayer(pInstance, eWindow);
9177 if (enVopOsdLayer >= E_VOP_LAYER_RESERVED)
9178 {
9179 // do nothing
9180 printf("[%s] error layer id[%u]\n",__FUNCTION__,enVopOsdLayer);
9181 return E_APIXC_RET_FAIL;
9182 }
9183 MS_BOOL bMux1Top = (enVopOsdLayer == E_VOP_LAYER_FRAME_VIDEO_MUX2_MUX1)
9184 || (enVopOsdLayer == E_VOP_LAYER_FRAME_MUX2_VIDEO_MUX1)
9185 || (enVopOsdLayer == E_VOP_LAYER_FRAME_MUX2_MUX1_VIDEO);
9186 switch (enlayer) // translate layer to register value
9187 {
9188 case E_VIDEO_ON_OSD_LAYER_DEAFULT:
9189 if ((enVopOsdLayer == E_VOP_LAYER_VIDEO_MUX1_MUX2)
9190 || (enVopOsdLayer == E_VOP_LAYER_FRAME_VIDEO_MUX1_MUX2)
9191 || (enVopOsdLayer == E_VOP_LAYER_FRAME_VIDEO_MUX2_MUX1))
9192 {
9193 // do nothing, layer right
9194 }
9195 else
9196 {
9197 if (bMux1Top)
9198 {
9199 eResult = Hal_SC_Set_OSDLayer(pInstance, E_VOP_LAYER_FRAME_VIDEO_MUX2_MUX1, eWindow);
9200 }
9201 else
9202 {
9203 eResult = Hal_SC_Set_OSDLayer(pInstance, E_VOP_LAYER_FRAME_VIDEO_MUX1_MUX2, eWindow);
9204 }
9205 }
9206 break;
9207 case E_VIDEO_ON_OSD_LAYER_0:
9208 if ((enVopOsdLayer == E_VOP_LAYER_FRAME_MUX1_VIDEO_MUX2)
9209 || (enVopOsdLayer == E_VOP_LAYER_FRAME_MUX2_VIDEO_MUX1))
9210 {
9211 // do nothing, layer right
9212 }
9213 else
9214 {
9215 if (bMux1Top)
9216 {
9217 eResult = Hal_SC_Set_OSDLayer(pInstance, E_VOP_LAYER_FRAME_MUX2_VIDEO_MUX1, eWindow);
9218 }
9219 else
9220 {
9221 eResult = Hal_SC_Set_OSDLayer(pInstance, E_VOP_LAYER_FRAME_MUX1_VIDEO_MUX2, eWindow);
9222 }
9223 }
9224 break;
9225 case E_VIDEO_ON_OSD_LAYER_1:
9226 case E_VIDEO_ON_OSD_LAYER_2:
9227 case E_VIDEO_ON_OSD_LAYER_3:
9228 case E_VIDEO_ON_OSD_LAYER_4:
9229 default:
9230 if ((enVopOsdLayer == E_VOP_LAYER_FRAME_MUX1_MUX2_VIDEO)
9231 || (enVopOsdLayer == E_VOP_LAYER_FRAME_MUX2_MUX1_VIDEO))
9232 {
9233 // do nothing, layer right
9234 }
9235 else
9236 {
9237 if (bMux1Top)
9238 {
9239 eResult = Hal_SC_Set_OSDLayer(pInstance, E_VOP_LAYER_FRAME_MUX2_MUX1_VIDEO, eWindow);
9240 }
9241 else
9242 {
9243 eResult = Hal_SC_Set_OSDLayer(pInstance, E_VOP_LAYER_FRAME_MUX1_MUX2_VIDEO, eWindow);
9244 }
9245 }
9246 break;
9247 }
9248 return E_APIXC_RET_OK;
9249 #endif
9250 #if (VIDEO_OSD_SWITCH_VER >= 2) // clippers mode
9251 switch (enlayer) // translate layer to register value
9252 {
9253 case E_VIDEO_ON_OSD_LAYER_DEAFULT:
9254 u16RegVal = 0;
9255 break;
9256 case E_VIDEO_ON_OSD_LAYER_0:
9257 u16RegVal = 2; //FrameColor->GOP1->Video->GOP2->GOP3->GOP4
9258 break;
9259 case E_VIDEO_ON_OSD_LAYER_1:
9260 u16RegVal = 3; //FrameColor->GOP1->GOP2->Video->GOP3->GOP4
9261 break;
9262 case E_VIDEO_ON_OSD_LAYER_2:
9263 u16RegVal = 4; //FrameColor->GOP1->GOP2->GOP3->Video->GOP4
9264 break;
9265 case E_VIDEO_ON_OSD_LAYER_3:
9266 u16RegVal = 5; //FrameColor->GOP1->GOP2->GOP3->GOP4->Video
9267 break;
9268 case E_VIDEO_ON_OSD_LAYER_4:
9269 default:
9270 u16RegVal = 5; //FrameColor->GOP1->GOP2->GOP3->GOP4->Video
9271 break;
9272 }
9273 #if (VIDEO_OSD_SWITCH_VER == 3) // kano mode
9274 MS_BOOL bCtrlByGop = (SC_R2BYTEMSK(0, REG_SC_BK2F_36_L, BIT(5))) == BIT(5);
9275 if (bCtrlByGop)
9276 {
9277 GOP_W2BYTEMSK(_PK_L_(0x0,0x6B), 1<<13, 1<<13); //double buffer
9278 GOP_W2BYTEMSK(_PK_L_(0x0,0x6A), u16RegVal, 0x0007);
9279 GOP_W2BYTEMSK(_PK_L_(0x0,0x6B), 1<<15, 1<<15); //trigger
9280 }
9281 else
9282 #endif
9283 {
9284 SC_W2BYTEMSK(0, REG_SC_BK2F_36_L, u16RegVal, 0x7);
9285 }
9286 #else
9287 return E_APIXC_RET_FAIL_FUN_NOT_SUPPORT;
9288 #endif
9289 return E_APIXC_RET_OK;
9290 }
9291 #else
9292 return E_APIXC_RET_FAIL_FUN_NOT_SUPPORT;
9293 #endif
9294 return E_APIXC_RET_OK;
9295
9296 }
9297
MDrv_SC_SetOSDLayerBlending(void * pInstance,MS_U8 u8Layer,MS_BOOL bEnable,SCALER_WIN eWindow)9298 E_APIXC_ReturnValue MDrv_SC_SetOSDLayerBlending(void *pInstance, MS_U8 u8Layer, MS_BOOL bEnable, SCALER_WIN eWindow)
9299 {
9300 #if (VIDEO_OSD_SWITCH_VER > 0)
9301 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
9302 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
9303 MS_U32 u32Addr[] = {REG_SC_BK10_6B_L, REG_SC_BK10_60_L,
9304 REG_SC_BK10_61_L, REG_SC_BK10_62_L,
9305 REG_SC_BK10_1B_L};
9306 if ((u8Layer >= OSD_LAYER_NUM) || (eWindow >= MAX_WINDOW))
9307 {
9308 return E_APIXC_RET_FAIL_INVALID_PARAMETER;
9309 }
9310
9311 #if (VIDEO_OSD_SWITCH_VER > 1) // correct register init value
9312 if (0 == (SC_R2BYTE(psXCInstPri->u32DeviceID, u32Addr[u8Layer]) & BIT(8)))
9313 {
9314 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32Addr[u8Layer], BIT(8), BIT(10)|BIT(9)|BIT(8));
9315 }
9316 #endif
9317
9318 if (MAIN_WINDOW == eWindow)
9319 {
9320 #if (VIDEO_OSD_SWITCH_VER < 2) // ver 1
9321 if(_bZorderMLoadEn)
9322 {
9323 _u32ZorderMLoadCmd[_u16ZorderMLoadCmdCnt]=u32Addr[u8Layer];
9324 _u16ZorderMLoadVal[_u16ZorderMLoadCmdCnt]=(bEnable<<8);
9325 _u16ZorderMLoadMsk[_u16ZorderMLoadCmdCnt]=BIT(8);
9326 _u16ZorderMLoadCmdCnt++;
9327 }
9328 else
9329 {
9330 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32Addr[u8Layer], (bEnable<<8), BIT(8));
9331 }
9332 #elif (VIDEO_OSD_SWITCH_VER < 3) // ver 2
9333 if(_bZorderMLoadEn)
9334 {
9335 _u32ZorderMLoadCmd[_u16ZorderMLoadCmdCnt]=u32Addr[u8Layer];
9336 _u16ZorderMLoadVal[_u16ZorderMLoadCmdCnt]=(bEnable<<9)|BIT(8);
9337 _u16ZorderMLoadMsk[_u16ZorderMLoadCmdCnt]=BIT(9)|BIT(8);
9338 _u16ZorderMLoadCmdCnt++;
9339 }
9340 else
9341 {
9342 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32Addr[u8Layer], (bEnable<<9)|BIT(8), BIT(9)|BIT(8));
9343 }
9344 #endif
9345 }
9346 #if (VIDEO_OSD_SWITCH_VER > 1) // ver > 1, with sub blending
9347 else
9348 {
9349 if(_bZorderMLoadEn)
9350 {
9351 _u32ZorderMLoadCmd[_u16ZorderMLoadCmdCnt]=u32Addr[u8Layer];
9352 _u16ZorderMLoadVal[_u16ZorderMLoadCmdCnt]=(bEnable<<10)|BIT(8);
9353 _u16ZorderMLoadMsk[_u16ZorderMLoadCmdCnt]=BIT(10)|BIT(8);
9354 _u16ZorderMLoadCmdCnt++;
9355 }
9356 else
9357 {
9358 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32Addr[u8Layer], (bEnable<<10)|BIT(8), BIT(10)|BIT(8));
9359 }
9360 }
9361 #endif
9362 return E_APIXC_RET_OK;
9363 #else
9364 return E_APIXC_RET_FAIL_FUN_NOT_SUPPORT;
9365 #endif
9366 }
9367
MDrv_SC_SetOSDLayerAlpha(void * pInstance,MS_U8 u8Layer,MS_U8 u8Alpha)9368 E_APIXC_ReturnValue MDrv_SC_SetOSDLayerAlpha(void *pInstance, MS_U8 u8Layer, MS_U8 u8Alpha)
9369 {
9370 #if (VIDEO_OSD_SWITCH_VER > 0)
9371 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
9372 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
9373 MS_U32 u32Addr[] = {REG_SC_BK10_6B_L, REG_SC_BK10_60_L,
9374 REG_SC_BK10_61_L, REG_SC_BK10_62_L,
9375 REG_SC_BK10_1B_L};
9376 MS_U16 u16BlendingModeMask[] = {BIT(5)|BIT(4), BIT(7)|BIT(6),
9377 BIT(9)|BIT(8), BIT(13)|BIT(12),
9378 BIT(15)|BIT(14)};
9379 if ((u8Layer >= OSD_LAYER_NUM))
9380 {
9381 return E_APIXC_RET_FAIL_INVALID_PARAMETER;
9382 }
9383 if ((SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_23_L) & BIT(5)) || (SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_1C_L) & BIT(u8Layer)))
9384 {
9385 u8Alpha = 0xFF - u8Alpha;
9386 }
9387 // check mode1. If on, alpha inverse
9388 if ((SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_5B_L) & u16BlendingModeMask[u8Layer]) == u16BlendingModeMask[u8Layer])
9389 {
9390 u8Alpha = 0xFF - u8Alpha;
9391 }
9392 if(_bZorderMLoadEn)
9393 {
9394 _u32ZorderMLoadCmd[_u16ZorderMLoadCmdCnt]=u32Addr[u8Layer];
9395 _u16ZorderMLoadVal[_u16ZorderMLoadCmdCnt]=u8Alpha;
9396 _u16ZorderMLoadMsk[_u16ZorderMLoadCmdCnt]=BITMASK(7:0);
9397 _u16ZorderMLoadCmdCnt++;
9398 }
9399 else
9400 {
9401 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32Addr[u8Layer], u8Alpha, BITMASK(7:0));
9402 }
9403
9404 return E_APIXC_RET_OK;
9405 #else
9406 return E_APIXC_RET_FAIL_FUN_NOT_SUPPORT;
9407 #endif
9408 }
9409
MDrv_SC_SetOSDBlendingFormula(void * pInstance,E_XC_OSD_INDEX enOsdIndex,E_XC_OSD_BlENDING_TYPE enType,SCALER_WIN eWindow)9410 E_APIXC_ReturnValue MDrv_SC_SetOSDBlendingFormula(void *pInstance, E_XC_OSD_INDEX enOsdIndex, E_XC_OSD_BlENDING_TYPE enType, SCALER_WIN eWindow)
9411 {
9412 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
9413 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
9414 E_APIXC_ReturnValue bRet = E_APIXC_RET_OK;
9415 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
9416 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
9417
9418 if ((enOsdIndex >= OSD_LAYER_NUM) || (enType >= E_XC_OSD_BlENDING_TYPE_NUM) || (eWindow >= MAX_WINDOW))
9419 {
9420 return E_APIXC_RET_FAIL_INVALID_PARAMETER;
9421 }
9422 bRet = Hal_SC_SetOSDBlendingFormula(pInstance, enOsdIndex, enType, eWindow);
9423 return bRet;
9424 #if 0
9425 if (eWindow == MAIN_WINDOW)
9426 {
9427 switch(enOsdIndex)
9428 {
9429 case E_XC_OSD_0:
9430 if(E_XC_OSD_BlENDING_MODE1 == enType) //OSD + (1-a)*Video
9431 {
9432 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_5B_L, BIT(5)|BIT(4), BIT(5)|BIT(4));
9433 //osd check alpha define
9434 //1: for define 8'hFF is transparent
9435 //0: for define 8'h00 is transparent
9436 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_6B_L, BIT(0), BIT(0));
9437 // for zorder
9438 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_6B_L, BIT(15), BIT(15));
9439
9440 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
9441 #ifdef GOP_SUPPORT_DUALRATE
9442 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BKC9_50_L, BIT(10), BIT(10));
9443 #endif
9444 #endif
9445 }
9446 else //a*OSD + (1-a)*Video
9447 {
9448 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_5B_L, 0x00, BIT(5)|BIT(4));
9449 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_6B_L, 0x00, BIT(0));
9450 // for zorder
9451 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_6B_L, 0, BIT(15));
9452
9453 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
9454 #ifdef GOP_SUPPORT_DUALRATE
9455 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BKC9_50_L, 0, BIT(10));
9456 #endif
9457 #endif
9458 }
9459 break;
9460
9461 case E_XC_OSD_1:
9462 if(E_XC_OSD_BlENDING_MODE1 == enType) //OSD + (1-a)*Video
9463 {
9464 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_5B_L, BIT(7)|BIT(6), BIT(7)|BIT(6));
9465 //osd check alpha define
9466 //1: for define 8'hFF is transparent
9467 //0: for define 8'h00 is transparent
9468 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_6B_L, BIT(1), BIT(1));
9469 // for zorder
9470 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_60_L, BIT(15), BIT(15));
9471
9472 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
9473 #ifdef GOP_SUPPORT_DUALRATE
9474 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BKC9_51_L, BIT(10), BIT(10));
9475 #endif
9476 #endif
9477 }
9478 else //a*OSD + (1-a)*Video
9479 {
9480 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_5B_L, 0x00, BIT(7)|BIT(6));
9481 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_6B_L, 0x00, BIT(1));
9482 // for zorder
9483 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_60_L, 0, BIT(15));
9484
9485 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
9486 #ifdef GOP_SUPPORT_DUALRATE
9487 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BKC9_51_L, 0, BIT(10));
9488 #endif
9489 #endif
9490 }
9491 break;
9492
9493 case E_XC_OSD_2:
9494 if(E_XC_OSD_BlENDING_MODE1 == enType) //OSD + (1-a)*Video
9495 {
9496 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_5B_L, BIT(9)|BIT(8), BIT(9)|BIT(8));
9497 //osd check alpha define
9498 //1: for define 8'hFF is transparent
9499 //0: for define 8'h00 is transparent
9500 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_6B_L, BIT(2), BIT(2));
9501 // for zorder
9502 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_61_L, BIT(15), BIT(15));
9503
9504 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
9505 #ifdef GOP_SUPPORT_DUALRATE
9506 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BKC9_52_L, BIT(10), BIT(10));
9507 #endif
9508 #endif
9509 }
9510 else //a*OSD + (1-a)*Video
9511 {
9512 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_5B_L, 0x00, BIT(9)|BIT(8));
9513 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_6B_L, 0x00, BIT(2));
9514 // for zorder
9515 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_61_L, 0, BIT(15));
9516
9517 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
9518 #ifdef GOP_SUPPORT_DUALRATE
9519 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BKC9_52_L, 0, BIT(10));
9520 #endif
9521 #endif
9522 }
9523 break;
9524 #if (OSD_LAYER_NUM > 3)
9525 case E_XC_OSD_3:
9526 if(E_XC_OSD_BlENDING_MODE1 == enType) //OSD + (1-a)*Video
9527 {
9528 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_5B_L, BIT(13)|BIT(12), BIT(13)|BIT(12));
9529 //osd check alpha define
9530 //1: for define 8'hFF is transparent
9531 //0: for define 8'h00 is transparent
9532 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_6B_L, BIT(3), BIT(3));
9533 // for zorder
9534 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_62_L, BIT(15), BIT(15));
9535 }
9536 else //a*OSD + (1-a)*Video
9537 {
9538 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_5B_L, 0x00, BIT(13)|BIT(12));
9539 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_6B_L, 0x00, BIT(3));
9540 // for zorder
9541 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_62_L, 0, BIT(15));
9542 }
9543 break;
9544 #endif
9545 #if (OSD_LAYER_NUM > 4)
9546 case E_XC_OSD_4:
9547 if(E_XC_OSD_BlENDING_MODE1 == enType) //OSD + (1-a)*Video
9548 {
9549 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_5B_L, BIT(15)|BIT(14), BIT(15)|BIT(14));
9550 //osd check alpha define
9551 //1: for define 8'hFF is transparent
9552 //0: for define 8'h00 is transparent
9553 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_6B_L, BIT(4), BIT(4));
9554 // for zorder
9555 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_1B_L, BIT(15), BIT(15));
9556 }
9557 else //a*OSD + (1-a)*Video
9558 {
9559 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_5B_L, 0x00, BIT(15)|BIT(14));
9560 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_6B_L, 0x00, BIT(4));
9561 // for zorder
9562 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_1B_L, 0, BIT(15));
9563 }
9564 break;
9565 #endif
9566 default:
9567 printf("[MDrv_SC_SetOSDBlendingFormula]Invalid Parameter!enOsdIndex=%u\n", enOsdIndex);
9568 bRet = E_APIXC_RET_FAIL_INVALID_PARAMETER;
9569 break;
9570 }
9571 }
9572 else
9573 {
9574 // do nothing
9575 printf("[MDrv_SC_SetOSDBlendingFormula] Not support sub window now \n");
9576 bRet = E_APIXC_RET_FAIL_FUN_NOT_SUPPORT;
9577 }
9578
9579 return bRet;
9580 #endif
9581 }
9582
9583
MDrv_SC_SetMCDIBufferAddress(void * pInstance,MS_PHY u32FBAddress,MS_PHY u32FBSize,E_XC_MCDI_TYPE eType)9584 void MDrv_SC_SetMCDIBufferAddress(void *pInstance, MS_PHY u32FBAddress, MS_PHY u32FBSize, E_XC_MCDI_TYPE eType)
9585 {
9586 MS_U8 u8MIUSel;
9587 SCALER_WIN _eWindow = MAIN_WINDOW;
9588 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
9589 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
9590 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
9591 MS_PHY phyFBAddressFromReg;
9592
9593 if (eType >= E_XC_MCDI_MAX)
9594 {
9595 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"the MDCI type(%d) is invalid for frame buffer setting \n",eType);
9596 return;
9597 }
9598
9599 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
9600
9601 phyFBAddressFromReg = Hal_SC_get_mcdi_memoryaddressfromreg(pInstance, eType);
9602 if((pXCResourcePrivate->stdrvXC_Display._u32MCDIFBAddress[eType]==u32FBAddress)
9603 && (pXCResourcePrivate->stdrvXC_Display._u32MCDIFBSize[eType]==u32FBSize)
9604 && (phyFBAddressFromReg == u32FBAddress))
9605 {
9606 return;
9607 }
9608
9609 pXCResourcePrivate->stdrvXC_Display._u32MCDIFBAddress[eType]=u32FBAddress;
9610 pXCResourcePrivate->stdrvXC_Display._u32MCDIFBSize[eType]=u32FBSize;
9611
9612 if (eType <= E_XC_MCDI_BOTH)
9613 {
9614 _eWindow = MAIN_WINDOW;
9615 }
9616 else if ( (eType > E_XC_MCDI_BOTH) && (eType <= E_XC_MCDI_SUB_BOTH))
9617 {
9618 _eWindow = SUB_WINDOW;
9619 }
9620
9621 pXCResourcePrivate->stdrvXC_MVideo_Context.g_u32MCDIFBAddress_Suspend[eType] = u32FBAddress;
9622 pXCResourcePrivate->stdrvXC_MVideo_Context.g_u32MCDIFBSize_Suspend[eType] = u32FBSize;
9623
9624 _phy_to_miu_offset(u8MIUSel, u32FBAddress, u32FBAddress);
9625
9626 Hal_SC_Enable_MiuMask(pInstance);
9627
9628 Hal_SC_set_mrq_miusel(pInstance, u8MIUSel);
9629
9630 Hal_SC_set_mcdi_memoryaddress(pInstance, u32FBAddress, eType);
9631
9632 Hal_SC_set_mcdi_write_limit(pInstance, ENABLE, (u32FBAddress + u32FBSize), eType);
9633
9634 Hal_SC_Disable_MiuMask(pInstance);
9635 #if defined (__aarch64__)
9636 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"Change MCDI mode = %d FB_Start_Addr=%lx, Size=%lx\n",eType ,u32FBAddress, u32FBSize);
9637 #else
9638 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"Change MCDI mode = %d FB_Start_Addr=%tx, Size=%tx\n",eType ,(ptrdiff_t)u32FBAddress, (ptrdiff_t)u32FBSize);
9639 #endif
9640 }
9641
MDrv_SC_EnableMCDI(void * pInstance,MS_BOOL bEnable,E_XC_MCDI_TYPE eType)9642 void MDrv_SC_EnableMCDI(void *pInstance, MS_BOOL bEnable, E_XC_MCDI_TYPE eType)
9643 {
9644 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
9645 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
9646 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
9647 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
9648 if (E_POWER_SUSPEND != pXCResourcePrivate->stdrvXC_MVideo._enPrevPowerState)
9649 {
9650 pXCResourcePrivate->stdrvXC_MVideo_Context.g_bEnableMCDI_Suspend[eType] = bEnable;
9651 }
9652 Hal_SC_enable_mcdi(pInstance, bEnable, eType);
9653 }
9654
9655 //-------------------------------------------------------------------------------------------------
9656 /// Adjust OSD DE reference position
9657 /// @param bEnable allow OSD position reference enable or not
9658 /// @param VStart the vertical starting position for OSD reference
9659 /// @param VEnd the vertical ending position for OSD reference
9660 /// @param HStart the horizontal starting position for OSD reference
9661 /// @param HEnd the horizontal ending position for OSD reference
9662 //-------------------------------------------------------------------------------------------------
MDrv_XC_3D_AdjustOSDVDE(void * pInstance,MS_BOOL bEnable,MS_U16 VStart,MS_U16 VEnd,MS_U16 HStart,MS_U16 HEnd)9663 void MDrv_XC_3D_AdjustOSDVDE(void *pInstance, MS_BOOL bEnable, MS_U16 VStart, MS_U16 VEnd, MS_U16 HStart, MS_U16 HEnd)
9664 {
9665 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
9666 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
9667 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK2D_10_L, HStart, BMASK(12:0));
9668 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK2D_11_L, HEnd, BMASK(12:0));
9669 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK2D_12_L, VStart, BMASK(11:0));
9670 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK2D_13_L, VEnd, BMASK(11:0));
9671
9672 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK2D_10_L, bEnable?BIT(15):0, BIT(15));
9673 }
9674
MDrv_SC_ForceReadFrame(void * pInstance,MS_BOOL bEnable,MS_U16 u16FrameIndex)9675 E_APIXC_ReturnValue MDrv_SC_ForceReadFrame(void *pInstance, MS_BOOL bEnable, MS_U16 u16FrameIndex)
9676 {
9677 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
9678 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
9679 MS_U16 u16value = (bEnable << 11) | ((u16FrameIndex & 0x07) << 8);
9680
9681 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, u16value, 0x0F00);
9682
9683 return E_APIXC_RET_OK;
9684 }
9685
9686 //-------------------------------------------------------------------------------------------------
9687 /// Get XC free run status
9688 /// @return TRUE if it is free run, FALSE if not
9689 //-------------------------------------------------------------------------------------------------
MApi_XC_GetFreeRunStatus_U2(void * pInstance)9690 MS_BOOL MApi_XC_GetFreeRunStatus_U2(void* pInstance)
9691 {
9692 MS_BOOL bSourceSyncEn = FALSE, bFrameLPLLEn = FALSE;
9693
9694 _XC_ENTRY(pInstance);
9695
9696 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
9697 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
9698
9699 bSourceSyncEn = (MS_BOOL)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_03_L, BIT(15)) >> 15);
9700
9701 LPLL_BK_STORE;
9702 LPLL_BK_SWITCH(0x00);
9703 bFrameLPLLEn = (MS_BOOL)(MDrv_ReadRegBit(L_BK_LPLL(0x0C), BIT(3)) >> 3);
9704 LPLL_BK_RESTORE;
9705
9706 _XC_RETURN(pInstance);
9707
9708 if (!bSourceSyncEn || !bFrameLPLLEn)
9709 {
9710 return TRUE;
9711 }
9712 else
9713 {
9714 return FALSE;
9715 }
9716 }
9717
MApi_XC_GetFreeRunStatus(void)9718 MS_BOOL MApi_XC_GetFreeRunStatus(void)
9719 {
9720 if (pu32XCInst == NULL)
9721 {
9722 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
9723 return FALSE;
9724 }
9725
9726 stXC_GET_FREERUN_STATUS XCArgs;
9727 XCArgs.bReturnValue = FALSE;
9728
9729 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_GET_FREERUN_STATUS, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
9730 {
9731 printf("Obtain XC engine fail\n");
9732 return FALSE;
9733 }
9734 else
9735 {
9736 return XCArgs.bReturnValue;
9737 }
9738 }
9739
9740 //-------------------------------------------------------------------------------------------------
9741 /// MApi_XC_BYPASS_SetCSC
9742 /// @param bEnable \b IN: ENABLE/DISABLE the color space convert
9743 //-------------------------------------------------------------------------------------------------
MApi_XC_BYPASS_SetCSC_U2(void * pInstance,MS_BOOL bEnable)9744 void MApi_XC_BYPASS_SetCSC_U2(void* pInstance, MS_BOOL bEnable)
9745 {
9746 _XC_ENTRY(pInstance);
9747 MHal_XC_BYPASS_SetCSC(pInstance, bEnable);
9748 _XC_RETURN(pInstance);
9749 }
9750
MApi_XC_BYPASS_SetCSC(MS_BOOL bEnable)9751 void MApi_XC_BYPASS_SetCSC(MS_BOOL bEnable)
9752 {
9753 if (pu32XCInst == NULL)
9754 {
9755 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
9756 return;
9757 }
9758
9759 stXC_SET_BYPASS_CSC XCArgs;
9760 XCArgs.bEnable = bEnable;
9761
9762 if(UtopiaIoctl(pu32XCInst, E_XC_CMD_SET_BYPASS_CSC, (void*)&XCArgs) != UTOPIA_STATUS_SUCCESS)
9763 {
9764 printf("Obtain XC engine fail\n");
9765 return;
9766 }
9767 else
9768 {
9769 return;
9770 }
9771 }
9772
MDrv_SC_EnableReadBankSwitchControl(void * pInstance,MS_BOOL bEnable,MS_U16 u16SwitchCnt,SCALER_WIN eWindow)9773 void MDrv_SC_EnableReadBankSwitchControl(void* pInstance, MS_BOOL bEnable, MS_U16 u16SwitchCnt, SCALER_WIN eWindow)
9774 {
9775 MHal_SC_set_manual_rbank_switch_cnt(pInstance, bEnable, u16SwitchCnt, eWindow);
9776 }
9777
MDrv_XC_SetPixelShift(void * pInstance,MS_S8 s8H,MS_S8 s8V)9778 E_APIXC_ReturnValue MDrv_XC_SetPixelShift(void* pInstance, MS_S8 s8H, MS_S8 s8V)
9779 {
9780 E_APIXC_ReturnValue eRet = E_APIXC_RET_FAIL;
9781 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
9782 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
9783 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
9784 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
9785
9786 if((s8V != 0) && (gSrcInfo[MAIN_WINDOW].Status2.stXCPanelDefaultTiming.u16VStart < pXCResourcePrivate->stdrvXC_MVideo.gu16VPixelShiftRange))
9787 {
9788 //If first adjust V, and default vstart <gu16VPixelShiftRange, reset all XC window setting
9789 MS_WINDOW_TYPE stDEWin;
9790 memcpy(&stDEWin, &(gSrcInfo[MAIN_WINDOW].Status2.stXCPanelDefaultTiming), sizeof(MS_WINDOW_TYPE));
9791 gSrcInfo[MAIN_WINDOW].stDispWin.y -= stDEWin.y;
9792 gSrcInfo[SUB_WINDOW].stDispWin.y -= stDEWin.y;
9793 stDEWin.y = pXCResourcePrivate->stdrvXC_MVideo.gu16VPixelShiftRange;
9794 gSrcInfo[MAIN_WINDOW].stDispWin.y += stDEWin.y;
9795 gSrcInfo[SUB_WINDOW].stDispWin.y += stDEWin.y;
9796 MDrv_XC_UpdateWindow(pInstance, &stDEWin, &(gSrcInfo[MAIN_WINDOW].stDispWin), &(gSrcInfo[SUB_WINDOW].stDispWin), &stDEWin, NULL);
9797 }
9798
9799 if ((s8H >= -(pXCResourcePrivate->stdrvXC_MVideo.gu16HPixelShiftRange/2))
9800 && (s8H <= (pXCResourcePrivate->stdrvXC_MVideo.gu16HPixelShiftRange/2))
9801 && (s8V >= -(pXCResourcePrivate->stdrvXC_MVideo.gu16VPixelShiftRange/2)) &&
9802 (s8V <= (pXCResourcePrivate->stdrvXC_MVideo.gu16VPixelShiftRange/2)))
9803 {
9804 if (MDrv_XC_GetMirrorModeTypeEx(pInstance, MAIN_WINDOW) == MIRROR_HV)
9805 {
9806 s8H = s8H * -1;
9807 s8V = s8V * -1;
9808 printf("Mirror! H=%d,V=%d\n", s8H, s8V);
9809 }
9810
9811 eRet = MDrv_SC_ShiftDisplayWindowDirectly(pInstance, s8H, s8V, pXCResourcePrivate->stdrvXC_MVideo.s8HPixelShift, pXCResourcePrivate->stdrvXC_MVideo.s8VPixelShift);
9812 pXCResourcePrivate->stdrvXC_MVideo.s8HPixelShift = s8H;
9813 pXCResourcePrivate->stdrvXC_MVideo.s8VPixelShift = s8V;
9814 }
9815 else
9816 {
9817 pXCResourcePrivate->stdrvXC_MVideo.s8HPixelShift = 0;
9818 pXCResourcePrivate->stdrvXC_MVideo.s8VPixelShift = 0;
9819 printf("Error: %s (%d, %d): Invalid value range.\n", __FUNCTION__, s8H, s8V);
9820 }
9821
9822 return eRet;
9823 }
9824
MDrv_SC_Get_GOPOffset(MS_U16 * u16OffsetH,MS_U16 * u16OffsetV)9825 void MDrv_SC_Get_GOPOffset(MS_U16 *u16OffsetH, MS_U16 *u16OffsetV)
9826 {
9827 *u16OffsetH = 0;
9828 *u16OffsetV = 0;
9829
9830 #if (FRC_INSIDE && (HW_DESIGN_4K2K_VER == 6))
9831 void *pInstance = pu32XCInst_private;
9832 if (pu32XCInst_private == NULL)
9833 {
9834 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_XC_Init() first\n",__FUNCTION__,__LINE__);
9835 return;
9836 }
9837 _XC_SEMAPHORE_ENTRY(pInstance,E_XC_ID_VAR);
9838 _XC_ENTRY(pInstance);
9839 MHal_FRC_GetGOPOffset(pInstance, u16OffsetH, u16OffsetV);
9840 _XC_RETURN(pInstance);
9841 _XC_SEMAPHORE_RETURN(pInstance,E_XC_ID_VAR);
9842 #endif
9843 }
9844
9845 #ifdef UFO_XC_AUTO_DOWNLOAD
_MDrv_XC_AutoDownload_Convert2KDrvClient(EN_XC_AUTODOWNLOAD_CLIENT enClient,EN_KDRV_XC_AUTODOWNLOAD_CLIENT * penClient)9846 static MS_BOOL _MDrv_XC_AutoDownload_Convert2KDrvClient(EN_XC_AUTODOWNLOAD_CLIENT enClient, EN_KDRV_XC_AUTODOWNLOAD_CLIENT *penClient)
9847 {
9848 if (penClient == NULL)
9849 {
9850 return FALSE;
9851 }
9852
9853 switch(enClient)
9854 {
9855 case E_XC_AUTODOWNLOAD_CLIENT_HDR:
9856 {
9857 *penClient = E_KDRV_XC_AUTODOWNLOAD_CLIENT_HDR;
9858 break;
9859 }
9860 case E_XC_AUTODOWNLOAD_CLIENT_OP2GAMMA:
9861 {
9862 *penClient = E_KDRV_XC_AUTODOWNLOAD_CLIENT_OP2GAMMA;
9863 break;
9864 }
9865 case E_XC_AUTODOWNLOAD_CLIENT_FRCOP2GAMMA:
9866 {
9867 *penClient = E_KDRV_XC_AUTODOWNLOAD_CLIENT_FRCOP2GAMMA;
9868 break;
9869 }
9870 case E_XC_AUTODOWNLOAD_CLIENT_XVYCC:
9871 {
9872 *penClient = E_KDRV_XC_AUTODOWNLOAD_CLIENT_XVYCC;
9873 break;
9874 }
9875 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE1:
9876 {
9877 *penClient = E_KDRV_XC_AUTODOWNLOAD_CLIENT_ODTABLE1;
9878 break;
9879 }
9880 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE2:
9881 {
9882 *penClient = E_KDRV_XC_AUTODOWNLOAD_CLIENT_ODTABLE2;
9883 break;
9884 }
9885 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE3:
9886 {
9887 *penClient = E_KDRV_XC_AUTODOWNLOAD_CLIENT_ODTABLE3;
9888 break;
9889 }
9890 case E_XC_AUTODOWNLOAD_CLIENT_DEMURA:
9891 {
9892 *penClient = E_KDRV_XC_AUTODOWNLOAD_CLIENT_DEMURA;
9893 break;
9894 }
9895 case E_XC_AUTODOWNLOAD_CLIENT_OP2LUT:
9896 {
9897 *penClient = E_KDRV_XC_AUTODOWNLOAD_CLIENT_OP2LUT;
9898 break;
9899 }
9900 case E_XC_AUTODOWNLOAD_CLIENT_T3D_0:
9901 {
9902 *penClient = E_KDRV_XC_AUTODOWNLOAD_CLIENT_T3D_0;
9903 break;
9904 }
9905 case E_XC_AUTODOWNLOAD_CLIENT_T3D_1:
9906 {
9907 *penClient = E_KDRV_XC_AUTODOWNLOAD_CLIENT_T3D_1;
9908 break;
9909 }
9910 case E_XC_AUTODOWNLOAD_CLIENT_FRCSPTPOPM:
9911 {
9912 *penClient = E_KDRV_XC_AUTODOWNLOAD_CLIENT_FRCSPTPOPM;
9913 break;
9914 }
9915 case E_XC_AUTODOWNLOAD_CLIENT_FOOPM:
9916 {
9917 *penClient = E_KDRV_XC_AUTODOWNLOAD_CLIENT_FOOPM;
9918 break;
9919 }
9920 case E_XC_AUTODOWNLOAD_CLIENT_MAX:
9921 {
9922 *penClient = E_KDRV_XC_AUTODOWNLOAD_CLIENT_MAX;
9923 break;
9924 }
9925 default:
9926 {
9927 return FALSE;
9928 break;
9929 }
9930
9931 }
9932
9933 return TRUE;
9934 }
9935
_MDrv_XC_AutoDownload_Convert2KDrvMode(EN_XC_AUTODOWNLOAD_MODE enMode,EN_KDRV_XC_AUTODOWNLOAD_MODE * penMode)9936 static MS_BOOL _MDrv_XC_AutoDownload_Convert2KDrvMode(EN_XC_AUTODOWNLOAD_MODE enMode, EN_KDRV_XC_AUTODOWNLOAD_MODE *penMode)
9937 {
9938 if (penMode == NULL)
9939 {
9940 return FALSE;
9941 }
9942
9943 switch (enMode)
9944 {
9945 case E_XC_AUTODOWNLOAD_TRIGGER_MODE:
9946 {
9947 *penMode = E_KDRV_XC_AUTODOWNLOAD_TRIGGER_MODE;
9948 break;
9949 }
9950 case E_XC_AUTODOWNLOAD_ENABLE_MODE:
9951 {
9952 *penMode = E_KDRV_XC_AUTODOWNLOAD_ENABLE_MODE;
9953 break;
9954 }
9955 default:
9956 {
9957 return FALSE;
9958 break;
9959 }
9960 }
9961
9962 return TRUE;
9963 }
9964
_MDrv_XC_AutoDownload_Convert2KDrvSubClient(EN_XC_AUTODOWNLOAD_SUB_CLIENT enSubClient,EN_KDRV_XC_AUTODOWNLOAD_SUB_CLIENT * penSubClient)9965 static MS_BOOL _MDrv_XC_AutoDownload_Convert2KDrvSubClient(EN_XC_AUTODOWNLOAD_SUB_CLIENT enSubClient, EN_KDRV_XC_AUTODOWNLOAD_SUB_CLIENT *penSubClient)
9966 {
9967 if (penSubClient == NULL)
9968 {
9969 return FALSE;
9970 }
9971
9972 switch(enSubClient)
9973 {
9974 case E_XC_AUTODOWNLOAD_HDR_SUB_TMO:
9975 {
9976 *penSubClient = E_KDRV_XC_AUTODOWNLOAD_HDR_SUB_TMO;
9977 break;
9978 }
9979 case E_XC_AUTODOWNLOAD_HDR_SUB_3DLUT:
9980 {
9981 *penSubClient = E_KDRV_XC_AUTODOWNLOAD_HDR_SUB_3DLUT;
9982 break;
9983 }
9984 case E_XC_AUTODOWNLOAD_HDR_SUB_GAMMA:
9985 {
9986 *penSubClient = E_KDRV_XC_AUTODOWNLOAD_HDR_SUB_GAMMA;
9987 break;
9988 }
9989 case E_XC_AUTODOWNLOAD_HDR_SUB_DEGAMMA:
9990 {
9991 *penSubClient = E_KDRV_XC_AUTODOWNLOAD_HDR_SUB_DEGAMMA;
9992 break;
9993 }
9994 default:
9995 {
9996 return FALSE;
9997 break;
9998 }
9999
10000 }
10001
10002 return TRUE;
10003 }
10004
MDrv_XC_AutoDownload_Config(void * pInstance,XC_AUTODOWNLOAD_CONFIG_INFO * pstConfigInfo)10005 E_APIXC_ReturnValue MDrv_XC_AutoDownload_Config(void* pInstance, XC_AUTODOWNLOAD_CONFIG_INFO *pstConfigInfo)
10006 {
10007 E_APIXC_ReturnValue eRet = E_APIXC_RET_FAIL;
10008
10009 #if (defined AUTO_DOWNLOAD_HDR_IN_KERNEL) || (defined AUTO_DOWNLOAD_XVYCC_IN_KERNEL)
10010 if ((pstConfigInfo->enClient == E_XC_AUTODOWNLOAD_CLIENT_HDR) || (pstConfigInfo->enClient == E_XC_AUTODOWNLOAD_CLIENT_XVYCC))
10011 {
10012 EN_KDRV_XC_AUTODOWNLOAD_CLIENT enKDrvClient;
10013 if (_MDrv_XC_AutoDownload_Convert2KDrvClient(pstConfigInfo->enClient, &enKDrvClient) != TRUE)
10014 {
10015 printf("_MDrv_XC_AutoDownload_Convert2KDrvClient fail.\n");
10016 return E_APIXC_RET_FAIL;
10017 }
10018
10019 EN_KDRV_XC_AUTODOWNLOAD_MODE enKDrvMode;
10020 if (_MDrv_XC_AutoDownload_Convert2KDrvMode(pstConfigInfo->enMode, &enKDrvMode) != TRUE)
10021 {
10022 printf("_MDrv_XC_AutoDownload_Convert2KDrvMode fail.\n");
10023 return E_APIXC_RET_FAIL;
10024 }
10025
10026 ST_KDRV_XC_AUTODOWNLOAD_CONFIG_INFO stAutoDownloadConfigInfo;
10027 memset(&stAutoDownloadConfigInfo, 0, sizeof(ST_KDRV_XC_AUTODOWNLOAD_CONFIG_INFO));
10028 stAutoDownloadConfigInfo.bEnable = pstConfigInfo->bEnable;
10029 stAutoDownloadConfigInfo.enClient = enKDrvClient;
10030 stAutoDownloadConfigInfo.enMode = enKDrvMode;
10031 stAutoDownloadConfigInfo.phyBaseAddr = pstConfigInfo->phyBaseAddr;
10032 stAutoDownloadConfigInfo.u32Size = pstConfigInfo->u32Size;
10033 #ifdef HAL_MIU2_BASE
10034 if (pstConfigInfo->phyBaseAddr >= HAL_MIU2_BASE)
10035 {
10036 stAutoDownloadConfigInfo.u32MiuNo = 2;
10037 }
10038 else
10039 #endif
10040 #ifdef HAL_MIU1_BASE
10041 if (pstConfigInfo->phyBaseAddr >= HAL_MIU1_BASE)
10042 {
10043 stAutoDownloadConfigInfo.u32MiuNo = 1;
10044 }
10045 else
10046 #endif
10047 {
10048 stAutoDownloadConfigInfo.u32MiuNo = 0;
10049 }
10050
10051
10052 #if (defined MSOS_TYPE_LINUX) || (defined ANDROID)
10053 if(0 > _s32FdScaler)
10054 {
10055 _s32FdScaler = open("/dev/scaler", O_RDWR);
10056
10057 if(0 > _s32FdScaler)
10058 {
10059 printf("Scaler device not opened!!!!\n");
10060 return E_APIXC_RET_FAIL;
10061 }
10062 }
10063
10064 if (ioctl(_s32FdScaler, MDRV_XC_IOC_CONFIG_AUTO_DOWNLOAD, &stAutoDownloadConfigInfo))
10065 {
10066 printf("MDRV_XC_IOC_CONFIG_AUTO_DOWNLOAD fail!!!!\n");
10067 return E_APIXC_RET_FAIL;
10068 }
10069
10070 eRet = E_APIXC_RET_OK;
10071 #endif
10072 #if (defined(MSOS_TYPE_LINUX_KERNEL) && defined(CONFIG_MSTAR_XC_HDR_SUPPORT))
10073 if (MDrv_XC_ConfigAutoDownload(&stAutoDownloadConfigInfo) != TRUE)
10074 {
10075 return E_APIXC_RET_FAIL;
10076 }
10077 #endif
10078 }
10079 else
10080 #endif
10081 {
10082 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
10083 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
10084 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
10085 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
10086 MS_BOOL bEnable = pXCResourcePrivate->stdrvXC_Display._stClientInfo[pstConfigInfo->enClient].bEnable;
10087
10088 if ((pstConfigInfo->bEnable == TRUE) && (pstConfigInfo->bEnable != bEnable))
10089 {
10090 pXCResourcePrivate->stdrvXC_Display._stClientInfo[pstConfigInfo->enClient].phyBaseAddr = pstConfigInfo->phyBaseAddr;
10091 pXCResourcePrivate->stdrvXC_Display._stClientInfo[pstConfigInfo->enClient].u32Size = pstConfigInfo->u32Size;
10092 pXCResourcePrivate->stdrvXC_Display._stClientInfo[pstConfigInfo->enClient].bEnable = pstConfigInfo->bEnable;
10093
10094 MS_U8* pu8BaseAddr = (MS_U8 *)MS_PA2KSEG1(pstConfigInfo->phyBaseAddr);
10095 memset(pu8BaseAddr, 0, pstConfigInfo->u32Size);
10096
10097 eRet = MHal_XC_AutoDownload_Config(pInstance, pstConfigInfo->enClient, pstConfigInfo->phyBaseAddr, pstConfigInfo->enMode);
10098 }
10099 else if (pstConfigInfo->bEnable == FALSE)
10100 {
10101 pXCResourcePrivate->stdrvXC_Display._stClientInfo[pstConfigInfo->enClient].bEnable = pstConfigInfo->bEnable;
10102 }
10103 }
10104
10105 return eRet;
10106 }
10107
MDrv_XC_AutoDownload_Write(void * pInstance,XC_AUTODOWNLOAD_DATA_INFO * pstDataInfo)10108 E_APIXC_ReturnValue MDrv_XC_AutoDownload_Write(void* pInstance, XC_AUTODOWNLOAD_DATA_INFO *pstDataInfo)
10109 {
10110 E_APIXC_ReturnValue eRet = E_APIXC_RET_FAIL;
10111
10112 #if (defined AUTO_DOWNLOAD_HDR_IN_KERNEL) || (defined AUTO_DOWNLOAD_XVYCC_IN_KERNEL)
10113 if ((pstDataInfo->enClient == E_XC_AUTODOWNLOAD_CLIENT_HDR) || (pstDataInfo->enClient == E_XC_AUTODOWNLOAD_CLIENT_XVYCC))
10114 {
10115 EN_KDRV_XC_AUTODOWNLOAD_CLIENT enKDrvClient;
10116 if (_MDrv_XC_AutoDownload_Convert2KDrvClient(pstDataInfo->enClient, &enKDrvClient) != TRUE)
10117 {
10118 printf("_MDrv_XC_AutoDownload_Convert2KDrvClient fail.\n");
10119 return E_APIXC_RET_FAIL;
10120 }
10121
10122 XC_AUTODOWNLOAD_FORMAT_INFO *pstFormatInfo = (XC_AUTODOWNLOAD_FORMAT_INFO *)pstDataInfo->pParam;
10123
10124 EN_KDRV_XC_AUTODOWNLOAD_SUB_CLIENT enKDrvSubClient;
10125 if (_MDrv_XC_AutoDownload_Convert2KDrvSubClient(pstFormatInfo->enSubClient, &enKDrvSubClient) != TRUE)
10126 {
10127 printf("_MDrv_XC_AutoDownload_Convert2KDrvSubClient fail.\n");
10128 return E_APIXC_RET_FAIL;
10129 }
10130
10131 ST_KDRV_XC_AUTODOWNLOAD_FORMAT_INFO stAutoDownloadForamtInfo;
10132 memset(&stAutoDownloadForamtInfo, 0, sizeof(ST_KDRV_XC_AUTODOWNLOAD_FORMAT_INFO));
10133 stAutoDownloadForamtInfo.bEnableRange = pstFormatInfo->bEnableRange;
10134 stAutoDownloadForamtInfo.enSubClient = enKDrvSubClient;
10135 stAutoDownloadForamtInfo.u16StartAddr = pstFormatInfo->u16StartAddr;
10136 stAutoDownloadForamtInfo.u16EndAddr = pstFormatInfo->u16EndAddr;
10137
10138 ST_KDRV_XC_AUTODOWNLOAD_DATA_INFO stAutoDownloadDataInfo;
10139 memset(&stAutoDownloadDataInfo, 0, sizeof(ST_KDRV_XC_AUTODOWNLOAD_DATA_INFO));
10140 stAutoDownloadDataInfo.enClient = enKDrvClient;
10141 stAutoDownloadDataInfo.pu8Data = pstDataInfo->pu8Data;
10142 stAutoDownloadDataInfo.u32Size = pstDataInfo->u32Size;
10143 stAutoDownloadDataInfo.pParam = &stAutoDownloadForamtInfo;
10144
10145 #if (defined MSOS_TYPE_LINUX) || (defined ANDROID)
10146 if(0 > _s32FdScaler)
10147 {
10148 _s32FdScaler = open("/dev/scaler", O_RDWR);
10149
10150 if(0 > _s32FdScaler)
10151 {
10152 printf("Scaler device not opened!!!!\n");
10153 return E_APIXC_RET_FAIL;
10154 }
10155 }
10156 if (ioctl(_s32FdScaler, MDRV_XC_IOC_WRITE_AUTO_DOWNLOAD, &stAutoDownloadDataInfo))
10157 {
10158 printf("MDRV_XC_IOC_WRITE_AUTO_DOWNLOAD fail!!!!\n");
10159 return E_APIXC_RET_FAIL;
10160 }
10161
10162 eRet = E_APIXC_RET_OK;
10163 #endif
10164 #if (defined(MSOS_TYPE_LINUX_KERNEL) && defined(CONFIG_MSTAR_XC_HDR_SUPPORT))
10165 if (MDrv_XC_WriteAutoDownload(&stAutoDownloadDataInfo) != TRUE)
10166 {
10167 return E_APIXC_RET_FAIL;
10168 }
10169 #endif
10170 }
10171 else
10172 #endif
10173 {
10174 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
10175 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
10176 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
10177 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
10178 MS_BOOL bEnable = pXCResourcePrivate->stdrvXC_Display._stClientInfo[pstDataInfo->enClient].bEnable;
10179
10180 if (!bEnable)
10181 {
10182 XC_LOG_TRACE(XC_DBGLEVEL_PARAMETER_TRACE, "auto download is not enabled(client: %d).\n", pstDataInfo->enClient);
10183 return E_APIXC_RET_FAIL;
10184 }
10185
10186 eRet = MHal_XC_AutoDownload_Write(pInstance, pstDataInfo->enClient, pstDataInfo->pu8Data, pstDataInfo->u32Size, pstDataInfo->pParam);
10187 }
10188
10189 return eRet;
10190 }
10191
MDrv_XC_AutoDownload_Fire(void * pInstance,EN_XC_AUTODOWNLOAD_CLIENT enClient)10192 E_APIXC_ReturnValue MDrv_XC_AutoDownload_Fire(void* pInstance, EN_XC_AUTODOWNLOAD_CLIENT enClient)
10193 {
10194 E_APIXC_ReturnValue eRet = E_APIXC_RET_FAIL;
10195 XC_LOG_TRACE(XC_DBGLEVEL_PARAMETER_TRACE, "Fire auto download(client: %d).\n", enClient);
10196
10197 #if (defined AUTO_DOWNLOAD_HDR_IN_KERNEL) || (defined AUTO_DOWNLOAD_XVYCC_IN_KERNEL)
10198 if ((enClient == E_XC_AUTODOWNLOAD_CLIENT_HDR) || (enClient == E_XC_AUTODOWNLOAD_CLIENT_XVYCC))
10199 {
10200 EN_KDRV_XC_AUTODOWNLOAD_CLIENT enKDrvClient;
10201 if (_MDrv_XC_AutoDownload_Convert2KDrvClient(enClient, &enKDrvClient) != TRUE)
10202 {
10203 printf("_MDrv_XC_AutoDownload_Convert2KDrvClient fail.\n");
10204 return E_APIXC_RET_FAIL;
10205 }
10206 #if (defined MSOS_TYPE_LINUX) || (defined ANDROID)
10207 if(0 > _s32FdScaler)
10208 {
10209 _s32FdScaler = open("/dev/scaler", O_RDWR);
10210
10211 if(0 > _s32FdScaler)
10212 {
10213 printf("Scaler device not opened!!!!\n");
10214 return E_APIXC_RET_FAIL;
10215 }
10216 }
10217
10218 if (ioctl(_s32FdScaler, MDRV_XC_IOC_FIRE_AUTO_DOWNLOAD, &enKDrvClient))
10219 {
10220 printf("MDRV_XC_IOC_FIRE_AUTO_DOWNLOAD fail!!!!\n");
10221 return E_APIXC_RET_FAIL;
10222 }
10223
10224 eRet = E_APIXC_RET_OK;
10225 #endif
10226 #if (defined(MSOS_TYPE_LINUX_KERNEL) && defined(CONFIG_MSTAR_XC_HDR_SUPPORT))
10227 if (MDrv_XC_FireAutoDownload(enKDrvClient) != TRUE)
10228 {
10229 return E_APIXC_RET_FAIL;
10230 }
10231 #endif
10232 }
10233 else
10234 #endif
10235 {
10236 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
10237 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
10238 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
10239 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
10240 MS_BOOL bEnable = pXCResourcePrivate->stdrvXC_Display._stClientInfo[enClient].bEnable;
10241
10242 if (!bEnable)
10243 {
10244 XC_LOG_TRACE(XC_DBGLEVEL_PARAMETER_TRACE, "auto download is not enabled(client: %d).\n", enClient);
10245 return E_APIXC_RET_FAIL;
10246 }
10247
10248 eRet = MHal_XC_AutoDownload_Fire(pInstance, enClient);
10249 }
10250
10251 return eRet;
10252 }
10253
MDrv_XC_GetAutoDownloadCaps(EN_XC_AUTODOWNLOAD_CLIENT enClient,MS_BOOL * pbSupported)10254 E_APIXC_ReturnValue MDrv_XC_GetAutoDownloadCaps(EN_XC_AUTODOWNLOAD_CLIENT enClient, MS_BOOL *pbSupported)
10255 {
10256 E_APIXC_ReturnValue eRet = E_APIXC_RET_FAIL;
10257 #if (defined AUTO_DOWNLOAD_HDR_IN_KERNEL) || (defined AUTO_DOWNLOAD_XVYCC_IN_KERNEL)
10258 if ((enClient == E_XC_AUTODOWNLOAD_CLIENT_HDR) || (enClient == E_XC_AUTODOWNLOAD_CLIENT_XVYCC))
10259 {
10260 EN_KDRV_XC_AUTODOWNLOAD_CLIENT enKDrvClient;
10261 if (_MDrv_XC_AutoDownload_Convert2KDrvClient(enClient, &enKDrvClient) != TRUE)
10262 {
10263 printf("_MDrv_XC_AutoDownload_Convert2KDrvClient fail.\n");
10264 return E_APIXC_RET_FAIL;
10265 }
10266
10267 ST_KDRV_XC_AUTODOWNLOAD_CLIENT_SUPPORTED_CAPS stAutoDownloadCaps;
10268 memset(&stAutoDownloadCaps, 0, sizeof(ST_KDRV_XC_AUTODOWNLOAD_CLIENT_SUPPORTED_CAPS));
10269 stAutoDownloadCaps.enClient = enKDrvClient;
10270 #if (defined MSOS_TYPE_LINUX) || (defined ANDROID)
10271 if(0 > _s32FdScaler)
10272 {
10273 _s32FdScaler = open("/dev/scaler", O_RDWR);
10274
10275 if(0 > _s32FdScaler)
10276 {
10277 printf("Scaler device not opened!!!!\n");
10278 return E_APIXC_RET_FAIL;
10279 }
10280 }
10281 if (ioctl(_s32FdScaler, MDRV_XC_IOC_GET_AUTO_DOWNLOAD_CAPS, &stAutoDownloadCaps))
10282 {
10283 printf("MDRV_XC_IOC_GET_AUTO_DOWNLOAD_CAPS fail!!!!\n");
10284 return E_APIXC_RET_FAIL;
10285 }
10286
10287 *pbSupported = stAutoDownloadCaps.bSupported;
10288 eRet = E_APIXC_RET_OK;
10289 #endif
10290 #if (defined(MSOS_TYPE_LINUX_KERNEL) && defined(CONFIG_MSTAR_XC_HDR_SUPPORT))
10291 if (KDrv_XC_GetAutoDownloadCaps(&stAutoDownloadCaps) != TRUE)
10292 {
10293 return E_APIXC_RET_FAIL;
10294 }
10295
10296 *pbSupported = stAutoDownloadCaps.bSupported;
10297 eRet = E_APIXC_RET_OK;
10298 #endif
10299 }
10300 else
10301 #endif
10302 {
10303 eRet = MHal_XC_GetAutoDownloadCaps(enClient, pbSupported);
10304 }
10305 XC_LOG_TRACE(XC_DBGLEVEL_PARAMETER_TRACE, "Get auto download caps(client: %d, bSupport: %d).\n", enClient, *pbSupported);
10306
10307 return eRet;
10308 }
10309 #endif
10310
10311 #ifdef UFO_XC_HDR
10312 #if (UFO_XC_HDR_VERSION == 2)
_MDrv_XC_AutoDownload_Convert2KDrvColorFormat(EN_XC_HDR_COLOR_FORMAT enColorFormat,EN_KDRV_XC_HDR_COLOR_FORMAT * penColorFormat)10313 static MS_BOOL _MDrv_XC_AutoDownload_Convert2KDrvColorFormat(EN_XC_HDR_COLOR_FORMAT enColorFormat, EN_KDRV_XC_HDR_COLOR_FORMAT *penColorFormat)
10314 {
10315 if (penColorFormat == NULL)
10316 {
10317 return FALSE;
10318 }
10319
10320 switch (enColorFormat)
10321 {
10322 case E_XC_HDR_COLOR_NONE:
10323 {
10324 *penColorFormat = E_KDRV_XC_HDR_COLOR_NONE;
10325 break;
10326 }
10327 case E_XC_HDR_COLOR_YUV420:
10328 {
10329 *penColorFormat = E_KDRV_XC_HDR_COLOR_YUV420;
10330 break;
10331 }
10332 case E_XC_HDR_COLOR_YUV422:
10333 {
10334 *penColorFormat = E_KDRV_XC_HDR_COLOR_YUV422;
10335 break;
10336 }
10337 case E_KDRV_XC_HDR_COLOR_YUV444:
10338 {
10339 *penColorFormat = E_KDRV_XC_HDR_COLOR_YUV444;
10340 break;
10341 }
10342 case E_KDRV_XC_HDR_COLOR_RGB:
10343 {
10344 *penColorFormat = E_KDRV_XC_HDR_COLOR_RGB;
10345 break;
10346 }
10347 case E_XC_HDR_COLOR_MAX:
10348 {
10349 *penColorFormat = E_KDRV_XC_HDR_COLOR_MAX;
10350 break;
10351 }
10352 default:
10353 {
10354 return FALSE;
10355 break;
10356 }
10357 }
10358
10359 return TRUE;
10360 }
10361
MDrv_XC_HDR_Control(void * pInstance,EN_XC_HDR_CTRL_TYPE enCtrlType,void * pParam)10362 E_APIXC_ReturnValue MDrv_XC_HDR_Control(void* pInstance, EN_XC_HDR_CTRL_TYPE enCtrlType, void *pParam)
10363 {
10364 if ((enCtrlType <= E_XC_HDR_CTRL_NONE) || (enCtrlType >= E_XC_HDR_CTRL_MAX))
10365 {
10366 XC_LOG_TRACE(XC_DBGLEVEL_PARAMETER_TRACE, "HDR ctrl fail.\n");
10367 return E_APIXC_RET_FAIL;
10368 }
10369
10370 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
10371 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
10372
10373 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
10374 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
10375
10376 #if (defined MSOS_TYPE_LINUX) || (defined ANDROID)
10377 if(0 > _s32FdScaler)
10378 {
10379 _s32FdScaler = open("/dev/scaler", O_RDWR);
10380
10381 if(0 > _s32FdScaler)
10382 {
10383 printf("Scaler device not opened!!!!\n");
10384 return E_APIXC_RET_FAIL;
10385 }
10386 }
10387 #endif
10388
10389 switch(enCtrlType)
10390 {
10391 case E_XC_HDR_CTRL_ENABLE:
10392 {
10393 MS_BOOL bEnable = *(MS_BOOL *)pParam;
10394
10395 pXCResourcePrivate->stdrvXC_Display._bEnableHDR = bEnable;
10396
10397 #if (defined MSOS_TYPE_LINUX) || (defined ANDROID)
10398 if (ioctl(_s32FdScaler, MDRV_XC_IOC_ENABLE_HDR, &bEnable))
10399 {
10400 printf("MDRV_XC_IOC_ENABLE_HDR fail!!!!\n");
10401 return E_APIXC_RET_FAIL;
10402 }
10403 #endif
10404 #if (defined(MSOS_TYPE_LINUX_KERNEL) && defined(CONFIG_MSTAR_XC_HDR_SUPPORT))
10405 if (MDrv_XC_EnableHDR(bEnable) != TRUE)
10406 {
10407 return E_APIXC_RET_FAIL;
10408 }
10409 #endif
10410
10411 break;
10412 }
10413 case E_XC_HDR_CTRL_SET_TYPE:
10414 {
10415 EN_XC_HDR_TYPE enHDRType = *(EN_XC_HDR_TYPE *)pParam;
10416
10417 pXCResourcePrivate->stdrvXC_Display._enHDRType = enHDRType;
10418 EN_KDRV_XC_HDR_TYPE enXCHDRType = E_KDRV_XC_HDR_NONE;
10419
10420 if (enHDRType == E_XC_HDR_TYPE_OPEN)
10421 {
10422 enXCHDRType = E_KDRV_XC_HDR_OPEN;
10423 }
10424 else if (enHDRType == E_XC_HDR_TYPE_DOLBY)
10425 {
10426 enXCHDRType = E_KDRV_XC_HDR_DOLBY;
10427 }
10428 else if (enHDRType == E_XC_HDR_TYPE_TECHNICOLOR)
10429 {
10430 enXCHDRType = E_KDRV_XC_HDR_TECHNICOLOR;
10431 }
10432
10433 #if (defined MSOS_TYPE_LINUX) || (defined ANDROID)
10434 if (ioctl(_s32FdScaler, MDRV_XC_IOC_SET_HDR_TYPE, &enXCHDRType))
10435 {
10436 printf("MDRV_XC_IOC_SET_HDR_TYPE fail!!!!\n");
10437 return E_APIXC_RET_FAIL;
10438 }
10439 #endif
10440
10441 #if (defined(MSOS_TYPE_LINUX_KERNEL) && defined(CONFIG_MSTAR_XC_HDR_SUPPORT))
10442 if (MDrv_XC_SetHDRType(enHDRType) != TRUE)
10443 {
10444 return E_APIXC_RET_FAIL;
10445 }
10446 #endif
10447 break;
10448 }
10449 case E_XC_HDR_CTRL_GET_TYPE:
10450 {
10451 EN_XC_HDR_TYPE *penHDRType = (EN_XC_HDR_TYPE *)pParam;
10452 EN_KDRV_XC_HDR_TYPE enXCHDRType = E_KDRV_XC_HDR_NONE;
10453 #if (defined MSOS_TYPE_LINUX) || (defined ANDROID)
10454 if (ioctl(_s32FdScaler, MDRV_XC_IOC_GET_HDR_TYPE, &enXCHDRType))
10455 {
10456 printf("MDRV_XC_IOC_GET_HDR_TYPE fail!!!!\n");
10457 return E_APIXC_RET_FAIL;
10458 }
10459 #endif
10460
10461 #if (defined(MSOS_TYPE_LINUX_KERNEL) && defined(CONFIG_MSTAR_XC_HDR_SUPPORT))
10462 if (MDrv_XC_GetHDRType(&enXCHDRType) != TRUE)
10463 {
10464 return E_APIXC_RET_FAIL;
10465 }
10466 #endif
10467 switch (enXCHDRType)
10468 {
10469 default:
10470 case E_KDRV_XC_HDR_MAX:
10471 case E_KDRV_XC_HDR_NONE:
10472 *penHDRType = E_XC_HDR_TYPE_NONE;
10473 break;
10474 case E_KDRV_XC_HDR_OPEN:
10475 *penHDRType = E_XC_HDR_TYPE_OPEN;
10476 break;
10477 case E_KDRV_XC_HDR_DOLBY:
10478 *penHDRType = E_XC_HDR_TYPE_DOLBY;
10479 break;
10480 }
10481 break;
10482 }
10483 case E_XC_HDR_CTRL_SET_3DLUT:
10484 {
10485 XC_HDR_3DLUT_INFO st3DLutInfo = *(XC_HDR_3DLUT_INFO *)pParam;
10486 ST_KDRV_XC_3DLUT_INFO stXC3DLutInfo;
10487 memset(&stXC3DLutInfo, 0, sizeof(ST_KDRV_XC_3DLUT_INFO));
10488 stXC3DLutInfo.pu8Data = st3DLutInfo.pu8Data;
10489 stXC3DLutInfo.u32Size = st3DLutInfo.u32Size;
10490
10491 #if (defined MSOS_TYPE_LINUX) || (defined ANDROID)
10492
10493 if (ioctl(_s32FdScaler, MDRV_XC_IOC_SET_3DLUT_INFO, &stXC3DLutInfo))
10494 {
10495 printf("MDRV_XC_IOC_SET_3DLUT_INFO fail!!!!\n");
10496 return E_APIXC_RET_FAIL;
10497 }
10498 #endif
10499 #if (defined(MSOS_TYPE_LINUX_KERNEL) && defined(CONFIG_MSTAR_XC_HDR_SUPPORT))
10500 if (MDrv_XC_Set3DLutInfo(&stXC3DLutInfo) < 0)
10501 {
10502 printf("MDRV_XC_IOC_SET_3DLUT_INFO fail!!!!\n");
10503 return E_APIXC_RET_FAIL;
10504 }
10505 #endif
10506 break;
10507 }
10508 case E_XC_HDR_CTRL_CONFIG_DMA:
10509 {
10510 XC_HDR_DMA_CONFIG_INFO stDMAConfigInfo = *(XC_HDR_DMA_CONFIG_INFO *)pParam;
10511
10512 pXCResourcePrivate->stdrvXC_Display._stDMAConfigInfo = stDMAConfigInfo;
10513 break;
10514 }
10515 case E_XC_HDR_CTRL_INIT_DMA:
10516 {
10517 XC_HDR_DMA_INIT_INFO stDMAInitInfo = *(XC_HDR_DMA_INIT_INFO *)pParam;
10518
10519 pXCResourcePrivate->stdrvXC_Display._stDMAInitInfo = stDMAInitInfo;
10520 break;
10521 }
10522 #ifdef UFO_XC_HDMI_4K2K_DMA
10523 case E_XC_HDR_CTRL_INIT_DMA_HDMI:
10524 {
10525 XC_HDR_DMA_INIT_INFO stDMAInitInfo = *(XC_HDR_DMA_INIT_INFO *)pParam;
10526
10527 pXCResourcePrivate->stdrvXC_Display._stDMAInitInfo_Hdmi = stDMAInitInfo;
10528 break;
10529 }
10530 #endif
10531 case E_XC_HDR_CTRL_SET_OTT_SHARE_MEMORY:
10532 {
10533 XC_HDR_OTT_SHARE_MEMORY_INFO stShareMemInfo = *(XC_HDR_OTT_SHARE_MEMORY_INFO *)pParam;
10534 ST_KDRV_XC_SHARE_MEMORY_INFO stXCShareMemInfo;
10535 memset(&stXCShareMemInfo, 0, sizeof(ST_KDRV_XC_SHARE_MEMORY_INFO));
10536 stXCShareMemInfo.phyBaseAddr = stShareMemInfo.phyBaseAddr;
10537 stXCShareMemInfo.u32Size = stShareMemInfo.u32Size;
10538
10539 #ifdef HAL_MIU2_BASE
10540 if (stShareMemInfo.phyBaseAddr >= HAL_MIU2_BASE)
10541 {
10542 stXCShareMemInfo.u32MiuNo = 2;
10543 }
10544 else
10545 #endif
10546 #ifdef HAL_MIU1_BASE
10547 if (stShareMemInfo.phyBaseAddr >= HAL_MIU1_BASE)
10548 {
10549 stXCShareMemInfo.u32MiuNo = 1;
10550 }
10551 else
10552 #endif
10553 {
10554 stXCShareMemInfo.u32MiuNo = 0;
10555 }
10556
10557 #if (defined MSOS_TYPE_LINUX) || (defined ANDROID)
10558 if (ioctl(_s32FdScaler, MDRV_XC_IOC_SET_SHMEM_INFO, &stXCShareMemInfo))
10559 {
10560 printf("MDRV_XC_IOC_SET_SHMEM_INFO fail!!!!\n");
10561 return E_APIXC_RET_FAIL;
10562 }
10563 #endif
10564 #if (defined(MSOS_TYPE_LINUX_KERNEL) && defined(CONFIG_MSTAR_XC_HDR_SUPPORT))
10565 if (MDrv_XC_SetShareMemInfo(&stXCShareMemInfo) != TRUE)
10566 {
10567 return E_APIXC_RET_FAIL;
10568 }
10569 #endif
10570 break;
10571 }
10572 case E_XC_HDR_CTRL_SET_OPEN_METADATA:
10573 {
10574 //XC_HDR_OPEN_METADATA_INFO stOpenInfo = *(XC_HDR_OPEN_METADATA_INFO *)pParam;
10575 // to do
10576 break;
10577 }
10578 case E_XC_HDR_CTRL_SET_COLOR_FORMAT:
10579 {
10580 EN_XC_HDR_COLOR_FORMAT enColorFormat = *(EN_XC_HDR_COLOR_FORMAT *)pParam;
10581
10582 pXCResourcePrivate->stdrvXC_Display._enColorFormat = enColorFormat;
10583 EN_KDRV_XC_HDR_COLOR_FORMAT enXCKDrvColorFormat;
10584 if (_MDrv_XC_AutoDownload_Convert2KDrvColorFormat(enColorFormat, &enXCKDrvColorFormat) != TRUE)
10585 {
10586 printf("_MDrv_XC_AutoDownload_Convert2KDrvColorFormat fail.\n");
10587 return E_APIXC_RET_FAIL;
10588 }
10589 #if (defined MSOS_TYPE_LINUX) || (defined ANDROID)
10590 if (ioctl(_s32FdScaler, MDRV_XC_IOC_SET_COLOR_FORMAT, &enXCKDrvColorFormat))
10591 {
10592 printf("MDRV_XC_IOC_SET_COLOR_FORMAT fail!!!!\n");
10593 return E_APIXC_RET_FAIL;
10594 }
10595 #endif
10596 #if (defined(MSOS_TYPE_LINUX_KERNEL) && defined(CONFIG_MSTAR_XC_HDR_SUPPORT))
10597 if (MDrv_XC_SetColorFormat(enXCKDrvColorFormat) != TRUE)
10598 {
10599 return E_APIXC_RET_FAIL;
10600 }
10601 #endif
10602 break;
10603 }
10604 case E_XC_HDR_CTRL_CFD_CONTROL:
10605 {
10606 XC_CFD_CONTROL_INFO stCfdControlInfo = *(XC_CFD_CONTROL_INFO *)pParam;
10607 ST_KDRV_XC_CFD_CONTROL_INFO stXCCfdControlInfo;
10608 memset(&stXCCfdControlInfo, 0, sizeof(ST_KDRV_XC_CFD_CONTROL_INFO));
10609 stXCCfdControlInfo.enCtrlType = stCfdControlInfo.enCtrlType;
10610 stXCCfdControlInfo.pParam = stCfdControlInfo.pParam;
10611 stXCCfdControlInfo.u32ParamLen = stCfdControlInfo.u32ParamLen;
10612 stXCCfdControlInfo.u16ErrCode = stCfdControlInfo.u16ErrCode;
10613 #if (defined MSOS_TYPE_LINUX) || (defined ANDROID)
10614 if (ioctl(_s32FdScaler, MDRV_XC_IOC_CFDCONCTRL, pParam))
10615 {
10616 printf("MDRV_XC_IOC_CFDCONCTRL fail!!!!\n");
10617 return E_APIXC_RET_FAIL;
10618 }
10619 #endif
10620 #if (defined(MSOS_TYPE_LINUX_KERNEL) && defined(CONFIG_MSTAR_XC_HDR_SUPPORT))
10621 if (MDrv_XC_CFDControl(&stXCCfdControlInfo) != TRUE)
10622 {
10623 return E_APIXC_RET_FAIL;
10624 }
10625 #endif
10626 break;
10627 }
10628 default:
10629 {
10630 break;
10631 }
10632 }
10633
10634 return MHal_XC_HDR_Control(pInstance, enCtrlType, pParam);
10635 }
10636
MDrv_XC_HDR_SetInputSource(void * pInstance,INPUT_SOURCE_TYPE_t enInputSourceType)10637 E_APIXC_ReturnValue MDrv_XC_HDR_SetInputSource(void* pInstance, INPUT_SOURCE_TYPE_t enInputSourceType)
10638 {
10639 EN_XC_INPUT_SOURCE_TYPE enInputSource = E_XC_INPUT_SOURCE_TYPE_NONE;
10640 EN_KDRV_XC_INPUT_SOURCE_TYPE enXCInputSource = E_KDRV_XC_INPUT_SOURCE_NONE;
10641
10642 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
10643 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
10644
10645 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
10646 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
10647
10648 if(IsSrcTypeHDMI(enInputSourceType))
10649 {
10650 enInputSource = E_XC_INPUT_SOURCE_TYPE_HDMI;
10651 enXCInputSource = E_KDRV_XC_INPUT_SOURCE_HDMI;
10652 }
10653 else if (IsSrcTypeStorage(enInputSourceType))
10654 {
10655 enInputSource = E_XC_INPUT_SOURCE_TYPE_OTT;
10656 enXCInputSource = E_KDRV_XC_INPUT_SOURCE_OTT;
10657 }
10658 pXCResourcePrivate->stdrvXC_Display._enInputSourceType = enInputSource;
10659
10660 #if (defined MSOS_TYPE_LINUX) || (defined ANDROID)
10661 if(0 > _s32FdScaler)
10662 {
10663 _s32FdScaler = open("/dev/scaler", O_RDWR);
10664
10665 if(0 > _s32FdScaler)
10666 {
10667 printf("Scaler device not opened!!!!\n");
10668 return E_APIXC_RET_FAIL;
10669 }
10670 }
10671
10672 if (ioctl(_s32FdScaler, MDRV_XC_IOC_SET_INPUT_SOURCE_TYPE, &enXCInputSource))
10673 {
10674 printf("MDRV_XC_IOC_SET_INPUT_SOURCE_TYPE fail!!!!\n");
10675 return E_APIXC_RET_FAIL;
10676 }
10677 #endif
10678
10679 #if (defined(MSOS_TYPE_LINUX_KERNEL) && defined(CONFIG_MSTAR_XC_HDR_SUPPORT))
10680 if (MDrv_XC_SetInputSourceType(enInputSourceType) != TRUE)
10681 {
10682 return E_APIXC_RET_FAIL;
10683 }
10684 #endif
10685
10686 return E_APIXC_RET_OK;
10687 }
10688
MDrv_XC_HDR_GetCaps(void * pInstance,XC_HDR_SUPPORTED_CAPS * pstHDRCaps)10689 E_APIXC_ReturnValue MDrv_XC_HDR_GetCaps(void *pInstance, XC_HDR_SUPPORTED_CAPS *pstHDRCaps)
10690 {
10691 E_APIXC_ReturnValue eRet = E_APIXC_RET_FAIL;
10692 EN_XC_HDR_TYPE enHDRType = pstHDRCaps->enHDRType;
10693
10694 if ((enHDRType <= E_XC_HDR_TYPE_NONE) || (enHDRType >= E_XC_HDR_TYPE_MAX))
10695 {
10696 return E_APIXC_RET_FAIL_INVALID_PARAMETER;
10697 }
10698
10699 eRet = MHal_XC_HDR_GetCaps(pInstance, pstHDRCaps);
10700 XC_LOG_TRACE(XC_DBGLEVEL_PARAMETER_TRACE, "Get HDR caps(type: %d, bSupport: %d).\n", enHDRType, pstHDRCaps->bSupported);
10701
10702 return eRet;
10703 }
10704
MDrv_XC_HDR_SetWindow(void * pInstance,MS_WINDOW_TYPE stCapWin)10705 E_APIXC_ReturnValue MDrv_XC_HDR_SetWindow(void* pInstance, MS_WINDOW_TYPE stCapWin)
10706 {
10707 ST_KDRV_XC_WINDOW_INFO stXCWindowInfo;
10708
10709 stXCWindowInfo.u16X = stCapWin.x;
10710 stXCWindowInfo.u16Y = stCapWin.y;
10711 stXCWindowInfo.u16Width = stCapWin.width;
10712 stXCWindowInfo.u16Height = stCapWin.height;
10713
10714 #if (defined MSOS_TYPE_LINUX) || (defined ANDROID)
10715 if(0 > _s32FdScaler)
10716 {
10717 _s32FdScaler = open("/dev/scaler", O_RDWR);
10718
10719 if(0 > _s32FdScaler)
10720 {
10721 printf("Scaler device not opened!!!!\n");
10722 return E_APIXC_RET_FAIL;
10723 }
10724 }
10725
10726 if (ioctl(_s32FdScaler, MDRV_XC_IOC_SET_HDR_WINDOW, &stXCWindowInfo))
10727 {
10728 printf("MDRV_XC_IOC_SET_INPUT_SOURCE_TYPE fail!!!!\n");
10729 return E_APIXC_RET_FAIL;
10730 }
10731 #endif
10732 #if (defined(MSOS_TYPE_LINUX_KERNEL) && defined(CONFIG_MSTAR_XC_HDR_SUPPORT))
10733 if (MDrv_XC_SetHDRWindow(&stXCWindowInfo) != TRUE)
10734 {
10735 return E_APIXC_RET_FAIL;
10736 }
10737 #endif
10738 return E_APIXC_RET_OK;
10739 }
10740 #endif
10741 #endif
10742
MDrv_XC_SetSWDRInfo(void * pInstance,XC_SWDR_INFO * pSWDR_INFO)10743 MS_BOOL MDrv_XC_SetSWDRInfo(void* pInstance, XC_SWDR_INFO *pSWDR_INFO)
10744 {
10745 #if defined(UFO_XC_SWDR)
10746 ST_KDRV_XC_SWDR_INFO stKdrvXcSwdrInfo;
10747 memset(&stKdrvXcSwdrInfo, 0, sizeof(ST_KDRV_XC_SWDR_INFO));
10748
10749 stKdrvXcSwdrInfo.bDRE_En = pSWDR_INFO->bDRE_En;
10750 stKdrvXcSwdrInfo.bDRE_SWDR_En = pSWDR_INFO->bDRE_SWDR_En;
10751 stKdrvXcSwdrInfo.u8DRE_DR_Set_BasicStrength = pSWDR_INFO->u8DRE_DR_Set_BasicStrength;
10752 stKdrvXcSwdrInfo.u8DRE_SWDR_Set_BasicStrength = pSWDR_INFO->u8DRE_SWDR_Set_BasicStrength;
10753 stKdrvXcSwdrInfo.u16DRE_SWDR_Set_StrengthDk = pSWDR_INFO->u16DRE_SWDR_Set_StrengthDk;
10754 stKdrvXcSwdrInfo.u16DRE_SWDR_Set_StrengthBr = pSWDR_INFO->u16DRE_SWDR_Set_StrengthBr;
10755 stKdrvXcSwdrInfo.u8DRE_SWDR_Set_SceneProtectLevel = pSWDR_INFO->u8DRE_SWDR_Set_SceneProtectLevel;
10756 stKdrvXcSwdrInfo.u8DRE_Set_TemporalFilterLevel = pSWDR_INFO->u8DRE_Set_TemporalFilterLevel;
10757 stKdrvXcSwdrInfo.u8DRE_Set_ColorCorrectLevel = pSWDR_INFO->u8DRE_Set_ColorCorrectLevel;
10758
10759 #if (defined MSOS_TYPE_LINUX) || (defined ANDROID)
10760 if(0 > _s32FdScaler)
10761 {
10762 _s32FdScaler = open("/dev/scaler", O_RDWR);
10763
10764 if(0 > _s32FdScaler)
10765 {
10766 printf("Scaler device not opened!!!!\n");
10767 return E_APIXC_RET_FAIL;
10768 }
10769 }
10770
10771 if (ioctl(_s32FdScaler, MDRV_XC_IOC_SET_SWDR_INFO, &stKdrvXcSwdrInfo))
10772 {
10773 printf("MDRV_XC_IOC_SET_SWDR_INFO fail!!!!\n");
10774 return E_APIXC_RET_FAIL;
10775 }
10776 #endif
10777 #if defined(MSOS_TYPE_LINUX_KERNEL)
10778 if (KDrv_XC_SetSWDRInfo(&stKdrvXcSwdrInfo) != TRUE)
10779 {
10780 return E_APIXC_RET_FAIL;
10781 }
10782 #endif
10783 #endif
10784 return TRUE;
10785
10786 }
MDrv_XC_GetSWDRInfo(void * pInstance,XC_SWDR_INFO * pSWDR_INFO)10787 MS_BOOL MDrv_XC_GetSWDRInfo(void* pInstance, XC_SWDR_INFO *pSWDR_INFO)
10788 {
10789 #if defined(UFO_XC_SWDR)
10790 ST_KDRV_XC_SWDR_INFO stKdrvXcSwdrInfo;
10791 memset(&stKdrvXcSwdrInfo, 0, sizeof(ST_KDRV_XC_SWDR_INFO));
10792
10793 #if (defined MSOS_TYPE_LINUX) || (defined ANDROID)
10794 if(0 > _s32FdScaler)
10795 {
10796 _s32FdScaler = open("/dev/scaler", O_RDWR);
10797
10798 if(0 > _s32FdScaler)
10799 {
10800 printf("Scaler device not opened!!!!\n");
10801 return E_APIXC_RET_FAIL;
10802 }
10803 }
10804
10805 if (ioctl(_s32FdScaler, MDRV_XC_IOC_GET_SWDR_INFO, &stKdrvXcSwdrInfo))
10806 {
10807 printf("MDRV_XC_IOC_GET_SWDR_INFO fail!!!!\n");
10808 return E_APIXC_RET_FAIL;
10809 }
10810 #endif
10811 #if defined(MSOS_TYPE_LINUX_KERNEL)
10812 if (KDrv_XC_GetSWDRInfo(&stKdrvXcSwdrInfo) != TRUE)
10813 {
10814 return E_APIXC_RET_FAIL;
10815 }
10816 #endif
10817
10818 pSWDR_INFO->bDRE_En = stKdrvXcSwdrInfo.bDRE_En;
10819 pSWDR_INFO->bDRE_SWDR_En = stKdrvXcSwdrInfo.bDRE_SWDR_En;
10820 pSWDR_INFO->u8DRE_DR_Set_BasicStrength = stKdrvXcSwdrInfo.u8DRE_DR_Set_BasicStrength;
10821 pSWDR_INFO->u8DRE_SWDR_Set_BasicStrength = stKdrvXcSwdrInfo.u8DRE_SWDR_Set_BasicStrength;
10822 pSWDR_INFO->u16DRE_SWDR_Set_StrengthDk = stKdrvXcSwdrInfo.u16DRE_SWDR_Set_StrengthDk;
10823 pSWDR_INFO->u16DRE_SWDR_Set_StrengthBr = stKdrvXcSwdrInfo.u16DRE_SWDR_Set_StrengthBr;
10824 pSWDR_INFO->u8DRE_SWDR_Set_SceneProtectLevel = stKdrvXcSwdrInfo.u8DRE_SWDR_Set_SceneProtectLevel;
10825 pSWDR_INFO->u8DRE_Set_TemporalFilterLevel = stKdrvXcSwdrInfo.u8DRE_Set_TemporalFilterLevel;
10826 pSWDR_INFO->u8DRE_Set_ColorCorrectLevel = stKdrvXcSwdrInfo.u8DRE_Set_ColorCorrectLevel;
10827 #endif
10828
10829 return TRUE;
10830
10831 }
10832
MDrv_SC_GetHDMIPolicy(void * pInstance)10833 MS_U32 MDrv_SC_GetHDMIPolicy(void *pInstance)
10834 {
10835 MS_U32 u32HDMIPolicyInfo = 0;
10836 u32HDMIPolicyInfo = Hal_SC_get_HDMIpolicy(pInstance);
10837 return u32HDMIPolicyInfo;
10838 }
10839