1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3 * Copyright (C) 2017 Timesys Corporation.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright notice,
10 * this list of conditions and the following disclaimer.
11 *
12 * 2. Redistributions in binary form must reproduce the above copyright notice,
13 * this list of conditions and the following disclaimer in the documentation
14 * and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <arm32.h>
30 #include <console.h>
31 #include <drivers/atmel_saic.h>
32 #include <drivers/atmel_uart.h>
33 #include <io.h>
34 #include <kernel/boot.h>
35 #include <kernel/misc.h>
36 #include <kernel/panic.h>
37 #include <kernel/tz_ssvce_def.h>
38 #include <matrix.h>
39 #include <mm/core_mmu.h>
40 #include <mm/core_memprot.h>
41 #include <platform_config.h>
42 #include <sama5d2.h>
43 #include <stdint.h>
44 #include <sm/optee_smc.h>
45 #include <tz_matrix.h>
46
47 #define MATRIX_AXIMX 1
48 #define MATRIX_H64MX 2
49 #define MATRIX_H32MX 3
50
51 static struct matrix matrixes[] = {
52 {
53 .matrix = MATRIX_H64MX,
54 .p = { .pa = AT91C_BASE_MATRIX64 }
55 },
56 {
57 .matrix = MATRIX_H32MX,
58 .p = { .pa = AT91C_BASE_MATRIX32, }
59 }
60 };
61
62 static struct peri_security peri_security_array[] = {
63 {
64 .peri_id = AT91C_ID_PMC,
65 .matrix = MATRIX_H64MX,
66 .security_type = SECURITY_TYPE_PS,
67 .addr = AT91C_BASE_PMC,
68 },
69 {
70 .peri_id = AT91C_ID_ARM,
71 .matrix = MATRIX_H64MX,
72 .security_type = SECURITY_TYPE_PS,
73 },
74 {
75 .peri_id = AT91C_ID_PIT,
76 .matrix = MATRIX_H32MX,
77 .security_type = SECURITY_TYPE_PS,
78 .addr = AT91C_BASE_PITC,
79 },
80 {
81 .peri_id = AT91C_ID_WDT,
82 .matrix = MATRIX_H32MX,
83 .security_type = SECURITY_TYPE_PS,
84 .addr = AT91C_BASE_WDT,
85 },
86 {
87 .peri_id = AT91C_ID_GMAC,
88 .matrix = MATRIX_H32MX,
89 .security_type = SECURITY_TYPE_PS,
90 .addr = AT91C_BASE_GMAC,
91 },
92 {
93 .peri_id = AT91C_ID_XDMAC0,
94 .matrix = MATRIX_H64MX,
95 .security_type = SECURITY_TYPE_PS,
96 .addr = AT91C_BASE_XDMAC0,
97 },
98 {
99 .peri_id = AT91C_ID_XDMAC1,
100 .matrix = MATRIX_H64MX,
101 .security_type = SECURITY_TYPE_PS,
102 .addr = AT91C_BASE_XDMAC1,
103 },
104 {
105 .peri_id = AT91C_ID_ICM,
106 .matrix = MATRIX_H32MX,
107 .security_type = SECURITY_TYPE_PS,
108 .addr = AT91C_BASE_ICM,
109 },
110 {
111 .peri_id = AT91C_ID_AES,
112 .matrix = MATRIX_H64MX,
113 .security_type = SECURITY_TYPE_PS,
114 .addr = AT91C_BASE_AES,
115 },
116 {
117 .peri_id = AT91C_ID_AESB,
118 .matrix = MATRIX_H64MX,
119 .security_type = SECURITY_TYPE_PS,
120 .addr = AT91C_BASE_AESB,
121 },
122 {
123 .peri_id = AT91C_ID_TDES,
124 .matrix = MATRIX_H32MX,
125 .security_type = SECURITY_TYPE_PS,
126 .addr = AT91C_BASE_TDES,
127 },
128 {
129 .peri_id = AT91C_ID_SHA,
130 .matrix = MATRIX_H64MX,
131 .security_type = SECURITY_TYPE_PS,
132 .addr = AT91C_BASE_SHA,
133 },
134 {
135 .peri_id = AT91C_ID_MPDDRC,
136 .matrix = MATRIX_H64MX,
137 .security_type = SECURITY_TYPE_PS,
138 .addr = AT91C_BASE_MPDDRC,
139 },
140 {
141 .peri_id = AT91C_ID_MATRIX1,
142 .matrix = MATRIX_H32MX,
143 .security_type = SECURITY_TYPE_AS,
144 .addr = AT91C_BASE_MATRIX32,
145 },
146 {
147 .peri_id = AT91C_ID_MATRIX0,
148 .matrix = MATRIX_H64MX,
149 .security_type = SECURITY_TYPE_AS,
150 .addr = AT91C_BASE_MATRIX64,
151 },
152 {
153 .peri_id = AT91C_ID_SECUMOD,
154 .matrix = MATRIX_H32MX,
155 .security_type = SECURITY_TYPE_AS,
156 .addr = AT91C_BASE_SECUMOD,
157 },
158 {
159 .peri_id = AT91C_ID_HSMC,
160 .matrix = MATRIX_H32MX,
161 .security_type = SECURITY_TYPE_PS,
162 .addr = AT91C_BASE_HSMC,
163 },
164 {
165 .peri_id = AT91C_ID_PIOA,
166 .matrix = MATRIX_H32MX,
167 .security_type = SECURITY_TYPE_AS,
168 .addr = AT91C_BASE_PIOA,
169 },
170 {
171 .peri_id = AT91C_ID_FLEXCOM0,
172 .matrix = MATRIX_H32MX,
173 .security_type = SECURITY_TYPE_PS,
174 .addr = AT91C_BASE_FLEXCOM0,
175 },
176 {
177 .peri_id = AT91C_ID_FLEXCOM1,
178 .matrix = MATRIX_H32MX,
179 .security_type = SECURITY_TYPE_PS,
180 .addr = AT91C_BASE_FLEXCOM1,
181 },
182 {
183 .peri_id = AT91C_ID_FLEXCOM2,
184 .matrix = MATRIX_H32MX,
185 .security_type = SECURITY_TYPE_PS,
186 .addr = AT91C_BASE_FLEXCOM2,
187 },
188 {
189 .peri_id = AT91C_ID_FLEXCOM3,
190 .matrix = MATRIX_H32MX,
191 .security_type = SECURITY_TYPE_PS,
192 .addr = AT91C_BASE_FLEXCOM3,
193 },
194 {
195 .peri_id = AT91C_ID_FLEXCOM4,
196 .matrix = MATRIX_H32MX,
197 .security_type = SECURITY_TYPE_PS,
198 .addr = AT91C_BASE_FLEXCOM4,
199 },
200 {
201 .peri_id = AT91C_ID_UART0,
202 .matrix = MATRIX_H32MX,
203 .security_type = SECURITY_TYPE_PS,
204 .addr = AT91C_BASE_UART0,
205 },
206 {
207 .peri_id = AT91C_ID_UART1,
208 .matrix = MATRIX_H32MX,
209 .security_type = SECURITY_TYPE_PS,
210 .addr = AT91C_BASE_UART1,
211 },
212 {
213 .peri_id = AT91C_ID_UART2,
214 .matrix = MATRIX_H32MX,
215 .security_type = SECURITY_TYPE_PS,
216 .addr = AT91C_BASE_UART2,
217 },
218 {
219 .peri_id = AT91C_ID_UART3,
220 .matrix = MATRIX_H32MX,
221 .security_type = SECURITY_TYPE_PS,
222 .addr = AT91C_BASE_UART3,
223 },
224 {
225 .peri_id = AT91C_ID_UART4,
226 .matrix = MATRIX_H32MX,
227 .security_type = SECURITY_TYPE_PS,
228 .addr = AT91C_BASE_UART4,
229 },
230 {
231 .peri_id = AT91C_ID_TWI0,
232 .matrix = MATRIX_H32MX,
233 .security_type = SECURITY_TYPE_PS,
234 .addr = AT91C_BASE_TWI0,
235 },
236 {
237 .peri_id = AT91C_ID_TWI1,
238 .matrix = MATRIX_H32MX,
239 .security_type = SECURITY_TYPE_PS,
240 .addr = AT91C_BASE_TWI1,
241 },
242 {
243 .peri_id = AT91C_ID_SDMMC0,
244 .matrix = MATRIX_H64MX,
245 .security_type = SECURITY_TYPE_PS,
246 .addr = AT91C_BASE_SDHC0,
247 },
248 {
249 .peri_id = AT91C_ID_SDMMC1,
250 .matrix = MATRIX_H64MX,
251 .security_type = SECURITY_TYPE_PS,
252 .addr = AT91C_BASE_SDHC1,
253 },
254 {
255 .peri_id = AT91C_ID_SPI0,
256 .matrix = MATRIX_H32MX,
257 .security_type = SECURITY_TYPE_PS,
258 .addr = AT91C_BASE_SPI0,
259 },
260 {
261 .peri_id = AT91C_ID_SPI1,
262 .matrix = MATRIX_H32MX,
263 .security_type = SECURITY_TYPE_PS,
264 .addr = AT91C_BASE_SPI1,
265 },
266 {
267 .peri_id = AT91C_ID_TC0,
268 .matrix = MATRIX_H32MX,
269 .security_type = SECURITY_TYPE_PS,
270 .addr = AT91C_BASE_TC0,
271 },
272 {
273 .peri_id = AT91C_ID_TC1,
274 .matrix = MATRIX_H32MX,
275 .security_type = SECURITY_TYPE_PS,
276 .addr = AT91C_BASE_TC1,
277 },
278 {
279 .peri_id = AT91C_ID_PWM,
280 .matrix = MATRIX_H32MX,
281 .security_type = SECURITY_TYPE_PS,
282 .addr = AT91C_BASE_PWMC,
283 },
284 {
285 .peri_id = AT91C_ID_ADC,
286 .matrix = MATRIX_H32MX,
287 .security_type = SECURITY_TYPE_PS,
288 .addr = AT91C_BASE_ADC,
289 },
290 {
291 .peri_id = AT91C_ID_UHPHS,
292 .matrix = MATRIX_H32MX,
293 .security_type = SECURITY_TYPE_PS,
294 },
295 {
296 .peri_id = AT91C_ID_UDPHS,
297 .matrix = MATRIX_H32MX,
298 .security_type = SECURITY_TYPE_PS,
299 .addr = AT91C_BASE_UDPHS,
300 },
301 {
302 .peri_id = AT91C_ID_SSC0,
303 .matrix = MATRIX_H32MX,
304 .security_type = SECURITY_TYPE_PS,
305 .addr = AT91C_BASE_SSC0,
306 },
307 {
308 .peri_id = AT91C_ID_SSC1,
309 .matrix = MATRIX_H32MX,
310 .security_type = SECURITY_TYPE_PS,
311 .addr = AT91C_BASE_SSC1,
312 },
313 {
314 .peri_id = AT91C_ID_LCDC,
315 .matrix = MATRIX_H64MX,
316 .security_type = SECURITY_TYPE_PS,
317 .addr = AT91C_BASE_LCDC,
318 },
319 {
320 .peri_id = AT91C_ID_ISI,
321 .matrix = MATRIX_H64MX,
322 .security_type = SECURITY_TYPE_PS,
323 .addr = AT91C_BASE_HXISI,
324 },
325 {
326 .peri_id = AT91C_ID_TRNG,
327 .matrix = MATRIX_H32MX,
328 .security_type = SECURITY_TYPE_PS,
329 .addr = AT91C_BASE_TRNG,
330 },
331 {
332 .peri_id = AT91C_ID_PDMIC,
333 .matrix = MATRIX_H32MX,
334 .security_type = SECURITY_TYPE_PS,
335 .addr = AT91C_BASE_PDMIC,
336 },
337 {
338 .peri_id = AT91C_ID_IRQ,
339 .matrix = MATRIX_H32MX,
340 .security_type = SECURITY_TYPE_NS,
341 },
342 {
343 .peri_id = AT91C_ID_SFC,
344 .matrix = MATRIX_H32MX,
345 .security_type = SECURITY_TYPE_PS,
346 .addr = AT91C_BASE_SFC,
347 },
348 {
349 .peri_id = AT91C_ID_SECURAM,
350 .matrix = MATRIX_H32MX,
351 .security_type = SECURITY_TYPE_AS,
352 .addr = AT91C_BASE_SECURAM,
353 },
354 {
355 .peri_id = AT91C_ID_QSPI0,
356 .matrix = MATRIX_H64MX,
357 .security_type = SECURITY_TYPE_PS,
358 .addr = AT91C_BASE_QSPI0,
359 },
360 {
361 .peri_id = AT91C_ID_QSPI1,
362 .matrix = MATRIX_H64MX,
363 .security_type = SECURITY_TYPE_PS,
364 .addr = AT91C_BASE_QSPI1,
365 },
366 {
367 .peri_id = AT91C_ID_I2SC0,
368 .matrix = MATRIX_H32MX,
369 .security_type = SECURITY_TYPE_PS,
370 .addr = AT91C_BASE_I2SC0,
371 },
372 {
373 .peri_id = AT91C_ID_I2SC1,
374 .matrix = MATRIX_H32MX,
375 .security_type = SECURITY_TYPE_PS,
376 .addr = AT91C_BASE_I2SC1,
377 },
378 {
379 .peri_id = AT91C_ID_CAN0_INT0,
380 .matrix = MATRIX_H32MX,
381 .security_type = SECURITY_TYPE_PS,
382 },
383 {
384 .peri_id = AT91C_ID_CAN1_INT0,
385 .matrix = MATRIX_H32MX,
386 .security_type = SECURITY_TYPE_PS,
387 },
388 {
389 .peri_id = AT91C_ID_CLASSD,
390 .matrix = MATRIX_H32MX,
391 .security_type = SECURITY_TYPE_PS,
392 .addr = AT91C_BASE_CLASSD,
393 },
394 {
395 .peri_id = AT91C_ID_SFR,
396 .matrix = MATRIX_H32MX,
397 .security_type = SECURITY_TYPE_PS,
398 .addr = AT91C_BASE_SFR,
399 },
400 {
401 .peri_id = AT91C_ID_SAIC,
402 .matrix = MATRIX_H32MX,
403 .security_type = SECURITY_TYPE_AS,
404 .addr = AT91C_BASE_SAIC,
405 },
406 {
407 .peri_id = AT91C_ID_AIC,
408 .matrix = MATRIX_H32MX,
409 .security_type = SECURITY_TYPE_NS,
410 .addr = AT91C_BASE_AIC,
411 },
412 {
413 .peri_id = AT91C_ID_L2CC,
414 .matrix = MATRIX_H64MX,
415 .security_type = SECURITY_TYPE_PS,
416 .addr = AT91C_BASE_L2CC,
417 },
418 {
419 .peri_id = AT91C_ID_CAN0_INT1,
420 .matrix = MATRIX_H32MX,
421 .security_type = SECURITY_TYPE_PS,
422 },
423 {
424 .peri_id = AT91C_ID_CAN1_INT1,
425 .matrix = MATRIX_H32MX,
426 .security_type = SECURITY_TYPE_PS,
427 },
428 {
429 .peri_id = AT91C_ID_GMAC_Q1,
430 .matrix = MATRIX_H32MX,
431 .security_type = SECURITY_TYPE_PS,
432 },
433 {
434 .peri_id = AT91C_ID_GMAC_Q2,
435 .matrix = MATRIX_H32MX,
436 .security_type = SECURITY_TYPE_PS,
437 },
438 {
439 .peri_id = AT91C_ID_PIOB,
440 .matrix = MATRIX_H32MX,
441 .security_type = SECURITY_TYPE_AS,
442 .addr = AT91C_BASE_PIOB,
443 },
444 {
445 .peri_id = AT91C_ID_PIOC,
446 .matrix = MATRIX_H32MX,
447 .security_type = SECURITY_TYPE_AS,
448 .addr = AT91C_BASE_PIOC,
449 },
450 {
451 .peri_id = AT91C_ID_PIOD,
452 .matrix = MATRIX_H32MX,
453 .security_type = SECURITY_TYPE_AS,
454 .addr = AT91C_BASE_PIOD,
455 },
456 {
457 .peri_id = AT91C_ID_SDMMC0_TIMER,
458 .matrix = MATRIX_H32MX,
459 .security_type = SECURITY_TYPE_PS,
460 },
461 {
462 .peri_id = AT91C_ID_SDMMC1_TIMER,
463 .matrix = MATRIX_H32MX,
464 .security_type = SECURITY_TYPE_PS,
465 },
466 {
467 .peri_id = AT91C_ID_SYS,
468 .matrix = MATRIX_H32MX,
469 .security_type = SECURITY_TYPE_PS,
470 .addr = AT91C_BASE_SYSC,
471 },
472 {
473 .peri_id = AT91C_ID_ACC,
474 .matrix = MATRIX_H32MX,
475 .security_type = SECURITY_TYPE_PS,
476 .addr = AT91C_BASE_ACC,
477 },
478 {
479 .peri_id = AT91C_ID_RXLP,
480 .matrix = MATRIX_H32MX,
481 .security_type = SECURITY_TYPE_PS,
482 .addr = AT91C_BASE_RXLP,
483 },
484 {
485 .peri_id = AT91C_ID_SFRBU,
486 .matrix = MATRIX_H32MX,
487 .security_type = SECURITY_TYPE_PS,
488 .addr = AT91C_BASE_SFRBU,
489 },
490 {
491 .peri_id = AT91C_ID_CHIPID,
492 .matrix = MATRIX_H32MX,
493 .security_type = SECURITY_TYPE_PS,
494 .addr = AT91C_BASE_CHIPID,
495 },
496 };
497
498 static struct atmel_uart_data console_data;
499 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE,
500 CORE_MMU_PGDIR_SIZE);
501
plat_console_init(void)502 void plat_console_init(void)
503 {
504 atmel_uart_init(&console_data, CONSOLE_UART_BASE);
505 register_serial_console(&console_data.chip);
506 }
507
508 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AT91C_BASE_MATRIX32,
509 CORE_MMU_PGDIR_SIZE);
510 register_phys_mem_pgdir(MEM_AREA_IO_SEC, AT91C_BASE_MATRIX64,
511 CORE_MMU_PGDIR_SIZE);
512
peri_security_get(unsigned int idx)513 struct peri_security *peri_security_get(unsigned int idx)
514 {
515 struct peri_security *p = NULL;
516
517 if (idx < ARRAY_SIZE(peri_security_array))
518 p = &peri_security_array[idx];
519
520 return p;
521 }
522
matrix_get(unsigned int idx)523 struct matrix *matrix_get(unsigned int idx)
524 {
525 struct matrix *pmatrix = NULL;
526
527 if (idx < ARRAY_SIZE(matrixes))
528 pmatrix = &matrixes[idx];
529
530 return pmatrix;
531 }
532
matrix_configure_slave_h64mx(void)533 static void matrix_configure_slave_h64mx(void)
534 {
535 unsigned int ddr_port;
536 unsigned int ssr_setting;
537 unsigned int sasplit_setting;
538 unsigned int srtop_setting;
539
540 /*
541 * 0: Bridge from H64MX to AXIMX
542 * (Internal ROM, Crypto Library, PKCC RAM): Always Secured
543 */
544
545 /* 1: H64MX Peripheral Bridge: SDMMC0, SDMMC1 Non-Secure */
546 srtop_setting = MATRIX_SRTOP(1, MATRIX_SRTOP_VALUE_128M)
547 | MATRIX_SRTOP(2, MATRIX_SRTOP_VALUE_128M);
548 sasplit_setting = MATRIX_SASPLIT(1, MATRIX_SASPLIT_VALUE_128M)
549 | MATRIX_SASPLIT(2, MATRIX_SASPLIT_VALUE_128M);
550 ssr_setting = (MATRIX_LANSECH_NS(1)
551 | MATRIX_LANSECH_NS(2)
552 | MATRIX_RDNSECH_NS(1)
553 | MATRIX_RDNSECH_NS(2)
554 | MATRIX_WRNSECH_NS(1)
555 | MATRIX_WRNSECH_NS(2));
556 matrix_configure_slave_security(matrix_base(MATRIX_H64MX),
557 H64MX_SLAVE_PERI_BRIDGE,
558 srtop_setting,
559 sasplit_setting,
560 ssr_setting);
561
562 /*
563 * Matrix DDR configuration is hardcoded here and is difficult to
564 * generate at runtime. Since this configuration expect the secure
565 * DRAM to be at start of RAM and 8M of size, enforce it here.
566 */
567 COMPILE_TIME_ASSERT(CFG_TZDRAM_START == AT91C_BASE_DDRCS);
568 COMPILE_TIME_ASSERT(CFG_TZDRAM_SIZE == 0x800000);
569
570 /* 2 ~ 9 DDR2 Port1 ~ 7: Non-Secure, except op-tee tee/ta memory */
571 srtop_setting = MATRIX_SRTOP(0, MATRIX_SRTOP_VALUE_128M);
572 sasplit_setting = (MATRIX_SASPLIT(0, MATRIX_SASPLIT_VALUE_8M)
573 | MATRIX_SASPLIT(1, MATRIX_SASPLIT_VALUE_128M)
574 | MATRIX_SASPLIT(2, MATRIX_SASPLIT_VALUE_128M)
575 | MATRIX_SASPLIT(3, MATRIX_SASPLIT_VALUE_128M));
576 ssr_setting = (MATRIX_LANSECH_S(0)
577 | MATRIX_LANSECH_NS(1)
578 | MATRIX_LANSECH_NS(2)
579 | MATRIX_LANSECH_NS(3)
580 | MATRIX_RDNSECH_S(0)
581 | MATRIX_RDNSECH_NS(1)
582 | MATRIX_RDNSECH_NS(2)
583 | MATRIX_RDNSECH_NS(3)
584 | MATRIX_WRNSECH_S(0)
585 | MATRIX_WRNSECH_NS(1)
586 | MATRIX_WRNSECH_NS(2)
587 | MATRIX_WRNSECH_NS(3));
588 /* DDR port 0 not used from NWd */
589 for (ddr_port = 1; ddr_port < 8; ddr_port++) {
590 matrix_configure_slave_security(matrix_base(MATRIX_H64MX),
591 H64MX_SLAVE_DDR2_PORT_0 +
592 ddr_port, srtop_setting,
593 sasplit_setting,
594 ssr_setting);
595 }
596
597 /*
598 * 10: Internal SRAM 128K:
599 * - First 64K are reserved for suspend code in Secure World
600 * - Last 64K are for Non-Secure world (used by CAN)
601 */
602 srtop_setting = MATRIX_SRTOP(0, MATRIX_SRTOP_VALUE_128K);
603 sasplit_setting = MATRIX_SASPLIT(0, MATRIX_SRTOP_VALUE_64K);
604 ssr_setting = (MATRIX_LANSECH_S(0) | MATRIX_RDNSECH_S(0) |
605 MATRIX_WRNSECH_S(0));
606 matrix_configure_slave_security(matrix_base(MATRIX_H64MX),
607 H64MX_SLAVE_INTERNAL_SRAM,
608 srtop_setting, sasplit_setting,
609 ssr_setting);
610
611 /* 11: Internal SRAM 128K (Cache L2): Default */
612
613 /* 12: QSPI0: Normal world */
614 /* 13: QSPI1: Normal world */
615 srtop_setting = MATRIX_SRTOP(0, MATRIX_SRTOP_VALUE_128M);
616 sasplit_setting = MATRIX_SASPLIT(0, MATRIX_SASPLIT_VALUE_128M);
617 ssr_setting = MATRIX_LANSECH_NS(0) | MATRIX_RDNSECH_NS(0) |
618 MATRIX_WRNSECH_NS(0);
619
620 matrix_configure_slave_security(matrix_base(MATRIX_H64MX),
621 H64MX_SLAVE_QSPI0,
622 srtop_setting, sasplit_setting,
623 ssr_setting);
624 matrix_configure_slave_security(matrix_base(MATRIX_H64MX),
625 H64MX_SLAVE_QSPI1,
626 srtop_setting, sasplit_setting,
627 ssr_setting);
628 /* 14: AESB: Default */
629 }
630
matrix_configure_slave_h32mx(void)631 static void matrix_configure_slave_h32mx(void)
632 {
633 unsigned int ssr_setting;
634 unsigned int sasplit_setting;
635 unsigned int srtop_setting;
636
637 /* 0: Bridge from H32MX to H64MX: Not Secured */
638 /* 1: H32MX Peripheral Bridge 0: Not Secured */
639 /* 2: H32MX Peripheral Bridge 1: Not Secured */
640
641 /*
642 * 3: External Bus Interface
643 * EBI CS0 Memory(256M) ----> Slave Region 0, 1
644 * EBI CS1 Memory(256M) ----> Slave Region 2, 3
645 * EBI CS2 Memory(256M) ----> Slave Region 4, 5
646 * EBI CS3 Memory(128M) ----> Slave Region 6
647 * NFC Command Registers(128M) -->Slave Region 7
648 * NANDFlash(EBI CS3) --> Slave Region 6: Non-Secure
649 */
650 srtop_setting = MATRIX_SRTOP(6, MATRIX_SRTOP_VALUE_128M);
651 srtop_setting |= MATRIX_SRTOP(7, MATRIX_SRTOP_VALUE_128M);
652 sasplit_setting = MATRIX_SASPLIT(6, MATRIX_SASPLIT_VALUE_128M);
653 sasplit_setting |= MATRIX_SASPLIT(7, MATRIX_SASPLIT_VALUE_128M);
654 ssr_setting = (MATRIX_LANSECH_NS(6)
655 | MATRIX_RDNSECH_NS(6)
656 | MATRIX_WRNSECH_NS(6));
657 ssr_setting |= (MATRIX_LANSECH_NS(7)
658 | MATRIX_RDNSECH_NS(7)
659 | MATRIX_WRNSECH_NS(7));
660 matrix_configure_slave_security(matrix_base(MATRIX_H32MX),
661 H32MX_EXTERNAL_EBI,
662 srtop_setting,
663 sasplit_setting,
664 ssr_setting);
665
666 /* 4: NFC SRAM (4K): Non-Secure */
667 srtop_setting = MATRIX_SRTOP(0, MATRIX_SRTOP_VALUE_8K);
668 sasplit_setting = MATRIX_SASPLIT(0, MATRIX_SASPLIT_VALUE_8K);
669 ssr_setting = (MATRIX_LANSECH_NS(0)
670 | MATRIX_RDNSECH_NS(0)
671 | MATRIX_WRNSECH_NS(0));
672 matrix_configure_slave_security(matrix_base(MATRIX_H32MX),
673 H32MX_NFC_SRAM,
674 srtop_setting,
675 sasplit_setting,
676 ssr_setting);
677
678 /* 5:
679 * USB Device High Speed Dual Port RAM (DPR): 1M
680 * USB Host OHCI registers: 1M
681 * USB Host EHCI registers: 1M
682 */
683 srtop_setting = (MATRIX_SRTOP(0, MATRIX_SRTOP_VALUE_1M)
684 | MATRIX_SRTOP(1, MATRIX_SRTOP_VALUE_1M)
685 | MATRIX_SRTOP(2, MATRIX_SRTOP_VALUE_1M));
686 sasplit_setting = (MATRIX_SASPLIT(0, MATRIX_SASPLIT_VALUE_1M)
687 | MATRIX_SASPLIT(1, MATRIX_SASPLIT_VALUE_1M)
688 | MATRIX_SASPLIT(2, MATRIX_SASPLIT_VALUE_1M));
689 ssr_setting = (MATRIX_LANSECH_NS(0)
690 | MATRIX_LANSECH_NS(1)
691 | MATRIX_LANSECH_NS(2)
692 | MATRIX_RDNSECH_NS(0)
693 | MATRIX_RDNSECH_NS(1)
694 | MATRIX_RDNSECH_NS(2)
695 | MATRIX_WRNSECH_NS(0)
696 | MATRIX_WRNSECH_NS(1)
697 | MATRIX_WRNSECH_NS(2));
698 matrix_configure_slave_security(matrix_base(MATRIX_H32MX),
699 H32MX_USB,
700 srtop_setting,
701 sasplit_setting,
702 ssr_setting);
703 }
704
705 static unsigned int security_ps_peri_id[] = {
706 AT91C_ID_PMC,
707 AT91C_ID_ARM,
708 AT91C_ID_PIT,
709 AT91C_ID_WDT,
710 AT91C_ID_GMAC,
711 AT91C_ID_XDMAC0,
712 AT91C_ID_XDMAC1,
713 AT91C_ID_ICM,
714 AT91C_ID_AES,
715 AT91C_ID_AESB,
716 AT91C_ID_TDES,
717 AT91C_ID_SHA,
718 AT91C_ID_MPDDRC,
719 AT91C_ID_HSMC,
720 AT91C_ID_FLEXCOM0,
721 AT91C_ID_FLEXCOM1,
722 AT91C_ID_FLEXCOM2,
723 AT91C_ID_FLEXCOM3,
724 AT91C_ID_FLEXCOM4,
725 AT91C_ID_UART0,
726 AT91C_ID_UART1,
727 AT91C_ID_UART2,
728 AT91C_ID_UART3,
729 AT91C_ID_UART4,
730 AT91C_ID_TWI0,
731 AT91C_ID_TWI1,
732 AT91C_ID_SDMMC0,
733 AT91C_ID_SDMMC1,
734 AT91C_ID_SPI0,
735 AT91C_ID_SPI1,
736 AT91C_ID_TC0,
737 AT91C_ID_TC1,
738 AT91C_ID_PWM,
739 AT91C_ID_ADC,
740 AT91C_ID_UHPHS,
741 AT91C_ID_UDPHS,
742 AT91C_ID_SSC0,
743 AT91C_ID_SSC1,
744 AT91C_ID_LCDC,
745 AT91C_ID_ISI,
746 AT91C_ID_TRNG,
747 AT91C_ID_PDMIC,
748 AT91C_ID_SFC,
749 AT91C_ID_QSPI0,
750 AT91C_ID_QSPI1,
751 AT91C_ID_I2SC0,
752 AT91C_ID_I2SC1,
753 AT91C_ID_CAN0_INT0,
754 AT91C_ID_CAN1_INT0,
755 AT91C_ID_CLASSD,
756 AT91C_ID_SFR,
757 AT91C_ID_L2CC,
758 AT91C_ID_CAN0_INT1,
759 AT91C_ID_CAN1_INT1,
760 AT91C_ID_GMAC_Q1,
761 AT91C_ID_GMAC_Q2,
762 AT91C_ID_SDMMC0_TIMER,
763 AT91C_ID_SDMMC1_TIMER,
764 AT91C_ID_SYS,
765 AT91C_ID_ACC,
766 AT91C_ID_RXLP,
767 AT91C_ID_SFRBU,
768 AT91C_ID_CHIPID,
769 };
770
matrix_init(void)771 static int matrix_init(void)
772 {
773 matrix_write_protect_disable(matrix_base(MATRIX_H64MX));
774 matrix_write_protect_disable(matrix_base(MATRIX_H32MX));
775
776 matrix_configure_slave_h64mx();
777 matrix_configure_slave_h32mx();
778
779 return matrix_configure_periph_non_secure(security_ps_peri_id,
780 ARRAY_SIZE(security_ps_peri_id));
781 }
782
plat_primary_init_early(void)783 void plat_primary_init_early(void)
784 {
785 matrix_init();
786 }
787
boot_primary_init_intc(void)788 void boot_primary_init_intc(void)
789 {
790 if (atmel_saic_setup())
791 panic("Failed to init interrupts\n");
792 }
793