1 /* 2 * Copyright (C) 2012-2017 ARM Limited. All rights reserved. 3 * 4 * This program is free software and is provided to you under the terms of the GNU General Public License version 2 5 * as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence. 6 * 7 * A copy of the licence is included with the program, and can also be obtained from Free Software 8 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 9 */ 10 11 /** 12 * @file mali_utgard.h 13 * Defines types and interface exposed by the Mali Utgard device driver 14 */ 15 16 #ifndef __MALI_UTGARD_H__ 17 #define __MALI_UTGARD_H__ 18 19 #include "mali_osk_types.h" 20 #ifdef CONFIG_MALI_DEVFREQ 21 #include <linux/devfreq.h> 22 #include "mali_pm_metrics.h" 23 #ifdef CONFIG_DEVFREQ_THERMAL 24 #include <linux/devfreq_cooling.h> 25 #endif 26 #endif 27 28 #define MALI_GPU_NAME_UTGARD "mali-utgard" 29 30 31 #define MALI_OFFSET_GP 0x00000 32 #define MALI_OFFSET_GP_MMU 0x03000 33 34 #define MALI_OFFSET_PP0 0x08000 35 #define MALI_OFFSET_PP0_MMU 0x04000 36 #define MALI_OFFSET_PP1 0x0A000 37 #define MALI_OFFSET_PP1_MMU 0x05000 38 #define MALI_OFFSET_PP2 0x0C000 39 #define MALI_OFFSET_PP2_MMU 0x06000 40 #define MALI_OFFSET_PP3 0x0E000 41 #define MALI_OFFSET_PP3_MMU 0x07000 42 43 #define MALI_OFFSET_PP4 0x28000 44 #define MALI_OFFSET_PP4_MMU 0x1C000 45 #define MALI_OFFSET_PP5 0x2A000 46 #define MALI_OFFSET_PP5_MMU 0x1D000 47 #define MALI_OFFSET_PP6 0x2C000 48 #define MALI_OFFSET_PP6_MMU 0x1E000 49 #define MALI_OFFSET_PP7 0x2E000 50 #define MALI_OFFSET_PP7_MMU 0x1F000 51 52 #define MALI_OFFSET_L2_RESOURCE0 0x01000 53 #define MALI_OFFSET_L2_RESOURCE1 0x10000 54 #define MALI_OFFSET_L2_RESOURCE2 0x11000 55 56 #define MALI400_OFFSET_L2_CACHE0 MALI_OFFSET_L2_RESOURCE0 57 #define MALI450_OFFSET_L2_CACHE0 MALI_OFFSET_L2_RESOURCE1 58 #define MALI450_OFFSET_L2_CACHE1 MALI_OFFSET_L2_RESOURCE0 59 #define MALI450_OFFSET_L2_CACHE2 MALI_OFFSET_L2_RESOURCE2 60 #define MALI470_OFFSET_L2_CACHE1 MALI_OFFSET_L2_RESOURCE0 61 62 #define MALI_OFFSET_BCAST 0x13000 63 #define MALI_OFFSET_DLBU 0x14000 64 65 #define MALI_OFFSET_PP_BCAST 0x16000 66 #define MALI_OFFSET_PP_BCAST_MMU 0x15000 67 68 #define MALI_OFFSET_PMU 0x02000 69 #define MALI_OFFSET_DMA 0x12000 70 71 /* Mali-300 */ 72 73 #define MALI_GPU_RESOURCES_MALI300(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq) \ 74 MALI_GPU_RESOURCES_MALI400_MP1(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq) 75 76 #define MALI_GPU_RESOURCES_MALI300_PMU(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq) \ 77 MALI_GPU_RESOURCES_MALI400_MP1_PMU(base_addr, gp_irq, gp_mmu_irq, pp_irq, pp_mmu_irq) 78 79 /* Mali-400 */ 80 81 #define MALI_GPU_RESOURCES_MALI400_MP1(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq) \ 82 MALI_GPU_RESOURCE_L2(base_addr + MALI400_OFFSET_L2_CACHE0) \ 83 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \ 84 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) 85 86 #define MALI_GPU_RESOURCES_MALI400_MP1_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq) \ 87 MALI_GPU_RESOURCES_MALI400_MP1(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq) \ 88 MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU) 89 90 #define MALI_GPU_RESOURCES_MALI400_MP2(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq) \ 91 MALI_GPU_RESOURCE_L2(base_addr + MALI400_OFFSET_L2_CACHE0) \ 92 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \ 93 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \ 94 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + MALI_OFFSET_PP1, pp1_irq, base_addr + MALI_OFFSET_PP1_MMU, pp1_mmu_irq) 95 96 #define MALI_GPU_RESOURCES_MALI400_MP2_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq) \ 97 MALI_GPU_RESOURCES_MALI400_MP2(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq) \ 98 MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU) 99 100 #define MALI_GPU_RESOURCES_MALI400_MP3(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq) \ 101 MALI_GPU_RESOURCE_L2(base_addr + MALI400_OFFSET_L2_CACHE0) \ 102 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \ 103 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \ 104 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + MALI_OFFSET_PP1, pp1_irq, base_addr + MALI_OFFSET_PP1_MMU, pp1_mmu_irq) \ 105 MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + MALI_OFFSET_PP2, pp2_irq, base_addr + MALI_OFFSET_PP2_MMU, pp2_mmu_irq) 106 107 #define MALI_GPU_RESOURCES_MALI400_MP3_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq) \ 108 MALI_GPU_RESOURCES_MALI400_MP3(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq) \ 109 MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU) 110 111 #define MALI_GPU_RESOURCES_MALI400_MP4(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq) \ 112 MALI_GPU_RESOURCE_L2(base_addr + MALI400_OFFSET_L2_CACHE0) \ 113 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \ 114 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \ 115 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + MALI_OFFSET_PP1, pp1_irq, base_addr + MALI_OFFSET_PP1_MMU, pp1_mmu_irq) \ 116 MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + MALI_OFFSET_PP2, pp2_irq, base_addr + MALI_OFFSET_PP2_MMU, pp2_mmu_irq) \ 117 MALI_GPU_RESOURCE_PP_WITH_MMU(3, base_addr + MALI_OFFSET_PP3, pp3_irq, base_addr + MALI_OFFSET_PP3_MMU, pp3_mmu_irq) 118 119 #define MALI_GPU_RESOURCES_MALI400_MP4_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq) \ 120 MALI_GPU_RESOURCES_MALI400_MP4(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq) \ 121 MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU) \ 122 123 /* Mali-450 */ 124 #define MALI_GPU_RESOURCES_MALI450_MP2(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp_bcast_irq) \ 125 MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE0) \ 126 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \ 127 MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE1) \ 128 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \ 129 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + MALI_OFFSET_PP1, pp1_irq, base_addr + MALI_OFFSET_PP1_MMU, pp1_mmu_irq) \ 130 MALI_GPU_RESOURCE_BCAST(base_addr + MALI_OFFSET_BCAST) \ 131 MALI_GPU_RESOURCE_DLBU(base_addr + MALI_OFFSET_DLBU) \ 132 MALI_GPU_RESOURCE_PP_BCAST(base_addr + MALI_OFFSET_PP_BCAST, pp_bcast_irq) \ 133 MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + MALI_OFFSET_PP_BCAST_MMU) \ 134 MALI_GPU_RESOURCE_DMA(base_addr + MALI_OFFSET_DMA) 135 136 #define MALI_GPU_RESOURCES_MALI450_MP2_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp_bcast_irq) \ 137 MALI_GPU_RESOURCES_MALI450_MP2(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp_bcast_irq) \ 138 MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU) \ 139 140 #define MALI_GPU_RESOURCES_MALI450_MP3(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp_bcast_irq) \ 141 MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE0) \ 142 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \ 143 MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE1) \ 144 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \ 145 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + MALI_OFFSET_PP1, pp1_irq, base_addr + MALI_OFFSET_PP1_MMU, pp1_mmu_irq) \ 146 MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + MALI_OFFSET_PP2, pp2_irq, base_addr + MALI_OFFSET_PP2_MMU, pp2_mmu_irq) \ 147 MALI_GPU_RESOURCE_BCAST(base_addr + MALI_OFFSET_BCAST) \ 148 MALI_GPU_RESOURCE_DLBU(base_addr + MALI_OFFSET_DLBU) \ 149 MALI_GPU_RESOURCE_PP_BCAST(base_addr + MALI_OFFSET_PP_BCAST, pp_bcast_irq) \ 150 MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + MALI_OFFSET_PP_BCAST_MMU) 151 152 #define MALI_GPU_RESOURCES_MALI450_MP3_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp_bcast_irq) \ 153 MALI_GPU_RESOURCES_MALI450_MP3(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp_bcast_irq) \ 154 MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU) \ 155 156 #define MALI_GPU_RESOURCES_MALI450_MP4(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp_bcast_irq) \ 157 MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE0) \ 158 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \ 159 MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE1) \ 160 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \ 161 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + MALI_OFFSET_PP1, pp1_irq, base_addr + MALI_OFFSET_PP1_MMU, pp1_mmu_irq) \ 162 MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + MALI_OFFSET_PP2, pp2_irq, base_addr + MALI_OFFSET_PP2_MMU, pp2_mmu_irq) \ 163 MALI_GPU_RESOURCE_PP_WITH_MMU(3, base_addr + MALI_OFFSET_PP3, pp3_irq, base_addr + MALI_OFFSET_PP3_MMU, pp3_mmu_irq) \ 164 MALI_GPU_RESOURCE_BCAST(base_addr + MALI_OFFSET_BCAST) \ 165 MALI_GPU_RESOURCE_DLBU(base_addr + MALI_OFFSET_DLBU) \ 166 MALI_GPU_RESOURCE_PP_BCAST(base_addr + MALI_OFFSET_PP_BCAST, pp_bcast_irq) \ 167 MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + MALI_OFFSET_PP_BCAST_MMU) \ 168 MALI_GPU_RESOURCE_DMA(base_addr + MALI_OFFSET_DMA) 169 170 #define MALI_GPU_RESOURCES_MALI450_MP4_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp_bcast_irq) \ 171 MALI_GPU_RESOURCES_MALI450_MP4(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp_bcast_irq) \ 172 MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU) \ 173 174 #define MALI_GPU_RESOURCES_MALI450_MP6(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp_bcast_irq) \ 175 MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE0) \ 176 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \ 177 MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE1) \ 178 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \ 179 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + MALI_OFFSET_PP1, pp1_irq, base_addr + MALI_OFFSET_PP1_MMU, pp1_mmu_irq) \ 180 MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + MALI_OFFSET_PP2, pp2_irq, base_addr + MALI_OFFSET_PP2_MMU, pp2_mmu_irq) \ 181 MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE2) \ 182 MALI_GPU_RESOURCE_PP_WITH_MMU(3, base_addr + MALI_OFFSET_PP4, pp3_irq, base_addr + MALI_OFFSET_PP4_MMU, pp3_mmu_irq) \ 183 MALI_GPU_RESOURCE_PP_WITH_MMU(4, base_addr + MALI_OFFSET_PP5, pp4_irq, base_addr + MALI_OFFSET_PP5_MMU, pp4_mmu_irq) \ 184 MALI_GPU_RESOURCE_PP_WITH_MMU(5, base_addr + MALI_OFFSET_PP6, pp5_irq, base_addr + MALI_OFFSET_PP6_MMU, pp5_mmu_irq) \ 185 MALI_GPU_RESOURCE_BCAST(base_addr + MALI_OFFSET_BCAST) \ 186 MALI_GPU_RESOURCE_DLBU(base_addr + MALI_OFFSET_DLBU) \ 187 MALI_GPU_RESOURCE_PP_BCAST(base_addr + MALI_OFFSET_PP_BCAST, pp_bcast_irq) \ 188 MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + MALI_OFFSET_PP_BCAST_MMU) \ 189 MALI_GPU_RESOURCE_DMA(base_addr + MALI_OFFSET_DMA) 190 191 #define MALI_GPU_RESOURCES_MALI450_MP6_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp_bcast_irq) \ 192 MALI_GPU_RESOURCES_MALI450_MP6(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp_bcast_irq) \ 193 MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU) \ 194 195 #define MALI_GPU_RESOURCES_MALI450_MP8(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp6_irq, pp6_mmu_irq, pp7_irq, pp7_mmu_irq, pp_bcast_irq) \ 196 MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE0) \ 197 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \ 198 MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE1) \ 199 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \ 200 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + MALI_OFFSET_PP1, pp1_irq, base_addr + MALI_OFFSET_PP1_MMU, pp1_mmu_irq) \ 201 MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + MALI_OFFSET_PP2, pp2_irq, base_addr + MALI_OFFSET_PP2_MMU, pp2_mmu_irq) \ 202 MALI_GPU_RESOURCE_PP_WITH_MMU(3, base_addr + MALI_OFFSET_PP3, pp3_irq, base_addr + MALI_OFFSET_PP3_MMU, pp3_mmu_irq) \ 203 MALI_GPU_RESOURCE_L2(base_addr + MALI450_OFFSET_L2_CACHE2) \ 204 MALI_GPU_RESOURCE_PP_WITH_MMU(4, base_addr + MALI_OFFSET_PP4, pp4_irq, base_addr + MALI_OFFSET_PP4_MMU, pp4_mmu_irq) \ 205 MALI_GPU_RESOURCE_PP_WITH_MMU(5, base_addr + MALI_OFFSET_PP5, pp5_irq, base_addr + MALI_OFFSET_PP5_MMU, pp5_mmu_irq) \ 206 MALI_GPU_RESOURCE_PP_WITH_MMU(6, base_addr + MALI_OFFSET_PP6, pp6_irq, base_addr + MALI_OFFSET_PP6_MMU, pp6_mmu_irq) \ 207 MALI_GPU_RESOURCE_PP_WITH_MMU(7, base_addr + MALI_OFFSET_PP7, pp7_irq, base_addr + MALI_OFFSET_PP7_MMU, pp7_mmu_irq) \ 208 MALI_GPU_RESOURCE_BCAST(base_addr + MALI_OFFSET_BCAST) \ 209 MALI_GPU_RESOURCE_DLBU(base_addr + MALI_OFFSET_DLBU) \ 210 MALI_GPU_RESOURCE_PP_BCAST(base_addr + MALI_OFFSET_PP_BCAST, pp_bcast_irq) \ 211 MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + MALI_OFFSET_PP_BCAST_MMU) \ 212 MALI_GPU_RESOURCE_DMA(base_addr + MALI_OFFSET_DMA) 213 214 #define MALI_GPU_RESOURCES_MALI450_MP8_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp6_irq, pp6_mmu_irq, pp7_irq, pp7_mmu_irq, pp_bcast_irq) \ 215 MALI_GPU_RESOURCES_MALI450_MP8(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp4_irq, pp4_mmu_irq, pp5_irq, pp5_mmu_irq, pp6_irq, pp6_mmu_irq, pp7_irq, pp7_mmu_irq, pp_bcast_irq) \ 216 MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU) \ 217 218 /* Mali - 470 */ 219 #define MALI_GPU_RESOURCES_MALI470_MP1(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp_bcast_irq) \ 220 MALI_GPU_RESOURCE_L2(base_addr + MALI470_OFFSET_L2_CACHE1) \ 221 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \ 222 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \ 223 MALI_GPU_RESOURCE_BCAST(base_addr + MALI_OFFSET_BCAST) \ 224 MALI_GPU_RESOURCE_DLBU(base_addr + MALI_OFFSET_DLBU) \ 225 MALI_GPU_RESOURCE_PP_BCAST(base_addr + MALI_OFFSET_PP_BCAST, pp_bcast_irq) \ 226 MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + MALI_OFFSET_PP_BCAST_MMU) 227 228 #define MALI_GPU_RESOURCES_MALI470_MP1_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp_bcast_irq) \ 229 MALI_GPU_RESOURCES_MALI470_MP1(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp_bcast_irq) \ 230 MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU) \ 231 232 #define MALI_GPU_RESOURCES_MALI470_MP2(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp_bcast_irq) \ 233 MALI_GPU_RESOURCE_L2(base_addr + MALI470_OFFSET_L2_CACHE1) \ 234 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \ 235 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \ 236 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + MALI_OFFSET_PP1, pp1_irq, base_addr + MALI_OFFSET_PP1_MMU, pp1_mmu_irq) \ 237 MALI_GPU_RESOURCE_BCAST(base_addr + MALI_OFFSET_BCAST) \ 238 MALI_GPU_RESOURCE_DLBU(base_addr + MALI_OFFSET_DLBU) \ 239 MALI_GPU_RESOURCE_PP_BCAST(base_addr + MALI_OFFSET_PP_BCAST, pp_bcast_irq) \ 240 MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + MALI_OFFSET_PP_BCAST_MMU) 241 242 #define MALI_GPU_RESOURCES_MALI470_MP2_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp_bcast_irq) \ 243 MALI_GPU_RESOURCES_MALI470_MP2(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp_bcast_irq) \ 244 MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU) \ 245 246 #define MALI_GPU_RESOURCES_MALI470_MP3(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp_bcast_irq) \ 247 MALI_GPU_RESOURCE_L2(base_addr + MALI470_OFFSET_L2_CACHE1) \ 248 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \ 249 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \ 250 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + MALI_OFFSET_PP1, pp1_irq, base_addr + MALI_OFFSET_PP1_MMU, pp1_mmu_irq) \ 251 MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + MALI_OFFSET_PP2, pp2_irq, base_addr + MALI_OFFSET_PP2_MMU, pp2_mmu_irq) \ 252 MALI_GPU_RESOURCE_BCAST(base_addr + MALI_OFFSET_BCAST) \ 253 MALI_GPU_RESOURCE_DLBU(base_addr + MALI_OFFSET_DLBU) \ 254 MALI_GPU_RESOURCE_PP_BCAST(base_addr + MALI_OFFSET_PP_BCAST, pp_bcast_irq) \ 255 MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + MALI_OFFSET_PP_BCAST_MMU) 256 257 #define MALI_GPU_RESOURCES_MALI470_MP3_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp_bcast_irq) \ 258 MALI_GPU_RESOURCES_MALI470_MP3(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp_bcast_irq) \ 259 MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU) \ 260 261 #define MALI_GPU_RESOURCES_MALI470_MP4(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp_bcast_irq) \ 262 MALI_GPU_RESOURCE_L2(base_addr + MALI470_OFFSET_L2_CACHE1) \ 263 MALI_GPU_RESOURCE_GP_WITH_MMU(base_addr + MALI_OFFSET_GP, gp_irq, base_addr + MALI_OFFSET_GP_MMU, gp_mmu_irq) \ 264 MALI_GPU_RESOURCE_PP_WITH_MMU(0, base_addr + MALI_OFFSET_PP0, pp0_irq, base_addr + MALI_OFFSET_PP0_MMU, pp0_mmu_irq) \ 265 MALI_GPU_RESOURCE_PP_WITH_MMU(1, base_addr + MALI_OFFSET_PP1, pp1_irq, base_addr + MALI_OFFSET_PP1_MMU, pp1_mmu_irq) \ 266 MALI_GPU_RESOURCE_PP_WITH_MMU(2, base_addr + MALI_OFFSET_PP2, pp2_irq, base_addr + MALI_OFFSET_PP2_MMU, pp2_mmu_irq) \ 267 MALI_GPU_RESOURCE_PP_WITH_MMU(3, base_addr + MALI_OFFSET_PP3, pp3_irq, base_addr + MALI_OFFSET_PP3_MMU, pp3_mmu_irq) \ 268 MALI_GPU_RESOURCE_BCAST(base_addr + MALI_OFFSET_BCAST) \ 269 MALI_GPU_RESOURCE_DLBU(base_addr + MALI_OFFSET_DLBU) \ 270 MALI_GPU_RESOURCE_PP_BCAST(base_addr + MALI_OFFSET_PP_BCAST, pp_bcast_irq) \ 271 MALI_GPU_RESOURCE_PP_MMU_BCAST(base_addr + MALI_OFFSET_PP_BCAST_MMU) 272 273 #define MALI_GPU_RESOURCES_MALI470_MP4_PMU(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp_bcast_irq) \ 274 MALI_GPU_RESOURCES_MALI470_MP4(base_addr, gp_irq, gp_mmu_irq, pp0_irq, pp0_mmu_irq, pp1_irq, pp1_mmu_irq, pp2_irq, pp2_mmu_irq, pp3_irq, pp3_mmu_irq, pp_bcast_irq) \ 275 MALI_GPU_RESOURCE_PMU(base_addr + MALI_OFFSET_PMU) \ 276 277 #define MALI_GPU_RESOURCE_L2(addr) \ 278 { \ 279 .name = "Mali_L2", \ 280 .flags = IORESOURCE_MEM, \ 281 .start = addr, \ 282 .end = addr + 0x200, \ 283 }, 284 285 #define MALI_GPU_RESOURCE_GP(gp_addr, gp_irq) \ 286 { \ 287 .name = "Mali_GP", \ 288 .flags = IORESOURCE_MEM, \ 289 .start = gp_addr, \ 290 .end = gp_addr + 0x100, \ 291 }, \ 292 { \ 293 .name = "Mali_GP_IRQ", \ 294 .flags = IORESOURCE_IRQ, \ 295 .start = gp_irq, \ 296 .end = gp_irq, \ 297 }, \ 298 299 #define MALI_GPU_RESOURCE_GP_WITH_MMU(gp_addr, gp_irq, gp_mmu_addr, gp_mmu_irq) \ 300 { \ 301 .name = "Mali_GP", \ 302 .flags = IORESOURCE_MEM, \ 303 .start = gp_addr, \ 304 .end = gp_addr + 0x100, \ 305 }, \ 306 { \ 307 .name = "Mali_GP_IRQ", \ 308 .flags = IORESOURCE_IRQ, \ 309 .start = gp_irq, \ 310 .end = gp_irq, \ 311 }, \ 312 { \ 313 .name = "Mali_GP_MMU", \ 314 .flags = IORESOURCE_MEM, \ 315 .start = gp_mmu_addr, \ 316 .end = gp_mmu_addr + 0x100, \ 317 }, \ 318 { \ 319 .name = "Mali_GP_MMU_IRQ", \ 320 .flags = IORESOURCE_IRQ, \ 321 .start = gp_mmu_irq, \ 322 .end = gp_mmu_irq, \ 323 }, 324 325 #define MALI_GPU_RESOURCE_PP(pp_addr, pp_irq) \ 326 { \ 327 .name = "Mali_PP", \ 328 .flags = IORESOURCE_MEM, \ 329 .start = pp_addr, \ 330 .end = pp_addr + 0x1100, \ 331 }, \ 332 { \ 333 .name = "Mali_PP_IRQ", \ 334 .flags = IORESOURCE_IRQ, \ 335 .start = pp_irq, \ 336 .end = pp_irq, \ 337 }, \ 338 339 #define MALI_GPU_RESOURCE_PP_WITH_MMU(id, pp_addr, pp_irq, pp_mmu_addr, pp_mmu_irq) \ 340 { \ 341 .name = "Mali_PP" #id, \ 342 .flags = IORESOURCE_MEM, \ 343 .start = pp_addr, \ 344 .end = pp_addr + 0x1100, \ 345 }, \ 346 { \ 347 .name = "Mali_PP" #id "_IRQ", \ 348 .flags = IORESOURCE_IRQ, \ 349 .start = pp_irq, \ 350 .end = pp_irq, \ 351 }, \ 352 { \ 353 .name = "Mali_PP" #id "_MMU", \ 354 .flags = IORESOURCE_MEM, \ 355 .start = pp_mmu_addr, \ 356 .end = pp_mmu_addr + 0x100, \ 357 }, \ 358 { \ 359 .name = "Mali_PP" #id "_MMU_IRQ", \ 360 .flags = IORESOURCE_IRQ, \ 361 .start = pp_mmu_irq, \ 362 .end = pp_mmu_irq, \ 363 }, 364 365 #define MALI_GPU_RESOURCE_MMU(mmu_addr, mmu_irq) \ 366 { \ 367 .name = "Mali_MMU", \ 368 .flags = IORESOURCE_MEM, \ 369 .start = mmu_addr, \ 370 .end = mmu_addr + 0x100, \ 371 }, \ 372 { \ 373 .name = "Mali_MMU_IRQ", \ 374 .flags = IORESOURCE_IRQ, \ 375 .start = mmu_irq, \ 376 .end = mmu_irq, \ 377 }, 378 379 #define MALI_GPU_RESOURCE_PMU(pmu_addr) \ 380 { \ 381 .name = "Mali_PMU", \ 382 .flags = IORESOURCE_MEM, \ 383 .start = pmu_addr, \ 384 .end = pmu_addr + 0x100, \ 385 }, 386 387 #define MALI_GPU_RESOURCE_DMA(dma_addr) \ 388 { \ 389 .name = "Mali_DMA", \ 390 .flags = IORESOURCE_MEM, \ 391 .start = dma_addr, \ 392 .end = dma_addr + 0x100, \ 393 }, 394 395 #define MALI_GPU_RESOURCE_DLBU(dlbu_addr) \ 396 { \ 397 .name = "Mali_DLBU", \ 398 .flags = IORESOURCE_MEM, \ 399 .start = dlbu_addr, \ 400 .end = dlbu_addr + 0x100, \ 401 }, 402 403 #define MALI_GPU_RESOURCE_BCAST(bcast_addr) \ 404 { \ 405 .name = "Mali_Broadcast", \ 406 .flags = IORESOURCE_MEM, \ 407 .start = bcast_addr, \ 408 .end = bcast_addr + 0x100, \ 409 }, 410 411 #define MALI_GPU_RESOURCE_PP_BCAST(pp_addr, pp_irq) \ 412 { \ 413 .name = "Mali_PP_Broadcast", \ 414 .flags = IORESOURCE_MEM, \ 415 .start = pp_addr, \ 416 .end = pp_addr + 0x1100, \ 417 }, \ 418 { \ 419 .name = "Mali_PP_Broadcast_IRQ", \ 420 .flags = IORESOURCE_IRQ, \ 421 .start = pp_irq, \ 422 .end = pp_irq, \ 423 }, \ 424 425 #define MALI_GPU_RESOURCE_PP_MMU_BCAST(pp_mmu_bcast_addr) \ 426 { \ 427 .name = "Mali_PP_MMU_Broadcast", \ 428 .flags = IORESOURCE_MEM, \ 429 .start = pp_mmu_bcast_addr, \ 430 .end = pp_mmu_bcast_addr + 0x100, \ 431 }, 432 433 struct mali_gpu_utilization_data { 434 unsigned int utilization_gpu; /* Utilization for GP and all PP cores combined, 0 = no utilization, 256 = full utilization */ 435 unsigned int utilization_gp; /* Utilization for GP core only, 0 = no utilization, 256 = full utilization */ 436 unsigned int utilization_pp; /* Utilization for all PP cores combined, 0 = no utilization, 256 = full utilization */ 437 }; 438 439 struct mali_gpu_clk_item { 440 unsigned int clock; /* unit(MHz) */ 441 unsigned int vol; 442 }; 443 444 struct mali_gpu_clock { 445 struct mali_gpu_clk_item *item; 446 unsigned int num_of_steps; 447 }; 448 449 struct mali_gpu_device_data { 450 /* Shared GPU memory */ 451 unsigned long shared_mem_size; 452 453 /* 454 * Mali PMU switch delay. 455 * Only needed if the power gates are connected to the PMU in a high fanout 456 * network. This value is the number of Mali clock cycles it takes to 457 * enable the power gates and turn on the power mesh. 458 * This value will have no effect if a daisy chain implementation is used. 459 */ 460 u32 pmu_switch_delay; 461 462 /* Mali Dynamic power domain configuration in sequence from 0-11 463 * GP PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7, L2$0 L2$1 L2$2 464 */ 465 u16 pmu_domain_config[12]; 466 467 /* Dedicated GPU memory range (physical). */ 468 unsigned long dedicated_mem_start; 469 unsigned long dedicated_mem_size; 470 471 /* Frame buffer memory to be accessible by Mali GPU (physical) */ 472 unsigned long fb_start; 473 unsigned long fb_size; 474 475 /* Max runtime [ms] for jobs */ 476 int max_job_runtime; 477 478 /* Report GPU utilization and related control in this interval (specified in ms) */ 479 unsigned long control_interval; 480 481 /* Function that will receive periodic GPU utilization numbers */ 482 void (*utilization_callback)(struct mali_gpu_utilization_data *data); 483 484 /* Fuction that platform callback for freq setting, needed when CONFIG_MALI_DVFS enabled */ 485 int (*set_freq)(int setting_clock_step); 486 /* Function that platfrom report it's clock info which driver can set, needed when CONFIG_MALI_DVFS enabled */ 487 void (*get_clock_info)(struct mali_gpu_clock **data); 488 /* Function that get the current clock info, needed when CONFIG_MALI_DVFS enabled */ 489 int (*get_freq)(void); 490 /* Function that init the mali gpu secure mode */ 491 int (*secure_mode_init)(void); 492 /* Function that deinit the mali gpu secure mode */ 493 void (*secure_mode_deinit)(void); 494 /* Function that reset GPU and enable gpu secure mode */ 495 int (*gpu_reset_and_secure_mode_enable)(void); 496 /* Function that Reset GPU and disable gpu secure mode */ 497 int (*gpu_reset_and_secure_mode_disable)(void); 498 /* ipa related interface customer need register */ 499 #if defined(CONFIG_MALI_DEVFREQ) && defined(CONFIG_DEVFREQ_THERMAL) 500 struct devfreq_cooling_power *gpu_cooling_ops; 501 #endif 502 }; 503 504 /** 505 * Pause the scheduling and power state changes of Mali device driver. 506 * mali_dev_resume() must always be called as soon as possible after this function 507 * in order to resume normal operation of the Mali driver. 508 */ 509 void mali_dev_pause(void); 510 511 /** 512 * Resume scheduling and allow power changes in Mali device driver. 513 * This must always be called after mali_dev_pause(). 514 */ 515 void mali_dev_resume(void); 516 517 /** @brief Set the desired number of PP cores to use. 518 * 519 * The internal Mali PMU will be used, if present, to physically power off the PP cores. 520 * 521 * @param num_cores The number of desired cores 522 * @return 0 on success, otherwise error. -EINVAL means an invalid number of cores was specified. 523 */ 524 int mali_perf_set_num_pp_cores(unsigned int num_cores); 525 526 #endif 527