1 /* 2 * Copyright (c) 2025-2026, Texas Instruments Incorporated - https://www.ti.com/ 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <ti_platform_defs.h> 11 12 #define TI_MAILBOX_TX_BASE UL(0x44240000) /* TFA sending IPC messages to TIFS */ 13 #define TI_MAILBOX_RX_BASE UL(0x44250000) /* TIFS sending IPC messages to A53 */ 14 15 /* We just need 512 bytes starting from TX/RX each, but simpler to just remap a 128K page */ 16 #define TI_MAILBOX_RX_TX_SIZE UL(0x20000) 17 18 #define WKUP_CTRL_MMR0_BASE UL(0x43000000) 19 #define WKUP_CTRL_MMR0_SIZE UL(0x80000) 20 21 #define WKUP_CTRL_MMR0_DEVICE_RESET_OFFSET UL(0x54000) 22 23 #define BL1_RO_BASE 0x70800000 /* SRAM base address used as readonly segment */ 24 #define BL1_RO_LIMIT 0x7080BFFF /* end of readonly segment */ 25 26 #define BL1_RW_BASE 0x7080D000 /* RW segment for data, stack and others */ 27 #ifdef DEBUG 28 /* 29 * HACK: Extended by 4K for debug builds to fit larger xlat tables. 30 * This build is NOT FUNCTIONAL - do not use in production. 31 */ 32 #define BL1_RW_LIMIT 0x70811000 /* end of RW segment (debug: +4K hack) */ 33 #else 34 #define BL1_RW_LIMIT 0x70810000 /* end of RW segment */ 35 #endif 36 37 #define BL2_BASE 0x80000000 /* BL2 base at start of DDR memory */ 38 #define BL2_LIMIT 0x100000000 /* BL2 limit */ 39 40 #define MAX_IO_HANDLES 1 41 #define MAX_IO_DEVICES 1 42 43 #define PLAT_PROC_START_ID U(32) 44 #define PLAT_PROC_DEVICE_START_ID U(135) 45 #define PLAT_CLUSTER_DEVICE_START_ID U(134) 46 #define PLAT_BOARD_DEVICE_ID U(157) 47 48 #define MAILBOX_SHMEM_REGION_BASE UL(0x70810000) 49 #define MAILBOX_SHMEM_REGION_SIZE UL(0x6000) 50 51 /* Pre-decided SRAM Addresses for sending and receiving messages */ 52 #define MAILBOX_TX_START_REGION UL(0x70814000) 53 #define MAILBOX_RX_START_REGION UL(0x70815000) 54 /* 1 slot in the memory buffer dedicated for IPC is 64 bytes */ 55 #define MAILBOX_RX_SLOT_SZ U(64) 56 /* There are 5 slots in the memory buffer dedicated for IPC */ 57 #define MAILBOX_RX_NUM_SLOTS U(5) 58 /* 59 * Pre-calculated MAX size of a message 60 * sec_hdr + (type/host/seq + flags) + payload 61 * 4 + 16 + 36 62 */ 63 #define MAILBOX_MAX_MESSAGE_SIZE U(56) 64 65 /* Ensure the RX Slot size is not smaller than the max message size */ 66 #if (MAILBOX_MAX_MESSAGE_SIZE > MAILBOX_RX_SLOT_SZ) 67 #error "MAILBOX_MAX_MESSAGE_SIZE > MAILBOX_RX_SLOT_SZ" 68 #endif 69 70 #endif /* PLATFORM_DEF_H */ 71