xref: /rk3399_ARM-atf/plat/ti/k3low/common/drivers/k3-ddrss/common/lpddr4_if.h (revision 6c0c3a74dda68e7ffc8bd6c156918ddbfea7e03a)
1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /*
3  * Cadence DDR Driver
4  *
5  * Copyright (C) 2012-2026 Cadence Design Systems, Inc.
6  * Copyright (C) 2018-2026 Texas Instruments Incorporated - https://www.ti.com/
7  */
8 
9 #ifndef LPDDR4_IF_H
10 #define LPDDR4_IF_H
11 
12 #include <inttypes.h>
13 #include <stdbool.h>
14 
15 #include <lpddr4_16bit_if.h>
16 
17 typedef struct ti_lpddr4_config_s ti_lpddr4_config;
18 typedef struct ti_lpddr4_privatedata_s ti_lpddr4_privatedata;
19 
20 typedef enum {
21 	LPDDR4_CTL_REGS		= 0U,
22 	LPDDR4_PHY_REGS		= 1U,
23 	LPDDR4_PHY_INDEP_REGS	= 2U
24 } ti_lpddr4_regblock;
25 
26 typedef enum {
27 	LPDDR4_DRV_NONE				= 0U,
28 	LPDDR4_DRV_SOC_PLL_UPDATE		= 1U,
29 	LPDDR4_DRV_SOC_PHY_REDUCED_FREQ		= 2U,
30 	LPDDR4_DRV_SOC_PHY_DATA_RET_ASSERT	= 3U,
31 	LPDDR4_DRV_SOC_PHY_DATA_RET_DEASSERT	= 4U
32 } ti_lpddr4_infotype;
33 
34 typedef void (*lpddr4_infocallback)(const ti_lpddr4_privatedata *pd, ti_lpddr4_infotype infotype);
35 
36 typedef void (*lpddr4_ctlcallback)(const ti_lpddr4_privatedata *pd,
37 				   ti_lpddr4_intr_ctlinterrupt ctlinterrupt,
38 				   uint8_t chipselect);
39 
40 typedef void (*lpddr4_phyindepcallback)(const ti_lpddr4_privatedata *pd,
41 					ti_lpddr4_intr_phyindepinterrupt phyindepinterrupt,
42 					uint8_t chipselect);
43 
44 uint32_t ti_lpddr4_probe(const ti_lpddr4_config *config, uint16_t *configsize);
45 
46 uint32_t ti_lpddr4_init(ti_lpddr4_privatedata *pd, const ti_lpddr4_config *cfg);
47 
48 uint32_t ti_lpddr4_start(const ti_lpddr4_privatedata *pd);
49 
50 uint32_t ti_lpddr4_readreg(const ti_lpddr4_privatedata *pd, ti_lpddr4_regblock cpp,
51 			   uint32_t regoffset, uint32_t *regvalue);
52 
53 uint32_t ti_lpddr4_writereg(const ti_lpddr4_privatedata *pd, ti_lpddr4_regblock cpp,
54 			    uint32_t regoffset, uint32_t regvalue);
55 
56 uint32_t ti_lpddr4_writectlconfigex(const ti_lpddr4_privatedata *pd,
57 				    const uint32_t regvalues[], uint16_t regcount);
58 
59 uint32_t ti_lpddr4_writephyconfigex(const ti_lpddr4_privatedata *pd,
60 				    const uint32_t regvalues[], uint16_t regcount);
61 
62 uint32_t ti_lpddr4_writephyindepconfigex(const ti_lpddr4_privatedata *pd,
63 					 const uint32_t regvalues[], uint16_t regcount);
64 
65 uint32_t ti_lpddr4_checkctlinterrupt(const ti_lpddr4_privatedata *pd,
66 				     ti_lpddr4_intr_ctlinterrupt intr, bool *irqstatus);
67 
68 uint32_t ti_lpddr4_ackctlinterrupt(const ti_lpddr4_privatedata *pd,
69 				   ti_lpddr4_intr_ctlinterrupt intr);
70 
71 uint32_t ti_lpddr4_checkphyindepinterrupt(const ti_lpddr4_privatedata *pd,
72 					  ti_lpddr4_intr_phyindepinterrupt intr,
73 					  bool *irqstatus);
74 
75 uint32_t ti_lpddr4_ackphyindepinterrupt(const ti_lpddr4_privatedata *pd,
76 					ti_lpddr4_intr_phyindepinterrupt intr);
77 #endif  /* LPDDR4_IF_H */
78