1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2024, Linaro Limited 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #ifndef PLATFORM_CONFIG_H 8 #define PLATFORM_CONFIG_H 9 10 #include <mm/generic_ram_layout.h> 11 12 /* Make stacks aligned to data cache line length */ 13 #define STACK_ALIGNMENT 64 14 15 #if defined(PLATFORM_FLAVOR_kodiak) || defined(PLATFORM_FLAVOR_lemans) 16 /* GIC related constants */ 17 #define GICD_BASE UL(0x17a00000) 18 #define GICR_BASE UL(0x17a60000) 19 20 #define RAMBLUR_PIMEM_REG_BASE UL(0x610000) 21 #define SEC_PRNG_REG_BASE UL(0x010D1000) 22 #endif 23 24 #if defined(PLATFORM_FLAVOR_kodiak) 25 #define DRAM0_BASE UL(0x80000000) 26 #define DRAM0_SIZE UL(0x80000000) 27 #define DRAM1_BASE ULL(0x100000000) 28 #define DRAM1_SIZE ULL(0x100000000) 29 30 /* DDR reserved*/ 31 #define RAMBLUR_PIMEM_VAULT_TA_BASE ULL(0xc1800000) 32 #define RAMBLUR_PIMEM_VAULT_TA_SIZE ULL(0x01c00000) 33 34 #define GENI_UART_REG_BASE UL(0x994000) 35 #define GCC_BASE UL(0x100000) 36 #define GCC_SIZE UL(0x100000) 37 #define WPSS_BASE UL(0x8a00000) 38 #define WPSS_SIZE UL(0x200000) 39 #define TURING_BASE UL(0x09800000) 40 #define TURING_SIZE ULL(0x00e00000) 41 #define LPASS_BASE UL(0x02c00000) 42 #define LPASS_SIZE ULL(0x01080000) 43 #define IRIS_BASE UL(0x0aa00000) 44 #define IRIS_SIZE ULL(0x00200000) 45 #endif 46 47 #if defined(PLATFORM_FLAVOR_lemans) 48 #define DRAM0_BASE UL(0x80000000) 49 #define DRAM0_SIZE UL(0x380000000) 50 #define DRAM1_BASE ULL(0x800000000) 51 #define DRAM1_SIZE ULL(0x800000000) 52 53 /* DDR reserved*/ 54 #define RAMBLUR_PIMEM_VAULT_TA_BASE ULL(0xd1900000) 55 #define RAMBLUR_PIMEM_VAULT_TA_SIZE ULL(0x01c00000) 56 57 #define GENI_UART_REG_BASE UL(0xa8c000) 58 #endif 59 60 #define PAS_ID_QDSP6 1 61 #define PAS_ID_WPSS 6 62 #define PAS_ID_VENUS 9 63 #define PAS_ID_TURING 18 64 65 #endif /*PLATFORM_CONFIG_H*/ 66