1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * 4 * (C) COPYRIGHT 2019-2022 ARM Limited. All rights reserved. 5 * 6 * This program is free software and is provided to you under the terms of the 7 * GNU General Public License version 2 as published by the Free Software 8 * Foundation, and any use by you of this program is subject to the terms 9 * of such GNU license. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, you can access it online at 18 * http://www.gnu.org/licenses/gpl-2.0.html. 19 * 20 */ 21 #ifndef _KBASE_GPU_REGMAP_JM_H_ 22 #define _KBASE_GPU_REGMAP_JM_H_ 23 24 #if MALI_USE_CSF && defined(__KERNEL__) 25 #error "Cannot be compiled with CSF" 26 #endif 27 28 /* Set to implementation defined, outer caching */ 29 #define AS_MEMATTR_AARCH64_OUTER_IMPL_DEF 0x88ull 30 /* Set to write back memory, outer caching */ 31 #define AS_MEMATTR_AARCH64_OUTER_WA 0x8Dull 32 /* Set to inner non-cacheable, outer-non-cacheable 33 * Setting defined by the alloc bits is ignored, but set to a valid encoding: 34 * - no-alloc on read 35 * - no alloc on write 36 */ 37 #define AS_MEMATTR_AARCH64_NON_CACHEABLE 0x4Cull 38 39 /* Symbols for default MEMATTR to use 40 * Default is - HW implementation defined caching 41 */ 42 #define AS_MEMATTR_INDEX_DEFAULT 0 43 #define AS_MEMATTR_INDEX_DEFAULT_ACE 3 44 45 /* HW implementation defined caching */ 46 #define AS_MEMATTR_INDEX_IMPL_DEF_CACHE_POLICY 0 47 /* Force cache on */ 48 #define AS_MEMATTR_INDEX_FORCE_TO_CACHE_ALL 1 49 /* Write-alloc */ 50 #define AS_MEMATTR_INDEX_WRITE_ALLOC 2 51 /* Outer coherent, inner implementation defined policy */ 52 #define AS_MEMATTR_INDEX_OUTER_IMPL_DEF 3 53 /* Outer coherent, write alloc inner */ 54 #define AS_MEMATTR_INDEX_OUTER_WA 4 55 /* Normal memory, inner non-cacheable, outer non-cacheable (ARMv8 mode only) */ 56 #define AS_MEMATTR_INDEX_NON_CACHEABLE 5 57 58 /* GPU control registers */ 59 60 #define CORE_FEATURES 0x008 /* (RO) Shader Core Features */ 61 #define JS_PRESENT 0x01C /* (RO) Job slots present */ 62 63 #define PRFCNT_BASE_LO 0x060 /* (RW) Performance counter memory 64 * region base address, low word 65 */ 66 #define PRFCNT_BASE_HI 0x064 /* (RW) Performance counter memory 67 * region base address, high word 68 */ 69 #define PRFCNT_CONFIG 0x068 /* (RW) Performance counter 70 * configuration 71 */ 72 #define PRFCNT_JM_EN 0x06C /* (RW) Performance counter enable 73 * flags for Job Manager 74 */ 75 #define PRFCNT_SHADER_EN 0x070 /* (RW) Performance counter enable 76 * flags for shader cores 77 */ 78 #define PRFCNT_TILER_EN 0x074 /* (RW) Performance counter enable 79 * flags for tiler 80 */ 81 #define PRFCNT_MMU_L2_EN 0x07C /* (RW) Performance counter enable 82 * flags for MMU/L2 cache 83 */ 84 85 #define JS0_FEATURES 0x0C0 /* (RO) Features of job slot 0 */ 86 #define JS1_FEATURES 0x0C4 /* (RO) Features of job slot 1 */ 87 #define JS2_FEATURES 0x0C8 /* (RO) Features of job slot 2 */ 88 #define JS3_FEATURES 0x0CC /* (RO) Features of job slot 3 */ 89 #define JS4_FEATURES 0x0D0 /* (RO) Features of job slot 4 */ 90 #define JS5_FEATURES 0x0D4 /* (RO) Features of job slot 5 */ 91 #define JS6_FEATURES 0x0D8 /* (RO) Features of job slot 6 */ 92 #define JS7_FEATURES 0x0DC /* (RO) Features of job slot 7 */ 93 #define JS8_FEATURES 0x0E0 /* (RO) Features of job slot 8 */ 94 #define JS9_FEATURES 0x0E4 /* (RO) Features of job slot 9 */ 95 #define JS10_FEATURES 0x0E8 /* (RO) Features of job slot 10 */ 96 #define JS11_FEATURES 0x0EC /* (RO) Features of job slot 11 */ 97 #define JS12_FEATURES 0x0F0 /* (RO) Features of job slot 12 */ 98 #define JS13_FEATURES 0x0F4 /* (RO) Features of job slot 13 */ 99 #define JS14_FEATURES 0x0F8 /* (RO) Features of job slot 14 */ 100 #define JS15_FEATURES 0x0FC /* (RO) Features of job slot 15 */ 101 102 #define JS_FEATURES_REG(n) GPU_CONTROL_REG(JS0_FEATURES + ((n) << 2)) 103 104 #define JM_CONFIG 0xF00 /* (RW) Job manager configuration (implementation-specific) */ 105 106 /* Job control registers */ 107 108 #define JOB_IRQ_JS_STATE 0x010 /* status==active and _next == busy snapshot from last JOB_IRQ_CLEAR */ 109 #define JOB_IRQ_THROTTLE 0x014 /* cycles to delay delivering an interrupt externally. The JOB_IRQ_STATUS is NOT affected by this, just the delivery of the interrupt. */ 110 111 #define JOB_SLOT1 0x880 /* Configuration registers for job slot 1 */ 112 #define JOB_SLOT2 0x900 /* Configuration registers for job slot 2 */ 113 #define JOB_SLOT3 0x980 /* Configuration registers for job slot 3 */ 114 #define JOB_SLOT4 0xA00 /* Configuration registers for job slot 4 */ 115 #define JOB_SLOT5 0xA80 /* Configuration registers for job slot 5 */ 116 #define JOB_SLOT6 0xB00 /* Configuration registers for job slot 6 */ 117 #define JOB_SLOT7 0xB80 /* Configuration registers for job slot 7 */ 118 #define JOB_SLOT8 0xC00 /* Configuration registers for job slot 8 */ 119 #define JOB_SLOT9 0xC80 /* Configuration registers for job slot 9 */ 120 #define JOB_SLOT10 0xD00 /* Configuration registers for job slot 10 */ 121 #define JOB_SLOT11 0xD80 /* Configuration registers for job slot 11 */ 122 #define JOB_SLOT12 0xE00 /* Configuration registers for job slot 12 */ 123 #define JOB_SLOT13 0xE80 /* Configuration registers for job slot 13 */ 124 #define JOB_SLOT14 0xF00 /* Configuration registers for job slot 14 */ 125 #define JOB_SLOT15 0xF80 /* Configuration registers for job slot 15 */ 126 127 #define JS_XAFFINITY 0x1C /* (RO) Extended affinity mask for job slot n*/ 128 129 #define JS_COMMAND 0x20 /* (WO) Command register for job slot n */ 130 #define JS_STATUS 0x24 /* (RO) Status register for job slot n */ 131 132 #define JS_XAFFINITY_NEXT 0x5C /* (RW) Next extended affinity mask for job slot n */ 133 134 #define JS_FLUSH_ID_NEXT 0x70 /* (RW) Next job slot n cache flush ID */ 135 136 /* No JM-specific MMU control registers */ 137 /* No JM-specific MMU address space control registers */ 138 139 /* JS_COMMAND register commands */ 140 #define JS_COMMAND_NOP 0x00 /* NOP Operation. Writing this value is ignored */ 141 #define JS_COMMAND_START 0x01 /* Start processing a job chain. Writing this value is ignored */ 142 #define JS_COMMAND_SOFT_STOP 0x02 /* Gently stop processing a job chain */ 143 #define JS_COMMAND_HARD_STOP 0x03 /* Rudely stop processing a job chain */ 144 #define JS_COMMAND_SOFT_STOP_0 0x04 /* Execute SOFT_STOP if JOB_CHAIN_FLAG is 0 */ 145 #define JS_COMMAND_HARD_STOP_0 0x05 /* Execute HARD_STOP if JOB_CHAIN_FLAG is 0 */ 146 #define JS_COMMAND_SOFT_STOP_1 0x06 /* Execute SOFT_STOP if JOB_CHAIN_FLAG is 1 */ 147 #define JS_COMMAND_HARD_STOP_1 0x07 /* Execute HARD_STOP if JOB_CHAIN_FLAG is 1 */ 148 149 #define JS_COMMAND_MASK 0x07 /* Mask of bits currently in use by the HW */ 150 151 /* Possible values of JS_CONFIG and JS_CONFIG_NEXT registers */ 152 #define JS_CONFIG_START_FLUSH_NO_ACTION (0u << 0) 153 #define JS_CONFIG_START_FLUSH_CLEAN (1u << 8) 154 #define JS_CONFIG_START_FLUSH_INV_SHADER_OTHER (2u << 8) 155 #define JS_CONFIG_START_FLUSH_CLEAN_INVALIDATE (3u << 8) 156 #define JS_CONFIG_START_MMU (1u << 10) 157 #define JS_CONFIG_JOB_CHAIN_FLAG (1u << 11) 158 #define JS_CONFIG_END_FLUSH_NO_ACTION JS_CONFIG_START_FLUSH_NO_ACTION 159 #define JS_CONFIG_END_FLUSH_CLEAN (1u << 12) 160 #define JS_CONFIG_END_FLUSH_CLEAN_INVALIDATE (3u << 12) 161 #define JS_CONFIG_ENABLE_FLUSH_REDUCTION (1u << 14) 162 #define JS_CONFIG_DISABLE_DESCRIPTOR_WR_BK (1u << 15) 163 #define JS_CONFIG_THREAD_PRI(n) ((n) << 16) 164 165 /* JS_XAFFINITY register values */ 166 #define JS_XAFFINITY_XAFFINITY_ENABLE (1u << 0) 167 #define JS_XAFFINITY_TILER_ENABLE (1u << 8) 168 #define JS_XAFFINITY_CACHE_ENABLE (1u << 16) 169 170 /* JS_STATUS register values */ 171 172 /* NOTE: Please keep this values in sync with enum base_jd_event_code in mali_base_kernel.h. 173 * The values are separated to avoid dependency of userspace and kernel code. 174 */ 175 176 /* Group of values representing the job status instead of a particular fault */ 177 #define JS_STATUS_NO_EXCEPTION_BASE 0x00 178 #define JS_STATUS_INTERRUPTED (JS_STATUS_NO_EXCEPTION_BASE + 0x02) /* 0x02 means INTERRUPTED */ 179 #define JS_STATUS_STOPPED (JS_STATUS_NO_EXCEPTION_BASE + 0x03) /* 0x03 means STOPPED */ 180 #define JS_STATUS_TERMINATED (JS_STATUS_NO_EXCEPTION_BASE + 0x04) /* 0x04 means TERMINATED */ 181 182 /* General fault values */ 183 #define JS_STATUS_FAULT_BASE 0x40 184 #define JS_STATUS_CONFIG_FAULT (JS_STATUS_FAULT_BASE) /* 0x40 means CONFIG FAULT */ 185 #define JS_STATUS_POWER_FAULT (JS_STATUS_FAULT_BASE + 0x01) /* 0x41 means POWER FAULT */ 186 #define JS_STATUS_READ_FAULT (JS_STATUS_FAULT_BASE + 0x02) /* 0x42 means READ FAULT */ 187 #define JS_STATUS_WRITE_FAULT (JS_STATUS_FAULT_BASE + 0x03) /* 0x43 means WRITE FAULT */ 188 #define JS_STATUS_AFFINITY_FAULT (JS_STATUS_FAULT_BASE + 0x04) /* 0x44 means AFFINITY FAULT */ 189 #define JS_STATUS_BUS_FAULT (JS_STATUS_FAULT_BASE + 0x08) /* 0x48 means BUS FAULT */ 190 191 /* Instruction or data faults */ 192 #define JS_STATUS_INSTRUCTION_FAULT_BASE 0x50 193 #define JS_STATUS_INSTR_INVALID_PC (JS_STATUS_INSTRUCTION_FAULT_BASE) /* 0x50 means INSTR INVALID PC */ 194 #define JS_STATUS_INSTR_INVALID_ENC (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x01) /* 0x51 means INSTR INVALID ENC */ 195 #define JS_STATUS_INSTR_TYPE_MISMATCH (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x02) /* 0x52 means INSTR TYPE MISMATCH */ 196 #define JS_STATUS_INSTR_OPERAND_FAULT (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x03) /* 0x53 means INSTR OPERAND FAULT */ 197 #define JS_STATUS_INSTR_TLS_FAULT (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x04) /* 0x54 means INSTR TLS FAULT */ 198 #define JS_STATUS_INSTR_BARRIER_FAULT (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x05) /* 0x55 means INSTR BARRIER FAULT */ 199 #define JS_STATUS_INSTR_ALIGN_FAULT (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x06) /* 0x56 means INSTR ALIGN FAULT */ 200 /* NOTE: No fault with 0x57 code defined in spec. */ 201 #define JS_STATUS_DATA_INVALID_FAULT (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x08) /* 0x58 means DATA INVALID FAULT */ 202 #define JS_STATUS_TILE_RANGE_FAULT (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x09) /* 0x59 means TILE RANGE FAULT */ 203 #define JS_STATUS_ADDRESS_RANGE_FAULT (JS_STATUS_INSTRUCTION_FAULT_BASE + 0x0A) /* 0x5A means ADDRESS RANGE FAULT */ 204 205 /* Other faults */ 206 #define JS_STATUS_MEMORY_FAULT_BASE 0x60 207 #define JS_STATUS_OUT_OF_MEMORY (JS_STATUS_MEMORY_FAULT_BASE) /* 0x60 means OUT OF MEMORY */ 208 #define JS_STATUS_UNKNOWN 0x7F /* 0x7F means UNKNOWN */ 209 210 /* JS<n>_FEATURES register */ 211 #define JS_FEATURE_NULL_JOB (1u << 1) 212 #define JS_FEATURE_SET_VALUE_JOB (1u << 2) 213 #define JS_FEATURE_CACHE_FLUSH_JOB (1u << 3) 214 #define JS_FEATURE_COMPUTE_JOB (1u << 4) 215 #define JS_FEATURE_VERTEX_JOB (1u << 5) 216 #define JS_FEATURE_GEOMETRY_JOB (1u << 6) 217 #define JS_FEATURE_TILER_JOB (1u << 7) 218 #define JS_FEATURE_FUSED_JOB (1u << 8) 219 #define JS_FEATURE_FRAGMENT_JOB (1u << 9) 220 221 /* JM_CONFIG register */ 222 #define JM_TIMESTAMP_OVERRIDE (1ul << 0) 223 #define JM_CLOCK_GATE_OVERRIDE (1ul << 1) 224 #define JM_JOB_THROTTLE_ENABLE (1ul << 2) 225 #define JM_JOB_THROTTLE_LIMIT_SHIFT (3) 226 #define JM_MAX_JOB_THROTTLE_LIMIT (0x3F) 227 #define JM_FORCE_COHERENCY_FEATURES_SHIFT (2) 228 229 /* GPU_COMMAND values */ 230 #define GPU_COMMAND_NOP 0x00 /* No operation, nothing happens */ 231 #define GPU_COMMAND_SOFT_RESET 0x01 /* Stop all external bus interfaces, and then reset the entire GPU. */ 232 #define GPU_COMMAND_HARD_RESET 0x02 /* Immediately reset the entire GPU. */ 233 #define GPU_COMMAND_PRFCNT_CLEAR 0x03 /* Clear all performance counters, setting them all to zero. */ 234 #define GPU_COMMAND_PRFCNT_SAMPLE 0x04 /* Sample all performance counters, writing them out to memory */ 235 #define GPU_COMMAND_CYCLE_COUNT_START 0x05 /* Starts the cycle counter, and system timestamp propagation */ 236 #define GPU_COMMAND_CYCLE_COUNT_STOP 0x06 /* Stops the cycle counter, and system timestamp propagation */ 237 #define GPU_COMMAND_CLEAN_CACHES 0x07 /* Clean all caches */ 238 #define GPU_COMMAND_CLEAN_INV_CACHES 0x08 /* Clean and invalidate all caches */ 239 #define GPU_COMMAND_SET_PROTECTED_MODE 0x09 /* Places the GPU in protected mode */ 240 241 /* GPU_COMMAND cache flush alias to CSF command payload */ 242 #define GPU_COMMAND_CACHE_CLN_INV_L2 GPU_COMMAND_CLEAN_INV_CACHES 243 #define GPU_COMMAND_CACHE_CLN_INV_L2_LSC GPU_COMMAND_CLEAN_INV_CACHES 244 #define GPU_COMMAND_CACHE_CLN_INV_FULL GPU_COMMAND_CLEAN_INV_CACHES 245 #define GPU_COMMAND_CACHE_CLN_INV_LSC GPU_COMMAND_CLEAN_INV_CACHES 246 247 /* Merge cache flush commands */ 248 #define GPU_COMMAND_FLUSH_CACHE_MERGE(cmd1, cmd2) \ 249 ((cmd1) > (cmd2) ? (cmd1) : (cmd2)) 250 251 /* IRQ flags */ 252 #define GPU_FAULT (1 << 0) /* A GPU Fault has occurred */ 253 #define MULTIPLE_GPU_FAULTS (1 << 7) /* More than one GPU Fault occurred. */ 254 #define RESET_COMPLETED (1 << 8) /* Set when a reset has completed. */ 255 #define POWER_CHANGED_SINGLE (1 << 9) /* Set when a single core has finished powering up or down. */ 256 #define POWER_CHANGED_ALL (1 << 10) /* Set when all cores have finished powering up or down. */ 257 #define PRFCNT_SAMPLE_COMPLETED (1 << 16) /* Set when a performance count sample has completed. */ 258 #define CLEAN_CACHES_COMPLETED (1 << 17) /* Set when a cache clean operation has completed. */ 259 #define FLUSH_PA_RANGE_COMPLETED \ 260 (1 << 20) /* Set when a physical range cache clean operation has completed. */ 261 262 /* 263 * In Debug build, 264 * GPU_IRQ_REG_COMMON | POWER_CHANGED_SINGLE is used to clear and enable interupts sources of GPU_IRQ 265 * by writing it onto GPU_IRQ_CLEAR/MASK registers. 266 * 267 * In Release build, 268 * GPU_IRQ_REG_COMMON is used. 269 * 270 * Note: 271 * CLEAN_CACHES_COMPLETED - Used separately for cache operation. 272 */ 273 #define GPU_IRQ_REG_COMMON (GPU_FAULT | MULTIPLE_GPU_FAULTS | RESET_COMPLETED \ 274 | POWER_CHANGED_ALL | PRFCNT_SAMPLE_COMPLETED) 275 276 #endif /* _KBASE_GPU_REGMAP_JM_H_ */ 277