1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd. 4 * Copyright (C) 2019, Theobroma Systems Design und Consulting GmbH 5 * Copyright (c) 2024, Rockchip, Inc. All rights reserved. 6 */ 7 8 #ifndef PLATFORM_CONFIG_H 9 #define PLATFORM_CONFIG_H 10 11 #include <mm/generic_ram_layout.h> 12 13 /* Make stacks aligned to data cache line length */ 14 #define STACK_ALIGNMENT 64 15 16 #define SIZE_K(n) ((n) * 1024) 17 #define SIZE_M(n) ((n) * 1024 * 1024) 18 19 #if defined(PLATFORM_FLAVOR_rk322x) 20 21 #define GIC_BASE 0x32010000 22 #define GIC_SIZE SIZE_K(64) 23 #define GICD_BASE (GIC_BASE + 0x1000) 24 #define GICC_BASE (GIC_BASE + 0x2000) 25 26 #define SGRF_BASE 0x10140000 27 #define SGRF_SIZE SIZE_K(64) 28 29 #define DDRSGRF_BASE 0x10150000 30 #define DDRSGRF_SIZE SIZE_K(64) 31 32 #define GRF_BASE 0x11000000 33 #define GRF_SIZE SIZE_K(64) 34 35 #define UART2_BASE 0x11030000 36 #define UART2_SIZE SIZE_K(64) 37 38 #define CRU_BASE 0x110e0000 39 #define CRU_SIZE SIZE_K(64) 40 41 /* Internal SRAM */ 42 #define ISRAM_BASE 0x10080000 43 #define ISRAM_SIZE SIZE_K(8) 44 45 #elif defined(PLATFORM_FLAVOR_rk3399) 46 47 #define MMIO_BASE 0xF8000000 48 49 #define GIC_BASE (MMIO_BASE + 0x06E00000) 50 #define GIC_SIZE SIZE_M(2) 51 #define GICC_BASE (MMIO_BASE + 0x07F00000) 52 #define GICD_BASE GIC_BASE 53 #define GICR_BASE (GIC_BASE + SIZE_M(1)) 54 55 #define UART0_BASE (MMIO_BASE + 0x07180000) 56 #define UART0_SIZE SIZE_K(64) 57 58 #define UART1_BASE (MMIO_BASE + 0x07190000) 59 #define UART1_SIZE SIZE_K(64) 60 61 #define UART2_BASE (MMIO_BASE + 0x071A0000) 62 #define UART2_SIZE SIZE_K(64) 63 64 #define UART3_BASE (MMIO_BASE + 0x071B0000) 65 #define UART3_SIZE SIZE_K(64) 66 67 #define SGRF_BASE (MMIO_BASE + 0x07330000) 68 #define SGRF_SIZE SIZE_K(64) 69 70 #elif defined(PLATFORM_FLAVOR_px30) 71 72 #define GIC_BASE 0xff130000 73 #define GIC_SIZE SIZE_K(64) 74 #define GICD_BASE (GIC_BASE + 0x1000) 75 #define GICC_BASE (GIC_BASE + 0x2000) 76 77 #define UART1_BASE 0xff158000 78 #define UART1_SIZE SIZE_K(64) 79 80 #define UART2_BASE 0xff160000 81 #define UART2_SIZE SIZE_K(64) 82 83 #define UART5_BASE 0xff178000 84 #define UART5_SIZE SIZE_K(64) 85 86 #define FIREWALL_DDR_BASE 0xff534000 87 #define FIREWALL_DDR_SIZE SIZE_K(16) 88 89 #elif defined(PLATFORM_FLAVOR_rk3588) 90 91 #define GIC_BASE 0xfe600000 92 #define GIC_SIZE SIZE_K(64) 93 #define GICC_BASE 0 94 #define GICD_BASE GIC_BASE 95 #define GICR_BASE (GIC_BASE + 0x80000) 96 97 #define UART0_BASE 0xfd890000 98 #define UART0_SIZE SIZE_K(64) 99 100 #define UART1_BASE 0xfeb40000 101 #define UART1_SIZE SIZE_K(64) 102 103 #define UART2_BASE 0xfeb50000 104 #define UART2_SIZE SIZE_K(64) 105 106 #define UART3_BASE 0xfeb60000 107 #define UART3_SIZE SIZE_K(64) 108 109 #define FIREWALL_DDR_BASE 0xfe030000 110 #define FIREWALL_DDR_SIZE SIZE_K(32) 111 112 #define FIREWALL_DSU_BASE 0xfe010000 113 #define FIREWALL_DSU_SIZE SIZE_K(32) 114 115 #define TRNG_S_BASE 0xfe398000 116 #define TRNG_S_SIZE SIZE_K(32) 117 118 #define OTP_S_BASE 0xfe3a0000 119 #define OTP_S_SIZE SIZE_K(64) 120 121 #define ROCKCHIP_OTP_HUK_INDEX 0x104 122 #define ROCKCHIP_OTP_HUK_SIZE 0x4 123 124 #else 125 #error "Unknown platform flavor" 126 #endif 127 128 #ifdef CFG_WITH_LPAE 129 #define MAX_XLAT_TABLES 5 130 #endif 131 132 #endif 133