1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 /* 3 * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd 4 * 5 * author: 6 * Alpha Lin, alpha.lin@rock-chips.com 7 * 8 */ 9 10 #ifndef __ROCKCHIP_IEP2_REGS_H__ 11 #define __ROCKCHIP_IEP2_REGS_H__ 12 13 #define IEP2_REG_FRM_START 0x0000 14 #define IEP2_REG_FRM_EN BIT(0) 15 #define IEP2_REG_IEP_CONFIG0 0x0004 16 #define IEP2_REG_CCLK_SRESET_P BIT(22) 17 #define IEP2_REG_ACLK_SRESET_P BIT(21) 18 #define IEP2_REG_HANDSAVE_P BIT(20) 19 #define IEP2_REG_RST_PROTECT_EN BIT(19) 20 #define IEP2_REG_DEBUG_DATA_EN BIT(16) 21 #define IEP2_REG_DST_YUV_SWAP(x) (((x) & 3) << 12) 22 #define IEP2_REG_DST_FMT(x) (((x) & 3) << 8) 23 #define IEP2_REG_SRC_YUV_SWAP(x) (((x) & 3) << 4) 24 #define IEP2_REG_SRC_FMT(x) ((x) & 3) 25 #define IEP2_REG_WORK_MODE 0x0008 26 #define IEP2_REG_IEP2_MODE BIT(0) 27 #define IEP2_REG_GATING_CTRL 0x0010 28 #define IEP2_REG_REG_CLK_ON BIT(11) 29 #define IEP2_REG_DMA_CLK_ON BIT(10) 30 #define IEP2_REG_RAM_CLK_ON BIT(9) 31 #define IEP2_REG_CTRL_CLK_ON BIT(8) 32 #define IEP2_REG_OUT_CLK_ON BIT(7) 33 #define IEP2_REG_BLE_CLK_ON BIT(6) 34 #define IEP2_REG_EEDI_CLK_ON BIT(5) 35 #define IEP2_REG_MC_CLK_ON BIT(4) 36 #define IEP2_REG_ME_CLK_ON BIT(3) 37 #define IEP2_REG_DECT_CLK_ON BIT(2) 38 #define IEP2_REG_MD_CLK_ON BIT(1) 39 #define IEP2_REG_CLK_ON BIT(0) 40 #define IEP2_REG_STATUS 0x0014 41 #define IEP2_REG_ARST_FINISH_DONE BIT(0) 42 #define IEP2_REG_INT_EN 0x0020 43 #define IEP2_REG_TIMEOUT_EN BIT(5) 44 #define IEP2_REG_BUS_ERROR_EN BIT(4) 45 #define IEP2_REG_OSD_MAX_EN BIT(1) 46 #define IEP2_REG_FRM_DONE_EN BIT(0) 47 #define IEP2_REG_INT_CLR 0x0024 48 #define IEP2_REG_TIMEOUT_CLR BIT(5) 49 #define IEP2_REG_BUS_ERROR_CLR BIT(4) 50 #define IEP2_REG_OSD_MAX_CLR BIT(1) 51 #define IEP2_REG_FRM_DONE_CLR BIT(0) 52 #define IEP2_REG_INT_STS 0x0028 53 #define IEP2_REG_RO_TIMEOUT_STS(x) ((x) & BIT(5)) 54 #define IEP2_REG_RO_BUS_ERROR_STS(x) ((x) & BIT(4)) 55 #define IEP2_REG_RO_OSD_MAX_STS(x) ((x) & BIT(1)) 56 #define IEP2_REG_RO_FRM_DONE_STS(x) ((x) & BIT(0)) 57 #define IEP2_REG_RO_VALID_INT_STS(x) ((x) & (BIT(5) | BIT(4) | BIT(0))) 58 #define IEP2_REG_INT_RAW_STS 0x002c 59 #define IEP2_REG_VIR_SRC_IMG_WIDTH 0x0030 60 #define IEP2_REG_SRC_VIR_UV_STRIDE(x) (((x) & 0xffff) << 16) 61 #define IEP2_REG_SRC_VIR_Y_STRIDE(x) ((x) & 0xffff) 62 #define IEP2_REG_VIR_DST_IMG_WIDTH 0x0034 63 #define IEP2_REG_DST_VIR_STRIDE(x) ((x) & 0xffff) 64 #define IEP2_REG_SRC_IMG_SIZE 0x0038 65 #define IEP2_REG_SRC_PIC_HEIGHT(x) (((x) & 0x7ff) << 16) 66 #define IEP2_REG_SRC_PIC_WIDTH(x) ((x) & 0x7ff) 67 #define IEP2_REG_DIL_CONFIG0 0x0040 68 #define IEP2_REG_DIL_MV_HIST_EN BIT(17) 69 #define IEP2_REG_DIL_ROI_EN BIT(16) 70 #define IEP2_REG_DIL_COMB_EN BIT(15) 71 #define IEP2_REG_DIL_BLE_EN BIT(14) 72 #define IEP2_REG_DIL_EEDI_EN BIT(13) 73 #define IEP2_REG_DIL_MEMC_EN BIT(12) 74 #define IEP2_REG_DIL_OSD_EN BIT(11) 75 #define IEP2_REG_DIL_PD_EN BIT(10) 76 #define IEP2_REG_DIL_FF_EN BIT(9) 77 #define IEP2_REG_DIL_MD_PRE_EN BIT(8) 78 #define IEP2_REG_DIL_FIELD_ORDER(x) (((x) & 1) << 5) 79 #define IEP2_REG_DIL_OUT_MODE(x) (((x) & 1) << 4) 80 #define IEP2_REG_DIL_MODE(x) ((x) & 0xf) 81 #define IEP2_REG_TIMEOUT_CFG 0x0050 82 #define IEP2_REG_TIMEOUT_CFG_EN BIT(31) 83 #define IEP2_REG_DBG_FRM_CNT 0x0058 84 #define IEP2_REG_DBG_TIMEOUT_CNT 0x005c 85 #define IEP2_REG_SRC_ADDR_CURY 0x0060 86 #define IEP2_REG_SRC_ADDR_NXTY 0x0064 87 #define IEP2_REG_SRC_ADDR_PREY 0x0068 88 #define IEP2_REG_SRC_ADDR_CURUV 0x006c 89 #define IEP2_REG_SRC_ADDR_CURV 0x0070 90 #define IEP2_REG_SRC_ADDR_NXTUV 0x0074 91 #define IEP2_REG_SRC_ADDR_NXTV 0x0078 92 #define IEP2_REG_SRC_ADDR_PREUV 0x007c 93 #define IEP2_REG_SRC_ADDR_PREV 0x0080 94 #define IEP2_REG_SRC_ADDR_MD 0x0084 95 #define IEP2_REG_SRC_ADDR_MV 0x0088 96 #define IEP2_REG_ROI_ADDR 0x008c 97 #define IEP2_REG_DST_ADDR_TOPY 0x00b0 98 #define IEP2_REG_DST_ADDR_BOTY 0x00b4 99 #define IEP2_REG_DST_ADDR_TOPC 0x00b8 100 #define IEP2_REG_DST_ADDR_BOTC 0x00bc 101 #define IEP2_REG_DST_ADDR_MD 0x00c0 102 #define IEP2_REG_DST_ADDR_MV 0x00c4 103 #define IEP2_REG_MD_CONFIG0 0x00e0 104 #define IEP2_REG_MD_THETA(x) (((x) & 3) << 8) 105 #define IEP2_REG_MD_R(x) (((x) & 0xf) << 4) 106 #define IEP2_REG_MD_LAMBDA(x) ((x) & 0xf) 107 #define IEP2_REG_DECT_CONFIG0 0x00e4 108 #define IEP2_REG_OSD_GRADV_THR(x) (((x) & 0xff) << 24) 109 #define IEP2_REG_OSD_GRADH_THR(x) (((x) & 0xff) << 16) 110 #define IEP2_REG_OSD_AREA_NUM(x) (((x) & 0xf) << 8) 111 #define IEP2_REG_DECT_RESI_THR(x) ((x) & 0xff) 112 #define IEP2_REG_OSD_LIMIT_CONFIG 0x00f0 113 #define IEP2_REG_OSD_POS_LIMIT_NUM(x) (((x) & 7) << 4) 114 #define IEP2_REG_OSD_POS_LIMIT_EN BIT(0) 115 #define IEP2_REG_OSD_LIMIT_AREA(i) (0x00f4 + ((i) * 4)) 116 #define IEP2_REG_OSD_CONFIG0 0x00fc 117 #define IEP2_REG_OSD_LINE_NUM(x) (((x) & 0x1ff) << 16) 118 #define IEP2_REG_OSD_PEC_THR(x) ((x) & 0x7ff) 119 #define IEP2_REG_OSD_AREA_CONF(i) (0x0100 + ((i) * 4)) 120 #define IEP2_REG_OSD_Y_END(x) (((x) & 0x1ff) << 23) 121 #define IEP2_REG_OSD_Y_STA(x) (((x) & 0x1ff) << 14) 122 #define IEP2_REG_OSD_X_END(x) (((x) & 0x7f) << 7) 123 #define IEP2_REG_OSD_X_STA(x) ((x) & 0x7f) 124 #define IEP2_REG_ME_CONFIG0 0x0120 125 #define IEP2_REG_ME_THR_OFFSET(x) (((x) & 0xff) << 16) 126 #define IEP2_REG_MV_SIMILAR_NUM_THR0(x) (((x) & 0xf) << 12) 127 #define IEP2_REG_MV_SIMILAR_THR(x) (((x) & 0xf) << 8) 128 #define IEP2_REG_MV_BONUS(x) (((x) & 0xf) << 4) 129 #define IEP2_REG_ME_PENA(x) ((x) & 0xf) 130 #define IEP2_REG_ME_LIMIT_CONFIG 0x0124 131 #define IEP2_REG_MV_RIGHT_LIMIT(x) (((x) & 0x3f) << 8) 132 #define IEP2_REG_MV_LEFT_LIMIT(x) ((x) & 0x3f) 133 #define IEP2_REG_MV_TRU_LIST(i) (0x0128 + ((i) * 4)) 134 #define IEP2_REG_MV_TRU_LIST3_7(x) (((x) & 0x3f) << 26) 135 #define IEP2_REG_MV_TRU_LIST3_7_VLD BIT(24) 136 #define IEP2_REG_MV_TRU_LIST2_6(x) (((x) & 0x3f) << 18) 137 #define IEP2_REG_MV_TRU_LIST2_6_VLD BIT(16) 138 #define IEP2_REG_MV_TRU_LIST1_5(x) (((x) & 0x3f) << 10) 139 #define IEP2_REG_MV_TRU_LIST1_5_VLD BIT(8) 140 #define IEP2_REG_MV_TRU_LIST0_4(x) (((x) & 0x3f) << 2) 141 #define IEP2_REG_MV_TRU_LIST0_4_VLD BIT(0) 142 #define IEP2_REG_EEDI_CONFIG0 0x0130 143 #define IEP2_REG_EEDI_THR0(x) ((x) & 0x1f) 144 #define IEP2_REG_BLE_CONFIG0 0x0134 145 #define IEP2_REG_BLE_BACKTOMA_NUM(x) ((x) & 7) 146 #define IEP2_REG_COMB_CONFIG0 0x0138 147 #define IEP2_REG_COMB_CNT_THR(x) (((x) & 0xf) << 24) 148 #define IEP2_REG_COMB_FEATRUE_THR(x) (((x) & 0x3f) << 16) 149 #define IEP2_REG_COMB_T_THR(x) (((x) & 0xff) << 8) 150 #define IEP2_REG_COMB_OSD_VLD(i) BIT(i) 151 #define IEP2_REG_DIL_MTN_TAB(i) (0x0140 + ((i) * 4)) 152 #define IEP2_REG_MTN_SUB_TAB3_7_11_15(x) (((x) & 0x7f) << 24) 153 #define IEP2_REG_MTN_SUB_TAB2_6_10_14(x) (((x) & 0x7f) << 16) 154 #define IEP2_REG_MTN_SUB_TAB1_5_9_13(x) (((x) & 0x7f) << 8) 155 #define IEP2_REG_MTN_SUB_TAB0_4_8_12(x) ((x) & 0x7f) 156 #define IEP2_REG_RO_PD_TCNT 0x0400 157 #define IEP2_REG_RO_PD_BCNT 0x0404 158 #define IEP2_REG_RO_FF_CUR_TCNT 0x0408 159 #define IEP2_REG_RO_FF_CUR_BCNT 0x040c 160 #define IEP2_REG_RO_FF_NXT_TCNT 0x0410 161 #define IEP2_REG_RO_FF_NXT_BCNT 0x0414 162 #define IEP2_REG_RO_FF_BLE_TCNT 0x0418 163 #define IEP2_REG_RO_FF_BLE_BCNT 0x041c 164 #define IEP2_REG_RO_FF_COMB_NZ 0x0420 165 #define IEP2_REG_RO_FF_COMB_F 0x0424 166 #define IEP2_REG_RO_OSD_NUM 0x0428 167 #define IEP2_REG_RO_COMB_CNT 0x042c 168 #define IEP2_REG_RO_OUT_OSD_COMB_CNT(x) ((x) >> 16) 169 #define IEP2_REG_RO_OUT_COMB_CNT(x) ((x) & 0xffff) 170 #define IEP2_REG_RO_FF_GRADT_TCNT 0x0430 171 #define IEP2_REG_RO_FF_GRADT_BCNT 0x0434 172 #define IEP2_REG_RO_OSD_AREA_X(i) (0x0440 + ((i) * 8)) 173 #define IEP2_REG_RO_X_END(x) (((x) >> 16) & 0x7ff) 174 #define IEP2_REG_RO_X_STA(x) ((x) & 0x7ff) 175 #define IEP2_REG_RO_OSD_AREA_Y(i) (0x0444 + ((i) * 8)) 176 #define IEP2_REG_RO_Y_END(x) (((x) >> 16) & 0x7ff) 177 #define IEP2_REG_RO_Y_STA(x) ((x) & 0x7ff) 178 #define IEP2_REG_RO_MV_HIST_BIN(i) (0x480 + ((i) * 4)) 179 #define IEP2_REG_RO_MV_HIST_ODD(x) ((x) >> 16) 180 #define IEP2_REG_RO_MV_HIST_EVEN(x) ((x) & 0xffff) 181 182 #endif 183 184