1 /*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Include file for Alchemy Semiconductor's Au1k CPU.
5 *
6 * Copyright 2000,2001 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * SPDX-License-Identifier: GPL-2.0+
11 */
12
13 /*
14 * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
15 */
16
17 #ifndef _AU1X00_H_
18 #define _AU1X00_H_
19
20 #ifndef __ASSEMBLY__
21 /* cpu pipeline flush */
au_sync(void)22 void static inline au_sync(void)
23 {
24 __asm__ volatile ("sync");
25 }
26
au_sync_udelay(int us)27 void static inline au_sync_udelay(int us)
28 {
29 __asm__ volatile ("sync");
30 udelay(us);
31 }
32
au_writeb(u8 val,int reg)33 void static inline au_writeb(u8 val, int reg)
34 {
35 *(volatile u8 *)(reg) = val;
36 }
37
au_writew(u16 val,int reg)38 void static inline au_writew(u16 val, int reg)
39 {
40 *(volatile u16 *)(reg) = val;
41 }
42
au_writel(u32 val,int reg)43 void static inline au_writel(u32 val, int reg)
44 {
45 *(volatile u32 *)(reg) = val;
46 }
47
au_readb(unsigned long port)48 static inline u8 au_readb(unsigned long port)
49 {
50 return (*(volatile u8 *)port);
51 }
52
au_readw(unsigned long port)53 static inline u16 au_readw(unsigned long port)
54 {
55 return (*(volatile u16 *)port);
56 }
57
au_readl(unsigned long port)58 static inline u32 au_readl(unsigned long port)
59 {
60 return (*(volatile u32 *)port);
61 }
62
63 /* These next three functions should be a generic part of the MIPS
64 * kernel (with the 'au_' removed from the name) and selected for
65 * processors that support the instructions.
66 * Taken from PPC tree. -- Dan
67 */
68 /* Return the bit position of the most significant 1 bit in a word */
__ilog2(unsigned int x)69 static __inline__ int __ilog2(unsigned int x)
70 {
71 int lz;
72
73 asm volatile (
74 ".set\tnoreorder\n\t"
75 ".set\tnoat\n\t"
76 ".set\tmips32\n\t"
77 "clz\t%0,%1\n\t"
78 ".set\tmips0\n\t"
79 ".set\tat\n\t"
80 ".set\treorder"
81 : "=r" (lz)
82 : "r" (x));
83
84 return 31 - lz;
85 }
86
au_ffz(unsigned int x)87 static __inline__ int au_ffz(unsigned int x)
88 {
89 if ((x = ~x) == 0)
90 return 32;
91 return __ilog2(x & -x);
92 }
93
94 /*
95 * ffs: find first bit set. This is defined the same way as
96 * the libc and compiler builtin ffs routines, therefore
97 * differs in spirit from the above ffz (man ffs).
98 */
au_ffs(int x)99 static __inline__ int au_ffs(int x)
100 {
101 return __ilog2(x & -x) + 1;
102 }
103
104 #define gpio_set(Value) outl(Value, SYS_OUTPUTSET)
105 #define gpio_clear(Value) outl(Value, SYS_OUTPUTCLR)
106 #define gpio_read() inl(SYS_PINSTATERD)
107 #define gpio_tristate(Value) outl(Value, SYS_TRIOUTCLR)
108
109 #endif /* !ASSEMBLY */
110
111 #ifdef CONFIG_PM
112 /* no CP0 timer irq */
113 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
114 #else
115 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
116 #endif
117
118 #define CP0_IWATCHLO $18,1
119 #define CP0_DEBUG $23
120
121 /* SDRAM Controller */
122 #ifdef CONFIG_SOC_AU1550
123
124 #define MEM_SDMODE0 0xB4000800
125 #define MEM_SDMODE1 0xB4000808
126 #define MEM_SDMODE2 0xB4000810
127
128 #define MEM_SDADDR0 0xB4000820
129 #define MEM_SDADDR1 0xB4000828
130 #define MEM_SDADDR2 0xB4000830
131
132 #define MEM_SDCONFIGA 0xB4000840
133 #define MEM_SDCONFIGB 0xB4000848
134 #define MEM_SDPRECMD 0xB40008c0
135 #define MEM_SDAUTOREF 0xB40008c8
136
137 #define MEM_SDWRMD0 0xB4000880
138 #define MEM_SDWRMD1 0xB4000888
139 #define MEM_SDWRMD2 0xB4000890
140
141 #else /* CONFIG_SOC_AU1550 */
142
143 #define MEM_SDMODE0 0xB4000000
144 #define MEM_SDMODE1 0xB4000004
145 #define MEM_SDMODE2 0xB4000008
146
147 #define MEM_SDADDR0 0xB400000C
148 #define MEM_SDADDR1 0xB4000010
149 #define MEM_SDADDR2 0xB4000014
150
151 #define MEM_SDREFCFG 0xB4000018
152 #define MEM_SDPRECMD 0xB400001C
153 #define MEM_SDAUTOREF 0xB4000020
154
155 #define MEM_SDWRMD0 0xB4000024
156 #define MEM_SDWRMD1 0xB4000028
157 #define MEM_SDWRMD2 0xB400002C
158
159 #endif /* CONFIG_SOC_AU1550 */
160
161 #define MEM_SDSLEEP 0xB4000030
162 #define MEM_SDSMCKE 0xB4000034
163
164 /* Static Bus Controller */
165 #define MEM_STCFG0 0xB4001000
166 #define MEM_STTIME0 0xB4001004
167 #define MEM_STADDR0 0xB4001008
168
169 #define MEM_STCFG1 0xB4001010
170 #define MEM_STTIME1 0xB4001014
171 #define MEM_STADDR1 0xB4001018
172
173 #define MEM_STCFG2 0xB4001020
174 #define MEM_STTIME2 0xB4001024
175 #define MEM_STADDR2 0xB4001028
176
177 #define MEM_STCFG3 0xB4001030
178 #define MEM_STTIME3 0xB4001034
179 #define MEM_STADDR3 0xB4001038
180
181 /* Interrupt Controller 0 */
182 #define IC0_CFG0RD 0xB0400040
183 #define IC0_CFG0SET 0xB0400040
184 #define IC0_CFG0CLR 0xB0400044
185
186 #define IC0_CFG1RD 0xB0400048
187 #define IC0_CFG1SET 0xB0400048
188 #define IC0_CFG1CLR 0xB040004C
189
190 #define IC0_CFG2RD 0xB0400050
191 #define IC0_CFG2SET 0xB0400050
192 #define IC0_CFG2CLR 0xB0400054
193
194 #define IC0_REQ0INT 0xB0400054
195 #define IC0_SRCRD 0xB0400058
196 #define IC0_SRCSET 0xB0400058
197 #define IC0_SRCCLR 0xB040005C
198 #define IC0_REQ1INT 0xB040005C
199
200 #define IC0_ASSIGNRD 0xB0400060
201 #define IC0_ASSIGNSET 0xB0400060
202 #define IC0_ASSIGNCLR 0xB0400064
203
204 #define IC0_WAKERD 0xB0400068
205 #define IC0_WAKESET 0xB0400068
206 #define IC0_WAKECLR 0xB040006C
207
208 #define IC0_MASKRD 0xB0400070
209 #define IC0_MASKSET 0xB0400070
210 #define IC0_MASKCLR 0xB0400074
211
212 #define IC0_RISINGRD 0xB0400078
213 #define IC0_RISINGCLR 0xB0400078
214 #define IC0_FALLINGRD 0xB040007C
215 #define IC0_FALLINGCLR 0xB040007C
216
217 #define IC0_TESTBIT 0xB0400080
218
219 /* Interrupt Controller 1 */
220 #define IC1_CFG0RD 0xB1800040
221 #define IC1_CFG0SET 0xB1800040
222 #define IC1_CFG0CLR 0xB1800044
223
224 #define IC1_CFG1RD 0xB1800048
225 #define IC1_CFG1SET 0xB1800048
226 #define IC1_CFG1CLR 0xB180004C
227
228 #define IC1_CFG2RD 0xB1800050
229 #define IC1_CFG2SET 0xB1800050
230 #define IC1_CFG2CLR 0xB1800054
231
232 #define IC1_REQ0INT 0xB1800054
233 #define IC1_SRCRD 0xB1800058
234 #define IC1_SRCSET 0xB1800058
235 #define IC1_SRCCLR 0xB180005C
236 #define IC1_REQ1INT 0xB180005C
237
238 #define IC1_ASSIGNRD 0xB1800060
239 #define IC1_ASSIGNSET 0xB1800060
240 #define IC1_ASSIGNCLR 0xB1800064
241
242 #define IC1_WAKERD 0xB1800068
243 #define IC1_WAKESET 0xB1800068
244 #define IC1_WAKECLR 0xB180006C
245
246 #define IC1_MASKRD 0xB1800070
247 #define IC1_MASKSET 0xB1800070
248 #define IC1_MASKCLR 0xB1800074
249
250 #define IC1_RISINGRD 0xB1800078
251 #define IC1_RISINGCLR 0xB1800078
252 #define IC1_FALLINGRD 0xB180007C
253 #define IC1_FALLINGCLR 0xB180007C
254
255 #define IC1_TESTBIT 0xB1800080
256
257 /* Interrupt Configuration Modes */
258 #define INTC_INT_DISABLED 0
259 #define INTC_INT_RISE_EDGE 0x1
260 #define INTC_INT_FALL_EDGE 0x2
261 #define INTC_INT_RISE_AND_FALL_EDGE 0x3
262 #define INTC_INT_HIGH_LEVEL 0x5
263 #define INTC_INT_LOW_LEVEL 0x6
264 #define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
265
266 /* Interrupt Numbers */
267 #define AU1X00_UART0_INT 0
268 #define AU1000_UART1_INT 1 /* au1000 */
269 #define AU1000_UART2_INT 2 /* au1000 */
270
271 #define AU1500_PCI_INTA 1 /* au1500 */
272 #define AU1500_PCI_INTB 2 /* au1500 */
273
274 #define AU1X00_UART3_INT 3
275
276 #define AU1000_SSI0_INT 4 /* au1000 */
277 #define AU1000_SSI1_INT 5 /* au1000 */
278
279 #define AU1500_PCI_INTC 4 /* au1500 */
280 #define AU1500_PCI_INTD 5 /* au1500 */
281
282 #define AU1X00_DMA_INT_BASE 6
283 #define AU1X00_TOY_INT 14
284 #define AU1X00_TOY_MATCH0_INT 15
285 #define AU1X00_TOY_MATCH1_INT 16
286 #define AU1X00_TOY_MATCH2_INT 17
287 #define AU1X00_RTC_INT 18
288 #define AU1X00_RTC_MATCH0_INT 19
289 #define AU1X00_RTC_MATCH1_INT 20
290 #define AU1X00_RTC_MATCH2_INT 21
291 #define AU1000_IRDA_TX_INT 22 /* au1000 */
292 #define AU1000_IRDA_RX_INT 23 /* au1000 */
293 #define AU1X00_USB_DEV_REQ_INT 24
294 #define AU1X00_USB_DEV_SUS_INT 25
295 #define AU1X00_USB_HOST_INT 26
296 #define AU1X00_ACSYNC_INT 27
297 #define AU1X00_MAC0_DMA_INT 28
298 #define AU1X00_MAC1_DMA_INT 29
299 #define AU1X00_ETH0_IRQ AU1X00_MAC0_DMA_INT
300 #define AU1X00_ETH1_IRQ AU1X00_MAC1_DMA_INT
301 #define AU1000_I2S_UO_INT 30 /* au1000 */
302 #define AU1X00_AC97C_INT 31
303 #define AU1X00_LAST_INTC0_INT AU1X00_AC97C_INT
304 #define AU1X00_GPIO_0 32
305 #define AU1X00_GPIO_1 33
306 #define AU1X00_GPIO_2 34
307 #define AU1X00_GPIO_3 35
308 #define AU1X00_GPIO_4 36
309 #define AU1X00_GPIO_5 37
310 #define AU1X00_GPIO_6 38
311 #define AU1X00_GPIO_7 39
312 #define AU1X00_GPIO_8 40
313 #define AU1X00_GPIO_9 41
314 #define AU1X00_GPIO_10 42
315 #define AU1X00_GPIO_11 43
316 #define AU1X00_GPIO_12 44
317 #define AU1X00_GPIO_13 45
318 #define AU1X00_GPIO_14 46
319 #define AU1X00_GPIO_15 47
320
321 /* Au1000 only */
322 #define AU1000_GPIO_16 48
323 #define AU1000_GPIO_17 49
324 #define AU1000_GPIO_18 50
325 #define AU1000_GPIO_19 51
326 #define AU1000_GPIO_20 52
327 #define AU1000_GPIO_21 53
328 #define AU1000_GPIO_22 54
329 #define AU1000_GPIO_23 55
330 #define AU1000_GPIO_24 56
331 #define AU1000_GPIO_25 57
332 #define AU1000_GPIO_26 58
333 #define AU1000_GPIO_27 59
334 #define AU1000_GPIO_28 60
335 #define AU1000_GPIO_29 61
336 #define AU1000_GPIO_30 62
337 #define AU1000_GPIO_31 63
338
339 /* Au1500 only */
340 #define AU1500_GPIO_200 48
341 #define AU1500_GPIO_201 49
342 #define AU1500_GPIO_202 50
343 #define AU1500_GPIO_203 51
344 #define AU1500_GPIO_20 52
345 #define AU1500_GPIO_204 53
346 #define AU1500_GPIO_205 54
347 #define AU1500_GPIO_23 55
348 #define AU1500_GPIO_24 56
349 #define AU1500_GPIO_25 57
350 #define AU1500_GPIO_26 58
351 #define AU1500_GPIO_27 59
352 #define AU1500_GPIO_28 60
353 #define AU1500_GPIO_206 61
354 #define AU1500_GPIO_207 62
355 #define AU1500_GPIO_208_215 63
356
357 #define AU1X00_MAX_INTR 63
358
359 #define AU1100_SD 2
360 #define AU1100_GPIO_208_215 29
361 /* REDEFINE SECONDARY GPIO BLOCK INTO IC1 CONTROLLER HERE */
362
363 /* Programmable Counters 0 and 1 */
364 #define SYS_BASE 0xB1900000
365 #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
366 #define SYS_CNTRL_E1S (1<<23)
367 #define SYS_CNTRL_T1S (1<<20)
368 #define SYS_CNTRL_M21 (1<<19)
369 #define SYS_CNTRL_M11 (1<<18)
370 #define SYS_CNTRL_M01 (1<<17)
371 #define SYS_CNTRL_C1S (1<<16)
372 #define SYS_CNTRL_BP (1<<14)
373 #define SYS_CNTRL_EN1 (1<<13)
374 #define SYS_CNTRL_BT1 (1<<12)
375 #define SYS_CNTRL_EN0 (1<<11)
376 #define SYS_CNTRL_BT0 (1<<10)
377 #define SYS_CNTRL_E0 (1<<8)
378 #define SYS_CNTRL_E0S (1<<7)
379 #define SYS_CNTRL_32S (1<<5)
380 #define SYS_CNTRL_T0S (1<<4)
381 #define SYS_CNTRL_M20 (1<<3)
382 #define SYS_CNTRL_M10 (1<<2)
383 #define SYS_CNTRL_M00 (1<<1)
384 #define SYS_CNTRL_C0S (1<<0)
385
386 /* Programmable Counter 0 Registers */
387 #define SYS_TOYTRIM (SYS_BASE + 0)
388 #define SYS_TOYWRITE (SYS_BASE + 4)
389 #define SYS_TOYMATCH0 (SYS_BASE + 8)
390 #define SYS_TOYMATCH1 (SYS_BASE + 0xC)
391 #define SYS_TOYMATCH2 (SYS_BASE + 0x10)
392 #define SYS_TOYREAD (SYS_BASE + 0x40)
393
394 /* Programmable Counter 1 Registers */
395 #define SYS_RTCTRIM (SYS_BASE + 0x44)
396 #define SYS_RTCWRITE (SYS_BASE + 0x48)
397 #define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
398 #define SYS_RTCMATCH1 (SYS_BASE + 0x50)
399 #define SYS_RTCMATCH2 (SYS_BASE + 0x54)
400 #define SYS_RTCREAD (SYS_BASE + 0x58)
401
402 /* I2S Controller */
403 #define I2S_DATA 0xB1000000
404 #define I2S_DATA_MASK (0xffffff)
405 #define I2S_CONFIG 0xB1000004
406 #define I2S_CONFIG_XU (1<<25)
407 #define I2S_CONFIG_XO (1<<24)
408 #define I2S_CONFIG_RU (1<<23)
409 #define I2S_CONFIG_RO (1<<22)
410 #define I2S_CONFIG_TR (1<<21)
411 #define I2S_CONFIG_TE (1<<20)
412 #define I2S_CONFIG_TF (1<<19)
413 #define I2S_CONFIG_RR (1<<18)
414 #define I2S_CONFIG_RE (1<<17)
415 #define I2S_CONFIG_RF (1<<16)
416 #define I2S_CONFIG_PD (1<<11)
417 #define I2S_CONFIG_LB (1<<10)
418 #define I2S_CONFIG_IC (1<<9)
419 #define I2S_CONFIG_FM_BIT 7
420 #define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
421 #define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
422 #define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
423 #define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
424 #define I2S_CONFIG_TN (1<<6)
425 #define I2S_CONFIG_RN (1<<5)
426 #define I2S_CONFIG_SZ_BIT 0
427 #define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
428
429 #define I2S_CONTROL 0xB1000008
430 #define I2S_CONTROL_D (1<<1)
431 #define I2S_CONTROL_CE (1<<0)
432
433 /* USB Host Controller */
434 /* We pass USB_OHCI_BASE to ioremap, so it needs to be a physical address */
435 #define USB_OHCI_BASE 0x10100000
436 #define USB_OHCI_LEN 0x00100000
437 #define USB_HOST_CONFIG 0xB017fffc
438
439 /* USB Device Controller */
440 #define USBD_EP0RD 0xB0200000
441 #define USBD_EP0WR 0xB0200004
442 #define USBD_EP2WR 0xB0200008
443 #define USBD_EP3WR 0xB020000C
444 #define USBD_EP4RD 0xB0200010
445 #define USBD_EP5RD 0xB0200014
446 #define USBD_INTEN 0xB0200018
447 #define USBD_INTSTAT 0xB020001C
448 #define USBDEV_INT_SOF (1<<12)
449 #define USBDEV_INT_HF_BIT 6
450 #define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
451 #define USBDEV_INT_CMPLT_BIT 0
452 #define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
453 #define USBD_CONFIG 0xB0200020
454 #define USBD_EP0CS 0xB0200024
455 #define USBD_EP2CS 0xB0200028
456 #define USBD_EP3CS 0xB020002C
457 #define USBD_EP4CS 0xB0200030
458 #define USBD_EP5CS 0xB0200034
459 #define USBDEV_CS_SU (1<<14)
460 #define USBDEV_CS_NAK (1<<13)
461 #define USBDEV_CS_ACK (1<<12)
462 #define USBDEV_CS_BUSY (1<<11)
463 #define USBDEV_CS_TSIZE_BIT 1
464 #define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
465 #define USBDEV_CS_STALL (1<<0)
466 #define USBD_EP0RDSTAT 0xB0200040
467 #define USBD_EP0WRSTAT 0xB0200044
468 #define USBD_EP2WRSTAT 0xB0200048
469 #define USBD_EP3WRSTAT 0xB020004C
470 #define USBD_EP4RDSTAT 0xB0200050
471 #define USBD_EP5RDSTAT 0xB0200054
472 #define USBDEV_FSTAT_FLUSH (1<<6)
473 #define USBDEV_FSTAT_UF (1<<5)
474 #define USBDEV_FSTAT_OF (1<<4)
475 #define USBDEV_FSTAT_FCNT_BIT 0
476 #define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
477 #define USBD_ENABLE 0xB0200058
478 #define USBDEV_ENABLE (1<<1)
479 #define USBDEV_CE (1<<0)
480
481 /* Ethernet Controllers */
482 #define AU1000_ETH0_BASE 0xB0500000
483 #define AU1000_ETH1_BASE 0xB0510000
484 #define AU1500_ETH0_BASE 0xB1500000
485 #define AU1500_ETH1_BASE 0xB1510000
486 #define AU1100_ETH0_BASE 0xB0500000
487 #define AU1550_ETH0_BASE 0xB0500000
488 #define AU1550_ETH1_BASE 0xB0510000
489
490 /* 4 byte offsets from AU1000_ETH_BASE */
491 #define MAC_CONTROL 0x0
492 #define MAC_RX_ENABLE (1<<2)
493 #define MAC_TX_ENABLE (1<<3)
494 #define MAC_DEF_CHECK (1<<5)
495 #define MAC_SET_BL(X) (((X)&0x3)<<6)
496 #define MAC_AUTO_PAD (1<<8)
497 #define MAC_DISABLE_RETRY (1<<10)
498 #define MAC_DISABLE_BCAST (1<<11)
499 #define MAC_LATE_COL (1<<12)
500 #define MAC_HASH_MODE (1<<13)
501 #define MAC_HASH_ONLY (1<<15)
502 #define MAC_PASS_ALL (1<<16)
503 #define MAC_INVERSE_FILTER (1<<17)
504 #define MAC_PROMISCUOUS (1<<18)
505 #define MAC_PASS_ALL_MULTI (1<<19)
506 #define MAC_FULL_DUPLEX (1<<20)
507 #define MAC_NORMAL_MODE 0
508 #define MAC_INT_LOOPBACK (1<<21)
509 #define MAC_EXT_LOOPBACK (1<<22)
510 #define MAC_DISABLE_RX_OWN (1<<23)
511 #define MAC_BIG_ENDIAN (1<<30)
512 #define MAC_RX_ALL (1<<31)
513 #define MAC_ADDRESS_HIGH 0x4
514 #define MAC_ADDRESS_LOW 0x8
515 #define MAC_MCAST_HIGH 0xC
516 #define MAC_MCAST_LOW 0x10
517 #define MAC_MII_CNTRL 0x14
518 #define MAC_MII_BUSY (1<<0)
519 #define MAC_MII_READ 0
520 #define MAC_MII_WRITE (1<<1)
521 #define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6)
522 #define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11)
523 #define MAC_MII_DATA 0x18
524 #define MAC_FLOW_CNTRL 0x1C
525 #define MAC_FLOW_CNTRL_BUSY (1<<0)
526 #define MAC_FLOW_CNTRL_ENABLE (1<<1)
527 #define MAC_PASS_CONTROL (1<<2)
528 #define MAC_SET_PAUSE(X) (((X)&0xffff)<<16)
529 #define MAC_VLAN1_TAG 0x20
530 #define MAC_VLAN2_TAG 0x24
531
532 /* Ethernet Controller Enable */
533 #define AU1000_MAC0_ENABLE 0xB0520000
534 #define AU1000_MAC1_ENABLE 0xB0520004
535 #define AU1500_MAC0_ENABLE 0xB1520000
536 #define AU1500_MAC1_ENABLE 0xB1520004
537 #define AU1100_MAC0_ENABLE 0xB0520000
538 #define AU1550_MAC0_ENABLE 0xB0520000
539 #define AU1550_MAC1_ENABLE 0xB0520004
540
541 #define MAC_EN_CLOCK_ENABLE (1<<0)
542 #define MAC_EN_RESET0 (1<<1)
543 #define MAC_EN_TOSS (0<<2)
544 #define MAC_EN_CACHEABLE (1<<3)
545 #define MAC_EN_RESET1 (1<<4)
546 #define MAC_EN_RESET2 (1<<5)
547 #define MAC_DMA_RESET (1<<6)
548
549 /* Ethernet Controller DMA Channels */
550
551 #define MAC0_TX_DMA_ADDR 0xB4004000
552 #define MAC1_TX_DMA_ADDR 0xB4004200
553 /* offsets from MAC_TX_RING_ADDR address */
554 #define MAC_TX_BUFF0_STATUS 0x0
555 #define TX_FRAME_ABORTED (1<<0)
556 #define TX_JAB_TIMEOUT (1<<1)
557 #define TX_NO_CARRIER (1<<2)
558 #define TX_LOSS_CARRIER (1<<3)
559 #define TX_EXC_DEF (1<<4)
560 #define TX_LATE_COLL_ABORT (1<<5)
561 #define TX_EXC_COLL (1<<6)
562 #define TX_UNDERRUN (1<<7)
563 #define TX_DEFERRED (1<<8)
564 #define TX_LATE_COLL (1<<9)
565 #define TX_COLL_CNT_MASK (0xF<<10)
566 #define TX_PKT_RETRY (1<<31)
567 #define MAC_TX_BUFF0_ADDR 0x4
568 #define TX_DMA_ENABLE (1<<0)
569 #define TX_T_DONE (1<<1)
570 #define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
571 #define MAC_TX_BUFF0_LEN 0x8
572 #define MAC_TX_BUFF1_STATUS 0x10
573 #define MAC_TX_BUFF1_ADDR 0x14
574 #define MAC_TX_BUFF1_LEN 0x18
575 #define MAC_TX_BUFF2_STATUS 0x20
576 #define MAC_TX_BUFF2_ADDR 0x24
577 #define MAC_TX_BUFF2_LEN 0x28
578 #define MAC_TX_BUFF3_STATUS 0x30
579 #define MAC_TX_BUFF3_ADDR 0x34
580 #define MAC_TX_BUFF3_LEN 0x38
581
582 #define MAC0_RX_DMA_ADDR 0xB4004100
583 #define MAC1_RX_DMA_ADDR 0xB4004300
584 /* offsets from MAC_RX_RING_ADDR */
585 #define MAC_RX_BUFF0_STATUS 0x0
586 #define RX_FRAME_LEN_MASK 0x3fff
587 #define RX_WDOG_TIMER (1<<14)
588 #define RX_RUNT (1<<15)
589 #define RX_OVERLEN (1<<16)
590 #define RX_COLL (1<<17)
591 #define RX_ETHER (1<<18)
592 #define RX_MII_ERROR (1<<19)
593 #define RX_DRIBBLING (1<<20)
594 #define RX_CRC_ERROR (1<<21)
595 #define RX_VLAN1 (1<<22)
596 #define RX_VLAN2 (1<<23)
597 #define RX_LEN_ERROR (1<<24)
598 #define RX_CNTRL_FRAME (1<<25)
599 #define RX_U_CNTRL_FRAME (1<<26)
600 #define RX_MCAST_FRAME (1<<27)
601 #define RX_BCAST_FRAME (1<<28)
602 #define RX_FILTER_FAIL (1<<29)
603 #define RX_PACKET_FILTER (1<<30)
604 #define RX_MISSED_FRAME (1<<31)
605
606 #define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
607 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
608 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
609 #define MAC_RX_BUFF0_ADDR 0x4
610 #define RX_DMA_ENABLE (1<<0)
611 #define RX_T_DONE (1<<1)
612 #define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3)
613 #define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0)
614 #define MAC_RX_BUFF1_STATUS 0x10
615 #define MAC_RX_BUFF1_ADDR 0x14
616 #define MAC_RX_BUFF2_STATUS 0x20
617 #define MAC_RX_BUFF2_ADDR 0x24
618 #define MAC_RX_BUFF3_STATUS 0x30
619 #define MAC_RX_BUFF3_ADDR 0x34
620
621
622 /* UARTS 0-3 */
623 #define UART0_ADDR 0xB1100000
624 #define UART1_ADDR 0xB1200000
625 #define UART2_ADDR 0xB1300000
626 #define UART3_ADDR 0xB1400000
627 #define UART_BASE UART0_ADDR
628 #define UART_DEBUG_BASE UART2_ADDR
629
630 #define UART_RX 0 /* Receive buffer */
631 #define UART_TX 4 /* Transmit buffer */
632 #define UART_IER 8 /* Interrupt Enable Register */
633 #define UART_IIR 0xC /* Interrupt ID Register */
634 #define UART_FCR 0x10 /* FIFO Control Register */
635 #define UART_LCR 0x14 /* Line Control Register */
636 #define UART_MCR 0x18 /* Modem Control Register */
637 #define UART_LSR 0x1C /* Line Status Register */
638 #define UART_MSR 0x20 /* Modem Status Register */
639 #define UART_CLK 0x28 /* Baud Rate Clock Divider */
640 #define UART_ENABLE 0x100 /* Uart enable */
641
642 #define UART_EN_CE 1 /* Clock enable */
643 #define UART_EN_E 2 /* Enable */
644
645 #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
646 #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
647 #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
648 #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
649 #define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */
650 #define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */
651 #define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */
652 #define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */
653 #define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */
654 #define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */
655 #define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */
656 #define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */
657 #define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */
658
659 /*
660 * These are the definitions for the Line Control Register
661 */
662 #define UART_LCR_SBC 0x40 /* Set break control */
663 #define UART_LCR_SPAR 0x20 /* Stick parity (?) */
664 #define UART_LCR_EPAR 0x10 /* Even parity select */
665 #define UART_LCR_PARITY 0x08 /* Parity Enable */
666 #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
667 #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
668 #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
669 #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
670 #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
671
672 /*
673 * These are the definitions for the Line Status Register
674 */
675 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
676 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
677 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
678 #define UART_LSR_FE 0x08 /* Frame error indicator */
679 #define UART_LSR_PE 0x04 /* Parity error indicator */
680 #define UART_LSR_OE 0x02 /* Overrun error indicator */
681 #define UART_LSR_DR 0x01 /* Receiver data ready */
682
683 /*
684 * These are the definitions for the Interrupt Identification Register
685 */
686 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
687 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
688 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
689 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
690 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
691 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
692
693 /*
694 * These are the definitions for the Interrupt Enable Register
695 */
696 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
697 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
698 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
699 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
700
701 /*
702 * These are the definitions for the Modem Control Register
703 */
704 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
705 #define UART_MCR_OUT2 0x08 /* Out2 complement */
706 #define UART_MCR_OUT1 0x04 /* Out1 complement */
707 #define UART_MCR_RTS 0x02 /* RTS complement */
708 #define UART_MCR_DTR 0x01 /* DTR complement */
709
710 /*
711 * These are the definitions for the Modem Status Register
712 */
713 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
714 #define UART_MSR_RI 0x40 /* Ring Indicator */
715 #define UART_MSR_DSR 0x20 /* Data Set Ready */
716 #define UART_MSR_CTS 0x10 /* Clear to Send */
717 #define UART_MSR_DDCD 0x08 /* Delta DCD */
718 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
719 #define UART_MSR_DDSR 0x02 /* Delta DSR */
720 #define UART_MSR_DCTS 0x01 /* Delta CTS */
721 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
722
723
724 /* SSIO */
725 #define SSI0_STATUS 0xB1600000
726 #define SSI_STATUS_BF (1<<4)
727 #define SSI_STATUS_OF (1<<3)
728 #define SSI_STATUS_UF (1<<2)
729 #define SSI_STATUS_D (1<<1)
730 #define SSI_STATUS_B (1<<0)
731 #define SSI0_INT 0xB1600004
732 #define SSI_INT_OI (1<<3)
733 #define SSI_INT_UI (1<<2)
734 #define SSI_INT_DI (1<<1)
735 #define SSI0_INT_ENABLE 0xB1600008
736 #define SSI_INTE_OIE (1<<3)
737 #define SSI_INTE_UIE (1<<2)
738 #define SSI_INTE_DIE (1<<1)
739 #define SSI0_CONFIG 0xB1600020
740 #define SSI_CONFIG_AO (1<<24)
741 #define SSI_CONFIG_DO (1<<23)
742 #define SSI_CONFIG_ALEN_BIT 20
743 #define SSI_CONFIG_ALEN_MASK (0x7<<20)
744 #define SSI_CONFIG_DLEN_BIT 16
745 #define SSI_CONFIG_DLEN_MASK (0x7<<16)
746 #define SSI_CONFIG_DD (1<<11)
747 #define SSI_CONFIG_AD (1<<10)
748 #define SSI_CONFIG_BM_BIT 8
749 #define SSI_CONFIG_BM_MASK (0x3<<8)
750 #define SSI_CONFIG_CE (1<<7)
751 #define SSI_CONFIG_DP (1<<6)
752 #define SSI_CONFIG_DL (1<<5)
753 #define SSI_CONFIG_EP (1<<4)
754 #define SSI0_ADATA 0xB1600024
755 #define SSI_AD_D (1<<24)
756 #define SSI_AD_ADDR_BIT 16
757 #define SSI_AD_ADDR_MASK (0xff<<16)
758 #define SSI_AD_DATA_BIT 0
759 #define SSI_AD_DATA_MASK (0xfff<<0)
760 #define SSI0_CLKDIV 0xB1600028
761 #define SSI0_CONTROL 0xB1600100
762 #define SSI_CONTROL_CD (1<<1)
763 #define SSI_CONTROL_E (1<<0)
764
765 /* SSI1 */
766 #define SSI1_STATUS 0xB1680000
767 #define SSI1_INT 0xB1680004
768 #define SSI1_INT_ENABLE 0xB1680008
769 #define SSI1_CONFIG 0xB1680020
770 #define SSI1_ADATA 0xB1680024
771 #define SSI1_CLKDIV 0xB1680028
772 #define SSI1_ENABLE 0xB1680100
773
774 /*
775 * Register content definitions
776 */
777 #define SSI_STATUS_BF (1<<4)
778 #define SSI_STATUS_OF (1<<3)
779 #define SSI_STATUS_UF (1<<2)
780 #define SSI_STATUS_D (1<<1)
781 #define SSI_STATUS_B (1<<0)
782
783 /* SSI_INT */
784 #define SSI_INT_OI (1<<3)
785 #define SSI_INT_UI (1<<2)
786 #define SSI_INT_DI (1<<1)
787
788 /* SSI_INTEN */
789 #define SSI_INTEN_OIE (1<<3)
790 #define SSI_INTEN_UIE (1<<2)
791 #define SSI_INTEN_DIE (1<<1)
792
793 #define SSI_CONFIG_AO (1<<24)
794 #define SSI_CONFIG_DO (1<<23)
795 #define SSI_CONFIG_ALEN (7<<20)
796 #define SSI_CONFIG_DLEN (15<<16)
797 #define SSI_CONFIG_DD (1<<11)
798 #define SSI_CONFIG_AD (1<<10)
799 #define SSI_CONFIG_BM (3<<8)
800 #define SSI_CONFIG_CE (1<<7)
801 #define SSI_CONFIG_DP (1<<6)
802 #define SSI_CONFIG_DL (1<<5)
803 #define SSI_CONFIG_EP (1<<4)
804 #define SSI_CONFIG_ALEN_N(N) ((N-1)<<20)
805 #define SSI_CONFIG_DLEN_N(N) ((N-1)<<16)
806 #define SSI_CONFIG_BM_HI (0<<8)
807 #define SSI_CONFIG_BM_LO (1<<8)
808 #define SSI_CONFIG_BM_CY (2<<8)
809
810 #define SSI_ADATA_D (1<<24)
811 #define SSI_ADATA_ADDR (0xFF<<16)
812 #define SSI_ADATA_DATA (0x0FFF)
813 #define SSI_ADATA_ADDR_N(N) (N<<16)
814
815 #define SSI_ENABLE_CD (1<<1)
816 #define SSI_ENABLE_E (1<<0)
817
818
819 /* IrDA Controller */
820 #define IRDA_BASE 0xB0300000
821 #define IR_RING_PTR_STATUS (IRDA_BASE+0x00)
822 #define IR_RING_BASE_ADDR_H (IRDA_BASE+0x04)
823 #define IR_RING_BASE_ADDR_L (IRDA_BASE+0x08)
824 #define IR_RING_SIZE (IRDA_BASE+0x0C)
825 #define IR_RING_PROMPT (IRDA_BASE+0x10)
826 #define IR_RING_ADDR_CMPR (IRDA_BASE+0x14)
827 #define IR_INT_CLEAR (IRDA_BASE+0x18)
828 #define IR_CONFIG_1 (IRDA_BASE+0x20)
829 #define IR_RX_INVERT_LED (1<<0)
830 #define IR_TX_INVERT_LED (1<<1)
831 #define IR_ST (1<<2)
832 #define IR_SF (1<<3)
833 #define IR_SIR (1<<4)
834 #define IR_MIR (1<<5)
835 #define IR_FIR (1<<6)
836 #define IR_16CRC (1<<7)
837 #define IR_TD (1<<8)
838 #define IR_RX_ALL (1<<9)
839 #define IR_DMA_ENABLE (1<<10)
840 #define IR_RX_ENABLE (1<<11)
841 #define IR_TX_ENABLE (1<<12)
842 #define IR_LOOPBACK (1<<14)
843 #define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
844 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
845 #define IR_SIR_FLAGS (IRDA_BASE+0x24)
846 #define IR_ENABLE (IRDA_BASE+0x28)
847 #define IR_RX_STATUS (1<<9)
848 #define IR_TX_STATUS (1<<10)
849 #define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C)
850 #define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30)
851 #define IR_MAX_PKT_LEN (IRDA_BASE+0x34)
852 #define IR_RX_BYTE_CNT (IRDA_BASE+0x38)
853 #define IR_CONFIG_2 (IRDA_BASE+0x3C)
854 #define IR_MODE_INV (1<<0)
855 #define IR_ONE_PIN (1<<1)
856 #define IR_INTERFACE_CONFIG (IRDA_BASE+0x40)
857
858 /* GPIO */
859 #define SYS_PINFUNC 0xB190002C
860 #define SYS_PF_USB (1<<15) /* 2nd USB device/host */
861 #define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */
862 #define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */
863 #define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */
864 #define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */
865 #define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */
866 #define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */
867 #define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */
868 #define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */
869 #define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */
870 #define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */
871 #define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */
872 #define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */
873 #define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */
874 #define SYS_PF_A97 (1<<1) /* AC97/SSL1 */
875 #define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */
876 #define SYS_TRIOUTRD 0xB1900100
877 #define SYS_TRIOUTCLR 0xB1900100
878 #define SYS_OUTPUTRD 0xB1900108
879 #define SYS_OUTPUTSET 0xB1900108
880 #define SYS_OUTPUTCLR 0xB190010C
881 #define SYS_PINSTATERD 0xB1900110
882 #define SYS_PININPUTEN 0xB1900110
883
884 /* GPIO2, Au1500 only */
885 #define GPIO2_BASE 0xB1700000
886 #define GPIO2_DIR (GPIO2_BASE + 0)
887 #define GPIO2_DATA_EN (GPIO2_BASE + 8)
888 #define GPIO2_PIN_STATE (GPIO2_BASE + 0xC)
889 #define GPIO2_INT_ENABLE (GPIO2_BASE + 0x10)
890 #define GPIO2_ENABLE (GPIO2_BASE + 0x14)
891
892 /* Power Management */
893 #define SYS_SCRATCH0 0xB1900018
894 #define SYS_SCRATCH1 0xB190001C
895 #define SYS_WAKEMSK 0xB1900034
896 #define SYS_ENDIAN 0xB1900038
897 #define SYS_POWERCTRL 0xB190003C
898 #define SYS_WAKESRC 0xB190005C
899 #define SYS_SLPPWR 0xB1900078
900 #define SYS_SLEEP 0xB190007C
901
902 /* Clock Controller */
903 #define SYS_FREQCTRL0 0xB1900020
904 #define SYS_FC_FRDIV2_BIT 22
905 #define SYS_FC_FRDIV2_MASK (0xff << FQC2_FRDIV2_BIT)
906 #define SYS_FC_FE2 (1<<21)
907 #define SYS_FC_FS2 (1<<20)
908 #define SYS_FC_FRDIV1_BIT 12
909 #define SYS_FC_FRDIV1_MASK (0xff << FQC2_FRDIV1_BIT)
910 #define SYS_FC_FE1 (1<<11)
911 #define SYS_FC_FS1 (1<<10)
912 #define SYS_FC_FRDIV0_BIT 2
913 #define SYS_FC_FRDIV0_MASK (0xff << FQC2_FRDIV0_BIT)
914 #define SYS_FC_FE0 (1<<1)
915 #define SYS_FC_FS0 (1<<0)
916 #define SYS_FREQCTRL1 0xB1900024
917 #define SYS_FC_FRDIV5_BIT 22
918 #define SYS_FC_FRDIV5_MASK (0xff << FQC2_FRDIV5_BIT)
919 #define SYS_FC_FE5 (1<<21)
920 #define SYS_FC_FS5 (1<<20)
921 #define SYS_FC_FRDIV4_BIT 12
922 #define SYS_FC_FRDIV4_MASK (0xff << FQC2_FRDIV4_BIT)
923 #define SYS_FC_FE4 (1<<11)
924 #define SYS_FC_FS4 (1<<10)
925 #define SYS_FC_FRDIV3_BIT 2
926 #define SYS_FC_FRDIV3_MASK (0xff << FQC2_FRDIV3_BIT)
927 #define SYS_FC_FE3 (1<<1)
928 #define SYS_FC_FS3 (1<<0)
929 #define SYS_CLKSRC 0xB1900028
930 #define SYS_CS_ME1_BIT 27
931 #define SYS_CS_ME1_MASK (0x7<<CSC_ME1_BIT)
932 #define SYS_CS_DE1 (1<<26)
933 #define SYS_CS_CE1 (1<<25)
934 #define SYS_CS_ME0_BIT 22
935 #define SYS_CS_ME0_MASK (0x7<<CSC_ME0_BIT)
936 #define SYS_CS_DE0 (1<<21)
937 #define SYS_CS_CE0 (1<<20)
938 #define SYS_CS_MI2_BIT 17
939 #define SYS_CS_MI2_MASK (0x7<<CSC_MI2_BIT)
940 #define SYS_CS_DI2 (1<<16)
941 #define SYS_CS_CI2 (1<<15)
942 #define SYS_CS_MUH_BIT 12
943 #define SYS_CS_MUH_MASK (0x7<<CSC_MUH_BIT)
944 #define SYS_CS_DUH (1<<11)
945 #define SYS_CS_CUH (1<<10)
946 #define SYS_CS_MUD_BIT 7
947 #define SYS_CS_MUD_MASK (0x7<<CSC_MUD_BIT)
948 #define SYS_CS_DUD (1<<6)
949 #define SYS_CS_CUD (1<<5)
950 #define SYS_CS_MIR_BIT 2
951 #define SYS_CS_MIR_MASK (0x7<<CSC_MIR_BIT)
952 #define SYS_CS_DIR (1<<1)
953 #define SYS_CS_CIR (1<<0)
954
955 #define SYS_CS_MUX_AUX 0x1
956 #define SYS_CS_MUX_FQ0 0x2
957 #define SYS_CS_MUX_FQ1 0x3
958 #define SYS_CS_MUX_FQ2 0x4
959 #define SYS_CS_MUX_FQ3 0x5
960 #define SYS_CS_MUX_FQ4 0x6
961 #define SYS_CS_MUX_FQ5 0x7
962 #define SYS_CPUPLL 0xB1900060
963 #define SYS_AUXPLL 0xB1900064
964
965 /* AC97 Controller */
966 #define AC97C_CONFIG 0xB0000000
967 #define AC97C_RECV_SLOTS_BIT 13
968 #define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
969 #define AC97C_XMIT_SLOTS_BIT 3
970 #define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
971 #define AC97C_SG (1<<2)
972 #define AC97C_SYNC (1<<1)
973 #define AC97C_RESET (1<<0)
974 #define AC97C_STATUS 0xB0000004
975 #define AC97C_XU (1<<11)
976 #define AC97C_XO (1<<10)
977 #define AC97C_RU (1<<9)
978 #define AC97C_RO (1<<8)
979 #define AC97C_READY (1<<7)
980 #define AC97C_CP (1<<6)
981 #define AC97C_TR (1<<5)
982 #define AC97C_TE (1<<4)
983 #define AC97C_TF (1<<3)
984 #define AC97C_RR (1<<2)
985 #define AC97C_RE (1<<1)
986 #define AC97C_RF (1<<0)
987 #define AC97C_DATA 0xB0000008
988 #define AC97C_CMD 0xB000000C
989 #define AC97C_WD_BIT 16
990 #define AC97C_READ (1<<7)
991 #define AC97C_INDEX_MASK 0x7f
992 #define AC97C_CNTRL 0xB0000010
993 #define AC97C_RS (1<<1)
994 #define AC97C_CE (1<<0)
995
996 #define DB1000_BCSR_ADDR 0xAE000000
997 #define DB1550_BCSR_ADDR 0xAF000000
998
999 #ifdef CONFIG_DBAU1550
1000 #define DB1XX0_BCSR_ADDR DB1550_BCSR_ADDR
1001 #else
1002 #define DB1XX0_BCSR_ADDR DB1000_BCSR_ADDR
1003 #endif
1004
1005 #ifdef CONFIG_SOC_AU1500
1006 /* Au1500 PCI Controller */
1007 #define Au1500_CFG_BASE 0xB4005000 /* virtual, kseg0 addr */
1008 #define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
1009 #define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
1010 #define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27))
1011 #define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
1012 #define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
1013 #define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
1014 #define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)
1015 #define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
1016 #define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
1017 #define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
1018 #define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)
1019 #define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)
1020 #define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)
1021 #define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)
1022 #define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)
1023
1024 #define Au1500_PCI_HDR 0xB4005100 /* virtual, kseg0 addr */
1025
1026 /* All of our structures, like pci resource, have 32 bit members.
1027 * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
1028 * hard to store 0x4 0000 0000 in a 32 bit type. We require a small patch
1029 * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
1030 * (u32)Au1500_PCI_MEM_END and change those to the full 36 bit PCI MEM
1031 * addresses. For PCI IO, it's simpler because we get to do the ioremap
1032 * ourselves and then adjust the device's resources.
1033 */
1034 #define Au1500_EXT_CFG 0x600000000
1035 #define Au1500_EXT_CFG_TYPE1 0x680000000
1036 #define Au1500_PCI_IO_START 0x500000000
1037 #define Au1500_PCI_IO_END 0x5000FFFFF
1038 #define Au1500_PCI_MEM_START 0x440000000
1039 #define Au1500_PCI_MEM_END 0x443FFFFFF
1040
1041 #define PCI_IO_START (Au1500_PCI_IO_START + 0x300)
1042 #define PCI_IO_END (Au1500_PCI_IO_END)
1043 #define PCI_MEM_START (Au1500_PCI_MEM_START)
1044 #define PCI_MEM_END (Au1500_PCI_MEM_END)
1045 #define PCI_FIRST_DEVFN (0<<3)
1046 #define PCI_LAST_DEVFN (19<<3)
1047
1048 #endif
1049
1050 #if defined(CONFIG_SOC_AU1100) || (defined(CONFIG_SOC_AU1000) && !defined(CONFIG_MIPS_PB1000))
1051 /* no PCI bus controller */
1052 #define PCI_IO_START 0
1053 #define PCI_IO_END 0
1054 #define PCI_MEM_START 0
1055 #define PCI_MEM_END 0
1056 #define PCI_FIRST_DEVFN 0
1057 #define PCI_LAST_DEVFN 0
1058 #endif
1059 #define AU1X_SOCK0_IO 0xF00000000
1060 #define AU1X_SOCK0_PHYS_ATTR 0xF40000000
1061 #define AU1X_SOCK0_PHYS_MEM 0xF80000000
1062
1063 /* pcmcia socket 1 needs external glue logic so the memory map
1064 * differs from board to board.
1065 */
1066
1067 /* Only for db board, not older pb */
1068 #define AU1X_SOCK1_IO 0xF04000000
1069 #define AU1X_SOCK1_PHYS_ATTR 0xF44000000
1070 #define AU1X_SOCK1_PHYS_MEM 0xF84000000
1071
1072 #endif
1073