1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 *
19 ******************************************************************************/
20 #define _RTW_MP_C_
21
22 #include <drv_types.h>
23
24 #ifdef PLATFORM_FREEBSD
25 #include <sys/unistd.h> /* for RFHIGHPID */
26 #endif
27
28 #include "../hal/phydm/phydm_precomp.h"
29 #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8821A)
30 #include <rtw_bt_mp.h>
31 #endif
32
33
34 #ifdef CONFIG_MP_INCLUDED
35
read_macreg(_adapter * padapter,u32 addr,u32 sz)36 u32 read_macreg(_adapter *padapter, u32 addr, u32 sz)
37 {
38 u32 val = 0;
39
40 switch(sz)
41 {
42 case 1:
43 val = rtw_read8(padapter, addr);
44 break;
45 case 2:
46 val = rtw_read16(padapter, addr);
47 break;
48 case 4:
49 val = rtw_read32(padapter, addr);
50 break;
51 default:
52 val = 0xffffffff;
53 break;
54 }
55
56 return val;
57
58 }
59
write_macreg(_adapter * padapter,u32 addr,u32 val,u32 sz)60 void write_macreg(_adapter *padapter, u32 addr, u32 val, u32 sz)
61 {
62 switch(sz)
63 {
64 case 1:
65 rtw_write8(padapter, addr, (u8)val);
66 break;
67 case 2:
68 rtw_write16(padapter, addr, (u16)val);
69 break;
70 case 4:
71 rtw_write32(padapter, addr, val);
72 break;
73 default:
74 break;
75 }
76
77 }
78
read_bbreg(_adapter * padapter,u32 addr,u32 bitmask)79 u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask)
80 {
81 return rtw_hal_read_bbreg(padapter, addr, bitmask);
82 }
83
write_bbreg(_adapter * padapter,u32 addr,u32 bitmask,u32 val)84 void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val)
85 {
86 rtw_hal_write_bbreg(padapter, addr, bitmask, val);
87 }
88
_read_rfreg(PADAPTER padapter,u8 rfpath,u32 addr,u32 bitmask)89 u32 _read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask)
90 {
91 return rtw_hal_read_rfreg(padapter, rfpath, addr, bitmask);
92 }
93
_write_rfreg(PADAPTER padapter,u8 rfpath,u32 addr,u32 bitmask,u32 val)94 void _write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val)
95 {
96 rtw_hal_write_rfreg(padapter, rfpath, addr, bitmask, val);
97 }
98
read_rfreg(PADAPTER padapter,u8 rfpath,u32 addr)99 u32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr)
100 {
101 return _read_rfreg(padapter, rfpath, addr, bRFRegOffsetMask);
102 }
103
write_rfreg(PADAPTER padapter,u8 rfpath,u32 addr,u32 val)104 void write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val)
105 {
106 _write_rfreg(padapter, rfpath, addr, bRFRegOffsetMask, val);
107 }
108
_init_mp_priv_(struct mp_priv * pmp_priv)109 static void _init_mp_priv_(struct mp_priv *pmp_priv)
110 {
111 WLAN_BSSID_EX *pnetwork;
112
113 _rtw_memset(pmp_priv, 0, sizeof(struct mp_priv));
114
115 pmp_priv->mode = MP_OFF;
116
117 pmp_priv->channel = 1;
118 pmp_priv->bandwidth = CHANNEL_WIDTH_20;
119 pmp_priv->prime_channel_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
120 pmp_priv->rateidx = MPT_RATE_1M;
121 pmp_priv->txpoweridx = 0x2A;
122
123 pmp_priv->antenna_tx = ANTENNA_A;
124 pmp_priv->antenna_rx = ANTENNA_AB;
125
126 pmp_priv->check_mp_pkt = 0;
127
128 pmp_priv->tx_pktcount = 0;
129
130 pmp_priv->rx_bssidpktcount=0;
131 pmp_priv->rx_pktcount = 0;
132 pmp_priv->rx_crcerrpktcount = 0;
133
134 pmp_priv->network_macaddr[0] = 0x00;
135 pmp_priv->network_macaddr[1] = 0xE0;
136 pmp_priv->network_macaddr[2] = 0x4C;
137 pmp_priv->network_macaddr[3] = 0x87;
138 pmp_priv->network_macaddr[4] = 0x66;
139 pmp_priv->network_macaddr[5] = 0x55;
140
141 pmp_priv->bSetRxBssid = _FALSE;
142 pmp_priv->bRTWSmbCfg = _FALSE;
143
144 pnetwork = &pmp_priv->mp_network.network;
145 _rtw_memcpy(pnetwork->MacAddress, pmp_priv->network_macaddr, ETH_ALEN);
146
147 pnetwork->Ssid.SsidLength = 8;
148 _rtw_memcpy(pnetwork->Ssid.Ssid, "mp_871x", pnetwork->Ssid.SsidLength);
149
150 pmp_priv->tx.payload = 2;
151 #ifdef CONFIG_80211N_HT
152 pmp_priv->tx.attrib.ht_en = 1;
153 #endif
154
155 }
156
157 #ifdef PLATFORM_WINDOWS
158 /*
159 void mp_wi_callback(
160 IN NDIS_WORK_ITEM* pwk_item,
161 IN PVOID cntx
162 )
163 {
164 _adapter* padapter =(_adapter *)cntx;
165 struct mp_priv *pmppriv=&padapter->mppriv;
166 struct mp_wi_cntx *pmp_wi_cntx=&pmppriv->wi_cntx;
167
168 // Execute specified action.
169 if(pmp_wi_cntx->curractfunc != NULL)
170 {
171 LARGE_INTEGER cur_time;
172 ULONGLONG start_time, end_time;
173 NdisGetCurrentSystemTime(&cur_time); // driver version
174 start_time = cur_time.QuadPart/10; // The return value is in microsecond
175
176 pmp_wi_cntx->curractfunc(padapter);
177
178 NdisGetCurrentSystemTime(&cur_time); // driver version
179 end_time = cur_time.QuadPart/10; // The return value is in microsecond
180
181 RT_TRACE(_module_mp_, _drv_info_,
182 ("WorkItemActType: %d, time spent: %I64d us\n",
183 pmp_wi_cntx->param.act_type, (end_time-start_time)));
184 }
185
186 NdisAcquireSpinLock(&(pmp_wi_cntx->mp_wi_lock));
187 pmp_wi_cntx->bmp_wi_progress= _FALSE;
188 NdisReleaseSpinLock(&(pmp_wi_cntx->mp_wi_lock));
189
190 if (pmp_wi_cntx->bmpdrv_unload)
191 {
192 NdisSetEvent(&(pmp_wi_cntx->mp_wi_evt));
193 }
194
195 }
196 */
197
init_mp_priv_by_os(struct mp_priv * pmp_priv)198 static int init_mp_priv_by_os(struct mp_priv *pmp_priv)
199 {
200 struct mp_wi_cntx *pmp_wi_cntx;
201
202 if (pmp_priv == NULL) return _FAIL;
203
204 pmp_priv->rx_testcnt = 0;
205 pmp_priv->rx_testcnt1 = 0;
206 pmp_priv->rx_testcnt2 = 0;
207
208 pmp_priv->tx_testcnt = 0;
209 pmp_priv->tx_testcnt1 = 0;
210
211 pmp_wi_cntx = &pmp_priv->wi_cntx
212 pmp_wi_cntx->bmpdrv_unload = _FALSE;
213 pmp_wi_cntx->bmp_wi_progress = _FALSE;
214 pmp_wi_cntx->curractfunc = NULL;
215
216 return _SUCCESS;
217 }
218 #endif
219
220 #ifdef PLATFORM_LINUX
init_mp_priv_by_os(struct mp_priv * pmp_priv)221 static int init_mp_priv_by_os(struct mp_priv *pmp_priv)
222 {
223 int i, res;
224 struct mp_xmit_frame *pmp_xmitframe;
225
226 if (pmp_priv == NULL) return _FAIL;
227
228 _rtw_init_queue(&pmp_priv->free_mp_xmitqueue);
229
230 pmp_priv->pallocated_mp_xmitframe_buf = NULL;
231 pmp_priv->pallocated_mp_xmitframe_buf = rtw_zmalloc(NR_MP_XMITFRAME * sizeof(struct mp_xmit_frame) + 4);
232 if (pmp_priv->pallocated_mp_xmitframe_buf == NULL) {
233 res = _FAIL;
234 goto _exit_init_mp_priv;
235 }
236
237 pmp_priv->pmp_xmtframe_buf = pmp_priv->pallocated_mp_xmitframe_buf + 4 - ((SIZE_PTR) (pmp_priv->pallocated_mp_xmitframe_buf) & 3);
238
239 pmp_xmitframe = (struct mp_xmit_frame*)pmp_priv->pmp_xmtframe_buf;
240
241 for (i = 0; i < NR_MP_XMITFRAME; i++)
242 {
243 _rtw_init_listhead(&pmp_xmitframe->list);
244 rtw_list_insert_tail(&pmp_xmitframe->list, &pmp_priv->free_mp_xmitqueue.queue);
245
246 pmp_xmitframe->pkt = NULL;
247 pmp_xmitframe->frame_tag = MP_FRAMETAG;
248 pmp_xmitframe->padapter = pmp_priv->papdater;
249
250 pmp_xmitframe++;
251 }
252
253 pmp_priv->free_mp_xmitframe_cnt = NR_MP_XMITFRAME;
254
255 res = _SUCCESS;
256
257 _exit_init_mp_priv:
258
259 return res;
260 }
261 #endif
262
mp_init_xmit_attrib(struct mp_tx * pmptx,PADAPTER padapter)263 static void mp_init_xmit_attrib(struct mp_tx *pmptx, PADAPTER padapter)
264 {
265 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
266
267 struct pkt_attrib *pattrib;
268
269 // init xmitframe attribute
270 pattrib = &pmptx->attrib;
271 _rtw_memset(pattrib, 0, sizeof(struct pkt_attrib));
272 _rtw_memset(pmptx->desc, 0, TXDESC_SIZE);
273
274 pattrib->ether_type = 0x8712;
275 #if 0
276 _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
277 _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
278 #endif
279 _rtw_memset(pattrib->dst, 0xFF, ETH_ALEN);
280
281 // pattrib->dhcp_pkt = 0;
282 // pattrib->pktlen = 0;
283 pattrib->ack_policy = 0;
284 // pattrib->pkt_hdrlen = ETH_HLEN;
285 pattrib->hdrlen = WLAN_HDR_A3_LEN;
286 pattrib->subtype = WIFI_DATA;
287 pattrib->priority = 0;
288 pattrib->qsel = pattrib->priority;
289 // do_queue_select(padapter, pattrib);
290 pattrib->nr_frags = 1;
291 pattrib->encrypt = 0;
292 pattrib->bswenc = _FALSE;
293 pattrib->qos_en = _FALSE;
294
295 pattrib->pktlen = 1500;
296
297 #ifdef CONFIG_80211AC_VHT
298 if (pHalData->rf_type == RF_1T1R)
299 pattrib->raid = RATEID_IDX_VHT_1SS;
300 else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R)
301 pattrib->raid = RATEID_IDX_VHT_2SS;
302 else if (pHalData->rf_type == RF_3T3R)
303 pattrib->raid = RATEID_IDX_VHT_3SS;
304 else
305 pattrib->raid = RATEID_IDX_BGN_40M_1SS;
306 #endif
307 }
308
init_mp_priv(PADAPTER padapter)309 s32 init_mp_priv(PADAPTER padapter)
310 {
311 struct mp_priv *pmppriv = &padapter->mppriv;
312 PHAL_DATA_TYPE pHalData;
313
314 pHalData = GET_HAL_DATA(padapter);
315
316 _init_mp_priv_(pmppriv);
317 pmppriv->papdater = padapter;
318 pmppriv->mp_dm =0;
319 pmppriv->tx.stop = 1;
320 pmppriv->bSetTxPower=0; //for manually set tx power
321 pmppriv->bTxBufCkFail=_FALSE;
322 pmppriv->pktInterval=0;
323
324 mp_init_xmit_attrib(&pmppriv->tx, padapter);
325
326 switch (padapter->registrypriv.rf_config) {
327 case RF_1T1R:
328 pmppriv->antenna_tx = ANTENNA_A;
329 pmppriv->antenna_rx = ANTENNA_A;
330 break;
331 case RF_1T2R:
332 default:
333 pmppriv->antenna_tx = ANTENNA_A;
334 pmppriv->antenna_rx = ANTENNA_AB;
335 break;
336 case RF_2T2R:
337 case RF_2T2R_GREEN:
338 pmppriv->antenna_tx = ANTENNA_AB;
339 pmppriv->antenna_rx = ANTENNA_AB;
340 break;
341 case RF_2T4R:
342 pmppriv->antenna_tx = ANTENNA_BC;
343 pmppriv->antenna_rx = ANTENNA_ABCD;
344 break;
345 }
346
347 pHalData->AntennaRxPath = pmppriv->antenna_rx;
348 pHalData->AntennaTxPath = pmppriv->antenna_tx;
349
350 return _SUCCESS;
351 }
352
free_mp_priv(struct mp_priv * pmp_priv)353 void free_mp_priv(struct mp_priv *pmp_priv)
354 {
355 if (pmp_priv->pallocated_mp_xmitframe_buf) {
356 rtw_mfree(pmp_priv->pallocated_mp_xmitframe_buf, 0);
357 pmp_priv->pallocated_mp_xmitframe_buf = NULL;
358 }
359 pmp_priv->pmp_xmtframe_buf = NULL;
360 }
361
362
PHY_IQCalibrate_default(IN PADAPTER pAdapter,IN BOOLEAN bReCovery)363 static VOID PHY_IQCalibrate_default(
364 IN PADAPTER pAdapter,
365 IN BOOLEAN bReCovery
366 )
367 {
368 DBG_871X("%s\n", __func__);
369 }
370
PHY_LCCalibrate_default(IN PADAPTER pAdapter)371 static VOID PHY_LCCalibrate_default(
372 IN PADAPTER pAdapter
373 )
374 {
375 DBG_871X("%s\n", __func__);
376 }
377
PHY_SetRFPathSwitch_default(IN PADAPTER pAdapter,IN BOOLEAN bMain)378 static VOID PHY_SetRFPathSwitch_default(
379 IN PADAPTER pAdapter,
380 IN BOOLEAN bMain
381 )
382 {
383 DBG_871X("%s\n", __func__);
384 }
385
386
mpt_InitHWConfig(PADAPTER Adapter)387 void mpt_InitHWConfig(PADAPTER Adapter)
388 {
389 if (IS_HARDWARE_TYPE_8723B(Adapter)) {
390 // TODO: <20130114, Kordan> The following setting is only for DPDT and Fixed board type.
391 // TODO: A better solution is configure it according EFUSE during the run-time.
392
393 PHY_SetMacReg(Adapter, 0x64, BIT20, 0x0); //0x66[4]=0
394 PHY_SetMacReg(Adapter, 0x64, BIT24, 0x0); //0x66[8]=0
395 PHY_SetMacReg(Adapter, 0x40, BIT4, 0x0); //0x40[4]=0
396 PHY_SetMacReg(Adapter, 0x40, BIT3, 0x1); //0x40[3]=1
397 PHY_SetMacReg(Adapter, 0x4C, BIT24, 0x1); //0x4C[24:23]=10
398 PHY_SetMacReg(Adapter, 0x4C, BIT23, 0x0); //0x4C[24:23]=10
399 PHY_SetBBReg(Adapter, 0x944, BIT1|BIT0, 0x3); //0x944[1:0]=11
400 PHY_SetBBReg(Adapter, 0x930, bMaskByte0, 0x77); //0x930[7:0]=77
401 PHY_SetMacReg(Adapter, 0x38, BIT11, 0x1); //0x38[11]=1
402
403 // TODO: <20130206, Kordan> The default setting is wrong, hard-coded here.
404 PHY_SetMacReg(Adapter, 0x778, 0x3, 0x3); // Turn off hardware PTA control (Asked by Scott)
405 PHY_SetMacReg(Adapter, 0x64, bMaskDWord, 0x36000000); //Fix BT S0/S1
406 PHY_SetMacReg(Adapter, 0x948, bMaskDWord, 0x0); //Fix BT can't Tx
407
408 /* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou) */
409 PHY_SetBBReg(Adapter, 0xA00, BIT8, 0x0); /*0xA01[0] = 0*/
410 } else if (IS_HARDWARE_TYPE_8821(Adapter)) {
411 /* <20131121, VincentL> Add for 8821AU DPDT setting and fix switching antenna issue (Asked by Rock)
412 <20131122, VincentL> Enable for all 8821A/8811AU (Asked by Alex)*/
413 PHY_SetMacReg(Adapter, 0x4C, BIT23, 0x0); /*0x4C[23:22]=01*/
414 PHY_SetMacReg(Adapter, 0x4C, BIT22, 0x1); /*0x4C[23:22]=01*/
415 } else if (IS_HARDWARE_TYPE_8188ES(Adapter))
416 PHY_SetMacReg(Adapter, 0x4C , BIT23, 0); /*select DPDT_P and DPDT_N as output pin*/
417 #ifdef CONFIG_RTL8814A
418 else if (IS_HARDWARE_TYPE_8814A(Adapter))
419 PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8814A, 0x2000);
420 #endif
421 /*
422 else if(IS_HARDWARE_TYPE_8822B(Adapter))
423 {
424 PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8822B, 0x2000);
425 }*/
426 }
427
428 #ifdef CONFIG_RTL8188E
429 #define PHY_IQCalibrate(a,b) PHY_IQCalibrate_8188E(a,b)
430 #define PHY_LCCalibrate(a) PHY_LCCalibrate_8188E(&(GET_HAL_DATA(a)->odmpriv))
431 #define PHY_SetRFPathSwitch(a,b) PHY_SetRFPathSwitch_8188E(a,b)
432 #endif
433
434 #ifdef CONFIG_RTL8814A
435 #define PHY_IQCalibrate(a,b) PHY_IQCalibrate_8814A(&(GET_HAL_DATA(a)->odmpriv), b)
436 #define PHY_LCCalibrate(a) PHY_LCCalibrate_8814A(&(GET_HAL_DATA(a)->odmpriv))
437 #define PHY_SetRFPathSwitch(a,b) PHY_SetRFPathSwitch_8814A(a,b)
438 #endif /* CONFIG_RTL8814A */
439
440 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
441 /*
442 #define PHY_IQCalibrate(a,b) PHY_IQCalibrate_8812A(a,b)
443 #define PHY_LCCalibrate(a) PHY_LCCalibrate_8812A(&(GET_HAL_DATA(a)->odmpriv))
444 #define PHY_SetRFPathSwitch(a,b) PHY_SetRFPathSwitch_8812A(a,b)
445 */
446
447 #ifndef CONFIG_RTL8812A
448 #define PHY_IQCalibrate_8812A
449 #define PHY_LCCalibrate_8812A
450 #define PHY_SetRFPathSwitch_8812A
451 #endif
452
453 #ifndef CONFIG_RTL8821A
454 #define PHY_IQCalibrate_8821A
455 #define PHY_LCCalibrate_8821A
456 #define PHY_SetRFPathSwitch_8812A
457 #endif
458
459 #define PHY_IQCalibrate(_Adapter, b) \
460 IS_HARDWARE_TYPE_8812(_Adapter) ? PHY_IQCalibrate_8812A(_Adapter, b) : \
461 IS_HARDWARE_TYPE_8821(_Adapter) ? PHY_IQCalibrate_8821A(&(GET_HAL_DATA(_Adapter)->odmpriv), b) : \
462 PHY_IQCalibrate_default(_Adapter, b)
463
464 #define PHY_LCCalibrate(_Adapter) \
465 IS_HARDWARE_TYPE_8812(_Adapter) ? PHY_LCCalibrate_8812A(&(GET_HAL_DATA(_Adapter)->odmpriv)) : \
466 IS_HARDWARE_TYPE_8821(_Adapter) ? PHY_LCCalibrate_8821A(&(GET_HAL_DATA(_Adapter)->odmpriv)) : \
467 PHY_LCCalibrate_default(_Adapter)
468
469 #define PHY_SetRFPathSwitch(_Adapter, b) \
470 (IS_HARDWARE_TYPE_JAGUAR(_Adapter)) ? PHY_SetRFPathSwitch_8812A(_Adapter, b) : \
471 PHY_SetRFPathSwitch_default(_Adapter, b)
472
473 #endif //#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
474 #ifdef CONFIG_RTL8192E
475 #define PHY_IQCalibrate(a,b) PHY_IQCalibrate_8192E(a,b)
476 #define PHY_LCCalibrate(a) PHY_LCCalibrate_8192E(&(GET_HAL_DATA(a)->odmpriv))
477 #define PHY_SetRFPathSwitch(a,b) PHY_SetRFPathSwitch_8192E(a,b)
478 #endif //CONFIG_RTL8812A_8821A
479
480 #ifdef CONFIG_RTL8723B
PHY_IQCalibrate(PADAPTER padapter,u8 bReCovery)481 static void PHY_IQCalibrate(PADAPTER padapter, u8 bReCovery)
482 {
483 PHAL_DATA_TYPE pHalData;
484 u8 b2ant; //false:1ant, true:2-ant
485 u8 RF_Path; //0:S1, 1:S0
486
487 pHalData = GET_HAL_DATA(padapter);
488 b2ant = pHalData->EEPROMBluetoothAntNum==Ant_x2?_TRUE:_FALSE;
489
490 PHY_IQCalibrate_8723B(padapter, bReCovery, _FALSE, b2ant, pHalData->ant_path);
491 }
492
493
494 #define PHY_LCCalibrate(a) PHY_LCCalibrate_8723B(&(GET_HAL_DATA(a)->odmpriv))
495 #define PHY_SetRFPathSwitch(a,b) PHY_SetRFPathSwitch_8723B(a,b)
496 #endif
497
498 #ifdef CONFIG_RTL8703B
PHY_IQCalibrate(PADAPTER padapter,u8 bReCovery)499 static void PHY_IQCalibrate(PADAPTER padapter, u8 bReCovery)
500 {
501 PHY_IQCalibrate_8703B(padapter, bReCovery);
502 }
503
504
505 #define PHY_LCCalibrate(a) PHY_LCCalibrate_8703B(&(GET_HAL_DATA(a)->odmpriv))
506 #define PHY_SetRFPathSwitch(a, b)
507 #endif
508
509 #ifdef CONFIG_RTL8188F
PHY_IQCalibrate(PADAPTER padapter,u8 bReCovery)510 static void PHY_IQCalibrate(PADAPTER padapter, u8 bReCovery)
511 {
512 PHY_IQCalibrate_8188F(padapter, bReCovery, _FALSE);
513 }
514
515
516 #define PHY_LCCalibrate(a) PHY_LCCalibrate_8188F(&(GET_HAL_DATA(a)->odmpriv))
517 #define PHY_SetRFPathSwitch(a, b) PHY_SetRFPathSwitch_8188F(a, b)
518 #endif
519
520 s32
MPT_InitializeAdapter(IN PADAPTER pAdapter,IN u8 Channel)521 MPT_InitializeAdapter(
522 IN PADAPTER pAdapter,
523 IN u8 Channel
524 )
525 {
526 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
527 s32 rtStatus = _SUCCESS;
528 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx;
529 u32 ledsetting;
530 struct mlme_priv *pmlmepriv = &pAdapter->mlmepriv;
531
532 pMptCtx->bMptDrvUnload = _FALSE;
533 pMptCtx->bMassProdTest = _FALSE;
534 pMptCtx->bMptIndexEven = _TRUE; //default gain index is -6.0db
535 pMptCtx->h2cReqNum = 0x0;
536 //init for BT MP
537 #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8821A)
538 pMptCtx->bMPh2c_timeout = _FALSE;
539 pMptCtx->MptH2cRspEvent = _FALSE;
540 pMptCtx->MptBtC2hEvent = _FALSE;
541 _rtw_init_sema(&pMptCtx->MPh2c_Sema, 0);
542 _init_timer( &pMptCtx->MPh2c_timeout_timer, pAdapter->pnetdev, MPh2c_timeout_handle, pAdapter );
543 #endif
544
545 mpt_InitHWConfig(pAdapter);
546
547 #ifdef CONFIG_RTL8723B
548 rtl8723b_InitAntenna_Selection(pAdapter);
549 if (IS_HARDWARE_TYPE_8723B(pAdapter))
550 {
551
552 /* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou)*/
553 PHY_SetBBReg(pAdapter, 0xA00, BIT8, 0x0);
554 PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); /*default use Main*/
555 /*<20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten. */
556 if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90))
557 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E);
558 else
559 PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);
560 }
561 /*set ant to wifi side in mp mode*/
562 rtw_write16(pAdapter, 0x870, 0x300);
563 rtw_write16(pAdapter, 0x860, 0x110);
564 #endif
565
566 pMptCtx->bMptWorkItemInProgress = _FALSE;
567 pMptCtx->CurrMptAct = NULL;
568 pMptCtx->MptRfPath = ODM_RF_PATH_A;
569 //-------------------------------------------------------------------------
570 // Don't accept any packets
571 rtw_write32(pAdapter, REG_RCR, 0);
572
573 //ledsetting = rtw_read32(pAdapter, REG_LEDCFG0);
574 //rtw_write32(pAdapter, REG_LEDCFG0, ledsetting & ~LED0DIS);
575
576 //rtw_write32(pAdapter, REG_LEDCFG0, 0x08080);
577 ledsetting = rtw_read32(pAdapter, REG_LEDCFG0);
578
579
580 PHY_LCCalibrate(pAdapter);
581 PHY_IQCalibrate(pAdapter, _FALSE);
582 //dm_CheckTXPowerTracking(&pHalData->odmpriv); //trigger thermal meter
583
584 PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); //default use Main
585
586 pMptCtx->backup0xc50 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0);
587 pMptCtx->backup0xc58 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0);
588 pMptCtx->backup0xc30 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_RxDetector1, bMaskByte0);
589 pMptCtx->backup0x52_RF_A = (u1Byte)PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
590 pMptCtx->backup0x52_RF_B = (u1Byte)PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
591 #ifdef CONFIG_RTL8188E
592 rtw_write32(pAdapter, REG_MACID_NO_LINK_0, 0x0);
593 rtw_write32(pAdapter, REG_MACID_NO_LINK_1, 0x0);
594 #endif
595 return rtStatus;
596 }
597
598 /*-----------------------------------------------------------------------------
599 * Function: MPT_DeInitAdapter()
600 *
601 * Overview: Extra DeInitialization for Mass Production Test.
602 *
603 * Input: PADAPTER pAdapter
604 *
605 * Output: NONE
606 *
607 * Return: NONE
608 *
609 * Revised History:
610 * When Who Remark
611 * 05/08/2007 MHC Create Version 0.
612 * 05/18/2007 MHC Add normal driver MPHalt code.
613 *
614 *---------------------------------------------------------------------------*/
615 VOID
MPT_DeInitAdapter(IN PADAPTER pAdapter)616 MPT_DeInitAdapter(
617 IN PADAPTER pAdapter
618 )
619 {
620 PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx;
621
622 pMptCtx->bMptDrvUnload = _TRUE;
623 #if defined(CONFIG_RTL8723B)
624 _rtw_free_sema(&(pMptCtx->MPh2c_Sema));
625 _cancel_timer_ex( &pMptCtx->MPh2c_timeout_timer);
626 #endif
627 #if defined(CONFIG_RTL8723B)
628 PHY_SetBBReg(pAdapter,0xA01, BIT0, 1); ///suggestion by jerry for MP Rx.
629 #endif
630 #if 0 // for Windows
631 PlatformFreeWorkItem( &(pMptCtx->MptWorkItem) );
632
633 while(pMptCtx->bMptWorkItemInProgress)
634 {
635 if(NdisWaitEvent(&(pMptCtx->MptWorkItemEvent), 50))
636 {
637 break;
638 }
639 }
640 NdisFreeSpinLock( &(pMptCtx->MptWorkItemSpinLock) );
641 #endif
642 }
643
mpt_ProStartTest(PADAPTER padapter)644 static u8 mpt_ProStartTest(PADAPTER padapter)
645 {
646 PMPT_CONTEXT pMptCtx = &padapter->mppriv.MptCtx;
647
648 pMptCtx->bMassProdTest = _TRUE;
649 pMptCtx->bStartContTx = _FALSE;
650 pMptCtx->bCckContTx = _FALSE;
651 pMptCtx->bOfdmContTx = _FALSE;
652 pMptCtx->bSingleCarrier = _FALSE;
653 pMptCtx->bCarrierSuppression = _FALSE;
654 pMptCtx->bSingleTone = _FALSE;
655
656 return _SUCCESS;
657 }
658
659 /*
660 * General use
661 */
SetPowerTracking(PADAPTER padapter,u8 enable)662 s32 SetPowerTracking(PADAPTER padapter, u8 enable)
663 {
664
665 hal_mpt_SetPowerTracking(padapter, enable);
666 return 0;
667 }
668
GetPowerTracking(PADAPTER padapter,u8 * enable)669 void GetPowerTracking(PADAPTER padapter, u8 *enable)
670 {
671 hal_mpt_GetPowerTracking(padapter, enable);
672 }
673
disable_dm(PADAPTER padapter)674 static void disable_dm(PADAPTER padapter)
675 {
676 u8 v8;
677 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
678 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
679
680 //3 1. disable firmware dynamic mechanism
681 // disable Power Training, Rate Adaptive
682 v8 = rtw_read8(padapter, REG_BCN_CTRL);
683 v8 &= ~EN_BCN_FUNCTION;
684 rtw_write8(padapter, REG_BCN_CTRL, v8);
685
686 //3 2. disable driver dynamic mechanism
687 rtw_phydm_func_disable_all(padapter);
688
689 // enable APK, LCK and IQK but disable power tracking
690 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _FALSE;
691 rtw_phydm_func_set(padapter, ODM_RF_CALIBRATION);
692
693 //#ifdef CONFIG_BT_COEXIST
694 // rtw_btcoex_Switch(padapter, 0); //remove for BT MP Down.
695 //#endif
696 }
697
698
MPT_PwrCtlDM(PADAPTER padapter,u32 bstart)699 void MPT_PwrCtlDM(PADAPTER padapter, u32 bstart)
700 {
701 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
702 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
703
704 if (bstart==1){
705 DBG_871X("in MPT_PwrCtlDM start\n");
706 rtw_phydm_func_set(padapter, ODM_RF_TX_PWR_TRACK | ODM_RF_CALIBRATION);
707
708 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE;
709 padapter->mppriv.mp_dm =1;
710
711 }else{
712 DBG_871X("in MPT_PwrCtlDM stop \n");
713 disable_dm(padapter);
714 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _FALSE;
715 padapter->mppriv.mp_dm = 0;
716 {
717 TXPWRTRACK_CFG c;
718 u1Byte chnl =0 ;
719 _rtw_memset(&c, 0, sizeof(TXPWRTRACK_CFG));
720 ConfigureTxpowerTrack(pDM_Odm, &c);
721 ODM_ClearTxPowerTrackingState(pDM_Odm);
722 if (*c.ODM_TxPwrTrackSetPwr) {
723 (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, ODM_RF_PATH_A, chnl);
724 (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, ODM_RF_PATH_B, chnl);
725 }
726 }
727 }
728
729 }
730
731
mp_join(PADAPTER padapter,u8 mode)732 u32 mp_join(PADAPTER padapter,u8 mode)
733 {
734 WLAN_BSSID_EX bssid;
735 struct sta_info *psta;
736 u32 length;
737 u8 val8;
738 _irqL irqL;
739 s32 res = _SUCCESS;
740
741 struct mp_priv *pmppriv = &padapter->mppriv;
742 struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
743 struct wlan_network *tgt_network = &pmlmepriv->cur_network;
744 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
745 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
746 WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network));
747
748 #ifdef CONFIG_IOCTL_CFG80211
749 struct wireless_dev *pwdev = padapter->rtw_wdev;
750 #endif //#ifdef CONFIG_IOCTL_CFG80211
751 // 1. initialize a new WLAN_BSSID_EX
752 _rtw_memset(&bssid, 0, sizeof(WLAN_BSSID_EX));
753 DBG_8192C("%s ,pmppriv->network_macaddr=%x %x %x %x %x %x \n",__func__,
754 pmppriv->network_macaddr[0],pmppriv->network_macaddr[1],pmppriv->network_macaddr[2],pmppriv->network_macaddr[3],pmppriv->network_macaddr[4],pmppriv->network_macaddr[5]);
755 _rtw_memcpy(bssid.MacAddress, pmppriv->network_macaddr, ETH_ALEN);
756
757 if( mode==WIFI_FW_ADHOC_STATE ){
758 bssid.Ssid.SsidLength = strlen("mp_pseudo_adhoc");
759 _rtw_memcpy(bssid.Ssid.Ssid, (u8*)"mp_pseudo_adhoc", bssid.Ssid.SsidLength);
760 bssid.InfrastructureMode = Ndis802_11IBSS;
761 bssid.NetworkTypeInUse = Ndis802_11DS;
762 bssid.IELength = 0;
763 bssid.Configuration.DSConfig=pmppriv->channel;
764
765 }else if(mode==WIFI_FW_STATION_STATE){
766 bssid.Ssid.SsidLength = strlen("mp_pseudo_STATION");
767 _rtw_memcpy(bssid.Ssid.Ssid, (u8*)"mp_pseudo_STATION", bssid.Ssid.SsidLength);
768 bssid.InfrastructureMode = Ndis802_11Infrastructure;
769 bssid.NetworkTypeInUse = Ndis802_11DS;
770 bssid.IELength = 0;
771 }
772
773 length = get_WLAN_BSSID_EX_sz(&bssid);
774 if (length % 4)
775 bssid.Length = ((length >> 2) + 1) << 2; //round up to multiple of 4 bytes.
776 else
777 bssid.Length = length;
778
779 _enter_critical_bh(&pmlmepriv->lock, &irqL);
780
781 if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)
782 goto end_of_mp_start_test;
783
784 //init mp_start_test status
785 if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
786 rtw_disassoc_cmd(padapter, 500, _TRUE);
787 rtw_indicate_disconnect(padapter);
788 rtw_free_assoc_resources(padapter, 1);
789 }
790 pmppriv->prev_fw_state = get_fwstate(pmlmepriv);
791 pmlmepriv->fw_state = WIFI_MP_STATE;
792
793 set_fwstate(pmlmepriv, _FW_UNDER_LINKING);
794
795 //3 2. create a new psta for mp driver
796 //clear psta in the cur_network, if any
797 psta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress);
798 if (psta) rtw_free_stainfo(padapter, psta);
799
800 psta = rtw_alloc_stainfo(&padapter->stapriv, bssid.MacAddress);
801 if (psta == NULL) {
802 RT_TRACE(_module_mp_, _drv_err_, ("mp_start_test: Can't alloc sta_info!\n"));
803 pmlmepriv->fw_state = pmppriv->prev_fw_state;
804 res = _FAIL;
805 goto end_of_mp_start_test;
806 }
807 set_fwstate(pmlmepriv,WIFI_ADHOC_MASTER_STATE);
808 //3 3. join psudo AdHoc
809 tgt_network->join_res = 1;
810 tgt_network->aid = psta->aid = 1;
811
812 _rtw_memcpy(&padapter->registrypriv.dev_network, &bssid, length);
813 rtw_update_registrypriv_dev_network(padapter);
814 _rtw_memcpy(&tgt_network->network,&padapter->registrypriv.dev_network, padapter->registrypriv.dev_network.Length);
815 _rtw_memcpy(pnetwork,&padapter->registrypriv.dev_network, padapter->registrypriv.dev_network.Length);
816
817 rtw_indicate_connect(padapter);
818 _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
819 set_fwstate(pmlmepriv,_FW_LINKED);
820
821 end_of_mp_start_test:
822
823 _exit_critical_bh(&pmlmepriv->lock, &irqL);
824
825 if(1) //(res == _SUCCESS)
826 {
827 // set MSR to WIFI_FW_ADHOC_STATE
828 if( mode==WIFI_FW_ADHOC_STATE ){
829
830 val8 = rtw_read8(padapter, MSR) & 0xFC; // 0x0102
831 val8 |= WIFI_FW_ADHOC_STATE;
832 rtw_write8(padapter, MSR, val8); // Link in ad hoc network
833 }
834 else {
835 Set_MSR(padapter, WIFI_FW_STATION_STATE);
836
837 DBG_8192C("%s , pmppriv->network_macaddr =%x %x %x %x %x %x\n",__func__,
838 pmppriv->network_macaddr[0],pmppriv->network_macaddr[1],pmppriv->network_macaddr[2],pmppriv->network_macaddr[3],pmppriv->network_macaddr[4],pmppriv->network_macaddr[5]);
839
840 rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmppriv->network_macaddr);
841 }
842 }
843
844 return res;
845 }
846 //This function initializes the DUT to the MP test mode
mp_start_test(PADAPTER padapter)847 s32 mp_start_test(PADAPTER padapter)
848 {
849 struct mp_priv *pmppriv = &padapter->mppriv;
850 s32 res = _SUCCESS;
851
852 padapter->registrypriv.mp_mode = 1;
853
854 //3 disable dynamic mechanism
855 disable_dm(padapter);
856 #ifdef CONFIG_RTL8814A
857 rtl8814_InitHalDm(padapter);
858 #endif /* CONFIG_RTL8814A */
859 #ifdef CONFIG_RTL8812A
860 rtl8812_InitHalDm(padapter);
861 #endif /* CONFIG_RTL8812A */
862 #ifdef CONFIG_RTL8723B
863 rtl8723b_InitHalDm(padapter);
864 #endif /* CONFIG_RTL8723B */
865 #ifdef CONFIG_RTL8703B
866 rtl8703b_InitHalDm(padapter);
867 #endif /* CONFIG_RTL8703B */
868 #ifdef CONFIG_RTL8192E
869 rtl8192e_InitHalDm(padapter);
870 #endif
871 #ifdef CONFIG_RTL8188F
872 rtl8188f_InitHalDm(padapter);
873 #endif
874 #ifdef CONFIG_RTL8188E
875 rtl8188e_InitHalDm(padapter);
876 #endif
877
878 //3 0. update mp_priv
879
880 if (padapter->registrypriv.rf_config == RF_MAX_TYPE) {
881 // switch (phal->rf_type) {
882 switch (GET_RF_TYPE(padapter)) {
883 case RF_1T1R:
884 pmppriv->antenna_tx = ANTENNA_A;
885 pmppriv->antenna_rx = ANTENNA_A;
886 break;
887 case RF_1T2R:
888 default:
889 pmppriv->antenna_tx = ANTENNA_A;
890 pmppriv->antenna_rx = ANTENNA_AB;
891 break;
892 case RF_2T2R:
893 case RF_2T2R_GREEN:
894 pmppriv->antenna_tx = ANTENNA_AB;
895 pmppriv->antenna_rx = ANTENNA_AB;
896 break;
897 case RF_2T4R:
898 pmppriv->antenna_tx = ANTENNA_AB;
899 pmppriv->antenna_rx = ANTENNA_ABCD;
900 break;
901 }
902 }
903
904 mpt_ProStartTest(padapter);
905
906 mp_join(padapter,WIFI_FW_ADHOC_STATE);
907
908 return res;
909 }
910 //------------------------------------------------------------------------------
911 //This function change the DUT from the MP test mode into normal mode
mp_stop_test(PADAPTER padapter)912 void mp_stop_test(PADAPTER padapter)
913 {
914 struct mp_priv *pmppriv = &padapter->mppriv;
915 struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
916 struct wlan_network *tgt_network = &pmlmepriv->cur_network;
917 struct sta_info *psta;
918
919 _irqL irqL;
920
921 if(pmppriv->mode==MP_ON)
922 {
923 pmppriv->bSetTxPower=0;
924 _enter_critical_bh(&pmlmepriv->lock, &irqL);
925 if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _FALSE)
926 goto end_of_mp_stop_test;
927
928 //3 1. disconnect psudo AdHoc
929 rtw_indicate_disconnect(padapter);
930
931 //3 2. clear psta used in mp test mode.
932 // rtw_free_assoc_resources(padapter, 1);
933 psta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress);
934 if (psta) rtw_free_stainfo(padapter, psta);
935
936 //3 3. return to normal state (default:station mode)
937 pmlmepriv->fw_state = pmppriv->prev_fw_state; // WIFI_STATION_STATE;
938
939 //flush the cur_network
940 _rtw_memset(tgt_network, 0, sizeof(struct wlan_network));
941
942 _clr_fwstate_(pmlmepriv, WIFI_MP_STATE);
943
944 end_of_mp_stop_test:
945
946 _exit_critical_bh(&pmlmepriv->lock, &irqL);
947
948 #ifdef CONFIG_RTL8812A
949 rtl8812_InitHalDm(padapter);
950 #endif
951 #ifdef CONFIG_RTL8723B
952 rtl8723b_InitHalDm(padapter);
953 #endif
954 #ifdef CONFIG_RTL8703B
955 rtl8703b_InitHalDm(padapter);
956 #endif
957 #ifdef CONFIG_RTL8192E
958 rtl8192e_InitHalDm(padapter);
959 #endif
960 #ifdef CONFIG_RTL8188F
961 rtl8188f_InitHalDm(padapter);
962 #endif
963 }
964 }
965 /*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/
966 #if 0
967 //#ifdef CONFIG_USB_HCI
968 static VOID mpt_AdjustRFRegByRateByChan92CU(PADAPTER pAdapter, u8 RateIdx, u8 Channel, u8 BandWidthID)
969 {
970 u8 eRFPath;
971 u32 rfReg0x26;
972 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
973
974
975 if (RateIdx < MPT_RATE_6M) { // CCK rate,for 88cu
976 rfReg0x26 = 0xf400;
977 }
978 else if ((RateIdx >= MPT_RATE_6M) && (RateIdx <= MPT_RATE_54M)) {// OFDM rate,for 88cu
979 if ((4 == Channel) || (8 == Channel) || (12 == Channel))
980 rfReg0x26 = 0xf000;
981 else if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel))
982 rfReg0x26 = 0xf400;
983 else
984 rfReg0x26 = 0x4f200;
985 }
986 else if ((RateIdx >= MPT_RATE_MCS0) && (RateIdx <= MPT_RATE_MCS15)) {// MCS 20M ,for 88cu // MCS40M rate,for 88cu
987
988 if (CHANNEL_WIDTH_20 == BandWidthID) {
989 if ((4 == Channel) || (8 == Channel))
990 rfReg0x26 = 0xf000;
991 else if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel))
992 rfReg0x26 = 0xf400;
993 else
994 rfReg0x26 = 0x4f200;
995 }
996 else{
997 if ((4 == Channel) || (8 == Channel))
998 rfReg0x26 = 0xf000;
999 else if ((5 == Channel) || (7 == Channel))
1000 rfReg0x26 = 0xf400;
1001 else
1002 rfReg0x26 = 0x4f200;
1003 }
1004 }
1005
1006 // RT_TRACE(COMP_CMD, DBG_LOUD, ("\n mpt_AdjustRFRegByRateByChan92CU():Chan:%d Rate=%d rfReg0x26:0x%08x\n",Channel, RateIdx,rfReg0x26));
1007 for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) {
1008 write_rfreg(pAdapter, eRFPath, RF_SYN_G2, rfReg0x26);
1009 }
1010 }
1011 #endif
1012 /*-----------------------------------------------------------------------------
1013 * Function: mpt_SwitchRfSetting
1014 *
1015 * Overview: Change RF Setting when we siwthc channel/rate/BW for MP.
1016 *
1017 * Input: IN PADAPTER pAdapter
1018 *
1019 * Output: NONE
1020 *
1021 * Return: NONE
1022 *
1023 * Revised History:
1024 * When Who Remark
1025 * 01/08/2009 MHC Suggestion from SD3 Willis for 92S series.
1026 * 01/09/2009 MHC Add CCK modification for 40MHZ. Suggestion from SD3.
1027 *
1028 *---------------------------------------------------------------------------*/
mpt_SwitchRfSetting(PADAPTER pAdapter)1029 static void mpt_SwitchRfSetting(PADAPTER pAdapter)
1030 {
1031 hal_mpt_SwitchRfSetting(pAdapter);
1032 }
1033
1034 /*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/
1035 /*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
MPT_CCKTxPowerAdjust(PADAPTER Adapter,BOOLEAN bInCH14)1036 static void MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
1037 {
1038 hal_mpt_CCKTxPowerAdjust(Adapter, bInCH14);
1039 }
1040
MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter,BOOLEAN beven)1041 static void MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven)
1042 {
1043 hal_mpt_CCKTxPowerAdjustbyIndex(pAdapter, beven);
1044 }
1045
1046 /*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
1047
1048 /*
1049 * SetChannel
1050 * Description
1051 * Use H2C command to change channel,
1052 * not only modify rf register, but also other setting need to be done.
1053 */
SetChannel(PADAPTER pAdapter)1054 void SetChannel(PADAPTER pAdapter)
1055 {
1056 hal_mpt_SetChannel(pAdapter);
1057 }
1058
1059 /*
1060 * Notice
1061 * Switch bandwitdth may change center frequency(channel)
1062 */
SetBandwidth(PADAPTER pAdapter)1063 void SetBandwidth(PADAPTER pAdapter)
1064 {
1065 hal_mpt_SetBandwidth(pAdapter);
1066
1067 }
1068
SetAntenna(PADAPTER pAdapter)1069 void SetAntenna(PADAPTER pAdapter)
1070 {
1071 hal_mpt_SetAntenna(pAdapter);
1072 }
1073
SetTxPower(PADAPTER pAdapter)1074 int SetTxPower(PADAPTER pAdapter)
1075 {
1076
1077 hal_mpt_SetTxPower(pAdapter);
1078 return _TRUE;
1079 }
1080
SetTxAGCOffset(PADAPTER pAdapter,u32 ulTxAGCOffset)1081 void SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset)
1082 {
1083 u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D,tmpAGC;
1084
1085 TxAGCOffset_B = (ulTxAGCOffset&0x000000ff);
1086 TxAGCOffset_C = ((ulTxAGCOffset&0x0000ff00)>>8);
1087 TxAGCOffset_D = ((ulTxAGCOffset&0x00ff0000)>>16);
1088
1089 tmpAGC = (TxAGCOffset_D<<8 | TxAGCOffset_C<<4 | TxAGCOffset_B);
1090 write_bbreg(pAdapter, rFPGA0_TxGainStage,
1091 (bXBTxAGC|bXCTxAGC|bXDTxAGC), tmpAGC);
1092 }
1093
SetDataRate(PADAPTER pAdapter)1094 void SetDataRate(PADAPTER pAdapter)
1095 {
1096 hal_mpt_SetDataRate(pAdapter);
1097 }
1098
MP_PHY_SetRFPathSwitch(PADAPTER pAdapter,BOOLEAN bMain)1099 void MP_PHY_SetRFPathSwitch(PADAPTER pAdapter ,BOOLEAN bMain)
1100 {
1101
1102 PHY_SetRFPathSwitch(pAdapter, bMain);
1103
1104 }
1105
1106
SetThermalMeter(PADAPTER pAdapter,u8 target_ther)1107 s32 SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
1108 {
1109 return hal_mpt_SetThermalMeter(pAdapter, target_ther);
1110 }
1111
TriggerRFThermalMeter(PADAPTER pAdapter)1112 static void TriggerRFThermalMeter(PADAPTER pAdapter)
1113 {
1114 hal_mpt_TriggerRFThermalMeter(pAdapter);
1115 }
1116
ReadRFThermalMeter(PADAPTER pAdapter)1117 static u8 ReadRFThermalMeter(PADAPTER pAdapter)
1118 {
1119 return hal_mpt_ReadRFThermalMeter(pAdapter);
1120 }
1121
GetThermalMeter(PADAPTER pAdapter,u8 * value)1122 void GetThermalMeter(PADAPTER pAdapter, u8 *value)
1123 {
1124 hal_mpt_GetThermalMeter(pAdapter, value);
1125 }
1126
SetSingleCarrierTx(PADAPTER pAdapter,u8 bStart)1127 void SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
1128 {
1129 PhySetTxPowerLevel(pAdapter);
1130 hal_mpt_SetSingleCarrierTx(pAdapter, bStart);
1131 }
1132
SetSingleToneTx(PADAPTER pAdapter,u8 bStart)1133 void SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
1134 {
1135 PhySetTxPowerLevel(pAdapter);
1136 hal_mpt_SetSingleToneTx(pAdapter, bStart);
1137 }
1138
SetCarrierSuppressionTx(PADAPTER pAdapter,u8 bStart)1139 void SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
1140 {
1141 PhySetTxPowerLevel(pAdapter);
1142 hal_mpt_SetCarrierSuppressionTx(pAdapter, bStart);
1143 }
1144
SetCCKContinuousTx(PADAPTER pAdapter,u8 bStart)1145 void SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart)
1146 {
1147 PhySetTxPowerLevel(pAdapter);
1148 hal_mpt_SetCCKContinuousTx(pAdapter, bStart);
1149 }
1150
SetOFDMContinuousTx(PADAPTER pAdapter,u8 bStart)1151 void SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart)
1152 {
1153 PhySetTxPowerLevel(pAdapter);
1154 hal_mpt_SetOFDMContinuousTx(pAdapter, bStart);
1155 }/* mpt_StartOfdmContTx */
1156
SetContinuousTx(PADAPTER pAdapter,u8 bStart)1157 void SetContinuousTx(PADAPTER pAdapter, u8 bStart)
1158 {
1159 PhySetTxPowerLevel(pAdapter);
1160 hal_mpt_SetContinuousTx(pAdapter, bStart);
1161 }
1162
1163
PhySetTxPowerLevel(PADAPTER pAdapter)1164 void PhySetTxPowerLevel(PADAPTER pAdapter)
1165 {
1166 struct mp_priv *pmp_priv = &pAdapter->mppriv;
1167
1168 if (pmp_priv->bSetTxPower==0) // for NO manually set power index
1169 {
1170 #ifdef CONFIG_RTL8188E
1171 PHY_SetTxPowerLevel8188E(pAdapter,pmp_priv->channel);
1172 #endif
1173 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
1174 PHY_SetTxPowerLevel8812(pAdapter,pmp_priv->channel);
1175 #endif
1176 #if defined(CONFIG_RTL8192E)
1177 PHY_SetTxPowerLevel8192E(pAdapter,pmp_priv->channel);
1178 #endif
1179 #if defined(CONFIG_RTL8723B)
1180 PHY_SetTxPowerLevel8723B(pAdapter,pmp_priv->channel);
1181 #endif
1182 #if defined(CONFIG_RTL8188F)
1183 PHY_SetTxPowerLevel8188F(pAdapter, pmp_priv->channel);
1184 #endif
1185 mpt_ProQueryCalTxPower(pAdapter,pmp_priv->antenna_tx);
1186
1187 }
1188 }
1189
1190 //------------------------------------------------------------------------------
dump_mpframe(PADAPTER padapter,struct xmit_frame * pmpframe)1191 static void dump_mpframe(PADAPTER padapter, struct xmit_frame *pmpframe)
1192 {
1193 rtw_hal_mgnt_xmit(padapter, pmpframe);
1194 }
1195
alloc_mp_xmitframe(struct xmit_priv * pxmitpriv)1196 static struct xmit_frame *alloc_mp_xmitframe(struct xmit_priv *pxmitpriv)
1197 {
1198 struct xmit_frame *pmpframe;
1199 struct xmit_buf *pxmitbuf;
1200
1201 if ((pmpframe = rtw_alloc_xmitframe(pxmitpriv)) == NULL)
1202 {
1203 return NULL;
1204 }
1205
1206 if ((pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv)) == NULL)
1207 {
1208 rtw_free_xmitframe(pxmitpriv, pmpframe);
1209 return NULL;
1210 }
1211
1212 pmpframe->frame_tag = MP_FRAMETAG;
1213
1214 pmpframe->pxmitbuf = pxmitbuf;
1215
1216 pmpframe->buf_addr = pxmitbuf->pbuf;
1217
1218 pxmitbuf->priv_data = pmpframe;
1219
1220 return pmpframe;
1221
1222 }
1223
mp_xmit_packet_thread(thread_context context)1224 static thread_return mp_xmit_packet_thread(thread_context context)
1225 {
1226 struct xmit_frame *pxmitframe;
1227 struct mp_tx *pmptx;
1228 struct mp_priv *pmp_priv;
1229 struct xmit_priv *pxmitpriv;
1230 PADAPTER padapter;
1231
1232 pmp_priv = (struct mp_priv *)context;
1233 pmptx = &pmp_priv->tx;
1234 padapter = pmp_priv->papdater;
1235 pxmitpriv = &(padapter->xmitpriv);
1236
1237 thread_enter("RTW_MP_THREAD");
1238
1239 DBG_871X("%s:pkTx Start\n", __func__);
1240 while (1) {
1241 pxmitframe = alloc_mp_xmitframe(pxmitpriv);
1242 if (pxmitframe == NULL) {
1243 if (pmptx->stop ||
1244 RTW_CANNOT_RUN(padapter)) {
1245 goto exit;
1246 }
1247 else {
1248 rtw_usleep_os(10);
1249 continue;
1250 }
1251 }
1252 _rtw_memcpy((u8 *)(pxmitframe->buf_addr+TXDESC_OFFSET), pmptx->buf, pmptx->write_size);
1253 _rtw_memcpy(&(pxmitframe->attrib), &(pmptx->attrib), sizeof(struct pkt_attrib));
1254
1255
1256 rtw_usleep_os(padapter->mppriv.pktInterval);
1257 dump_mpframe(padapter, pxmitframe);
1258
1259 pmptx->sended++;
1260 pmp_priv->tx_pktcount++;
1261
1262 if (pmptx->stop ||
1263 RTW_CANNOT_RUN(padapter))
1264 goto exit;
1265 if ((pmptx->count != 0) &&
1266 (pmptx->count == pmptx->sended))
1267 goto exit;
1268
1269 flush_signals_thread();
1270 }
1271
1272 exit:
1273 //DBG_871X("%s:pkTx Exit\n", __func__);
1274 rtw_mfree(pmptx->pallocated_buf, pmptx->buf_size);
1275 pmptx->pallocated_buf = NULL;
1276 pmptx->stop = 1;
1277
1278 thread_exit(NULL);
1279 return 0;
1280 }
1281
fill_txdesc_for_mp(PADAPTER padapter,u8 * ptxdesc)1282 void fill_txdesc_for_mp(PADAPTER padapter, u8 *ptxdesc)
1283 {
1284 struct mp_priv *pmp_priv = &padapter->mppriv;
1285 _rtw_memcpy(ptxdesc, pmp_priv->tx.desc, TXDESC_SIZE);
1286 }
1287
1288 #if defined(CONFIG_RTL8188E)
fill_tx_desc_8188e(PADAPTER padapter)1289 void fill_tx_desc_8188e(PADAPTER padapter)
1290 {
1291 struct mp_priv *pmp_priv = &padapter->mppriv;
1292 struct tx_desc *desc = (struct tx_desc *)&(pmp_priv->tx.desc);
1293 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1294 u32 pkt_size = pattrib->last_txcmdsz;
1295 s32 bmcast = IS_MCAST(pattrib->ra);
1296 // offset 0
1297 #if !defined(CONFIG_RTL8188E_SDIO) && !defined(CONFIG_PCI_HCI)
1298 desc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
1299 desc->txdw0 |= cpu_to_le32(pkt_size & 0x0000FFFF); // packet size
1300 desc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) & 0x00FF0000); //32 bytes for TX Desc
1301 if (bmcast) desc->txdw0 |= cpu_to_le32(BMC); // broadcast packet
1302
1303 desc->txdw1 |= cpu_to_le32((0x01 << 26) & 0xff000000);
1304 #endif
1305
1306 desc->txdw1 |= cpu_to_le32((pattrib->mac_id) & 0x3F); //CAM_ID(MAC_ID)
1307 desc->txdw1 |= cpu_to_le32((pattrib->qsel << QSEL_SHT) & 0x00001F00); // Queue Select, TID
1308 desc->txdw1 |= cpu_to_le32((pattrib->raid << RATE_ID_SHT) & 0x000F0000); // Rate Adaptive ID
1309 // offset 8
1310 // desc->txdw2 |= cpu_to_le32(AGG_BK);//AGG BK
1311
1312 desc->txdw3 |= cpu_to_le32((pattrib->seqnum<<16)&0x0fff0000);
1313 desc->txdw4 |= cpu_to_le32(HW_SSN);
1314
1315 desc->txdw4 |= cpu_to_le32(USERATE);
1316 desc->txdw4 |= cpu_to_le32(DISDATAFB);
1317
1318 if( pmp_priv->preamble ){
1319 if (pmp_priv->rateidx <= MPT_RATE_54M)
1320 desc->txdw4 |= cpu_to_le32(DATA_SHORT); // CCK Short Preamble
1321 }
1322
1323 if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1324 desc->txdw4 |= cpu_to_le32(DATA_BW);
1325
1326 // offset 20
1327 desc->txdw5 |= cpu_to_le32(pmp_priv->rateidx & 0x0000001F);
1328
1329 if( pmp_priv->preamble ){
1330 if (pmp_priv->rateidx > MPT_RATE_54M)
1331 desc->txdw5 |= cpu_to_le32(SGI); // MCS Short Guard Interval
1332 }
1333
1334 desc->txdw5 |= cpu_to_le32(RTY_LMT_EN); // retry limit enable
1335 desc->txdw5 |= cpu_to_le32(0x00180000); // DATA/RTS Rate Fallback Limit
1336
1337
1338 }
1339 #endif
1340
1341 #if defined(CONFIG_RTL8814A)
fill_tx_desc_8814a(PADAPTER padapter)1342 void fill_tx_desc_8814a(PADAPTER padapter)
1343 {
1344 struct mp_priv *pmp_priv = &padapter->mppriv;
1345 u8 *pDesc = (u8 *)&(pmp_priv->tx.desc);
1346 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1347
1348 u32 pkt_size = pattrib->last_txcmdsz;
1349 s32 bmcast = IS_MCAST(pattrib->ra);
1350 u8 data_rate,pwr_status,offset;
1351
1352 //SET_TX_DESC_FIRST_SEG_8814A(pDesc, 1);
1353 SET_TX_DESC_LAST_SEG_8814A(pDesc, 1);
1354 //SET_TX_DESC_OWN_(pDesc, 1);
1355
1356 SET_TX_DESC_PKT_SIZE_8814A(pDesc, pkt_size);
1357
1358 offset = TXDESC_SIZE + OFFSET_SZ;
1359
1360 SET_TX_DESC_OFFSET_8814A(pDesc, offset);
1361 SET_TX_DESC_PKT_OFFSET_8814A(pDesc, 1);
1362
1363 if (bmcast) {
1364 SET_TX_DESC_BMC_8814A(pDesc, 1);
1365 }
1366
1367 SET_TX_DESC_MACID_8814A(pDesc, pattrib->mac_id);
1368 SET_TX_DESC_RATE_ID_8814A(pDesc, pattrib->raid);
1369
1370 //SET_TX_DESC_RATE_ID_8812(pDesc, RATEID_IDX_G);
1371 SET_TX_DESC_QUEUE_SEL_8814A(pDesc, pattrib->qsel);
1372 //SET_TX_DESC_QUEUE_SEL_8812(pDesc, QSLT_MGNT);
1373
1374 if ( pmp_priv->preamble ){
1375 SET_TX_DESC_DATA_SHORT_8814A(pDesc, 1);
1376 }
1377
1378 if (!pattrib->qos_en) {
1379 SET_TX_DESC_HWSEQ_EN_8814A(pDesc, 1); // Hw set sequence number
1380 } else {
1381 SET_TX_DESC_SEQ_8814A(pDesc, pattrib->seqnum);
1382 }
1383
1384 if (pmp_priv->bandwidth <= CHANNEL_WIDTH_160) {
1385 SET_TX_DESC_DATA_BW_8814A(pDesc, pmp_priv->bandwidth);
1386 } else {
1387 DBG_871X("%s:Err: unknown bandwidth %d, use 20M\n", __func__,pmp_priv->bandwidth);
1388 SET_TX_DESC_DATA_BW_8814A(pDesc, CHANNEL_WIDTH_20);
1389 }
1390
1391 SET_TX_DESC_DISABLE_FB_8814A(pDesc, 1);
1392 SET_TX_DESC_USE_RATE_8814A(pDesc, 1);
1393 SET_TX_DESC_TX_RATE_8814A(pDesc, pmp_priv->rateidx);
1394
1395 }
1396 #endif
1397
1398 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
fill_tx_desc_8812a(PADAPTER padapter)1399 void fill_tx_desc_8812a(PADAPTER padapter)
1400 {
1401 struct mp_priv *pmp_priv = &padapter->mppriv;
1402 u8 *pDesc = (u8 *)&(pmp_priv->tx.desc);
1403 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1404
1405 u32 pkt_size = pattrib->last_txcmdsz;
1406 s32 bmcast = IS_MCAST(pattrib->ra);
1407 u8 data_rate,pwr_status,offset;
1408
1409 SET_TX_DESC_FIRST_SEG_8812(pDesc, 1);
1410 SET_TX_DESC_LAST_SEG_8812(pDesc, 1);
1411 SET_TX_DESC_OWN_8812(pDesc, 1);
1412
1413 SET_TX_DESC_PKT_SIZE_8812(pDesc, pkt_size);
1414
1415 offset = TXDESC_SIZE + OFFSET_SZ;
1416
1417 SET_TX_DESC_OFFSET_8812(pDesc, offset);
1418 SET_TX_DESC_PKT_OFFSET_8812(pDesc, 1);
1419
1420 if (bmcast) {
1421 SET_TX_DESC_BMC_8812(pDesc, 1);
1422 }
1423
1424 SET_TX_DESC_MACID_8812(pDesc, pattrib->mac_id);
1425 SET_TX_DESC_RATE_ID_8812(pDesc, pattrib->raid);
1426
1427 //SET_TX_DESC_RATE_ID_8812(pDesc, RATEID_IDX_G);
1428 SET_TX_DESC_QUEUE_SEL_8812(pDesc, pattrib->qsel);
1429 //SET_TX_DESC_QUEUE_SEL_8812(pDesc, QSLT_MGNT);
1430
1431 if (!pattrib->qos_en) {
1432 SET_TX_DESC_HWSEQ_EN_8812(pDesc, 1); // Hw set sequence number
1433 } else {
1434 SET_TX_DESC_SEQ_8812(pDesc, pattrib->seqnum);
1435 }
1436
1437 if (pmp_priv->bandwidth <= CHANNEL_WIDTH_160) {
1438 SET_TX_DESC_DATA_BW_8812(pDesc, pmp_priv->bandwidth);
1439 } else {
1440 DBG_871X("%s:Err: unknown bandwidth %d, use 20M\n", __func__,pmp_priv->bandwidth);
1441 SET_TX_DESC_DATA_BW_8812(pDesc, CHANNEL_WIDTH_20);
1442 }
1443
1444 SET_TX_DESC_DISABLE_FB_8812(pDesc, 1);
1445 SET_TX_DESC_USE_RATE_8812(pDesc, 1);
1446 SET_TX_DESC_TX_RATE_8812(pDesc, pmp_priv->rateidx);
1447
1448 }
1449 #endif
1450 #if defined(CONFIG_RTL8192E)
fill_tx_desc_8192e(PADAPTER padapter)1451 void fill_tx_desc_8192e(PADAPTER padapter)
1452 {
1453 struct mp_priv *pmp_priv = &padapter->mppriv;
1454 u8 *pDesc = (u8 *)&(pmp_priv->tx.desc);
1455 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1456
1457 u32 pkt_size = pattrib->last_txcmdsz;
1458 s32 bmcast = IS_MCAST(pattrib->ra);
1459 u8 data_rate,pwr_status,offset;
1460
1461
1462 SET_TX_DESC_PKT_SIZE_92E(pDesc, pkt_size);
1463
1464 offset = TXDESC_SIZE + OFFSET_SZ;
1465
1466 SET_TX_DESC_OFFSET_92E(pDesc, offset);
1467 #if defined(CONFIG_PCI_HCI) /* 8192EE */
1468
1469 SET_TX_DESC_PKT_OFFSET_92E(pDesc, 0); /* 8192EE pkt_offset is 0 */
1470 #else /* 8192EU 8192ES */
1471 SET_TX_DESC_PKT_OFFSET_92E(pDesc, 1);
1472 #endif
1473
1474 if (bmcast) {
1475 SET_TX_DESC_BMC_92E(pDesc, 1);
1476 }
1477
1478 SET_TX_DESC_MACID_92E(pDesc, pattrib->mac_id);
1479 SET_TX_DESC_RATE_ID_92E(pDesc, pattrib->raid);
1480
1481
1482 SET_TX_DESC_QUEUE_SEL_92E(pDesc, pattrib->qsel);
1483 //SET_TX_DESC_QUEUE_SEL_8812(pDesc, QSLT_MGNT);
1484
1485 if (!pattrib->qos_en) {
1486 SET_TX_DESC_EN_HWSEQ_92E(pDesc, 1);// Hw set sequence number
1487 SET_TX_DESC_HWSEQ_SEL_92E(pDesc, pattrib->hw_ssn_sel);
1488 } else {
1489 SET_TX_DESC_SEQ_92E(pDesc, pattrib->seqnum);
1490 }
1491
1492 if ((pmp_priv->bandwidth == CHANNEL_WIDTH_20) || (pmp_priv->bandwidth == CHANNEL_WIDTH_40)) {
1493 SET_TX_DESC_DATA_BW_92E(pDesc, pmp_priv->bandwidth);
1494 } else {
1495 DBG_871X("%s:Err: unknown bandwidth %d, use 20M\n", __func__,pmp_priv->bandwidth);
1496 SET_TX_DESC_DATA_BW_92E(pDesc, CHANNEL_WIDTH_20);
1497 }
1498
1499 //SET_TX_DESC_DATA_SC_92E(pDesc, SCMapping_92E(padapter,pattrib));
1500
1501 SET_TX_DESC_DISABLE_FB_92E(pDesc, 1);
1502 SET_TX_DESC_USE_RATE_92E(pDesc, 1);
1503 SET_TX_DESC_TX_RATE_92E(pDesc, pmp_priv->rateidx);
1504
1505 }
1506 #endif
1507
1508 #if defined(CONFIG_RTL8723B)
fill_tx_desc_8723b(PADAPTER padapter)1509 void fill_tx_desc_8723b(PADAPTER padapter)
1510 {
1511 struct mp_priv *pmp_priv = &padapter->mppriv;
1512 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1513 u8 *ptxdesc = pmp_priv->tx.desc;
1514
1515 SET_TX_DESC_AGG_BREAK_8723B(ptxdesc, 1);
1516 SET_TX_DESC_MACID_8723B(ptxdesc, pattrib->mac_id);
1517 SET_TX_DESC_QUEUE_SEL_8723B(ptxdesc, pattrib->qsel);
1518
1519 SET_TX_DESC_RATE_ID_8723B(ptxdesc, pattrib->raid);
1520 SET_TX_DESC_SEQ_8723B(ptxdesc, pattrib->seqnum);
1521 SET_TX_DESC_HWSEQ_EN_8723B(ptxdesc, 1);
1522 SET_TX_DESC_USE_RATE_8723B(ptxdesc, 1);
1523 SET_TX_DESC_DISABLE_FB_8723B(ptxdesc, 1);
1524
1525 if (pmp_priv->preamble)
1526 if (pmp_priv->rateidx <= MPT_RATE_54M) {
1527 SET_TX_DESC_DATA_SHORT_8723B(ptxdesc, 1);
1528 }
1529
1530 if (pmp_priv->bandwidth == CHANNEL_WIDTH_40) {
1531 SET_TX_DESC_DATA_BW_8723B(ptxdesc, 1);
1532 }
1533
1534 SET_TX_DESC_TX_RATE_8723B(ptxdesc, pmp_priv->rateidx);
1535
1536 SET_TX_DESC_DATA_RATE_FB_LIMIT_8723B(ptxdesc, 0x1F);
1537 SET_TX_DESC_RTS_RATE_FB_LIMIT_8723B(ptxdesc, 0xF);
1538 }
1539 #endif
1540
1541 #if defined(CONFIG_RTL8703B)
fill_tx_desc_8703b(PADAPTER padapter)1542 void fill_tx_desc_8703b(PADAPTER padapter)
1543 {
1544 struct mp_priv *pmp_priv = &padapter->mppriv;
1545 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1546 u8 *ptxdesc = pmp_priv->tx.desc;
1547
1548 SET_TX_DESC_AGG_BREAK_8703B(ptxdesc, 1);
1549 SET_TX_DESC_MACID_8703B(ptxdesc, pattrib->mac_id);
1550 SET_TX_DESC_QUEUE_SEL_8703B(ptxdesc, pattrib->qsel);
1551
1552 SET_TX_DESC_RATE_ID_8703B(ptxdesc, pattrib->raid);
1553 SET_TX_DESC_SEQ_8703B(ptxdesc, pattrib->seqnum);
1554 SET_TX_DESC_HWSEQ_EN_8703B(ptxdesc, 1);
1555 SET_TX_DESC_USE_RATE_8703B(ptxdesc, 1);
1556 SET_TX_DESC_DISABLE_FB_8703B(ptxdesc, 1);
1557
1558 if (pmp_priv->preamble) {
1559 if (pmp_priv->rateidx <= MPT_RATE_54M)
1560 SET_TX_DESC_DATA_SHORT_8703B(ptxdesc, 1);
1561 }
1562
1563 if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1564 SET_TX_DESC_DATA_BW_8703B(ptxdesc, 1);
1565
1566 SET_TX_DESC_TX_RATE_8703B(ptxdesc, pmp_priv->rateidx);
1567
1568 SET_TX_DESC_DATA_RATE_FB_LIMIT_8703B(ptxdesc, 0x1F);
1569 SET_TX_DESC_RTS_RATE_FB_LIMIT_8703B(ptxdesc, 0xF);
1570 }
1571 #endif
1572
1573 #if defined(CONFIG_RTL8188F)
fill_tx_desc_8188f(PADAPTER padapter)1574 void fill_tx_desc_8188f(PADAPTER padapter)
1575 {
1576 struct mp_priv *pmp_priv = &padapter->mppriv;
1577 struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1578 u8 *ptxdesc = pmp_priv->tx.desc;
1579
1580 SET_TX_DESC_AGG_BREAK_8188F(ptxdesc, 1);
1581 SET_TX_DESC_MACID_8188F(ptxdesc, pattrib->mac_id);
1582 SET_TX_DESC_QUEUE_SEL_8188F(ptxdesc, pattrib->qsel);
1583
1584 SET_TX_DESC_RATE_ID_8188F(ptxdesc, pattrib->raid);
1585 SET_TX_DESC_SEQ_8188F(ptxdesc, pattrib->seqnum);
1586 SET_TX_DESC_HWSEQ_EN_8188F(ptxdesc, 1);
1587 SET_TX_DESC_USE_RATE_8188F(ptxdesc, 1);
1588 SET_TX_DESC_DISABLE_FB_8188F(ptxdesc, 1);
1589
1590 if (pmp_priv->preamble)
1591 if (pmp_priv->rateidx <= MPT_RATE_54M)
1592 SET_TX_DESC_DATA_SHORT_8188F(ptxdesc, 1);
1593
1594 if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1595 SET_TX_DESC_DATA_BW_8188F(ptxdesc, 1);
1596
1597 SET_TX_DESC_TX_RATE_8188F(ptxdesc, pmp_priv->rateidx);
1598
1599 SET_TX_DESC_DATA_RATE_FB_LIMIT_8188F(ptxdesc, 0x1F);
1600 SET_TX_DESC_RTS_RATE_FB_LIMIT_8188F(ptxdesc, 0xF);
1601 }
1602 #endif
1603
Rtw_MPSetMacTxEDCA(PADAPTER padapter)1604 static void Rtw_MPSetMacTxEDCA(PADAPTER padapter)
1605 {
1606
1607 rtw_write32(padapter, 0x508 , 0x00a422); //Disable EDCA BE Txop for MP pkt tx adjust Packet interval
1608 //DBG_871X("%s:write 0x508~~~~~~ 0x%x\n", __func__,rtw_read32(padapter, 0x508));
1609 PHY_SetMacReg(padapter, 0x458 ,bMaskDWord , 0x0);
1610 //DBG_8192C("%s()!!!!! 0x460 = 0x%x\n" ,__func__,PHY_QueryBBReg(padapter, 0x460, bMaskDWord));
1611 PHY_SetMacReg(padapter, 0x460 ,bMaskLWord , 0x0);//fast EDCA queue packet interval & time out vaule
1612 //PHY_SetMacReg(padapter, ODM_EDCA_VO_PARAM ,bMaskLWord , 0x431C);
1613 //PHY_SetMacReg(padapter, ODM_EDCA_BE_PARAM ,bMaskLWord , 0x431C);
1614 //PHY_SetMacReg(padapter, ODM_EDCA_BK_PARAM ,bMaskLWord , 0x431C);
1615 DBG_8192C("%s()!!!!! 0x460 = 0x%x\n" ,__func__,PHY_QueryBBReg(padapter, 0x460, bMaskDWord));
1616
1617 }
1618
SetPacketTx(PADAPTER padapter)1619 void SetPacketTx(PADAPTER padapter)
1620 {
1621 u8 *ptr, *pkt_start, *pkt_end,*fctrl;
1622 u32 pkt_size,offset,startPlace,i;
1623 struct rtw_ieee80211_hdr *hdr;
1624 u8 payload;
1625 s32 bmcast;
1626 struct pkt_attrib *pattrib;
1627 struct mp_priv *pmp_priv;
1628
1629 pmp_priv = &padapter->mppriv;
1630
1631 if (pmp_priv->tx.stop) return;
1632 pmp_priv->tx.sended = 0;
1633 pmp_priv->tx.stop = 0;
1634 pmp_priv->tx_pktcount = 0;
1635
1636 //3 1. update_attrib()
1637 pattrib = &pmp_priv->tx.attrib;
1638 _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
1639 _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
1640 _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
1641 bmcast = IS_MCAST(pattrib->ra);
1642 if (bmcast) {
1643 pattrib->mac_id = 1;
1644 pattrib->psta = rtw_get_bcmc_stainfo(padapter);
1645 } else {
1646 pattrib->mac_id = 0;
1647 pattrib->psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv));
1648 }
1649 pattrib->mbssid = 0;
1650
1651 pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->pktlen;
1652
1653 //3 2. allocate xmit buffer
1654 pkt_size = pattrib->last_txcmdsz;
1655
1656 if (pmp_priv->tx.pallocated_buf)
1657 rtw_mfree(pmp_priv->tx.pallocated_buf, pmp_priv->tx.buf_size);
1658 pmp_priv->tx.write_size = pkt_size;
1659 pmp_priv->tx.buf_size = pkt_size + XMITBUF_ALIGN_SZ;
1660 pmp_priv->tx.pallocated_buf = rtw_zmalloc(pmp_priv->tx.buf_size);
1661 if (pmp_priv->tx.pallocated_buf == NULL) {
1662 DBG_871X("%s: malloc(%d) fail!!\n", __func__, pmp_priv->tx.buf_size);
1663 return;
1664 }
1665 pmp_priv->tx.buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pmp_priv->tx.pallocated_buf), XMITBUF_ALIGN_SZ);
1666 ptr = pmp_priv->tx.buf;
1667
1668 _rtw_memset(pmp_priv->tx.desc, 0, TXDESC_SIZE);
1669 pkt_start = ptr;
1670 pkt_end = pkt_start + pkt_size;
1671
1672 //3 3. init TX descriptor
1673 #if defined(CONFIG_RTL8188E)
1674 if(IS_HARDWARE_TYPE_8188E(padapter))
1675 fill_tx_desc_8188e(padapter);
1676 #endif
1677
1678 #if defined(CONFIG_RTL8814A)
1679 if(IS_HARDWARE_TYPE_8814A(padapter))
1680 fill_tx_desc_8814a(padapter);
1681 #endif /* defined(CONFIG_RTL8814A) */
1682
1683 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
1684 if(IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter))
1685 fill_tx_desc_8812a(padapter);
1686 #endif
1687
1688 #if defined(CONFIG_RTL8192E)
1689 if(IS_HARDWARE_TYPE_8192E(padapter))
1690 fill_tx_desc_8192e(padapter);
1691 #endif
1692 #if defined(CONFIG_RTL8723B)
1693 if(IS_HARDWARE_TYPE_8723B(padapter))
1694 fill_tx_desc_8723b(padapter);
1695 #endif
1696 #if defined(CONFIG_RTL8703B)
1697 if (IS_HARDWARE_TYPE_8703B(padapter))
1698 fill_tx_desc_8703b(padapter);
1699 #endif
1700
1701 #if defined(CONFIG_RTL8188F)
1702 if (IS_HARDWARE_TYPE_8188F(padapter))
1703 fill_tx_desc_8188f(padapter);
1704 #endif
1705
1706 //3 4. make wlan header, make_wlanhdr()
1707 hdr = (struct rtw_ieee80211_hdr *)pkt_start;
1708 SetFrameSubType(&hdr->frame_ctl, pattrib->subtype);
1709 //
1710 SetFrDs(&hdr->frame_ctl);
1711 _rtw_memcpy(hdr->addr1, pattrib->dst, ETH_ALEN); // DA
1712 _rtw_memcpy(hdr->addr2, pattrib->src, ETH_ALEN); // SA
1713 _rtw_memcpy(hdr->addr3, get_bssid(&padapter->mlmepriv), ETH_ALEN); // RA, BSSID
1714
1715 //3 5. make payload
1716 ptr = pkt_start + pattrib->hdrlen;
1717
1718 switch (pmp_priv->tx.payload) {
1719 case 0:
1720 payload = 0x00;
1721 break;
1722 case 1:
1723 payload = 0x5a;
1724 break;
1725 case 2:
1726 payload = 0xa5;
1727 break;
1728 case 3:
1729 payload = 0xff;
1730 break;
1731 default:
1732 payload = 0x00;
1733 break;
1734 }
1735 pmp_priv->TXradomBuffer = rtw_zmalloc(4096);
1736 if(pmp_priv->TXradomBuffer == NULL)
1737 {
1738 DBG_871X("mp create random buffer fail!\n");
1739 goto exit;
1740 }
1741
1742
1743 for(i=0;i<4096;i++)
1744 pmp_priv->TXradomBuffer[i] = rtw_random32() %0xFF;
1745
1746 //startPlace = (u32)(rtw_random32() % 3450);
1747 _rtw_memcpy(ptr, pmp_priv->TXradomBuffer,pkt_end - ptr);
1748 //_rtw_memset(ptr, payload, pkt_end - ptr);
1749 rtw_mfree(pmp_priv->TXradomBuffer,4096);
1750
1751 //3 6. start thread
1752 #ifdef PLATFORM_LINUX
1753 pmp_priv->tx.PktTxThread = kthread_run(mp_xmit_packet_thread, pmp_priv, "RTW_MP_THREAD");
1754 if (IS_ERR(pmp_priv->tx.PktTxThread))
1755 DBG_871X("Create PktTx Thread Fail !!!!!\n");
1756 #endif
1757 #ifdef PLATFORM_FREEBSD
1758 {
1759 struct proc *p;
1760 struct thread *td;
1761 pmp_priv->tx.PktTxThread = kproc_kthread_add(mp_xmit_packet_thread, pmp_priv,
1762 &p, &td, RFHIGHPID, 0, "MPXmitThread", "MPXmitThread");
1763
1764 if (pmp_priv->tx.PktTxThread < 0)
1765 DBG_871X("Create PktTx Thread Fail !!!!!\n");
1766 }
1767 #endif
1768
1769 Rtw_MPSetMacTxEDCA(padapter);
1770 exit:
1771 return;
1772 }
1773
SetPacketRx(PADAPTER pAdapter,u8 bStartRx,u8 bAB)1774 void SetPacketRx(PADAPTER pAdapter, u8 bStartRx, u8 bAB)
1775 {
1776 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1777 struct mp_priv *pmppriv = &pAdapter->mppriv;
1778 u8 type;
1779 type = _HW_STATE_AP_;
1780 if(bStartRx)
1781 {
1782 #ifdef CONFIG_RTL8723B
1783 PHY_SetMacReg(pAdapter, 0xe70, BIT23|BIT22, 0x3);// Power on adc (in RX_WAIT_CCA state)
1784 write_bbreg(pAdapter, 0xa01, BIT0, bDisable);// improve Rx performance by jerry
1785 #endif
1786 if( pmppriv->bSetRxBssid == _TRUE ){
1787 //pHalData->ReceiveConfig = RCR_APM | RCR_AM | RCR_AB |RCR_CBSSID_DATA| RCR_CBSSID_BCN| RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_MIC | RCR_APP_PHYST_RXFF;
1788 pHalData->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AB |RCR_AMF | RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_MIC | RCR_APP_PHYST_RXFF ;
1789 pHalData->ReceiveConfig |= ACRC32;
1790
1791 DBG_8192C("%s , pmppriv->network_macaddr =%x %x %x %x %x %x\n",__func__,
1792 pmppriv->network_macaddr[0],pmppriv->network_macaddr[1],pmppriv->network_macaddr[2],pmppriv->network_macaddr[3],pmppriv->network_macaddr[4],pmppriv->network_macaddr[5]);
1793 //Set_MSR(pAdapter, WIFI_FW_AP_STATE);
1794 //rtw_hal_set_hwreg(pAdapter, HW_VAR_BSSID, pmppriv->network_macaddr);
1795 //rtw_hal_set_hwreg(pAdapter, HW_VAR_SET_OPMODE, (u8 *)(&type));
1796 }
1797 else
1798 {
1799 pHalData->ReceiveConfig = AAP | APM | AM | AB | APP_ICV | ADF | AMF | HTC_LOC_CTRL | APP_MIC | APP_PHYSTS;
1800 pHalData->ReceiveConfig |= ACRC32;
1801 rtw_write32(pAdapter, REG_RCR, pHalData->ReceiveConfig);
1802 // Accept all data frames
1803 rtw_write16(pAdapter, REG_RXFLTMAP2, 0xFFFF);
1804 // Accept CRC error and destination address
1805 }
1806 }
1807 else
1808 {
1809 #ifdef CONFIG_RTL8723B
1810 PHY_SetMacReg(pAdapter, 0xe70, BIT23|BIT22, 0x00);// Power off adc (in RX_WAIT_CCA state)
1811 write_bbreg(pAdapter, 0xa01, BIT0, bEnable);// improve Rx performance by jerry
1812 #endif
1813 rtw_write32(pAdapter, REG_RCR, 0);
1814 }
1815
1816 if (bAB)
1817 rtw_write32(pAdapter, REG_RCR, rtw_read32(pAdapter, REG_RCR)|RCR_AB);
1818 else
1819 rtw_write32(pAdapter, REG_RCR, rtw_read32(pAdapter, REG_RCR)&(~RCR_AB));
1820 }
1821
ResetPhyRxPktCount(PADAPTER pAdapter)1822 void ResetPhyRxPktCount(PADAPTER pAdapter)
1823 {
1824 u32 i, phyrx_set = 0;
1825
1826 for (i = 0; i <= 0xF; i++) {
1827 phyrx_set = 0;
1828 phyrx_set |= _RXERR_RPT_SEL(i); //select
1829 phyrx_set |= RXERR_RPT_RST; // set counter to zero
1830 rtw_write32(pAdapter, REG_RXERR_RPT, phyrx_set);
1831 }
1832 }
1833
GetPhyRxPktCounts(PADAPTER pAdapter,u32 selbit)1834 static u32 GetPhyRxPktCounts(PADAPTER pAdapter, u32 selbit)
1835 {
1836 //selection
1837 u32 phyrx_set = 0, count = 0;
1838
1839 phyrx_set = _RXERR_RPT_SEL(selbit & 0xF);
1840 rtw_write32(pAdapter, REG_RXERR_RPT, phyrx_set);
1841
1842 //Read packet count
1843 count = rtw_read32(pAdapter, REG_RXERR_RPT) & RXERR_COUNTER_MASK;
1844
1845 return count;
1846 }
1847
GetPhyRxPktReceived(PADAPTER pAdapter)1848 u32 GetPhyRxPktReceived(PADAPTER pAdapter)
1849 {
1850 u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0;
1851
1852 OFDM_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_OFDM_MPDU_OK);
1853 CCK_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_CCK_MPDU_OK);
1854 HT_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_HT_MPDU_OK);
1855
1856 return OFDM_cnt + CCK_cnt + HT_cnt;
1857 }
1858
GetPhyRxPktCRC32Error(PADAPTER pAdapter)1859 u32 GetPhyRxPktCRC32Error(PADAPTER pAdapter)
1860 {
1861 u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0;
1862
1863 OFDM_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_OFDM_MPDU_FAIL);
1864 CCK_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_CCK_MPDU_FAIL);
1865 HT_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_HT_MPDU_FAIL);
1866
1867 return OFDM_cnt + CCK_cnt + HT_cnt;
1868 }
1869
1870 //reg 0x808[9:0]: FFT data x
1871 //reg 0x808[22]: 0 --> 1 to get 1 FFT data y
1872 //reg 0x8B4[15:0]: FFT data y report
rtw_GetPSDData(PADAPTER pAdapter,u32 point)1873 static u32 rtw_GetPSDData(PADAPTER pAdapter, u32 point)
1874 {
1875 u32 psd_val=0;
1876
1877 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A)
1878 u16 psd_reg = 0x910;
1879 u16 psd_regL= 0xF44;
1880 #else
1881 u16 psd_reg = 0x808;
1882 u16 psd_regL= 0x8B4;
1883 #endif
1884
1885 psd_val = rtw_read32(pAdapter, psd_reg);
1886
1887 psd_val &= 0xFFBFFC00;
1888 psd_val |= point;
1889
1890 rtw_write32(pAdapter, psd_reg, psd_val);
1891 rtw_mdelay_os(1);
1892 psd_val |= 0x00400000;
1893
1894 rtw_write32(pAdapter, psd_reg, psd_val);
1895 rtw_mdelay_os(1);
1896
1897 psd_val = rtw_read32(pAdapter, psd_regL);
1898 psd_val &= 0x0000FFFF;
1899
1900 return psd_val;
1901 }
1902
1903 /*
1904 * pts start_point_min stop_point_max
1905 * 128 64 64 + 128 = 192
1906 * 256 128 128 + 256 = 384
1907 * 512 256 256 + 512 = 768
1908 * 1024 512 512 + 1024 = 1536
1909 *
1910 */
mp_query_psd(PADAPTER pAdapter,u8 * data)1911 u32 mp_query_psd(PADAPTER pAdapter, u8 *data)
1912 {
1913 u32 i, psd_pts=0, psd_start=0, psd_stop=0;
1914 u32 psd_data=0;
1915
1916
1917 #ifdef PLATFORM_LINUX
1918 if (!netif_running(pAdapter->pnetdev)) {
1919 RT_TRACE(_module_mp_, _drv_warning_, ("mp_query_psd: Fail! interface not opened!\n"));
1920 return 0;
1921 }
1922 #endif
1923
1924 if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
1925 RT_TRACE(_module_mp_, _drv_warning_, ("mp_query_psd: Fail! not in MP mode!\n"));
1926 return 0;
1927 }
1928
1929 if (strlen(data) == 0) { //default value
1930 psd_pts = 128;
1931 psd_start = 64;
1932 psd_stop = 128;
1933 } else {
1934 sscanf(data, "pts=%d,start=%d,stop=%d", &psd_pts, &psd_start, &psd_stop);
1935 }
1936
1937 data[0]='\0';
1938
1939 i = psd_start;
1940 while (i < psd_stop)
1941 {
1942 if (i >= psd_pts) {
1943 psd_data = rtw_GetPSDData(pAdapter, i-psd_pts);
1944 } else {
1945 psd_data = rtw_GetPSDData(pAdapter, i);
1946 }
1947 sprintf(data, "%s%x ", data, psd_data);
1948 i++;
1949 }
1950
1951 #ifdef CONFIG_LONG_DELAY_ISSUE
1952 rtw_msleep_os(100);
1953 #else
1954 rtw_mdelay_os(100);
1955 #endif
1956
1957 return strlen(data)+1;
1958 }
1959
1960
1961 #if 0
1962 void _rtw_mp_xmit_priv (struct xmit_priv *pxmitpriv)
1963 {
1964 int i,res;
1965 _adapter *padapter = pxmitpriv->adapter;
1966 struct xmit_frame *pxmitframe = (struct xmit_frame*) pxmitpriv->pxmit_frame_buf;
1967 struct xmit_buf *pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf;
1968
1969 u32 max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ;
1970 u32 num_xmit_extbuf = NR_XMIT_EXTBUFF;
1971 if(padapter->registrypriv.mp_mode ==0)
1972 {
1973 max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ;
1974 num_xmit_extbuf = NR_XMIT_EXTBUFF;
1975 }
1976 else
1977 {
1978 max_xmit_extbuf_size = 6000;
1979 num_xmit_extbuf = 8;
1980 }
1981
1982 pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf;
1983 for(i=0; i<num_xmit_extbuf; i++)
1984 {
1985 rtw_os_xmit_resource_free(padapter, pxmitbuf,(max_xmit_extbuf_size + XMITBUF_ALIGN_SZ), _FALSE);
1986
1987 pxmitbuf++;
1988 }
1989
1990 if(pxmitpriv->pallocated_xmit_extbuf) {
1991 rtw_vmfree(pxmitpriv->pallocated_xmit_extbuf, num_xmit_extbuf * sizeof(struct xmit_buf) + 4);
1992 }
1993
1994 if(padapter->registrypriv.mp_mode ==0)
1995 {
1996 max_xmit_extbuf_size = 6000;
1997 num_xmit_extbuf = 8;
1998 }
1999 else
2000 {
2001 max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ;
2002 num_xmit_extbuf = NR_XMIT_EXTBUFF;
2003 }
2004
2005 // Init xmit extension buff
2006 _rtw_init_queue(&pxmitpriv->free_xmit_extbuf_queue);
2007
2008 pxmitpriv->pallocated_xmit_extbuf = rtw_zvmalloc(num_xmit_extbuf * sizeof(struct xmit_buf) + 4);
2009
2010 if (pxmitpriv->pallocated_xmit_extbuf == NULL){
2011 RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("alloc xmit_extbuf fail!\n"));
2012 res= _FAIL;
2013 goto exit;
2014 }
2015
2016 pxmitpriv->pxmit_extbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmit_extbuf), 4);
2017
2018 pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf;
2019
2020 for (i = 0; i < num_xmit_extbuf; i++)
2021 {
2022 _rtw_init_listhead(&pxmitbuf->list);
2023
2024 pxmitbuf->priv_data = NULL;
2025 pxmitbuf->padapter = padapter;
2026 pxmitbuf->buf_tag = XMITBUF_MGNT;
2027
2028 if((res=rtw_os_xmit_resource_alloc(padapter, pxmitbuf,max_xmit_extbuf_size + XMITBUF_ALIGN_SZ, _TRUE)) == _FAIL) {
2029 res= _FAIL;
2030 goto exit;
2031 }
2032
2033 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
2034 pxmitbuf->phead = pxmitbuf->pbuf;
2035 pxmitbuf->pend = pxmitbuf->pbuf + max_xmit_extbuf_size;
2036 pxmitbuf->len = 0;
2037 pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
2038 #endif
2039
2040 rtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmit_extbuf_queue.queue));
2041 #ifdef DBG_XMIT_BUF_EXT
2042 pxmitbuf->no=i;
2043 #endif
2044 pxmitbuf++;
2045
2046 }
2047
2048 pxmitpriv->free_xmit_extbuf_cnt = num_xmit_extbuf;
2049
2050 exit:
2051 ;
2052 }
2053 #endif
2054
2055
getPowerDiffByRate8188E(IN PADAPTER pAdapter,IN u1Byte CurrChannel,IN ULONG RfPath)2056 ULONG getPowerDiffByRate8188E(
2057 IN PADAPTER pAdapter,
2058 IN u1Byte CurrChannel,
2059 IN ULONG RfPath
2060 )
2061 {
2062 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
2063 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2064 ULONG PwrGroup=0;
2065 ULONG TxPower=0, Limit=0;
2066 ULONG Pathmapping = (RfPath == ODM_RF_PATH_A?0:8);
2067
2068 switch(pHalData->EEPROMRegulatory)
2069 {
2070 case 0: // driver-defined maximum power offset for longer communication range
2071 // refer to power by rate table
2072 PwrGroup = 0;
2073 Limit = 0xff;
2074 break;
2075 case 1: // Power-limit table-defined maximum power offset range
2076 // choosed by min(power by rate, power limit).
2077 {
2078 if(pHalData->pwrGroupCnt == 1)
2079 PwrGroup = 0;
2080 if(pHalData->pwrGroupCnt >= 3)
2081 {
2082 if(CurrChannel <= 3)
2083 PwrGroup = 0;
2084 else if(CurrChannel >= 4 && CurrChannel <= 9)
2085 PwrGroup = 1;
2086 else if(CurrChannel > 9)
2087 PwrGroup = 2;
2088
2089 if(pHalData->CurrentChannelBW == CHANNEL_WIDTH_20)
2090 PwrGroup++;
2091 else
2092 PwrGroup+=4;
2093 }
2094 Limit = 0xff;
2095 }
2096 break;
2097 case 2: // not support power offset by rate.
2098 // don't increase any power diff
2099 PwrGroup = 0;
2100 Limit = 0;
2101 break;
2102 default:
2103 PwrGroup = 0;
2104 Limit = 0xff;
2105 break;
2106 }
2107
2108
2109 {
2110 switch(pMptCtx->MptRateIndex)
2111 {
2112 case MPT_RATE_1M:
2113 case MPT_RATE_2M:
2114 case MPT_RATE_55M:
2115 case MPT_RATE_11M:
2116 //CCK rates, don't add any tx power index.
2117 //RT_DISP(FPHY, PHY_TXPWR,("CCK rates!\n"));
2118 break;
2119 case MPT_RATE_6M: //0xe00 [31:0] = 18M,12M,09M,06M
2120 TxPower += ((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0+Pathmapping])&0xff);
2121 //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x, OFDM 6M, TxPower = %d\n",
2122 // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0], TxPower));
2123 break;
2124 case MPT_RATE_9M:
2125 TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0+Pathmapping])&0xff00)>>8);
2126 //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x, OFDM 9M, TxPower = %d\n",
2127 // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0], TxPower));
2128 break;
2129 case MPT_RATE_12M:
2130 TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0+Pathmapping])&0xff0000)>>16);
2131 //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x, OFDM 12M, TxPower = %d\n",
2132 // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0], TxPower));
2133 break;
2134 case MPT_RATE_18M:
2135 TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0+Pathmapping])&0xff000000)>>24);
2136 //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x, OFDM 24M, TxPower = %d\n",
2137 // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0], TxPower));
2138 break;
2139 case MPT_RATE_24M: //0xe04[31:0] = 54M,48M,36M,24M
2140 TxPower += ((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1+Pathmapping])&0xff);
2141 //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x, OFDM 24M, TxPower = %d\n",
2142 // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1], TxPower));
2143 break;
2144 case MPT_RATE_36M:
2145 TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1+Pathmapping])&0xff00)>>8);
2146 //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x, OFDM 36M, TxPower = %d\n",
2147 // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1], TxPower));
2148 break;
2149 case MPT_RATE_48M:
2150 TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1+Pathmapping])&0xff0000)>>16);
2151 //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x, OFDM 48M, TxPower = %d\n",
2152 // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1], TxPower));
2153 break;
2154 case MPT_RATE_54M:
2155 TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1+Pathmapping])&0xff000000)>>24);
2156 //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x, OFDM 54M, TxPower = %d\n",
2157 // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1], TxPower));
2158 break;
2159 case MPT_RATE_MCS0: //0xe10[31:0]= MCS=03,02,01,00
2160 TxPower += ((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2+Pathmapping])&0xff);
2161 //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x, MCS0, TxPower = %d\n",
2162 // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2], TxPower));
2163 break;
2164 case MPT_RATE_MCS1:
2165 TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2+Pathmapping])&0xff00)>>8);
2166 //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x, MCS1, TxPower = %d\n",
2167 // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2], TxPower));
2168 break;
2169 case MPT_RATE_MCS2:
2170 TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2+Pathmapping])&0xff0000)>>16);
2171 //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x, MCS2, TxPower = %d\n",
2172 // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2], TxPower));
2173 break;
2174 case MPT_RATE_MCS3:
2175 TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2+Pathmapping])&0xff000000)>>24);
2176 //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x, MCS3, TxPower = %d\n",
2177 // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2], TxPower));
2178 break;
2179 case MPT_RATE_MCS4: //0xe14[31:0]= MCS=07,06,05,04
2180 TxPower += ((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3+Pathmapping])&0xff);
2181 //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x, MCS4, TxPower = %d\n",
2182 // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3], TxPower));
2183 break;
2184 case MPT_RATE_MCS5:
2185 TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3+Pathmapping])&0xff00)>>8);
2186 //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x, MCS5, TxPower = %d\n",
2187 // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3], TxPower));
2188 break;
2189 case MPT_RATE_MCS6:
2190 TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3+Pathmapping])&0xff0000)>>16);
2191 //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x, MCS6, TxPower = %d\n",
2192 // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3], TxPower));
2193 break;
2194 case MPT_RATE_MCS7:
2195 TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3+Pathmapping])&0xff000000)>>24);
2196 //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x, MCS7, TxPower = %d\n",
2197 // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3], TxPower));
2198 break;
2199
2200 case MPT_RATE_MCS8: //0xe18[31:0]= MCS=11,10,09,08
2201 TxPower += ((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4+Pathmapping])&0xff);
2202 //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x, MCS8, TxPower = %d\n",
2203 // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4], TxPower));
2204 break;
2205 case MPT_RATE_MCS9:
2206 TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4+Pathmapping])&0xff00)>>8);
2207 //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x, MCS9, TxPower = %d\n",
2208 // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4], TxPower));
2209 break;
2210 case MPT_RATE_MCS10:
2211 TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4+Pathmapping])&0xff0000)>>16);
2212 //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x, MCS10, TxPower = %d\n",
2213 // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4], TxPower));
2214 break;
2215 case MPT_RATE_MCS11:
2216 TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4+Pathmapping])&0xff000000)>>24);
2217 //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x, MCS11, TxPower = %d\n",
2218 // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4], TxPower));
2219 break;
2220 case MPT_RATE_MCS12: //0xe1c[31:0]= MCS=15,14,13,12
2221 TxPower += ((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5+Pathmapping])&0xff);
2222 //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x, MCS12, TxPower = %d\n",
2223 // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5], TxPower));
2224 break;
2225 case MPT_RATE_MCS13:
2226 TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5+Pathmapping])&0xff00)>>8);
2227 //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x, MCS13, TxPower = %d\n",
2228 // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5], TxPower));
2229 break;
2230 case MPT_RATE_MCS14:
2231 TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5+Pathmapping])&0xff0000)>>16);
2232 //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x, MCS14, TxPower = %d\n",
2233 // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5], TxPower));
2234 break;
2235 case MPT_RATE_MCS15:
2236 TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5+Pathmapping])&0xff000000)>>24);
2237 //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x, MCS15, TxPower = %d\n",
2238 // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5], TxPower));
2239 break;
2240 default:
2241 break;
2242 }
2243 }
2244
2245 if(TxPower > Limit)
2246 TxPower = Limit;
2247
2248 return TxPower;
2249 }
2250
2251
2252
2253 static ULONG
mpt_ProQueryCalTxPower_8188E(IN PADAPTER pAdapter,IN u1Byte RfPath)2254 mpt_ProQueryCalTxPower_8188E(
2255 IN PADAPTER pAdapter,
2256 IN u1Byte RfPath
2257 )
2258 {
2259 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2260 u1Byte TxCount=TX_1S, i = 0; //default set to 1S
2261 //PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);
2262 ULONG TxPower = 1, PwrGroup=0, PowerDiffByRate=0;
2263 ULONG TxPowerCCK = 1, TxPowerOFDM = 1, TxPowerBW20 = 1, TxPowerBW40 = 1 ;
2264 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
2265 u1Byte CurrChannel = pHalData->CurrentChannel;
2266 u1Byte index = (CurrChannel -1);
2267 u1Byte rf_path=(RfPath), rfPath;
2268 u1Byte limit = 0, rate = 0;
2269
2270 if(HAL_IsLegalChannel(pAdapter, CurrChannel) == FALSE)
2271 {
2272 CurrChannel = 1;
2273 }
2274
2275 if(pMptCtx->MptRateIndex <= MPT_RATE_11M )
2276 {
2277 TxPower = pHalData->Index24G_CCK_Base[rf_path][index];
2278 }
2279 else if(pMptCtx->MptRateIndex >= MPT_RATE_6M &&
2280 pMptCtx->MptRateIndex <= MPT_RATE_54M )
2281 {
2282 TxPower = pHalData->Index24G_BW40_Base[rf_path][index];
2283 }
2284 else if(pMptCtx->MptRateIndex >= MPT_RATE_MCS0 &&
2285 pMptCtx->MptRateIndex <= MPT_RATE_MCS7 )
2286 {
2287 TxPower = pHalData->Index24G_BW40_Base[rf_path][index];
2288 }
2289
2290 //RT_DISP(FPHY, PHY_TXPWR, ("HT40 rate(%d) Tx power(RF-%c) = 0x%x\n", pMptCtx->MptRateIndex, ((rf_path==0)?'A':'B'), TxPower));
2291
2292
2293 if(pMptCtx->MptRateIndex >= MPT_RATE_6M &&
2294 pMptCtx->MptRateIndex <= MPT_RATE_54M )
2295 {
2296 TxPower += pHalData->OFDM_24G_Diff[rf_path][TxCount];
2297 ///RT_DISP(FPHY, PHY_TXPWR, ("+OFDM_PowerDiff(RF-%c) = 0x%x\n", ((rf_path==0)?'A':'B'),
2298 // pHalData->OFDM_24G_Diff[rf_path][TxCount]));
2299 }
2300
2301 if(pMptCtx->MptRateIndex >= MPT_RATE_MCS0)
2302 {
2303 if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_20)
2304 {
2305 TxPower += pHalData->BW20_24G_Diff[rf_path][TxCount];
2306 // RT_DISP(FPHY, PHY_TXPWR, ("+HT20_PowerDiff(RF-%c) = 0x%x\n", ((rf_path==0)?'A':'B'),
2307 // pHalData->BW20_24G_Diff[rf_path][TxCount]));
2308 }
2309 }
2310
2311
2312 #ifdef ENABLE_POWER_BY_RATE
2313 PowerDiffByRate = getPowerDiffByRate8188E(pAdapter, CurrChannel, RfPath);
2314 #else
2315 PowerDiffByRate = 0;
2316 #endif
2317
2318 // 2012/11/02 Awk: add power limit mechansim
2319 if( pMptCtx->MptRateIndex <= MPT_RATE_11M )
2320 {
2321 rate = MGN_1M;
2322 }
2323 else if(pMptCtx->MptRateIndex >= MPT_RATE_6M &&
2324 pMptCtx->MptRateIndex <= MPT_RATE_54M )
2325 {
2326 rate = MGN_54M;
2327 }
2328 else if(pMptCtx->MptRateIndex >= MPT_RATE_MCS0 &&
2329 pMptCtx->MptRateIndex <= MPT_RATE_MCS7 )
2330 {
2331 rate = MGN_MCS7;
2332 }
2333
2334 limit = (u8)PHY_GetTxPowerLimit(pAdapter, pMptCtx->RegTxPwrLimit,
2335 pHalData->CurrentBandType,
2336 pHalData->CurrentChannelBW,RfPath,
2337 rate, CurrChannel);
2338
2339 //RT_DISP(FPHY, PHY_TXPWR, ("+PowerDiffByRate(RF-%c) = 0x%x\n", ((rf_path==0)?'A':'B'),
2340 // PowerDiffByRate));
2341 TxPower += PowerDiffByRate;
2342 //RT_DISP(FPHY, PHY_TXPWR, ("PowerDiffByRate limit value(RF-%c) = %d\n", ((rf_path==0)?'A':'B'),
2343 // limit));
2344
2345 TxPower += limit > (s8) PowerDiffByRate ? PowerDiffByRate : limit;
2346
2347 return TxPower;
2348 }
2349
2350
2351 u8
MptToMgntRate(IN ULONG MptRateIdx)2352 MptToMgntRate(
2353 IN ULONG MptRateIdx
2354 )
2355 {
2356 // Mapped to MGN_XXX defined in MgntGen.h
2357 switch (MptRateIdx)
2358 {
2359 /* CCK rate. */
2360 case MPT_RATE_1M: return MGN_1M;
2361 case MPT_RATE_2M: return MGN_2M;
2362 case MPT_RATE_55M: return MGN_5_5M;
2363 case MPT_RATE_11M: return MGN_11M;
2364
2365 /* OFDM rate. */
2366 case MPT_RATE_6M: return MGN_6M;
2367 case MPT_RATE_9M: return MGN_9M;
2368 case MPT_RATE_12M: return MGN_12M;
2369 case MPT_RATE_18M: return MGN_18M;
2370 case MPT_RATE_24M: return MGN_24M;
2371 case MPT_RATE_36M: return MGN_36M;
2372 case MPT_RATE_48M: return MGN_48M;
2373 case MPT_RATE_54M: return MGN_54M;
2374
2375 /* HT rate. */
2376 case MPT_RATE_MCS0: return MGN_MCS0;
2377 case MPT_RATE_MCS1: return MGN_MCS1;
2378 case MPT_RATE_MCS2: return MGN_MCS2;
2379 case MPT_RATE_MCS3: return MGN_MCS3;
2380 case MPT_RATE_MCS4: return MGN_MCS4;
2381 case MPT_RATE_MCS5: return MGN_MCS5;
2382 case MPT_RATE_MCS6: return MGN_MCS6;
2383 case MPT_RATE_MCS7: return MGN_MCS7;
2384 case MPT_RATE_MCS8: return MGN_MCS8;
2385 case MPT_RATE_MCS9: return MGN_MCS9;
2386 case MPT_RATE_MCS10: return MGN_MCS10;
2387 case MPT_RATE_MCS11: return MGN_MCS11;
2388 case MPT_RATE_MCS12: return MGN_MCS12;
2389 case MPT_RATE_MCS13: return MGN_MCS13;
2390 case MPT_RATE_MCS14: return MGN_MCS14;
2391 case MPT_RATE_MCS15: return MGN_MCS15;
2392 case MPT_RATE_MCS16: return MGN_MCS16;
2393 case MPT_RATE_MCS17: return MGN_MCS17;
2394 case MPT_RATE_MCS18: return MGN_MCS18;
2395 case MPT_RATE_MCS19: return MGN_MCS19;
2396 case MPT_RATE_MCS20: return MGN_MCS20;
2397 case MPT_RATE_MCS21: return MGN_MCS21;
2398 case MPT_RATE_MCS22: return MGN_MCS22;
2399 case MPT_RATE_MCS23: return MGN_MCS23;
2400 case MPT_RATE_MCS24: return MGN_MCS24;
2401 case MPT_RATE_MCS25: return MGN_MCS25;
2402 case MPT_RATE_MCS26: return MGN_MCS26;
2403 case MPT_RATE_MCS27: return MGN_MCS27;
2404 case MPT_RATE_MCS28: return MGN_MCS28;
2405 case MPT_RATE_MCS29: return MGN_MCS29;
2406 case MPT_RATE_MCS30: return MGN_MCS30;
2407 case MPT_RATE_MCS31: return MGN_MCS31;
2408
2409 /* VHT rate. */
2410 case MPT_RATE_VHT1SS_MCS0: return MGN_VHT1SS_MCS0;
2411 case MPT_RATE_VHT1SS_MCS1: return MGN_VHT1SS_MCS1;
2412 case MPT_RATE_VHT1SS_MCS2: return MGN_VHT1SS_MCS2;
2413 case MPT_RATE_VHT1SS_MCS3: return MGN_VHT1SS_MCS3;
2414 case MPT_RATE_VHT1SS_MCS4: return MGN_VHT1SS_MCS4;
2415 case MPT_RATE_VHT1SS_MCS5: return MGN_VHT1SS_MCS5;
2416 case MPT_RATE_VHT1SS_MCS6: return MGN_VHT1SS_MCS6;
2417 case MPT_RATE_VHT1SS_MCS7: return MGN_VHT1SS_MCS7;
2418 case MPT_RATE_VHT1SS_MCS8: return MGN_VHT1SS_MCS8;
2419 case MPT_RATE_VHT1SS_MCS9: return MGN_VHT1SS_MCS9;
2420 case MPT_RATE_VHT2SS_MCS0: return MGN_VHT2SS_MCS0;
2421 case MPT_RATE_VHT2SS_MCS1: return MGN_VHT2SS_MCS1;
2422 case MPT_RATE_VHT2SS_MCS2: return MGN_VHT2SS_MCS2;
2423 case MPT_RATE_VHT2SS_MCS3: return MGN_VHT2SS_MCS3;
2424 case MPT_RATE_VHT2SS_MCS4: return MGN_VHT2SS_MCS4;
2425 case MPT_RATE_VHT2SS_MCS5: return MGN_VHT2SS_MCS5;
2426 case MPT_RATE_VHT2SS_MCS6: return MGN_VHT2SS_MCS6;
2427 case MPT_RATE_VHT2SS_MCS7: return MGN_VHT2SS_MCS7;
2428 case MPT_RATE_VHT2SS_MCS8: return MGN_VHT2SS_MCS8;
2429 case MPT_RATE_VHT2SS_MCS9: return MGN_VHT2SS_MCS9;
2430 case MPT_RATE_VHT3SS_MCS0: return MGN_VHT3SS_MCS0;
2431 case MPT_RATE_VHT3SS_MCS1: return MGN_VHT3SS_MCS1;
2432 case MPT_RATE_VHT3SS_MCS2: return MGN_VHT3SS_MCS2;
2433 case MPT_RATE_VHT3SS_MCS3: return MGN_VHT3SS_MCS3;
2434 case MPT_RATE_VHT3SS_MCS4: return MGN_VHT3SS_MCS4;
2435 case MPT_RATE_VHT3SS_MCS5: return MGN_VHT3SS_MCS5;
2436 case MPT_RATE_VHT3SS_MCS6: return MGN_VHT3SS_MCS6;
2437 case MPT_RATE_VHT3SS_MCS7: return MGN_VHT3SS_MCS7;
2438 case MPT_RATE_VHT3SS_MCS8: return MGN_VHT3SS_MCS8;
2439 case MPT_RATE_VHT3SS_MCS9: return MGN_VHT3SS_MCS9;
2440 case MPT_RATE_VHT4SS_MCS0: return MGN_VHT4SS_MCS0;
2441 case MPT_RATE_VHT4SS_MCS1: return MGN_VHT4SS_MCS1;
2442 case MPT_RATE_VHT4SS_MCS2: return MGN_VHT4SS_MCS2;
2443 case MPT_RATE_VHT4SS_MCS3: return MGN_VHT4SS_MCS3;
2444 case MPT_RATE_VHT4SS_MCS4: return MGN_VHT4SS_MCS4;
2445 case MPT_RATE_VHT4SS_MCS5: return MGN_VHT4SS_MCS5;
2446 case MPT_RATE_VHT4SS_MCS6: return MGN_VHT4SS_MCS6;
2447 case MPT_RATE_VHT4SS_MCS7: return MGN_VHT4SS_MCS7;
2448 case MPT_RATE_VHT4SS_MCS8: return MGN_VHT4SS_MCS8;
2449 case MPT_RATE_VHT4SS_MCS9: return MGN_VHT4SS_MCS9;
2450
2451 case MPT_RATE_LAST: // fully automatiMGN_VHT2SS_MCS1;
2452 default:
2453 DBG_871X("<===MptToMgntRate(), Invalid Rate: %d!!\n", MptRateIdx);
2454 return 0x0;
2455 }
2456 }
2457
rtw_mpRateParseFunc(PADAPTER pAdapter,u8 * targetStr)2458 u8 rtw_mpRateParseFunc(PADAPTER pAdapter, u8 *targetStr)
2459 {
2460 u16 i=0;
2461 u8* rateindex_Array[] = { "1M","2M","5.5M","11M","6M","9M","12M","18M","24M","36M","48M","54M",
2462 "HTMCS0","HTMCS1","HTMCS2","HTMCS3","HTMCS4","HTMCS5","HTMCS6","HTMCS7",
2463 "HTMCS8","HTMCS9","HTMCS10","HTMCS11","HTMCS12","HTMCS13","HTMCS14","HTMCS15",
2464 "HTMCS16","HTMCS17","HTMCS18","HTMCS19","HTMCS20","HTMCS21","HTMCS22","HTMCS23",
2465 "HTMCS24","HTMCS25","HTMCS26","HTMCS27","HTMCS28","HTMCS29","HTMCS30","HTMCS31",
2466 "VHT1MCS0","VHT1MCS1","VHT1MCS2","VHT1MCS3","VHT1MCS4","VHT1MCS5","VHT1MCS6","VHT1MCS7","VHT1MCS8","VHT1MCS9",
2467 "VHT2MCS0","VHT2MCS1","VHT2MCS2","VHT2MCS3","VHT2MCS4","VHT2MCS5","VHT2MCS6","VHT2MCS7","VHT2MCS8","VHT2MCS9",
2468 "VHT3MCS0","VHT3MCS1","VHT3MCS2","VHT3MCS3","VHT3MCS4","VHT3MCS5","VHT3MCS6","VHT3MCS7","VHT3MCS8","VHT3MCS9",
2469 "VHT4MCS0","VHT4MCS1","VHT4MCS2","VHT4MCS3","VHT4MCS4","VHT4MCS5","VHT4MCS6","VHT4MCS7","VHT4MCS8","VHT4MCS9"};
2470
2471 for(i=0;i<=83;i++){
2472 if(strcmp(targetStr, rateindex_Array[i]) == 0){
2473 DBG_871X("%s , index = %d \n",__func__ ,i);
2474 return i;
2475 }
2476 }
2477
2478 printk("%s ,please input a Data RATE String as:",__func__);
2479 for(i=0;i<=83;i++){
2480 printk("%s ",rateindex_Array[i]);
2481 if(i%10==0)
2482 printk("\n");
2483 }
2484 return _FAIL;
2485 }
2486
mpt_ProQueryCalTxPower(PADAPTER pAdapter,u8 RfPath)2487 ULONG mpt_ProQueryCalTxPower(
2488 PADAPTER pAdapter,
2489 u8 RfPath
2490 )
2491 {
2492
2493 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2494 PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
2495
2496 ULONG TxPower = 1, PwrGroup=0, PowerDiffByRate=0;
2497 u1Byte limit = 0, rate = 0;
2498
2499 #if defined(CONFIG_RTL8188E)
2500 if (IS_HARDWARE_TYPE_8188E(pAdapter))
2501 {
2502 //return mpt_ProQueryCalTxPower_8188E(pAdapter, RfPath);
2503 rate = MptToMgntRate(pAdapter->mppriv.rateidx);
2504 TxPower = PHY_GetTxPowerIndex_8188E(pAdapter, RfPath, rate,
2505 pHalData->CurrentChannelBW, pHalData->CurrentChannel);
2506
2507 }
2508 #endif
2509
2510 #if defined(CONFIG_RTL8723B)
2511 if( IS_HARDWARE_TYPE_8723B(pAdapter) )
2512 {
2513 rate = MptToMgntRate(pAdapter->mppriv.rateidx);
2514 TxPower = PHY_GetTxPowerIndex_8723B(pAdapter, RfPath, rate,
2515 pHalData->CurrentChannelBW, pHalData->CurrentChannel);
2516 }
2517 #endif
2518
2519 #if defined(CONFIG_RTL8192E)
2520 if( IS_HARDWARE_TYPE_8192E(pAdapter) )
2521 {
2522 rate = MptToMgntRate(pAdapter->mppriv.rateidx);
2523 TxPower = PHY_GetTxPowerIndex_8192E(pAdapter, RfPath, rate,
2524 pHalData->CurrentChannelBW, pHalData->CurrentChannel);
2525 }
2526 #endif
2527 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
2528 if( IS_HARDWARE_TYPE_JAGUAR(pAdapter) )
2529 {
2530 rate = MptToMgntRate(pAdapter->mppriv.rateidx);
2531 TxPower = PHY_GetTxPowerIndex_8812A(pAdapter, RfPath, rate,
2532 pHalData->CurrentChannelBW, pHalData->CurrentChannel);
2533 }
2534 #endif
2535 #if defined(CONFIG_RTL8814A)
2536 if ( IS_HARDWARE_TYPE_8814A(pAdapter) )
2537 {
2538 rate = MptToMgntRate(pAdapter->mppriv.rateidx);
2539 TxPower = PHY_GetTxPowerIndex_8814A(pAdapter, RfPath, rate,
2540 pHalData->CurrentChannelBW, pHalData->CurrentChannel);
2541 }
2542 #endif
2543 #if defined(CONFIG_RTL8703B)
2544 if (IS_HARDWARE_TYPE_8703B(pAdapter)) {
2545 rate = MptToMgntRate(pAdapter->mppriv.rateidx);
2546 TxPower = PHY_GetTxPowerIndex_8703B(pAdapter, RfPath, rate,
2547 pHalData->CurrentChannelBW, pHalData->CurrentChannel);
2548 }
2549 #endif
2550
2551 #if defined(CONFIG_RTL8188F)
2552 if (IS_HARDWARE_TYPE_8188F(pAdapter)) {
2553 rate = MptToMgntRate(pAdapter->mppriv.rateidx);
2554 TxPower = PHY_GetTxPowerIndex_8188F(pAdapter, RfPath, rate,
2555 pHalData->CurrentChannelBW, pHalData->CurrentChannel);
2556 }
2557 #endif
2558
2559 DBG_8192C("txPower=%d ,CurrentChannelBW=%d ,CurrentChannel=%d ,rate =%d\n",
2560 TxPower, pHalData->CurrentChannelBW, pHalData->CurrentChannel, rate);
2561
2562 pAdapter->mppriv.txpoweridx = (u8)TxPower;
2563 pMptCtx->TxPwrLevel[ODM_RF_PATH_A] = (u8)TxPower;
2564 pMptCtx->TxPwrLevel[ODM_RF_PATH_B] = (u8)TxPower;
2565 pMptCtx->TxPwrLevel[ODM_RF_PATH_C] = (u8)TxPower;
2566 pMptCtx->TxPwrLevel[ODM_RF_PATH_D] = (u8)TxPower;
2567 hal_mpt_SetTxPower(pAdapter);
2568
2569 return TxPower;
2570 }
2571
2572
Hal_ProSetCrystalCap(PADAPTER pAdapter,u32 CrystalCap)2573 void Hal_ProSetCrystalCap (PADAPTER pAdapter , u32 CrystalCap)
2574 {
2575 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2576
2577 CrystalCap = CrystalCap & 0x3F;
2578
2579 if (IS_HARDWARE_TYPE_8188E(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter)) {
2580 /* write 0x24[16:11] = 0x24[22:17] = CrystalCap*/
2581 PHY_SetBBReg(pAdapter, REG_AFE_XTAL_CTRL, 0x7FF800, (CrystalCap | (CrystalCap << 6)));
2582 } else if (IS_HARDWARE_TYPE_8812(pAdapter)) {
2583 /* write 0x2C[30:25] = 0x2C[24:19] = CrystalCap*/
2584 PHY_SetBBReg(pAdapter, REG_MAC_PHY_CTRL, 0x7FF80000, (CrystalCap | (CrystalCap << 6)));
2585 } else if (IS_HARDWARE_TYPE_8821(pAdapter) || IS_HARDWARE_TYPE_8192E(pAdapter) ||
2586 IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8703B(pAdapter)) {
2587 /* write 0x2C[23:18] = 0x2C[17:12] = CrystalCap*/
2588 PHY_SetBBReg(pAdapter, REG_MAC_PHY_CTRL, 0xFFF000, (CrystalCap | (CrystalCap << 6)));
2589 } else if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
2590 /* write 0x2C[26:21] = 0x2C[20:15] = CrystalCap*/
2591 PHY_SetBBReg(pAdapter, REG_MAC_PHY_CTRL, 0x07FF8000, (CrystalCap | (CrystalCap << 6)));
2592 } else
2593 DBG_871X("%s ,unknown HARDWARE_TYPE\n", __func__);
2594
2595 }
2596 #endif
2597
2598