1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 *
19 ******************************************************************************/
20
21 #define _USB_HALINIT_C_
22
23 #include <rtl8723b_hal.h>
24 #ifdef CONFIG_WOWLAN
25 #include "hal_com_h2c.h"
26 #endif
27
28
29
_dbg_dump_macreg(_adapter * padapter)30 static void _dbg_dump_macreg(_adapter *padapter)
31 {
32 u32 offset = 0;
33 u32 val32 = 0;
34 u32 index =0 ;
35 for(index=0;index<64;index++)
36 {
37 offset = index*4;
38 val32 = rtw_read32(padapter,offset);
39 DBG_8192C("offset : 0x%02x ,val:0x%08x\n",offset,val32);
40 }
41 }
42
43 static VOID
_ConfigChipOutEP_8723(IN PADAPTER pAdapter,IN u8 NumOutPipe)44 _ConfigChipOutEP_8723(
45 IN PADAPTER pAdapter,
46 IN u8 NumOutPipe
47 )
48 {
49 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
50
51
52 pHalData->OutEpQueueSel = 0;
53 pHalData->OutEpNumber = 0;
54
55 switch(NumOutPipe){
56 case 4:
57 pHalData->OutEpQueueSel=TX_SELE_HQ| TX_SELE_LQ|TX_SELE_NQ;
58 pHalData->OutEpNumber=4;
59 break;
60 case 3:
61 pHalData->OutEpQueueSel=TX_SELE_HQ| TX_SELE_LQ|TX_SELE_NQ;
62 pHalData->OutEpNumber=3;
63 break;
64 case 2:
65 pHalData->OutEpQueueSel=TX_SELE_HQ| TX_SELE_NQ;
66 pHalData->OutEpNumber=2;
67 break;
68 case 1:
69 pHalData->OutEpQueueSel=TX_SELE_HQ;
70 pHalData->OutEpNumber=1;
71 break;
72 default:
73 break;
74
75 }
76 DBG_871X("%s OutEpQueueSel(0x%02x), OutEpNumber(%d) \n",__FUNCTION__,pHalData->OutEpQueueSel,pHalData->OutEpNumber );
77
78 }
79
HalUsbSetQueuePipeMapping8723BUsb(IN PADAPTER pAdapter,IN u8 NumInPipe,IN u8 NumOutPipe)80 static BOOLEAN HalUsbSetQueuePipeMapping8723BUsb(
81 IN PADAPTER pAdapter,
82 IN u8 NumInPipe,
83 IN u8 NumOutPipe
84 )
85 {
86 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
87 BOOLEAN result = _FALSE;
88
89 _ConfigChipOutEP_8723(pAdapter, NumOutPipe);
90
91 // Normal chip with one IN and one OUT doesn't have interrupt IN EP.
92 if(1 == pHalData->OutEpNumber){
93 if(1 != NumInPipe){
94 return result;
95 }
96 }
97
98 // All config other than above support one Bulk IN and one Interrupt IN.
99 //if(2 != NumInPipe){
100 // return result;
101 //}
102
103 result = Hal_MappingOutPipe(pAdapter, NumOutPipe);
104
105 return result;
106
107 }
108
rtl8723bu_interface_configure(_adapter * padapter)109 void rtl8723bu_interface_configure(_adapter *padapter)
110 {
111 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
112 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
113
114 if (IS_HIGH_SPEED_USB(padapter))
115 {
116 pHalData->UsbBulkOutSize = USB_HIGH_SPEED_BULK_SIZE;//512 bytes
117 }
118 else
119 {
120 pHalData->UsbBulkOutSize = USB_FULL_SPEED_BULK_SIZE;//64 bytes
121 }
122
123 pHalData->interfaceIndex = pdvobjpriv->InterfaceNumber;
124
125 #ifdef CONFIG_USB_TX_AGGREGATION
126 pHalData->UsbTxAggMode = 1;
127 pHalData->UsbTxAggDescNum = 0x6; // only 4 bits
128 #endif
129
130 #ifdef CONFIG_USB_RX_AGGREGATION
131 pHalData->UsbRxAggMode = USB_RX_AGG_USB;
132 pHalData->UsbRxAggBlockCount = 0x5; /* unit: 4KB, for USB mode */
133 pHalData->UsbRxAggBlockTimeout = 0x20; /* unit: 32us, for USB mode */
134 pHalData->UsbRxAggPageCount = 0xF; /* uint: 1KB, for DMA mode */
135 pHalData->UsbRxAggPageTimeout = 0x20; /* unit: 32us, for DMA mode */
136 #endif
137
138 HalUsbSetQueuePipeMapping8723BUsb(padapter,
139 pdvobjpriv->RtNumInPipes, pdvobjpriv->RtNumOutPipes);
140
141 }
142
_InitPowerOn_8723BU(PADAPTER padapter)143 static u32 _InitPowerOn_8723BU(PADAPTER padapter)
144 {
145 u8 status = _SUCCESS;
146 u16 value16=0;
147 u8 value8 = 0;
148 u32 value32;
149
150 rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &value8);
151 if (value8 == _TRUE)
152 return _SUCCESS;
153
154 // HW Power on sequence
155 if(!HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, rtl8723B_card_enable_flow ))
156 return _FAIL;
157
158 // Enable MAC DMA/WMAC/SCHEDULE/SEC block
159 // Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31.
160 rtw_write8(padapter, REG_CR_8723B, 0x00); //suggseted by zhouzhou, by page, 20111230
161 value16 = rtw_read16(padapter, REG_CR_8723B);
162 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
163 | PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN);
164 rtw_write16(padapter, REG_CR_8723B, value16);
165
166 value8 = _TRUE;
167 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &value8);
168
169 #ifdef CONFIG_BT_COEXIST
170 rtw_btcoex_PowerOnSetting(padapter);
171
172 // external switch to S1
173 // 0x38[11] = 0x1
174 // 0x4c[23] = 0x1
175 // 0x64[0] = 0
176 value16 = rtw_read16(padapter, REG_PWR_DATA);
177 // Switch the control of EESK, EECS to RFC for DPDT or Antenna switch
178 value16 |= BIT(11); // BIT_EEPRPAD_RFE_CTRL_EN
179 rtw_write16(padapter, REG_PWR_DATA, value16);
180 //DBG_8192C("%s: REG_PWR_DATA(0x%x)=0x%04X\n", __FUNCTION__, REG_PWR_DATA, rtw_read16(padapter, REG_PWR_DATA));
181
182 value32 = rtw_read32(padapter, REG_LEDCFG0);
183 value32 |= BIT(23); // DPDT_SEL_EN, 1 for SW control
184 rtw_write32(padapter, REG_LEDCFG0, value32);
185 //DBG_8192C("%s: REG_LEDCFG0(0x%x)=0x%08X\n", __FUNCTION__, REG_LEDCFG0, rtw_read32(padapter, REG_LEDCFG0));
186
187 value8 = rtw_read8(padapter, REG_PAD_CTRL1_8723B);
188 value8 &= ~BIT(0); // BIT_SW_DPDT_SEL_DATA, DPDT_SEL default configuration
189 rtw_write8(padapter, REG_PAD_CTRL1_8723B, value8);
190 //DBG_8192C("%s: REG_PAD_CTRL1(0x%x)=0x%02X\n", __FUNCTION__, REG_PAD_CTRL1_8723B, rtw_read8(padapter, REG_PAD_CTRL1_8723B));
191 #endif // CONFIG_BT_COEXIST
192
193 return status;
194 }
195
196
197
198 //-------------------------------------------------------------------------
199 //
200 // LLT R/W/Init function
201 //
202 //-------------------------------------------------------------------------
_LLTWrite(IN PADAPTER Adapter,IN u32 address,IN u32 data)203 static u8 _LLTWrite(
204 IN PADAPTER Adapter,
205 IN u32 address,
206 IN u32 data
207 )
208 {
209 u8 status = _SUCCESS;
210 s8 count = POLLING_LLT_THRESHOLD;
211 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
212
213 rtw_write32(Adapter, REG_LLT_INIT, value);
214
215 //polling
216 do{
217 value = rtw_read32(Adapter, REG_LLT_INIT);
218 if(_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)){
219 break;
220 }
221 }while(--count);
222
223 if(count <= 0){
224 DBG_871X("Failed to polling write LLT done at address %d!\n", address);
225 status = _FAIL;
226 }
227 return status;
228
229 }
230
231
_LLTRead(IN PADAPTER Adapter,IN u32 address)232 static u8 _LLTRead(
233 IN PADAPTER Adapter,
234 IN u32 address
235 )
236 {
237 int count = 0;
238 u32 value = _LLT_INIT_ADDR(address) | _LLT_OP(_LLT_READ_ACCESS);
239
240 rtw_write32(Adapter, REG_LLT_INIT, value);
241
242 //polling and get value
243 do{
244
245 value = rtw_read32(Adapter, REG_LLT_INIT);
246 if(_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)){
247 return (u8)value;
248 }
249
250 if(count > POLLING_LLT_THRESHOLD){
251 //RT_TRACE(COMP_INIT,DBG_SERIOUS,("Failed to polling read LLT done at address %d!\n", address));
252 break;
253 }
254 }while(count++);
255
256 return 0xFF;
257
258 }
259
260
261 //---------------------------------------------------------------
262 //
263 // MAC init functions
264 //
265 //---------------------------------------------------------------
266
267 /*
268 * USB has no hardware interrupt,
269 * so no need to initialize HIMR.
270 */
_InitInterrupt(PADAPTER padapter)271 static void _InitInterrupt(PADAPTER padapter)
272 {
273 #ifdef CONFIG_SUPPORT_USB_INT
274 /* clear interrupt, write 1 clear */
275 rtw_write32(padapter, REG_HISR0_8723B, 0xFFFFFFFF);
276 rtw_write32(padapter, REG_HISR1_8723B, 0xFFFFFFFF);
277 #endif /* CONFIG_SUPPORT_USB_INT */
278 }
279
_InitQueueReservedPage(PADAPTER padapter)280 static void _InitQueueReservedPage(PADAPTER padapter)
281 {
282 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
283 struct registry_priv *pregistrypriv = &padapter->registrypriv;
284 u32 outEPNum = (u32)pHalData->OutEpNumber;
285 u32 numHQ = 0;
286 u32 numLQ = 0;
287 u32 numNQ = 0;
288 u32 numPubQ;
289 u32 value32;
290 u8 value8;
291 BOOLEAN bWiFiConfig = pregistrypriv->wifi_spec;
292
293 if (pHalData->OutEpQueueSel & TX_SELE_HQ)
294 {
295 numHQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_HPQ_8723B : NORMAL_PAGE_NUM_HPQ_8723B;
296 }
297
298 if (pHalData->OutEpQueueSel & TX_SELE_LQ)
299 {
300 numLQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_LPQ_8723B : NORMAL_PAGE_NUM_LPQ_8723B;
301 }
302
303 // NOTE: This step shall be proceed before writting REG_RQPN.
304 if (pHalData->OutEpQueueSel & TX_SELE_NQ) {
305 numNQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_NPQ_8723B : NORMAL_PAGE_NUM_NPQ_8723B;
306 }
307 value8 = (u8)_NPQ(numNQ);
308 rtw_write8(padapter, REG_RQPN_NPQ, value8);
309
310 numPubQ = TX_TOTAL_PAGE_NUMBER_8723B - numHQ - numLQ - numNQ;
311
312 // TX DMA
313 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
314 rtw_write32(padapter, REG_RQPN, value32);
315
316 }
317
_InitTxBufferBoundary(PADAPTER padapter)318 static void _InitTxBufferBoundary(PADAPTER padapter)
319 {
320 struct registry_priv *pregistrypriv = &padapter->registrypriv;
321 #ifdef CONFIG_CONCURRENT_MODE
322 u8 val8;
323 #endif // CONFIG_CONCURRENT_MODE
324
325 //u16 txdmactrl;
326 u8 txpktbuf_bndy;
327
328 if(!pregistrypriv->wifi_spec){
329 txpktbuf_bndy = TX_PAGE_BOUNDARY_8723B;
330 } else {
331 //for WMM
332 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_8723B;
333 }
334
335 rtw_write8(padapter, REG_TXPKTBUF_BCNQ_BDNY_8723B, txpktbuf_bndy);
336 rtw_write8(padapter, REG_TXPKTBUF_MGQ_BDNY_8723B, txpktbuf_bndy);
337 rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B, txpktbuf_bndy);
338 rtw_write8(padapter, REG_TRXFF_BNDY, txpktbuf_bndy);
339 rtw_write8(padapter, REG_TDECTRL+1, txpktbuf_bndy);
340
341 #ifdef CONFIG_CONCURRENT_MODE
342 val8 = txpktbuf_bndy + 8;
343 rtw_write8(padapter, REG_BCNQ1_BDNY, val8);
344 rtw_write8(padapter, REG_DWBCN1_CTRL_8723B+1, val8); // BCN1_HEAD
345
346 val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8723B+2);
347 val8 |= BIT(1); // BIT1- BIT_SW_BCN_SEL_EN
348 rtw_write8(padapter, REG_DWBCN1_CTRL_8723B+2, val8);
349 #endif // CONFIG_CONCURRENT_MODE
350 }
351
352
353 VOID
_InitTransferPageSize_8723bu(PADAPTER Adapter)354 _InitTransferPageSize_8723bu(
355 PADAPTER Adapter
356 )
357 {
358
359 u1Byte value8;
360 value8 = _PSRX(PBP_256) | _PSTX(PBP_256);
361
362 rtw_write8(Adapter, REG_PBP_8723B, value8);
363 }
364
365
366 static VOID
_InitNormalChipRegPriority(IN PADAPTER Adapter,IN u16 beQ,IN u16 bkQ,IN u16 viQ,IN u16 voQ,IN u16 mgtQ,IN u16 hiQ)367 _InitNormalChipRegPriority(
368 IN PADAPTER Adapter,
369 IN u16 beQ,
370 IN u16 bkQ,
371 IN u16 viQ,
372 IN u16 voQ,
373 IN u16 mgtQ,
374 IN u16 hiQ
375 )
376 {
377 u16 value16 = (rtw_read16(Adapter, REG_TRXDMA_CTRL_8723B) & 0x7);
378
379 value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
380 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
381 _TXDMA_MGQ_MAP(mgtQ)| _TXDMA_HIQ_MAP(hiQ);
382
383 rtw_write16(Adapter, REG_TRXDMA_CTRL_8723B, value16);
384 }
385
386
387 static VOID
_InitNormalChipTwoOutEpPriority(IN PADAPTER Adapter)388 _InitNormalChipTwoOutEpPriority(
389 IN PADAPTER Adapter
390 )
391 {
392 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
393 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
394 u16 beQ,bkQ,viQ,voQ,mgtQ,hiQ;
395
396
397 u16 valueHi = 0;
398 u16 valueLow = 0;
399
400 switch(pHalData->OutEpQueueSel)
401 {
402 case (TX_SELE_HQ | TX_SELE_LQ):
403 valueHi = QUEUE_HIGH;
404 valueLow = QUEUE_LOW;
405 break;
406 case (TX_SELE_NQ | TX_SELE_LQ):
407 valueHi = QUEUE_NORMAL;
408 valueLow = QUEUE_LOW;
409 break;
410 case (TX_SELE_HQ | TX_SELE_NQ):
411 valueHi = QUEUE_HIGH;
412 valueLow = QUEUE_NORMAL;
413 break;
414 default:
415 //RT_ASSERT(FALSE,("Shall not reach here!\n"));
416 break;
417 }
418
419 if(!pregistrypriv->wifi_spec ){
420 beQ = valueLow;
421 bkQ = valueLow;
422 viQ = valueHi;
423 voQ = valueHi;
424 mgtQ = valueHi;
425 hiQ = valueHi;
426 }
427 else{//for WMM ,CONFIG_OUT_EP_WIFI_MODE
428 beQ = valueLow;
429 bkQ = valueHi;
430 viQ = valueHi;
431 voQ = valueLow;
432 mgtQ = valueHi;
433 hiQ = valueHi;
434 }
435
436 _InitNormalChipRegPriority(Adapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ);
437
438 }
439
440 static VOID
_InitNormalChipThreeOutEpPriority(IN PADAPTER padapter)441 _InitNormalChipThreeOutEpPriority(
442 IN PADAPTER padapter
443 )
444 {
445 struct registry_priv *pregistrypriv = &padapter->registrypriv;
446 u16 beQ,bkQ,viQ,voQ,mgtQ,hiQ;
447
448 if(!pregistrypriv->wifi_spec ){// typical setting
449 beQ = QUEUE_LOW;
450 bkQ = QUEUE_LOW;
451 viQ = QUEUE_NORMAL;
452 voQ = QUEUE_HIGH;
453 mgtQ = QUEUE_HIGH;
454 hiQ = QUEUE_HIGH;
455 }
456 else{// for WMM
457 beQ = QUEUE_LOW;
458 bkQ = QUEUE_NORMAL;
459 viQ = QUEUE_NORMAL;
460 voQ = QUEUE_HIGH;
461 mgtQ = QUEUE_HIGH;
462 hiQ = QUEUE_HIGH;
463 }
464 _InitNormalChipRegPriority(padapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ);
465 }
466
_InitQueuePriority(PADAPTER padapter)467 static void _InitQueuePriority(PADAPTER padapter)
468 {
469 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
470 switch(pHalData->OutEpNumber)
471 {
472 case 2:
473 _InitNormalChipTwoOutEpPriority(padapter);
474 break;
475 case 3:
476 case 4:
477 _InitNormalChipThreeOutEpPriority(padapter);
478 break;
479 default:
480 //RT_ASSERT(FALSE,("Shall not reach here!\n"));
481 break;
482 }
483
484 }
485
486
_InitPageBoundary(PADAPTER padapter)487 static void _InitPageBoundary(PADAPTER padapter)
488 {
489 /* RX FIFO(RXFF0) Boundary, unit is byte */
490 rtw_write16(padapter, REG_TRXFF_BNDY+2, RX_DMA_BOUNDARY_8723B);
491 }
492
493 static VOID
_InitHardwareDropIncorrectBulkOut(IN PADAPTER Adapter)494 _InitHardwareDropIncorrectBulkOut(
495 IN PADAPTER Adapter
496 )
497 {
498 u32 value32 = rtw_read32(Adapter, REG_TXDMA_OFFSET_CHK);
499 value32 |= DROP_DATA_EN;
500 rtw_write32(Adapter, REG_TXDMA_OFFSET_CHK, value32);
501 }
502
503 static VOID
_InitNetworkType(IN PADAPTER Adapter)504 _InitNetworkType(
505 IN PADAPTER Adapter
506 )
507 {
508 u32 value32;
509
510 value32 = rtw_read32(Adapter, REG_CR);
511
512 // TODO: use the other function to set network type
513 #if 0//RTL8191C_FPGA_NETWORKTYPE_ADHOC
514 value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AD_HOC);
515 #else
516 value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
517 #endif
518 rtw_write32(Adapter, REG_CR, value32);
519 // RASSERT(pIoBase->rtw_read8(REG_CR + 2) == 0x2);
520 }
521
522
523 static VOID
_InitDriverInfoSize(IN PADAPTER Adapter,IN u8 drvInfoSize)524 _InitDriverInfoSize(
525 IN PADAPTER Adapter,
526 IN u8 drvInfoSize
527 )
528 {
529 rtw_write8(Adapter,REG_RX_DRVINFO_SZ, drvInfoSize);
530 }
531
532 static VOID
_InitWMACSetting(IN PADAPTER Adapter)533 _InitWMACSetting(
534 IN PADAPTER Adapter
535 )
536 {
537 //u4Byte value32;
538 u16 value16;
539 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
540
541 // pHalData->ReceiveConfig = AAP | APM | AM |AB |ADD3|APWRMGT| APP_ICV | APP_MIC |APP_FCS|ADF |ACF|AMF|HTC_LOC_CTRL|APP_PHYSTS;
542 pHalData->ReceiveConfig = 0;
543 pHalData->ReceiveConfig |= APM | AM | AB;
544 pHalData->ReceiveConfig |= CBSSID_DATA | CBSSID_BCN | AMF;
545 pHalData->ReceiveConfig |= HTC_LOC_CTRL;
546 pHalData->ReceiveConfig |= APP_PHYSTS | APP_ICV | APP_MIC;
547
548 rtw_write32(Adapter, REG_RCR, pHalData->ReceiveConfig);
549
550 // Accept all data frames
551 value16 = 0xFFFF;
552 rtw_write16(Adapter, REG_RXFLTMAP2_8723B, value16);
553
554 // 2010.09.08 hpfan
555 // Since ADF is removed from RCR, ps-poll will not be indicate to driver,
556 // RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll.
557
558 value16 = 0x400;
559 rtw_write16(Adapter, REG_RXFLTMAP1_8723B, value16);
560
561 // Accept all management frames
562 value16 = 0xFFFF;
563 rtw_write16(Adapter, REG_RXFLTMAP0_8723B, value16);
564
565 }
566
567 static VOID
_InitAdaptiveCtrl(IN PADAPTER Adapter)568 _InitAdaptiveCtrl(
569 IN PADAPTER Adapter
570 )
571 {
572 u16 value16;
573 u32 value32;
574
575 // Response Rate Set
576 value32 = rtw_read32(Adapter, REG_RRSR);
577 value32 &= ~RATE_BITMAP_ALL;
578 value32 |= RATE_RRSR_CCK_ONLY_1M;
579 rtw_write32(Adapter, REG_RRSR, value32);
580
581 // CF-END Threshold
582 //m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1);
583
584 // SIFS (used in NAV)
585 value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
586 rtw_write16(Adapter, REG_SPEC_SIFS, value16);
587
588 // Retry Limit
589 value16 = _LRL(0x30) | _SRL(0x30);
590 rtw_write16(Adapter, REG_RL, value16);
591
592 }
593
594 static VOID
_InitRateFallback(IN PADAPTER Adapter)595 _InitRateFallback(
596 IN PADAPTER Adapter
597 )
598 {
599 // Set Data Auto Rate Fallback Retry Count register.
600 rtw_write32(Adapter, REG_DARFRC, 0x00000000);
601 rtw_write32(Adapter, REG_DARFRC+4, 0x10080404);
602 rtw_write32(Adapter, REG_RARFRC, 0x04030201);
603 rtw_write32(Adapter, REG_RARFRC+4, 0x08070605);
604
605 }
606
607
608 static VOID
_InitEDCA(IN PADAPTER Adapter)609 _InitEDCA(
610 IN PADAPTER Adapter
611 )
612 {
613 // Set Spec SIFS (used in NAV)
614 rtw_write16(Adapter,REG_SPEC_SIFS, 0x100a);
615 rtw_write16(Adapter,REG_MAC_SPEC_SIFS, 0x100a);
616
617 // Set SIFS for CCK
618 rtw_write16(Adapter,REG_SIFS_CTX, 0x100a);
619
620 // Set SIFS for OFDM
621 rtw_write16(Adapter,REG_SIFS_TRX, 0x100a);
622
623 // TXOP
624 rtw_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B);
625 rtw_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F);
626 rtw_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324);
627 rtw_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226);
628 }
629
630 #ifdef CONFIG_LED
_InitHWLed(PADAPTER Adapter)631 static void _InitHWLed(PADAPTER Adapter)
632 {
633 struct led_priv *pledpriv = &(Adapter->ledpriv);
634
635 if( pledpriv->LedStrategy != HW_LED)
636 return;
637
638 // HW led control
639 // to do ....
640 //must consider cases of antenna diversity/ commbo card/solo card/mini card
641
642 }
643 #endif //CONFIG_LED
644
645 static VOID
_InitRDGSetting_8723bu(IN PADAPTER Adapter)646 _InitRDGSetting_8723bu(
647 IN PADAPTER Adapter
648 )
649 {
650 rtw_write8(Adapter,REG_RD_CTRL_8723B,0xFF);
651 rtw_write16(Adapter, REG_RD_NAV_NXT_8723B, 0x200);
652 rtw_write8(Adapter,REG_RD_RESP_PKT_TH_8723B,0x05);
653 }
654
655 static VOID
_InitRetryFunction(IN PADAPTER Adapter)656 _InitRetryFunction(
657 IN PADAPTER Adapter
658 )
659 {
660 u8 value8;
661
662 value8 = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL);
663 value8 |= EN_AMPDU_RTY_NEW;
664 rtw_write8(Adapter, REG_FWHW_TXQ_CTRL, value8);
665
666 // Set ACK timeout
667 rtw_write8(Adapter, REG_ACKTO, 0x40);
668 }
669
_InitBurstPktLen(PADAPTER padapter)670 static void _InitBurstPktLen(PADAPTER padapter)
671 {
672 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
673 u8 tmp8;
674
675
676 tmp8 = rtw_read8(padapter, REG_RXDMA_PRO_8723B);
677 tmp8 &= ~(BIT(4) | BIT(5));
678 switch (pHalData->UsbBulkOutSize) {
679 case USB_HIGH_SPEED_BULK_SIZE:
680 tmp8 |= BIT(4); // set burst pkt len=512B
681 break;
682 case USB_FULL_SPEED_BULK_SIZE:
683 default:
684 tmp8 |= BIT(5); // set burst pkt len=64B
685 break;
686 }
687 tmp8 |= BIT(1) | BIT(2) | BIT(3);
688 rtw_write8(padapter, REG_RXDMA_PRO_8723B, tmp8);
689
690 pHalData->bSupportUSB3 = _FALSE;
691
692 tmp8 = rtw_read8(padapter, REG_HT_SINGLE_AMPDU_8723B);
693 tmp8 |= BIT(7); // enable single pkt ampdu
694 rtw_write8(padapter, REG_HT_SINGLE_AMPDU_8723B, tmp8);
695 rtw_write16(padapter, REG_MAX_AGGR_NUM, 0x0C14);
696 rtw_write8(padapter, REG_AMPDU_MAX_TIME_8723B, 0x5E);
697 rtw_write32(padapter, REG_AMPDU_MAX_LENGTH_8723B, 0xffffffff);
698 if (pHalData->AMPDUBurstMode)
699 rtw_write8(padapter, REG_AMPDU_BURST_MODE_8723B, 0x5F);
700
701 // for VHT packet length 11K
702 rtw_write8(padapter, REG_RX_PKT_LIMIT, 0x18);
703
704 rtw_write8(padapter, REG_PIFS, 0x00);
705 rtw_write8(padapter, REG_FWHW_TXQ_CTRL, 0x80);
706 rtw_write32(padapter, REG_FAST_EDCA_CTRL, 0x03086666);
707 rtw_write8(padapter, REG_USTIME_TSF_8723B, 0x50);
708 rtw_write8(padapter, REG_USTIME_EDCA_8723B, 0x50);
709
710 // to prevent mac is reseted by bus. 20111208, by Page
711 tmp8 = rtw_read8(padapter, REG_RSV_CTRL);
712 tmp8 |= BIT(5) | BIT(6);
713 rtw_write8(padapter, REG_RSV_CTRL, tmp8);
714 }
715
716 /*-----------------------------------------------------------------------------
717 * Function: usb_AggSettingTxUpdate()
718 *
719 * Overview: Seperate TX/RX parameters update independent for TP detection and
720 * dynamic TX/RX aggreagtion parameters update.
721 *
722 * Input: PADAPTER
723 *
724 * Output/Return: NONE
725 *
726 * Revised History:
727 * When Who Remark
728 * 12/10/2010 MHC Seperate to smaller function.
729 *
730 *---------------------------------------------------------------------------*/
731 static VOID
usb_AggSettingTxUpdate(IN PADAPTER Adapter)732 usb_AggSettingTxUpdate(
733 IN PADAPTER Adapter
734 )
735 {
736 #ifdef CONFIG_USB_TX_AGGREGATION
737 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
738 //PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
739 u32 value32;
740
741 if(Adapter->registrypriv.wifi_spec)
742 pHalData->UsbTxAggMode = _FALSE;
743
744 if(pHalData->UsbTxAggMode){
745 value32 = rtw_read32(Adapter, REG_DWBCN0_CTRL_8723B);
746 value32 = value32 & ~(BLK_DESC_NUM_MASK << BLK_DESC_NUM_SHIFT);
747 value32 |= ((pHalData->UsbTxAggDescNum & BLK_DESC_NUM_MASK) << BLK_DESC_NUM_SHIFT);
748
749 rtw_write32(Adapter, REG_DWBCN0_CTRL_8723B, value32);
750 rtw_write8(Adapter, REG_DWBCN1_CTRL_8723B, pHalData->UsbTxAggDescNum<<1);
751 }
752
753 #endif
754 } // usb_AggSettingTxUpdate
755
756
757 /*-----------------------------------------------------------------------------
758 * Function: usb_AggSettingRxUpdate()
759 *
760 * Overview: Seperate TX/RX parameters update independent for TP detection and
761 * dynamic TX/RX aggreagtion parameters update.
762 *
763 * Input: PADAPTER
764 *
765 * Output/Return: NONE
766 *
767 *---------------------------------------------------------------------------*/
usb_AggSettingRxUpdate(PADAPTER padapter)768 static void usb_AggSettingRxUpdate(PADAPTER padapter)
769 {
770 PHAL_DATA_TYPE pHalData;
771 u8 aggctrl;
772 u32 aggrx;
773 u32 agg_size;
774
775
776 pHalData = GET_HAL_DATA(padapter);
777
778 aggctrl = rtw_read8(padapter, REG_TRXDMA_CTRL);
779 aggctrl &= ~RXDMA_AGG_EN;
780
781 aggrx = rtw_read32(padapter, REG_RXDMA_AGG_PG_TH);
782 aggrx &= ~BIT_USB_RXDMA_AGG_EN;
783 aggrx &= ~0xFF0F; // reset agg size and timeout
784
785 #ifdef CONFIG_USB_RX_AGGREGATION
786 switch(pHalData->UsbRxAggMode) {
787 case USB_RX_AGG_DMA:
788 agg_size = pHalData->UsbRxAggPageCount << 10;
789 if (agg_size > RX_DMA_BOUNDARY_8723B)
790 agg_size = RX_DMA_BOUNDARY_8723B >> 1;
791 if ((agg_size + 2048) > MAX_RECVBUF_SZ)
792 agg_size = MAX_RECVBUF_SZ - 2048;
793 agg_size >>= 10; /* unit: 1K */
794 if (agg_size > 0xF)
795 agg_size = 0xF;
796
797 aggctrl |= RXDMA_AGG_EN;
798 aggrx |= BIT_USB_RXDMA_AGG_EN;
799 aggrx |= agg_size;
800 aggrx |= (pHalData->UsbRxAggPageTimeout << 8);
801 DBG_8192C("%s: RX Agg-DMA mode, size=%dKB, timeout=%dus\n",
802 __func__, agg_size, pHalData->UsbRxAggPageTimeout*32);
803 break;
804
805 case USB_RX_AGG_USB:
806 case USB_RX_AGG_MIX:
807 agg_size = pHalData->UsbRxAggBlockCount << 12;
808 if ((agg_size + 2048) > MAX_RECVBUF_SZ)
809 agg_size = MAX_RECVBUF_SZ - 2048;
810 agg_size >>= 12; /* unit: 4K */
811 if (agg_size > 0xF)
812 agg_size = 0xF;
813
814 aggctrl |= RXDMA_AGG_EN;
815 aggrx &= ~BIT_USB_RXDMA_AGG_EN;
816 aggrx |= agg_size;
817 aggrx |= (pHalData->UsbRxAggBlockTimeout << 8);
818 DBG_8192C("%s: RX Agg-USB mode, size=%dKB, timeout=%dus\n",
819 __func__, agg_size*4, pHalData->UsbRxAggBlockTimeout*32);
820 break;
821
822 case USB_RX_AGG_DISABLE:
823 default:
824 DBG_8192C("%s: RX Aggregation Disable!\n", __FUNCTION__);
825 break;
826 }
827 #endif // CONFIG_USB_RX_AGGREGATION
828
829 rtw_write8(padapter, REG_TRXDMA_CTRL, aggctrl);
830 rtw_write32(padapter, REG_RXDMA_AGG_PG_TH, aggrx);
831 }
832
833 static VOID
_initUsbAggregationSetting(IN PADAPTER Adapter)834 _initUsbAggregationSetting(
835 IN PADAPTER Adapter
836 )
837 {
838 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
839
840 // Tx aggregation setting
841 usb_AggSettingTxUpdate(Adapter);
842
843 // Rx aggregation setting
844 usb_AggSettingRxUpdate(Adapter);
845
846 // 201/12/10 MH Add for USB agg mode dynamic switch.
847 pHalData->UsbRxHighSpeedMode = _FALSE;
848 }
849
850 static VOID
PHY_InitAntennaSelection8723B(PADAPTER Adapter)851 PHY_InitAntennaSelection8723B(
852 PADAPTER Adapter
853 )
854 {
855 // TODO: <20130114, Kordan> The following setting is only for DPDT and Fixed board type.
856 // TODO: A better solution is configure it according EFUSE during the run-time.
857 PHY_SetMacReg(Adapter, 0x64, BIT20, 0x0); //0x66[4]=0
858 PHY_SetMacReg(Adapter, 0x64, BIT24, 0x0); //0x66[8]=0
859 PHY_SetMacReg(Adapter, 0x40, BIT4, 0x0); //0x40[4]=0
860 PHY_SetMacReg(Adapter, 0x40, BIT3, 0x1); //0x40[3]=1
861 PHY_SetMacReg(Adapter, 0x4C, BIT24, 0x1); //0x4C[24:23]=10
862 PHY_SetMacReg(Adapter, 0x4C, BIT23, 0x0); //0x4C[24:23]=10
863 PHY_SetBBReg(Adapter, 0x944, BIT1|BIT0, 0x3); //0x944[1:0]=11
864 PHY_SetBBReg(Adapter, 0x930, bMaskByte0, 0x77); //0x930[7:0]=77
865 PHY_SetMacReg(Adapter, 0x38, BIT11, 0x1); //0x38[11]=1
866 }
867
_InitAdhocWorkaroundParams(IN PADAPTER Adapter)868 static VOID _InitAdhocWorkaroundParams(IN PADAPTER Adapter)
869 {
870 #ifdef CONFIG_ADHOC_WORKAROUND_SETTING
871 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
872 pHalData->RegBcnCtrlVal = rtw_read8(Adapter, REG_BCN_CTRL);
873 pHalData->RegTxPause = rtw_read8(Adapter, REG_TXPAUSE);
874 pHalData->RegFwHwTxQCtrl = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL+2);
875 pHalData->RegReg542 = rtw_read8(Adapter, REG_TBTT_PROHIBIT+2);
876 #endif
877 }
878
879 // Set CCK and OFDM Block "ON"
_BBTurnOnBlock(IN PADAPTER Adapter)880 static VOID _BBTurnOnBlock(
881 IN PADAPTER Adapter
882 )
883 {
884 #if (DISABLE_BB_RF)
885 return;
886 #endif
887
888 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1);
889 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
890 }
891
892 #define MgntActSet_RF_State(...)
893
894 enum {
895 Antenna_Lfet = 1,
896 Antenna_Right = 2,
897 };
898
899 //
900 // 2010/08/09 MH Add for power down check.
901 //
902 static BOOLEAN
HalDetectPwrDownMode(IN PADAPTER Adapter)903 HalDetectPwrDownMode(
904 IN PADAPTER Adapter
905 )
906 {
907 u8 tmpvalue;
908 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
909 struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter);
910
911 EFUSE_ShadowRead(Adapter, 1, EEPROM_FEATURE_OPTION_8723B, (u32 *)&tmpvalue);
912
913 // 2010/08/25 MH INF priority > PDN Efuse value.
914 if(tmpvalue & BIT4 && pwrctrlpriv->reg_pdnmode)
915 {
916 pHalData->pwrdown = _TRUE;
917 }
918 else
919 {
920 pHalData->pwrdown = _FALSE;
921 }
922
923 DBG_8192C("HalDetectPwrDownMode(): PDN=%d\n", pHalData->pwrdown);
924 return pHalData->pwrdown;
925
926 } // HalDetectPwrDownMode
927
928
929 //
930 // 2010/08/26 MH Add for selective suspend mode check.
931 // If Efuse 0x0e bit1 is not enabled, we can not support selective suspend for Minicard and
932 // slim card.
933 //
934 static VOID
HalDetectSelectiveSuspendMode(IN PADAPTER Adapter)935 HalDetectSelectiveSuspendMode(
936 IN PADAPTER Adapter
937 )
938 {
939 #if 0 //amyma
940 u8 tmpvalue;
941 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
942 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter);
943
944 // If support HW radio detect, we need to enable WOL ability, otherwise, we
945 // can not use FW to notify host the power state switch.
946
947 EFUSE_ShadowRead(Adapter, 1, EEPROM_USB_OPTIONAL1, (u32 *)&tmpvalue);
948
949 DBG_8192C("HalDetectSelectiveSuspendMode(): SS ");
950 if(tmpvalue & BIT1)
951 {
952 DBG_8192C("Enable\n");
953 }
954 else
955 {
956 DBG_8192C("Disable\n");
957 pdvobjpriv->RegUsbSS = _FALSE;
958 }
959
960 // 2010/09/01 MH According to Dongle Selective Suspend INF. We can switch SS mode.
961 if (pdvobjpriv->RegUsbSS && !SUPPORT_HW_RADIO_DETECT(pHalData))
962 {
963 //PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
964
965 //if (!pMgntInfo->bRegDongleSS)
966 //{
967 // RT_TRACE(COMP_INIT, DBG_LOUD, ("Dongle disable SS\n"));
968 pdvobjpriv->RegUsbSS = _FALSE;
969 //}
970 }
971 #endif
972 } // HalDetectSelectiveSuspendMode
973 /*-----------------------------------------------------------------------------
974 * Function: HwSuspendModeEnable92Cu()
975 *
976 * Overview: HW suspend mode switch.
977 *
978 * Input: NONE
979 *
980 * Output: NONE
981 *
982 * Return: NONE
983 *
984 * Revised History:
985 * When Who Remark
986 * 08/23/2010 MHC HW suspend mode switch test..
987 *---------------------------------------------------------------------------*/
988 static VOID
HwSuspendModeEnable92Cu(IN PADAPTER pAdapter,IN u8 Type)989 HwSuspendModeEnable92Cu(
990 IN PADAPTER pAdapter,
991 IN u8 Type
992 )
993 {
994 //PRT_USB_DEVICE pDevice = GET_RT_USB_DEVICE(pAdapter);
995 u16 reg = rtw_read16(pAdapter, REG_GPIO_MUXCFG);
996
997 //if (!pDevice->RegUsbSS)
998 {
999 return;
1000 }
1001
1002 //
1003 // 2010/08/23 MH According to Alfred's suggestion, we need to to prevent HW
1004 // to enter suspend mode automatically. Otherwise, it will shut down major power
1005 // domain and 8051 will stop. When we try to enter selective suspend mode, we
1006 // need to prevent HW to enter D2 mode aumotmatically. Another way, Host will
1007 // issue a S10 signal to power domain. Then it will cleat SIC setting(from Yngli).
1008 // We need to enable HW suspend mode when enter S3/S4 or disable. We need
1009 // to disable HW suspend mode for IPS/radio_off.
1010 //
1011 //RT_TRACE(COMP_RF, DBG_LOUD, ("HwSuspendModeEnable92Cu = %d\n", Type));
1012 if (Type == _FALSE)
1013 {
1014 reg |= BIT14;
1015 //RT_TRACE(COMP_RF, DBG_LOUD, ("REG_GPIO_MUXCFG = %x\n", reg));
1016 rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
1017 reg |= BIT12;
1018 //RT_TRACE(COMP_RF, DBG_LOUD, ("REG_GPIO_MUXCFG = %x\n", reg));
1019 rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
1020 }
1021 else
1022 {
1023 reg &= (~BIT12);
1024 rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
1025 reg &= (~BIT14);
1026 rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg);
1027 }
1028
1029 } // HwSuspendModeEnable92Cu
RfOnOffDetect(IN PADAPTER pAdapter)1030 rt_rf_power_state RfOnOffDetect(IN PADAPTER pAdapter )
1031 {
1032 //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
1033 u8 val8;
1034 rt_rf_power_state rfpowerstate = rf_off;
1035
1036 if(adapter_to_pwrctl(pAdapter)->bHWPowerdown)
1037 {
1038 val8 = rtw_read8(pAdapter, REG_HSISR);
1039 DBG_8192C("pwrdown, 0x5c(BIT7)=%02x\n", val8);
1040 rfpowerstate = (val8 & BIT7) ? rf_off: rf_on;
1041 }
1042 else // rf on/off
1043 {
1044 rtw_write8( pAdapter, REG_MAC_PINMUX_CFG,rtw_read8(pAdapter, REG_MAC_PINMUX_CFG)&~(BIT3));
1045 val8 = rtw_read8(pAdapter, REG_GPIO_IO_SEL);
1046 DBG_8192C("GPIO_IN=%02x\n", val8);
1047 rfpowerstate = (val8 & BIT3) ? rf_on : rf_off;
1048 }
1049 return rfpowerstate;
1050 } // HalDetectPwrDownMode
1051
1052 void _ps_open_RF(_adapter *padapter);
1053
rtl8723bu_hal_init(PADAPTER padapter)1054 u32 rtl8723bu_hal_init(PADAPTER padapter)
1055 {
1056 u8 value8 = 0, u1bRegCR;
1057 u32 boundary, status = _SUCCESS;
1058 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
1059 struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
1060 struct registry_priv *pregistrypriv = &padapter->registrypriv;
1061 rt_rf_power_state eRfPowerStateToSet;
1062 u32 NavUpper = WiFiNavUpperUs;
1063 u32 value32;
1064 u32 init_start_time = rtw_get_current_time();
1065
1066
1067 #ifdef DBG_HAL_INIT_PROFILING
1068
1069 enum HAL_INIT_STAGES {
1070 HAL_INIT_STAGES_BEGIN = 0,
1071 HAL_INIT_STAGES_INIT_PW_ON,
1072 HAL_INIT_STAGES_INIT_LLTT,
1073 HAL_INIT_STAGES_MISC01,
1074 HAL_INIT_STAGES_DOWNLOAD_FW,
1075 HAL_INIT_STAGES_MAC,
1076 HAL_INIT_STAGES_BB,
1077 HAL_INIT_STAGES_RF,
1078 HAL_INIT_STAGES_MISC02,
1079 HAL_INIT_STAGES_TURN_ON_BLOCK,
1080 HAL_INIT_STAGES_INIT_SECURITY,
1081 HAL_INIT_STAGES_MISC11,
1082 //HAL_INIT_STAGES_RF_PS,
1083 HAL_INIT_STAGES_INIT_HAL_DM,
1084 // HAL_INIT_STAGES_IQK,
1085 // HAL_INIT_STAGES_PW_TRACK,
1086 // HAL_INIT_STAGES_LCK,
1087 HAL_INIT_STAGES_MISC21,
1088 //HAL_INIT_STAGES_INIT_PABIAS,
1089 HAL_INIT_STAGES_BT_COEXIST,
1090 //HAL_INIT_STAGES_ANTENNA_SEL,
1091 HAL_INIT_STAGES_MISC31,
1092 HAL_INIT_STAGES_END,
1093 HAL_INIT_STAGES_NUM
1094 };
1095
1096 char * hal_init_stages_str[] = {
1097 "HAL_INIT_STAGES_BEGIN",
1098 "HAL_INIT_STAGES_INIT_PW_ON",
1099 "HAL_INIT_STAGES_INIT_LLTT",
1100 "HAL_INIT_STAGES_MISC01",
1101 "HAL_INIT_STAGES_DOWNLOAD_FW",
1102 "HAL_INIT_STAGES_MAC",
1103 "HAL_INIT_STAGES_BB",
1104 "HAL_INIT_STAGES_RF",
1105 "HAL_INIT_STAGES_MISC02",
1106 "HAL_INIT_STAGES_TURN_ON_BLOCK",
1107 "HAL_INIT_STAGES_INIT_SECURITY",
1108 "HAL_INIT_STAGES_MISC11",
1109 //"HAL_INIT_STAGES_RF_PS",
1110 "HAL_INIT_STAGES_INIT_HAL_DM",
1111 // "HAL_INIT_STAGES_IQK",
1112 // "HAL_INIT_STAGES_PW_TRACK",
1113 // "HAL_INIT_STAGES_LCK",
1114 "HAL_INIT_STAGES_MISC21",
1115 //"HAL_INIT_STAGES_INIT_PABIAS",
1116 "HAL_INIT_STAGES_BT_COEXIST",
1117 //"HAL_INIT_STAGES_ANTENNA_SEL",
1118 "HAL_INIT_STAGES_MISC31",
1119 "HAL_INIT_STAGES_END",
1120 };
1121
1122 int hal_init_profiling_i;
1123 u32 hal_init_stages_timestamp[HAL_INIT_STAGES_NUM]; //used to record the time of each stage's starting point
1124
1125 for(hal_init_profiling_i=0;hal_init_profiling_i<HAL_INIT_STAGES_NUM;hal_init_profiling_i++)
1126 hal_init_stages_timestamp[hal_init_profiling_i]=0;
1127
1128 #define HAL_INIT_PROFILE_TAG(stage) hal_init_stages_timestamp[(stage)]=rtw_get_current_time();
1129 #else
1130 #define HAL_INIT_PROFILE_TAG(stage) do {} while(0)
1131 #endif //DBG_HAL_INIT_PROFILING
1132
1133
1134
1135 _func_enter_;
1136
1137 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN);
1138
1139 /* if(rtw_is_surprise_removed(padapter))
1140 return _FAIL;*/
1141
1142 // Check if MAC has already power on.
1143 value8 = rtw_read8(padapter, REG_SYS_CLKR_8723B+1);
1144 u1bRegCR = rtw_read8(padapter, REG_CR_8723B);
1145 DBG_871X(" power-on :REG_SYS_CLKR 0x09=0x%02x. REG_CR 0x100=0x%02x.\n", value8, u1bRegCR);
1146 if((value8&BIT3) && (u1bRegCR != 0 && u1bRegCR != 0xEA))
1147 {
1148 DBG_871X(" MAC has already power on.\n");
1149 }
1150 else
1151 {
1152 // Set FwPSState to ALL_ON mode to prevent from the I/O be return because of 32k
1153 // state which is set before sleep under wowlan mode. 2012.01.04. by tynli.
1154 //pHalData->FwPSState = FW_PS_STATE_ALL_ON_88E;
1155 DBG_871X(" MAC has not been powered on yet.\n");
1156 }
1157
1158
1159 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON);
1160 status = rtw_hal_power_on(padapter);
1161 if(status == _FAIL){
1162 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init power on!\n"));
1163 goto exit;
1164 }
1165
1166
1167 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT);
1168 if (!pregistrypriv->wifi_spec) {
1169 boundary = TX_PAGE_BOUNDARY_8723B;
1170 } else {
1171 // for WMM
1172 boundary = WMM_NORMAL_TX_PAGE_BOUNDARY_8723B;
1173 }
1174 status = rtl8723b_InitLLTTable(padapter);
1175 if(status == _FAIL){
1176 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init LLT table\n"));
1177 goto exit;
1178 }
1179
1180 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01);
1181 if(pHalData->bRDGEnable){
1182 _InitRDGSetting_8723bu(padapter);
1183 }
1184
1185
1186 //Enable TX Report
1187 //Enable Tx Report Timer
1188 value8 = rtw_read8(padapter, REG_TX_RPT_CTRL);
1189 rtw_write8(padapter, REG_TX_RPT_CTRL, value8|BIT1);
1190 //Set MAX RPT MACID
1191 rtw_write8(padapter, REG_TX_RPT_CTRL+1, 2);
1192 //Tx RPT Timer. Unit: 32us
1193 rtw_write16(padapter, REG_TX_RPT_TIME, 0xCdf0);
1194
1195 #ifdef CONFIG_TX_EARLY_MODE
1196 if(pHalData->AMPDUBurstMode)
1197 {
1198 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("EarlyMode Enabled!!!\n"));
1199
1200 value8 = rtw_read8(padapter, REG_EARLY_MODE_CONTROL_8723B);
1201 #if RTL8723B_EARLY_MODE_PKT_NUM_10 == 1
1202 value8 = value8|0x1f;
1203 #else
1204 value8 = value8|0xf;
1205 #endif
1206 rtw_write8(padapter, REG_EARLY_MODE_CONTROL_8723B, value8);
1207
1208 rtw_write8(padapter, REG_EARLY_MODE_CONTROL_8723B+3, 0x80);
1209
1210 value8 = rtw_read8(padapter, REG_TCR_8723B+1);
1211 value8 = value8|0x40;
1212 rtw_write8(padapter,REG_TCR_8723B+1, value8);
1213 }
1214 else
1215 rtw_write8(padapter,REG_EARLY_MODE_CONTROL_8723B, 0);
1216 #endif
1217
1218 // <Kordan> InitHalDm should be put ahead of FirmwareDownload. (HWConfig flow: FW->MAC->-BB->RF)
1219 //InitHalDm(Adapter);
1220
1221 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW);
1222 /* if (padapter->registrypriv.mp_mode == 0) */
1223 {
1224 status = rtl8723b_FirmwareDownload(padapter,_FALSE);
1225 if(status != _SUCCESS)
1226 {
1227 padapter->bFWReady = _FALSE;
1228 pHalData->fw_ractrl = _FALSE;
1229 DBG_871X("fw download fail!\n");
1230 goto exit;
1231 }
1232 else
1233 {
1234 padapter->bFWReady = _TRUE;
1235 pHalData->fw_ractrl = _TRUE;
1236 DBG_871X("fw download ok!\n");
1237 }
1238 }
1239
1240 if(pwrctrlpriv->reg_rfoff == _TRUE){
1241 pwrctrlpriv->rf_pwrstate = rf_off;
1242 }
1243
1244 // Set RF type for BB/RF configuration
1245 //_InitRFType(Adapter);
1246
1247 // We should call the function before MAC/BB configuration.
1248 PHY_InitAntennaSelection8723B(padapter);
1249
1250
1251
1252 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC);
1253 #if (HAL_MAC_ENABLE == 1)
1254 status = PHY_MACConfig8723B(padapter);
1255 if(status == _FAIL)
1256 {
1257 DBG_871X("PHY_MACConfig8723B fault !!\n");
1258 goto exit;
1259 }
1260 #endif
1261
1262
1263 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB);
1264 //
1265 //d. Initialize BB related configurations.
1266 //
1267 #if (HAL_BB_ENABLE == 1)
1268 status = PHY_BBConfig8723B(padapter);
1269 if(status == _FAIL)
1270 {
1271 DBG_871X("PHY_BBConfig8723B fault !!\n");
1272 goto exit;
1273 }
1274 #endif
1275
1276
1277
1278
1279 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF);
1280 #if (HAL_RF_ENABLE == 1)
1281 status = PHY_RFConfig8723B(padapter);
1282
1283 if(status == _FAIL)
1284 {
1285 DBG_871X("PHY_RFConfig8723B fault !!\n");
1286 goto exit;
1287 }
1288
1289
1290
1291 #endif
1292
1293
1294
1295 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02);
1296 _InitQueueReservedPage(padapter);
1297 _InitTxBufferBoundary(padapter);
1298 _InitQueuePriority(padapter);
1299 _InitPageBoundary(padapter);
1300 _InitTransferPageSize_8723bu(padapter);
1301
1302
1303 // Get Rx PHY status in order to report RSSI and others.
1304 _InitDriverInfoSize(padapter, DRVINFO_SZ);
1305
1306 _InitInterrupt(padapter);
1307 hal_init_macaddr(padapter);//set mac_address
1308 _InitNetworkType(padapter);//set msr
1309 _InitWMACSetting(padapter);
1310 _InitAdaptiveCtrl(padapter);
1311 _InitEDCA(padapter);
1312 _InitRateFallback(padapter);
1313 _InitRetryFunction(padapter);
1314 // _InitOperationMode(Adapter);//todo
1315 rtl8723b_InitBeaconParameters(padapter);
1316 rtl8723b_InitBeaconMaxError(padapter, _TRUE);
1317
1318 _InitBurstPktLen(padapter);
1319 _initUsbAggregationSetting(padapter);
1320
1321 #ifdef ENABLE_USB_DROP_INCORRECT_OUT
1322 _InitHardwareDropIncorrectBulkOut(padapter);
1323 #endif
1324
1325 #if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_TX_MCAST2UNI)
1326
1327 #ifdef CONFIG_CHECK_AC_LIFETIME
1328 // Enable lifetime check for the four ACs
1329 rtw_write8(padapter, REG_LIFETIME_CTRL, 0x0F);
1330 #endif // CONFIG_CHECK_AC_LIFETIME
1331
1332 #ifdef CONFIG_TX_MCAST2UNI
1333 rtw_write16(padapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400); // unit: 256us. 256ms
1334 rtw_write16(padapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400); // unit: 256us. 256ms
1335 #else // CONFIG_TX_MCAST2UNI
1336 rtw_write16(padapter, REG_PKT_VO_VI_LIFE_TIME, 0x3000); // unit: 256us. 3s
1337 rtw_write16(padapter, REG_PKT_BE_BK_LIFE_TIME, 0x3000); // unit: 256us. 3s
1338 #endif // CONFIG_TX_MCAST2UNI
1339 #endif // CONFIG_CONCURRENT_MODE || CONFIG_TX_MCAST2UNI
1340
1341
1342 #ifdef CONFIG_LED
1343 _InitHWLed(padapter);
1344 #endif //CONFIG_LED
1345
1346 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK);
1347 _BBTurnOnBlock(padapter);
1348 //NicIFSetMacAddress(padapter, padapter->PermanentAddress);
1349
1350
1351 rtw_hal_set_chnl_bw(padapter, padapter->registrypriv.channel,
1352 CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HAL_PRIME_CHNL_OFFSET_DONT_CARE);
1353
1354 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY);
1355 invalidate_cam_all(padapter);
1356
1357 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11);
1358 // 2010/12/17 MH We need to set TX power according to EFUSE content at first.
1359 //PHY_SetTxPowerLevel8723B(padapter, pHalData->CurrentChannel);
1360 rtl8723b_InitAntenna_Selection(padapter);
1361
1362 // HW SEQ CTRL
1363 //set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM.
1364 rtw_write8(padapter,REG_HWSEQ_CTRL, 0xFF);
1365
1366 //
1367 // Disable BAR, suggested by Scott
1368 // 2010.04.09 add by hpfan
1369 //
1370 rtw_write32(padapter, REG_BAR_MODE_CTRL, 0x0201ffff);
1371
1372 if(pregistrypriv->wifi_spec)
1373 rtw_write16(padapter,REG_FAST_EDCA_CTRL ,0);
1374
1375 // Move by Neo for USB SS from above setp
1376
1377 // _RfPowerSave(Adapter);
1378
1379 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM);
1380 rtl8723b_InitHalDm(padapter);
1381
1382 #if (MP_DRIVER == 1)
1383 if (padapter->registrypriv.mp_mode == 1)
1384 {
1385 padapter->mppriv.channel = pHalData->CurrentChannel;
1386 MPT_InitializeAdapter(padapter, padapter->mppriv.channel);
1387 }
1388 else
1389 #endif
1390 {
1391 pwrctrlpriv->rf_pwrstate = rf_on;
1392
1393 if (pwrctrlpriv->rf_pwrstate == rf_on)
1394 {
1395 struct pwrctrl_priv *pwrpriv;
1396 u32 start_time;
1397 u8 restore_iqk_rst;
1398 u8 b2Ant;
1399 u8 h2cCmdBuf;
1400
1401 pwrpriv = adapter_to_pwrctl(padapter);
1402
1403 PHY_LCCalibrate_8723B(&pHalData->odmpriv);
1404
1405 /* Inform WiFi FW that it is the beginning of IQK */
1406 h2cCmdBuf = 1;
1407 FillH2CCmd8723B(padapter, H2C_8723B_BT_WLAN_CALIBRATION, 1, &h2cCmdBuf);
1408
1409 start_time = rtw_get_current_time();
1410 do {
1411 if (rtw_read8(padapter, 0x1e7) & 0x01)
1412 break;
1413
1414 rtw_msleep_os(50);
1415 } while (rtw_get_passing_time_ms(start_time) <= 400);
1416
1417 #ifdef CONFIG_BT_COEXIST
1418 rtw_btcoex_IQKNotify(padapter, _TRUE);
1419 #endif
1420 restore_iqk_rst = (pwrpriv->bips_processing==_TRUE)?_TRUE:_FALSE;
1421 b2Ant = pHalData->EEPROMBluetoothAntNum==Ant_x2?_TRUE:_FALSE;
1422 PHY_IQCalibrate_8723B(padapter, _FALSE, restore_iqk_rst, b2Ant, pHalData->ant_path);
1423 pHalData->bIQKInitialized = _TRUE;
1424 #ifdef CONFIG_BT_COEXIST
1425 rtw_btcoex_IQKNotify(padapter, _FALSE);
1426 #endif
1427
1428 /* Inform WiFi FW that it is the finish of IQK */
1429 h2cCmdBuf = 0;
1430 FillH2CCmd8723B(padapter, H2C_8723B_BT_WLAN_CALIBRATION, 1, &h2cCmdBuf);
1431
1432 ODM_TXPowerTrackingCheck(&pHalData->odmpriv);
1433 }
1434 }
1435
1436
1437 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC21);
1438
1439 //HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PABIAS);
1440 // _InitPABias(Adapter);
1441
1442 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BT_COEXIST);
1443 #ifdef CONFIG_BT_COEXIST
1444 // Init BT hw config.
1445 rtw_btcoex_HAL_Initialize(padapter, _FALSE);
1446 #else
1447 rtw_btcoex_HAL_Initialize(padapter, _TRUE);
1448 #endif
1449
1450 #if 0
1451 // 2010/05/20 MH We need to init timer after update setting. Otherwise, we can not get correct inf setting.
1452 // 2010/05/18 MH For SE series only now. Init GPIO detect time
1453 if(pDevice->RegUsbSS)
1454 {
1455 RT_TRACE(COMP_INIT, DBG_LOUD, (" call GpioDetectTimerStart8192CU\n"));
1456 GpioDetectTimerStart8192CU(Adapter); // Disable temporarily
1457 }
1458
1459 // 2010/08/23 MH According to Alfred's suggestion, we need to to prevent HW enter
1460 // suspend mode automatically.
1461 HwSuspendModeEnable92Cu(Adapter, _FALSE);
1462 #endif
1463
1464 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC31);
1465 rtw_hal_set_hwreg(padapter, HW_VAR_NAV_UPPER, (u8*)&NavUpper);
1466
1467 #ifdef CONFIG_XMIT_ACK
1468 //ack for xmit mgmt frames.
1469 rtw_write32(padapter, REG_FWHW_TXQ_CTRL, rtw_read32(padapter, REG_FWHW_TXQ_CTRL)|BIT(12));
1470 #endif //CONFIG_XMIT_ACK
1471
1472 // Enable MACTXEN/MACRXEN block
1473 u1bRegCR = rtw_read8(padapter, REG_CR);
1474 u1bRegCR |= (MACTXEN | MACRXEN);
1475 rtw_write8(padapter, REG_CR, u1bRegCR);
1476
1477 //_dbg_dump_macreg(Adapter);
1478
1479 exit:
1480 HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END);
1481
1482 DBG_871X("%s in %dms\n", __FUNCTION__, rtw_get_passing_time_ms(init_start_time));
1483
1484 #ifdef DBG_HAL_INIT_PROFILING
1485 hal_init_stages_timestamp[HAL_INIT_STAGES_END]=rtw_get_current_time();
1486
1487 for(hal_init_profiling_i=0;hal_init_profiling_i<HAL_INIT_STAGES_NUM-1;hal_init_profiling_i++) {
1488 DBG_871X("DBG_HAL_INIT_PROFILING: %35s, %u, %5u, %5u\n"
1489 , hal_init_stages_str[hal_init_profiling_i]
1490 , hal_init_stages_timestamp[hal_init_profiling_i]
1491 , (hal_init_stages_timestamp[hal_init_profiling_i+1]-hal_init_stages_timestamp[hal_init_profiling_i])
1492 , rtw_get_time_interval_ms(hal_init_stages_timestamp[hal_init_profiling_i], hal_init_stages_timestamp[hal_init_profiling_i+1])
1493 );
1494 }
1495 #endif
1496
1497 _func_exit_;
1498
1499 return status;
1500 }
1501
1502
1503 static VOID
_DisableGPIO(IN PADAPTER Adapter)1504 _DisableGPIO(
1505 IN PADAPTER Adapter
1506 )
1507 {
1508 /***************************************
1509 j. GPIO_PIN_CTRL 0x44[31:0]=0x000 //
1510 k. Value = GPIO_PIN_CTRL[7:0]
1511 l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); //write external PIN level
1512 m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
1513 n. LEDCFG 0x4C[15:0] = 0x8080
1514 ***************************************/
1515 u8 value8;
1516 u16 value16;
1517 u32 value32;
1518
1519 //1. Disable GPIO[7:0]
1520 rtw_write16(Adapter, REG_GPIO_PIN_CTRL+2, 0x0000);
1521 value32 = rtw_read32(Adapter, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
1522 value8 = (u8) (value32&0x000000FF);
1523 value32 |= ((value8<<8) | 0x00FF0000);
1524 rtw_write32(Adapter, REG_GPIO_PIN_CTRL, value32);
1525
1526 //2. Disable GPIO[10:8]
1527 rtw_write8(Adapter, REG_GPIO_MUXCFG+3, 0x00);
1528 value16 = rtw_read16(Adapter, REG_GPIO_MUXCFG+2) & 0xFF0F;
1529 value8 = (u8) (value16&0x000F);
1530 value16 |= ((value8<<4) | 0x0780);
1531 rtw_write16(Adapter, REG_GPIO_MUXCFG+2, value16);
1532
1533 //3. Disable LED0 & 1
1534 rtw_write16(Adapter, REG_LEDCFG0, 0x8080);
1535
1536 //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Disable GPIO and LED.\n"));
1537
1538 } //end of _DisableGPIO()
1539
1540 static VOID
_ResetFWDownloadRegister(IN PADAPTER Adapter)1541 _ResetFWDownloadRegister(
1542 IN PADAPTER Adapter
1543 )
1544 {
1545 u32 value32;
1546
1547 value32 = rtw_read32(Adapter, REG_MCUFWDL);
1548 value32 &= ~(MCUFWDL_EN | MCUFWDL_RDY);
1549 rtw_write32(Adapter, REG_MCUFWDL, value32);
1550 //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reset FW download register.\n"));
1551 }
1552
1553 static VOID
_ResetBB(IN PADAPTER Adapter)1554 _ResetBB(
1555 IN PADAPTER Adapter
1556 )
1557 {
1558 u16 value16;
1559
1560 //reset BB
1561 value16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
1562 value16 &= ~(FEN_BBRSTB | FEN_BB_GLB_RSTn);
1563 rtw_write16(Adapter, REG_SYS_FUNC_EN, value16);
1564 //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reset BB.\n"));
1565 }
1566
1567 static VOID
_ResetMCU(IN PADAPTER Adapter)1568 _ResetMCU(
1569 IN PADAPTER Adapter
1570 )
1571 {
1572 u16 value16;
1573
1574 // reset MCU
1575 value16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
1576 value16 &= ~FEN_CPUEN;
1577 rtw_write16(Adapter, REG_SYS_FUNC_EN, value16);
1578 //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reset MCU.\n"));
1579 }
1580
1581 static VOID
_DisableMAC_AFE_PLL(IN PADAPTER Adapter)1582 _DisableMAC_AFE_PLL(
1583 IN PADAPTER Adapter
1584 )
1585 {
1586 u32 value32;
1587
1588 //disable MAC/ AFE PLL
1589 value32 = rtw_read32(Adapter, REG_APS_FSMCO);
1590 value32 |= APDM_MAC;
1591 rtw_write32(Adapter, REG_APS_FSMCO, value32);
1592
1593 value32 |= APFM_OFF;
1594 rtw_write32(Adapter, REG_APS_FSMCO, value32);
1595 //RT_TRACE(COMP_INIT, DBG_LOUD, ("Disable MAC, AFE PLL.\n"));
1596 }
1597
1598 static VOID
_AutoPowerDownToHostOff(IN PADAPTER Adapter)1599 _AutoPowerDownToHostOff(
1600 IN PADAPTER Adapter
1601 )
1602 {
1603 u32 value32;
1604 rtw_write8(Adapter, REG_SPS0_CTRL, 0x22);
1605
1606 value32 = rtw_read32(Adapter, REG_APS_FSMCO);
1607
1608 value32 |= APDM_HOST;//card disable
1609 rtw_write32(Adapter, REG_APS_FSMCO, value32);
1610 //RT_TRACE(COMP_INIT, DBG_LOUD, ("Auto Power Down to Host-off state.\n"));
1611
1612 // set USB suspend
1613 value32 = rtw_read32(Adapter, REG_APS_FSMCO);
1614 value32 &= ~AFSM_PCIE;
1615 rtw_write32(Adapter, REG_APS_FSMCO, value32);
1616
1617 }
1618
1619 static VOID
_SetUsbSuspend(IN PADAPTER Adapter)1620 _SetUsbSuspend(
1621 IN PADAPTER Adapter
1622 )
1623 {
1624 u32 value32;
1625
1626 value32 = rtw_read32(Adapter, REG_APS_FSMCO);
1627
1628 // set USB suspend
1629 value32 |= AFSM_HSUS;
1630 rtw_write32(Adapter, REG_APS_FSMCO, value32);
1631
1632 //RT_ASSERT(0 == (rtw_read32(Adapter, REG_APS_FSMCO) & BIT(12)),(""));
1633 //RT_TRACE(COMP_INIT, DBG_LOUD, ("Set USB suspend.\n"));
1634
1635 }
1636
1637 static VOID
_DisableRFAFEAndResetBB(IN PADAPTER Adapter)1638 _DisableRFAFEAndResetBB(
1639 IN PADAPTER Adapter
1640 )
1641 {
1642 /**************************************
1643 a. TXPAUSE 0x522[7:0] = 0xFF //Pause MAC TX queue
1644 b. RF path 0 offset 0x00 = 0x00 // disable RF
1645 c. APSD_CTRL 0x600[7:0] = 0x40
1646 d. SYS_FUNC_EN 0x02[7:0] = 0x16 //reset BB state machine
1647 e. SYS_FUNC_EN 0x02[7:0] = 0x14 //reset BB state machine
1648 ***************************************/
1649 u8 eRFPath = 0,value8 = 0;
1650 rtw_write8(Adapter, REG_TXPAUSE, 0xFF);
1651 PHY_SetRFReg(Adapter, eRFPath, 0x0, bMaskByte0, 0x0);
1652
1653 value8 |= APSDOFF;
1654 rtw_write8(Adapter, REG_APSD_CTRL, value8);//0x40
1655
1656 value8 = 0 ;
1657 value8 |=( FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
1658 rtw_write8(Adapter, REG_SYS_FUNC_EN,value8 );//0x16
1659
1660 value8 &=( ~FEN_BB_GLB_RSTn );
1661 rtw_write8(Adapter, REG_SYS_FUNC_EN, value8); //0x14
1662
1663 //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> RF off and reset BB.\n"));
1664 }
1665
1666 static VOID
_ResetDigitalProcedure1(IN PADAPTER Adapter,IN BOOLEAN bWithoutHWSM)1667 _ResetDigitalProcedure1(
1668 IN PADAPTER Adapter,
1669 IN BOOLEAN bWithoutHWSM
1670 )
1671 {
1672
1673 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1674
1675 if(pHalData->FirmwareVersion <= 0x20){
1676 #if 0
1677 /*****************************
1678 f. SYS_FUNC_EN 0x03[7:0]=0x54 // reset MAC register, DCORE
1679 g. MCUFWDL 0x80[7:0]=0 // reset MCU ready status
1680 ******************************/
1681 u4Byte value32 = 0;
1682 PlatformIOWrite1Byte(Adapter, REG_SYS_FUNC_EN+1, 0x54);
1683 PlatformIOWrite1Byte(Adapter, REG_MCUFWDL, 0);
1684 #else
1685 /*****************************
1686 f. MCUFWDL 0x80[7:0]=0 // reset MCU ready status
1687 g. SYS_FUNC_EN 0x02[10]= 0 // reset MCU register, (8051 reset)
1688 h. SYS_FUNC_EN 0x02[15-12]= 5 // reset MAC register, DCORE
1689 i. SYS_FUNC_EN 0x02[10]= 1 // enable MCU register, (8051 enable)
1690 ******************************/
1691 u16 valu16 = 0;
1692 rtw_write8(Adapter, REG_MCUFWDL, 0);
1693
1694 valu16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
1695 rtw_write16(Adapter, REG_SYS_FUNC_EN, (valu16 & (~FEN_CPUEN)));//reset MCU ,8051
1696
1697 valu16 = rtw_read16(Adapter, REG_SYS_FUNC_EN)&0x0FFF;
1698 rtw_write16(Adapter, REG_SYS_FUNC_EN, (valu16 |(FEN_HWPDN|FEN_ELDR)));//reset MAC
1699
1700 #ifdef DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE
1701 {
1702 u8 val;
1703 if( (val=rtw_read8(Adapter, REG_MCUFWDL)))
1704 DBG_871X("DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE %s:%d REG_MCUFWDL:0x%02x\n", __FUNCTION__, __LINE__, val);
1705 }
1706 #endif
1707
1708
1709 valu16 = rtw_read16(Adapter, REG_SYS_FUNC_EN);
1710 rtw_write16(Adapter, REG_SYS_FUNC_EN, (valu16 | FEN_CPUEN));//enable MCU ,8051
1711
1712
1713 #endif
1714 }
1715 else{
1716 u8 retry_cnts = 0;
1717
1718 if(rtw_read8(Adapter, REG_MCUFWDL) & BIT1)
1719 { //IF fw in RAM code, do reset
1720
1721 rtw_write8(Adapter, REG_MCUFWDL, 0);
1722 if(Adapter->bFWReady){
1723 // 2010/08/25 MH Accordign to RD alfred's suggestion, we need to disable other
1724 // HRCV INT to influence 8051 reset.
1725 rtw_write8(Adapter, REG_FWIMR, 0x20);
1726
1727 rtw_write8(Adapter, REG_HMETFR+3, 0x20);//8051 reset by self
1728
1729 while( (retry_cnts++ <100) && (FEN_CPUEN &rtw_read16(Adapter, REG_SYS_FUNC_EN)))
1730 {
1731 rtw_udelay_os(50);//PlatformStallExecution(50);//us
1732 }
1733
1734 if(retry_cnts >= 100){
1735 DBG_8192C("%s #####=> 8051 reset failed!.........................\n", __FUNCTION__);
1736 // if 8051 reset fail we trigger GPIO 0 for LA
1737 //PlatformEFIOWrite4Byte( Adapter,
1738 // REG_GPIO_PIN_CTRL,
1739 // 0x00010100);
1740 // 2010/08/31 MH According to Filen's info, if 8051 reset fail, reset MAC directly.
1741 rtw_write8(Adapter, REG_SYS_FUNC_EN+1, 0x50); //Reset MAC and Enable 8051
1742 rtw_mdelay_os(10);
1743 }
1744 else {
1745 //DBG_871X("%s =====> 8051 reset success (%d) .\n", __FUNCTION__, retry_cnts);
1746 }
1747 }
1748 else {
1749 DBG_871X("%s =====> 8051 in RAM but !Adapter->bFWReady\n", __FUNCTION__);
1750 }
1751 }
1752 else{
1753 //DBG_871X("%s =====> 8051 in ROM.\n", __FUNCTION__);
1754 }
1755
1756 #ifdef DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE
1757 {
1758 u8 val;
1759 if( (val=rtw_read8(Adapter, REG_MCUFWDL)))
1760 DBG_871X("DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE %s:%d REG_MCUFWDL:0x%02x\n", __FUNCTION__, __LINE__, val);
1761 }
1762 #endif
1763
1764 rtw_write8(Adapter, REG_SYS_FUNC_EN+1, 0x54); //Reset MAC and Enable 8051
1765 }
1766
1767 // Clear rpwm value for initial toggle bit trigger.
1768 rtw_write8(Adapter, REG_USB_HRPWM, 0x00);
1769
1770 if(bWithoutHWSM){
1771 /*****************************
1772 Without HW auto state machine
1773 g. SYS_CLKR 0x08[15:0] = 0x30A3 //disable MAC clock
1774 h. AFE_PLL_CTRL 0x28[7:0] = 0x80 //disable AFE PLL
1775 i. AFE_XTAL_CTRL 0x24[15:0] = 0x880F //gated AFE DIG_CLOCK
1776 j. SYS_ISO_CTRL 0x00[7:0] = 0xF9 // isolated digital to PON
1777 ******************************/
1778 //rtw_write16(Adapter, REG_SYS_CLKR, 0x30A3);
1779 rtw_write16(Adapter, REG_SYS_CLKR, 0x70A3);//modify to 0x70A3 by Scott.
1780 rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x80);
1781 rtw_write16(Adapter, REG_AFE_XTAL_CTRL, 0x880F);
1782 rtw_write8(Adapter, REG_SYS_ISO_CTRL, 0xF9);
1783 }
1784 else
1785 {
1786 // Disable all RF/BB power
1787 rtw_write8(Adapter, REG_RF_CTRL, 0x00);
1788 }
1789 //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Reset Digital.\n"));
1790
1791 }
1792
1793 static VOID
_ResetDigitalProcedure2(IN PADAPTER Adapter)1794 _ResetDigitalProcedure2(
1795 IN PADAPTER Adapter
1796 )
1797 {
1798 /*****************************
1799 k. SYS_FUNC_EN 0x03[7:0] = 0x44 // disable ELDR runction
1800 l. SYS_CLKR 0x08[15:0] = 0x3083 // disable ELDR clock
1801 m. SYS_ISO_CTRL 0x01[7:0] = 0x83 // isolated ELDR to PON
1802 ******************************/
1803 //rtw_write8(Adapter, REG_SYS_FUNC_EN+1, 0x44);//marked by Scott.
1804 //rtw_write16(Adapter, REG_SYS_CLKR, 0x3083);
1805 //rtw_write8(Adapter, REG_SYS_ISO_CTRL+1, 0x83);
1806
1807 rtw_write16(Adapter, REG_SYS_CLKR, 0x70a3); //modify to 0x70a3 by Scott.
1808 rtw_write8(Adapter, REG_SYS_ISO_CTRL+1, 0x82); //modify to 0x82 by Scott.
1809 }
1810
1811 static VOID
_DisableAnalog(IN PADAPTER Adapter,IN BOOLEAN bWithoutHWSM)1812 _DisableAnalog(
1813 IN PADAPTER Adapter,
1814 IN BOOLEAN bWithoutHWSM
1815 )
1816 {
1817 u16 value16 = 0;
1818 u8 value8=0;
1819 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
1820
1821 if(bWithoutHWSM){
1822 /*****************************
1823 n. LDOA15_CTRL 0x20[7:0] = 0x04 // disable A15 power
1824 o. LDOV12D_CTRL 0x21[7:0] = 0x54 // disable digital core power
1825 r. When driver call disable, the ASIC will turn off remaining clock automatically
1826 ******************************/
1827
1828 rtw_write8(Adapter, REG_LDOA15_CTRL, 0x04);
1829 //PlatformIOWrite1Byte(Adapter, REG_LDOV12D_CTRL, 0x54);
1830
1831 value8 = rtw_read8(Adapter, REG_LDOV12D_CTRL);
1832 value8 &= (~LDV12_EN);
1833 rtw_write8(Adapter, REG_LDOV12D_CTRL, value8);
1834 //RT_TRACE(COMP_INIT, DBG_LOUD, (" REG_LDOV12D_CTRL Reg0x21:0x%02x.\n",value8));
1835 }
1836
1837 /*****************************
1838 h. SPS0_CTRL 0x11[7:0] = 0x23 //enter PFM mode
1839 i. APS_FSMCO 0x04[15:0] = 0x4802 // set USB suspend
1840 ******************************/
1841
1842
1843 value8 = 0x23;
1844
1845 rtw_write8(Adapter, REG_SPS0_CTRL, value8);
1846
1847
1848 if(bWithoutHWSM)
1849 {
1850 //value16 |= (APDM_HOST | /*AFSM_HSUS |*/PFM_ALDN);
1851 // 2010/08/31 According to Filen description, we need to use HW to shut down 8051 automatically.
1852 // Becasue suspend operatione need the asistance of 8051 to wait for 3ms.
1853 value16 |= (APDM_HOST | AFSM_HSUS |PFM_ALDN);
1854 }
1855 else
1856 {
1857 value16 |= (APDM_HOST | AFSM_HSUS |PFM_ALDN);
1858 }
1859
1860 rtw_write16(Adapter, REG_APS_FSMCO,value16 );//0x4802
1861
1862 rtw_write8(Adapter, REG_RSV_CTRL, 0x0e);
1863
1864 #if 0
1865 //tynli_test for suspend mode.
1866 if(!bWithoutHWSM){
1867 rtw_write8(Adapter, 0xfe10, 0x19);
1868 }
1869 #endif
1870
1871 //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Disable Analog Reg0x04:0x%04x.\n",value16));
1872 }
1873
rtl8723bu_hw_power_down(_adapter * padapter)1874 static void rtl8723bu_hw_power_down(_adapter *padapter)
1875 {
1876 u8 u1bTmp;
1877
1878 DBG_8192C("PowerDownRTL8723U\n");
1879
1880
1881 // 1. Run Card Disable Flow
1882 // Done before this function call.
1883
1884 // 2. 0x04[16] = 0 // reset WLON
1885 u1bTmp = rtw_read8(padapter, REG_APS_FSMCO+2);
1886 rtw_write8(padapter, REG_APS_FSMCO+2, (u1bTmp&(~BIT0)));
1887
1888 // 3. 0x04[12:11] = 2b'11 // enable suspend
1889 // Done before this function call.
1890
1891 // 4. 0x04[15] = 1 // enable PDN
1892 u1bTmp = rtw_read8(padapter, REG_APS_FSMCO+1);
1893 rtw_write8(padapter, REG_APS_FSMCO+1, (u1bTmp|BIT7));
1894 }
1895
1896 //
1897 // Description: RTL8723e card disable power sequence v003 which suggested by Scott.
1898 // First created by tynli. 2011.01.28.
1899 //
1900 VOID
CardDisableRTL8723U(PADAPTER Adapter)1901 CardDisableRTL8723U(
1902 PADAPTER Adapter
1903 )
1904 {
1905 u8 u1bTmp;
1906
1907 rtw_hal_get_hwreg(Adapter, HW_VAR_APFM_ON_MAC, &u1bTmp);
1908 DBG_8192C(FUNC_ADPT_FMT ": bMacPwrCtrlOn=%d\n", FUNC_ADPT_ARG(Adapter), u1bTmp);
1909 if (u1bTmp == _FALSE)
1910 return;
1911 u1bTmp = _FALSE;
1912 rtw_hal_set_hwreg(Adapter, HW_VAR_APFM_ON_MAC, &u1bTmp);
1913
1914 //Stop Tx Report Timer. 0x4EC[Bit1]=b'0
1915 u1bTmp = rtw_read8(Adapter, REG_TX_RPT_CTRL);
1916 rtw_write8(Adapter, REG_TX_RPT_CTRL, u1bTmp&(~BIT1));
1917
1918 // stop rx
1919 rtw_write8(Adapter, REG_CR_8723B, 0x0);
1920
1921 // 1. Run LPS WL RFOFF flow
1922 HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, rtl8723B_enter_lps_flow);
1923
1924 if((rtw_read8(Adapter, REG_MCUFWDL_8723B)&BIT7) &&
1925 Adapter->bFWReady) //8051 RAM code
1926 {
1927 rtl8723b_FirmwareSelfReset(Adapter);
1928 }
1929
1930 // Reset MCU. Suggested by Filen. 2011.01.26. by tynli.
1931 u1bTmp = rtw_read8(Adapter, REG_SYS_FUNC_EN_8723B+1);
1932 rtw_write8(Adapter, REG_SYS_FUNC_EN_8723B+1, (u1bTmp&(~BIT2)));
1933
1934 // MCUFWDL 0x80[1:0]=0 // reset MCU ready status
1935 rtw_write8(Adapter, REG_MCUFWDL_8723B, 0x00);
1936
1937 // Card disable power action flow
1938 HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, rtl8723B_card_disable_flow);
1939
1940 Adapter->bFWReady = _FALSE;
1941 }
1942
1943
rtl8723bu_hal_deinit(PADAPTER padapter)1944 u32 rtl8723bu_hal_deinit(PADAPTER padapter)
1945 {
1946 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1947
1948
1949 DBG_8192C("==> %s\n", __FUNCTION__);
1950
1951
1952 // 2011/02/18 To Fix RU LNA power leakage problem. We need to execute below below in
1953 // Adapter init and halt sequence. Accordingto EEchou's opinion, we can enable the ability for all
1954 // IC. Accord to johnny's opinion, only RU need the support.
1955 rtw_hal_power_off(padapter);
1956
1957 return _SUCCESS;
1958 }
1959
1960
rtl8723bu_inirp_init(PADAPTER Adapter)1961 unsigned int rtl8723bu_inirp_init(PADAPTER Adapter)
1962 {
1963 u8 i;
1964 struct recv_buf *precvbuf;
1965 uint status;
1966 struct dvobj_priv *pdev= adapter_to_dvobj(Adapter);
1967 struct intf_hdl * pintfhdl=&Adapter->iopriv.intf;
1968 struct recv_priv *precvpriv = &(Adapter->recvpriv);
1969 u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
1970 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
1971 u32 (*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr);
1972 HAL_DATA_TYPE *pHalData=GET_HAL_DATA(Adapter);
1973 #endif //CONFIG_USB_INTERRUPT_IN_PIPE
1974
1975 _func_enter_;
1976
1977 _read_port = pintfhdl->io_ops._read_port;
1978
1979 status = _SUCCESS;
1980
1981 RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("===> usb_inirp_init \n"));
1982
1983 precvpriv->ff_hwaddr = RECV_BULK_IN_ADDR;
1984
1985 //issue Rx irp to receive data
1986 precvbuf = (struct recv_buf *)precvpriv->precv_buf;
1987 for(i=0; i<NR_RECVBUFF; i++)
1988 {
1989 if(_read_port(pintfhdl, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf) == _FALSE )
1990 {
1991 RT_TRACE(_module_hci_hal_init_c_,_drv_err_,("usb_rx_init: usb_read_port error \n"));
1992 status = _FAIL;
1993 goto exit;
1994 }
1995
1996 precvbuf++;
1997 precvpriv->free_recv_buf_queue_cnt--;
1998 }
1999
2000 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
2001 _read_interrupt = pintfhdl->io_ops._read_interrupt;
2002 if(_read_interrupt(pintfhdl, RECV_INT_IN_ADDR) == _FALSE )
2003 {
2004 RT_TRACE(_module_hci_hal_init_c_,_drv_err_,("usb_rx_init: usb_read_interrupt error \n"));
2005 status = _FAIL;
2006 }
2007 pHalData->IntrMask[0]=rtw_read32(Adapter, REG_USB_HIMR);
2008 MSG_8192C("pHalData->IntrMask = 0x%04x\n", pHalData->IntrMask[0]);
2009 pHalData->IntrMask[0]|=UHIMR_C2HCMD|UHIMR_CPWM;
2010 rtw_write32(Adapter, REG_USB_HIMR,pHalData->IntrMask[0]);
2011 #endif //CONFIG_USB_INTERRUPT_IN_PIPE
2012
2013 exit:
2014
2015 RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("<=== usb_inirp_init \n"));
2016
2017 _func_exit_;
2018
2019 return status;
2020
2021 }
2022
rtl8723bu_inirp_deinit(PADAPTER Adapter)2023 unsigned int rtl8723bu_inirp_deinit(PADAPTER Adapter)
2024 {
2025 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
2026 u32 (*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr);
2027 HAL_DATA_TYPE *pHalData=GET_HAL_DATA(Adapter);
2028 #endif //CONFIG_USB_INTERRUPT_IN_PIPE
2029 RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("\n ===> usb_rx_deinit \n"));
2030
2031 rtw_read_port_cancel(Adapter);
2032 #ifdef CONFIG_USB_INTERRUPT_IN_PIPE
2033 pHalData->IntrMask[0]=rtw_read32(Adapter, REG_USB_HIMR);
2034 MSG_8192C("%s pHalData->IntrMask = 0x%04x\n",__FUNCTION__, pHalData->IntrMask[0]);
2035 pHalData->IntrMask[0]=0x0;
2036 rtw_write32(Adapter, REG_USB_HIMR,pHalData->IntrMask[0]);
2037 RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("\n <=== usb_rx_deinit \n"));
2038 #endif //CONFIG_USB_INTERRUPT_IN_PIPE
2039 return _SUCCESS;
2040 }
2041
2042
2043 static u32
_GetChannelGroup(IN u32 channel)2044 _GetChannelGroup(
2045 IN u32 channel
2046 )
2047 {
2048 //RT_ASSERT((channel < 14), ("Channel %d no is supported!\n"));
2049
2050 if(channel < 3){ // Channel 1~3
2051 return 0;
2052 }
2053 else if(channel < 9){ // Channel 4~9
2054 return 1;
2055 }
2056
2057 return 2; // Channel 10~14
2058 }
2059
2060
2061 //-------------------------------------------------------------------
2062 //
2063 // EEPROM/EFUSE Content Parsing
2064 //
2065 //-------------------------------------------------------------------
2066 static VOID
_ReadLEDSetting(IN PADAPTER Adapter,IN u8 * PROMContent,IN BOOLEAN AutoloadFail)2067 _ReadLEDSetting(
2068 IN PADAPTER Adapter,
2069 IN u8* PROMContent,
2070 IN BOOLEAN AutoloadFail
2071 )
2072 {
2073 struct led_priv *pledpriv = &(Adapter->ledpriv);
2074 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2075
2076 #ifdef CONFIG_SW_LED
2077 pledpriv->bRegUseLed = _TRUE;
2078
2079 //
2080 // Led mode
2081 //
2082 switch(pHalData->CustomerID)
2083 {
2084 case RT_CID_DEFAULT:
2085 pledpriv->LedStrategy = SW_LED_MODE1;
2086 pledpriv->bRegUseLed = _TRUE;
2087 break;
2088
2089 case RT_CID_819x_HP:
2090 pledpriv->LedStrategy = SW_LED_MODE6;
2091 break;
2092
2093 default:
2094 pledpriv->LedStrategy = SW_LED_MODE1;
2095 break;
2096 }
2097
2098 pHalData->bLedOpenDrain = _TRUE;// Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16.
2099 #else // HW LED
2100 pledpriv->LedStrategy = HW_LED;
2101 #endif //CONFIG_SW_LED
2102 }
2103
2104 static VOID
_ReadRFSetting(IN PADAPTER Adapter,IN u8 * PROMContent,IN BOOLEAN AutoloadFail)2105 _ReadRFSetting(
2106 IN PADAPTER Adapter,
2107 IN u8* PROMContent,
2108 IN BOOLEAN AutoloadFail
2109 )
2110 {
2111 }
2112
2113 // Read HW power down mode selection
_ReadPSSetting(IN PADAPTER Adapter,IN u8 * PROMContent,IN u8 AutoloadFail)2114 static void _ReadPSSetting(IN PADAPTER Adapter,IN u8*PROMContent,IN u8 AutoloadFail)
2115 {
2116 struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(Adapter);
2117
2118 if(AutoloadFail){
2119 pwrctl->bHWPowerdown = _FALSE;
2120 pwrctl->bSupportRemoteWakeup = _FALSE;
2121 }
2122 else {
2123 //if(SUPPORT_HW_RADIO_DETECT(Adapter))
2124 pwrctl->bHWPwrPindetect = Adapter->registrypriv.hwpwrp_detect;
2125 //else
2126 //pwrctl->bHWPwrPindetect = _FALSE;//dongle not support new
2127
2128
2129 //hw power down mode selection , 0:rf-off / 1:power down
2130
2131 if(Adapter->registrypriv.hwpdn_mode==2)
2132 pwrctl->bHWPowerdown = (PROMContent[EEPROM_FEATURE_OPTION_8723B] & BIT4);
2133 else
2134 pwrctl->bHWPowerdown = Adapter->registrypriv.hwpdn_mode;
2135
2136 // decide hw if support remote wakeup function
2137 // if hw supported, 8051 (SIE) will generate WeakUP signal( D+/D- toggle) when autoresume
2138 pwrctl->bSupportRemoteWakeup = (PROMContent[EEPROM_USB_OPTIONAL_FUNCTION0] & BIT1)?_TRUE :_FALSE;
2139
2140 //if(SUPPORT_HW_RADIO_DETECT(Adapter))
2141 //Adapter->registrypriv.usbss_enable = pwrctl->bSupportRemoteWakeup ;
2142
2143 DBG_8192C("%s...bHWPwrPindetect(%x)-bHWPowerdown(%x) ,bSupportRemoteWakeup(%x)\n",__FUNCTION__,
2144 pwrctl->bHWPwrPindetect, pwrctl->bHWPowerdown, pwrctl->bSupportRemoteWakeup);
2145
2146 DBG_8192C("### PS params=> power_mgnt(%x),usbss_enable(%x) ###\n",Adapter->registrypriv.power_mgnt,Adapter->registrypriv.usbss_enable);
2147
2148 }
2149
2150 }
2151
2152
2153
2154
2155
2156
2157 VOID
Hal_EfuseParsePIDVID_8723BU(IN PADAPTER pAdapter,IN u8 * hwinfo,IN BOOLEAN AutoLoadFail)2158 Hal_EfuseParsePIDVID_8723BU(
2159 IN PADAPTER pAdapter,
2160 IN u8* hwinfo,
2161 IN BOOLEAN AutoLoadFail
2162 )
2163 {
2164 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
2165
2166 if(AutoLoadFail)
2167 {
2168 pHalData->EEPROMVID = 0;
2169 pHalData->EEPROMPID = 0;
2170 }
2171 else
2172 {
2173 // VID, PID
2174 pHalData->EEPROMVID = le16_to_cpu(*(u16*)&hwinfo[EEPROM_VID_8723BU]);
2175 pHalData->EEPROMPID = le16_to_cpu(*(u16*)&hwinfo[EEPROM_PID_8723BU]);
2176
2177 }
2178
2179 MSG_8192C("EEPROM VID = 0x%4x\n", pHalData->EEPROMVID);
2180 MSG_8192C("EEPROM PID = 0x%4x\n", pHalData->EEPROMPID);
2181 }
2182
2183 static VOID
InitAdapterVariablesByPROM_8723BU(IN PADAPTER padapter)2184 InitAdapterVariablesByPROM_8723BU(
2185 IN PADAPTER padapter
2186 )
2187 {
2188
2189 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
2190 u8* hwinfo = NULL;
2191
2192 if (sizeof(pHalData->efuse_eeprom_data) < HWSET_MAX_SIZE_8723B)
2193 DBG_871X("[WARNING] size of efuse_eeprom_data is less than HWSET_MAX_SIZE_8723B!\n");
2194
2195 hwinfo = pHalData->efuse_eeprom_data;
2196
2197 Hal_InitPGData(padapter, hwinfo);
2198
2199 Hal_EfuseParseIDCode(padapter, hwinfo);
2200 Hal_EfuseParsePIDVID_8723BU(padapter, hwinfo, pHalData->bautoload_fail_flag);
2201 Hal_EfuseParseEEPROMVer_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
2202 hal_config_macaddr(padapter, pHalData->bautoload_fail_flag);
2203 Hal_EfuseParseTxPowerInfo_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
2204 Hal_EfuseParseBoardType_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
2205
2206 Hal_EfuseParseBTCoexistInfo_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
2207
2208 Hal_EfuseParseChnlPlan_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
2209 Hal_EfuseParseThermalMeter_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
2210 // _ReadLEDSetting(Adapter, PROMContent, pHalData->bautoload_fail_flag);
2211 // _ReadRFSetting(Adapter, PROMContent, pHalData->bautoload_fail_flag);
2212 // _ReadPSSetting(Adapter, PROMContent, pHalData->bautoload_fail_flag);
2213 Hal_EfuseParseAntennaDiversity_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
2214
2215 Hal_EfuseParseEEPROMVer_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
2216 Hal_EfuseParseCustomerID_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
2217 // Hal_EfuseParseRateIndicationOption(padapter, hwinfo, pHalData->bautoload_fail_flag);
2218 Hal_EfuseParseXtal_8723B(padapter, hwinfo, pHalData->bautoload_fail_flag);
2219 //
2220 // The following part initialize some vars by PG info.
2221 //
2222
2223 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
2224 Hal_DetectWoWMode(padapter);
2225 #endif
2226
2227 //hal_CustomizedBehavior_8723U(Adapter);
2228
2229 // Adapter->bDongle = (PROMContent[EEPROM_EASY_REPLACEMENT] == 1)? 0: 1;
2230 DBG_8192C("%s(): REPLACEMENT = %x\n",__FUNCTION__,padapter->bDongle);
2231 }
2232
_ReadPROMContent(IN PADAPTER Adapter)2233 static void _ReadPROMContent(
2234 IN PADAPTER Adapter
2235 )
2236 {
2237 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
2238
2239 u8 eeValue;
2240 u32 i;
2241 u16 value16;
2242
2243 eeValue = rtw_read8(Adapter, REG_9346CR);
2244 // To check system boot selection.
2245 pHalData->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? _TRUE : _FALSE;
2246 pHalData->bautoload_fail_flag = (eeValue & EEPROM_EN) ? _FALSE : _TRUE;
2247
2248
2249 DBG_8192C("Boot from %s, Autoload %s !\n", (pHalData->EepromOrEfuse ? "EEPROM" : "EFUSE"),
2250 (pHalData->bautoload_fail_flag ? "Fail" : "OK") );
2251
2252
2253 InitAdapterVariablesByPROM_8723BU(Adapter);
2254 }
2255
2256 static VOID
_ReadRFType(IN PADAPTER Adapter)2257 _ReadRFType(
2258 IN PADAPTER Adapter
2259 )
2260 {
2261 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2262
2263 #if DISABLE_BB_RF
2264 pHalData->rf_chip = RF_PSEUDO_11N;
2265 #else
2266 pHalData->rf_chip = RF_6052;
2267 #endif
2268 }
2269
2270
2271
2272 //
2273 // Description:
2274 // We should set Efuse cell selection to WiFi cell in default.
2275 //
2276 // Assumption:
2277 // PASSIVE_LEVEL
2278 //
2279 // Added by Roger, 2010.11.23.
2280 //
2281 void
hal_EfuseCellSel(IN PADAPTER Adapter)2282 hal_EfuseCellSel(
2283 IN PADAPTER Adapter
2284 )
2285 {
2286 u32 value32;
2287
2288 value32 = rtw_read32(Adapter, EFUSE_TEST);
2289 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
2290 rtw_write32(Adapter, EFUSE_TEST, value32);
2291 }
2292
ReadAdapterInfo8723BU(PADAPTER Adapter)2293 static void ReadAdapterInfo8723BU(PADAPTER Adapter)
2294 {
2295 /* Read EEPROM size before call any EEPROM function */
2296 Adapter->EepromAddressSize = GetEEPROMSize8723B(Adapter);
2297
2298 //Efuse_InitSomeVar(Adapter);
2299
2300 hal_EfuseCellSel(Adapter);
2301
2302 _ReadRFType(Adapter);//rf_chip -> _InitRFType()
2303 _ReadPROMContent(Adapter);
2304 }
2305
2306 #define GPIO_DEBUG_PORT_NUM 0
rtl8723bu_trigger_gpio_0(_adapter * padapter)2307 static void rtl8723bu_trigger_gpio_0(_adapter *padapter)
2308 {
2309
2310 u32 gpioctrl;
2311 DBG_871X("==> trigger_gpio_0...\n");
2312 rtw_write16_async(padapter,REG_GPIO_PIN_CTRL,0);
2313 rtw_write8_async(padapter,REG_GPIO_PIN_CTRL+2,0xFF);
2314 gpioctrl = (BIT(GPIO_DEBUG_PORT_NUM)<<24 )|(BIT(GPIO_DEBUG_PORT_NUM)<<16);
2315 rtw_write32_async(padapter,REG_GPIO_PIN_CTRL,gpioctrl);
2316 gpioctrl |= (BIT(GPIO_DEBUG_PORT_NUM)<<8);
2317 rtw_write32_async(padapter,REG_GPIO_PIN_CTRL,gpioctrl);
2318 DBG_871X("<=== trigger_gpio_0...\n");
2319
2320 }
2321
2322 /*
2323 * If variable not handled here,
2324 * some variables will be processed in SetHwReg8723A()
2325 */
SetHwReg8723BU(PADAPTER Adapter,u8 variable,u8 * val)2326 void SetHwReg8723BU(PADAPTER Adapter, u8 variable, u8* val)
2327 {
2328 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
2329
2330 _func_enter_;
2331
2332 switch(variable)
2333 {
2334 case HW_VAR_RXDMA_AGG_PG_TH:
2335 #ifdef CONFIG_USB_RX_AGGREGATION
2336 {
2337 u8 threshold = *val;
2338 if (threshold == 0)
2339 threshold = pHalData->UsbRxAggPageCount;
2340 SetHwReg8723B(Adapter, HW_VAR_RXDMA_AGG_PG_TH, &threshold);
2341 }
2342 #endif
2343 break;
2344
2345 case HW_VAR_SET_RPWM:
2346 rtw_write8(Adapter, REG_USB_HRPWM, *val);
2347 break;
2348
2349 case HW_VAR_TRIGGER_GPIO_0:
2350 rtl8723bu_trigger_gpio_0(Adapter);
2351 break;
2352
2353 default:
2354 SetHwReg8723B(Adapter, variable, val);
2355 break;
2356 }
2357
2358 _func_exit_;
2359 }
2360
2361 /*
2362 * If variable not handled here,
2363 * some variables will be processed in GetHwReg8723A()
2364 */
GetHwReg8723BU(PADAPTER Adapter,u8 variable,u8 * val)2365 void GetHwReg8723BU(PADAPTER Adapter, u8 variable, u8* val)
2366 {
2367 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
2368
2369 _func_enter_;
2370
2371 switch (variable)
2372 {
2373 default:
2374 GetHwReg8723B(Adapter, variable, val);
2375 break;
2376 }
2377
2378 _func_exit_;
2379 }
2380
2381 //
2382 // Description:
2383 // Query setting of specified variable.
2384 //
2385 u8
GetHalDefVar8723BUsb(IN PADAPTER Adapter,IN HAL_DEF_VARIABLE eVariable,IN PVOID pValue)2386 GetHalDefVar8723BUsb(
2387 IN PADAPTER Adapter,
2388 IN HAL_DEF_VARIABLE eVariable,
2389 IN PVOID pValue
2390 )
2391 {
2392 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2393 u8 bResult = _SUCCESS;
2394
2395 switch(eVariable)
2396 {
2397 case HAL_DEF_IS_SUPPORT_ANT_DIV:
2398 #ifdef CONFIG_ANTENNA_DIVERSITY
2399 *((u8 *)pValue) =_FALSE;
2400 #endif
2401 break;
2402
2403 case HAL_DEF_DRVINFO_SZ:
2404 *(( u32*)pValue) = DRVINFO_SZ;
2405 break;
2406 case HAL_DEF_MAX_RECVBUF_SZ:
2407 *(( u32*)pValue) = MAX_RECVBUF_SZ;
2408 break;
2409 case HAL_DEF_RX_PACKET_OFFSET:
2410 *(( u32*)pValue) = RXDESC_SIZE + DRVINFO_SZ;
2411 break;
2412 case HW_VAR_MAX_RX_AMPDU_FACTOR:
2413 *((HT_CAP_AMPDU_FACTOR*)pValue) = MAX_AMPDU_FACTOR_64K;
2414 break;
2415 default:
2416 bResult = GetHalDefVar8723B(Adapter, eVariable, pValue);
2417 break;
2418 }
2419
2420 return bResult;
2421 }
2422
2423
2424
2425
2426 //
2427 // Description:
2428 // Change default setting of specified variable.
2429 //
2430 u8
SetHalDefVar8723BUsb(IN PADAPTER Adapter,IN HAL_DEF_VARIABLE eVariable,IN PVOID pValue)2431 SetHalDefVar8723BUsb(
2432 IN PADAPTER Adapter,
2433 IN HAL_DEF_VARIABLE eVariable,
2434 IN PVOID pValue
2435 )
2436 {
2437 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
2438 u8 bResult = _SUCCESS;
2439
2440 switch(eVariable)
2441 {
2442 default:
2443 bResult = SetHalDefVar8723B(Adapter, eVariable, pValue);
2444 break;
2445 }
2446
2447 return bResult;
2448 }
2449
_update_response_rate(_adapter * padapter,unsigned int mask)2450 void _update_response_rate(_adapter *padapter,unsigned int mask)
2451 {
2452 u8 RateIndex = 0;
2453 // Set RRSR rate table.
2454 rtw_write8(padapter, REG_RRSR, mask&0xff);
2455 rtw_write8(padapter,REG_RRSR+1, (mask>>8)&0xff);
2456
2457 // Set RTS initial rate
2458 while(mask > 0x1)
2459 {
2460 mask = (mask>> 1);
2461 RateIndex++;
2462 }
2463 rtw_write8(padapter, REG_INIRTS_RATE_SEL, RateIndex);
2464 }
2465
rtl8723bu_init_default_value(PADAPTER padapter)2466 static void rtl8723bu_init_default_value(PADAPTER padapter)
2467 {
2468 rtl8723b_init_default_value(padapter);
2469 }
2470
rtl8723bu_ps_func(PADAPTER Adapter,HAL_INTF_PS_FUNC efunc_id,u8 * val)2471 static u8 rtl8723bu_ps_func(PADAPTER Adapter,HAL_INTF_PS_FUNC efunc_id, u8 *val)
2472 {
2473 u8 bResult = _TRUE;
2474 switch(efunc_id){
2475
2476 #if defined(CONFIG_AUTOSUSPEND) && defined(SUPPORT_HW_RFOFF_DETECTED)
2477 case HAL_USB_SELECT_SUSPEND:
2478 {
2479 u8 bfwpoll = *(( u8*)val);
2480 rtl8723b_set_FwSelectSuspend_cmd(Adapter,bfwpoll ,500);//note fw to support hw power down ping detect
2481 }
2482 break;
2483 #endif //CONFIG_AUTOSUSPEND && SUPPORT_HW_RFOFF_DETECTED
2484
2485 default:
2486 break;
2487 }
2488 return bResult;
2489 }
2490
rtl8723bu_set_hal_ops(_adapter * padapter)2491 void rtl8723bu_set_hal_ops(_adapter * padapter)
2492 {
2493 struct hal_ops *pHalFunc = &padapter->HalFunc;
2494
2495 _func_enter_;
2496
2497 rtl8723b_set_hal_ops(pHalFunc);
2498
2499 pHalFunc->hal_power_on = &_InitPowerOn_8723BU;
2500 pHalFunc->hal_power_off = &CardDisableRTL8723U;
2501
2502 pHalFunc->hal_init = &rtl8723bu_hal_init;
2503 pHalFunc->hal_deinit = &rtl8723bu_hal_deinit;
2504
2505 pHalFunc->inirp_init = &rtl8723bu_inirp_init;
2506 pHalFunc->inirp_deinit = &rtl8723bu_inirp_deinit;
2507
2508 pHalFunc->init_xmit_priv = &rtl8723bu_init_xmit_priv;
2509 pHalFunc->free_xmit_priv = &rtl8723bu_free_xmit_priv;
2510
2511 pHalFunc->init_recv_priv = &rtl8723bu_init_recv_priv;
2512 pHalFunc->free_recv_priv = &rtl8723bu_free_recv_priv;
2513 #ifdef CONFIG_SW_LED
2514 pHalFunc->InitSwLeds = &rtl8723bu_InitSwLeds;
2515 pHalFunc->DeInitSwLeds = &rtl8723bu_DeInitSwLeds;
2516 #else //case of hw led or no led
2517 pHalFunc->InitSwLeds = NULL;
2518 pHalFunc->DeInitSwLeds = NULL;
2519 #endif//CONFIG_SW_LED
2520
2521 pHalFunc->init_default_value = &rtl8723b_init_default_value;
2522 pHalFunc->intf_chip_configure = &rtl8723bu_interface_configure;
2523 pHalFunc->read_adapter_info = &ReadAdapterInfo8723BU;
2524
2525 pHalFunc->SetHwRegHandler = &SetHwReg8723BU;
2526 pHalFunc->GetHwRegHandler = &GetHwReg8723BU;
2527 pHalFunc->GetHalDefVarHandler = &GetHalDefVar8723BUsb;
2528 pHalFunc->SetHalDefVarHandler = &SetHalDefVar8723BUsb;
2529
2530 pHalFunc->hal_xmit = &rtl8723bu_hal_xmit;
2531 pHalFunc->mgnt_xmit = &rtl8723bu_mgnt_xmit;
2532 pHalFunc->hal_xmitframe_enqueue = &rtl8723bu_hal_xmitframe_enqueue;
2533
2534 #ifdef CONFIG_HOSTAPD_MLME
2535 pHalFunc->hostap_mgnt_xmit_entry = &rtl8723bu_hostap_mgnt_xmit_entry;
2536 #endif
2537 pHalFunc->interface_ps_func = &rtl8723bu_ps_func;
2538
2539 #ifdef CONFIG_XMIT_THREAD_MODE
2540 pHalFunc->xmit_thread_handler = &rtl8723bu_xmit_buf_handler;
2541 #endif
2542 #ifdef CONFIG_SUPPORT_USB_INT
2543 pHalFunc->interrupt_handler = interrupt_handler_8723bu;
2544 #endif
2545
2546 _func_exit_;
2547 }
2548
2549