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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// @file drvHVD.h 98 /// @brief HVD Driver Interface 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _DRV_HVD_DEF_H_ 103 #define _DRV_HVD_DEF_H_ 104 105 #include "drvHVD_Common.h" 106 107 //------------------------------------------------------------------------------------------------- 108 // Driver Capability 109 //------------------------------------------------------------------------------------------------- 110 111 // HW capability 112 #define HVD_HW_SVD 1 113 #define HVD_HW_HVD 2 114 #if defined(CHIP_T2) 115 #define HVD_HW_VERSION HVD_HW_SVD 116 #else 117 #define HVD_HW_VERSION HVD_HW_HVD 118 #endif 119 120 //------------------------------------------------------------------------------------------------- 121 // Macro and Define 122 //------------------------------------------------------------------------------------------------- 123 // Feature switch 124 #if defined(UDMA_FPGA_ENVI) 125 #define HVD_ENABLE_MUTEX_PROTECT 0 126 #define HVD_ENABLE_MIU_RST_PROTECT 0 127 #define HVD_ENABLE_AUTO_SET_REG_BASE 0 128 #define HVD_ENABLE_MSOS_SYSTEM_CALL 0 129 #define HVD_ENABLE_PATCH_ISFRAMERDY 0 130 #define HVD_ENABLE_STOP_ACCESS_OVER_256 1 131 #define HVD_ENABLE_AUTO_AVI_NULL_PACKET 0 132 #define HVD_ENABLE_MSOS_MIU1_BASE 0 133 #define HVD_ENABLE_BDMA_2_BITSTREAMBUF 0 134 #define HVD_ENABLE_EMBEDDED_FW_BINARY 1 135 #define HVD_ENABLE_BDMA_FW_FLASH_2_SDRAM 0 136 #define HVD_ENABLE_CHECK_STATE_BEFORE_SET_CMD 0 137 #define HVD_ENABLE_WAIT_CMD_FINISHED 0 138 #define HVD_ENABLE_TIME_MEASURE 0 139 #define HVD_ENABLE_RV_FEATURE 0 140 #elif defined(REDLION_LINUX_KERNEL_ENVI) 141 #define HVD_ENABLE_MUTEX_PROTECT 0 142 #define HVD_ENABLE_MIU_RST_PROTECT 1 143 #define HVD_ENABLE_AUTO_SET_REG_BASE 0 144 #define HVD_ENABLE_MSOS_SYSTEM_CALL 0 145 #define HVD_ENABLE_PATCH_ISFRAMERDY 0 146 #define HVD_ENABLE_STOP_ACCESS_OVER_256 0 147 #define HVD_ENABLE_AUTO_AVI_NULL_PACKET 0 148 #define HVD_ENABLE_MSOS_MIU1_BASE 0 149 #define HVD_ENABLE_BDMA_2_BITSTREAMBUF 0 150 #define HVD_ENABLE_EMBEDDED_FW_BINARY 1 151 #define HVD_ENABLE_BDMA_FW_FLASH_2_SDRAM 0 152 #define HVD_ENABLE_CHECK_STATE_BEFORE_SET_CMD 0 153 #define HVD_ENABLE_WAIT_CMD_FINISHED 0 154 #define HVD_ENABLE_TIME_MEASURE 0 155 #define HVD_ENABLE_REINIT_FAILED 1 156 #define HVD_ENABLE_RV_FEATURE 0 157 #else 158 #define HVD_ENABLE_MUTEX_PROTECT 1 159 #define HVD_ENABLE_MIU_RST_PROTECT 1 160 #if 1//defined( MSOS_TYPE_LINUX) 161 #define HVD_ENABLE_AUTO_SET_REG_BASE 1 162 #else 163 #define HVD_ENABLE_AUTO_SET_REG_BASE 0 164 #endif 165 #if defined( MSOS_TYPE_LINUX) || defined( MSOS_TYPE_ECOS) //|| defined( MSOS_TYPE_NOS) 166 #define HVD_ENABLE_PATCH_ISFRAMERDY 0 167 #define HVD_ENABLE_MSOS_SYSTEM_CALL 1 168 #else 169 #define HVD_ENABLE_PATCH_ISFRAMERDY 1 170 #define HVD_ENABLE_MSOS_SYSTEM_CALL 1 171 #endif 172 #if defined( MSOS_TYPE_NOS) && (defined( CHIP_T3 ) || defined( CHIP_T8 ) || defined(CHIP_J2)) 173 #define HVD_ENABLE_STOP_ACCESS_OVER_256 1 174 #define HVD_ENABLE_BDMA_2_BITSTREAMBUF 1 175 #else 176 #define HVD_ENABLE_STOP_ACCESS_OVER_256 0 177 #define HVD_ENABLE_BDMA_2_BITSTREAMBUF 0 178 #endif 179 180 #define HVD_ENABLE_AUTO_AVI_NULL_PACKET 1 181 182 #if defined(CHIP_JANUS) 183 #define HVD_ENABLE_MSOS_MIU1_BASE 0 184 #else 185 #define HVD_ENABLE_MSOS_MIU1_BASE 1 186 #endif 187 188 #if defined( FW_EXTERNAL_BIN ) 189 #define HVD_ENABLE_EMBEDDED_FW_BINARY 0 190 #define HVD_ENABLE_BDMA_FW_FLASH_2_SDRAM 1 191 #else // defined( FW_EMBEDDED_ASC ) 192 #define HVD_ENABLE_EMBEDDED_FW_BINARY 1 193 #define HVD_ENABLE_BDMA_FW_FLASH_2_SDRAM 0 194 #endif 195 196 #define HVD_ENABLE_CHECK_STATE_BEFORE_SET_CMD 0 197 #define HVD_ENABLE_WAIT_CMD_FINISHED 0 198 #define HVD_ENABLE_TIME_MEASURE 0 199 #define HVD_ENABLE_REINIT_FAILED 0 200 201 #if defined(CHIP_T2) || defined(CHIP_U3) || defined(CHIP_T3) || defined(CHIP_T4) || defined(CHIP_T7) 202 #define HVD_ENABLE_RV_FEATURE 0 203 #else 204 #define HVD_ENABLE_RV_FEATURE 1 205 #endif 206 207 #endif 208 209 #if defined(REDLION_LINUX_KERNEL_ENVI) 210 #include "drvHVD_redlion.h" 211 #endif 212 213 #if (HVD_ENABLE_MUTEX_PROTECT) || ( HVD_ENABLE_MSOS_SYSTEM_CALL ) 214 #include "osalHVD.h" 215 #endif 216 217 #if HVD_ENABLE_MSOS_MIU1_BASE 218 #include "halCHIP.h" 219 #endif 220 221 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF 222 #include "drvBDMA.h" 223 #define HVD_dmacpy( DESTADDR, SRCADDR , LEN) MDrv_BDMA_CopyHnd((MS_PHYADDR)(SRCADDR), (MS_PHYADDR)(DESTADDR), (LEN), E_BDMA_SDRAM2SDRAM1, BDMA_OPCFG_DEF) 224 #define HVD_BDMAcpy(DESTADDR, SRCADDR, LEN , Flag) MDrv_BDMA_CopyHnd((MS_PHYADDR)(SRCADDR), (MS_PHYADDR)(DESTADDR), (LEN), (Flag), BDMA_OPCFG_DEF) 225 #endif 226 227 #if HVD_ENABLE_BDMA_FW_FLASH_2_SDRAM 228 #include "drvSERFLASH.h" 229 #define HVD_FLASHcpy(DESTADDR, SRCADDR, LEN , Flag) MDrv_SERFLASH_CopyHnd((MS_PHYADDR)(SRCADDR), (MS_PHYADDR)(DESTADDR), (LEN), (Flag), SPIDMA_OPCFG_DEF) 230 #endif 231 232 // debug switch 233 // DEBUG 234 #define HVD_MSG_MUST(format, args...) HVD_UART_PRINTF( E_HVD_UART_CTRL_MUST ,format, ##args) 235 #define HVD_MSG_ERR(format, args...) HVD_UART_PRINTF( E_HVD_UART_CTRL_ERR ,format, ##args) 236 #define HVD_MSG_INFO(format, args...) HVD_UART_PRINTF( E_HVD_UART_CTRL_INFO , format, ##args) 237 #define HVD_MSG_DEG(format, args...) HVD_UART_PRINTF( E_HVD_UART_CTRL_DBG , format, ##args) 238 #define HVD_MSG_TRACE() HVD_UART_PRINTF( E_HVD_UART_CTRL_TRACE , "HVD TRACE:%s ; %s ; %d \n" , __FILE__ , __FUNCTION__, __LINE__) 239 //#define HVD_FW_DEG(format, args...) HVD_UART_PRINTF( E_HVD_UART_CTRL_FW , format, ##args) 240 241 // Configs 242 #define HVD_FW_IDLE_THRESHOLD 5000 // VPU ticks 243 #define HVD_BBU_ST_ADDR_IN_BITSTREAMBUF 0x400 244 245 #define HVD_DRV_CMD_WAIT_FINISH_TIMEOUT 100 246 247 248 // Util or Functions 249 #define HVD_MAX3(x,y,z) (((x)>(y) ? (x):(y)) > (z) ? ((x)>(y) ? (x):(y)):(z)) 250 #define HVD_LWORD(x) (MS_U16)((x)&0xffff) 251 #define HVD_HWORD(x) (MS_U16)(((x)>>16)&0xffff) 252 #define HVD_U32_MAX 0xffffffffUL 253 #define HVD_RV_BROKENBYUS_MASK 0x00800000 254 255 #ifdef MSOS_TYPE_LINUX 256 #if HVD_ENABLE_MSOS_SYSTEM_CALL 257 #define HVD_VA2PA(x ) (x)//(MS_U32)(MS_VA2PA( (void*)(x))) // fixme 258 #else 259 #define HVD_VA2PA(x ) (x)//(MS_U32)(MS_VA2PA( (void*)(x))) // fixme 260 #endif 261 #else 262 #define HVD_VA2PA(x) (x) 263 #endif 264 265 #if defined(REDLION_LINUX_KERNEL_ENVI) 266 #define HVD_PA2VA(x ) (MS_U32)MDrv_SYS_PA2NonCacheSeg((void*)(x)) 267 #else 268 #define HVD_PA2VA(x ) (MS_U32)MS_PA2KSEG1((MS_U32)(x)) 269 #endif 270 271 #if 0//def memset 272 #define HVD_memset(x , y , z) memset(x, y, z) 273 #else 274 #define HVD_memset( pDstAddr, u8value, u32Size) \ 275 do { \ 276 MS_U32 i = 0; \ 277 volatile MS_U8 *Dest = (volatile MS_U8 *)(pDstAddr) ; \ 278 for (i = 0; i < (u32Size); i++) \ 279 { \ 280 Dest[i] = (u8value); \ 281 } \ 282 }while(0) 283 #endif 284 285 #if 0//def memcpy 286 #define HVD_memcpy(x , y , z) memcpy(x, y, z) 287 #else 288 289 #if 0 290 #define HVD_memcpy( pDstAddr, pSrcAddr, u32Size) \ 291 do { \ 292 MS_U32 i = 0; \ 293 volatile MS_U8 *Dest = (volatile MS_U8 *)(pDstAddr ); \ 294 volatile MS_U8 *Src = ( volatile MS_U8 *)(pSrcAddr) ; \ 295 for (i = 0; i < (u32Size); i++) \ 296 { \ 297 Dest[i] = Src[i]; \ 298 } \ 299 }while(0) 300 #else 301 #define HVD_memcpy( pDstAddr, pSrcAddr, u32Size) \ 302 do { \ 303 register unsigned long u32I=0; \ 304 register unsigned long u32Dst = (unsigned long)pDstAddr; \ 305 void * pSrc = (void *)pSrcAddr; \ 306 MS_U32 _u32memsize = u32Size; \ 307 if( (u32Dst % 4) || ((unsigned long)pSrc % 4) ) \ 308 { \ 309 for( u32I=0; u32I< (unsigned long)(_u32memsize); u32I++) \ 310 { \ 311 ((volatile unsigned char *)u32Dst)[u32I] = ((volatile unsigned char *)pSrc)[u32I]; \ 312 } \ 313 } \ 314 else \ 315 { \ 316 for( u32I=0; u32I < ((unsigned long)(u32Size)/4); u32I++) \ 317 { \ 318 ((volatile unsigned long *)u32Dst)[u32I] = ((volatile unsigned long *)pSrc)[u32I]; \ 319 } \ 320 if((_u32memsize)%4) \ 321 { \ 322 u32Dst += u32I*4; \ 323 pSrc = (void *)((unsigned long)pSrc + u32I*4); \ 324 for( u32I=0; u32I<((unsigned long)(_u32memsize)%4); u32I++) \ 325 { \ 326 ((volatile unsigned char *)u32Dst)[u32I] = ((volatile unsigned char *)pSrc)[u32I]; \ 327 } \ 328 } \ 329 } \ 330 }while(0) 331 #endif 332 333 #endif 334 335 336 337 #if HVD_ENABLE_MSOS_SYSTEM_CALL 338 #define HVD_Delay_ms(x) MsOS_DelayTask(x) 339 #define HVD_SYSTEM_DELAY_MS_TYPE 2 340 #elif defined(REDLION_LINUX_KERNEL_ENVI) 341 #define HVD_Delay_ms(x) msleep(x) 342 //#define HVD_Delay_ms(x) MHal_H264_Delay_ms(x) 343 #define HVD_SYSTEM_DELAY_MS_TYPE 3 344 #else 345 #define HVD_Delay_ms(x) \ 346 do { \ 347 volatile MS_U32 ticks=0; \ 348 while( ticks < ( ((MS_U32)(x)) <<13) ) \ 349 { \ 350 ticks++; \ 351 } \ 352 } while(0) 353 #define HVD_SYSTEM_DELAY_MS_TYPE 0 354 #endif // HVD_ENABLE_MSOS_SYSTEM_CALL 355 356 357 #define HVD_DumpMemory( addr, size , ascii , NonCacheMask) \ 358 do{ \ 359 MS_U32 i = 0; \ 360 MS_U32 j = 0; \ 361 MS_U8* temp = (MS_U8*)addr; \ 362 MS_U8 string[17] ; \ 363 HVD_MSG_DEG("HVD Dump Memory addr: 0x%x ; size: 0x%x \r\n", addr, size); \ 364 temp = (MS_U8*)(((MS_U32)temp) | NonCacheMask); \ 365 HVD_memset(string , 0 , sizeof(string)); \ 366 for (j = 0; j < (size >> 4); j++) \ 367 { \ 368 if (ascii) \ 369 { \ 370 for (i = 0; i < 16; i++) \ 371 { \ 372 if (*(temp + i) >= 30 && *(temp + i) <= 126) \ 373 string[i] = *(temp + i); \ 374 else \ 375 string[i] = '.'; \ 376 } \ 377 HVD_MSG_DEG("0x%08x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %s\n" \ 378 , j << 4 , *temp, *(temp + 1), *(temp + 2), *(temp + 3), *(temp + 4), *(temp + 5), *(temp + 6), *(temp + 7), *(temp + 8), *(temp + 9), *(temp + 10), *(temp + 11), *(temp + 12), *(temp + 13), *(temp + 14), *(temp + 15) , string); \ 379 } \ 380 else \ 381 { \ 382 HVD_MSG_DEG("0x%08x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n" \ 383 , j << 4 , *temp, *(temp + 1), *(temp + 2), *(temp + 3), *(temp + 4), *(temp + 5), *(temp + 6), *(temp + 7), *(temp + 8), *(temp + 9), *(temp + 10), *(temp + 11), *(temp + 12), *(temp + 13), *(temp + 14), *(temp + 15)); \ 384 } \ 385 temp += 16; \ 386 } \ 387 HVD_MSG_DEG("0x%08x " , j << 4); \ 388 HVD_memset(string , 0 , sizeof(string)); \ 389 for (i = 0; i < (size & 0x0f); i++) \ 390 { \ 391 if (*(temp + i) >= 30 && *(temp + i) <= 126) \ 392 string[i] = *(temp + i); \ 393 else \ 394 string[i] = '.'; \ 395 HVD_MSG_DEG("%02x ", *(MS_U8*)(temp + i)); \ 396 } \ 397 if (ascii) \ 398 { \ 399 for (; i < 16 ; i++) \ 400 HVD_MSG_DEG(" "); \ 401 HVD_MSG_DEG(" %s\n" , string); \ 402 } \ 403 else \ 404 HVD_MSG_DEG("\n"); \ 405 }while(0) 406 407 408 #if HVD_ENABLE_MSOS_SYSTEM_CALL 409 #define HVD_GetSysTime_ms() MsOS_GetSystemTime() 410 #define HVD_SYSTEM_CLOCK_TYPE 1 411 #elif defined(REDLION_LINUX_KERNEL_ENVI) 412 #define HVD_GetSysTime_ms() MHal_H264_GetSyetemTime() 413 #define HVD_SYSTEM_CLOCK_TYPE 2 414 #else 415 #define HVD_GetSysTime_ms() 1 416 #define HVD_SYSTEM_CLOCK_TYPE 0 417 #endif // MsOS_GetSystemTime 418 419 420 #if defined(REDLION_LINUX_KERNEL_ENVI) 421 #define HVD_SYSTEM_UART_TYPE 2 422 #define HVD_UART_PRINTF( u32type, format , args...) \ 423 do{ \ 424 if( u32UartCtrl & u32type ) \ 425 { \ 426 printk( format , ##args ); \ 427 } \ 428 }while(0) 429 #else 430 #define HVD_SYSTEM_UART_TYPE 1 431 #define HVD_UART_PRINTF( u32type, format , args...) \ 432 do{ \ 433 if( u32UartCtrl & u32type ) \ 434 { \ 435 printf( format , ##args ); \ 436 } \ 437 }while(0) 438 #endif 439 440 #if HVD_ENABLE_MSOS_SYSTEM_CALL 441 #include "asmCPU.h" 442 #define HAL_MEMORY_BARRIER() MAsm_CPU_Sync() 443 #define HVD_MEMORY_BARRIER_TYPE 3 444 #else 445 #if defined (__mips__) 446 #define HAL_MEMORY_BARRIER() __asm__ volatile ("sync;") 447 #define HVD_MEMORY_BARRIER_TYPE 1 448 #elif defined (__aeon__) 449 #ifdef __AEONR2__ 450 #define HAL_MEMORY_BARRIER() __asm__ volatile ("b.syncwritebuffer;") 451 #define HVD_MEMORY_BARRIER_TYPE 22 452 #else 453 #if defined( CHIP_T2 ) 454 #define HAL_MEMORY_BARRIER() __asm__ volatile ("l.msync;") 455 #define HVD_MEMORY_BARRIER_TYPE 21 456 #else 457 #define HAL_MEMORY_BARRIER() __asm__ volatile ("l.syncwritebuffer;") 458 #define HVD_MEMORY_BARRIER_TYPE 23 459 #endif 460 #endif 461 #else 462 #define HAL_MEMORY_BARRIER() 463 #define HVD_MEMORY_BARRIER_TYPE 0 464 #endif 465 #endif 466 467 #if defined(UDMA_FPGA_ENVI) 468 #define HVD_UDMA_memcpy( pDstAddr, pSrcAddr, u32Size ) 469 #endif 470 471 //------------------------------------------------------------------------------------------------- 472 // Type and Structure 473 //------------------------------------------------------------------------------------------------- 474 typedef void (*HVD_ISRCallBack)(void); 475 476 typedef enum 477 { 478 E_HVD_RETURN_FAIL=0, 479 E_HVD_RETURN_SUCCESS, 480 E_HVD_RETURN_INVALID_PARAMETER, 481 E_HVD_RETURN_ILLEGAL_ACCESS, 482 E_HVD_RETURN_HARDWARE_BREAKDOWN, 483 E_HVD_RETURN_OUTOF_MEMORY, 484 E_HVD_RETURN_UNSUPPORTED, 485 E_HVD_RETURN_TIMEOUT, 486 E_HVD_RETURN_NOTREADY, 487 E_HVD_RETURN_MEMORY_OVERWIRTE, 488 E_HVD_RETURN_ES_FULL, 489 E_HVD_RETURN_RE_INIT, 490 E_HVD_RETURN_NOT_RUNNING, 491 } HVD_Return; 492 493 typedef enum 494 { 495 // share memory 496 E_HVD_GDATA_SHARE_MEM=0x1000, 497 // switch 498 //E_HVD_GDATA_SEMAPHORE, 499 E_HVD_GDATA_DISP_INFO_ADDR=(0x0100+E_HVD_GDATA_SHARE_MEM), 500 // report 501 E_HVD_GDATA_PTS=(0x0200+E_HVD_GDATA_SHARE_MEM), 502 E_HVD_GDATA_DECODE_CNT, 503 E_HVD_GDATA_DATA_ERROR_CNT, 504 E_HVD_GDATA_DEC_ERROR_CNT, 505 E_HVD_GDATA_ERROR_CODE, 506 E_HVD_GDATA_VPU_IDLE_CNT, 507 E_HVD_GDATA_DISP_FRM_INFO, 508 E_HVD_GDATA_DEC_FRM_INFO, 509 E_HVD_GDATA_ES_LEVEL, 510 E_HVD_GDATA_PTS_STC_DIFF, 511 512 // user data 513 E_HVD_GDATA_USERDATA_WPTR, 514 E_HVD_GDATA_USERDATA_IDX_TBL_ADDR, 515 E_HVD_GDATA_USERDATA_PACKET_TBL_ADDR, 516 E_HVD_GDATA_USERDATA_PACKET_SIZE, 517 E_HVD_GDATA_USERDATA_IDX_TBL_SIZE, 518 E_HVD_GDATA_USERDATA_PACKET_TBL_SIZE, 519 // report - modes 520 E_HVD_GDATA_IS_SHOW_ERR_FRM, 521 E_HVD_GDATA_IS_REPEAT_LAST_FIELD, 522 E_HVD_GDATA_IS_ERR_CONCEAL, 523 E_HVD_GDATA_IS_SYNC_ON, 524 E_HVD_GDATA_IS_PLAYBACK_FINISH, 525 E_HVD_GDATA_SYNC_MODE, 526 E_HVD_GDATA_SKIP_MODE, 527 E_HVD_GDATA_DROP_MODE, 528 E_HVD_GDATA_DISPLAY_DURATION, 529 E_HVD_GDATA_FRC_MODE, 530 E_HVD_GDATA_NEXT_PTS, 531 E_HVD_GDATA_DISP_Q_SIZE, 532 E_HVD_GDATA_DISP_Q_PTR, 533 E_HVD_GDATA_NEXT_DISP_FRM_INFO, 534 E_HVD_GDATA_REAL_FRAMERATE, 535 E_HVD_GDATA_IS_ORI_INTERLACE_MODE, 536 E_HVD_GDATA_FRM_PACKING_SEI_DATA, 537 E_HVD_GDATA_TYPE_FRAME_MBS_ONLY_FLAG, 538 E_HVD_GDATA_FB_USAGE_MEM, 539 540 // internal control 541 E_HVD_GDATA_IS_1ST_FRM_RDY=(0x0300+E_HVD_GDATA_SHARE_MEM), 542 E_HVD_GDATA_IS_I_FRM_FOUND, 543 E_HVD_GDATA_IS_SYNC_START, 544 E_HVD_GDATA_IS_SYNC_REACH, 545 E_HVD_GDATA_FW_VERSION_ID, 546 E_HVD_GDATA_FW_IF_VERSION_ID, 547 E_HVD_GDATA_BBU_Q_NUMB, 548 E_HVD_GDATA_DEC_Q_NUMB, 549 E_HVD_GDATA_DISP_Q_NUMB, 550 E_HVD_GDATA_PTS_Q_NUMB, 551 E_HVD_GDATA_FW_INIT_DONE, 552 // debug 553 E_HVD_GDATA_SKIP_CNT=(0x0400+E_HVD_GDATA_SHARE_MEM), 554 E_HVD_GDATA_GOP_CNT, 555 E_HVD_GDATA_DISP_CNT, 556 E_HVD_GDATA_DROP_CNT, 557 E_HVD_GDATA_DISP_STC, 558 E_HVD_GDATA_VSYNC_CNT, 559 E_HVD_GDATA_MAIN_LOOP_CNT, 560 // AVC 561 E_HVD_GDATA_AVC_LEVEL_IDC =(0x0500+E_HVD_GDATA_SHARE_MEM), 562 E_HVD_GDATA_AVC_LOW_DELAY, 563 E_HVD_GDATA_AVC_VUI_DISP_INFO, 564 //E_HVD_GDATA_AVC_SPS_ADDR, 565 566 // SRAM 567 E_HVD_GDATA_SRAM=0x2000, 568 //E_HVD_GDATA_AVC_NAL_CNT, 569 570 // Mailbox or Reg 571 E_HVD_GDATA_MBOX=0x3000, 572 E_HVD_GDATA_FW_STATE, // HVD RISC MBOX 0 (esp. FW init done) 573 E_HVD_GDATA_IS_DISP_INFO_UNCOPYED, // HVD RISC MBOX 0 (rdy only) 574 E_HVD_GDATA_IS_DISP_INFO_CHANGE, // HVD RISC MBOX 0 (rdy only) 575 E_HVD_GDATA_HVD_ISR_STATUS, // HVD RISC MBOX 1 (value only) 576 E_HVD_GDATA_VPU_ISR_STATUS, // VPU RISC MBOX 1 (value only) 577 E_HVD_GDATA_IS_FRAME_SHOWED, // HVD HI mbox 0 ( showed: rdy cleared ; not show: rdy enable ) 578 E_HVD_GDATA_ES_READ_PTR, // 579 E_HVD_GDATA_ES_WRITE_PTR, // 580 E_HVD_GDATA_BBU_READ_PTR, // 581 E_HVD_GDATA_BBU_WRITE_PTR, // 582 E_HVD_GDATA_BBU_WRITE_PTR_FIRED, // 583 E_HVD_GDATA_VPU_PC_CNT, // 584 585 // FW def 586 E_HVD_GDATA_FW_DEF=0x4000, 587 E_HVD_GDATA_FW_MAX_DUMMY_FIFO, // AVC: 256Bytes AVS: 2kB RM:??? 588 E_HVD_GDATA_FW_AVC_MAX_VIDEO_DELAY, 589 E_HVD_GDATA_FW_BBU_TOTAL_TBL_ENTRY, 590 E_HVD_GDATA_FW_BBU_TBL_ENTRY_NUMB, 591 E_HVD_GDATA_FW_PTS_TOTAL_ENTRY_NUMB, 592 E_HVD_GDATA_FW_DUMMY_WRITE_ADDR, 593 E_HVD_GDATA_FW_DS_BUF_ADDR, 594 E_HVD_GDATA_FW_DS_BUF_SIZE, 595 E_HVD_GDATA_FW_DS_VECTOR_DEPTH, 596 E_HVD_GDATA_FW_DS_INFO_ADDR, 597 E_HVD_GDATA_FW_DS_IS_ENABLED, 598 // BBU size 599 // default pitch number 600 // 601 } HVD_GetData; 602 603 typedef enum 604 { 605 // share memory 606 E_HVD_SDATA_SHARE_MEM=0x1000, 607 // switch 608 E_HVD_SDATA_FRAMEBUF_ADDR = (0x0100+E_HVD_SDATA_SHARE_MEM), 609 E_HVD_SDATA_FRAMEBUF_SIZE, 610 E_HVD_SDATA_ERROR_CODE, 611 E_HVD_SDATA_DISP_INFO_TH, 612 // display info 613 //E_HVD_SDATA_HOR_SIZE=(0x0200|E_HVD_SDATA_SHARE_MEM), 614 // report 615 //E_HVD_SDATA_PTS=0x0200, 616 // internal control 617 //E_HVD_SDATA_IDLE_CNT=0x0300, 618 // debug 619 //E_HVD_SDATA_SKIP_CNT=0x0400, 620 // RM 621 E_HVD_SDATA_RM_PICTURE_SIZES= ( 0x0500 |E_HVD_SDATA_SHARE_MEM ), 622 // SRAM 623 //E_HVD_SDATA_AVC_NAL_CNT=0x2000, 624 // Mailbox or Reg 625 E_HVD_SDATA_MAILBOX=0x3000, 626 E_HVD_SDATA_FW_CODE_TYPE=(0x0000|E_HVD_SDATA_MAILBOX), 627 E_HVD_SDATA_TRIGGER_DISP, // HVD HI mbox 0 ( 0: off ; rdy enable,1: on ) 628 E_HVD_SDATA_GET_DISP_INFO_DONE, // HVD RISC MBOX 1 ( clear rdy ) 629 E_HVD_SDATA_GET_DISP_INFO_START, // HVD RISC MBOX 0 ( clear rdy ) 630 // FW def 631 E_HVD_SDATA_FW_DEF=0x4000, 632 E_HVD_SDATA_VIRTUAL_BOX_WIDTH, 633 E_HVD_SDATA_VIRTUAL_BOX_HEIGHT, 634 //modify the state of the frame in DispQueue 635 E_HVD_SDATA_DISPQ_STATUS_VIEW, 636 E_HVD_SDATA_DISPQ_STATUS_DISP, 637 E_HVD_SDATA_DISPQ_STATUS_FREE, 638 } HVD_SetData; 639 640 typedef enum 641 { 642 E_HVD_UART_CTRL_DISABLE= BIT(4), 643 E_HVD_UART_CTRL_ERR= BIT(0), 644 E_HVD_UART_CTRL_INFO = BIT(1), 645 E_HVD_UART_CTRL_DBG= BIT(2), 646 E_HVD_UART_CTRL_FW= BIT(3), 647 E_HVD_UART_CTRL_MUST= BIT(4), 648 E_HVD_UART_CTRL_TRACE= BIT(5), 649 } HVD_Uart_Ctrl; 650 651 typedef enum 652 { 653 E_HVD_INIT_HW_MASK = BMASK(1:0), ///< HW Type 654 E_HVD_INIT_HW_AVC = BITS( 1:0,0) , ///< HW deflaut: AVC 0X00 655 E_HVD_INIT_HW_AVS = BITS( 1:0,1) , ///< HW : AVS 0X01 656 E_HVD_INIT_HW_RM =BITS( 1:0,2) , ///< HW: RM 0X10 657 E_HVD_INIT_MAIN_MASK = BMASK(3:2) , ///< main type 658 E_HVD_INIT_MAIN_FILE_RAW = BITS( 3:2,0) , ///< main type: default: 0X00 659 E_HVD_INIT_MAIN_FILE_TS = BITS( 3:2,1) , ///< main type: 0X01 660 E_HVD_INIT_MAIN_LIVE_STREAM = BITS( 3:2,2), ///< main type: 0X10 661 E_HVD_INIT_INPUT_MASK = BMASK(4:4) , ///< process path for filling BBU table: file mode. use drive; TSP: use tsp mode 662 E_HVD_INIT_INPUT_TSP = BITS( 4:4,0) , ///< tsp input( default) 663 E_HVD_INIT_INPUT_DRV = BITS( 4:4,1) , ///< driver input 664 E_HVD_INIT_START_CODE_MASK = BMASK(5:5) , ///< AVC FILE MODE ONLY: mkv, mp4 container use. 665 E_HVD_INIT_START_CODE_REMAINED = BITS( 5:5,0) , ///< start code remained.(Defualt) 666 E_HVD_INIT_START_CODE_REMOVED = BITS( 5:5,1) , ///< start code removed. 667 E_HVD_INIT_UTOPIA_ENVI = BIT( 6), ///< check MIU sel and set it 668 E_HVD_INIT_DBG_FW = BIT( 7) , ///< check FW is debug version or not 669 //E_HVD_INIT_ENABLE_ISR_DISP = BIT( 8) , ///< enable display ISR. ISR occurs at every Vsync. 670 } HVD_Init_Mode_Flag; 671 672 typedef enum 673 { 674 E_HVD_PLAY_NORMAL, 675 E_HVD_PLAY_PAUSE, 676 E_HVD_PLAY_STEP_DISPLAY, 677 } HVD_Play_Type; 678 679 typedef enum 680 { 681 E_HVD_ESB_LEVEL_NORMAL = 0, 682 E_HVD_ESB_LEVEL_UNDER = BIT(0), 683 E_HVD_ESB_LEVEL_OVER = BIT(1), 684 } HVD_ESBuf_Level; 685 686 //----------------------------------------------------------------------------- 687 /// @brief \b Enum \b Name: HVD_FWInputSourceType 688 /// @brief \b Enum \b Description: The type of fw binary input source 689 //----------------------------------------------------------------------------- 690 typedef enum 691 { 692 E_HVD_FW_INPUT_SOURCE_NONE, ///< No input fw. 693 E_HVD_FW_INPUT_SOURCE_DRAM, ///< input source from DRAM. 694 E_HVD_FW_INPUT_SOURCE_FLASH, ///< input source from FLASH. 695 } HVD_FWInputSourceType; 696 697 //----------------------------------------------------------------------------- 698 /// @brief \b Enum \b Name: HVD_FB_Reduction_Type 699 /// @brief \b Enum \b Description: The type of frame buffer reduction type 700 //----------------------------------------------------------------------------- 701 typedef enum 702 { 703 E_HVD_FB_REDUCTION_TYPE_NONE = 0, ///< FB reduction disable 704 E_HVD_FB_REDUCTION_TYPE_1_2 = 1, ///< FB reduction 1/2 705 E_HVD_FB_REDUCTION_TYPE_1_4 = 2, ///< FB reduction 1/4 706 } HVD_FBReductionType; 707 708 //----------------------------------------------------------------------------- 709 /// @brief \b Struct \b Name: HVD_Mem_Map 710 /// @brief \b Struct \b Description: Store the HVD driver config 711 //----------------------------------------------------------------------------- 712 typedef struct 713 { 714 MS_U32 u32MIU1BaseAddr; //!< the physical memory start address of MIU 1 base address. 0: default value. 715 MS_U32 u32FWBinaryVAddr; //!< virtual address of input FW binary in DRAM 716 MS_U32 u32FWBinaryAddr; //!< the physical memory start address in Flash memory of FW code source. 717 MS_U32 u32FWBinarySize; //!< the FW code size 718 MS_U32 u32VLCBinaryVAddr; ///< VLC table binary data buffer start address 719 MS_U32 u32VLCBinaryAddr; ///< VLC table binary data buffer start address 720 MS_U32 u32VLCBinarySize; ///<VLC table binary data buffer size 721 MS_U32 u32CodeBufVAddr; //!< the virtual memory start address of code buffer 722 MS_U32 u32CodeBufAddr; //!< the physical memory start address of code buffer 723 MS_U32 u32CodeBufSize; //!< the code buffer size 724 MS_U32 u32FrameBufVAddr; //!< the virtual memory start address of frame buffer 725 MS_U32 u32FrameBufAddr; //!< the physical memory start address of frame buffer 726 MS_U32 u32FrameBufSize; //!< the frame buffer size 727 MS_U32 u32BitstreamBufVAddr; //!< the virtual memory start address of bit stream buffer 728 MS_U32 u32BitstreamBufAddr; //!< the physical memory start address of bit stream buffer 729 MS_U32 u32BitstreamBufSize; //!< the bit stream buffer size 730 MS_U32 u32DrvProcessBufVAddr; //!< the virtual memory start address of driver process buffer 731 MS_U32 u32DrvProcessBufAddr; //!< the physical memory start address of driver process buffer 732 MS_U32 u32DrvProcessBufSize; //!< the driver process buffer size 733 MS_U32 u32DynSacalingBufVAddr; //!< the virtual memory start address of dynamic scaling buffer 734 MS_U32 u32DynSacalingBufAddr; //!< the physical memory start address of dynamic scaling buffer 735 MS_U32 u32DynSacalingBufSize; //!< the dynamic scaling buffer size 736 HVD_FWInputSourceType eFWSourceType; //!< the input FW source type. 737 } HVD_Mem_Map; 738 739 //----------------------------------------------------------------------------- 740 /// @brief \b Struct \b Name: HVD_Nal_Entry 741 /// @brief \b Struct \b Description: Store the information of one nal entry 742 //----------------------------------------------------------------------------- 743 typedef struct 744 { 745 MS_U32 u32NalID; ///< the ID nunber of this nal 746 MS_U32 u32NalAddr; ///< the offset of this nal from bit stream buffer start address. unit: byte 747 MS_U32 u32NalSize; ///< the size of this nal. unit: byte 748 MS_U32 u32NalPTS; ///< the time stamp of this nal. unit: ms 749 MS_BOOL bRVBrokenPacket; ///< the RV only 750 } HVD_Nal_Entry; 751 752 //----------------------------------------------------------------------------- 753 /// @brief \b Struct \b Name: RV_FileInfo 754 /// @brief \b Struct \b Description: RV file information 755 //----------------------------------------------------------------------------- 756 typedef struct 757 { 758 MS_U16 RV_Version; ///< Real Video Bitstream version 759 MS_U16 ulNumSizes; ///< Real Video Number sizes 760 MS_U16 ulPicSizes_w[8]; ///< Real Video file width 761 MS_U16 ulPicSizes_h[8]; ///< Real Video file height 762 } RV_FileInfo; 763 764 //----------------------------------------------------------------------------- 765 /// @brief \b Struct \b Name: HVD_FB_Reduction_Mode 766 /// @brief \b Struct \b Description: Set up frame buffer reduction mode 767 //----------------------------------------------------------------------------- 768 typedef struct 769 { 770 HVD_FBReductionType eLumaFBReductionMode; ///< Luma frame buffer reduction mode. 771 HVD_FBReductionType eChromaFBReductionMode; ///< Chroma frame buffer reduction mode. 772 MS_U8 u8EnableAutoMode; /// 0: Disable, 1: Enable 773 } HVD_FBReductionMode; 774 775 //----------------------------------------------------------------------------- 776 /// @brief \b Struct \b Name: HVD_Init_Params 777 /// @brief \b Struct \b Description: Store the initialization settings 778 //----------------------------------------------------------------------------- 779 typedef struct 780 { 781 MS_U32 u32ModeFlag; ///< init mode flag, use HVD_INIT_* to setup HVD. 782 MS_U32 u32FrameRate; ///< frame rate. 783 MS_U32 u32FrameRateBase; ///< frame rate base. The value of u32FrameRate /u32FrameRateBase must be frames per sec. 784 MS_U8 u8MinFrmGap; ///< set the min frame gap. 785 MS_U8 u8SyncType; ///< HVD_Sync_Type. sync type of current playback. 786 MS_U16 u16Pitch; ///< not zero: specify the pitch. 0: use default value. 787 MS_U32 u32MaxDecTick; ///< not zero: specify the max decode tick. 0: use default value. 788 MS_BOOL bSyncEachFrm; ///< TRUE: sync STC at each frame. FALSE: not sync each frame. 789 MS_BOOL bAutoFreeES; ///< TRUE: auto free ES buffer when ES buffer is full. FALSE: not do the auto free. 790 MS_BOOL bAutoPowerSaving; ///< TRUE: auto power saving. FALSE: not do the auto power saving. 791 MS_BOOL bDynamicScaling; ///< TRUE: enable Dynamic Scaling. FALSE: disable Dynamic Scaling. 792 MS_BOOL bFastDisplay; ///< TRUE: enable Fast Display. FALSE: disable Fast Display. 793 MS_BOOL bUserData; ///< TRUE: enable processing User data. FALSE: disable processing User data. 794 MS_U8 u8TurboInit; ///< HVD_TurboInitLevel. set the turbo init mode. 795 MS_U8 u8TimeUnit; ///< HVD_Time_Unit_Type.set the type of input/output time unit. 796 MS_U16 u16DecoderClock; ///< HVD decoder clock speed. 0: default value. non-zero: any nearist clock. 797 RV_FileInfo* pRVFileInfo; ///< pointer to RV file info 798 HVD_FBReductionMode stFBReduction; ///< HVD Frame buffer reduction type 799 } HVD_Init_Params; 800 801 //----------------------------------------------------------------------------- 802 /// @brief \b Struct \b Name: HVD_BBU_Info 803 /// @brief \b Struct \b Description: Store the packet information 804 //----------------------------------------------------------------------------- 805 typedef struct 806 { 807 MS_U32 u32Staddr; ///< Packet offset from bitstream buffer base address. unit: byte. 808 MS_U32 u32Length; ///< Packet size. unit: byte. 809 MS_U32 u32TimeStamp; ///< Packet time stamp. unit: ms. 810 MS_U32 u32ID_L; ///< Packet ID low part. 811 MS_U32 u32ID_H; ///< Packet ID high part. 812 MS_U32 u32OriPktAddr; ///< Original packet offset from bitstream buffer base address. unit: byte. 813 MS_BOOL bRVBrokenPacket; ///< the RV only 814 } HVD_BBU_Info; 815 816 //----------------------------------------------------------------------------- 817 /// @brief \b Struct \b Name: HVD_Alive_Status 818 /// @brief \b Struct \b Description: Store the decoder living information 819 //----------------------------------------------------------------------------- 820 typedef struct 821 { 822 MS_U32 u32DecCnt; 823 MS_U32 u32SkipCnt; 824 MS_U32 u32IdleCnt; 825 MS_U32 u32MainLoopCnt; 826 } HVD_Alive_Status; 827 828 //----------------------------------------------------------------------------- 829 /// @brief \b Struct \b Name: HVD_DISP_INFO_THRESHOLD 830 /// @brief \b Struct \b Description: Store the disp information threshold. 831 //----------------------------------------------------------------------------- 832 typedef struct 833 { 834 MS_U32 u32FrmrateUpBound; //Framerate filter upper bound 835 MS_U32 u32FrmrateLowBound; //Framerate filter lower bound 836 MS_U32 u32MvopUpBound; //mvop filter upper bound 837 MS_U32 u32MvopLowBound; //mvop filter lower bound 838 } HVD_Disp_Info_TH; 839 840 //----------------------------------------------------------------------------- 841 /// @brief \b Struct \b Name: HVD_Settings 842 /// @brief \b Struct \b Description: Store the settings of user requirment 843 //----------------------------------------------------------------------------- 844 typedef struct 845 { 846 // TODO: currently only DTV settings. Need to add more settings for MM. 847 // Mode 848 HVD_Disp_Info_TH DispInfoTH; 849 MS_U32 u32IsrEvent; 850 MS_BOOL bEnISR; 851 852 MS_U8 u8SkipMode; // HVD_Skip_Decode_Type 853 MS_U8 bIsShowErrFrm; 854 MS_U8 u8FrcMode; //HVD_FrmRateConv_Mode 855 856 MS_BOOL bIsErrConceal; 857 MS_BOOL bAutoFreeES; 858 MS_BOOL bDisDeblocking; 859 MS_BOOL bDisQuarterPixel; 860 861 MS_U8 bIsSyncOn; 862 MS_U32 u32SyncTolerance; 863 MS_U32 u32SyncRepeatTH; 864 MS_U32 u32SyncVideoDelay; 865 MS_U32 u32SyncFreeRunTH; 866 MS_U32 u32MiuBurstLevel; 867 } HVD_Settings; 868 869 870 871 872 873 //----------------------------------------------------------------------------- 874 /// @brief \b Struct \b Name: HVD_CC_Info 875 /// @brief \b Struct \b Description: HVD Close Caption Infomation. 876 //----------------------------------------------------------------------------- 877 typedef struct 878 { 879 MS_U8 u8UserDataMode; 880 MS_U8 u8ParsingStatus; 881 MS_BOOL b708Enable; 882 MS_BOOL b608InfoEnhance; 883 MS_BOOL bBufMiu1[2]; 884 MS_BOOL bOverFlow[2]; 885 MS_U32 u32RingBufStartPAddr[2];//physical address 886 MS_U32 u32RingBufLen[2]; 887 MS_U32 volatile u32RingBufVacancy[2]; 888 MS_U32 volatile u32RingBufRPAddr[2], u32RingBufWPAddr[2];//physical address 889 MS_U32 volatile u32FWUsrDataRIdx, u32FWUsrDataWIdx; 890 MS_U32 u32PktLen708; 891 MS_U32 u32PktHdrAddr708; 892 MS_U8 u8CC608buf[512]; 893 MS_U8 u8CC708buf[512]; 894 } HVD_CC_Info; 895 896 typedef struct 897 { 898 MS_U16 u16TmpRef; 899 MS_U16 u16PicStruct; 900 MS_U32 u32Pts; 901 MS_U8 u8UsrDataCnt; 902 } HVD_CC_608EnhanceInfo; 903 904 905 906 //----------------------------------------------------------------------------- 907 /// @brief \b Struct \b Name: HVD_Drv_Ctrl 908 /// @brief \b Struct \b Description: HVD driver internal control. 909 //----------------------------------------------------------------------------- 910 typedef struct 911 { 912 // init stage 913 HVD_Mem_Map MemMap; ///< HVD memory config 914 HVD_Init_Params InitParams; ///< HVD init settings 915 MS_BOOL bNoDrvProccBuf; 916 MS_BOOL bAutoRmLastZeroByte; 917 MS_BOOL bCannotAccessMIU256; 918 MS_U32 u32CmdTimeout; ///< HVD FW command timeout 919 920 // reset stage 921 MS_U32 u32CtrlMode; ///< HVD run-time control flag 922 MS_U32 u32DummyWriteBuf; ///< For dummy write MIU action. 923 //MS_U32 u32CPUNonCacheMask; ///< CPU non-cache mask 924 MS_U32 u32NULLPacketSize; ///< to store the size of AVI null packet pattern 925 MS_U32 u32NULLPacketAddr; ///< to store the start address of AVI null packet pattern from bitstream buffer base. 926 MS_U32 u32RV_FlushPacketSize; ///< to store the size of rm flush packet pattern 927 MS_U32 u32RV_FlushPacketAddr; ///< to store the start address of rm flush packet pattern from bitstream buffer base. 928 MS_U32 u32StepDecodeCnt; 929 //MS_U32 u32LastBBUPTS; 930 //MS_U32 u32DummyDataSize; ///< buffer size of dummy data. 931 //MS_U32 u32RestSizeofPushDummy; 932 //MS_U32 u32AddrPushDummy; 933 MS_U32 u32LastESRptr; 934 MS_U32 u32BBUTblInBitstreamBufAddr; 935 MS_U32 u32BBUPacketCnt; 936 MS_U32 u32BBUWptr_Fired; 937 MS_U32 u32LastErrCode; 938 //MS_BOOL bPushingDummy; 939 MS_BOOL bIsDispInfoChg; 940 HVD_Nal_Entry LastNal; 941 HVD_Alive_Status LivingStatus; 942 943 // recovery stage 944 MS_BOOL bStepDecoding; 945 HVD_Settings Settings; 946 947 MS_U8 bTurboFWMode; //TRUE:not reload FW more than once if pre-decoder is the same. 948 949 MS_U32 u32UsrDataRd; 950 MS_U32 u32UsrDataWr; 951 952 HVD_CC_Info CloseCaptionInfo; 953 954 } HVD_Drv_Ctrl; 955 956 //----------------------------------------------------------------------------- 957 /// @brief \b Struct \b Name: HVD_ISR_Ctrl 958 /// @brief \b Struct \b Description: HVD driver ISR control. 959 //----------------------------------------------------------------------------- 960 typedef struct 961 { 962 MS_BOOL bRegISR; 963 MS_BOOL bInISR; 964 MS_U32 u32ISRInfo; 965 HVD_ISRCallBack pfnISRCallBack; 966 } HVD_ISR_Ctrl; 967 968 //----------------------------------------------------------------------------- 969 /// @brief \b Struct \b Name: HVD_Pre_Ctrl 970 /// @brief \b Struct \b Description: HVD driver pre-setting control. 971 //----------------------------------------------------------------------------- 972 typedef struct 973 { 974 MS_BOOL bOnePendingBuffer; 975 MS_BOOL bFrameRateHandling; 976 MS_U32 u32PreSetFrameRate; 977 } HVD_Pre_Ctrl; 978 979 typedef void(*P_SC_ISR_Proc)(MS_U8 u8SCID); 980 981 982 //------------------------------------------------------------------------------------------------- 983 // Function and Variable 984 //------------------------------------------------------------------------------------------------- 985 extern MS_U32 u32UartCtrl; 986 extern MS_U32 u32InitSysTimeBase; 987 988 #endif // _DRV_HVD_DEF_H_ 989 990