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76 //******************************************************************************
77 //<MStar Software>
78 ///////////////////////////////////////////////////////////////////////////////////////////////////
79 ///
80 /// file drvXC_HDMI_if_v2.c
81 /// @author MStar Semiconductor Inc.
82 /// @brief HDMI Rx driver Function
83 ///////////////////////////////////////////////////////////////////////////////////////////////////
84
85 #ifndef _API_HDMI_RX_V2_C_
86 #define _API_HDMI_RX_V2_C_
87
88 //-------------------------------------------------------------------------------------------------
89 // Include Files
90 //-------------------------------------------------------------------------------------------------
91 #include "MsCommon.h"
92 #ifdef MSOS_TYPE_LINUX_KERNEL
93 #include <linux/string.h>
94 #else
95 #include "string.h"
96 #endif
97 #include "utopia.h"
98 #include "utopia_dapi.h"
99 #include "drvXC_IOPort.h"
100 #include "apiXC.h"
101 #include "apiXC_Adc.h"
102 #include "apiXC_Auto.h"
103 #include "apiXC_ModeParse.h"
104 #include "drv_sc_display.h"
105 #include "drv_sc_isr.h"
106 #include "apiXC_PCMonitor.h"
107 #include "drvXC_HDMI_if.h"
108 #include "mhal_xc_chip_config.h"
109 #include "mvideo_context.h"
110 #if (LD_ENABLE==1)
111 #include "mdrv_ld.h"
112 #include "mdrv_ldalgo.h"
113 #endif
114 #include "mdrv_sc_3d.h"
115 #include "drv_sc_menuload.h"
116 #include "drv_sc_ip.h"
117 #include "drvXC_ADC_Internal.h"
118 #include "mhal_sc.h"
119 #if FRC_INSIDE
120 #include "mdrv_frc.h"
121 #include "mhal_frc.h"
122 #endif
123 #include "XC_private.h"
124 #include "apiXC_v2.h"
125 #include "drvXC_HDMI_if_v2.h"
126 #include "apiHDMIRx_private.h"
127
128 //-------------------------------------------------------------------------------------------------
129 // Local Defines
130 //-------------------------------------------------------------------------------------------------
131 #if(defined(CONFIG_MLOG))
132 #include "ULog.h"
133
134 #define MAPI_HDMIRX_MSG_INFO(format, args...) ULOGI("HDMIRX", format, ##args)
135 #define MAPI_HDMIRX_MSG_WARNING(format, args...) ULOGW("HDMIRX", format, ##args)
136 #define MAPI_HDMIRX_MSG_DEBUG(format, args...) ULOGD("HDMIRX", format, ##args)
137 #define MAPI_HDMIRX_MSG_ERROR(format, args...) ULOGE("HDMIRX", format, ##args)
138 #define MAPI_HDMIRX_MSG_FATAL(format, args...) ULOGF("HDMIRX", format, ##args)
139
140 #else
141 #define MAPI_HDMIRX_MSG_INFO(format, args...) printf(format, ##args)
142 #define MAPI_HDMIRX_MSG_WARNING(format, args...) printf(format, ##args)
143 #define MAPI_HDMIRX_MSG_DEBUG(format, args...) printf(format, ##args)
144 #define MAPI_HDMIRX_MSG_ERROR(format, args...) printf(format, ##args)
145 #define MAPI_HDMIRX_MSG_FATAL(format, args...) printf(format, ##args)
146
147 #endif
148
149 //-------------------------------------------------------------------------------------------------
150 // Local Structures
151 //-------------------------------------------------------------------------------------------------
152
153 //-------------------------------------------------------------------------------------------------
154 // Global Variables
155 //-------------------------------------------------------------------------------------------------
156
157 //-------------------------------------------------------------------------------------------------
158 // Local Variables
159 //-------------------------------------------------------------------------------------------------
160
161 //-------------------------------------------------------------------------------------------------
162 // Local Functions
163 //-------------------------------------------------------------------------------------------------
164
165 //-------------------------------------------------------------------------------------------------
166 // Global Functions
167 //-------------------------------------------------------------------------------------------------
168
169 //**************************************************************************
170 // [Function Name]:
171 // HDMI_IF_Initialize()
172 // [Description]
173 //
174 // [Arguments]:
175 //
176 // [Return]:
177 //
178 //**************************************************************************
HDMI_IF_Initialize(XC_INSTANCE_PRIVATE * psXCInstPri,const void * const pAttribute)179 void HDMI_IF_Initialize(XC_INSTANCE_PRIVATE* psXCInstPri, const void* const pAttribute)
180 {
181 psXCInstPri->fpHDMI_Func_Caps = MDrv_HDMI_Func_Caps_U2;
182 psXCInstPri->fpHDMI_init = MDrv_HDMI_init_U2;
183 psXCInstPri->fpHDMI_Exit = MDrv_HDMI_Exit_U2;
184 psXCInstPri->fpHDMI_pkt_reset = MDrv_HDMI_pkt_reset_U2;
185 psXCInstPri->fpHDMI_pullhpd = MDrv_HDMI_pullhpd_U2;
186 psXCInstPri->fpHDMI_GC_Info = MDrv_HDMI_GC_Info_U2;
187 psXCInstPri->fpHDMI_Packet_Received = MDrv_HDMI_Packet_Received_U2;
188 psXCInstPri->fpHDMI_Get_ColorFormat = MDrv_HDMI_Get_ColorFormat_U2;
189 psXCInstPri->fpHDMI_Get_ColorRange = MDrv_HDMI_Get_ColorRange_U2;
190 psXCInstPri->fpHDMI_Set_EQ = MDrv_HDMI_Set_EQ_U2;
191 psXCInstPri->fpHDMI_Set_EQ_To_Port = MDrv_HDMI_Set_EQ_To_Port_U2;
192 psXCInstPri->fpHDMI_Audio_MUTE_Enable = MDrv_HDMI_Audio_MUTE_Enable_U2;
193 psXCInstPri->fpHDMI_Audio_Status_Clear = MDrv_HDMI_Audio_Status_Clear_U2;
194 psXCInstPri->fpHDMI_Get_AspectRatio = MDrv_HDMI_Get_AspectRatio_U2;
195 psXCInstPri->fpHDMI_Get_ActiveFormat_AspectRatio = MDrv_HDMI_Get_ActiveFormat_AspectRatio_U2;
196 psXCInstPri->fpHDMI_Get_AVIInfoFrameVer = MDrv_HDMI_Get_AVIInfoFrameVer_U2;
197 psXCInstPri->fpHDMI_err_status_update = MDrv_HDMI_err_status_update_U2;
198 psXCInstPri->fpHDMI_Get_TMDS_freq = MDrv_HDMI_GetTMDSFreq_U2;
199 psXCInstPri->fpHDMI_Get_PollingStatus = MDrv_HDMI_Get_PollingStatus_U2;
200 psXCInstPri->fpHDMI_IsHDMI_Mode = MDrv_HDMI_IsHDMI_Mode_U2;
201 psXCInstPri->fpHDMI_Get_MID_info = MDrv_HDMI_Get_MID_info_U2;
202 psXCInstPri->fpHDMI_get_packet_value = MDrv_HDMI_get_packet_value_U2;
203 psXCInstPri->fpDVI_ChannelPhaseStatus = MDrv_DVI_ChannelPhaseStatus_U2;
204 psXCInstPri->fpDVI_SoftwareReset = MDrv_DVI_SoftwareReset_U2;
205 psXCInstPri->fpdvi_reset = mdrv_dvi_reset_U2;
206 psXCInstPri->fpHDMI_Get_AVIInfoActiveInfoPresent = MDrv_HDMI_Get_AVIInfoActiveInfoPresent_U2;
207 psXCInstPri->fpDVI_ClkPullLow = MDrv_DVI_ClkPullLow_U2;
208 psXCInstPri->fpDVI_SwitchSrc = MDrv_DVI_SwitchSrc_U2;
209 psXCInstPri->fpHDMI_SetForClockLessThan70Mhz = MDrv_HDMI_SetForClockLessThan70Mhz_U2;
210 psXCInstPri->fpHDMI_dvi_adjust = MDrv_HDMI_dvi_adjust_U2;
211 psXCInstPri->fpHDMI_SetUpdatePhaseLineCount = MDrv_HDMI_SetUpdatePhaseLineCount_U2;
212 psXCInstPri->fpHDCP_Enable = MDrv_HDCP_Enable_U2;
213 psXCInstPri->fpHDMI_SetHdcpEnable = MDrv_HDMI_SetHdcpEnable_U2;
214 psXCInstPri->fpHDCP_ClearStatus = MDrv_HDCP_ClearStatus_U2;
215 psXCInstPri->fpHDCP_initproductionkey = MDrv_HDCP_initproductionkey_U2;
216 psXCInstPri->fpHDCP_GetStatus = MDrv_HDCP_GetStatus_U2;
217 psXCInstPri->fpHDCP_Vsync_end_en = MDrv_HDCP_Vsync_end_en_U2;
218 psXCInstPri->fpHDMI_audio_output = MDrv_HDMI_audio_output_U2;
219 psXCInstPri->fpHDMI_audio_cp_hdr_info = MDrv_HDMI_audio_cp_hdr_info_U2;
220 psXCInstPri->fpHDMI_audio_channel_status = MDrv_HDMI_audio_channel_status_U2;
221 psXCInstPri->fpHDMI_GetLibVer = MDrv_HDMI_GetLibVer_U2;
222 psXCInstPri->fpHDMI_GetInfo = MDrv_HDMI_GetInfo_U2;
223 psXCInstPri->fpHDMI_GetStatus = MDrv_HDMI_GetStatus_U2;
224 psXCInstPri->fpHDMI_READ_DDCRAM = MDrv_HDMI_READ_DDCRAM_U2;
225 psXCInstPri->fpHDMI_PROG_DDCRAM = MDrv_HDMI_PROG_DDCRAM_U2;
226 psXCInstPri->fpHDMI_Get_Ext_Colorimetry = MDrv_HDMI_Get_ExtColorimetry_U2;
227 psXCInstPri->fpHDMI_Get_Content_Type = MDrv_HDMI_Get_Content_Type_U2;
228 psXCInstPri->fpHDMI_Get_Pixel_Repetition = MDrv_HDMI_Get_Pixel_Repetition_U2;
229 psXCInstPri->fpHDMI_Check4K2K = MDrv_HDMI_Check4K2K_U2;
230 psXCInstPri->fpHDMI_3D_4Kx2K_Process = MDrv_HDMI_3D_4Kx2K_Process_U2;
231 psXCInstPri->fpHDMI_AVG_ScaleringDown = MDrv_HDMI_AVG_ScaleringDown_U2;
232 psXCInstPri->fpHDMI_Check_Additional_Format = MDrv_HDMI_Check_Additional_Format_U2;
233 psXCInstPri->fpHDMI_Get_3D_Structure = MDrv_HDMI_Get_3D_Structure_U2;
234 psXCInstPri->fpHDMI_Get_3D_Ext_Data = MDrv_HDMI_Get_3D_Ext_Data_U2;
235 psXCInstPri->fpHDMI_Get_3D_Meta_Field = MDrv_HDMI_Get_3D_Meta_Field_U2;
236 psXCInstPri->fpHDMI_Get_VIC_Code = MDrv_HDMI_Get_VIC_Code_U2;
237 psXCInstPri->fpHDMI_Get_4Kx2K_VIC_Code = MDrv_HDMI_Get_4Kx2K_VIC_Code_U2;
238 psXCInstPri->fpHDMI_ARC_PINControl = MDrv_HDMI_ARC_PINControl_U2;
239 psXCInstPri->fpDVI_Software_Reset = MDrv_DVI_Software_Reset_U2;
240 psXCInstPri->fpHDMI_Set_PowerState = MDrv_HDMI_SetPowerState_U2;
241 psXCInstPri->fpHDMI_dvi_hf_adjust = MDrv_DVI_HF_adjust_U2;
242 psXCInstPri->fpHDMI_checkhdmi20_setting = MDrv_HDMI_CheckHDMI20_Setting_U2;
243 psXCInstPri->fpHDMI_Set5VDetectGPIOSelect = MDrv_HDMI_Set5VDetectGPIOSelect_U2;
244 psXCInstPri->fpHDMI_GetDEStableStatus= MDrv_HDMI_GetDEStableStatus_U2;
245 psXCInstPri->fpHDMI_Ctrl = MDrv_HDMI_Ctrl_U2;
246 psXCInstPri->fpHDMI_GetDataInfo = MDrv_HDMI_GetDataInfo_U2;
247 return;
248 }
249
250 //**************************************************************************
251 // [Function Name]:
252 // _HDMI_IF_Ioctl()
253 // [Description]
254 //
255 // [Arguments]:
256 //
257 // [Return]:
258 //
259 //**************************************************************************
_HDMI_IF_Ioctl(void * pInstance,MS_U32 u32Cmd,void * pArgs)260 MS_U32 _HDMI_IF_Ioctl(void * pInstance, MS_U32 u32Cmd, void * pArgs)
261 {
262 //void* pModule = NULL;
263 //void* pResource = NULL;
264 MS_U32 u32Return = UTOPIA_STATUS_FAIL;
265 XC_INSTANCE_PRIVATE* psXCInstPri = NULL;
266
267 //UtopiaInstanceGetModule(pInstance, &pModule);
268
269 if(UtopiaInstanceGetPrivate(pInstance, (void*)&psXCInstPri)!=UTOPIA_STATUS_SUCCESS)
270 {
271 MAPI_HDMIRX_MSG_ERROR("[%s,%5d] Instance Get Private failed\n",__FUNCTION__,__LINE__);
272 }
273
274 switch(u32Cmd)
275 {
276 case E_XC_HDMI_IF_CMD_FUNC_CAPS:
277 {
278
279 pstHDMI_FUNC_CAPS pXCArgs = (pstHDMI_FUNC_CAPS) pArgs;
280 pXCArgs->u16ReturnValue = psXCInstPri->fpHDMI_Func_Caps(pInstance);
281
282 u32Return = UTOPIA_STATUS_SUCCESS;
283 break;
284 }
285
286 case E_XC_HDMI_IF_CMD_INIT:
287 {
288 pstHDMI_INITIAL_SETTING pXCArgs = (pstHDMI_INITIAL_SETTING)pArgs;
289
290 pXCArgs->stInitialTable = psXCInstPri->fpHDMI_init(pInstance);
291 #if PIP_PATCH_USING_SC1_MAIN_AS_SC0_SUB
292 //FIX ME: other hdmi interface may assess global vars,maybe should add device1 flow
293 CHECK_DEVICE1_INSTANCE();
294 pXCArgs->stInitialTable = psXCInstPri->fpHDMI_init(g_pDevice1Instance);
295 #endif
296 u32Return = UTOPIA_STATUS_SUCCESS;
297 break;
298 }
299
300 case E_XC_HDMI_IF_CMD_EXIT:
301 {
302
303 psXCInstPri->fpHDMI_Exit(pInstance);
304
305 u32Return = UTOPIA_STATUS_SUCCESS;
306 break;
307 }
308
309 case E_XC_HDMI_IF_CMD_PKT_RESET:
310 {
311
312 pstHDMI_PKT_RESET pXCArgs = (pstHDMI_PKT_RESET) pArgs;
313 psXCInstPri->fpHDMI_pkt_reset(pInstance, pXCArgs->breset);
314
315 u32Return = UTOPIA_STATUS_SUCCESS;
316 break;
317 }
318
319 case E_XC_HDMI_IF_CMD_PULLHPD:
320 {
321
322 pstHDMI_PULLHPD pXCArgs = (pstHDMI_PULLHPD) pArgs;
323 psXCInstPri->fpHDMI_pullhpd(pInstance, pXCArgs->bHighLow,
324 pXCArgs->enInputPortType,
325 pXCArgs->bInverse);
326
327 u32Return = UTOPIA_STATUS_SUCCESS;
328 break;
329 }
330
331 case E_XC_HDMI_IF_CMD_GC_INFO:
332 {
333 pstHDMI_GC_INFO pXCArgs = (pstHDMI_GC_INFO) pArgs;
334 pXCArgs->u16ReturnValue = psXCInstPri->fpHDMI_GC_Info(pInstance, pXCArgs->ucHDMIInfoSource, pXCArgs->gcontrol);
335
336 u32Return = UTOPIA_STATUS_SUCCESS;
337 break;
338 }
339
340 case E_XC_HDMI_IF_CMD_PACKET_RECEIVED:
341 {
342 pstHDMI_PACKET_RECEIVED pXCArgs = (pstHDMI_PACKET_RECEIVED) pArgs;
343 psXCInstPri->fpHDMI_Packet_Received(pInstance, pXCArgs->ucHDMIInfoSource, pXCArgs->bEnable, pXCArgs->ulPacketStatus);
344
345 u32Return = UTOPIA_STATUS_SUCCESS;
346 break;
347 }
348
349 case E_XC_HDMI_IF_CMD_GET_COLORFORMAT:
350 {
351 pstHDMI_GET_COLORFORMAT pXCArgs = (pstHDMI_GET_COLORFORMAT) pArgs;
352 pXCArgs->eReturnValue = psXCInstPri->fpHDMI_Get_ColorFormat(pInstance, pXCArgs->ucHDMIInfoSource);
353
354 u32Return = UTOPIA_STATUS_SUCCESS;
355 break;
356 }
357
358 case E_XC_HDMI_IF_CMD_GET_COLORRANGE:
359 {
360 pstHDMI_GET_COLORRANGE pXCArgs = (pstHDMI_GET_COLORRANGE) pArgs;
361 pXCArgs->eReturnValue = psXCInstPri->fpHDMI_Get_ColorRange(pInstance, pXCArgs->ucHDMIInfoSource);
362
363 u32Return = UTOPIA_STATUS_SUCCESS;
364 break;
365 }
366 case E_XC_HDMI_IF_CMD_SET_EQ:
367 {
368
369 pstHDMI_SET_EQ pXCArgs = (pstHDMI_SET_EQ) pArgs;
370 psXCInstPri->fpHDMI_Set_EQ(pInstance, pXCArgs->enEq, pXCArgs->u8EQValue);
371
372 u32Return = UTOPIA_STATUS_SUCCESS;
373 break;
374 }
375
376 case E_XC_HDMI_IF_CMD_SET_EQ_TO_PORT:
377 {
378 pstHDMI_SET_EQ_TO_PORT pXCArgs = (pstHDMI_SET_EQ_TO_PORT) pArgs;
379 pXCArgs->bReturnValue = psXCInstPri->fpHDMI_Set_EQ_To_Port(pInstance, pXCArgs->enEq, pXCArgs->u8EQValue, pXCArgs->enInputPortType);
380
381 u32Return = UTOPIA_STATUS_SUCCESS;
382 break;
383 }
384
385 case E_XC_HDMI_IF_CMD_AUDIO_MUTE_ENABLE:
386 {
387
388 pstHDMI_AUDIO_MUTE_ENABLE pXCArgs = (pstHDMI_AUDIO_MUTE_ENABLE) pArgs;
389 psXCInstPri->fpHDMI_Audio_MUTE_Enable(pInstance, pXCArgs->u16MuteEvent,
390 pXCArgs->u16MuteMask);
391
392 u32Return = UTOPIA_STATUS_SUCCESS;
393 break;
394 }
395
396 case E_XC_HDMI_IF_CMD_AUDIO_STATUS_CLEAR:
397 {
398
399 psXCInstPri->fpHDMI_Audio_Status_Clear(pInstance);
400
401 u32Return = UTOPIA_STATUS_SUCCESS;
402 break;
403 }
404
405 case E_XC_HDMI_IF_CMD_GET_ASPECTRATIO:
406 {
407 pstHDMI_GET_ASPECTRATIO pXCArgs = (pstHDMI_GET_ASPECTRATIO) pArgs;
408 pXCArgs->eReturnValue = psXCInstPri->fpHDMI_Get_AspectRatio(pInstance, pXCArgs->ucHDMIInfoSource, pXCArgs->bEn_PAR, pXCArgs->bEn_AFAR);
409
410 u32Return = UTOPIA_STATUS_SUCCESS;
411 break;
412 }
413
414 case E_XC_HDMI_IF_CMD_GET_ACTIVEFORMAT_ASPECTRATIO:
415 {
416 pstHDMI_GET_ACTIVEFORMAT_ASPECTRATIO pXCArgs = (pstHDMI_GET_ACTIVEFORMAT_ASPECTRATIO) pArgs;
417 pXCArgs->eReturnValue = psXCInstPri->fpHDMI_Get_ActiveFormat_AspectRatio(pInstance, pXCArgs->ucHDMIInfoSource, pXCArgs->bEn_AFAR);
418
419 u32Return = UTOPIA_STATUS_SUCCESS;
420 break;
421 }
422
423 case E_XC_HDMI_IF_CMD_GET_AVIINFOFRAMEVER:
424 {
425 pstHDMI_GET_AVIINFOFRAMEVER pXCArgs = (pstHDMI_GET_AVIINFOFRAMEVER) pArgs;
426 pXCArgs->eReturnValue = psXCInstPri->fpHDMI_Get_AVIInfoFrameVer(pInstance, pXCArgs->ucHDMIInfoSource);
427
428 u32Return = UTOPIA_STATUS_SUCCESS;
429 break;
430 }
431
432 case E_XC_HDMI_IF_CMD_ERR_STATUS_UPDATE:
433 {
434 pstHDMI_ERR_STATUS_UPDATE pXCArgs = (pstHDMI_ERR_STATUS_UPDATE) pArgs;
435 pXCArgs->u8ReturnValue = psXCInstPri->fpHDMI_err_status_update(pInstance, pXCArgs->ucHDMIInfoSource, pXCArgs->u8value, pXCArgs->bread);
436
437 u32Return = UTOPIA_STATUS_SUCCESS;
438 break;
439 }
440
441 case E_XC_HDMI_IF_CMD_GET_TMDS_FREQ:
442 {
443
444 pstHDMI_GET_TMDS_FREQ pXCArgs = (pstHDMI_GET_TMDS_FREQ) pArgs;
445 pXCArgs->u8ReturnValue = psXCInstPri->fpHDMI_Get_TMDS_freq(pInstance);
446
447 u32Return = UTOPIA_STATUS_SUCCESS;
448 break;
449 }
450
451 case E_XC_HDMI_IF_CMD_GET_POLLINGSTATUS:
452 {
453
454 pstHDMI_GET_POLLINGSTATUS pXCArgs = (pstHDMI_GET_POLLINGSTATUS) pArgs;
455 psXCInstPri->fpHDMI_Get_PollingStatus(pInstance, pXCArgs->pStatus);
456
457 u32Return = UTOPIA_STATUS_SUCCESS;
458 break;
459 }
460
461 case E_XC_HDMI_IF_CMD_ISHDMI_MODE:
462 {
463
464 pstHDMI_ISHDMI_MODE pXCArgs = (pstHDMI_ISHDMI_MODE) pArgs;
465 pXCArgs->bReturnValue = psXCInstPri->fpHDMI_IsHDMI_Mode(pInstance);
466
467 u32Return = UTOPIA_STATUS_SUCCESS;
468 break;
469 }
470
471 case E_XC_HDMI_IF_CMD_GET_MID_INFO:
472 {
473 pstHDMI_GET_MID_INFO pXCArgs = (pstHDMI_GET_MID_INFO) pArgs;
474 psXCInstPri->fpHDMI_Get_MID_info(pInstance, pXCArgs->ucHDMIInfoSource, pXCArgs->pu8ManufactorData);
475
476 u32Return = UTOPIA_STATUS_SUCCESS;
477 break;
478 }
479
480 case E_XC_HDMI_IF_CMD_GET_PACKET_VALUE:
481 {
482 pstHDMI_GET_PACKET_VALUE pXCArgs = (pstHDMI_GET_PACKET_VALUE) pArgs;
483 pXCArgs->bReturnValue = psXCInstPri->fpHDMI_get_packet_value(pInstance, pXCArgs->ucHDMIInfoSource, pXCArgs->u8state, pXCArgs->u8byte_idx, pXCArgs->pValue);
484
485 u32Return = UTOPIA_STATUS_SUCCESS;
486 break;
487 }
488
489 case E_XC_DVI_IF_CMD_CHANNELPHASESTATUS:
490 {
491
492 pstDVI_CHANNELPHASESTATUS pXCArgs = (pstDVI_CHANNELPHASESTATUS) pArgs;
493 pXCArgs->u16ReturnValue = psXCInstPri->fpDVI_ChannelPhaseStatus(pInstance, pXCArgs->u8Channel);
494
495 u32Return = UTOPIA_STATUS_SUCCESS;
496 break;
497 }
498
499 case E_XC_DVI_IF_CMD_SOFTWARERESET:
500 {
501
502 pstDVI_SOFTWARERESET pXCArgs = (pstDVI_SOFTWARERESET) pArgs;
503 psXCInstPri->fpDVI_SoftwareReset(pInstance, pXCArgs->u16Reset);
504
505 u32Return = UTOPIA_STATUS_SUCCESS;
506 break;
507 }
508
509 case E_XC_DVI_IF_CMD_RESET:
510 {
511
512 psXCInstPri->fpdvi_reset(pInstance);
513
514 u32Return = UTOPIA_STATUS_SUCCESS;
515 break;
516 }
517
518 case E_XC_HDMI_IF_CMD_AVIINFO_ACTIVEINFOPRESENT:
519 {
520 pstHDMI_GET_AVIIINFO_ACTIVEINFOPRESENT pXCArgs = (pstHDMI_GET_AVIIINFO_ACTIVEINFOPRESENT) pArgs;
521 pXCArgs->bReturnValue = psXCInstPri->fpHDMI_Get_AVIInfoActiveInfoPresent(pInstance, pXCArgs->ucHDMIInfoSource);
522
523 u32Return = UTOPIA_STATUS_SUCCESS;
524 break;
525 }
526
527 case E_XC_DVI_IF_CMD_CLKPULLLOW:
528 {
529
530 pstDVI_CLKPULLLOW pXCArgs = (pstDVI_CLKPULLLOW) pArgs;
531 psXCInstPri->fpDVI_ClkPullLow(pInstance,
532 pXCArgs->bPullLow,
533 pXCArgs->enInputPortType);
534
535 u32Return = UTOPIA_STATUS_SUCCESS;
536 break;
537 }
538
539 case E_XC_DVI_IF_CMD_SWITCHSRC:
540 {
541 pstDVI_SWITCHSRC pXCArgs = (pstDVI_SWITCHSRC) pArgs;
542 psXCInstPri->fpDVI_SwitchSrc(pInstance, pXCArgs->enInputPortType, pXCArgs->ucHDMIInfoSource);
543
544 u32Return = UTOPIA_STATUS_SUCCESS;
545 break;
546 }
547
548 case E_XC_HDMI_IF_CMD_SETFORCLOCKLESSTHAN70MHZ:
549 {
550
551 pstHDMI_SETFORCLOCKLESSTHAN70MHZ pXCArgs = (pstHDMI_SETFORCLOCKLESSTHAN70MHZ) pArgs;
552 pXCArgs->bReturnValue = psXCInstPri->fpHDMI_SetForClockLessThan70Mhz(pInstance, pXCArgs->enInputPortType);
553
554 u32Return = UTOPIA_STATUS_SUCCESS;
555 break;
556 }
557
558 case E_XC_HDMI_IF_CMD_DVI_ADJUST:
559 {
560
561 pstHDMI_DVI_ADJUST pXCArgs = (pstHDMI_DVI_ADJUST) pArgs;
562 psXCInstPri->fpHDMI_dvi_adjust(pInstance, pXCArgs->bClockLessThan70MHz);
563
564 u32Return = UTOPIA_STATUS_SUCCESS;
565 break;
566 }
567
568 case E_XC_HDMI_IF_CMD_SETUPDATEPHASELINECOUNT:
569 {
570
571 pstHDMI_SETUPDATEPHASELINECOUNT pXCArgs = (pstHDMI_SETUPDATEPHASELINECOUNT) pArgs;
572 psXCInstPri->fpHDMI_SetUpdatePhaseLineCount(pInstance, pXCArgs->enInputSourceType);
573
574 u32Return = UTOPIA_STATUS_SUCCESS;
575 break;
576 }
577
578 case E_XC_HDCP_IF_CMD_ENABLE:
579 {
580
581 pstHDCP_ENABLE pXCArgs = (pstHDCP_ENABLE) pArgs;
582 psXCInstPri->fpHDCP_Enable(pInstance, pXCArgs->bEnable);
583
584 u32Return = UTOPIA_STATUS_SUCCESS;
585 break;
586 }
587
588 case E_XC_HDMI_IF_CMD_SET_HDCP_ENABLE:
589 {
590 pstHDMI_SET_HDCPENABLE pXCArgs = (pstHDMI_SET_HDCPENABLE) pArgs;
591 pXCArgs->bReturnValue = psXCInstPri->fpHDMI_SetHdcpEnable(pInstance, pXCArgs->enInputPortType, pXCArgs->bEnable);
592
593 u32Return = UTOPIA_STATUS_SUCCESS;
594 break;
595 }
596
597 case E_XC_HDCP_IF_CMD_CLEARSTATUS:
598 {
599 psXCInstPri->fpHDCP_ClearStatus(pInstance);
600
601 u32Return = UTOPIA_STATUS_SUCCESS;
602 break;
603 }
604
605 case E_XC_HDCP_IF_CMD_INITPRODUCTIONKEY:
606 {
607 pstHDCP_INITPRODUCTIONKEY pXCArgs = (pstHDCP_INITPRODUCTIONKEY) pArgs;
608 psXCInstPri->fpHDCP_initproductionkey(pInstance, pXCArgs->pu8HdcpKeyData);
609
610 u32Return = UTOPIA_STATUS_SUCCESS;
611 break;
612 }
613
614 case E_XC_HDCP_IF_CMD_GETSTATUS:
615 {
616 pstHDCP_GETSTATUS pXCArgs = (pstHDCP_GETSTATUS)pArgs;
617 pXCArgs->usHDCPStatus = psXCInstPri->fpHDCP_GetStatus(pInstance);
618
619 u32Return = UTOPIA_STATUS_SUCCESS;
620 break;
621 }
622
623 case E_XC_HDCP_IF_CMD_VSYNC_END_EN:
624 {
625
626 pstHDCP_VSYNC_END_EN pXCArgs = (pstHDCP_VSYNC_END_EN) pArgs;
627 psXCInstPri->fpHDCP_Vsync_end_en(pInstance, pXCArgs->bStable);
628
629 u32Return = UTOPIA_STATUS_SUCCESS;
630 break;
631 }
632
633 case E_XC_HDMI_IF_CMD_AUDIO_OUTPUT:
634 {
635
636 pstHDMI_AUDIO_OUTPUT pXCArgs = (pstHDMI_AUDIO_OUTPUT) pArgs;
637 psXCInstPri->fpHDMI_audio_output(pInstance, pXCArgs->bEnable);
638
639 u32Return = UTOPIA_STATUS_SUCCESS;
640 break;
641 }
642
643 case E_XC_HDMI_IF_CMD_AUDIO_CP_HDR_INFO:
644 {
645 pstHDMI_AUDIO_CP_HDR_INFO pXCArgs = (pstHDMI_AUDIO_CP_HDR_INFO) pArgs;
646 pXCArgs->u8ReturnValue = psXCInstPri->fpHDMI_audio_cp_hdr_info(pInstance, pXCArgs->ucHDMIInfoSource);
647
648 u32Return = UTOPIA_STATUS_SUCCESS;
649 break;
650 }
651
652 case E_XC_HDMI_IF_CMD_AUDIO_CHANNEL_STATUS:
653 {
654 pstHDMI_AUDIO_CHANNEL_STATUS pXCArgs = (pstHDMI_AUDIO_CHANNEL_STATUS) pArgs;
655 pXCArgs->u8ReturnValue = psXCInstPri->fpHDMI_audio_channel_status(pInstance, pXCArgs->ucHDMIInfoSource, pXCArgs->u8byte);
656
657 u32Return = UTOPIA_STATUS_SUCCESS;
658 break;
659 }
660
661 case E_XC_HDMI_IF_CMD_GETLIBVER:
662 {
663
664 pstHDMI_GETLIBVER pXCArgs = (pstHDMI_GETLIBVER) pArgs;
665 pXCArgs->eReturnValue = psXCInstPri->fpHDMI_GetLibVer(pInstance, pXCArgs->ppVersion);
666
667 u32Return = UTOPIA_STATUS_SUCCESS;
668 break;
669 }
670
671 case E_XC_HDMI_IF_CMD_GETINFO:
672 {
673
674 pstHDMI_GETINFO pXCArgs = (pstHDMI_GETINFO) pArgs;
675 pXCArgs->eReturnValue = psXCInstPri->fpHDMI_GetInfo(pInstance, pXCArgs->pInfo);
676
677 u32Return = UTOPIA_STATUS_SUCCESS;
678 break;
679 }
680
681 case E_XC_HDMI_IF_CMD_GETSTATUS:
682 {
683
684 pstHDMI_GETSTATUS pXCArgs = (pstHDMI_GETSTATUS) pArgs;
685 pXCArgs->eReturnValue = psXCInstPri->fpHDMI_GetStatus(pInstance, pXCArgs->pStatus);
686
687 u32Return = UTOPIA_STATUS_SUCCESS;
688 break;
689 }
690
691 case E_XC_HDMI_IF_CMD_READ_DDCRAM:
692 {
693 pstHDMI_READ_DDCRAM pXCArgs = (pstHDMI_READ_DDCRAM) pArgs;
694 psXCInstPri->fpHDMI_READ_DDCRAM(pInstance, pXCArgs->pstDDCRam_Info, pXCArgs->u32SizeOfInfo);
695
696 u32Return = UTOPIA_STATUS_SUCCESS;
697 break;
698 }
699
700 case E_XC_HDMI_IF_CMD_PROG_DDCRAM:
701 {
702 pstHDMI_PROG_DDCRAM pXCArgs = (pstHDMI_PROG_DDCRAM) pArgs;
703 psXCInstPri->fpHDMI_PROG_DDCRAM(pInstance, pXCArgs->pstDDCRam_Info, pXCArgs->u32SizeOfInfo);
704
705 u32Return = UTOPIA_STATUS_SUCCESS;
706 break;
707 }
708
709 case E_XC_HDMI_IF_CMD_GET_CONTENT_TYPE:
710 {
711 pstHDMI_GET_CONTENT_TYPE pXCArgs = (pstHDMI_GET_CONTENT_TYPE) pArgs;
712 pXCArgs->enReturnValue = psXCInstPri->fpHDMI_Get_Content_Type(pInstance, pXCArgs->ucHDMIInfoSource);
713
714 u32Return = UTOPIA_STATUS_SUCCESS;
715 break;
716 }
717
718 case E_XC_HDMI_IF_CMD_GET_EXTCOLORIMETRY:
719 {
720 pstHDMI_GET_EXT_COLORIMETRY pXCArgs = (pstHDMI_GET_EXT_COLORIMETRY) pArgs;
721 pXCArgs->enReturnValue = psXCInstPri->fpHDMI_Get_Ext_Colorimetry(pInstance, pXCArgs->ucHDMIInfoSource);
722
723 u32Return = UTOPIA_STATUS_SUCCESS;
724 break;
725 }
726
727 case E_XC_HDMI_IF_CMD_GET_PIXEL_REPETITION:
728 {
729 pstHDMI_GET_PIXEL_REPETITION pXCArgs = (pstHDMI_GET_PIXEL_REPETITION) pArgs;
730 pXCArgs->u8ReturnValue = psXCInstPri->fpHDMI_Get_Pixel_Repetition(pInstance, pXCArgs->ucHDMIInfoSource);
731
732 u32Return = UTOPIA_STATUS_SUCCESS;
733 break;
734 }
735
736 case E_XC_HDMI_IF_CMD_CHECK_4K2K:
737 {
738 pstHDMI_CHECK_4K2K pXCArgs = (pstHDMI_CHECK_4K2K) pArgs;
739 pXCArgs->bReturnValue = psXCInstPri->fpHDMI_Check4K2K(pInstance, pXCArgs->ucHDMIInfoSource);
740
741 u32Return = UTOPIA_STATUS_SUCCESS;
742 break;
743 }
744
745 case E_XC_HDMI_IF_CMD_3D_4KX2K_PROCESS:
746 {
747 pstHDMI_3D_4K2K_PROCESS pXCArgs = (pstHDMI_3D_4K2K_PROCESS) pArgs;
748 psXCInstPri->fpHDMI_3D_4Kx2K_Process(pInstance, pXCArgs->ucHDMIInfoSource);
749
750 u32Return = UTOPIA_STATUS_SUCCESS;
751 break;
752 }
753
754 case E_XC_HDMI_IF_CMD_AVG_SCALERINGDOWN:
755 {
756 pstHDMI_AVG_SCALERINGDOWN pXCArgs = (pstHDMI_AVG_SCALERINGDOWN) pArgs;
757 psXCInstPri->fpHDMI_AVG_ScaleringDown(pInstance, pXCArgs->ucHDMIInfoSource, pXCArgs->bTrue);
758
759 u32Return = UTOPIA_STATUS_SUCCESS;
760 break;
761 }
762
763 case E_XC_HDMI_IF_CMD_CHECK_ADDITIONAL_FORMAT:
764 {
765 pstHDMI_CHECK_ADDITIONAL_FORMAT pXCArgs = (pstHDMI_CHECK_ADDITIONAL_FORMAT) pArgs;
766 pXCArgs->eReturnValue = psXCInstPri->fpHDMI_Check_Additional_Format(pInstance, pXCArgs->ucHDMIInfoSource);
767
768 u32Return = UTOPIA_STATUS_SUCCESS;
769 break;
770 }
771
772 case E_XC_HDMI_IF_CMD_GET_3D_STRUCTURE:
773 {
774 pstHDMI_GET_3D_STRUCTURE pXCArgs = (pstHDMI_GET_3D_STRUCTURE) pArgs;
775 pXCArgs->eReturnValue = psXCInstPri->fpHDMI_Get_3D_Structure(pInstance, pXCArgs->ucHDMIInfoSource);
776
777 u32Return = UTOPIA_STATUS_SUCCESS;
778 break;
779 }
780
781 case E_XC_HDMI_CMD_GET_3D_EXT_DATA:
782 {
783 pstHDMI_GET_3D_EXT_DATA pXCArgs = (pstHDMI_GET_3D_EXT_DATA) pArgs;
784 pXCArgs->eReturnValue = psXCInstPri->fpHDMI_Get_3D_Ext_Data(pInstance, pXCArgs->ucHDMIInfoSource);
785
786 u32Return = UTOPIA_STATUS_SUCCESS;
787 break;
788 }
789
790 case E_XC_HDMI_IF_CMD_GET_3D_META_FIELD:
791 {
792 pstHDMI_GET_3D_META_FIELD pXCArgs = (pstHDMI_GET_3D_META_FIELD) pArgs;
793 psXCInstPri->fpHDMI_Get_3D_Meta_Field(pInstance, pXCArgs->ucHDMIInfoSource, pXCArgs->pdata);
794
795 u32Return = UTOPIA_STATUS_SUCCESS;
796 break;
797 }
798
799 case E_XC_HDMI_IF_CMD_GET_VIC_CODE:
800 {
801 pstHDMI_GET_VIC_CODE pXCArgs = (pstHDMI_GET_VIC_CODE) pArgs;
802 pXCArgs->u8ReturnValue = psXCInstPri->fpHDMI_Get_VIC_Code(pInstance, pXCArgs->ucHDMIInfoSource);
803
804 u32Return = UTOPIA_STATUS_SUCCESS;
805 break;
806 }
807
808 case E_XC_HDMI_IF_CMD_GET_4KX2K_VIC_CODE:
809 {
810 pstHDMI_GET_4KX2K_VIC_CODE pXCArgs = (pstHDMI_GET_4KX2K_VIC_CODE) pArgs;
811 pXCArgs->eReturnValue = psXCInstPri->fpHDMI_Get_4Kx2K_VIC_Code(pInstance, pXCArgs->ucHDMIInfoSource);
812
813 u32Return = UTOPIA_STATUS_SUCCESS;
814 break;
815 }
816
817 case E_XC_HDMI_IF_CMD_ARC_PINCONTROL:
818 {
819 pstHDMI_ARC_PINCONTROL pXCArgs = (pstHDMI_ARC_PINCONTROL) pArgs;
820 psXCInstPri->fpHDMI_ARC_PINControl(pInstance,
821 pXCArgs->enInputPortType,
822 pXCArgs->bEnable,
823 pXCArgs->bDrivingHigh);
824
825 u32Return = UTOPIA_STATUS_SUCCESS;
826 break;
827 }
828
829 case E_XC_HDMI_IF_CMD_DVI_SOFTWARE_RESET:
830 {
831 pstDVI_SOFTWARE_RESET pXCArgs = (pstDVI_SOFTWARE_RESET) pArgs;
832 psXCInstPri->fpDVI_Software_Reset(pInstance,
833 pXCArgs->enInputPortType,
834 pXCArgs->u16Reset);
835
836 u32Return = UTOPIA_STATUS_SUCCESS;
837 break;
838 }
839
840 case E_XC_HDMI_IF_CMD_SET_POWERSTATE:
841 {
842 pstHDMI_SET_POWERSTATE pXCArgs = (pstHDMI_SET_POWERSTATE) pArgs;
843 pXCArgs->u32ReturnValue = psXCInstPri->fpHDMI_Set_PowerState(pInstance, pXCArgs->enPowerState);
844
845 u32Return = UTOPIA_STATUS_SUCCESS;
846 break;
847 }
848
849 case E_XC_HDMI_IF_CMD_DVI_HF_ADJUST:
850 {
851 psXCInstPri->fpHDMI_dvi_hf_adjust(pInstance);
852
853 u32Return = UTOPIA_STATUS_SUCCESS;
854 break;
855 }
856
857 case E_XC_HDMI_IF_CMD_CHECK_HDMI20_SETTING:
858 {
859 pstHDMI_CHECK_HDMI20_SETTING pXCArgs = (pstHDMI_CHECK_HDMI20_SETTING) pArgs;
860 pXCArgs->bReturnValue = psXCInstPri->fpHDMI_checkhdmi20_setting(pInstance, pXCArgs->enInputPortType);
861
862 u32Return = UTOPIA_STATUS_SUCCESS;
863 break;
864 }
865
866 case E_XC_HDMI_IF_CMD_SET_5V_DETECT_GPIO_SELECT:
867 {
868 pstHDMI_SET_5V_DETECT_GPIO_SELECT pXCArgs = (pstHDMI_SET_5V_DETECT_GPIO_SELECT) pArgs;
869 psXCInstPri->fpHDMI_Set5VDetectGPIOSelect(pInstance, pXCArgs->ul5VDetectGPIOSelect);
870
871 u32Return = UTOPIA_STATUS_SUCCESS;
872 break;
873 }
874
875 case E_XC_HDMI_IF_CMD_GET_DE_STABLE_STATUS:
876 {
877 pstHDMI_GET_DE_STABLE_STATUS pXCArgs = (pstHDMI_GET_DE_STABLE_STATUS) pArgs;
878 pXCArgs->bStatus = psXCInstPri->fpHDMI_GetDEStableStatus(pInstance, pXCArgs->enInputPortType);
879
880 u32Return = UTOPIA_STATUS_SUCCESS;
881 break;
882 }
883
884 case E_XC_HDMI_IF_CMD_CTRL:
885 {
886 pstHDMI_CONTROL pXCArgs = (pstHDMI_CONTROL)pArgs;
887 pXCArgs->bRet = psXCInstPri->fpHDMI_Ctrl(pInstance, pXCArgs->ucHDMIInfoSource, pXCArgs->u32Cmd, pXCArgs->pBuf, pXCArgs->u32BufSize);
888
889 u32Return = UTOPIA_STATUS_SUCCESS;
890 break;
891 }
892 case E_XC_HDMI_IF_CMD_GET_DATA_INFO:
893 {
894 pstHDMI_GET_DATA_INFO pXCArgs = (pstHDMI_GET_DATA_INFO)pArgs;
895 pXCArgs->usReturnValue = psXCInstPri->fpHDMI_GetDataInfo(pInstance, pXCArgs->enInfo, pXCArgs->ucHDMIInfoSource);
896
897 u32Return = UTOPIA_STATUS_SUCCESS;
898 break;
899 }
900
901 case E_XC_HDMI_IF_CMD_NONE:
902 case E_XC_HDMI_IF_CMD_MAX:
903 default:
904 {
905 MAPI_HDMIRX_MSG_WARNING("Command %td is not existed\n",(ptrdiff_t)u32Cmd);
906 u32Return = UTOPIA_STATUS_ERR_INVALID_HANDLE;
907 break;
908 }
909 }
910 return u32Return;
911 }
912
913 //**************************************************************************
914 // [Function Name]:
915 // HDMIRxOpen()
916 // [Description]
917 //
918 // [Arguments]:
919 //
920 // [Return]:
921 //
922 //**************************************************************************
HDMIRxOpen(void ** ppInstance,const void * const pAttribute)923 MS_U32 HDMIRxOpen(void** ppInstance, const void* const pAttribute)
924 {
925 HDMI_RX_INSTANT_PRIVATE *psHDMIRxInstPri = NULL;
926
927 //UTOPIA_TRACE(MS_UTOPIA_DB_LEVEL_TRACE,printf("enter %s %d\n",__FUNCTION__,__LINE__));
928 // instance is allocated here, also can allocate private for internal use, ex, BDMA_INSTANT_PRIVATE
929 UtopiaInstanceCreate(sizeof(HDMI_RX_INSTANT_PRIVATE), ppInstance);
930 // setup func in private and assign the calling func in func ptr in instance private
931 UtopiaInstanceGetPrivate(*ppInstance, (void**)&psHDMIRxInstPri);
932
933 psHDMIRxInstPri->fpHDMIRxInitial = (IOCTL_HDMIRX_INITIAL)mdrv_HDMI_InitialSetting;
934 psHDMIRxInstPri->fpHDMIRxStablePolling = (IOCTL_HDMIRX_STABLE_POLLING)mdrv_HDMI_StablePolling;
935 psHDMIRxInstPri->fpHDMIRxGetSourceVersion = (IOCTL_HDMIRX_GET_SOURCE_VERSION)mdrv_HDMI_GetSourceVersion;
936 psHDMIRxInstPri->fpHDMIRxCheckHDCPState = (IOCTL_HDMIRX_CHECK_HDCP_STATE)mdrv_HDMI_CheckHDCPState;
937 psHDMIRxInstPri->fpHDMIRxCheckHDCPENCState = (IOCTL_HDMIRX_CHECK_HDCP_ENC_STATE)mdrv_HDMI_CheckHDCPENCState;
938 psHDMIRxInstPri->fpHDMIRxCheckHDCP14KeyVaild = (IOCTL_HDMIRX_CHECK_HDCP14_KEY_VAILD)mdrv_HDMI_CheckHDCP14KeyVaild;
939 psHDMIRxInstPri->fpHDMIRxGetHDCP14KeyVaildFlag = (IOCTL_HDMIRX_GET_HDCP14_KEY_VAILD_FLAG)mdrv_HDMI_GetHDCP14KeyVaildFlag;
940 psHDMIRxInstPri->fpHDMIRxSetHPDInvertFlag = (IOCTL_HDMIRX_SET_HPD_INVERT_FLAG)mdrv_HDMI_SetHPDInvertFlag;
941 psHDMIRxInstPri->fpHDMIRxGetPacketReceive = (IOCTL_HDMIRX_GET_PACKET_RECEIVE)mdrv_HDMI_GetPacketReceiveStatus;
942 /*************************** HDCP Repeater ***************************/
943 psHDMIRxInstPri->fpHDMIRxWriteX74 = (IOCTL_HDMIRX_WRITE_X74)mdrv_HDCP_WriteX74;
944 psHDMIRxInstPri->fpHDMIRxReadX74 = (IOCTL_HDMIRX_READ_X74)mdrv_HDCP_ReadX74;
945 psHDMIRxInstPri->fpHDMIRxSetRepeater = (IOCTL_HDMIRX_SET_REPEATER)mdrv_HDCP_SetRepeater;
946 psHDMIRxInstPri->fpHDMIRxSetBstatus = (IOCTL_HDMIRX_SET_BSTATUS)mdrv_HDCP_SetBstatus;
947 psHDMIRxInstPri->fpHDMIRxSetHDMIMode = (IOCTL_HDMIRX_SET_HDMI_MODE)mdrv_HDCP_SetHDMIMode;
948 psHDMIRxInstPri->fpHDMIRxGetInterruptStatus = (IOCTL_HDMIRX_GET_INTERRUPT_STATUS)mdrv_HDCP_GetInterruptStatus;
949 psHDMIRxInstPri->fpHDMIRxWriteKSVList = (IOCTL_HDMIRX_WRITE_KSV_LIST)mdrv_HDCP_WriteKSVList;
950 psHDMIRxInstPri->fpHDMIRxSetVPrime = (IOCTL_HDMIRX_SET_VPRIME)mdrv_HDCP_SetVPrime;
951 /*************************** HDCP Repeater ***************************/
952 psHDMIRxInstPri->fpHDMIRxFillCipherKey = (IOCTL_HDMIRX_FILL_CIPHER_KEY)mdrv_HDCP22_FillCipherKey;
953 psHDMIRxInstPri->fpHDMIRxPortInit = (IOCTL_HDMIRX_PORT_INIT)mdrv_HDCP22_PortInit;
954 psHDMIRxInstPri->fpHDMIRxPollingReadDone = (IOCTL_HDMIRX_POLLING_READ_DONE)mdrv_HDCP22_PollingReadDone;
955 psHDMIRxInstPri->fpHDMIRxEnableCipher = (IOCTL_HDMIRX_ENABLE_CIPHER)mdrv_HDCP22_EnableCipher;
956 psHDMIRxInstPri->fpHDMIRxSendMessage = (IOCTL_HDMIRX_SEND_MESSAGE)mdrv_HDCP22_SendMessage;
957 psHDMIRxInstPri->fpHDMIRxHDCP22Handler = (IOCTL_HDMIRX_HDCP22_HANDER)mdrv_HDCP22_Handler;
958 psHDMIRxInstPri->fpHDMIRxHDCP22WaitEvent = (IOCTL_HDMIRX_HDCP22_WAIT_EVENT)mdrv_HDCP22_WaitEvent;
959
960 return UTOPIA_STATUS_SUCCESS;
961 }
962
963 //**************************************************************************
964 // [Function Name]:
965 // HDMIRxIoctl()
966 // [Description]
967 //
968 // [Arguments]:
969 //
970 // [Return]:
971 //
972 //**************************************************************************
HDMIRxIoctl(void * pInstance,MS_U32 u32Cmd,void * pArgs)973 MS_U32 HDMIRxIoctl(void* pInstance, MS_U32 u32Cmd, void* pArgs)
974 {
975 void* pModule = NULL;
976 MS_U32 ulReturnValue = UTOPIA_STATUS_SUCCESS;
977 HDMI_RX_INSTANT_PRIVATE* psHDMIRxInstPri = NULL;
978
979 UtopiaInstanceGetModule(pInstance, &pModule);
980 UtopiaInstanceGetPrivate(pInstance, (void**)&psHDMIRxInstPri);
981
982 switch(u32Cmd)
983 {
984 case MAPI_CMD_HDMIRX_INITIAL:
985 {
986 pstHDMI_INITIAL_SETTING pHDMIRxArgs = (pstHDMI_INITIAL_SETTING)pArgs;
987 psHDMIRxInstPri->fpHDMIRxInitial(pInstance, pHDMIRxArgs->stInitialTable);
988 }
989 break;
990
991 case MAPI_CMD_HDMIRX_STABLE_POLLING:
992 psHDMIRxInstPri->fpHDMIRxStablePolling(pInstance);
993 break;
994
995 case MAPI_CMD_HDMIRX_GET_SOURCE_VERSION:
996 {
997 pstHDMI_GET_SOURCE_VERSION pHDMIRxArgs = (pstHDMI_GET_SOURCE_VERSION)pArgs;
998 pHDMIRxArgs->ucSourceVersion = psHDMIRxInstPri->fpHDMIRxGetSourceVersion(pInstance, pHDMIRxArgs->enInputPortType);
999 }
1000 break;
1001
1002 case MAPI_CMD_HDMIRX_CHECK_HDCP_STATE:
1003 {
1004 pstHDMI_CHECK_HDCP_STATE pHDMIRxArgs = (pstHDMI_CHECK_HDCP_STATE)pArgs;
1005 pHDMIRxArgs->ucHDCPState = psHDMIRxInstPri->fpHDMIRxCheckHDCPState(pInstance, pHDMIRxArgs->enInputPortType);
1006 }
1007 break;
1008
1009 case MAPI_CMD_HDMIRX_CHECK_HDCP_ENC_STATE:
1010 {
1011 pstHDMI_CHECK_HDCP_ENC_STATE pHDMIRxArgs = (pstHDMI_CHECK_HDCP_ENC_STATE)pArgs;
1012 pHDMIRxArgs->ucHDCPENCState = psHDMIRxInstPri->fpHDMIRxCheckHDCPENCState(pInstance, pHDMIRxArgs->enInputPortType);
1013 }
1014 break;
1015
1016 case MAPI_CMD_HDMIRX_CHECK_HDCP14_KEY:
1017 {
1018 pstHDCP_INITPRODUCTIONKEY pHDMIRxArgs = (pstHDCP_INITPRODUCTIONKEY)pArgs;
1019 psHDMIRxInstPri->fpHDMIRxCheckHDCP14KeyVaild(pInstance, pHDMIRxArgs->pu8HdcpKeyData);
1020 }
1021 break;
1022
1023 case MAPI_CMD_HDMIRX_GET_HDCP14_KEY_VAILD:
1024 {
1025 pstHDMI_GET_HDCP14_KEY_VAILD pHDMIRxArgs = (pstHDMI_GET_HDCP14_KEY_VAILD)pArgs;
1026 pHDMIRxArgs->bHDCP14KeyVaildFlag = psHDMIRxInstPri->fpHDMIRxGetHDCP14KeyVaildFlag(pInstance);
1027 }
1028 break;
1029
1030 case MAPI_CMD_HDMIRX_SET_HPD_INVERT_FLAG:
1031 {
1032 pstHDMI_SET_HPD_INVERT_FLAG pHDMIRxArgs = (pstHDMI_SET_HPD_INVERT_FLAG)pArgs;
1033 psHDMIRxInstPri->fpHDMIRxSetHPDInvertFlag(pInstance, pHDMIRxArgs->enInputPortType, pHDMIRxArgs->bInverse);
1034 }
1035 break;
1036
1037 case MAPI_CMD_HDMIRX_GET_PACKET_RECEIVE:
1038 {
1039 pstHDMI_PACKET_RECEIVED pHDMIRxArgs = (pstHDMI_PACKET_RECEIVED)pArgs;
1040 pHDMIRxArgs->ulPacketStatus = psHDMIRxInstPri->fpHDMIRxGetPacketReceive(pInstance, pHDMIRxArgs->ucHDMIInfoSource);
1041 }
1042 break;
1043
1044 /*************************** HDCP Repeater ***************************/
1045 case MAPI_CMD_HDMIRX_WRITE_X74:
1046 {
1047 pstHDCP_WRITE_X74 pHDMIRxArgs = (pstHDCP_WRITE_X74)pArgs;
1048 psHDMIRxInstPri->fpHDMIRxWriteX74(pInstance, pHDMIRxArgs->enInputPortType, pHDMIRxArgs->ucOffset, pHDMIRxArgs->ucData);
1049 }
1050 break;
1051
1052 case MAPI_CMD_HDMIRX_READ_X74:
1053 {
1054 pstHDCP_READ_X74 pHDMIRxArgs = (pstHDCP_READ_X74)pArgs;
1055 pHDMIRxArgs->ucRetData = psHDMIRxInstPri->fpHDMIRxReadX74(pInstance, pHDMIRxArgs->enInputPortType, pHDMIRxArgs->ucOffset);
1056 }
1057 break;
1058
1059 case MAPI_CMD_HDMIRX_SET_REPEATER:
1060 {
1061 pstHDCP_SET_REPEATER pHDMIRxArgs = (pstHDCP_SET_REPEATER)pArgs;
1062 psHDMIRxInstPri->fpHDMIRxSetRepeater(pInstance, pHDMIRxArgs->enInputPortType, pHDMIRxArgs->bIsRepeater);
1063 }
1064 break;
1065
1066 case MAPI_CMD_HDMIRX_SET_BSTATUS:
1067 {
1068 pstHDCP_SET_BSTATUS pHDMIRxArgs = (pstHDCP_SET_BSTATUS)pArgs;
1069 psHDMIRxInstPri->fpHDMIRxSetBstatus(pInstance, pHDMIRxArgs->enInputPortType, pHDMIRxArgs->usBstatus);
1070 }
1071 break;
1072
1073 case MAPI_CMD_HDMIRX_SET_HDMI_MODE:
1074 {
1075 pstHDCP_SET_HDMI_MODE pHDMIRxArgs = (pstHDCP_SET_HDMI_MODE)pArgs;
1076 psHDMIRxInstPri->fpHDMIRxSetHDMIMode(pInstance, pHDMIRxArgs->enInputPortType, pHDMIRxArgs->bHDMIMode);
1077 }
1078 break;
1079
1080 case MAPI_CMD_HDMIRX_GET_INTERRUPT_STATUS:
1081 {
1082 pstHDCP_GET_INTERRUPT_STATUS pHDMIRxArgs = (pstHDCP_GET_INTERRUPT_STATUS)pArgs;
1083 pHDMIRxArgs->ucRetIntStatus = psHDMIRxInstPri->fpHDMIRxGetInterruptStatus(pInstance, pHDMIRxArgs->enInputPortType);
1084 }
1085 break;
1086
1087 case MAPI_CMD_HDMIRX_WRITE_KSV_LIST:
1088 {
1089 pstHDCP_WRITE_KSV_LIST pHDMIRxArgs = (pstHDCP_WRITE_KSV_LIST)pArgs;
1090 psHDMIRxInstPri->fpHDMIRxWriteKSVList(pInstance, pHDMIRxArgs->enInputPortType, pHDMIRxArgs->pucKSV, pHDMIRxArgs->ulLen);
1091 }
1092 break;
1093
1094 case MAPI_CMD_HDMIRX_SET_VPRIME:
1095 {
1096 pstHDCP_SET_VPRIME pHDMIRxArgs = (pstHDCP_SET_VPRIME)pArgs;
1097 psHDMIRxInstPri->fpHDMIRxSetVPrime(pInstance, pHDMIRxArgs->enInputPortType, pHDMIRxArgs->pucVPrime);
1098 }
1099 break;
1100 /*************************** HDCP Repeater ***************************/
1101
1102 case MAPI_CMD_HDMIRX_HDCP22_FILL_CIPHER_KEY:
1103 {
1104 pstHDCP22_FILL_CIPHER_KEY pHDMIRxArgs = (pstHDCP22_FILL_CIPHER_KEY)pArgs;
1105 psHDMIRxInstPri->fpHDMIRxFillCipherKey(pInstance, pHDMIRxArgs->ucPortIdx, pHDMIRxArgs->pucRiv, pHDMIRxArgs->pucSessionKey);
1106 }
1107 break;
1108
1109 case MAPI_CMD_HDMIRX_HDCP22_PORT_INIT:
1110 {
1111 pstHDCP22_PORT_INIT pHDMIRxArgs = (pstHDCP22_PORT_INIT)pArgs;
1112 psHDMIRxInstPri->fpHDMIRxPortInit(pInstance, pHDMIRxArgs->ucPortIdx);
1113 }
1114 break;
1115
1116 case MAPI_CMD_HDMIRX_HDCP22_POLLING_READ_DONE:
1117 {
1118 pstHDCP22_POLLING_READ_DONE pHDMIRxArgs = (pstHDCP22_POLLING_READ_DONE)pArgs;
1119 pHDMIRxArgs->bReturnValue = psHDMIRxInstPri->fpHDMIRxPollingReadDone(pInstance, pHDMIRxArgs->ucPortIdx);
1120 }
1121 break;
1122
1123 case MAPI_CMD_HDMIRX_HDCP22_ENABLE_CIPHER:
1124 {
1125 pstHDCP22_ENABLE_CIPHER pHDMIRxArgs = (pstHDCP22_ENABLE_CIPHER)pArgs;
1126 psHDMIRxInstPri->fpHDMIRxEnableCipher(pInstance, pHDMIRxArgs->ucPortType, pHDMIRxArgs->ucPortIdx, pHDMIRxArgs->bIsEnable);
1127 }
1128 break;
1129
1130 case MAPI_CMD_HDMIRX_HDCP22_SEND_MESSAGE:
1131 {
1132 pstHDCP22_SEND_MESSAGE pHDMIRxArgs = (pstHDCP22_SEND_MESSAGE)pArgs;
1133 psHDMIRxInstPri->fpHDMIRxSendMessage(pInstance, pHDMIRxArgs->ucPortType, pHDMIRxArgs->ucPortIdx, pHDMIRxArgs->pucData, pHDMIRxArgs->dwDataLen, pHDMIRxArgs->pDummy);
1134 }
1135 break;
1136
1137 case MAPI_CMD_HDMIRX_HDCP22_HANDLER:
1138 {
1139 pstHDCP22_HANDLER pHDMIRxArgs = (pstHDCP22_HANDLER)pArgs;
1140 pHDMIRxArgs->bHdcp22RecvMsgFlag = psHDMIRxInstPri->fpHDMIRxHDCP22Handler(pInstance, pHDMIRxArgs->ucPortIdx, &pHDMIRxArgs->ucHdcp22PortType, pHDMIRxArgs->pucHdcp22MsgData, &pHDMIRxArgs->ucHdcp22MsgLen, pHDMIRxArgs->bIRQModeFlag);
1141 }
1142 break;
1143
1144 case MAPI_CMD_HDMIRX_HDCP22_WAIT_EVENT:
1145 {
1146 pstHDCP22_WAIT_EVENT pHDMIRxArgs = (pstHDCP22_WAIT_EVENT)pArgs;
1147 pHDMIRxArgs->ucHDCPWriteDoneIndex = psHDMIRxInstPri->fpHDMIRxHDCP22WaitEvent(pInstance);
1148 }
1149 break;
1150
1151 default:
1152 ulReturnValue = UTOPIA_STATUS_FAIL;
1153 break;
1154 };
1155
1156 return ulReturnValue;
1157 }
1158
1159 //**************************************************************************
1160 // [Function Name]:
1161 // HDMIRxClose()
1162 // [Description]
1163 //
1164 // [Arguments]:
1165 //
1166 // [Return]:
1167 //
1168 //**************************************************************************
HDMIRxClose(void * pInstance)1169 MS_U32 HDMIRxClose(void* pInstance)
1170 {
1171 UtopiaInstanceDelete(pInstance);
1172
1173 return TRUE;
1174 }
1175
1176 //**************************************************************************
1177 // [Function Name]:
1178 // HDMIRxSTR()
1179 // [Description]
1180 //
1181 // [Arguments]:
1182 //
1183 // [Return]:
1184 //
1185 //**************************************************************************
HDMIRxSTR(MS_U32 ulPowerState,void * pModule)1186 MS_U32 HDMIRxSTR(MS_U32 ulPowerState, void* pModule)
1187 {
1188 MS_U32 ulReturnValue = UTOPIA_STATUS_FAIL;
1189
1190 ulReturnValue = mdrv_HDMI_STREventProc(pModule, (EN_POWER_MODE)ulPowerState);
1191
1192 return ulReturnValue;
1193 }
1194
1195 #ifdef CONFIG_UTOPIA_PROC_DBG_SUPPORT
1196 //**************************************************************************
1197 // [Function Name]:
1198 // HDMIRxMdbIoctl()
1199 // [Description]
1200 //
1201 // [Arguments]:
1202 //
1203 // [Return]:
1204 //
1205 //**************************************************************************
HDMIRxMdbIoctl(MS_U32 cmd,const void * const pArgs)1206 MS_U32 HDMIRxMdbIoctl(MS_U32 cmd, const void* const pArgs)
1207 {
1208 void* pInstance = NULL;
1209 MS_U32 ulReturnValue = UTOPIA_STATUS_SUCCESS;
1210 MDBCMD_CMDLINE_PARAMETER *paraCmdLine;
1211 MDBCMD_GETINFO_PARAMETER *paraGetInfo;
1212
1213 pInstance = UtopiaModuleGetLocalInstantList(MODULE_HDMIRX, pInstance);
1214
1215 switch(cmd)
1216 {
1217 case MDBCMD_CMDLINE:
1218 paraCmdLine = (MDBCMD_CMDLINE_PARAMETER *)pArgs;
1219 MdbPrint(paraCmdLine->u64ReqHdl,"u32CmdSize: %d\n", paraCmdLine->u32CmdSize);
1220 mdrv_HDMI_MDCMDEchoCommand(pInstance, paraCmdLine->u64ReqHdl, paraCmdLine->pcCmdLine);
1221 paraCmdLine->result = MDBRESULT_SUCCESS_FIN;
1222 break;
1223
1224 case MDBCMD_GETINFO:
1225 paraGetInfo = (MDBCMD_GETINFO_PARAMETER *)pArgs;
1226 mdrv_HDMI_MDCMDGetInfo(pInstance, paraGetInfo->u64ReqHdl);
1227 paraGetInfo->result = MDBRESULT_SUCCESS_FIN;
1228 break;
1229
1230 default:
1231 paraGetInfo = (MDBCMD_GETINFO_PARAMETER *)pArgs;
1232 MdbPrint(paraGetInfo->u64ReqHdl,"unknown cmd\n", __LINE__);
1233 break;
1234 };
1235
1236 return ulReturnValue;
1237 }
1238 #endif
1239
1240 //**************************************************************************
1241 // [Function Name]:
1242 // HDMIRXRegisterToUtopia()
1243 // [Description]
1244 //
1245 // [Arguments]:
1246 //
1247 // [Return]:
1248 //
1249 //**************************************************************************
HDMIRXRegisterToUtopia(FUtopiaOpen ModuleType)1250 void HDMIRXRegisterToUtopia(FUtopiaOpen ModuleType)
1251 {
1252 void* pUtopiaModule = NULL;
1253 void* psResource = NULL;
1254
1255 // 1. deal with module
1256 UtopiaModuleCreate(MODULE_HDMIRX, 0, &pUtopiaModule);
1257 UtopiaModuleRegister(pUtopiaModule);
1258 // register func for module, after register here, then ap call UtopiaOpen/UtopiaIoctl/UtopiaClose can call to these registered standard func
1259 UtopiaModuleSetupFunctionPtr(pUtopiaModule, (FUtopiaOpen)HDMIRxOpen, (FUtopiaClose)HDMIRxClose, (FUtopiaIOctl)HDMIRxIoctl);
1260
1261 #if(defined(MSOS_TYPE_LINUX_KERNEL))
1262 UtopiaModuleSetupSTRFunctionPtr(pUtopiaModule, (FUtopiaSTR)HDMIRxSTR);
1263 #endif
1264
1265 #ifdef CONFIG_UTOPIA_PROC_DBG_SUPPORT
1266 UtopiaModuleRegisterMdbNode("HDMIRX", (FUtopiaMdbIoctl)HDMIRxMdbIoctl);
1267 #endif
1268
1269 // 2. deal with resource
1270 // start func to add res, call once will create 2 access in resource. Also can declare BDMA_POOL_ID_BDMA1 for another channel depend on driver owner.
1271 UtopiaModuleAddResourceStart(pUtopiaModule, HDMI_RX_POOL);
1272 // resource can alloc private for internal use, ex, BDMA_RESOURCE_PRIVATE
1273 UtopiaResourceCreate("HDMIRX", sizeof(HDMI_RX_RESOURCE_PRIVATE), &psResource);
1274 // func to reg res
1275 UtopiaResourceRegister(pUtopiaModule, psResource, HDMI_RX_POOL);
1276
1277 UtopiaModuleAddResourceEnd(pUtopiaModule, HDMI_RX_POOL);
1278 }
1279
1280 #endif // _API_HDMI_RX_V2_C_
1281
1282