1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ARCH_H 9 #define ARCH_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MIDR bit definitions 15 ******************************************************************************/ 16 #define MIDR_IMPL_MASK U(0xff) 17 #define MIDR_IMPL_SHIFT U(0x18) 18 #define MIDR_VAR_SHIFT U(20) 19 #define MIDR_VAR_BITS U(4) 20 #define MIDR_VAR_MASK U(0xf) 21 #define MIDR_REV_SHIFT U(0) 22 #define MIDR_REV_BITS U(4) 23 #define MIDR_REV_MASK U(0xf) 24 #define MIDR_PN_MASK U(0xfff) 25 #define MIDR_PN_SHIFT U(0x4) 26 27 /* Extracts the CPU part number from MIDR for checking CPU match */ 28 #define EXTRACT_PARTNUM(x) ((x >> MIDR_PN_SHIFT) & MIDR_PN_MASK) 29 30 /******************************************************************************* 31 * MPIDR macros 32 ******************************************************************************/ 33 #define MPIDR_MT_MASK (ULL(1) << 24) 34 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 35 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 36 #define MPIDR_AFFINITY_BITS U(8) 37 #define MPIDR_AFFLVL_MASK ULL(0xff) 38 #define MPIDR_AFF0_SHIFT U(0) 39 #define MPIDR_AFF1_SHIFT U(8) 40 #define MPIDR_AFF2_SHIFT U(16) 41 #define MPIDR_AFF3_SHIFT U(32) 42 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 43 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 44 #define MPIDR_AFFLVL_SHIFT U(3) 45 #define MPIDR_AFFLVL0 ULL(0x0) 46 #define MPIDR_AFFLVL1 ULL(0x1) 47 #define MPIDR_AFFLVL2 ULL(0x2) 48 #define MPIDR_AFFLVL3 ULL(0x3) 49 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 50 #define MPIDR_AFFLVL0_VAL(mpidr) \ 51 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 52 #define MPIDR_AFFLVL1_VAL(mpidr) \ 53 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 54 #define MPIDR_AFFLVL2_VAL(mpidr) \ 55 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 56 #define MPIDR_AFFLVL3_VAL(mpidr) \ 57 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 58 /* 59 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 60 * add one while using this macro to define array sizes. 61 * TODO: Support only the first 3 affinity levels for now. 62 */ 63 #define MPIDR_MAX_AFFLVL U(2) 64 65 #define MPID_MASK (MPIDR_MT_MASK | \ 66 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 67 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 68 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 69 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 70 71 #define MPIDR_AFF_ID(mpid, n) \ 72 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 73 74 /* 75 * An invalid MPID. This value can be used by functions that return an MPID to 76 * indicate an error. 77 */ 78 #define INVALID_MPID U(0xFFFFFFFF) 79 80 /******************************************************************************* 81 * Definitions for Exception vector offsets 82 ******************************************************************************/ 83 #define CURRENT_EL_SP0 0x0 84 #define CURRENT_EL_SPX 0x200 85 #define LOWER_EL_AARCH64 0x400 86 #define LOWER_EL_AARCH32 0x600 87 88 #define SYNC_EXCEPTION 0x0 89 #define IRQ_EXCEPTION 0x80 90 #define FIQ_EXCEPTION 0x100 91 #define SERROR_EXCEPTION 0x180 92 93 /******************************************************************************* 94 * Encodings for GICv5 EL3 system registers 95 ******************************************************************************/ 96 #define ICC_PPI_DOMAINR0_EL3 S3_6_C12_C8_4 97 #define ICC_PPI_DOMAINR1_EL3 S3_6_C12_C8_5 98 #define ICC_PPI_DOMAINR2_EL3 S3_6_C12_C8_6 99 #define ICC_PPI_DOMAINR3_EL3 S3_6_C12_C8_7 100 101 #define ICC_PPI_DOMAINR_FIELD_MASK ULL(0x3) 102 #define ICC_PPI_DOMAINR_COUNT (32) 103 104 /******************************************************************************* 105 * Definitions for CPU system register interface to GICv3 106 ******************************************************************************/ 107 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 108 #define ICC_SGI1R S3_0_C12_C11_5 109 #define ICC_ASGI1R S3_0_C12_C11_6 110 #define ICC_SRE_EL1 S3_0_C12_C12_5 111 #define ICC_SRE_EL2 S3_4_C12_C9_5 112 #define ICC_SRE_EL3 S3_6_C12_C12_5 113 #define ICC_CTLR_EL1 S3_0_C12_C12_4 114 #define ICC_CTLR_EL3 S3_6_C12_C12_4 115 #define ICC_PMR_EL1 S3_0_C4_C6_0 116 #define ICC_RPR_EL1 S3_0_C12_C11_3 117 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 118 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 119 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 120 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 121 #define ICC_IAR0_EL1 S3_0_c12_c8_0 122 #define ICC_IAR1_EL1 S3_0_c12_c12_0 123 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 124 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 125 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 126 127 /******************************************************************************* 128 * Definitions for EL2 system registers for save/restore routine 129 ******************************************************************************/ 130 #define CNTPOFF_EL2 S3_4_C14_C0_6 131 #define HDFGRTR2_EL2 S3_4_C3_C1_0 132 #define HDFGWTR2_EL2 S3_4_C3_C1_1 133 #define HFGRTR2_EL2 S3_4_C3_C1_2 134 #define HFGWTR2_EL2 S3_4_C3_C1_3 135 #define HDFGRTR_EL2 S3_4_C3_C1_4 136 #define HDFGWTR_EL2 S3_4_C3_C1_5 137 #define HAFGRTR_EL2 S3_4_C3_C1_6 138 #define HFGITR2_EL2 S3_4_C3_C1_7 139 #define HFGITR_EL2 S3_4_C1_C1_6 140 #define HFGRTR_EL2 S3_4_C1_C1_4 141 #define HFGWTR_EL2 S3_4_C1_C1_5 142 #define ICH_HCR_EL2 S3_4_C12_C11_0 143 #define ICH_VMCR_EL2 S3_4_C12_C11_7 144 #define MPAMVPM0_EL2 S3_4_C10_C6_0 145 #define MPAMVPM1_EL2 S3_4_C10_C6_1 146 #define MPAMVPM2_EL2 S3_4_C10_C6_2 147 #define MPAMVPM3_EL2 S3_4_C10_C6_3 148 #define MPAMVPM4_EL2 S3_4_C10_C6_4 149 #define MPAMVPM5_EL2 S3_4_C10_C6_5 150 #define MPAMVPM6_EL2 S3_4_C10_C6_6 151 #define MPAMVPM7_EL2 S3_4_C10_C6_7 152 #define MPAMVPMV_EL2 S3_4_C10_C4_1 153 #define VNCR_EL2 S3_4_C2_C2_0 154 #define PMSCR_EL2 S3_4_C9_C9_0 155 #define TFSR_EL2 S3_4_C5_C6_0 156 #define CONTEXTIDR_EL2 S3_4_C13_C0_1 157 #define TTBR1_EL2 S3_4_C2_C0_1 158 159 /******************************************************************************* 160 * Generic timer memory mapped registers & offsets 161 ******************************************************************************/ 162 #define CNTCR_OFF U(0x000) 163 #define CNTCV_OFF U(0x008) 164 #define CNTFID_OFF U(0x020) 165 166 #define CNTCR_EN (U(1) << 0) 167 #define CNTCR_HDBG (U(1) << 1) 168 #define CNTCR_FCREQ(x) ((x) << 8) 169 170 /******************************************************************************* 171 * System register bit definitions 172 ******************************************************************************/ 173 /* CLIDR definitions */ 174 #define LOUIS_SHIFT U(21) 175 #define LOC_SHIFT U(24) 176 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 177 #define CLIDR_FIELD_WIDTH U(3) 178 179 /* CSSELR definitions */ 180 #define LEVEL_SHIFT U(1) 181 182 /* Data cache set/way op type defines */ 183 #define DCISW U(0x0) 184 #define DCCISW U(0x1) 185 #if ERRATA_A53_827319 186 #define DCCSW DCCISW 187 #else 188 #define DCCSW U(0x2) 189 #endif 190 191 #define ID_REG_FIELD_MASK ULL(0xf) 192 193 /******************************************************************************* 194 * PFR0_EL1 - Definitions for AArch32 Processor Feature Register 0 195 ******************************************************************************/ 196 #define ID_PFR0_EL1 S3_0_C0_C1_0 197 198 /******************************************************************************* 199 * PFR2_EL1 - Definitions for AArch32 Processor Feature Register 2 200 ******************************************************************************/ 201 #define ID_PFR2_EL1 S3_0_C0_C3_4 202 203 /******************************************************************************* 204 * ID_ISAR6_EL1 - Definition for AArch32 Instruction Set Attribute Register 6 205 ******************************************************************************/ 206 #define ID_ISAR6_EL1 S3_0_C0_C2_7 207 208 /******************************************************************************* 209 * ID_DFR1_EL1 - Definition for AArch32 Debug Feature Register 1 210 ******************************************************************************/ 211 #define ID_DFR1_EL1 S3_0_C0_C3_5 212 213 /* ID_AA64PFR0_EL1 definitions */ 214 #define ID_AA64PFR0_EL0_SHIFT U(0) 215 #define ID_AA64PFR0_EL1_SHIFT U(4) 216 #define ID_AA64PFR0_EL2_SHIFT U(8) 217 #define ID_AA64PFR0_EL3_SHIFT U(12) 218 219 #define ID_AA64PFR0_AMU_SHIFT U(44) 220 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 221 #define ID_AA64PFR0_AMU_V1 ULL(0x1) 222 #define ID_AA64PFR0_AMU_V1P1 U(0x2) 223 224 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 225 #define ID_AA64PFR0_EL0_MASK ID_AA64PFR0_ELX_MASK 226 #define ID_AA64PFR0_EL1_MASK ID_AA64PFR0_ELX_MASK 227 #define ID_AA64PFR0_EL2_MASK ID_AA64PFR0_ELX_MASK 228 #define ID_AA64PFR0_EL3_MASK ID_AA64PFR0_ELX_MASK 229 230 #define ID_AA64PFR0_GIC_SHIFT U(24) 231 #define ID_AA64PFR0_GIC_WIDTH U(4) 232 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 233 234 #define ID_AA64PFR0_SVE_SHIFT U(32) 235 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 236 #define ID_AA64PFR0_SVE_LENGTH U(4) 237 #define SVE_IMPLEMENTED ULL(0x1) 238 239 #define ID_AA64PFR0_SEL2_SHIFT U(36) 240 #define ID_AA64PFR0_SEL2_MASK ULL(0xf) 241 242 #define ID_AA64PFR0_MPAM_SHIFT U(40) 243 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 244 245 #define ID_AA64PFR0_DIT_SHIFT U(48) 246 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 247 #define ID_AA64PFR0_DIT_LENGTH U(4) 248 #define DIT_IMPLEMENTED ULL(1) 249 250 #define ID_AA64PFR0_CSV2_SHIFT U(56) 251 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 252 #define ID_AA64PFR0_CSV2_LENGTH U(4) 253 #define CSV2_2_IMPLEMENTED ULL(0x2) 254 #define CSV2_3_IMPLEMENTED ULL(0x3) 255 256 #define ID_AA64PFR0_FEAT_RME_SHIFT U(52) 257 #define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf) 258 #define ID_AA64PFR0_FEAT_RME_LENGTH U(4) 259 #define RME_NOT_IMPLEMENTED ULL(0) 260 #define RME_GPC2_IMPLEMENTED ULL(0x2) 261 262 #define ID_AA64PFR0_RAS_SHIFT U(28) 263 #define ID_AA64PFR0_RAS_MASK ULL(0xf) 264 #define ID_AA64PFR0_RAS_LENGTH U(4) 265 266 /* Exception level handling */ 267 #define EL_IMPL_NONE ULL(0) 268 #define EL_IMPL_A64ONLY ULL(1) 269 #define EL_IMPL_A64_A32 ULL(2) 270 271 /* ID_AA64DFR0_EL1.DebugVer definitions */ 272 #define ID_AA64DFR0_DEBUGVER_SHIFT U(0) 273 #define ID_AA64DFR0_DEBUGVER_MASK ULL(0xf) 274 #define DEBUGVER_V8P9_IMPLEMENTED ULL(0xb) 275 276 /* ID_AA64DFR0_EL1.TraceVer definitions */ 277 #define ID_AA64DFR0_TRACEVER_SHIFT U(4) 278 #define ID_AA64DFR0_TRACEVER_MASK ULL(0xf) 279 #define ID_AA64DFR0_TRACEVER_LENGTH U(4) 280 281 #define ID_AA64DFR0_TRACEFILT_SHIFT U(40) 282 #define ID_AA64DFR0_TRACEFILT_MASK U(0xf) 283 #define ID_AA64DFR0_TRACEFILT_LENGTH U(4) 284 #define TRACEFILT_IMPLEMENTED ULL(1) 285 286 #define ID_AA64DFR0_PMUVER_LENGTH U(4) 287 #define ID_AA64DFR0_PMUVER_SHIFT U(8) 288 #define ID_AA64DFR0_PMUVER_MASK U(0xf) 289 #define ID_AA64DFR0_PMUVER_PMUV3 U(1) 290 #define ID_AA64DFR0_PMUVER_PMUV3P9 U(9) 291 #define ID_AA64DFR0_PMUVER_IMP_DEF U(0xf) 292 293 /* ID_AA64DFR0_EL1.SEBEP definitions */ 294 #define ID_AA64DFR0_SEBEP_SHIFT U(24) 295 #define ID_AA64DFR0_SEBEP_MASK ULL(0xf) 296 #define SEBEP_IMPLEMENTED ULL(1) 297 298 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 299 #define ID_AA64DFR0_PMS_SHIFT U(32) 300 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 301 #define SPE_IMPLEMENTED ULL(0x1) 302 #define SPE_NOT_IMPLEMENTED ULL(0x0) 303 304 /* ID_AA64DFR0_EL1.TraceBuffer definitions */ 305 #define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44) 306 #define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf) 307 #define TRACEBUFFER_IMPLEMENTED ULL(1) 308 309 /* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */ 310 #define ID_AA64DFR0_MTPMU_SHIFT U(48) 311 #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) 312 #define MTPMU_IMPLEMENTED ULL(1) 313 #define MTPMU_NOT_IMPLEMENTED ULL(15) 314 315 /* ID_AA64DFR0_EL1.BRBE definitions */ 316 #define ID_AA64DFR0_BRBE_SHIFT U(52) 317 #define ID_AA64DFR0_BRBE_MASK ULL(0xf) 318 #define BRBE_IMPLEMENTED ULL(1) 319 320 /* ID_AA64DFR1_EL1 definitions */ 321 #define ID_AA64DFR1_EBEP_SHIFT U(48) 322 #define ID_AA64DFR1_EBEP_MASK ULL(0xf) 323 #define EBEP_IMPLEMENTED ULL(1) 324 325 #define ID_AA64DFR1_BRP_SHIFT U(8) 326 #define ID_AA64DFR1_BRP_WIDTH U(8) 327 328 #define ID_AA64ZFR0_EL1 S3_0_C0_C4_4 329 #define ID_AA64FPFR0_EL1 S3_0_C0_C4_7 330 #define ID_AA64DFR2_EL1 S3_0_C0_C5_2 331 #define GMID_EL1 S3_1_C0_C0_4 332 333 /* ID_AA64ISAR0_EL1 definitions */ 334 #define ID_AA64ISAR0_RNDR_SHIFT U(60) 335 #define ID_AA64ISAR0_RNDR_MASK ULL(0xf) 336 337 /* ID_AA64ISAR1_EL1 definitions */ 338 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 339 340 #define ID_AA64ISAR1_LS64_SHIFT U(60) 341 #define ID_AA64ISAR1_LS64_MASK ULL(0xf) 342 #define LS64_ACCDATA_IMPLEMENTED ULL(0x3) 343 #define LS64_V_IMPLEMENTED ULL(0x2) 344 #define LS64_IMPLEMENTED ULL(0x1) 345 #define LS64_NOT_IMPLEMENTED ULL(0x0) 346 347 #define ID_AA64ISAR1_SB_SHIFT U(36) 348 #define ID_AA64ISAR1_SB_MASK ULL(0xf) 349 #define SB_IMPLEMENTED ULL(0x1) 350 #define SB_NOT_IMPLEMENTED ULL(0x0) 351 352 #define ID_AA64ISAR1_GPI_SHIFT U(28) 353 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 354 #define ID_AA64ISAR1_GPA_SHIFT U(24) 355 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 356 357 #define ID_AA64ISAR1_API_SHIFT U(8) 358 #define ID_AA64ISAR1_API_MASK ULL(0xf) 359 #define ID_AA64ISAR1_APA_SHIFT U(4) 360 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 361 362 /* ID_AA64ISAR2_EL1 definitions */ 363 #define ID_AA64ISAR2_EL1 S3_0_C0_C6_2 364 #define ID_AA64ISAR2_EL1_MOPS_SHIFT U(16) 365 #define ID_AA64ISAR2_EL1_MOPS_MASK ULL(0xf) 366 367 #define MOPS_IMPLEMENTED ULL(0x1) 368 369 #define ID_AA64ISAR2_GPA3_SHIFT U(8) 370 #define ID_AA64ISAR2_GPA3_MASK ULL(0xf) 371 372 #define ID_AA64ISAR2_APA3_SHIFT U(12) 373 #define ID_AA64ISAR2_APA3_MASK ULL(0xf) 374 375 #define ID_AA64ISAR2_CLRBHB_SHIFT U(28) 376 #define ID_AA64ISAR2_CLRBHB_MASK ULL(0xf) 377 378 #define ID_AA64ISAR2_SYSREG128_SHIFT U(32) 379 #define ID_AA64ISAR2_SYSREG128_MASK ULL(0xf) 380 381 /* ID_AA64ISAR3_EL1 definitions */ 382 #define ID_AA64ISAR3_EL1 S3_0_C0_C6_3 383 #define ID_AA64ISAR3_EL1_CPA_SHIFT U(0) 384 #define ID_AA64ISAR3_EL1_CPA_MASK ULL(0xf) 385 386 #define CPA2_IMPLEMENTED ULL(0x2) 387 388 /* ID_AA64MMFR0_EL1 definitions */ 389 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 390 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 391 392 #define PARANGE_0000 U(32) 393 #define PARANGE_0001 U(36) 394 #define PARANGE_0010 U(40) 395 #define PARANGE_0011 U(42) 396 #define PARANGE_0100 U(44) 397 #define PARANGE_0101 U(48) 398 #define PARANGE_0110 U(52) 399 #define PARANGE_0111 U(56) 400 401 #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) 402 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) 403 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) 404 #define ECV_IMPLEMENTED ULL(0x1) 405 406 #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) 407 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) 408 #define FGT2_IMPLEMENTED ULL(0x2) 409 #define FGT_IMPLEMENTED ULL(0x1) 410 #define FGT_NOT_IMPLEMENTED ULL(0x0) 411 412 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 413 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 414 415 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 416 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 417 418 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 419 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 420 #define TGRAN16_IMPLEMENTED ULL(0x1) 421 422 /* ID_AA64MMFR1_EL1 definitions */ 423 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) 424 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) 425 #define TWED_IMPLEMENTED ULL(0x1) 426 427 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) 428 #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf) 429 #define PAN_IMPLEMENTED ULL(0x1) 430 #define PAN2_IMPLEMENTED ULL(0x2) 431 #define PAN3_IMPLEMENTED ULL(0x3) 432 433 #define ID_AA64MMFR1_EL1_VHE_SHIFT U(8) 434 #define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf) 435 436 #define ID_AA64MMFR1_EL1_HCX_SHIFT U(40) 437 #define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf) 438 #define HCX_IMPLEMENTED ULL(0x1) 439 440 /* ID_AA64MMFR2_EL1 definitions */ 441 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 442 443 #define ID_AA64MMFR2_EL1_IDS_SHIFT U(36) 444 #define ID_AA64MMFR2_EL1_IDS_MASK ULL(0xf) 445 446 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 447 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 448 449 #define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20) 450 #define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf) 451 #define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4) 452 453 #define ID_AA64MMFR2_EL1_UAO_SHIFT U(4) 454 #define ID_AA64MMFR2_EL1_UAO_MASK ULL(0xf) 455 456 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 457 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 458 459 #define ID_AA64MMFR2_EL1_NV_SHIFT U(24) 460 #define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf) 461 #define NV2_IMPLEMENTED ULL(0x2) 462 463 /* ID_AA64MMFR3_EL1 definitions */ 464 #define ID_AA64MMFR3_EL1 S3_0_C0_C7_3 465 466 #define ID_AA64MMFR3_EL1_D128_SHIFT U(32) 467 #define ID_AA64MMFR3_EL1_D128_MASK ULL(0xf) 468 #define D128_IMPLEMENTED ULL(0x1) 469 470 #define ID_AA64MMFR3_EL1_MEC_SHIFT U(28) 471 #define ID_AA64MMFR3_EL1_MEC_MASK ULL(0xf) 472 473 #define ID_AA64MMFR3_EL1_AIE_SHIFT U(24) 474 #define ID_AA64MMFR3_EL1_AIE_MASK ULL(0xf) 475 476 #define ID_AA64MMFR3_EL1_S2POE_SHIFT U(20) 477 #define ID_AA64MMFR3_EL1_S2POE_MASK ULL(0xf) 478 479 #define ID_AA64MMFR3_EL1_S1POE_SHIFT U(16) 480 #define ID_AA64MMFR3_EL1_S1POE_MASK ULL(0xf) 481 482 #define ID_AA64MMFR3_EL1_S2PIE_SHIFT U(12) 483 #define ID_AA64MMFR3_EL1_S2PIE_MASK ULL(0xf) 484 485 #define ID_AA64MMFR3_EL1_S1PIE_SHIFT U(8) 486 #define ID_AA64MMFR3_EL1_S1PIE_MASK ULL(0xf) 487 488 #define ID_AA64MMFR3_EL1_SCTLR2_SHIFT U(4) 489 #define ID_AA64MMFR3_EL1_SCTLR2_MASK ULL(0xf) 490 #define SCTLR2_IMPLEMENTED ULL(1) 491 492 #define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0) 493 #define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf) 494 495 /* ID_AA64MMFR4_EL1 definitions */ 496 #define ID_AA64MMFR4_EL1 S3_0_C0_C7_4 497 498 #define ID_AA64MMFR4_EL1_FGWTE3_SHIFT U(16) 499 #define ID_AA64MMFR4_EL1_FGWTE3_MASK ULL(0xf) 500 #define FGWTE3_IMPLEMENTED ULL(0x1) 501 502 #define ID_AA64MMFR4_EL1_RME_GDI_SHIFT U(28) 503 #define ID_AA64MMFR4_EL1_RME_GDI_MASK ULL(0xf) 504 #define ID_AA64MMFR4_EL1_RME_GDI_LENGTH U(4) 505 #define RME_GDI_IMPLEMENTED ULL(0x1) 506 507 /* ID_AA64PFR1_EL1 definitions */ 508 509 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 510 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 511 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 512 513 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 514 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 515 #define SSBS_NOT_IMPLEMENTED ULL(0) /* No architectural SSBS support */ 516 517 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 518 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 519 520 #define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28) 521 #define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf) 522 #define RNG_TRAP_IMPLEMENTED ULL(0x1) 523 524 #define ID_AA64PFR1_EL1_NMI_SHIFT U(36) 525 #define ID_AA64PFR1_EL1_NMI_MASK ULL(0xf) 526 #define NMI_IMPLEMENTED ULL(1) 527 528 #define ID_AA64PFR1_EL1_GCS_SHIFT U(44) 529 #define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf) 530 #define GCS_IMPLEMENTED ULL(1) 531 532 #define ID_AA64PFR1_EL1_THE_SHIFT U(48) 533 #define ID_AA64PFR1_EL1_THE_MASK ULL(0xf) 534 #define THE_IMPLEMENTED ULL(1) 535 536 #define ID_AA64PFR1_EL1_PFAR_SHIFT U(60) 537 #define ID_AA64PFR1_EL1_PFAR_MASK ULL(0xf) 538 539 540 /* ID_AA64PFR2_EL1 definitions */ 541 #define ID_AA64PFR2_EL1 S3_0_C0_C4_2 542 543 #define ID_AA64PFR2_EL1_MTEPERM_SHIFT U(0) 544 #define ID_AA64PFR2_EL1_MTEPERM_MASK ULL(0xf) 545 546 #define ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT U(4) 547 #define ID_AA64PFR2_EL1_MTESTOREONLY_MASK ULL(0xf) 548 549 #define ID_AA64PFR2_EL1_MTEFAR_SHIFT U(8) 550 #define ID_AA64PFR2_EL1_MTEFAR_MASK ULL(0xf) 551 552 #define ID_AA64PFR2_EL1_FPMR_SHIFT U(32) 553 #define ID_AA64PFR2_EL1_FPMR_MASK ULL(0xf) 554 555 #define FPMR_IMPLEMENTED ULL(0x1) 556 557 #define VDISR_EL2 S3_4_C12_C1_1 558 #define VSESR_EL2 S3_4_C5_C2_3 559 560 /* Memory Tagging Extension is not implemented */ 561 #define MTE_UNIMPLEMENTED U(0) 562 /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ 563 #define MTE_IMPLEMENTED_EL0 U(1) 564 /* FEAT_MTE2: Full MTE is implemented */ 565 #define MTE_IMPLEMENTED_ELX U(2) 566 /* 567 * FEAT_MTE3: MTE is implemented with support for 568 * asymmetric Tag Check Fault handling 569 */ 570 #define MTE_IMPLEMENTED_ASY U(3) 571 572 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) 573 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) 574 575 #define ID_AA64PFR1_EL1_SME_SHIFT U(24) 576 #define ID_AA64PFR1_EL1_SME_MASK ULL(0xf) 577 #define ID_AA64PFR1_EL1_SME_WIDTH U(4) 578 #define SME_IMPLEMENTED ULL(0x1) 579 #define SME2_IMPLEMENTED ULL(0x2) 580 #define SME_NOT_IMPLEMENTED ULL(0x0) 581 582 /* ID_AA64PFR2_EL1 definitions */ 583 #define ID_AA64PFR2_EL1 S3_0_C0_C4_2 584 #define ID_AA64PFR2_EL1_GCIE_SHIFT 12 585 #define ID_AA64PFR2_EL1_GCIE_MASK ULL(0xf) 586 587 /* ID_PFR1_EL1 definitions */ 588 #define ID_PFR1_VIRTEXT_SHIFT U(12) 589 #define ID_PFR1_VIRTEXT_MASK U(0xf) 590 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 591 & ID_PFR1_VIRTEXT_MASK) 592 593 /* SCTLR definitions */ 594 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 595 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 596 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 597 598 #define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ 599 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) 600 601 #define SCTLR_AARCH32_EL1_RES1 \ 602 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 603 (U(1) << 4) | (U(1) << 3)) 604 605 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 606 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 607 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 608 609 #define SCTLR_M_BIT (ULL(1) << 0) 610 #define SCTLR_A_BIT (ULL(1) << 1) 611 #define SCTLR_C_BIT (ULL(1) << 2) 612 #define SCTLR_SA_BIT (ULL(1) << 3) 613 #define SCTLR_SA0_BIT (ULL(1) << 4) 614 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 615 #define SCTLR_nAA_BIT (ULL(1) << 6) 616 #define SCTLR_ITD_BIT (ULL(1) << 7) 617 #define SCTLR_SED_BIT (ULL(1) << 8) 618 #define SCTLR_UMA_BIT (ULL(1) << 9) 619 #define SCTLR_EnRCTX_BIT (ULL(1) << 10) 620 #define SCTLR_EOS_BIT (ULL(1) << 11) 621 #define SCTLR_I_BIT (ULL(1) << 12) 622 #define SCTLR_EnDB_BIT (ULL(1) << 13) 623 #define SCTLR_DZE_BIT (ULL(1) << 14) 624 #define SCTLR_UCT_BIT (ULL(1) << 15) 625 #define SCTLR_NTWI_BIT (ULL(1) << 16) 626 #define SCTLR_NTWE_BIT (ULL(1) << 18) 627 #define SCTLR_WXN_BIT (ULL(1) << 19) 628 #define SCTLR_TSCXT_BIT (ULL(1) << 20) 629 #define SCTLR_IESB_BIT (ULL(1) << 21) 630 #define SCTLR_EIS_BIT (ULL(1) << 22) 631 #define SCTLR_SPAN_BIT (ULL(1) << 23) 632 #define SCTLR_E0E_BIT (ULL(1) << 24) 633 #define SCTLR_EE_BIT (ULL(1) << 25) 634 #define SCTLR_UCI_BIT (ULL(1) << 26) 635 #define SCTLR_EnDA_BIT (ULL(1) << 27) 636 #define SCTLR_nTLSMD_BIT (ULL(1) << 28) 637 #define SCTLR_LSMAOE_BIT (ULL(1) << 29) 638 #define SCTLR_EnIB_BIT (ULL(1) << 30) 639 #define SCTLR_EnIA_BIT (ULL(1) << 31) 640 #define SCTLR_BT0_BIT (ULL(1) << 35) 641 #define SCTLR_BT1_BIT (ULL(1) << 36) 642 #define SCTLR_BT_BIT (ULL(1) << 36) 643 #define SCTLR_ITFSB_BIT (ULL(1) << 37) 644 #define SCTLR_TCF0_SHIFT U(38) 645 #define SCTLR_TCF0_MASK ULL(3) 646 #define SCTLR_ENTP2_BIT (ULL(1) << 60) 647 #define SCTLR_SPINTMASK_BIT (ULL(1) << 62) 648 649 /* Tag Check Faults in EL0 have no effect on the PE */ 650 #define SCTLR_TCF0_NO_EFFECT U(0) 651 /* Tag Check Faults in EL0 cause a synchronous exception */ 652 #define SCTLR_TCF0_SYNC U(1) 653 /* Tag Check Faults in EL0 are asynchronously accumulated */ 654 #define SCTLR_TCF0_ASYNC U(2) 655 /* 656 * Tag Check Faults in EL0 cause a synchronous exception on reads, 657 * and are asynchronously accumulated on writes 658 */ 659 #define SCTLR_TCF0_SYNCR_ASYNCW U(3) 660 661 #define SCTLR_TCF_SHIFT U(40) 662 #define SCTLR_TCF_MASK ULL(3) 663 664 /* Tag Check Faults in EL1 have no effect on the PE */ 665 #define SCTLR_TCF_NO_EFFECT U(0) 666 /* Tag Check Faults in EL1 cause a synchronous exception */ 667 #define SCTLR_TCF_SYNC U(1) 668 /* Tag Check Faults in EL1 are asynchronously accumulated */ 669 #define SCTLR_TCF_ASYNC U(2) 670 /* 671 * Tag Check Faults in EL1 cause a synchronous exception on reads, 672 * and are asynchronously accumulated on writes 673 */ 674 #define SCTLR_TCF_SYNCR_ASYNCW U(3) 675 676 #define SCTLR_ATA0_BIT (ULL(1) << 42) 677 #define SCTLR_ATA_BIT (ULL(1) << 43) 678 #define SCTLR_DSSBS_SHIFT U(44) 679 #define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT) 680 #define SCTLR_TWEDEn_BIT (ULL(1) << 45) 681 #define SCTLR_TWEDEL_SHIFT U(46) 682 #define SCTLR_TWEDEL_MASK ULL(0xf) 683 #define SCTLR_EnASR_BIT (ULL(1) << 54) 684 #define SCTLR_EnAS0_BIT (ULL(1) << 55) 685 #define SCTLR_EnALS_BIT (ULL(1) << 56) 686 #define SCTLR_EPAN_BIT (ULL(1) << 57) 687 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 688 689 #define SCTLR2_EnPACM_BIT (ULL(1) << 7) 690 #define SCTLR2_CPTA_BIT (ULL(1) << 9) 691 #define SCTLR2_CPTM_BIT (ULL(1) << 11) 692 693 /* SCTLR2 currently has no RES1 fields so reset to 0 */ 694 #define SCTLR2_RESET_VAL ULL(0) 695 696 /* CPACR_EL1 definitions */ 697 #define CPACR_EL1_FPEN(x) ((x) << 20) 698 #define CPACR_EL1_FP_TRAP_EL0 UL(0x1) 699 #define CPACR_EL1_FP_TRAP_ALL UL(0x2) 700 #define CPACR_EL1_FP_TRAP_NONE UL(0x3) 701 #define CPACR_EL1_SMEN_SHIFT U(24) 702 #define CPACR_EL1_SMEN_MASK ULL(0x3) 703 704 /* SCR definitions */ 705 #if ENABLE_FEAT_GCIE 706 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5) | SCR_FIQ_BIT) 707 #else 708 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 709 #endif 710 #define SCR_NSE_SHIFT U(62) 711 #define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT) 712 #define SCR_FGTEN2_BIT (UL(1) << 59) 713 #define SCR_PFAREn_BIT (UL(1) << 53) 714 #define SCR_EnFPM_BIT (ULL(1) << 50) 715 #define SCR_MECEn_BIT (UL(1) << 49) 716 #define SCR_GPF_BIT (UL(1) << 48) 717 #define SCR_D128En_BIT (UL(1) << 47) 718 #define SCR_AIEn_BIT (UL(1) << 46) 719 #define SCR_TWEDEL_SHIFT U(30) 720 #define SCR_TWEDEL_MASK ULL(0xf) 721 #define SCR_PIEN_BIT (UL(1) << 45) 722 #define SCR_SCTLR2En_BIT (UL(1) << 44) 723 #define SCR_TCR2EN_BIT (UL(1) << 43) 724 #define SCR_RCWMASKEn_BIT (UL(1) << 42) 725 #define SCR_ENTP2_SHIFT U(41) 726 #define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT) 727 #define SCR_TRNDR_BIT (UL(1) << 40) 728 #define SCR_GCSEn_BIT (UL(1) << 39) 729 #define SCR_HXEn_BIT (UL(1) << 38) 730 #define SCR_ADEn_BIT (UL(1) << 37) 731 #define SCR_EnAS0_BIT (UL(1) << 36) 732 #define SCR_AMVOFFEN_SHIFT U(35) 733 #define SCR_AMVOFFEN_BIT (UL(1) << SCR_AMVOFFEN_SHIFT) 734 #define SCR_TWEDEn_BIT (UL(1) << 29) 735 #define SCR_ECVEN_BIT (UL(1) << 28) 736 #define SCR_FGTEN_BIT (UL(1) << 27) 737 #define SCR_ATA_BIT (UL(1) << 26) 738 #define SCR_EnSCXT_BIT (UL(1) << 25) 739 #define SCR_TID5_BIT (UL(1) << 23) 740 #define SCR_TID3_BIT (UL(1) << 22) 741 #define SCR_FIEN_BIT (UL(1) << 21) 742 #define SCR_EEL2_BIT (UL(1) << 18) 743 #define SCR_API_BIT (UL(1) << 17) 744 #define SCR_APK_BIT (UL(1) << 16) 745 #define SCR_TERR_BIT (UL(1) << 15) 746 #define SCR_TWE_BIT (UL(1) << 13) 747 #define SCR_TWI_BIT (UL(1) << 12) 748 #define SCR_ST_BIT (UL(1) << 11) 749 #define SCR_RW_BIT (UL(1) << 10) 750 #define SCR_SIF_BIT (UL(1) << 9) 751 #define SCR_HCE_BIT (UL(1) << 8) 752 #define SCR_SMD_BIT (UL(1) << 7) 753 #define SCR_EA_BIT (UL(1) << 3) 754 #define SCR_FIQ_BIT (UL(1) << 2) 755 #define SCR_IRQ_BIT (UL(1) << 1) 756 #define SCR_NS_BIT (UL(1) << 0) 757 #define SCR_VALID_BIT_MASK U(0x24000002F8F) 758 #define SCR_RESET_VAL SCR_RES1_BITS 759 760 /* MDCR_EL3 definitions */ 761 #define MDCR_EBWE_BIT (ULL(1) << 43) 762 #define MDCR_EnPMS3_BIT (ULL(1) << 42) 763 #define MDCR_PMEE(x) ((x) << 40) 764 #define MDCR_PMEE_CTRL_EL2 ULL(0x1) 765 #define MDCR_E3BREC_BIT (ULL(1) << 38) 766 #define MDCR_E3BREW_BIT (ULL(1) << 37) 767 #define MDCR_EnPMSN_BIT (ULL(1) << 36) 768 #define MDCR_MPMX_BIT (ULL(1) << 35) 769 #define MDCR_MCCD_BIT (ULL(1) << 34) 770 #define MDCR_SBRBE_SHIFT U(32) 771 #define MDCR_SBRBE(x) ((x) << MDCR_SBRBE_SHIFT) 772 #define MDCR_SBRBE_ALL ULL(0x3) 773 #define MDCR_SBRBE_NS ULL(0x1) 774 #define MDCR_NSTB_EN_BIT (ULL(1) << 24) 775 #define MDCR_NSTB_SS_BIT (ULL(1) << 25) 776 #define MDCR_NSTBE_BIT (ULL(1) << 26) 777 #define MDCR_MTPME_BIT (ULL(1) << 28) 778 #define MDCR_TDCC_BIT (ULL(1) << 27) 779 #define MDCR_SCCD_BIT (ULL(1) << 23) 780 #define MDCR_EPMAD_BIT (ULL(1) << 21) 781 #define MDCR_EDAD_BIT (ULL(1) << 20) 782 #define MDCR_TTRF_BIT (ULL(1) << 19) 783 #define MDCR_STE_BIT (ULL(1) << 18) 784 #define MDCR_SPME_BIT (ULL(1) << 17) 785 #define MDCR_SDD_BIT (ULL(1) << 16) 786 #define MDCR_SPD32(x) ((x) << 14) 787 #define MDCR_SPD32_LEGACY ULL(0x0) 788 #define MDCR_SPD32_DISABLE ULL(0x2) 789 #define MDCR_SPD32_ENABLE ULL(0x3) 790 #define MDCR_NSPB_SS_BIT (ULL(1) << 13) 791 #define MDCR_NSPB_EN_BIT (ULL(1) << 12) 792 #define MDCR_NSPBE_BIT (ULL(1) << 11) 793 #define MDCR_TDOSA_BIT (ULL(1) << 10) 794 #define MDCR_TDA_BIT (ULL(1) << 9) 795 #define MDCR_EnPM2_BIT (ULL(1) << 7) 796 #define MDCR_TPM_BIT (ULL(1) << 6) 797 #define MDCR_RLTE_BIT (ULL(1) << 0) 798 #define MDCR_EL3_RESET_VAL MDCR_MTPME_BIT 799 800 /* MDCR_EL2 definitions */ 801 #define MDCR_EL2_MTPME (ULL(1) << 28) 802 #define MDCR_EL2_HLP_BIT (ULL(1) << 26) 803 #define MDCR_EL2_E2TB(x) ULL((x) << 24) 804 #define MDCR_EL2_E2TB_EL1 ULL(0x3) 805 #define MDCR_EL2_HCCD_BIT (ULL(1) << 23) 806 #define MDCR_EL2_TTRF (ULL(1) << 19) 807 #define MDCR_EL2_HPMD_BIT (ULL(1) << 17) 808 #define MDCR_EL2_TPMS (ULL(1) << 14) 809 #define MDCR_EL2_E2PB(x) ULL((x) << 12) 810 #define MDCR_EL2_E2PB_EL1 ULL(0x3) 811 #define MDCR_EL2_TDRA_BIT (ULL(1) << 11) 812 #define MDCR_EL2_TDOSA_BIT (ULL(1) << 10) 813 #define MDCR_EL2_TDA_BIT (ULL(1) << 9) 814 #define MDCR_EL2_TDE_BIT (ULL(1) << 8) 815 #define MDCR_EL2_HPME_BIT (ULL(1) << 7) 816 #define MDCR_EL2_TPM_BIT (ULL(1) << 6) 817 #define MDCR_EL2_TPMCR_BIT (ULL(1) << 5) 818 #define MDCR_EL2_HPMN_MASK ULL(0x1f) 819 #define MDCR_EL2_RESET_VAL ULL(0x0) 820 821 /* HSTR_EL2 definitions */ 822 #define HSTR_EL2_RESET_VAL U(0x0) 823 #define HSTR_EL2_T_MASK U(0xff) 824 825 /* CNTHP_CTL_EL2 definitions */ 826 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 827 #define CNTHP_CTL_RESET_VAL U(0x0) 828 829 /* VTTBR_EL2 definitions */ 830 #define VTTBR_RESET_VAL ULL(0x0) 831 #define VTTBR_VMID_MASK ULL(0xff) 832 #define VTTBR_VMID_SHIFT U(48) 833 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 834 #define VTTBR_BADDR_SHIFT U(0) 835 836 /* HCR definitions */ 837 #define HCR_RESET_VAL ULL(0x0) 838 #define HCR_AMVOFFEN_SHIFT U(51) 839 #define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT) 840 #define HCR_TEA_BIT (ULL(1) << 47) 841 #define HCR_API_BIT (ULL(1) << 41) 842 #define HCR_APK_BIT (ULL(1) << 40) 843 #define HCR_E2H_BIT (ULL(1) << 34) 844 #define HCR_HCD_BIT (ULL(1) << 29) 845 #define HCR_TGE_BIT (ULL(1) << 27) 846 #define HCR_RW_SHIFT U(31) 847 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 848 #define HCR_TWE_BIT (ULL(1) << 14) 849 #define HCR_TWI_BIT (ULL(1) << 13) 850 #define HCR_AMO_BIT (ULL(1) << 5) 851 #define HCR_IMO_BIT (ULL(1) << 4) 852 #define HCR_FMO_BIT (ULL(1) << 3) 853 854 /* ISR definitions */ 855 #define ISR_A_SHIFT U(8) 856 #define ISR_I_SHIFT U(7) 857 #define ISR_F_SHIFT U(6) 858 859 /* CNTHCTL_EL2 definitions */ 860 #define CNTHCTL_RESET_VAL U(0x0) 861 #define EVNTEN_BIT (U(1) << 2) 862 #define EL1PCEN_BIT (U(1) << 1) 863 #define EL1PCTEN_BIT (U(1) << 0) 864 865 /* CNTKCTL_EL1 definitions */ 866 #define EL0PTEN_BIT (U(1) << 9) 867 #define EL0VTEN_BIT (U(1) << 8) 868 #define EL0PCTEN_BIT (U(1) << 0) 869 #define EL0VCTEN_BIT (U(1) << 1) 870 #define EVNTEN_BIT (U(1) << 2) 871 #define EVNTDIR_BIT (U(1) << 3) 872 #define EVNTI_SHIFT U(4) 873 #define EVNTI_MASK U(0xf) 874 875 /* CPTR_EL3 definitions */ 876 #define TCPAC_BIT (U(1) << 31) 877 #define TAM_SHIFT U(30) 878 #define TAM_BIT (U(1) << TAM_SHIFT) 879 #define TTA_BIT (U(1) << 20) 880 #define ESM_BIT (U(1) << 12) 881 #define TFP_BIT (U(1) << 10) 882 #define CPTR_EZ_BIT (U(1) << 8) 883 /* TCPAC is always set by default as the register is always present */ 884 #define CPTR_EL3_RESET_VAL ((TAM_BIT | TTA_BIT) & \ 885 ~(CPTR_EZ_BIT | ESM_BIT | TFP_BIT | TCPAC_BIT)) 886 887 /* CPTR_EL2 definitions */ 888 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 889 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 890 #define CPTR_EL2_TAM_SHIFT U(30) 891 #define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT) 892 #define CPTR_EL2_SMEN_MASK ULL(0x3) 893 #define CPTR_EL2_SMEN_SHIFT U(24) 894 #define CPTR_EL2_TTA_BIT (U(1) << 20) 895 #define CPTR_EL2_ZEN_MASK ULL(0x3) 896 #define CPTR_EL2_ZEN_SHIFT U(16) 897 #define CPTR_EL2_TSM_BIT (U(1) << 12) 898 #define CPTR_EL2_TFP_BIT (ULL(1) << 10) 899 #define CPTR_EL2_TZ_BIT (ULL(1) << 8) 900 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 901 902 /* VTCR_EL2 definitions */ 903 #define VTCR_RESET_VAL U(0x0) 904 #define VTCR_EL2_MSA (U(1) << 31) 905 906 /* CPSR/SPSR definitions */ 907 #define DAIF_FIQ_BIT (U(1) << 0) 908 #define DAIF_IRQ_BIT (U(1) << 1) 909 #define DAIF_ABT_BIT (U(1) << 2) 910 #define DAIF_DBG_BIT (U(1) << 3) 911 #define SPSR_V_BIT (U(1) << 28) 912 #define SPSR_C_BIT (U(1) << 29) 913 #define SPSR_Z_BIT (U(1) << 30) 914 #define SPSR_N_BIT (U(1) << 31) 915 #define SPSR_DAIF_SHIFT U(6) 916 #define SPSR_DAIF_MASK U(0xf) 917 918 #define SPSR_AIF_SHIFT U(6) 919 #define SPSR_AIF_MASK U(0x7) 920 921 #define SPSR_E_SHIFT U(9) 922 #define SPSR_E_MASK U(0x1) 923 #define SPSR_E_LITTLE U(0x0) 924 #define SPSR_E_BIG U(0x1) 925 926 #define SPSR_T_SHIFT U(5) 927 #define SPSR_T_MASK U(0x1) 928 #define SPSR_T_ARM U(0x0) 929 #define SPSR_T_THUMB U(0x1) 930 931 #define SPSR_M_SHIFT U(4) 932 #define SPSR_M_MASK U(0x1) 933 #define SPSR_M_AARCH64 U(0x0) 934 #define SPSR_M_AARCH32 U(0x1) 935 #define SPSR_M_EL1H U(0x5) 936 #define SPSR_M_EL2H U(0x9) 937 938 #define SPSR_EL_SHIFT U(2) 939 #define SPSR_EL_WIDTH U(2) 940 941 #define SPSR_BTYPE_SHIFT_AARCH64 U(10) 942 #define SPSR_BTYPE_MASK_AARCH64 U(0x3) 943 #define SPSR_SSBS_SHIFT_AARCH64 U(12) 944 #define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64) 945 #define SPSR_SSBS_SHIFT_AARCH32 U(23) 946 #define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32) 947 #define SPSR_ALLINT_BIT_AARCH64 BIT_64(13) 948 #define SPSR_IL_BIT BIT_64(20) 949 #define SPSR_SS_BIT BIT_64(21) 950 #define SPSR_PAN_BIT BIT_64(22) 951 #define SPSR_UAO_BIT_AARCH64 BIT_64(23) 952 #define SPSR_DIT_BIT BIT(24) 953 #define SPSR_TCO_BIT_AARCH64 BIT_64(25) 954 #define SPSR_PM_BIT_AARCH64 BIT_64(32) 955 #define SPSR_PPEND_BIT BIT(33) 956 #define SPSR_EXLOCK_BIT_AARCH64 BIT_64(34) 957 #define SPSR_NZCV (SPSR_V_BIT | SPSR_C_BIT | SPSR_Z_BIT | SPSR_N_BIT) 958 #define SPSR_PACM_BIT_AARCH64 BIT_64(35) 959 960 /* 961 * SPSR_EL2 962 * M=0x9 (0b1001 EL2h) 963 * M[4]=0 964 * DAIF=0xF Exceptions masked on entry. 965 * BTYPE=0 BTI not yet supported. 966 * SSBS=0 Not yet supported. 967 * IL=0 Not an illegal exception return. 968 * SS=0 Not single stepping. 969 * PAN=1 RMM shouldn't access Unprivileged memory when running in VHE mode. 970 * UAO=0 971 * DIT=0 972 * TCO=0 973 * NZCV=0 974 */ 975 #define SPSR_EL2_REALM (SPSR_M_EL2H | (0xF << SPSR_DAIF_SHIFT) | \ 976 SPSR_PAN_BIT) 977 978 #define DISABLE_ALL_EXCEPTIONS \ 979 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 980 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 981 982 /* 983 * RMR_EL3 definitions 984 */ 985 #define RMR_EL3_RR_BIT (U(1) << 1) 986 #define RMR_EL3_AA64_BIT (U(1) << 0) 987 988 /* 989 * HI-VECTOR address for AArch32 state 990 */ 991 #define HI_VECTOR_BASE U(0xFFFF0000) 992 993 /* 994 * TCR definitions 995 */ 996 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 997 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 998 #define TCR_EL1_IPS_SHIFT U(32) 999 #define TCR_EL2_PS_SHIFT U(16) 1000 #define TCR_EL3_PS_SHIFT U(16) 1001 1002 #define TCR_TxSZ_MIN ULL(16) 1003 #define TCR_TxSZ_MAX ULL(39) 1004 #define TCR_TxSZ_MAX_TTST ULL(48) 1005 1006 #define TCR_T0SZ_SHIFT U(0) 1007 #define TCR_T1SZ_SHIFT U(16) 1008 1009 /* (internal) physical address size bits in EL3/EL1 */ 1010 #define TCR_PS_BITS_4GB ULL(0x0) 1011 #define TCR_PS_BITS_64GB ULL(0x1) 1012 #define TCR_PS_BITS_1TB ULL(0x2) 1013 #define TCR_PS_BITS_4TB ULL(0x3) 1014 #define TCR_PS_BITS_16TB ULL(0x4) 1015 #define TCR_PS_BITS_256TB ULL(0x5) 1016 1017 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 1018 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 1019 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 1020 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 1021 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 1022 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 1023 1024 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 1025 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 1026 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 1027 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 1028 1029 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 1030 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 1031 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 1032 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 1033 1034 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 1035 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 1036 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 1037 1038 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 1039 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 1040 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 1041 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 1042 1043 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 1044 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 1045 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 1046 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 1047 1048 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 1049 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 1050 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 1051 1052 #define TCR_TG0_SHIFT U(14) 1053 #define TCR_TG0_MASK ULL(3) 1054 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 1055 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 1056 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 1057 1058 #define TCR_TG1_SHIFT U(30) 1059 #define TCR_TG1_MASK ULL(3) 1060 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 1061 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 1062 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 1063 1064 #define TCR_EPD0_BIT (ULL(1) << 7) 1065 #define TCR_EPD1_BIT (ULL(1) << 23) 1066 1067 #define MODE_SP_SHIFT U(0x0) 1068 #define MODE_SP_MASK U(0x1) 1069 #define MODE_SP_EL0 U(0x0) 1070 #define MODE_SP_ELX U(0x1) 1071 1072 #define MODE_RW_SHIFT U(0x4) 1073 #define MODE_RW_MASK U(0x1) 1074 #define MODE_RW_64 U(0x0) 1075 #define MODE_RW_32 U(0x1) 1076 1077 #define MODE_EL_SHIFT U(0x2) 1078 #define MODE_EL_MASK U(0x3) 1079 #define MODE_EL_WIDTH U(0x2) 1080 #define MODE_EL3 U(0x3) 1081 #define MODE_EL2 U(0x2) 1082 #define MODE_EL1 U(0x1) 1083 #define MODE_EL0 U(0x0) 1084 1085 #define MODE32_SHIFT U(0) 1086 #define MODE32_MASK U(0xf) 1087 #define MODE32_usr U(0x0) 1088 #define MODE32_fiq U(0x1) 1089 #define MODE32_irq U(0x2) 1090 #define MODE32_svc U(0x3) 1091 #define MODE32_mon U(0x6) 1092 #define MODE32_abt U(0x7) 1093 #define MODE32_hyp U(0xa) 1094 #define MODE32_und U(0xb) 1095 #define MODE32_sys U(0xf) 1096 1097 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 1098 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 1099 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 1100 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 1101 1102 #define SPSR_64(el, sp, daif) \ 1103 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 1104 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 1105 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 1106 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 1107 (~(SPSR_SSBS_BIT_AARCH64))) 1108 1109 #define SPSR_MODE32(mode, isa, endian, aif) \ 1110 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 1111 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 1112 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 1113 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 1114 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 1115 (~(SPSR_SSBS_BIT_AARCH32))) 1116 1117 /* 1118 * TTBR Definitions 1119 */ 1120 #define TTBR_CNP_BIT ULL(0x1) 1121 1122 /* 1123 * CTR_EL0 definitions 1124 */ 1125 #define CTR_CWG_SHIFT U(24) 1126 #define CTR_CWG_MASK U(0xf) 1127 #define CTR_ERG_SHIFT U(20) 1128 #define CTR_ERG_MASK U(0xf) 1129 #define CTR_DMINLINE_SHIFT U(16) 1130 #define CTR_DMINLINE_MASK U(0xf) 1131 #define CTR_L1IP_SHIFT U(14) 1132 #define CTR_L1IP_MASK U(0x3) 1133 #define CTR_IMINLINE_SHIFT U(0) 1134 #define CTR_IMINLINE_MASK U(0xf) 1135 1136 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 1137 1138 /* Physical timer control register bit fields shifts and masks */ 1139 #define CNTP_CTL_ENABLE_SHIFT U(0) 1140 #define CNTP_CTL_IMASK_SHIFT U(1) 1141 #define CNTP_CTL_ISTATUS_SHIFT U(2) 1142 1143 #define CNTP_CTL_ENABLE_MASK U(1) 1144 #define CNTP_CTL_IMASK_MASK U(1) 1145 #define CNTP_CTL_ISTATUS_MASK U(1) 1146 1147 /* Physical timer control macros */ 1148 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) 1149 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) 1150 1151 /* Exception Syndrome register bits and bobs */ 1152 #define ESR_EC_SHIFT U(26) 1153 #define ESR_EC_MASK U(0x3f) 1154 #define ESR_EC_LENGTH U(6) 1155 #define ESR_ISS_SHIFT U(0) 1156 #define ESR_ISS_LENGTH U(25) 1157 #define ESR_IL_BIT (U(1) << 25) 1158 #define EC_UNKNOWN U(0x0) 1159 #define EC_WFE_WFI U(0x1) 1160 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 1161 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 1162 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 1163 #define EC_AARCH32_CP14_LDC_STC U(0x6) 1164 #define EC_FP_SIMD U(0x7) 1165 #define EC_AARCH32_CP10_MRC U(0x8) 1166 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 1167 #define EC_ILLEGAL U(0xe) 1168 #define EC_AARCH32_SVC U(0x11) 1169 #define EC_AARCH32_HVC U(0x12) 1170 #define EC_AARCH32_SMC U(0x13) 1171 #define EC_AARCH64_SVC U(0x15) 1172 #define EC_AARCH64_HVC U(0x16) 1173 #define EC_AARCH64_SMC U(0x17) 1174 #define EC_AARCH64_SYS U(0x18) 1175 #define EC_IMP_DEF_EL3 U(0x1f) 1176 #define EC_IABORT_LOWER_EL U(0x20) 1177 #define EC_IABORT_CUR_EL U(0x21) 1178 #define EC_PC_ALIGN U(0x22) 1179 #define EC_DABORT_LOWER_EL U(0x24) 1180 #define EC_DABORT_CUR_EL U(0x25) 1181 #define EC_SP_ALIGN U(0x26) 1182 #define EC_AARCH32_FP U(0x28) 1183 #define EC_AARCH64_FP U(0x2c) 1184 #define EC_SERROR U(0x2f) 1185 #define EC_BRK U(0x3c) 1186 1187 /* 1188 * External Abort bit in Instruction and Data Aborts synchronous exception 1189 * syndromes. 1190 */ 1191 #define ESR_ISS_EABORT_EA_BIT U(9) 1192 1193 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 1194 1195 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 1196 #define RMR_RESET_REQUEST_SHIFT U(0x1) 1197 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 1198 1199 /******************************************************************************* 1200 * Definitions of register offsets, fields and macros for CPU system 1201 * instructions. 1202 ******************************************************************************/ 1203 1204 #define TLBI_ADDR_SHIFT U(12) 1205 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 1206 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 1207 1208 /******************************************************************************* 1209 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 1210 * system level implementation of the Generic Timer. 1211 ******************************************************************************/ 1212 #define CNTCTLBASE_CNTFRQ U(0x0) 1213 #define CNTNSAR U(0x4) 1214 #define CNTNSAR_NS_SHIFT(x) (x) 1215 1216 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 1217 #define CNTACR_RPCT_SHIFT U(0x0) 1218 #define CNTACR_RVCT_SHIFT U(0x1) 1219 #define CNTACR_RFRQ_SHIFT U(0x2) 1220 #define CNTACR_RVOFF_SHIFT U(0x3) 1221 #define CNTACR_RWVT_SHIFT U(0x4) 1222 #define CNTACR_RWPT_SHIFT U(0x5) 1223 1224 /******************************************************************************* 1225 * Definitions of register offsets and fields in the CNTBaseN Frame of the 1226 * system level implementation of the Generic Timer. 1227 ******************************************************************************/ 1228 /* Physical Count register. */ 1229 #define CNTPCT_LO U(0x0) 1230 /* Counter Frequency register. */ 1231 #define CNTBASEN_CNTFRQ U(0x10) 1232 /* Physical Timer CompareValue register. */ 1233 #define CNTP_CVAL_LO U(0x20) 1234 /* Physical Timer Control register. */ 1235 #define CNTP_CTL U(0x2c) 1236 1237 /* PMCR_EL0 definitions */ 1238 #define PMCR_EL0_RESET_VAL U(0x0) 1239 #define PMCR_EL0_N_SHIFT U(11) 1240 #define PMCR_EL0_N_MASK U(0x1f) 1241 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 1242 #define PMCR_EL0_LP_BIT (U(1) << 7) 1243 #define PMCR_EL0_LC_BIT (U(1) << 6) 1244 #define PMCR_EL0_DP_BIT (U(1) << 5) 1245 #define PMCR_EL0_X_BIT (U(1) << 4) 1246 #define PMCR_EL0_D_BIT (U(1) << 3) 1247 #define PMCR_EL0_C_BIT (U(1) << 2) 1248 #define PMCR_EL0_P_BIT (U(1) << 1) 1249 #define PMCR_EL0_E_BIT (U(1) << 0) 1250 1251 /******************************************************************************* 1252 * Definitions for system register interface to SVE 1253 ******************************************************************************/ 1254 #define ZCR_EL3 S3_6_C1_C2_0 1255 #define ZCR_EL2 S3_4_C1_C2_0 1256 1257 /* ZCR_EL3 definitions */ 1258 #define ZCR_EL3_LEN_MASK U(0xf) 1259 1260 /* ZCR_EL2 definitions */ 1261 #define ZCR_EL2_LEN_MASK U(0xf) 1262 1263 /******************************************************************************* 1264 * Definitions for system register interface to SME as needed in EL3 1265 ******************************************************************************/ 1266 #define ID_AA64SMFR0_EL1 S3_0_C0_C4_5 1267 #define SMCR_EL3 S3_6_C1_C2_6 1268 #define SVCR S3_3_C4_C2_2 1269 1270 /* ID_AA64SMFR0_EL1 definitions */ 1271 #define ID_AA64SMFR0_EL1_SME_FA64_SHIFT U(63) 1272 #define ID_AA64SMFR0_EL1_SME_FA64_MASK U(0x1) 1273 #define SME_FA64_IMPLEMENTED U(0x1) 1274 #define ID_AA64SMFR0_EL1_SME_VER_SHIFT U(55) 1275 #define ID_AA64SMFR0_EL1_SME_VER_MASK ULL(0xf) 1276 #define SME_INST_IMPLEMENTED ULL(0x0) 1277 #define SME2_INST_IMPLEMENTED ULL(0x1) 1278 1279 /* SMCR_ELx definitions */ 1280 #define SMCR_ELX_LEN_SHIFT U(0) 1281 #define SMCR_ELX_LEN_MAX U(0x1ff) 1282 #define SMCR_ELX_FA64_BIT (U(1) << 31) 1283 #define SMCR_ELX_EZT0_BIT (U(1) << 30) 1284 1285 /******************************************************************************* 1286 * Definitions of MAIR encodings for device and normal memory 1287 ******************************************************************************/ 1288 /* 1289 * MAIR encodings for device memory attributes. 1290 */ 1291 #define MAIR_DEV_nGnRnE ULL(0x0) 1292 #define MAIR_DEV_nGnRE ULL(0x4) 1293 #define MAIR_DEV_nGRE ULL(0x8) 1294 #define MAIR_DEV_GRE ULL(0xc) 1295 1296 /* 1297 * MAIR encodings for normal memory attributes. 1298 * 1299 * Cache Policy 1300 * WT: Write Through 1301 * WB: Write Back 1302 * NC: Non-Cacheable 1303 * 1304 * Transient Hint 1305 * NTR: Non-Transient 1306 * TR: Transient 1307 * 1308 * Allocation Policy 1309 * RA: Read Allocate 1310 * WA: Write Allocate 1311 * RWA: Read and Write Allocate 1312 * NA: No Allocation 1313 */ 1314 #define MAIR_NORM_WT_TR_WA ULL(0x1) 1315 #define MAIR_NORM_WT_TR_RA ULL(0x2) 1316 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 1317 #define MAIR_NORM_NC ULL(0x4) 1318 #define MAIR_NORM_WB_TR_WA ULL(0x5) 1319 #define MAIR_NORM_WB_TR_RA ULL(0x6) 1320 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 1321 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 1322 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 1323 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 1324 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 1325 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 1326 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 1327 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 1328 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 1329 1330 #define MAIR_NORM_OUTER_SHIFT U(4) 1331 1332 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 1333 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 1334 1335 /* PAR_EL1 fields */ 1336 #define PAR_F_SHIFT U(0) 1337 #define PAR_F_MASK ULL(0x1) 1338 1339 #define PAR_D128_ADDR_MASK GENMASK(55, 12) /* 44-bits-wide page address */ 1340 #define PAR_ADDR_MASK GENMASK(51, 12) /* 40-bits-wide page address */ 1341 1342 /******************************************************************************* 1343 * Definitions for system register interface to SPE 1344 ******************************************************************************/ 1345 #define PMBLIMITR_EL1 S3_0_C9_C10_0 1346 1347 /******************************************************************************* 1348 * Definitions for system register interface, shifts and masks for MPAM 1349 ******************************************************************************/ 1350 #define MPAMIDR_EL1 S3_0_C10_C4_4 1351 #define MPAM2_EL2 S3_4_C10_C5_0 1352 #define MPAMHCR_EL2 S3_4_C10_C4_0 1353 #define MPAM3_EL3 S3_6_C10_C5_0 1354 1355 #define MPAMIDR_EL1_VPMR_MAX_SHIFT ULL(18) 1356 #define MPAMIDR_EL1_VPMR_MAX_MASK ULL(0x7) 1357 /******************************************************************************* 1358 * Definitions for system register interface to AMU for FEAT_AMUv1 1359 ******************************************************************************/ 1360 #define AMCR_EL0 S3_3_C13_C2_0 1361 #define AMCFGR_EL0 S3_3_C13_C2_1 1362 #define AMCGCR_EL0 S3_3_C13_C2_2 1363 #define AMUSERENR_EL0 S3_3_C13_C2_3 1364 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 1365 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 1366 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 1367 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 1368 1369 /* Activity Monitor Group 0 Event Counter Registers */ 1370 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 1371 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 1372 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 1373 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 1374 1375 /* Activity Monitor Group 0 Event Type Registers */ 1376 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 1377 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 1378 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 1379 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 1380 1381 /* Activity Monitor Group 1 Event Counter Registers */ 1382 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 1383 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 1384 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 1385 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 1386 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 1387 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 1388 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 1389 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 1390 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 1391 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 1392 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 1393 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 1394 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 1395 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 1396 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 1397 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 1398 1399 /* Activity Monitor Group 1 Event Type Registers */ 1400 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 1401 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 1402 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 1403 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 1404 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 1405 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 1406 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 1407 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 1408 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 1409 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 1410 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 1411 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 1412 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 1413 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 1414 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 1415 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 1416 1417 /* AMCNTENSET0_EL0 definitions */ 1418 #define AMCNTENSET0_EL0_Pn_SHIFT U(0) 1419 #define AMCNTENSET0_EL0_Pn_MASK ULL(0xffff) 1420 1421 /* AMCNTENSET1_EL0 definitions */ 1422 #define AMCNTENSET1_EL0_Pn_SHIFT U(0) 1423 #define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff) 1424 1425 /* AMCNTENCLR0_EL0 definitions */ 1426 #define AMCNTENCLR0_EL0_Pn_SHIFT U(0) 1427 #define AMCNTENCLR0_EL0_Pn_MASK ULL(0xffff) 1428 1429 /* AMCNTENCLR1_EL0 definitions */ 1430 #define AMCNTENCLR1_EL0_Pn_SHIFT U(0) 1431 #define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff) 1432 1433 /* AMCFGR_EL0 definitions */ 1434 #define AMCFGR_EL0_NCG_SHIFT U(28) 1435 #define AMCFGR_EL0_NCG_MASK U(0xf) 1436 #define AMCFGR_EL0_N_SHIFT U(0) 1437 #define AMCFGR_EL0_N_MASK U(0xff) 1438 1439 /* AMCGCR_EL0 definitions */ 1440 #define AMCGCR_EL0_CG0NC_SHIFT U(0) 1441 #define AMCGCR_EL0_CG0NC_MASK U(0xff) 1442 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 1443 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 1444 1445 /* MPAM register definitions */ 1446 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 1447 #define MPAM3_EL3_TRAPLOWER_BIT (ULL(1) << 62) 1448 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 1449 #define MPAM3_EL3_RESET_VAL MPAM3_EL3_TRAPLOWER_BIT 1450 1451 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 1452 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 1453 1454 #define MPAMIDR_HAS_BW_CTRL_BIT (ULL(1) << 56) 1455 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 1456 1457 /* MPAM_PE_BW_CTRL register definitions */ 1458 #define MPAMBW2_EL2 S3_4_C10_C5_4 1459 #define MPAMBW2_EL2_HW_SCALE_ENABLE_BIT (ULL(1) << 63) 1460 #define MPAMBW2_EL2_ENABLED_BIT (ULL(1) << 62) 1461 #define MPAMBW2_EL2_HARDLIM_BIT (ULL(1) << 61) 1462 #define MPAMBW2_EL2_NTRAP_MPAMBWIDR_EL1_BIT (ULL(1) << 52) 1463 #define MPAMBW2_EL2_NTRAP_MPAMBW0_EL1_BIT (ULL(1) << 51) 1464 #define MPAMBW2_EL2_NTRAP_MPAMBW1_EL1_BIT (ULL(1) << 50) 1465 #define MPAMBW2_EL2_NTRAP_MPAMBWSM_EL1_BIT (ULL(1) << 49) 1466 1467 #define MPAMBW3_EL3 S3_6_C10_C5_4 1468 #define MPAMBW3_EL3_HW_SCALE_ENABLE_BIT (ULL(1) << 63) 1469 #define MPAMBW3_EL3_ENABLED_BIT (ULL(1) << 62) 1470 #define MPAMBW3_EL3_HARDLIM_BIT (ULL(1) << 61) 1471 #define MPAMBW3_EL3_NTRAPLOWER_BIT (ULL(1) << 49) 1472 1473 /******************************************************************************* 1474 * Definitions for system register interface to AMU for FEAT_AMUv1p1 1475 ******************************************************************************/ 1476 1477 /* Definition for register defining which virtual offsets are implemented. */ 1478 #define AMCG1IDR_EL0 S3_3_C13_C2_6 1479 #define AMCG1IDR_CTR_MASK ULL(0xffff) 1480 #define AMCG1IDR_CTR_SHIFT U(0) 1481 #define AMCG1IDR_VOFF_MASK ULL(0xffff) 1482 #define AMCG1IDR_VOFF_SHIFT U(16) 1483 1484 /* New bit added to AMCR_EL0 */ 1485 #define AMCR_CG1RZ_SHIFT U(17) 1486 #define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT) 1487 1488 /* 1489 * Definitions for virtual offset registers for architected activity monitor 1490 * event counters. 1491 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist. 1492 */ 1493 #define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0 1494 #define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2 1495 #define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3 1496 1497 /* 1498 * Definitions for virtual offset registers for auxiliary activity monitor event 1499 * counters. 1500 */ 1501 #define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0 1502 #define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1 1503 #define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2 1504 #define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3 1505 #define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4 1506 #define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5 1507 #define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6 1508 #define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7 1509 #define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0 1510 #define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1 1511 #define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2 1512 #define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3 1513 #define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4 1514 #define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5 1515 #define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6 1516 #define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7 1517 1518 /******************************************************************************* 1519 * Realm management extension register definitions 1520 ******************************************************************************/ 1521 #define GPCCR_EL3 S3_6_C2_C1_6 1522 #define GPTBR_EL3 S3_6_C2_C1_4 1523 1524 #define SCXTNUM_EL2 S3_4_C13_C0_7 1525 #define SCXTNUM_EL1 S3_0_C13_C0_7 1526 #define SCXTNUM_EL0 S3_3_C13_C0_7 1527 1528 /******************************************************************************* 1529 * RAS system registers 1530 ******************************************************************************/ 1531 #define DISR_EL1 S3_0_C12_C1_1 1532 #define DISR_A_BIT U(31) 1533 1534 #define ERRIDR_EL1 S3_0_C5_C3_0 1535 #define ERRIDR_MASK U(0xffff) 1536 1537 #define ERRSELR_EL1 S3_0_C5_C3_1 1538 1539 /* System register access to Standard Error Record registers */ 1540 #define ERXFR_EL1 S3_0_C5_C4_0 1541 #define ERXCTLR_EL1 S3_0_C5_C4_1 1542 #define ERXSTATUS_EL1 S3_0_C5_C4_2 1543 #define ERXADDR_EL1 S3_0_C5_C4_3 1544 #define ERXPFGF_EL1 S3_0_C5_C4_4 1545 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 1546 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 1547 #define ERXMISC0_EL1 S3_0_C5_C5_0 1548 #define ERXMISC1_EL1 S3_0_C5_C5_1 1549 1550 #define ERXCTLR_ED_SHIFT U(0) 1551 #define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT) 1552 #define ERXCTLR_UE_BIT (U(1) << 4) 1553 1554 #define ERXPFGCTL_UC_BIT (U(1) << 1) 1555 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 1556 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 1557 1558 /******************************************************************************* 1559 * Armv8.3 Pointer Authentication Registers 1560 ******************************************************************************/ 1561 #define APIAKeyLo_EL1 S3_0_C2_C1_0 1562 #define APIAKeyHi_EL1 S3_0_C2_C1_1 1563 #define APIBKeyLo_EL1 S3_0_C2_C1_2 1564 #define APIBKeyHi_EL1 S3_0_C2_C1_3 1565 #define APDAKeyLo_EL1 S3_0_C2_C2_0 1566 #define APDAKeyHi_EL1 S3_0_C2_C2_1 1567 #define APDBKeyLo_EL1 S3_0_C2_C2_2 1568 #define APDBKeyHi_EL1 S3_0_C2_C2_3 1569 #define APGAKeyLo_EL1 S3_0_C2_C3_0 1570 #define APGAKeyHi_EL1 S3_0_C2_C3_1 1571 1572 /******************************************************************************* 1573 * Armv8.4 Data Independent Timing Registers 1574 ******************************************************************************/ 1575 #define DIT S3_3_C4_C2_5 1576 #define DIT_BIT BIT(24) 1577 1578 /******************************************************************************* 1579 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 1580 ******************************************************************************/ 1581 #define SSBS S3_3_C4_C2_6 1582 1583 /******************************************************************************* 1584 * Armv8.5 - Memory Tagging Extension Registers 1585 ******************************************************************************/ 1586 #define TFSRE0_EL1 S3_0_C5_C6_1 1587 #define TFSR_EL1 S3_0_C5_C6_0 1588 #define RGSR_EL1 S3_0_C1_C0_5 1589 #define GCR_EL1 S3_0_C1_C0_6 1590 1591 #define GCR_EL1_RRND_BIT (UL(1) << 16) 1592 1593 /******************************************************************************* 1594 * Armv8.5 - Random Number Generator Registers 1595 ******************************************************************************/ 1596 #define RNDR S3_3_C2_C4_0 1597 #define RNDRRS S3_3_C2_C4_1 1598 1599 /******************************************************************************* 1600 * FEAT_HCX - Extended Hypervisor Configuration Register 1601 ******************************************************************************/ 1602 #define HCRX_EL2 S3_4_C1_C2_2 1603 #define HCRX_EL2_MSCEn_BIT (UL(1) << 11) 1604 #define HCRX_EL2_MCE2_BIT (UL(1) << 10) 1605 #define HCRX_EL2_CMOW_BIT (UL(1) << 9) 1606 #define HCRX_EL2_VFNMI_BIT (UL(1) << 8) 1607 #define HCRX_EL2_VINMI_BIT (UL(1) << 7) 1608 #define HCRX_EL2_TALLINT_BIT (UL(1) << 6) 1609 #define HCRX_EL2_SMPME_BIT (UL(1) << 5) 1610 #define HCRX_EL2_FGTnXS_BIT (UL(1) << 4) 1611 #define HCRX_EL2_FnXS_BIT (UL(1) << 3) 1612 #define HCRX_EL2_EnASR_BIT (UL(1) << 2) 1613 #define HCRX_EL2_EnALS_BIT (UL(1) << 1) 1614 #define HCRX_EL2_EnAS0_BIT (UL(1) << 0) 1615 #define HCRX_EL2_INIT_VAL ULL(0x0) 1616 1617 /******************************************************************************* 1618 * FEAT_FGT - Definitions for Fine-Grained Trap registers 1619 ******************************************************************************/ 1620 #define HFGITR_EL2_INIT_VAL ULL(0x180000000000000) 1621 #define HFGRTR_EL2_INIT_VAL ULL(0xC4000000000000) 1622 #define HFGWTR_EL2_INIT_VAL ULL(0xC4000000000000) 1623 1624 /******************************************************************************* 1625 * FEAT_TCR2 - Extended Translation Control Registers 1626 ******************************************************************************/ 1627 #define TCR2_EL1 S3_0_C2_C0_3 1628 #define TCR2_EL2 S3_4_C2_C0_3 1629 1630 /******************************************************************************* 1631 * Permission indirection and overlay Registers 1632 ******************************************************************************/ 1633 1634 #define PIRE0_EL1 S3_0_C10_C2_2 1635 #define PIRE0_EL2 S3_4_C10_C2_2 1636 #define PIR_EL1 S3_0_C10_C2_3 1637 #define PIR_EL2 S3_4_C10_C2_3 1638 #define POR_EL1 S3_0_C10_C2_4 1639 #define POR_EL2 S3_4_C10_C2_4 1640 #define S2PIR_EL2 S3_4_C10_C2_5 1641 #define S2POR_EL1 S3_0_C10_C2_5 1642 1643 /******************************************************************************* 1644 * FEAT_GCS - Guarded Control Stack Registers 1645 ******************************************************************************/ 1646 #define GCSCR_EL2 S3_4_C2_C5_0 1647 #define GCSPR_EL2 S3_4_C2_C5_1 1648 #define GCSCR_EL1 S3_0_C2_C5_0 1649 #define GCSCRE0_EL1 S3_0_C2_C5_2 1650 #define GCSPR_EL1 S3_0_C2_C5_1 1651 #define GCSPR_EL0 S3_3_C2_C5_1 1652 1653 #define GCSCR_EXLOCK_EN_BIT (UL(1) << 6) 1654 1655 /******************************************************************************* 1656 * FEAT_TRF - Trace Filter Control Registers 1657 ******************************************************************************/ 1658 #define TRFCR_EL2 S3_4_C1_C2_1 1659 #define TRFCR_EL1 S3_0_C1_C2_1 1660 1661 /******************************************************************************* 1662 * FEAT_THE - Translation Hardening Extension Registers 1663 ******************************************************************************/ 1664 #define RCWMASK_EL1 S3_0_C13_C0_6 1665 #define RCWSMASK_EL1 S3_0_C13_C0_3 1666 1667 /******************************************************************************* 1668 * FEAT_SCTLR2 - Extension to SCTLR_ELx Registers 1669 ******************************************************************************/ 1670 #define SCTLR2_EL3 S3_6_C1_C0_3 1671 #define SCTLR2_EL2 S3_4_C1_C0_3 1672 #define SCTLR2_EL1 S3_0_C1_C0_3 1673 1674 /******************************************************************************* 1675 * FEAT_BRBE - Branch Record Buffer Extension Registers 1676 ******************************************************************************/ 1677 #define BRBCR_EL2 S2_4_C9_C0_0 1678 1679 /******************************************************************************* 1680 * FEAT_LS64_ACCDATA - LoadStore64B with status data 1681 ******************************************************************************/ 1682 #define ACCDATA_EL1 S3_0_C13_C0_5 1683 1684 /******************************************************************************* 1685 * Definitions for DynamicIQ Shared Unit registers 1686 ******************************************************************************/ 1687 #define CLUSTERPWRDN_EL1 S3_0_C15_C3_6 1688 1689 /******************************************************************************* 1690 * FEAT_FPMR - Floating point Mode Register 1691 ******************************************************************************/ 1692 #define FPMR S3_3_C4_C4_2 1693 1694 /* CLUSTERPWRDN_EL1 register definitions */ 1695 #define DSU_CLUSTER_PWR_OFF 0 1696 #define DSU_CLUSTER_PWR_ON 1 1697 #define DSU_CLUSTER_PWR_MASK U(1) 1698 #define DSU_CLUSTER_MEM_RET BIT(1) 1699 1700 /* CLUSTERPMMDCR register definitions */ 1701 #define CLUSTERPMMDCR_SPME U(1) 1702 1703 /******************************************************************************* 1704 * Definitions for CPU Power/Performance Management registers 1705 ******************************************************************************/ 1706 1707 #define CPUPPMCR_EL3 S3_6_C15_C2_0 1708 #define CPUPPMCR_EL3_MPMMPINCTL_BIT BIT(0) 1709 1710 #define CPUMPMMCR_EL3 S3_6_C15_C2_1 1711 #define CPUMPMMCR_EL3_MPMM_EN_BIT BIT(0) 1712 1713 /* alternative system register encoding for the "sb" speculation barrier */ 1714 #define SYSREG_SB S0_3_C3_C0_7 1715 1716 #define CLUSTERPMCR_EL1 S3_0_C15_C5_0 1717 #define CLUSTERPMCNTENSET_EL1 S3_0_C15_C5_1 1718 #define CLUSTERPMCCNTR_EL1 S3_0_C15_C6_0 1719 #define CLUSTERPMOVSSET_EL1 S3_0_C15_C5_3 1720 #define CLUSTERPMOVSCLR_EL1 S3_0_C15_C5_4 1721 #define CLUSTERPMSELR_EL1 S3_0_C15_C5_5 1722 #define CLUSTERPMXEVTYPER_EL1 S3_0_C15_C6_1 1723 #define CLUSTERPMXEVCNTR_EL1 S3_0_C15_C6_2 1724 #define CLUSTERPMMDCR_EL3 S3_6_C15_C6_3 1725 1726 #define CLUSTERPMCR_E_BIT BIT(0) 1727 #define CLUSTERPMCR_N_SHIFT U(11) 1728 #define CLUSTERPMCR_N_MASK U(0x1f) 1729 1730 /******************************************************************************* 1731 * FEAT_MEC - Memory Encryption Contexts 1732 ******************************************************************************/ 1733 #define MECIDR_EL2 S3_4_C10_C8_7 1734 #define MECIDR_EL2_MECIDWidthm1_MASK U(0xf) 1735 #define MECIDR_EL2_MECIDWidthm1_SHIFT U(0) 1736 1737 /****************************************************************************** 1738 * FEAT_FGWTE3 - Fine Grained Write Trap 1739 ******************************************************************************/ 1740 #define FGWTE3_EL3 S3_6_C1_C1_5 1741 1742 /* FGWTE3_EL3 Defintions */ 1743 #define FGWTE3_EL3_VBAR_EL3_BIT (U(1) << 21) 1744 #define FGWTE3_EL3_TTBR0_EL3_BIT (U(1) << 20) 1745 #define FGWTE3_EL3_TPIDR_EL3_BIT (U(1) << 19) 1746 #define FGWTE3_EL3_TCR_EL3_BIT (U(1) << 18) 1747 #define FGWTE3_EL3_SPMROOTCR_EL3_BIT (U(1) << 17) 1748 #define FGWTE3_EL3_SCTLR2_EL3_BIT (U(1) << 16) 1749 #define FGWTE3_EL3_SCTLR_EL3_BIT (U(1) << 15) 1750 #define FGWTE3_EL3_PIR_EL3_BIT (U(1) << 14) 1751 #define FGWTE3_EL3_MECID_RL_A_EL3_BIT (U(1) << 12) 1752 #define FGWTE3_EL3_MAIR2_EL3_BIT (U(1) << 10) 1753 #define FGWTE3_EL3_MAIR_EL3_BIT (U(1) << 9) 1754 #define FGWTE3_EL3_GPTBR_EL3_BIT (U(1) << 8) 1755 #define FGWTE3_EL3_GPCCR_EL3_BIT (U(1) << 7) 1756 #define FGWTE3_EL3_GCSPR_EL3_BIT (U(1) << 6) 1757 #define FGWTE3_EL3_GCSCR_EL3_BIT (U(1) << 5) 1758 #define FGWTE3_EL3_AMAIR2_EL3_BIT (U(1) << 4) 1759 #define FGWTE3_EL3_AMAIR_EL3_BIT (U(1) << 3) 1760 #define FGWTE3_EL3_AFSR1_EL3_BIT (U(1) << 2) 1761 #define FGWTE3_EL3_AFSR0_EL3_BIT (U(1) << 1) 1762 #define FGWTE3_EL3_ACTLR_EL3_BIT (U(1) << 0) 1763 1764 #define FGWTE3_EL3_EARLY_INIT_VAL ( \ 1765 FGWTE3_EL3_VBAR_EL3_BIT | \ 1766 FGWTE3_EL3_TTBR0_EL3_BIT | \ 1767 FGWTE3_EL3_SPMROOTCR_EL3_BIT | \ 1768 FGWTE3_EL3_SCTLR2_EL3_BIT | \ 1769 FGWTE3_EL3_PIR_EL3_BIT | \ 1770 FGWTE3_EL3_MECID_RL_A_EL3_BIT | \ 1771 FGWTE3_EL3_MAIR2_EL3_BIT | \ 1772 FGWTE3_EL3_MAIR_EL3_BIT | \ 1773 FGWTE3_EL3_GPTBR_EL3_BIT | \ 1774 FGWTE3_EL3_GPCCR_EL3_BIT | \ 1775 FGWTE3_EL3_GCSPR_EL3_BIT | \ 1776 FGWTE3_EL3_GCSCR_EL3_BIT | \ 1777 FGWTE3_EL3_AMAIR2_EL3_BIT | \ 1778 FGWTE3_EL3_AMAIR_EL3_BIT | \ 1779 FGWTE3_EL3_AFSR1_EL3_BIT | \ 1780 FGWTE3_EL3_AFSR0_EL3_BIT) 1781 1782 #if HW_ASSISTED_COHERENCY 1783 #define FGWTE3_EL3_LATE_INIT_SCTLR_EL3_BIT FGWTE3_EL3_SCTLR_EL3_BIT | 1784 #else 1785 #define FGWTE3_EL3_LATE_INIT_SCTLR_EL3_BIT 1786 #endif 1787 1788 #if !(CRASH_REPORTING) 1789 #define FGWTE3_EL3_LATE_INIT_TPIDR_EL3_BIT FGWTE3_EL3_TPIDR_EL3_BIT | 1790 #else 1791 #define FGWTE3_EL3_LATE_INIT_TPIDR_EL3_BIT 1792 #endif 1793 1794 #define FGWTE3_EL3_LATE_INIT_VAL ( \ 1795 FGWTE3_EL3_EARLY_INIT_VAL | \ 1796 FGWTE3_EL3_LATE_INIT_SCTLR_EL3_BIT \ 1797 FGWTE3_EL3_LATE_INIT_TPIDR_EL3_BIT \ 1798 FGWTE3_EL3_TCR_EL3_BIT | \ 1799 FGWTE3_EL3_ACTLR_EL3_BIT) 1800 1801 #endif /* ARCH_H */ 1802