1 /* 2 * Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef VMIDMT_HAL_H 8 #define VMIDMT_HAL_H 9 10 #include <stdbool.h> 11 #include <stddef.h> 12 #include <stdint.h> 13 14 #include <lib/utils_def.h> 15 16 #define VMIDMT_INTERFACE_V1 0 17 18 #define HAL_VMIDMT_MAX_VMID 31 19 #define HAL_VMIDMT_SECURE_EXT_DEFAULT 0xFF 20 #define HAL_VMIDMT_ALL_ERROR_STATUS_BITS 0x7FFFFFFE 21 #define HAL_VMIDMT_VMID_ENABLE_BIT 1 22 #define HAL_VMIDMT_PERM_MASK 0x1 23 #define HAL_VMIDMT_PERM_WIDTH 1 24 #define HAL_VMIDMT_MASKS_PER_FIELD 32 25 #define HAL_VMIDMT_PERMS_PER_FIELD 32 26 27 #define HAL_VMIDMT_MASTER_MASK_WORDS \ 28 ((HAL_VMIDMT_MAX_VMID / HAL_VMIDMT_MASKS_PER_FIELD) + 1) 29 30 #define HAL_VMIDMT_MASTER_PERM_WORDS \ 31 ((HAL_VMIDMT_MAX_VMID / HAL_VMIDMT_PERMS_PER_FIELD) + 1) 32 33 enum hal_vmidmt_status { 34 HAL_VMIDMT_NO_ERROR, /* successful operation */ 35 HAL_VMIDMT_INVALID_INSTANCE, /* out of range VMIDMT instance */ 36 HAL_VMIDMT_UNSUPPORTED_INSTANCE_FOR_TARGET, 37 /* unsupported VMIDMT instance for the current target */ 38 HAL_VMIDMT_UNSUPPORTED_HANDLER, /* unsupported handler */ 39 HAL_VMIDMT_INVALID_BASE_ADDR, /* invalid VMIDMT instance base address */ 40 HAL_VMIDMT_INVALID_PARAM, /* invalid passed in parameter */ 41 HAL_VMIDMT_INVALID_HW_VALUE, /* invalid HW generic value */ 42 HAL_VMIDMT_READ_WRITE_MISMATCH /* read-after-write values not match */ 43 }; 44 45 enum hal_vmidmt_instance { 46 HAL_VMIDMT_CRYPTO0_AXI = 0, /* CRYPTO AXI - 0 */ 47 HAL_VMIDMT_CRYPTO1_AXI, /* CRYPTO AXI - 1 */ 48 HAL_VMIDMT_CRYPTO0_BAM, /* CRYPTO BAM - 0 */ 49 HAL_VMIDMT_CRYPTO0_CRYPTO = HAL_VMIDMT_CRYPTO0_BAM, 50 HAL_VMIDMT_CRYPTO1_BAM, /* CRYPTO BAM - 1 */ 51 HAL_VMIDMT_DEHR, /* DEHR */ 52 HAL_VMIDMT_DEHR_BIMC_WRAPPER = HAL_VMIDMT_DEHR, 53 HAL_VMIDMT_LPASS_DM, /* LPASS DM */ 54 HAL_VMIDMT_LPASS_LPAIF, /* LPASS LPAIF */ 55 HAL_VMIDMT_LPASS_MIDI, /* LPASS MIDI */ 56 HAL_VMIDMT_LPASS_Q6AHB, /* LPASS Q6AHB */ 57 HAL_VMIDMT_LPASS_Q6AXI, /* LPASS Q6AXI */ 58 HAL_VMIDMT_LPASS_RESAMPLER, /* LPASS Resampler */ 59 HAL_VMIDMT_LPASS_SLIMBUS, /* LPASS Slimbus */ 60 HAL_VMIDMT_CAMERA_SS, /* CAMERA Subsystem */ 61 HAL_VMIDMT_CAMSS_VBIF_JPEG, /* CAMERA VBIF JPEG */ 62 HAL_VMIDMT_CAMSS_VBIF_VFE, /* CAMERA VBIF VFE */ 63 HAL_VMIDMT_MMSS_DDR, /* MMSS DDR */ 64 HAL_VMIDMT_OCMEM, /* OCMEM */ 65 HAL_VMIDMT_OXILI, /* OXILI */ 66 HAL_VMIDMT_VENUS_CPUSS, /* Venus CPU SS */ 67 HAL_VMIDMT_VENUS_VBIF, /* Venus VBIF */ 68 HAL_VMIDMT_MSS_A2BAM, /* MSS A2BAM */ 69 HAL_VMIDMT_MSS_NAV_CE, /* MSS NAV CE */ 70 HAL_VMIDMT_MSS_Q6, /* MSS Q6 */ 71 HAL_VMIDMT_BAM_DMA, /* BAM DMA */ 72 HAL_VMIDMT_BAM_BLSP1_DMA, /* BAM BLSP DMA - 1 */ 73 HAL_VMIDMT_BLSP1_BLSP_BAM = HAL_VMIDMT_BAM_BLSP1_DMA, 74 HAL_VMIDMT_QUPV3_0 = HAL_VMIDMT_BAM_BLSP1_DMA, 75 HAL_VMIDMT_QUPV3_WEST = HAL_VMIDMT_BAM_BLSP1_DMA, 76 HAL_VMIDMT_BAM_BLSP2_DMA, /* BAM BLSP DMA - 2 */ 77 HAL_VMIDMT_BLSP2_BLSP_BAM = HAL_VMIDMT_BAM_BLSP2_DMA, 78 HAL_VMIDMT_QUPV3_1 = HAL_VMIDMT_BAM_BLSP2_DMA, 79 HAL_VMIDMT_QUPV3_EAST1 = HAL_VMIDMT_BAM_BLSP2_DMA, 80 HAL_VMIDMT_BAM_SDCC1, /* BAM SDCC1 */ 81 HAL_VMIDMT_BAM_SDCC2, /* BAM SDCC2 */ 82 HAL_VMIDMT_BAM_SDCC3, /* BAM SDCC3 */ 83 HAL_VMIDMT_BAM_SDCC4, /* BAM SDCC4 */ 84 HAL_VMIDMT_SDC_SDCC4_BAM = HAL_VMIDMT_BAM_SDCC4, 85 HAL_VMIDMT_TSIF, /* TSIF */ 86 HAL_VMIDMT_USB1_HS, /* BAM USB OTG */ 87 HAL_VMIDMT_USB2_HSIC, /* USB OTG */ 88 HAL_VMIDMT_QDSS_VMIDDAP, /* QDSS VMIDDAP */ 89 HAL_VMIDMT_QDSS_VMIDETR, /* QDSS VMIDETR */ 90 HAL_VMIDMT_RPM_MSGRAM, /* RPM MSGRAM */ 91 HAL_VMIDMT_RPM = HAL_VMIDMT_RPM_MSGRAM, 92 HAL_VMIDMT_AOP = HAL_VMIDMT_RPM_MSGRAM, 93 HAL_VMIDMT_SPDM_WRAPPER, /* SPDM TOP */ 94 HAL_VMIDMT_USB30, /* USB30 */ 95 HAL_VMIDMT_PRONTO, /* PRONTO */ 96 HAL_VMIDMT_QPIC_BAM, /* QPIC BAM */ 97 HAL_VMIDMT_QPIC = HAL_VMIDMT_QPIC_BAM, 98 HAL_VMIDMT_IPA, /* IPA */ 99 HAL_VMIDMT_IPA_0_IPA = HAL_VMIDMT_IPA, 100 HAL_VMIDMT_IPA_WRAPPER = HAL_VMIDMT_IPA, 101 HAL_VMIDMT_APCS, /* APCS */ 102 HAL_VMIDMT_CRYPTO2_AXI, /* CRYPTO AXI - 2 */ 103 HAL_VMIDMT_CRYPTO2_BAM, /* CRYPTO BAM - 2 */ 104 HAL_VMIDMT_EMAC, 105 HAL_VMIDMT_LPASS_HDMI, 106 HAL_VMIDMT_LPASS_SPDIF, 107 HAL_VMIDMT_VENUS_VBIF2, 108 HAL_VMIDMT_MMSS_VPU_MAPLE, 109 HAL_VMIDMT_USB_HS_SEC, 110 HAL_VMIDMT_SATA, 111 HAL_VMIDMT_PCIE20, 112 HAL_VMIDMT_PCIE_0_PCIE20 = HAL_VMIDMT_PCIE20, 113 HAL_VMIDMT_PCIE0, 114 HAL_VMIDMT_PCIE1, 115 HAL_VMIDMT_USB3_HSIC, 116 HAL_VMIDMT_UFS, 117 HAL_VMIDMT_LPASS_SB1, 118 HAL_VMIDMT_SSC_BLSP_BAM, 119 HAL_VMIDMT_SSC_SSC_BLSP_BAM = HAL_VMIDMT_SSC_BLSP_BAM, 120 HAL_VMIDMT_SSC_QUPV3 = HAL_VMIDMT_SSC_BLSP_BAM, 121 HAL_VMIDMT_LPASS_SENSOR_BLSP_BAM, 122 HAL_VMIDMT_SSC_SDC, 123 HAL_VMIDMT_LPASS_SSC_SDC, 124 HAL_VMIDMT_SPMI, 125 HAL_VMIDMT_SPMI_FETCHER = HAL_VMIDMT_SPMI, 126 HAL_VMIDMT_BAM_BLSP3_DMA, 127 HAL_VMIDMT_QUPV3_SOUTH = HAL_VMIDMT_BAM_BLSP2_DMA, 128 HAL_VMIDMT_QUPV3_NORTH = HAL_VMIDMT_BAM_BLSP1_DMA, 129 HAL_VMIDMT_QUPV3_2 = HAL_VMIDMT_BAM_BLSP3_DMA, 130 HAL_VMIDMT_QUPV3_EAST = HAL_VMIDMT_BAM_BLSP3_DMA, 131 HAL_VMIDMT_QSPI, 132 HAL_VMIDMT_LPASS_RXTX, 133 HAL_VMIDMT_LPASS_WSA, 134 HAL_VMIDMT_LPASS_VA, 135 HAL_VMIDMT_MSS_NAV, 136 HAL_VMIDMT_PCNOC_SNOC1, 137 HAL_VMIDMT_PCNOC_SNOC2, 138 HAL_VMIDMT_PCNOC_SNOC3, 139 HAL_VMIDMT_PCNOC_SNOC4, 140 HAL_VMIDMT_DEHR_BIMC, 141 HAL_VMIDMT_COUNT, 142 }; 143 144 struct hal_vmidmt_access_config { 145 uint32_t au_vmid[HAL_VMIDMT_MASTER_MASK_WORDS]; /* VMID to mask */ 146 uint32_t au_vmid_perm[HAL_VMIDMT_MASTER_PERM_WORDS]; /* VMID permissions */ 147 }; 148 149 enum hal_vmidmt_error_option { 150 HAL_VMIDMT_ERROR_O_SMCFCFG_EN = 0x1, /* stream match conflict fault */ 151 HAL_VMIDMT_ERROR_O_USFCFG_EN = 0x2, /* unidentified stream fault */ 152 HAL_VMIDMT_ERROR_O_GCFGFIE = 0x4, /* interrupt on global config fault */ 153 HAL_VMIDMT_ERROR_O_GCFGFRE = 0x8, /* report fault to offending master */ 154 HAL_VMIDMT_ERROR_O_GFIE = 0x10, /* interrupt on global client fault */ 155 }; 156 157 /* Store error reporting options ORed in this */ 158 typedef uint32_t hal_vmidmt_error_option_config; 159 160 struct hal_vmidmt_device_params { 161 uint16_t u_entry_count; /* Total number of table entries */ 162 uint16_t u_num_vmid; /* number of VMID supported by the core */ 163 uint8_t b_stream_map_support; /* Is stream mapping mode supported? */ 164 uint8_t u_num_ssd_index_bits; /* number of SSD index bits */ 165 uint8_t u_num_stream_id_bits; /* number of SID bits available */ 166 }; 167 168 enum hal_vmidmt_error_flags { 169 HAL_VMIDMT_ERROR_F_CLMULTI = 0x1, /* multiple error; 2nd is client */ 170 HAL_VMIDMT_ERROR_F_CFGMULTI = 0x2, /* multiple error; 2nd is config */ 171 HAL_VMIDMT_ERROR_F_PF = 0x4, /* permission fault */ 172 HAL_VMIDMT_ERROR_F_CAF = 0x8, /* configuration access fault */ 173 HAL_VMIDMT_ERROR_F_SMCF = 0x10, /* stream match conflict fault */ 174 HAL_VMIDMT_ERROR_F_USF = 0x20, /* unidentified stream fault */ 175 }; 176 177 /* Store error flags ORed in this */ 178 typedef uint32_t hal_vmidmt_error_flags_config; 179 180 enum hal_vmidmt_bus_error_flags { 181 HAL_VMIDMT_BUS_F_ERROR_NSATTR = 0x1, /* non-secure attribute */ 182 HAL_VMIDMT_BUS_F_ERROR_NSSTATE = 0x2, /* non-secure state */ 183 HAL_VMIDMT_BUS_F_ERROR_WNR = 0x4, /* write not read */ 184 }; 185 186 /* Store bus flags ORed in this */ 187 typedef uint32_t hal_vmidmt_bus_error_flags_mask; 188 189 struct hal_vmidmt_error { 190 hal_vmidmt_error_flags_config u_error_flags; /* Error Flags */ 191 hal_vmidmt_bus_error_flags_mask u_bus_flags; /* Bus specific flags */ 192 uint32_t u_physical_address_lower32; /* Lower 32 bits of PA */ 193 uint32_t u_physical_address_upper32; /* Upper 32 bits of PA */ 194 uint32_t u_ssd_index; /* SSD index */ 195 uint32_t u_sid; /* Stream ID */ 196 uint32_t u_master_id; /* Master ID */ 197 uint32_t u_avmid; /* Virtual master ID */ 198 uint32_t u_atid; /* ATID */ 199 uint32_t u_abid; /* ABID */ 200 uint32_t u_apid; /* APID */ 201 }; 202 203 typedef uint32_t hal_vmidmt_secure_status_det; 204 205 enum hal_vmidmt_non_secure_alloc_config { 206 HAL_VMIDMT_NSCFG_XTRAN = 0, /* use x_protns from transaction */ 207 HAL_VMIDMT_NSCFG_SECURE = 2, /* secure */ 208 HAL_VMIDMT_NSCFG_NONSECURE = 3, /* non-secure */ 209 HAL_VMIDMT_NSCFG_DEFAULT = 4 /* use default */ 210 }; 211 212 enum hal_vmidmt_write_alloc_config { 213 HAL_VMIDMT_WACFG_XTRAN = 0, /* use attributes from transaction */ 214 HAL_VMIDMT_WACFG_ALLOC = 2, /* allocate */ 215 HAL_VMIDMT_WACFG_NONALLOC = 3, /* non-allocate */ 216 HAL_VMIDMT_WACFG_DEFAULT = 4 /* use default */ 217 }; 218 219 enum hal_vmidmt_read_alloc_config { 220 HAL_VMIDMT_RACFG_XTRAN = 0, /* use attributes from transaction */ 221 HAL_VMIDMT_RACFG_ALLOC = 2, /* allocate */ 222 HAL_VMIDMT_RACFG_NONALLOC = 3, /* non-allocate */ 223 HAL_VMIDMT_RACFG_DEFAULT = 4 /* use default */ 224 }; 225 226 enum hal_vmidmt_shared_config { 227 HAL_VMIDMT_SHCFG_XTRAN = 0, /* use attributes from transaction */ 228 HAL_VMIDMT_SHCFG_OUTER_SHARE = 1, /* outer-shareable */ 229 HAL_VMIDMT_SHCFG_INNER_SHARE = 2, /* inner-shareable */ 230 HAL_VMIDMT_SHCFG_NON_SHARE = 3, /* non-shareable */ 231 HAL_VMIDMT_SHCFG_DEFAULT = 4 /* use default */ 232 }; 233 234 enum hal_vmidmt_mem_type_config { 235 HAL_VMIDMT_MTCFG_XTRAN = 0, /* use attributes from transaction */ 236 HAL_VMIDMT_MTCFG_MEMATTR = 1, /* use MemAttr field */ 237 HAL_VMIDMT_MTCFG_DEFAULT = 2 /* use default */ 238 }; 239 240 enum hal_vmidmt_transient_config { 241 HAL_VMIDMT_TRANSIENTCFG_XTRAN = 0, /* use transaction attr */ 242 HAL_VMIDMT_TRANSIENTCFG_NON_TRANSIENT = 2, /* non-transient */ 243 HAL_VMIDMT_TRANSIENTCFG_TRANSIENT = 3, /* transient */ 244 HAL_VMIDMT_TRANSIENTCFG_DEFAULT = 4 /* use default */ 245 }; 246 247 struct hal_vmidmt_bus_attrib { 248 enum hal_vmidmt_non_secure_alloc_config e_nscfg; /* non-secure allocate */ 249 enum hal_vmidmt_write_alloc_config e_wacfg; /* write allocate */ 250 enum hal_vmidmt_read_alloc_config e_racfg; /* read allocate */ 251 enum hal_vmidmt_shared_config e_shcfg; /* shareable attribute */ 252 enum hal_vmidmt_mem_type_config e_mtcfg; /* memory type config */ 253 uint8_t mem_attr; /* memory attributes (3b) */ 254 enum hal_vmidmt_transient_config e_transient_cfg; /* transient config */ 255 }; 256 257 enum hal_vmidmt_redir_cache_non_shareable_config { 258 HAL_VMIDMT_RCNSH_DISABLE = 0, /* do not redirect */ 259 HAL_VMIDMT_RCNSH_ENABLE = 1, /* enable redirect */ 260 HAL_VMIDMT_RCNSH_DEFAULT = 2 /* use default */ 261 }; 262 263 enum hal_vmidmt_redir_cache_inner_shareable_config { 264 HAL_VMIDMT_RCISH_DISABLE = 0, /* do not redirect */ 265 HAL_VMIDMT_RCISH_ENABLE = 1, /* enable redirect */ 266 HAL_VMIDMT_RCISH_DEFAULT = 2 /* use default */ 267 }; 268 269 enum hal_vmidmt_redir_cache_outer_shareable_config { 270 HAL_VMIDMT_RCOSH_DISABLE = 0, /* do not redirect */ 271 HAL_VMIDMT_RCOSH_ENABLE = 1, /* enable redirect */ 272 HAL_VMIDMT_RCOSH_DEFAULT = 2 /* use default */ 273 }; 274 275 enum hal_vmidmt_req_priority_config { 276 HAL_VMIDMT_REQPRICFG_XTRAN = 0, /* use transaction attr */ 277 HAL_VMIDMT_REQPRICFG_ACR_REQPRI = 278 1, /* use (S)ACR.REQPRIORITY override */ 279 HAL_VMIDMT_REQPRICFG_DEFAULT = 2 /* use default */ 280 }; 281 282 enum hal_vmidmt_req_priority { 283 HAL_VMIDMT_REQPRI_NORMAL = 0, /* normal priority */ 284 HAL_VMIDMT_REQPRI_HIGH = 1, /* high priority */ 285 HAL_VMIDMT_REQPRI_HIGHER = 2, /* higher priority */ 286 HAL_VMIDMT_REQPRI_HIGHEST = 3, /* highest priority */ 287 HAL_VMIDMT_REQPRI_DEFAULT = 4 /* use default */ 288 }; 289 290 struct hal_vmidmt_aux_config { 291 enum hal_vmidmt_redir_cache_non_shareable_config 292 e_rcnsh; /* redirect C-NSH */ 293 enum hal_vmidmt_redir_cache_inner_shareable_config 294 e_rcish; /* redirect C-ISH */ 295 enum hal_vmidmt_redir_cache_outer_shareable_config 296 e_rcosh; /* redirect C-OSH */ 297 enum hal_vmidmt_req_priority_config e_req_priority_cfg; /* req pri cfg */ 298 enum hal_vmidmt_req_priority e_req_priority; /* req priority */ 299 }; 300 301 struct hal_vmidmt_default_vmid_config { 302 struct hal_vmidmt_bus_attrib 303 *p_bypass_bus_attrib; /* bypass bus attributes */ 304 struct hal_vmidmt_aux_config *p_bypass_aux_config; /* bypass aux config */ 305 struct hal_vmidmt_access_config 306 *p_access_control; /* RPU access control */ 307 bool b_vmid_private_namespace_enable; /* private NS */ 308 uint8_t bypass_vmid; /* bypass VMID */ 309 }; 310 311 struct hal_vmidmt_default_secure_vmid_config { 312 struct hal_vmidmt_default_vmid_config 313 *p_default_secure_config; /* default cfg */ 314 bool b_glb_addr_space_restricted_acc_enable; 315 /* global address space restricted access enable */ 316 uint8_t secure_extensions; 317 /* non-secure number of stream mapping register groups override 318 * HAL_VMIDMT_SECURE_EXT_DEFAULT can be used for default setting 319 */ 320 }; 321 322 struct hal_vmidmt_context_config { 323 struct hal_vmidmt_bus_attrib *p_bus_attrib; /* config S2VRn */ 324 struct hal_vmidmt_aux_config *p_aux_config; /* config AS2VRn */ 325 uint8_t u_vmid; /* config VMID in S2VRn */ 326 }; 327 328 enum hal_vmidmt_int_status { 329 HAL_VMIDMT_INT_NO_ERROR, 330 HAL_VMIDMT_INT_PROPERTY_HANDLE_ERROR, 331 HAL_VMIDMT_INT_UNSUP_INST_FOR_TARGET, 332 }; 333 334 enum hal_vmidmt_access { 335 HAL_VMIDMT_NO_ACCESS, 336 HAL_VMIDMT_FULL_ACCESS, 337 HAL_VMIDMT_ACCESS_COUNT, 338 }; 339 340 struct hal_vmidmt_int_vmidmt_dev_params { 341 uint16_t entry_count; 342 uint16_t num_vmid; 343 uint8_t num_ssd_index_bits; 344 uint8_t num_stream_id_bits; 345 uint8_t input_addr_size; 346 uint8_t stream_match_support; 347 }; 348 349 struct hal_vmidmt_info { 350 uint64_t base_addr; 351 struct hal_vmidmt_int_vmidmt_dev_params dev_params; 352 }; 353 354 struct hal_vmidmt_port_map { 355 uint8_t port; 356 struct hal_vmidmt_info vmidmt_info; 357 }; 358 359 /* Initialize VMIDMT */ 360 enum hal_vmidmt_status 361 vmidmt_hal_init(struct hal_vmidmt_info *info, 362 const struct hal_vmidmt_default_secure_vmid_config *secure_def, 363 const struct hal_vmidmt_default_vmid_config *defcfg, 364 char **err_str); 365 366 /* Enable or disable client interface. */ 367 enum hal_vmidmt_status 368 vmidmt_hal_enable_client(const struct hal_vmidmt_info *info, bool enable); 369 370 /* Configure Secure Status Determination Table (SSDT). */ 371 enum hal_vmidmt_status 372 vmidmt_hal_config_ssdt(const struct hal_vmidmt_info *info, 373 const hal_vmidmt_secure_status_det *ssdt, 374 uint32_t count); 375 376 /* Configure a single context entry. */ 377 enum hal_vmidmt_status 378 vmidmt_hal_config_ctx(const struct hal_vmidmt_info *info, uint32_t index, 379 const struct hal_vmidmt_context_config *cfg); 380 381 /* Configure multiple context entries (extended). */ 382 enum hal_vmidmt_status 383 vmidmt_hal_config_ctx_ext(const struct hal_vmidmt_info *info, 384 uint32_t first_index, const uint32_t *index_list, 385 uint32_t list_len, 386 const struct hal_vmidmt_context_config *cfg); 387 388 /* Configure error reporting/handling options. */ 389 enum hal_vmidmt_status vmidmt_hal_cfg_err(const struct hal_vmidmt_info *info, 390 bool global_cfg, 391 hal_vmidmt_error_option_config opts); 392 393 /* Check if an error is latched. */ 394 bool vmidmt_hal_is_error(const struct hal_vmidmt_info *info, bool global_err); 395 396 /* Read back the latched error record. */ 397 void vmidmt_hal_get_error(const struct hal_vmidmt_info *info, bool global_err, 398 struct hal_vmidmt_error *err); 399 400 /* Clear latched error(s). */ 401 enum hal_vmidmt_status 402 vmidmt_hal_clear_error(const struct hal_vmidmt_info *info, bool global_err); 403 404 #endif /* VMIDMT_HAL_H */ 405