1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
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20 //
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75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
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91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #include "MsCommon.h"
101 #ifndef MSOS_TYPE_LINUX_KERNEL
102 #include <string.h>
103 #endif
104 #include "MsTypes.h"
105 #include "MsIRQ.h"
106 #include "MsOS.h"
107 #include "drvMVOP.h"
108 #include "drvMIU.h"
109
110 // Internal Definition
111 #include "regMVOP.h"
112 #include "halMVOP.h"
113
114 #ifndef ANDROID
115 #define MVOP_PRINTF printf
116 #else
117 #include <sys/mman.h>
118 #include <cutils/ashmem.h>
119 #include <cutils/log.h>
120
121 #define MVOP_PRINTF ALOGD
122 #endif
123
124 // Common
125 #ifdef MSOS_TYPE_LINUX_KERNEL
126 #include <asm/div64.h>
127 #else
128 #define do_div(x,y) ((x)/=(y))
129 #define do_mod(x,y) ((x)%=(y))
130 #endif
131 //-------------------------------------------------------------------------------------------------
132 // Driver Compiler Options
133 //-------------------------------------------------------------------------------------------------
134
135
136 //-------------------------------------------------------------------------------------------------
137 // Local Defines
138 //-------------------------------------------------------------------------------------------------
139 #define MPLL_CLOCK (432000000ULL)
140
141 #define BIT0 BIT(0)
142 #define BIT1 BIT(1)
143 #define BIT2 BIT(2)
144 #define BIT3 BIT(3)
145 #define BIT4 BIT(4)
146 #define BIT5 BIT(5)
147 #define BIT6 BIT(6)
148 #define BIT7 BIT(7)
149 #define BIT15 BIT(15)
150
151 #define ALIGN_UPTO_16(x) ((((x) + 15) >> 4) << 4)
152 #define ALIGN_UPTO_4(x) ((((x) + 3) >> 2) << 2)
153 #define ALIGN_UPTO_2(x) ((((x) + 1) >> 1) << 1)
154
155 #define MVOP_VBlank 45
156 #define MVOP_HBlank_SD 200
157 #define MVOP_HBlank_HD 300
158
159 #if 0
160 static MS_U32 u32RiuBaseAdd=0;
161 static MS_BOOL bMirrorModeVer = 0;
162 static MS_BOOL bMirrorModeHor = 0;
163 static MS_BOOL bMirrorMode=0;
164 static MS_BOOL bSubMirrorModeVer = 0;
165 static MS_BOOL bSubMirrorModeHor = 0;
166 static MS_BOOL bSubMirrorMode=0;
167 static MS_BOOL bEnableFreerunMode = FALSE;
168 static MS_BOOL bSubEnableFreerunMode = FALSE;
169 static MS_BOOL b3DLRMode=0; /// 3D L/R dual buffer mode
170 static MS_BOOL bSub3DLRMode=0;
171 static MS_BOOL b3DLRAltOutput = FALSE; /// 3D L/R line alternative output
172 static MS_BOOL bNewVSyncMode = FALSE;
173 static MVOP_RptFldMode eRepeatField = E_MVOP_RPTFLD_NONE; /// mvop output repeating fields for single field input.
174 static MVOP_RptFldMode eSubRepeatField = E_MVOP_RPTFLD_NONE; /// mvop output repeating fields for single field input.
175 static MVOP_RgbFormat eMainRgbFmt = E_MVOP_RGB_NONE;
176 static MVOP_RgbFormat eSubRgbFmt = E_MVOP_RGB_NONE;
177 #endif
178
179 typedef struct
180 {
181
182 MS_BOOL bMirrorModeVer;
183 MS_BOOL bMirrorModeHor;
184 MS_BOOL bMirrorMode;
185 MS_BOOL bEnableFreerunMode;
186 MS_BOOL b3DLRMode; /// 3D L/R dual buffer mode
187 MS_BOOL b3DLRAltOutput; /// 3D L/R line alternative output
188 MS_BOOL b3DLRAltSBSOutput; /// 3D L/R side by side output
189 MS_BOOL bNewVSyncMode;
190 MVOP_RptFldMode eRepeatField; /// mvop output repeating fields for single field input.
191 MVOP_RgbFormat eMainRgbFmt;
192 MS_BOOL bIsInit;
193 MS_BOOL bRptPreVsync;
194 MS_BOOL bIs422;
195 MS_BOOL bIsH265;
196 MS_BOOL bIsHS;
197 MS_U16 u16CropXStart;
198 MS_U16 u16CropYStart;
199 MS_U16 u16CropXSize;
200 MS_U16 u16CropYSize;
201 MS_BOOL bIsSetCrop;
202 MS_BOOL bIsXcTrig;
203 MS_U32 u32MVOPFixClk;
204 MS_BOOL bIsEnable;
205 MS_BOOL bIs2p;
206 MVOP_OutputImodeType eInterlaceType;
207 MS_U16 u16ECONum;
208 MS_U16 u16Hsize;
209 #if MVOP_SUPPORT_SUB
210 MS_BOOL bSubMirrorModeVer;
211 MS_BOOL bSubMirrorModeHor;
212 MS_BOOL bSubMirrorMode;
213 MS_BOOL bSubEnableFreerunMode;
214 MS_BOOL bSub3DLRMode;
215 MS_BOOL bSubNewVSyncMode;
216 MVOP_RptFldMode eSubRepeatField; /// mvop output repeating fields for single field input.
217 MVOP_RgbFormat eSubRgbFmt;
218 MS_BOOL bSubIsInit;
219 MS_BOOL bSubRptPreVsync;
220 MS_BOOL bSubIs422;
221 MS_BOOL bSubIsH265;
222 MS_BOOL bSub3DLRAltOutput; /// 3D L/R line alternative output
223 MS_BOOL bSub3DLRAltSBSOutput;
224 MS_BOOL bSubIsHS;
225 MS_U16 u16SubCropXStart;
226 MS_U16 u16SubCropYStart;
227 MS_U16 u16SubCropXSize;
228 MS_U16 u16SubCropYSize;
229 MS_BOOL bSubIsSetCrop;
230 MS_BOOL bSubIsXcTrig;
231 MS_U32 u32SubMVOPFixClk;
232 MS_BOOL bIsSubEnable;
233 MS_BOOL bSubIs2p;
234 MVOP_OutputImodeType eSubInterlaceType;
235 MS_U16 u16SubHsize;
236 #endif
237 }MVOP_CTX_HAL;
238
239 static MVOP_CTX_HAL *g_pHalMVOPCtx = NULL;
240 static MS_VIRT u32RiuBaseAdd=0;
241
242 #ifndef MSOS_TYPE_LINUX
243 MVOP_CTX_HAL g_stmvopHalCtx;
244 #endif
245 #define RIU_MAP u32RiuBaseAdd //obtained in init
246
247 #define RIU8 ((unsigned char volatile *) RIU_MAP)
248 #define RIU16 ((MS_U16 volatile *) RIU_MAP)
249 #define MST_MACRO_START do {
250 #define MST_MACRO_END } while (0)
251
252 #define HAL_WriteByte( u32Reg, u8Val ) \
253 MST_MACRO_START \
254 if ( __builtin_constant_p( u32Reg ) ) \
255 { \
256 RIU8[((u32Reg) * 2) - ((u32Reg) & 1)] = u8Val; \
257 } \
258 else \
259 { \
260 RIU8[(u32Reg << 1) - (u32Reg & 1)] = u8Val; \
261 } \
262 MST_MACRO_END
263
264 #define HAL_ReadByte( u32Reg ) \
265 (__builtin_constant_p( u32Reg ) ? \
266 (((u32Reg) & 0x01) ? RIU8[(u32Reg) * 2 - 1] : RIU8[(u32Reg) * 2]) : \
267 (RIU8[(u32Reg << 1) - (u32Reg & 1)]))
268
269 #define HAL_Read2Byte( u32Reg ) \
270 (RIU16[u32Reg])
271
272 #define HAL_ReadRegBit( u32Reg, u8Mask ) \
273 (RIU8[(u32Reg) * 2 - ((u32Reg) & 1)] & (u8Mask))
274
275 #define HAL_WriteRegBit( u32Reg, bEnable, u8Mask ) \
276 MST_MACRO_START \
277 MS_U32 u32Reg8 = ((u32Reg) * 2) - ((u32Reg) & 1); \
278 RIU8[u32Reg8] = (bEnable) ? (RIU8[u32Reg8] | (u8Mask)) : \
279 (RIU8[u32Reg8] & ~(u8Mask)); \
280 MST_MACRO_END
281
282 #define HAL_WriteByteMask( u32Reg, u8Val, u8Msk ) \
283 MST_MACRO_START \
284 MS_U32 u32Reg8 = ((u32Reg) * 2) - ((u32Reg) & 1); \
285 RIU8[u32Reg8] = (RIU8[u32Reg8] & ~(u8Msk)) | ((u8Val) & (u8Msk)); \
286 MST_MACRO_END
287
288 #define HAL_Write2Byte(u32Reg, u16Val) \
289 RIU16[u32Reg] = u16Val;
290
291 #define SUB_REG(x) (x-MVOP_REG_BASE+MVOP_SUB_REG_BASE)
292
293 #define _FUNC_NOT_USED() do {} while ( 0 )
294 #ifndef UNUSED
295 #define UNUSED(x) (void)(x)
296 #endif
297
298 #define LOWBYTE(u16) ((MS_U8)(u16))
299 #define HIGHBYTE(u16) ((MS_U8)((u16) >> 8))
300
301
302 #define VOP_ON_MIU1 ((HAL_ReadByte(0x12F9) & BIT2) == BIT2)
303 #define _MaskMiuReq_MVOP_R( m ) HAL_WriteRegBit(0x12C7, m, BIT2)
304 #define _MaskMiu1Req_MVOP_R( m ) HAL_WriteRegBit(0x06C7, m, BIT2)
305
306 #define HAL_MIU_SetReqMask( miu_clients, mask ) \
307 do { \
308 if (VOP_ON_MIU1 == 0) \
309 _MaskMiuReq_##miu_clients( mask ); \
310 else \
311 _MaskMiu1Req_##miu_clients( mask ); \
312 }while(0)
313
314 #define SUBVOP_ON_MIU1 ((HAL_ReadByte(0x12F9) & BIT2) == BIT2)
315 #define _MaskMiuReq_SUBMVOP_R( m ) HAL_WriteRegBit(0x12C7, m, BIT2)
316 #define _MaskMiu1Req_SUBMVOP_R( m ) HAL_WriteRegBit(0x06C7, m, BIT2)
317
318 #define HAL_MIU_SubSetReqMask( miu_clients, mask ) \
319 do { \
320 if (SUBVOP_ON_MIU1 == 0) \
321 _MaskMiuReq_##miu_clients( mask ); \
322 else \
323 _MaskMiu1Req_##miu_clients( mask ); \
324 }while(0)
325
326 #define MVOP_DBG_ENABLE 0
327 #if MVOP_DBG_ENABLE
328 #define MVOP_DBG(fmt, args...) MVOP_PRINTF(fmt, ##args)
329 #else
330 #define MVOP_DBG(fmt, args...) {}
331 #endif
332
333 typedef enum
334 {
335 E_MVOP_INIT_OK = 0,
336 E_MVOP_INIT_FAIL = 1,
337 E_MVOP_INIT_ALREADY_EXIST = 2
338 } MVOP_HalInitCtxResults;
339 //-------------------------------------------------------------------------------------------------
340 // Local Structures
341 //-------------------------------------------------------------------------------------------------
342
343
344 //-------------------------------------------------------------------------------------------------
345 // Global Variables
346 //-------------------------------------------------------------------------------------------------
347
348 #define Y_INFO 0
349 #define UV_INFO 1
350
351 //-------------------------------------------------------------------------------------------------
352 // Local Variables
353 //-------------------------------------------------------------------------------------------------
354
355
356 //-------------------------------------------------------------------------------------------------
357 // Debug Functions
358 //-------------------------------------------------------------------------------------------------
359
360
361 //-------------------------------------------------------------------------------------------------
362 // Local Functions
363 //-------------------------------------------------------------------------------------------------
364
365
366 //-------------------------------------------------------------------------------------------------
367 // Global Functions
368 //-------------------------------------------------------------------------------------------------
369
_HAL_MVOP_InitVarCtx(void)370 void _HAL_MVOP_InitVarCtx(void)
371 {
372 g_pHalMVOPCtx->bMirrorModeVer = 0;
373 g_pHalMVOPCtx->bMirrorModeHor = 0;
374 g_pHalMVOPCtx->bMirrorMode=0;
375 g_pHalMVOPCtx->bEnableFreerunMode = FALSE;
376 g_pHalMVOPCtx->b3DLRMode=0; /// 3D L/R dual buffer mode
377 g_pHalMVOPCtx->b3DLRAltOutput = FALSE; /// 3D L/R line alternative output
378 g_pHalMVOPCtx->b3DLRAltSBSOutput = FALSE;
379 g_pHalMVOPCtx->bNewVSyncMode = FALSE;
380 g_pHalMVOPCtx->eRepeatField = E_MVOP_RPTFLD_NONE; /// mvop output repeating fields for single field input.
381 g_pHalMVOPCtx->eMainRgbFmt = E_MVOP_RGB_NONE;
382 g_pHalMVOPCtx->bIsInit = 0;
383 g_pHalMVOPCtx->bRptPreVsync = 0;
384 g_pHalMVOPCtx->bIs422 = 0;
385 g_pHalMVOPCtx->bIsH265 = 0;
386 g_pHalMVOPCtx->bIsHS = FALSE;
387 g_pHalMVOPCtx->u16CropXStart = 0;
388 g_pHalMVOPCtx->u16CropYStart = 0;
389 g_pHalMVOPCtx->u16CropXSize = 0;
390 g_pHalMVOPCtx->u16CropYSize = 0;
391 g_pHalMVOPCtx->bIsSetCrop = FALSE;
392 g_pHalMVOPCtx->bIsXcTrig = TRUE;
393 g_pHalMVOPCtx->u32MVOPFixClk = 0;
394 g_pHalMVOPCtx->bIsEnable = 0;
395 g_pHalMVOPCtx->bIs2p = 0;
396 g_pHalMVOPCtx->eInterlaceType = E_MVOP_PRO;
397 g_pHalMVOPCtx->u16Hsize = 0;
398 }
399
_HAL_MVOP_SubInitVarCtx(void)400 void _HAL_MVOP_SubInitVarCtx(void)
401 {
402 #if MVOP_SUPPORT_SUB
403 g_pHalMVOPCtx->bSubMirrorModeVer = 0;
404 g_pHalMVOPCtx->bSubMirrorModeHor = 0;
405 g_pHalMVOPCtx->bSubMirrorMode=0;
406 g_pHalMVOPCtx->bSubEnableFreerunMode = FALSE;
407 g_pHalMVOPCtx->bSub3DLRMode=0;
408 g_pHalMVOPCtx->bSubNewVSyncMode = FALSE;
409 g_pHalMVOPCtx->eSubRepeatField = E_MVOP_RPTFLD_NONE; /// mvop output repeating fields for single field input.
410 g_pHalMVOPCtx->eSubRgbFmt = E_MVOP_RGB_NONE;
411 g_pHalMVOPCtx->bSubIsInit = 0;
412 g_pHalMVOPCtx->bSubRptPreVsync = 0;
413 g_pHalMVOPCtx->bSubIs422 = 0;
414 g_pHalMVOPCtx->bSubIsH265 = 0;
415 g_pHalMVOPCtx->bSub3DLRAltOutput = FALSE; /// 3D L/R line alternative output
416 g_pHalMVOPCtx->bSub3DLRAltSBSOutput = FALSE;
417 g_pHalMVOPCtx->bSubIsHS = FALSE;
418 g_pHalMVOPCtx->u16SubCropXStart = 0;
419 g_pHalMVOPCtx->u16SubCropYStart = 0;
420 g_pHalMVOPCtx->u16SubCropXSize = 0;
421 g_pHalMVOPCtx->u16SubCropYSize = 0;
422 g_pHalMVOPCtx->bSubIsSetCrop = FALSE;
423 g_pHalMVOPCtx->bSubIsXcTrig = TRUE;
424 g_pHalMVOPCtx->u32SubMVOPFixClk = 0;
425 g_pHalMVOPCtx->bIsSubEnable = 0;
426 g_pHalMVOPCtx->bSubIs2p = 0;
427 g_pHalMVOPCtx->eSubInterlaceType = E_MVOP_PRO;
428 g_pHalMVOPCtx->u16SubHsize = 0;
429 #endif
430 }
431
_HAL_MVOP_InitContext(MS_BOOL * pbFirstDrvInstant)432 MVOP_HalInitCtxResults _HAL_MVOP_InitContext(MS_BOOL *pbFirstDrvInstant)
433 {
434 MS_BOOL bNeedInitShared = FALSE;
435
436 //check first init by MsOS_SHM_GetId / MSOS_SHM_QUERY
437 #if 0
438 if (g_pHalMVOPCtx)
439 {
440 // The context instance has been created already
441 // before somewhere sometime in the same process.
442 *pbFirstDrvInstant = bNeedInitShared;
443 //return E_MVOP_INIT_FAIL;
444 return E_MVOP_INIT_OK;
445 }
446 #endif
447
448 #if defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_LINUX_KERNEL)
449 MS_U32 u32ShmId;
450 MS_VIRT u32Addr;
451 MS_U32 u32BufSize;
452
453 //MsOS_SHM_Init(); init in msos_init
454 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux MVOP HAL driver", sizeof(MVOP_CTX_HAL), &u32ShmId, &u32Addr, &u32BufSize, MSOS_SHM_QUERY))
455 {
456 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux MVOP HAL driver", sizeof(MVOP_CTX_HAL), &u32ShmId, &u32Addr, &u32BufSize, MSOS_SHM_CREATE))
457 {
458 MVOP_DBG(MVOP_PRINTF("MVOP: SHM allocation failed!\n");)
459 return E_MVOP_INIT_FAIL;
460 }
461 MVOP_DBG(MVOP_PRINTF("MVOP: [%s][%d] This is first initial 0x%08lx\n", __FUNCTION__, __LINE__, u32Addr);)
462 memset( (MS_U8*)u32Addr, 0, sizeof(MVOP_CTX_HAL));
463 bNeedInitShared = TRUE;
464 g_pHalMVOPCtx = (MVOP_CTX_HAL*)u32Addr;
465 _HAL_MVOP_InitVarCtx();
466 #if MVOP_SUPPORT_SUB
467 _HAL_MVOP_SubInitVarCtx();
468 #endif
469 }
470 else
471 {
472 g_pHalMVOPCtx = (MVOP_CTX_HAL*)u32Addr;
473 bNeedInitShared = FALSE;
474 *pbFirstDrvInstant = bNeedInitShared;
475
476 return E_MVOP_INIT_ALREADY_EXIST;
477 }
478 #else
479 g_pHalMVOPCtx = &g_stmvopHalCtx;
480 bNeedInitShared = TRUE;
481 #endif
482 *pbFirstDrvInstant = bNeedInitShared;
483
484 if (bNeedInitShared)
485 {
486 memset(g_pHalMVOPCtx, 0, sizeof(*g_pHalMVOPCtx));
487 }
488
489 return E_MVOP_INIT_OK;
490 }
491
_HAL_MVOP_IsSupport4k2k2P(void)492 MS_BOOL _HAL_MVOP_IsSupport4k2k2P(void)
493 {
494 return FALSE;
495 }
496
HAL_MVOP_RegSetBase(MS_VIRT u32Base)497 void HAL_MVOP_RegSetBase(MS_VIRT u32Base)
498 {
499 u32RiuBaseAdd = u32Base;
500 }
501
HAL_MVOP_InitMirrorMode(MS_BOOL bMir)502 void HAL_MVOP_InitMirrorMode(MS_BOOL bMir)
503 {
504 //set bit[3:7] to support mirror mode
505 HAL_WriteRegBit(VOP_MIRROR_CFG, bMir, VOP_MIRROR_CFG_ENABLE);
506 }
507
HAL_MVOP_SetVerticalMirrorMode(MS_BOOL bEnable)508 void HAL_MVOP_SetVerticalMirrorMode(MS_BOOL bEnable)
509 {
510 if (g_pHalMVOPCtx == NULL)
511 {
512 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
513 return;
514 }
515
516 if (VOP_MIRROR_CFG_ENABLE != HAL_ReadRegBit(VOP_MIRROR_CFG, VOP_MIRROR_CFG_ENABLE))
517 {
518 //MVOP_PRINTF("Setup mirror mode\n");
519 HAL_MVOP_InitMirrorMode(TRUE);
520 }
521
522 HAL_WriteRegBit(VOP_MIRROR_CFG, bEnable, VOP_MIRROR_CFG_VEN);
523 g_pHalMVOPCtx->bMirrorModeVer = bEnable;
524 }
525
HAL_MVOP_SetHorizontallMirrorMode(MS_BOOL bEnable)526 void HAL_MVOP_SetHorizontallMirrorMode(MS_BOOL bEnable)
527 {
528 if (g_pHalMVOPCtx == NULL)
529 {
530 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
531 return;
532 }
533
534 if (VOP_MIRROR_CFG_ENABLE != HAL_ReadRegBit(VOP_MIRROR_CFG, VOP_MIRROR_CFG_ENABLE))
535 {
536 //MVOP_PRINTF("Setup mirror mode\n");
537 HAL_MVOP_InitMirrorMode(TRUE);
538 }
539
540 HAL_WriteRegBit(VOP_MIRROR_CFG, bEnable, VOP_MIRROR_CFG_HEN);
541 g_pHalMVOPCtx->bMirrorModeHor = bEnable;
542 }
543
HAL_SetTSPCW(MVOP_DevID eID)544 void HAL_SetTSPCW(MVOP_DevID eID)
545 {
546 HAL_WriteByte((REG_TSP_CLK + 1), 0x00);
547 HAL_WriteRegBit(REG_TSP_RST, 0, BIT1);
548 HAL_WriteRegBit(REG_TSP_RST, 1, BIT1);
549 }
550
HAL_MVOP_Init(void)551 void HAL_MVOP_Init(void)
552 {
553 MVOP_HalInitCtxResults eRet;
554 MS_BOOL pbFirstDrvInstant;
555
556 eRet = _HAL_MVOP_InitContext(&pbFirstDrvInstant);
557 if(eRet == E_MVOP_INIT_FAIL)
558 {
559 MVOP_DBG(MVOP_PRINTF("[%s] MVOP Context Init failed!\n",__FUNCTION__);)
560 return;
561 }
562 else if(eRet == E_MVOP_INIT_ALREADY_EXIST)
563 {
564 if(g_pHalMVOPCtx->bIsInit)
565 {
566 MVOP_DBG(MVOP_PRINTF("[%s] Main MVOP Context has Initialized!\n",__FUNCTION__);)
567 return;
568 }
569 }
570
571 HAL_MVOP_InitMirrorMode(TRUE);
572 //Enable dynamic clock gating
573 //Note: cannot enable VOP_GCLK_VCLK_ON, or hsync cannot be sent out.
574 HAL_WriteByteMask(VOP_GCLK, VOP_GCLK_MIU_ON, VOP_GCLK_MIU_ON|VOP_GCLK_VCLK_ON);
575 HAL_SetTSPCW(E_MVOP_DEV_0);
576 g_pHalMVOPCtx->bIsInit = 1;
577 }
578
HAL_MVOP_SetFieldInverse(MS_BOOL b2MVD,MS_BOOL b2IP)579 void HAL_MVOP_SetFieldInverse(MS_BOOL b2MVD, MS_BOOL b2IP)
580 {
581 // Set fld inv & ofld_inv
582 HAL_WriteRegBit(VOP_CTRL0+1, b2MVD, BIT3); //inverse the field to MVD
583 HAL_WriteRegBit(VOP_CTRL0+1, b2IP, BIT4); //inverse the field to IP
584 }
585
HAL_MVOP_SetChromaWeighting(MS_BOOL bEnable)586 void HAL_MVOP_SetChromaWeighting(MS_BOOL bEnable)
587 {
588 HAL_WriteRegBit(VOP_REG_WEIGHT_CTRL, bEnable, BIT1);
589 }
590
591 //load new value into active registers 0x20-0x26
HAL_MVOP_LoadReg(void)592 void HAL_MVOP_LoadReg(void)
593 {
594 HAL_WriteRegBit(VOP_REG_WR, 1, BIT0);
595 HAL_WriteRegBit(VOP_REG_WR, 0, BIT0);
596
597 HAL_WriteRegBit(VOP_REG_WR, 1, BIT4);
598 HAL_WriteRegBit(VOP_REG_WR, 0, BIT4);
599 }
600
601
HAL_MVOP_SetMIUReqMask(MS_BOOL bEnable)602 void HAL_MVOP_SetMIUReqMask(MS_BOOL bEnable)
603 {
604 #if 0 //[FIXME]
605 if (bEnable)
606 { // mask MVOP2MI to protect MIU
607 HAL_MIU_SetReqMask(MVOP_R, 1);
608 MsOS_DelayTask(1);
609 }
610 else
611 { // unmask MVOP2MI
612 MsOS_DelayTask(1);
613 HAL_MIU_SetReqMask(MVOP_R, 0);
614 }
615 #endif
616 MS_U8 u8Miu;
617
618 if(HAL_MVOP_GetIsOnlyMiuIPControl() == TRUE)
619 {
620 // mask msb mvop
621 u8Miu = (HAL_ReadByte(VOP_MIU_SEL) & VOP_MSB_BUF0_MIU_SEL) >> 4;
622 }
623 else
624 {
625 u8Miu = VOP_ON_MIU1;
626 }
627 eMIUClientID eClientID = MIU_CLIENT_MVOP_128BIT_R;
628 //MVOP_PRINTF("Enter %s bEnable=%x ReqMask=0x%x, 0x%x\n", __FUNCTION__, bEnable,
629 // HAL_ReadByte(0x1266), HAL_ReadByte(0x0666));
630 if (bEnable)
631 { // mask MVOP2MI to protect MIU
632 MDrv_MIU_MaskReq(u8Miu,eClientID);
633 MsOS_DelayTask(1);
634 }
635 else
636 { // unmask MVOP2MI
637 MsOS_DelayTask(1);
638 MDrv_MIU_UnMaskReq(u8Miu,eClientID);
639 }
640
641 //MVOP_PRINTF(">Exit %s bEnable=%x ReqMask=0x%x, 0x%x\n", __FUNCTION__, bEnable,
642 // HAL_ReadByte(0x1266), HAL_ReadByte(0x0666));
643 }
644
HAL_MVOP_Rst(void)645 void HAL_MVOP_Rst(void)
646 {
647 HAL_WriteRegBit(VOP_CTRL0, 0, BIT0);
648 HAL_WriteRegBit(VOP_CTRL0, 1, BIT0);
649
650 HAL_WriteRegBit(VOP_CTRL0, 0, BIT4);
651 HAL_WriteRegBit(VOP_CTRL0, 1, BIT4);
652
653 g_pHalMVOPCtx->bIsEnable = 1;
654 }
655
HAL_MVOP_Enable(MS_BOOL bEnable,MS_U8 u8Framerate)656 void HAL_MVOP_Enable(MS_BOOL bEnable, MS_U8 u8Framerate)
657 {
658 MS_U8 regval;
659
660 regval = HAL_ReadByte(VOP_CTRL0);
661
662 if ( bEnable )
663 {
664 regval |= 0x1;
665 }
666 else
667 {
668 regval &= ~0x1;
669 }
670
671 g_pHalMVOPCtx->bIsEnable = bEnable;
672
673 HAL_WriteByte(VOP_CTRL0, regval);
674 }
675
HAL_MVOP_GetEnableState(void)676 MS_BOOL HAL_MVOP_GetEnableState(void)
677 {
678 return (HAL_ReadRegBit(VOP_CTRL0, BIT0));
679 }
680
HAL_MVOP_GetMaxFreerunClk(void)681 HALMVOPFREQUENCY HAL_MVOP_GetMaxFreerunClk(void)
682 {
683 return HALMVOP_160MHZ;
684 }
685
HAL_MVOP_Get4k2kClk(void)686 HALMVOPFREQUENCY HAL_MVOP_Get4k2kClk(void)
687 {
688 return HALMVOP_NOT_SUPPORT;
689 }
690
HAL_MVOP_SetFrequency(HALMVOPFREQUENCY enFrequency)691 void HAL_MVOP_SetFrequency(HALMVOPFREQUENCY enFrequency)
692 {
693 // clear
694 HAL_WriteByteMask(REG_CKG_DC0, 0, CKG_DC0_MASK);
695 switch(enFrequency)
696 {
697 case HALMVOP_SYNCMODE:
698 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_SYNCHRONOUS, CKG_DC0_MASK);
699 break;
700 case HALMVOP_FREERUNMODE:
701 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_FREERUN, CKG_DC0_MASK);
702 break;
703 case HALMVOP_320MHZ:
704 //K6LITE not support 4k2k
705 //HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_320MHZ, CKG_DC0_MASK);
706 MVOP_PRINTF("Attention! not support 320MHz!\n");
707 break;
708 case HALMVOP_108MHZ:
709 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_108MHZ, CKG_DC0_MASK);
710 break;
711 case HALMVOP_123MHZ:
712 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_123MHZ, CKG_DC0_MASK);
713 break;
714 case HALMVOP_144MHZ:
715 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_144MHZ, CKG_DC0_MASK);
716 break;
717 case HALMVOP_160MHZ:
718 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_160MHZ, CKG_DC0_MASK);
719 break;
720 case HALMVOP_192MHZ:
721 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_192MHZ, CKG_DC0_MASK);
722 break;
723 default:
724 HAL_WriteByteMask(REG_CKG_DC0, CKG_DC0_160MHZ, CKG_DC0_MASK);
725 MVOP_PRINTF("Attention! In HAL_MVOP_SetFrequency default 160MHz!\n");
726 break;
727 }
728 }
729
HAL_MVOP_GetMaximumClk(void)730 HALMVOPFREQUENCY HAL_MVOP_GetMaximumClk(void)
731 {
732 return HALMVOP_192MHZ;
733 }
734
HAL_MVOP_GetCurrentClk(void)735 HALMVOPFREQUENCY HAL_MVOP_GetCurrentClk(void)
736 {
737 MS_U8 u8DC0Clk;
738 HALMVOPFREQUENCY mvopFreq;
739
740 u8DC0Clk = HAL_ReadByte(REG_CKG_DC0)&CKG_DC0_MASK;
741
742 switch(u8DC0Clk)
743 {
744 case CKG_DC0_SYNCHRONOUS:
745 mvopFreq = HALMVOP_SYNCMODE;
746 break;
747 case CKG_DC0_FREERUN:
748 mvopFreq = HALMVOP_FREERUNMODE;
749 break;
750 case CKG_DC0_144MHZ:
751 mvopFreq = HALMVOP_144MHZ;
752 break;
753 case CKG_DC0_160MHZ:
754 mvopFreq = HALMVOP_160MHZ;
755 break;
756 case CKG_DC0_320MHZ:
757 mvopFreq = HALMVOP_320MHZ;
758 break;
759 default:
760 mvopFreq = 0;
761 break;
762 }
763 return mvopFreq;
764 }
765
HAL_MVOP_SetOutputInterlace(MS_BOOL bEnable,MS_U16 u16ECOVersion)766 void HAL_MVOP_SetOutputInterlace(MS_BOOL bEnable, MS_U16 u16ECOVersion)
767 {
768 MS_U8 regval;
769
770 regval = HAL_ReadByte(VOP_CTRL0);
771
772 if ( bEnable )
773 {
774 regval |= 0x80;
775 HAL_WriteRegBit(VOP_REG_BW_SAVE, 0, VOP_420_BW_SAVE_EX);
776 }
777 else
778 {
779 regval &= ~0x80;
780 }
781 //Kano patch for GOP
782 HAL_WriteRegBit(VOP_TST_IMG, bEnable, VOP_SC_VS_INV);
783 HAL_WriteByte(VOP_CTRL0, regval);
784 }
785
HAL_MVOP_SetPattern(MVOP_Pattern enMVOPPattern)786 void HAL_MVOP_SetPattern(MVOP_Pattern enMVOPPattern)
787 {
788 HAL_WriteByteMask(VOP_TST_IMG, enMVOPPattern, BIT2 | BIT1 | BIT0);
789 }
790
HAL_MVOP_SetTileFormat(MVOP_TileFormat eTileFmt)791 MS_BOOL HAL_MVOP_SetTileFormat(MVOP_TileFormat eTileFmt)
792 {
793 if (eTileFmt == E_MVOP_TILE_8x32)
794 {
795 HAL_WriteRegBit(VOP_REG_WR, 0, BIT1);
796 return TRUE;
797 }
798 else if (eTileFmt == E_MVOP_TILE_16x32)
799 {
800 HAL_WriteRegBit(VOP_REG_WR, 1, BIT1);
801 return TRUE;
802 }
803 else if (eTileFmt == E_MVOP_TILE_32x16)
804 {
805 HAL_WriteRegBit(VOP_REG_WR, 0, BIT1);
806 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 1, EVD_ENABLE);
807 return TRUE;
808 }
809 else if (eTileFmt == E_MVOP_TILE_32x32)
810 {
811 HAL_WriteRegBit(VOP_REG_WR, 0, BIT1);
812 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 0, EVD_ENABLE);
813 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 1, VOP_TILE_32x32);
814 return TRUE;
815 }
816 else
817 {
818 return FALSE;
819 }
820 }
821
HAL_MVOP_GetSupportRgbFormat(MVOP_RgbFormat eRgbFmt)822 MS_BOOL HAL_MVOP_GetSupportRgbFormat(MVOP_RgbFormat eRgbFmt)
823 {
824 if ((eRgbFmt == E_MVOP_RGB_565) || (eRgbFmt == E_MVOP_RGB_888))
825 {
826 return TRUE;
827 }
828 return FALSE;
829 }
830
HAL_MVOP_SetRgbFormat(MVOP_RgbFormat eRgbFmt)831 MS_BOOL HAL_MVOP_SetRgbFormat(MVOP_RgbFormat eRgbFmt)
832 {
833 MS_BOOL bRet = FALSE;
834
835 if (g_pHalMVOPCtx == NULL)
836 {
837 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
838 return FALSE;
839 }
840
841 if (eRgbFmt == E_MVOP_RGB_NONE)
842 {
843 HAL_WriteByteMask(VOP_RGB_FMT, 0, VOP_RGB_FMT_SEL);
844 bRet = TRUE;
845 }
846 else if (eRgbFmt == E_MVOP_RGB_565)
847 {
848 HAL_WriteByteMask(VOP_RGB_FMT, VOP_RGB_FMT_565, VOP_RGB_FMT_SEL);
849 bRet = TRUE;
850 }
851 else if (eRgbFmt == E_MVOP_RGB_888)
852 {
853 HAL_WriteByteMask(VOP_RGB_FMT, VOP_RGB_FMT_888, VOP_RGB_FMT_SEL);
854 bRet = TRUE;
855 }
856
857 if (bRet == TRUE)
858 {
859 g_pHalMVOPCtx->eMainRgbFmt = eRgbFmt;
860 }
861 return bRet;
862 }
863
HAL_MVOP_SetBlackBG(void)864 void HAL_MVOP_SetBlackBG(void)
865 {
866 MS_U8 regval;
867
868 //set MVOP test pattern to black
869 HAL_WriteByte((VOP_TST_IMG + 1), 0x10);
870 HAL_WriteByte(VOP_U_PAT , 0x80);
871 HAL_WriteByte((VOP_U_PAT + 1), 0x80);
872
873 regval = HAL_ReadByte(VOP_TST_IMG);
874 HAL_WriteByteMask(VOP_TST_IMG, 0x02, BIT2 | BIT1 | BIT0);
875 HAL_WriteByteMask(VOP_TST_IMG, 0x00, BIT2 | BIT1 | BIT0);
876 HAL_WriteByteMask(VOP_TST_IMG, regval, BIT2 | BIT1 | BIT0);
877 }
878
HAL_MVOP_SetCropWindow(MVOP_InputCfg * pparam)879 void HAL_MVOP_SetCropWindow(MVOP_InputCfg *pparam)
880 {
881 #if 1
882 UNUSED(pparam);
883 #else // enable it when test code is ready
884 MS_U32 x, y;
885 MS_U32 u32offset;
886
887 if(!pparam)
888 {
889 return;
890 }
891 //set MVOP test pattern to black
892 HAL_MVOP_SetBlackBG();
893 #if 0
894 if((pparam->enVideoType == MVOP_H264) && (pparam->u16StripSize == 1920))
895 {
896 pparam->u16StripSize = 1952;
897 }
898 #endif
899 if((pparam->enVideoType == MVOP_MPG) || (pparam->enVideoType == MVOP_MPEG4))
900 {
901 pparam->u16CropX = (pparam->u16CropX >> 3) << 3; // 8 bytes align
902 pparam->u16CropY = (pparam->u16CropY >> 6) << 6; // 64 bytes align
903 }
904 else if((pparam->enVideoType == MVOP_H264) || (pparam->enVideoType == MVOP_RM))
905 {
906 pparam->u16CropX = (pparam->u16CropX >> 4) << 4; // 16 bytes align
907 pparam->u16CropY = (pparam->u16CropY >> 6) << 6; // 64 bytes align
908 }
909 else
910 {
911 MS_ASSERT(0);
912 }
913
914 x = (MS_U32)pparam->u16CropX;
915 y = (MS_U32)pparam->u16CropY;
916
917 // y offset
918 u32offset = ((y * pparam->u16StripSize + (x << 5)) >> 3);
919 HAL_WriteByte((VOP_JPG_YSTR0_L ), (MS_U8)(u32offset));
920 HAL_WriteByte((VOP_JPG_YSTR0_L + 1), (MS_U8)(u32offset >> 8));
921 HAL_WriteByte((VOP_JPG_YSTR0_H ), (MS_U8)(u32offset >> 16));
922 HAL_WriteByte((VOP_JPG_YSTR0_H + 1), (MS_U8)((u32offset >> 24) & VOP_YUV_STR_HIBITS));
923
924 // uv offset
925 u32offset = ((y >> 1) * pparam->u16StripSize + (x << 5)) >> 3;
926 HAL_WriteByte((VOP_JPG_UVSTR0_L ), (MS_U8)(u32offset));
927 HAL_WriteByte((VOP_JPG_UVSTR0_L + 1), (MS_U8)(u32offset >> 8));
928 HAL_WriteByte((VOP_JPG_UVSTR0_H ), (MS_U8)(u32offset >> 16));
929 HAL_WriteByte((VOP_JPG_UVSTR0_H + 1), (MS_U8)((u32offset >> 24) & VOP_YUV_STR_HIBITS));
930
931 pparam->u16CropWidth= (pparam->u16CropWidth >> 3) << 3;
932 // HSize, VSize
933 HAL_WriteByte((VOP_JPG_HSIZE ), LOWBYTE(pparam->u16CropWidth ));
934 HAL_WriteByte((VOP_JPG_HSIZE + 1), HIGHBYTE(pparam->u16CropWidth ));
935 HAL_WriteByte((VOP_JPG_VSIZE ), LOWBYTE(pparam->u16CropHeight));
936 HAL_WriteByte((VOP_JPG_VSIZE + 1), HIGHBYTE(pparam->u16CropHeight ));
937
938 HAL_WriteByteMask(VOP_MPG_JPG_SWITCH, BIT0, BIT1|BIT0);
939
940 // clear extend strip len bit by default
941 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);
942 if((pparam->enVideoType == MVOP_MPG) || (pparam->enVideoType == MVOP_MPEG4))
943 {
944 // Disable H264 or RM Input
945 HAL_WriteRegBit(VOP_INPUT_SWITCH1, 0, BIT2|BIT3);
946 //8*32 tile format
947 HAL_WriteRegBit(VOP_REG_WR, 0, BIT1);
948 }
949 else if((pparam->enVideoType == MVOP_H264) || (pparam->enVideoType == MVOP_RM))
950 {
951 //16*32 tile format
952 HAL_WriteRegBit(VOP_REG_WR, 1, BIT1);
953 // SVD mode enable
954 HAL_WriteByteMask(VOP_INPUT_SWITCH1, BIT3, BIT2|BIT3);
955 // set mvop to 64bit interface
956 HAL_WriteByteMask(VOP_MIU_IF, VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
957 }
958 HAL_MVOP_LoadReg();
959 #endif
960 }
961
HAL_MVOP_SetRepeatField(MVOP_RptFldMode eMode)962 void HAL_MVOP_SetRepeatField(MVOP_RptFldMode eMode)
963 {
964 if (g_pHalMVOPCtx == NULL)
965 {
966 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
967 return;
968 }
969 g_pHalMVOPCtx->eRepeatField = eMode;
970 }
971
HAL_MVOP_SetFDMaskFromMVD(MS_BOOL bEnable)972 void HAL_MVOP_SetFDMaskFromMVD(MS_BOOL bEnable)
973 {
974 HAL_WriteRegBit(VOP_REG_FD_MASK_SEL, bEnable, BIT5); //FD MASK from MVD
975 }
976
HAL_MVOP_SetInputMode(VOPINPUTMODE mode,MVOP_InputCfg * pparam,MS_U16 u16ECOVersion)977 void HAL_MVOP_SetInputMode( VOPINPUTMODE mode, MVOP_InputCfg *pparam, MS_U16 u16ECOVersion)
978 {
979 MS_U8 regval;
980 MS_U16 u16strip, u16strip_lsb;
981
982 if (g_pHalMVOPCtx == NULL)
983 {
984 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
985 return;
986 }
987 #if 0
988 /*****************************************************/
989 // Reset MVOP setting
990 HAL_WriteByte(VOP_TST_IMG, 0x40); //reset test pattern or BG
991 HAL_MVOP_Set3DLRAltOutput_VHalfScaling(DISABLE); //reset to default: disable 3D L/R alternative output.
992 HAL_MVOP_Set3DLR2ndCfg(DISABLE); //reset to default: disable 3D L/R 2nd pitch.
993 HAL_MVOP_SetRgbFormat(E_MVOP_RGB_NONE); //reset rgb format
994 HAL_WriteRegBit(VOP_CTRL1, 0, VOP_MVD_VS_MD); //default use original vsync
995 //stb series
996 HAL_WriteRegBit(VOP_REG_422_OUT_EN, 1, BIT0);
997 HAL_WriteRegBit(VOP_HANDSHAKE, 1, VOP_HANDSHAKE_MODE);
998 HAL_MVOP_SetTimingFromXC(E_MVOP_DEV_0, TRUE);
999
1000 //set MVOP test pattern to black
1001 HAL_MVOP_SetBlackBG();
1002
1003 // clear extend strip len bit by default
1004 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);
1005
1006 // set mvop to 128bit_i128 interface
1007 HAL_WriteByteMask(VOP_MIU_IF, VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
1008
1009 // Disable H264 or RM Input
1010 HAL_WriteRegBit(VOP_INPUT_SWITCH1, 0, BIT2|BIT3);
1011 // Clear 422 Flag
1012 g_pHalMVOPCtx->bIs422 = 0;
1013 //8*32 tile format
1014 HAL_WriteRegBit(VOP_REG_WR, 0, BIT1);
1015 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD);
1016
1017 // EVD mode disable
1018 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 0, EVD_ENABLE);
1019 // Clear evd Flag for interlace mode setting
1020 g_pHalMVOPCtx->bIsH265 = 0;
1021 HAL_WriteRegBit(VOP_INFO_FROM_CODEC_L, 1, BIT3);
1022 HAL_WriteRegBit(VOP_MIRROR_CFG, 1, BIT5);
1023 // EVD 10 bits disable
1024 HAL_WriteByteMask(VOP_REG_MASK, BIT1, VOP_LSB_REQ_MASK);
1025 HAL_WriteRegBit(VOP_EVD_10B_EN, 0, VOP_EVD_10B_Y_EN);
1026 HAL_WriteRegBit(VOP_EVD_10B_EN, 0, VOP_EVD_10B_UV_EN);
1027 HAL_WriteRegBit(VOP_UV_SHIFT, 1, VOP_GCLK_MIU_ON);
1028 // Disable 420 BW Saving mode
1029 HAL_WriteRegBit(VOP_REG_DUMMY, 0, VOP_420_BW_SAVE);
1030 HAL_WriteRegBit(VOP_REG_BW_SAVE, 0, VOP_420_BW_SAVE_EX);
1031 // Disable New Vsync Mode
1032 g_pHalMVOPCtx->bNewVSyncMode = FALSE;
1033 // Disable 2p mode
1034 HAL_MVOP_SetEnable4k2k2P(FALSE);
1035 /* only for STB DC */
1036 // Handshake mode chip need to set from MVD: Kappa (maybe fix in after project)
1037 HAL_MVOP_SetFDMaskFromMVD(ENABLE);
1038 // Use frame sync (CLK_DC1 domain) to reset CLK_DC0 and CLK_MIU domain every frame
1039 HAL_WriteRegBit(VOP_REG_FRAME_RST+1, 0, BIT7); // reg_frame_rst = 0
1040
1041 // Kappa do not need to invert DC2SC field; the inverse was setted in SC XC_BK02_33[3]=1
1042 HAL_MVOP_SetFieldInverse(ENABLE, DISABLE);
1043 // kappa U02 need to bypass field from mvd to xc for FCR.
1044 HAL_WriteRegBit(VOP_REG_DUMMY_3D_1, 1, VOP_RGB_FILED_BYPASS);
1045
1046 // Clippers temp patch: New diu interface, waiting for decoder adding diu setting.
1047 HAL_WriteByteMask(VOP_INFO_FROM_CODEC_H, 0, VOP_INFO_FROM_CODEC_MIU_BUF0_SEL | VOP_INFO_FROM_CODEC_MIU_BUF1_SEL | VOP_INFO_FROM_CODEC_10BIT);
1048
1049 //Change MIU BW Default Value to 0x241C (after Einstein)
1050 //FIFO threshold
1051 HAL_WriteByteMask(VOP_DMA0, 0x08, VOP_FORCE_HIGH|VOP_HI_TSH|VOP_BURST_EXT);
1052 //burst and priority
1053 HAL_WriteByteMask(VOP_DMA1, 0x22, VOP_FORCE_HIGH|VOP_HI_TSH|VOP_BURST_EXT);
1054 HAL_WriteByte(VOP_BURST_CTRL0, 0x02);
1055 HAL_WriteByte(VOP_BURST_CTRL1, 0x00);
1056 //// clippers crop sw patch /////
1057 HAL_WriteRegBit(VOP_REG_SINGLE_3D_L, 0, VOP_FORCE_SKIP);
1058 HAL_WriteByteMask(VOP_REG_SINGLE_3D_L, 0, VOP_SKIP_SIZE_LVIEW);
1059 HAL_WriteByteMask(VOP_REG_SINGLE_3D_H, 0, VOP_SKIP_SIZE_RVIEW);
1060 HAL_WriteRegBit(VOP_REG_ENABLE_SKIP, 0, VOP_SKIP_LVIEW);
1061 HAL_WriteRegBit(VOP_REG_ENABLE_SKIP, 0, VOP_SKIP_RVIEW);
1062 g_pHalMVOPCtx->g_u16SetStartX = 0;
1063 g_pHalMVOPCtx->g_u16SetStartY = 0;
1064 g_pHalMVOPCtx->g_u16SetXSize = 0;
1065 g_pHalMVOPCtx->g_u16SetYSize = 0;
1066 g_pHalMVOPCtx->g_bIsY4Align = FALSE;
1067 g_pHalMVOPCtx->g_bIsSetCrop = FALSE;
1068 g_pHalMVOPCtx->bIsXcTrig = FALSE;
1069 g_pHalMVOPCtx->bSubIsXcTrig = FALSE;
1070 /*****************************************************/
1071 #endif
1072
1073 //regval = HAL_ReadByte(VOP_MPG_JPG_SWITCH);
1074 regval = 0;
1075 regval |= ( mode & 0x3 );
1076
1077 if ( mode == VOPINPUT_HARDWIRE )
1078 {
1079 HAL_WriteByte(VOP_MPG_JPG_SWITCH, regval);
1080 }
1081 else if ( mode == VOPINPUT_HARDWIRECLIP )
1082 {
1083 HAL_WriteByte(VOP_MPG_JPG_SWITCH, regval);
1084
1085 // HSize, VSize
1086 HAL_WriteByte(VOP_JPG_HSIZE , LOWBYTE( pparam->u16HSize ));
1087 HAL_WriteByte((VOP_JPG_HSIZE + 1), HIGHBYTE( pparam->u16HSize ));
1088 HAL_WriteByte(VOP_JPG_VSIZE , LOWBYTE( pparam->u16VSize ));
1089 HAL_WriteByte((VOP_JPG_VSIZE + 1), HIGHBYTE( pparam->u16VSize ));
1090 }
1091 else if (mode == VOPINPUT_MCUCTRL)
1092 {
1093 g_pHalMVOPCtx->bMirrorMode = (g_pHalMVOPCtx->bMirrorModeVer||g_pHalMVOPCtx->bMirrorModeHor);
1094 if ( pparam->bProgressive )
1095 regval |= 0x4;
1096 else
1097 {
1098 regval &= ~0x4;
1099 regval |= 0x1; //reg_dc_md=b'11 for interlace input
1100 if (E_MVOP_RPTFLD_NONE == g_pHalMVOPCtx->eRepeatField)
1101 {
1102 MVOP_DBG("%s normal NOT repeat field %x\n", __FUNCTION__, g_pHalMVOPCtx->eRepeatField);
1103 //To support mcu mode interlace, need to set h'3B[9]=1,
1104 //h'11[12]=0, and Y1/UV1 address equal to Y0/UV0 address.
1105 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 1, VOP_REF_SELF_FLD);
1106 //HAL_MVOP_SetFieldInverse(ENABLE, DISABLE); //do not inverse in kano: mvop gen timing + hsk mode
1107 // mheg5, mcu mode for i mode, do not bypass, 0x11[6] = 0: mvop t/b toggle
1108 HAL_WriteRegBit(VOP_REG_DUMMY_3D_1, 0, VOP_RGB_FILED_BYPASS);
1109 HAL_WriteRegBit(VOP_CTRL0, 0, VOP_EXTFLD_EN);
1110 }
1111 }
1112 // disable from wb
1113 //HAL_WriteRegBit(VOP_REG_MFDEC_2_L, 0, VOP_MF_FROM_WB);
1114 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 0, VOP_R2_WISHBONE);
1115 HAL_WriteRegBit(VOP_REG_DUMMY, 0, VOP_32x32_WB);
1116
1117 if ( pparam->bYUV422 )
1118 regval |= 0x10;
1119 else
1120 regval &= ~0x10;
1121
1122 if ( pparam->b422pack )
1123 regval |= 0x80;
1124
1125 if ( pparam->bDramRdContd == 1 )
1126 regval |= 0x20;
1127 else
1128 regval &= ~0x20;
1129
1130 // for backward compatable to saturn
1131 // [3] UV-7bit mode don't care
1132 // [5] dram_rd_md =0
1133 // [6] Fld don't care
1134 // [7] 422pack don'care
1135 HAL_WriteByte(VOP_MPG_JPG_SWITCH, regval);
1136 g_pHalMVOPCtx->bIs422 = pparam->bYUV422;
1137 HAL_WriteRegBit(VOP_REG_DUMMY, !(pparam->bYUV422), VOP_420_BW_SAVE);
1138 HAL_WriteRegBit(VOP_REG_BW_SAVE, !(pparam->bYUV422), VOP_420_BW_SAVE_EX);
1139
1140 if (pparam->u16StripSize == 0)
1141 {
1142 if (pparam->bSD)
1143 {
1144 u16strip = 720;
1145 u16strip_lsb = 720;
1146 }
1147 else
1148 {
1149 u16strip = 1920;
1150 u16strip_lsb = 1920;
1151 }
1152 }
1153 else
1154 {
1155 u16strip = pparam->u16StripSize;
1156 u16strip_lsb = pparam->u16StripSize;
1157 }
1158
1159 // set dc_strip[7:0]
1160 if ( pparam->bDramRdContd == 0 )
1161 {
1162 u16strip = (u16strip + 31) / 32 * 32; //need align for monaco
1163 u16strip = u16strip/8;
1164 u16strip_lsb = (u16strip_lsb+127)/128;
1165 u16strip_lsb *= 4;
1166 }
1167 else
1168 {
1169 if ( pparam->b422pack )
1170 {
1171 if (E_MVOP_RGB_888 == g_pHalMVOPCtx->eMainRgbFmt)
1172 {
1173 u16strip *= 2; //4bytes/pixel (yuv422:2bytes/pixel)
1174 }
1175 //VOP_REG_STRIP_ALIGN and Mirror mode are mutually exclusive, after M10(support mirror), VOP_DC_STRIP_H
1176 //replace VOP_REG_STRIP_ALIGN, which supported maximun Hsize is 8188
1177 #if 0
1178 // [071016 Andy] support YUV422 pack mode
1179 if ((u16strip < 1024) || g_pHalMVOPCtx->bMirrorMode)
1180 {
1181 u16strip = u16strip/4;
1182 // dont extend strip len
1183 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);
1184 }
1185 else
1186 {
1187 u16strip = u16strip/8;
1188 // extend strip len to 2048
1189 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 1, BIT0);
1190 }
1191 #endif
1192 u16strip = u16strip/4;
1193 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);
1194 }
1195 else
1196 {
1197 u16strip = u16strip/8;
1198 }
1199 }
1200
1201 if (u16strip >= 256 )
1202 {
1203 HAL_WriteByte(VOP_DC_STRIP_H, (u16strip>>8));
1204 //reg_dc_strip_h[2:0] = reg_dc_strip[10:8]
1205 }
1206 else
1207 {
1208 HAL_WriteByteMask(VOP_DC_STRIP_H, 0, BIT0 | BIT1 | BIT2);
1209 }
1210
1211 regval = u16strip;
1212 HAL_WriteByte(VOP_DC_STRIP, regval);
1213 //LSB strip
1214 HAL_WriteByte(VOP_DC_STRIP_LSB, u16strip_lsb & 0x3ff);
1215
1216
1217 HAL_MVOP_SetYUVBaseAdd(pparam->u32YOffset, pparam->u32UVOffset,
1218 pparam->bProgressive, pparam->b422pack);
1219
1220 if (E_MVOP_RPTFLD_NONE != g_pHalMVOPCtx->eRepeatField)
1221 {
1222 MVOP_DBG("%s reset eRepeatField=%x ==>", __FUNCTION__, g_pHalMVOPCtx->eRepeatField);
1223 //To output the same field for single field input,
1224 //do NOT set h'3B[9]=1 and h'11[12]=0
1225 g_pHalMVOPCtx->eRepeatField = E_MVOP_RPTFLD_NONE; //reset the flag to repeat field
1226 MVOP_DBG(" %x\n", g_pHalMVOPCtx->eRepeatField);
1227 }
1228
1229 // HSize
1230 MS_U16 u16HSize = ALIGN_UPTO_16(pparam->u16HSize);
1231 if (u16HSize != pparam->u16HSize)
1232 {
1233 MVOP_DBG(MVOP_PRINTF("\n\n Change HSize %d to %d\n", pparam->u16HSize, u16HSize);)
1234 }
1235 HAL_WriteByte(VOP_JPG_HSIZE , LOWBYTE( u16HSize ));
1236 HAL_WriteByte((VOP_JPG_HSIZE + 1), HIGHBYTE( u16HSize ));
1237
1238 // VSize
1239 MS_U16 u16VSize = pparam->u16VSize;
1240 if (g_pHalMVOPCtx->bMirrorModeVer)
1241 {
1242 u16VSize = ALIGN_UPTO_4(pparam->u16VSize);
1243 MVOP_DBG(MVOP_PRINTF("\n\n Change VSize %d to %d\n", pparam->u16VSize, u16VSize);)
1244 }
1245 HAL_WriteByte(VOP_JPG_VSIZE , LOWBYTE( u16VSize ));
1246 HAL_WriteByte((VOP_JPG_VSIZE + 1), HIGHBYTE( u16VSize ));
1247 }
1248
1249 HAL_MVOP_LoadReg();
1250 }
1251
1252
HAL_MVOP_EnableUVShift(MS_BOOL bEnable)1253 void HAL_MVOP_EnableUVShift(MS_BOOL bEnable)
1254 {
1255 MS_U8 regval;
1256
1257 regval = HAL_ReadByte(VOP_MPG_JPG_SWITCH);
1258
1259 if (((regval & BIT4) == BIT4) && ((regval & 0x3)== 0x2))
1260 { // 422 with MCU control mode
1261 if (bEnable)
1262 {
1263 MS_ASSERT(0);
1264 }
1265 }
1266
1267 // output 420 and interlace
1268 //[IP - Sheet] : Main Page --- 420CUP
1269 //[Project] : Titania2
1270 //[Description]: Chroma artifacts when 420to422 is applied duplicate method.
1271 //[Root cause]: Apply 420to422 average algorithm to all DTV input cases.
1272 //The average algorithm must cooperate with MVOP.
1273 HAL_WriteByteMask(VOP_UV_SHIFT, (bEnable)?1:0, 0x3);
1274 }
1275
1276 static MS_BOOL _bEnable60P = false;
HAL_MVOP_SetEnable60P(MS_BOOL bEnable)1277 void HAL_MVOP_SetEnable60P(MS_BOOL bEnable)
1278 {
1279 _bEnable60P = bEnable;
1280 }
1281
1282 static MS_BOOL _bEnable4k2kClk = false;
HAL_MVOP_SetEnable4k2kClk(MS_BOOL bEnable)1283 void HAL_MVOP_SetEnable4k2kClk(MS_BOOL bEnable)
1284 {
1285 _bEnable4k2kClk = bEnable;
1286 }
1287
HAL_MVOP_SetEnable4k2k2P(MS_BOOL bEnable)1288 void HAL_MVOP_SetEnable4k2k2P(MS_BOOL bEnable)
1289 {
1290 g_pHalMVOPCtx->bIs2p = bEnable;
1291 HAL_WriteRegBit(VOP_REG_4K2K_2P, bEnable, VOP_4K2K_2P);
1292 HAL_MVOP_Set420BWSaveMode(bEnable);
1293 }
1294
HAL_MVOP_Get4k2k2PMode(MVOP_DevID eID)1295 MS_BOOL HAL_MVOP_Get4k2k2PMode(MVOP_DevID eID)
1296 {
1297 MS_BOOL bEnable4k2k2P = FALSE;
1298 switch(eID)
1299 {
1300 case E_MVOP_DEV_0:
1301 bEnable4k2k2P = g_pHalMVOPCtx->bIs2p;
1302 break;
1303 #if MVOP_SUPPORT_SUB
1304 case E_MVOP_DEV_1:
1305 bEnable4k2k2P = g_pHalMVOPCtx->bSubIs2p;
1306 break;
1307 #endif
1308 default:
1309 MVOP_PRINTF("Attention! %s Not support eID=%u yet\n", __FUNCTION__, eID);
1310 break;
1311 }
1312 return bEnable4k2k2P;
1313 }
1314
1315 static MS_BOOL _bEnableFixClk = false;
HAL_MVOP_SetEnableFixClk(MS_BOOL bEnable)1316 void HAL_MVOP_SetEnableFixClk(MS_BOOL bEnable)
1317 {
1318 _bEnableFixClk = bEnable;
1319 }
1320
HAL_MVOP_EnableFreerunMode(MS_BOOL bEnable)1321 void HAL_MVOP_EnableFreerunMode(MS_BOOL bEnable)
1322 {
1323 if (g_pHalMVOPCtx == NULL)
1324 {
1325 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
1326 return;
1327 }
1328 g_pHalMVOPCtx->bEnableFreerunMode = bEnable;
1329 }
1330
HAL_MVOP_SetVSyncMode(MS_U8 u8Mode)1331 void HAL_MVOP_SetVSyncMode(MS_U8 u8Mode)
1332 {
1333 if (g_pHalMVOPCtx == NULL)
1334 {
1335 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
1336 return;
1337 }
1338 if (1==u8Mode)
1339 {
1340 g_pHalMVOPCtx->bNewVSyncMode = TRUE;
1341 }
1342 else
1343 {
1344 g_pHalMVOPCtx->bNewVSyncMode = FALSE;
1345 }
1346 }
1347
HAL_MVOP_SetOutputTiming(MVOP_Timing * ptiming)1348 void HAL_MVOP_SetOutputTiming( MVOP_Timing *ptiming )
1349 {
1350 MS_U8 regval;
1351
1352 if (g_pHalMVOPCtx == NULL)
1353 {
1354 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
1355 return;
1356 }
1357
1358 HAL_WriteByte(VOP_FRAME_VCOUNT , LOWBYTE( ptiming->u16V_TotalCount ));
1359 HAL_WriteByte((VOP_FRAME_VCOUNT + 1), HIGHBYTE( ptiming->u16V_TotalCount ));
1360 HAL_WriteByte(VOP_FRAME_HCOUNT , LOWBYTE( ptiming->u16H_TotalCount ));
1361 HAL_WriteByte((VOP_FRAME_HCOUNT + 1), HIGHBYTE( ptiming->u16H_TotalCount ));
1362
1363 HAL_WriteByte((VOP_VB0_STR ), LOWBYTE( ptiming->u16VBlank0_Start ));
1364 HAL_WriteByte((VOP_VB0_STR + 1), HIGHBYTE( ptiming->u16VBlank0_Start ));
1365 HAL_WriteByte((VOP_VB0_END ), LOWBYTE( ptiming->u16VBlank0_End ));
1366 HAL_WriteByte((VOP_VB0_END + 1), HIGHBYTE( ptiming->u16VBlank0_End ));
1367 HAL_WriteByte((VOP_VB1_STR ), LOWBYTE( ptiming->u16VBlank1_Start ));
1368 HAL_WriteByte((VOP_VB1_STR + 1), HIGHBYTE( ptiming->u16VBlank1_Start ));
1369 HAL_WriteByte((VOP_VB1_END ), LOWBYTE( ptiming->u16VBlank1_End ));
1370 HAL_WriteByte((VOP_VB1_END + 1), HIGHBYTE( ptiming->u16VBlank1_End ));
1371 HAL_WriteByte((VOP_TF_STR ), LOWBYTE( ptiming->u16TopField_Start ));
1372 HAL_WriteByte((VOP_TF_STR + 1), HIGHBYTE( ptiming->u16TopField_Start ));
1373 HAL_WriteByte((VOP_BF_STR ), LOWBYTE( ptiming->u16BottomField_Start ));
1374 HAL_WriteByte((VOP_BF_STR + 1), HIGHBYTE( ptiming->u16BottomField_Start ));
1375 HAL_WriteByte((VOP_HACT_STR ), LOWBYTE( ptiming->u16HActive_Start ));
1376 HAL_WriteByte((VOP_HACT_STR + 1), HIGHBYTE( ptiming->u16HActive_Start ));
1377
1378 HAL_WriteByte((VOP_TF_VS ), LOWBYTE( ptiming->u16TopField_VS ));
1379 HAL_WriteByte((VOP_TF_VS + 1), HIGHBYTE( ptiming->u16TopField_VS ));
1380 HAL_WriteByte((VOP_BF_VS ), LOWBYTE( ptiming->u16BottomField_VS ));
1381 HAL_WriteByte((VOP_BF_VS + 1), HIGHBYTE( ptiming->u16BottomField_VS ));
1382
1383 //if(((ptiming->u16V_TotalCount > 2160) || (ptiming->u16H_TotalCount > 3840)) && (ptiming->u8Framerate >= 30))
1384 if((!g_pHalMVOPCtx->bIsXcTrig) && (g_pHalMVOPCtx->bIsHS))
1385 {
1386 g_pHalMVOPCtx->bNewVSyncMode = TRUE;
1387 }
1388
1389 if (g_pHalMVOPCtx->bNewVSyncMode)
1390 {
1391 #define NEW_VSYNC_MODE_ADVANCE_LINECNT 30
1392 MVOP_DBG(MVOP_PRINTF("MVOP use new vync mode, forwarding %d lines\n",NEW_VSYNC_MODE_ADVANCE_LINECNT);)
1393
1394 MS_U16 u16BottomField_VS2MVD = ptiming->u16BottomField_VS - NEW_VSYNC_MODE_ADVANCE_LINECNT;
1395 MVOP_DBG(MVOP_PRINTF("BottomField VS ori=0x%x, new=0x%x\n", ptiming->u16BottomField_VS, u16BottomField_VS2MVD);)
1396 HAL_WriteByte((VOP_BF_VS_MVD ), LOWBYTE( u16BottomField_VS2MVD ));
1397 HAL_WriteByte((VOP_BF_VS_MVD + 1), HIGHBYTE( u16BottomField_VS2MVD ));
1398
1399 MS_U16 u16TopField_VS2MVD = ptiming->u16V_TotalCount - NEW_VSYNC_MODE_ADVANCE_LINECNT;
1400 MVOP_DBG(MVOP_PRINTF("TopField VS Vtt=0x%x, new=0x%x\n", ptiming->u16V_TotalCount, u16TopField_VS2MVD);)
1401 HAL_WriteByte((VOP_TF_VS_MVD ), LOWBYTE( u16TopField_VS2MVD ));
1402 HAL_WriteByte((VOP_TF_VS_MVD + 1), HIGHBYTE( u16TopField_VS2MVD ));
1403
1404 HAL_WriteRegBit(VOP_GCLK, 0, VOP_GCLK_MIU_ON);
1405
1406 HAL_WriteRegBit(VOP_CTRL1, 1, VOP_MVD_VS_MD); //Use new vsync
1407
1408 g_pHalMVOPCtx->bNewVSyncMode = FALSE; //restore to original mode
1409 }
1410 else
1411 {
1412 MS_U16 u16BottomField_VS2MVD = 0x200;
1413 HAL_WriteByte((VOP_BF_VS_MVD ), LOWBYTE( u16BottomField_VS2MVD ));
1414 HAL_WriteByte((VOP_BF_VS_MVD + 1), HIGHBYTE( u16BottomField_VS2MVD ));
1415
1416 MS_U16 u16TopField_VS2MVD = 0x200;
1417 HAL_WriteByte((VOP_TF_VS_MVD ), LOWBYTE( u16TopField_VS2MVD ));
1418 HAL_WriteByte((VOP_TF_VS_MVD + 1), HIGHBYTE( u16TopField_VS2MVD ));
1419 HAL_WriteRegBit(VOP_CTRL1, 0, VOP_MVD_VS_MD);
1420 }
1421
1422
1423 /* Clippers sw patch: sbs + handshake mode video not stable*/
1424 if(g_pHalMVOPCtx->b3DLRAltSBSOutput)
1425 {
1426 ptiming->u16VImg_Start0 = 0xfff;
1427 ptiming->u16VImg_Start1 = 0xfff;
1428 }
1429
1430 // + S3, set default IMG_HSTR, IMG_VSTR0, IMG_VSTR1
1431 #ifdef _SUPPORT_IMG_OFFSET_
1432 HAL_WriteByte((VOP_IMG_HSTR ), LOWBYTE( ptiming->u16HImg_Start));
1433 HAL_WriteByte((VOP_IMG_HSTR + 1), HIGHBYTE( ptiming->u16HImg_Start ));
1434 HAL_WriteByte((VOP_IMG_VSTR0 ), LOWBYTE( ptiming->u16VImg_Start0));
1435 HAL_WriteByte((VOP_IMG_VSTR0+ 1), HIGHBYTE( ptiming->u16VImg_Start0 ));
1436 HAL_WriteByte((VOP_IMG_VSTR1 ), LOWBYTE( ptiming->u16VImg_Start1 ));
1437 HAL_WriteByte((VOP_IMG_VSTR1+ 1), HIGHBYTE( ptiming->u16VImg_Start1 ));
1438 #else
1439 HAL_WriteByte((VOP_IMG_HSTR ), LOWBYTE( ptiming->u16HActive_Start ));
1440 HAL_WriteByte((VOP_IMG_HSTR + 1), HIGHBYTE( ptiming->u16HActive_Start ));
1441 HAL_WriteByte((VOP_IMG_VSTR0 ), LOWBYTE( ptiming->u16VBlank0_End ));
1442 HAL_WriteByte((VOP_IMG_VSTR0+ 1), HIGHBYTE( ptiming->u16VBlank0_End ));
1443 HAL_WriteByte((VOP_IMG_VSTR1 ), LOWBYTE( ptiming->u16VBlank1_End ));
1444 HAL_WriteByte((VOP_IMG_VSTR1+ 1), HIGHBYTE( ptiming->u16VBlank1_End ));
1445 #endif
1446 // select mvop output from frame color(black)
1447 HAL_WriteByte((VOP_TST_IMG + 1), 0x10);
1448 HAL_WriteByte((VOP_U_PAT ), 0x80);
1449 HAL_WriteByte((VOP_U_PAT + 1), 0x80);
1450 // set mvop src to test pattern
1451 regval = HAL_ReadByte(VOP_TST_IMG);
1452 HAL_WriteByteMask(VOP_TST_IMG, 0x02, BIT2 | BIT1 | BIT0);
1453 // make changed registers take effect
1454 HAL_MVOP_LoadReg();
1455
1456 HAL_MVOP_SetMIUReqMask(TRUE);
1457 // reset mvop to avoid timing change cause mvop hang-up
1458 HAL_MVOP_Rst();
1459 HAL_MVOP_SetMIUReqMask(FALSE);
1460
1461 // select mvop output from mvd
1462 HAL_WriteByteMask(VOP_TST_IMG, 0x00, BIT2 | BIT1 | BIT0);
1463 HAL_WriteByteMask(VOP_TST_IMG, regval, BIT2 | BIT1 | BIT0);
1464 HAL_WriteRegBit(VOP_CTRL0, ptiming->bHDuplicate, BIT2);// H pixel duplicate
1465
1466 g_pHalMVOPCtx->u16Hsize = ptiming->u16Width;
1467 //for supporting out of spec, line buffer only 2048
1468 if(ptiming->u16Width > 2048)
1469 {
1470 HAL_WriteRegBit(VOP_REG_DUMMY, 0, VOP_420_BW_SAVE);
1471 HAL_WriteRegBit(VOP_REG_BW_SAVE, 0, VOP_420_BW_SAVE_EX);
1472 HAL_MVOP_LoadReg();
1473 }
1474 #if 0
1475 MVOP_DBG(MVOP_PRINTF("\nMVOP SetOutputTiming\n");)
1476 MVOP_DBG(MVOP_PRINTF(" VTot=%u,\t",ptiming->u16V_TotalCount);)
1477 MVOP_DBG(MVOP_PRINTF(" HTot=%u,\t",ptiming->u16H_TotalCount);)
1478 MVOP_DBG(MVOP_PRINTF(" I/P=%u\n",ptiming->bInterlace);)
1479 MVOP_DBG(MVOP_PRINTF(" W=%u,\t",ptiming->u16Width);)
1480 MVOP_DBG(MVOP_PRINTF(" H=%u,\t",ptiming->u16Height);)
1481 MVOP_DBG(MVOP_PRINTF(" FRate=%u,\t",ptiming->u8Framerate);)
1482 MVOP_DBG(MVOP_PRINTF(" HFreq=%u\n",ptiming->u16H_Freq);)
1483 MVOP_DBG(MVOP_PRINTF(" Num=0x%x,\t",ptiming->u16Num);)
1484 MVOP_DBG(MVOP_PRINTF(" Den=0x%x,\t",ptiming->u16Den);)
1485 MVOP_DBG(MVOP_PRINTF(" u16ExpFRate=%u #\n\n", ptiming->u16ExpFrameRate);)
1486 #endif
1487 }
1488
HAL_MVOP_SetDCClk(MS_U8 clkNum,MS_BOOL bEnable)1489 void HAL_MVOP_SetDCClk(MS_U8 clkNum, MS_BOOL bEnable)
1490 {
1491 MS_ASSERT( (clkNum==0) || (clkNum==1) );
1492 if (clkNum==0)
1493 {
1494 HAL_WriteRegBit(REG_CKG_DC0, !bEnable, CKG_DC0_GATED);
1495 }
1496 }
1497
HAL_MVOP_SetDCSRAMClk(MS_U8 clkNum,MS_BOOL bEnable)1498 void HAL_MVOP_SetDCSRAMClk(MS_U8 clkNum, MS_BOOL bEnable)
1499 {
1500 MS_ASSERT( (clkNum==0) || (clkNum==1) );
1501 if (clkNum==0)
1502 {
1503 if(bEnable)
1504 HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x4, CKG_DC0_SRAM);//Dc0 enable & dc0_mfdec_en =0 57[3:0]= 0x4, others 57[3:0]=0x0
1505 else
1506 HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x0, CKG_DC0_SRAM);
1507 }
1508 }
1509
1510
HAL_MVOP_SetSynClk(MVOP_Timing * ptiming)1511 void HAL_MVOP_SetSynClk(MVOP_Timing *ptiming)
1512 {
1513 if (g_pHalMVOPCtx == NULL)
1514 {
1515 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
1516 return;
1517 }
1518
1519 if(g_pHalMVOPCtx->u32MVOPFixClk != 0)
1520 {
1521 HAL_MVOP_SetFrequency(g_pHalMVOPCtx->u32MVOPFixClk);
1522 if(g_pHalMVOPCtx->b3DLRMode)//4k1k mvc
1523 {
1524 //burst and priority
1525 HAL_WriteByte(VOP_DMA1, 0x26);
1526 HAL_WriteByte(VOP_BURST_CTRL0, 0x05);
1527 HAL_WriteByte(VOP_BURST_CTRL1, 0x00);
1528 }
1529 MVOP_DBG(MVOP_PRINTF("[MVOP][DBG] Set Fix clock\n");)
1530 }
1531 else if(g_pHalMVOPCtx->bEnableFreerunMode)
1532 {
1533 MS_U64 u64mpll_clock = MPLL_CLOCK << 27 ;
1534 do_div(u64mpll_clock, ((MS_U32)ptiming->u16H_TotalCount * (MS_U32)ptiming->u16V_TotalCount * (MS_U32)ptiming->u8Framerate));
1535 MS_U32 u32FreerunClk = (MS_U32)u64mpll_clock;
1536 HAL_MVOP_SetFrequency(HALMVOP_FREERUNMODE);
1537 HAL_WriteByte((REG_DC0_FREERUN_CW_L ), LOWBYTE((MS_U16)u32FreerunClk));
1538 HAL_WriteByte((REG_DC0_FREERUN_CW_L+1), HIGHBYTE((MS_U16)u32FreerunClk));
1539 HAL_WriteByte((REG_DC0_FREERUN_CW_H ), LOWBYTE((MS_U16)(u32FreerunClk >> 16)));
1540 HAL_WriteByte((REG_DC0_FREERUN_CW_H+1), HIGHBYTE((MS_U16)(u32FreerunClk >> 16)));
1541 HAL_WriteRegBit(REG_UPDATE_DC0_CW, 1, UPDATE_DC0_FREERUN_CW);
1542 HAL_WriteRegBit(REG_UPDATE_DC0_CW, 0, UPDATE_DC0_FREERUN_CW);
1543 MVOP_DBG(MVOP_PRINTF("[MVOP][DBG] Set Freerun clock\n");)
1544 }
1545 else if (_bEnable60P)
1546 {
1547 HAL_MVOP_SetFrequency(HAL_MVOP_GetMaxFreerunClk());
1548
1549 HAL_WriteRegBit(VOP_REG_FRAME_RST, 0, BIT15); // reg_frame_rst = 0
1550
1551 HAL_WriteRegBit(VOP_CTRL0, DISABLE, VOP_FSYNC_EN); // frame sync disable
1552
1553 if(g_pHalMVOPCtx->b3DLRMode)//4k1k mvc
1554 {
1555 //burst and priority
1556 HAL_WriteByte(VOP_DMA1, 0x26);
1557 HAL_WriteByte(VOP_BURST_CTRL0, 0x05);
1558 HAL_WriteByte(VOP_BURST_CTRL1, 0x00);
1559 }
1560
1561 MVOP_DBG(MVOP_PRINTF("[MVOP][DBG] Set 160MHz clock\n");)
1562 }
1563 else if (_bEnable4k2kClk)
1564 {
1565 HAL_MVOP_SetFrequency(HAL_MVOP_Get4k2kClk());
1566
1567 HAL_WriteRegBit(VOP_REG_FRAME_RST, 0, BIT15); // reg_frame_rst = 0
1568
1569 HAL_WriteRegBit(VOP_CTRL0, DISABLE, VOP_FSYNC_EN); // frame sync disable
1570 // Clippers sync wz xc: 4k2k default 2p mode enable(xc output 50 or 60)
1571 HAL_MVOP_SetEnable4k2k2P(TRUE);
1572 //Change MIU BW Default Value to 0x241C (after Einstein)
1573 //FIFO threshold
1574 HAL_WriteByte(VOP_DMA0, 0x10);
1575 //burst and priority
1576 HAL_WriteByte(VOP_DMA1, 0x26);
1577 HAL_WriteByte(VOP_BURST_CTRL0, 0x05);
1578 HAL_WriteByte(VOP_BURST_CTRL1, 0x00);
1579 MVOP_DBG(MVOP_PRINTF("[MVOP][DBG] Set 4k2k clock\n");)
1580 }
1581 else
1582 {
1583 HAL_MVOP_SetFrequency(HALMVOP_SYNCMODE);
1584 HAL_WriteByte((REG_DC0_NUM ), LOWBYTE( ptiming->u16Num));
1585 HAL_WriteByte((REG_DC0_NUM+1), HIGHBYTE(ptiming->u16Num));
1586 HAL_WriteByte((REG_DC0_DEN ), LOWBYTE( ptiming->u16Den));
1587 HAL_WriteByte((REG_DC0_DEN+1), HIGHBYTE(ptiming->u16Den));
1588 HAL_WriteRegBit(REG_UPDATE_DC0_CW, 1, UPDATE_DC0_SYNC_CW);
1589 HAL_WriteRegBit(REG_UPDATE_DC0_CW, 0, UPDATE_DC0_SYNC_CW);
1590 MVOP_DBG(MVOP_PRINTF("[MVOP][DBG] Set Sync clock\n");)
1591 }
1592 }
1593
1594
HAL_MVOP_SetMonoMode(MS_BOOL bEnable)1595 void HAL_MVOP_SetMonoMode(MS_BOOL bEnable)
1596 {
1597 if(bEnable)
1598 {
1599 HAL_WriteByte(VOP_U_PAT , 0x80);
1600 HAL_WriteByte((VOP_U_PAT+1), 0x80);
1601
1602 HAL_WriteRegBit(VOP_INPUT_SWITCH1, 1, BIT1); // Mono mode enable
1603 }
1604 else
1605 {
1606 HAL_WriteRegBit(VOP_INPUT_SWITCH1, 0, BIT1); //Mono mode disable
1607 }
1608 }
1609
1610 /******************************************************************************/
1611 /// Set MVOP for H264 Hardwire Mode
1612 /******************************************************************************/
HAL_MVOP_SetH264HardwireMode(MS_U16 u16ECOVersion)1613 void HAL_MVOP_SetH264HardwireMode(MS_U16 u16ECOVersion)
1614 {
1615 // Hardwire mode
1616 HAL_WriteByte(VOP_MPG_JPG_SWITCH, 0x00);
1617
1618 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);
1619
1620 //16*32 tile format
1621 HAL_WriteRegBit(VOP_REG_WR, 1, BIT1);
1622
1623 // SVD mode enable
1624 HAL_WriteByteMask(VOP_INPUT_SWITCH1, BIT3, BIT2|BIT3);
1625
1626 // set mvop to 128bit_i128 interface
1627 HAL_WriteByteMask(VOP_MIU_IF, VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
1628
1629 // Only for Monaco: Disable deciding bot by top address + 2
1630 HAL_WriteRegBit(VOP_MIRROR_CFG, 0, VOP_FIELD_FROM_ADDR);
1631
1632 HAL_WriteRegBit(VOP_REG_DUMMY, 1, VOP_32x32_WB); //32x32 from wb
1633
1634 // Write trigger
1635 HAL_MVOP_LoadReg();
1636 }
1637
1638 /******************************************************************************/
1639 /// Set MVOP for RM Hardwire Mode
1640 /******************************************************************************/
HAL_MVOP_SetRMHardwireMode(MS_U16 u16ECOVersion)1641 void HAL_MVOP_SetRMHardwireMode(MS_U16 u16ECOVersion)
1642 {
1643 HAL_MVOP_SetH264HardwireMode(u16ECOVersion);
1644 }
1645
1646 /******************************************************************************/
1647 /// Set MVOP for JPEG Hardwire Mode
1648 /******************************************************************************/
HAL_MVOP_SetJpegHardwireMode(void)1649 void HAL_MVOP_SetJpegHardwireMode(void)
1650 {
1651 MS_U8 regval = 0x00;
1652
1653 regval |= 0x80; // packmode
1654 regval |= 0x20; // Dram Rd Contd
1655 HAL_WriteByte(VOP_MPG_JPG_SWITCH, regval);
1656 g_pHalMVOPCtx->bIs422 = 1;
1657 HAL_WriteRegBit(VOP_REG_DUMMY, 0, VOP_420_BW_SAVE);
1658 HAL_WriteRegBit(VOP_REG_BW_SAVE, 0, VOP_420_BW_SAVE_EX);
1659
1660 HAL_WriteByteMask(VOP_INFO_FROM_CODEC_H, 0x00, VOP_INFO_FROM_CODEC_MIU_BUF0_SEL|VOP_INFO_FROM_CODEC_MIU_BUF1_SEL);
1661
1662 // Write trigger
1663 HAL_MVOP_LoadReg();
1664 }
1665
1666 /******************************************************************************/
1667 /// Set MVOP for EVD Hardwire Mode
1668 /******************************************************************************/
HAL_MVOP_SetEVDHardwireMode(MS_U16 u16ECOVersion)1669 void HAL_MVOP_SetEVDHardwireMode(MS_U16 u16ECOVersion)
1670 {
1671 // Hardwire mode
1672 HAL_WriteByte(VOP_MPG_JPG_SWITCH, 0x00);
1673
1674 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);
1675
1676 //16*32 tile format
1677 HAL_WriteRegBit(VOP_REG_WR, 1, BIT1);
1678
1679 // SVD mode enable
1680 // EVD use HVD interface
1681 //HAL_WriteByteMask(VOP_INPUT_SWITCH1, BIT3, BIT2|BIT3);
1682
1683 // EVD mode enable
1684 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 1, EVD_ENABLE);
1685
1686 // set mvop to 128bit_i128 interface
1687 HAL_WriteByteMask(VOP_MIU_IF, VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
1688
1689 // set evd flag for interlace mode setting
1690 g_pHalMVOPCtx->bIsH265 = 1;
1691
1692 // 10 bits from wb
1693 HAL_WriteRegBit(VOP_INFO_FROM_CODEC_H, 1, VOP_INFO_FROM_CODEC_10BIT);
1694
1695 // Write trigger
1696 HAL_MVOP_LoadReg();
1697 }
1698
1699 /******************************************************************************/
1700 /// Set MVOP for VP9 Hardwire Mode
1701 /// vp9 hw change in Manhathan: tile mode 16x32
1702 /******************************************************************************/
HAL_MVOP_SetVP9HardwireMode(MS_U16 u16ECOVersion)1703 void HAL_MVOP_SetVP9HardwireMode(MS_U16 u16ECOVersion)
1704 {
1705 HAL_MVOP_SetEVDHardwireMode(u16ECOVersion);
1706 }
1707
1708 /******************************************************************************/
1709 /// Set MVOP for EVD MCU Mode
1710 /******************************************************************************/
HAL_MVOP_SetEVDFeature(MVOP_DevID eID,MVOP_EVDFeature * stEVDInput)1711 void HAL_MVOP_SetEVDFeature(MVOP_DevID eID, MVOP_EVDFeature* stEVDInput)
1712 {
1713 switch(eID)
1714 {
1715 case E_MVOP_DEV_0:
1716
1717 HAL_WriteRegBit(VOP_INPUT_SWITCH0, stEVDInput->bEnableEVD, EVD_ENABLE);// 32x32 enable
1718
1719 switch(stEVDInput->eEVDBit[Y_INFO])
1720 {
1721 case E_MVOP_EVD_8BIT:
1722 HAL_WriteRegBit(VOP_EVD_10B_EN, 0, VOP_EVD_10B_Y_EN);
1723 break;
1724 case E_MVOP_EVD_10BIT:
1725 HAL_WriteRegBit(VOP_EVD_10B_EN, 1, VOP_EVD_10B_Y_EN);
1726 break;
1727 default:
1728 break;
1729 }
1730
1731 switch(stEVDInput->eEVDBit[UV_INFO])
1732 {
1733 case E_MVOP_EVD_8BIT:
1734 HAL_WriteRegBit(VOP_EVD_10B_EN, 0, VOP_EVD_10B_UV_EN);
1735 break;
1736 case E_MVOP_EVD_10BIT:
1737 HAL_WriteRegBit(VOP_EVD_10B_EN, 1, VOP_EVD_10B_UV_EN);
1738 break;
1739 default:
1740 break;
1741 }
1742
1743 //LSB BW Discard MASK
1744 if(stEVDInput->eEVDBit[Y_INFO] || stEVDInput->eEVDBit[UV_INFO])
1745 {
1746 HAL_WriteByteMask(VOP_REG_MASK, 0, VOP_LSB_REQ_MASK);
1747 HAL_WriteRegBit(VOP_UV_SHIFT, 0, VOP_GCLK_MIU_ON);
1748 MVOP_DBG(MVOP_PRINTF("[Debug] 10 bits display\n"););
1749 }
1750 else
1751 {
1752 HAL_WriteByteMask(VOP_REG_MASK, BIT1, VOP_LSB_REQ_MASK);
1753 }
1754
1755 // Write trigger
1756 HAL_MVOP_LoadReg();
1757 break;
1758 case E_MVOP_DEV_1:
1759 #if MVOP_SUPPORT_SUB
1760
1761 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), stEVDInput->bEnableEVD, EVD_ENABLE);// 32x32 enable
1762
1763 switch(stEVDInput->eEVDBit[Y_INFO])
1764 {
1765 case E_MVOP_EVD_8BIT:
1766 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 0, VOP_EVD_10B_Y_EN);
1767 break;
1768 case E_MVOP_EVD_10BIT:
1769 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 1, VOP_EVD_10B_Y_EN);
1770 break;
1771 default:
1772 break;
1773 }
1774
1775 switch(stEVDInput->eEVDBit[UV_INFO])
1776 {
1777 case E_MVOP_EVD_8BIT:
1778 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 0, VOP_EVD_10B_UV_EN);
1779 break;
1780 case E_MVOP_EVD_10BIT:
1781 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 1, VOP_EVD_10B_UV_EN);
1782 break;
1783 default:
1784 break;
1785 }
1786
1787 //LSB BW Discard MASK
1788 if(stEVDInput->eEVDBit[Y_INFO] || stEVDInput->eEVDBit[UV_INFO])
1789 {
1790 HAL_WriteByteMask(SUB_REG(VOP_REG_MASK), 0, VOP_LSB_REQ_MASK);
1791 HAL_WriteRegBit(SUB_REG(VOP_UV_SHIFT), 0, VOP_GCLK_MIU_ON);
1792 MVOP_DBG(MVOP_PRINTF("[Debug] 10 bits display\n"););
1793 }
1794 else
1795 {
1796 HAL_WriteByteMask(SUB_REG(VOP_REG_MASK), BIT1, VOP_LSB_REQ_MASK);
1797 }
1798 // Write trigger
1799 HAL_MVOP_SubLoadReg();
1800 #endif
1801 break;
1802 default:
1803 break;
1804 }
1805
1806 }
1807
1808
1809 ///Enable 3D L/R dual buffer mode
HAL_MVOP_Enable3DLR(MS_BOOL bEnable)1810 MS_BOOL HAL_MVOP_Enable3DLR(MS_BOOL bEnable)
1811 {
1812 if (g_pHalMVOPCtx == NULL)
1813 {
1814 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
1815 return FALSE;
1816 }
1817 HAL_WriteRegBit(VOP_MULTI_WIN_CFG0, bEnable, VOP_LR_BUF_MODE);
1818 g_pHalMVOPCtx->b3DLRMode = bEnable;
1819 if(bEnable)
1820 {
1821 HAL_WriteRegBit(VOP_REG_BW_SAVE, 0, VOP_420_BW_SAVE_EX);
1822 }
1823 return TRUE;
1824 }
1825
1826 ///Get if 3D L/R mode is enabled
HAL_MVOP_Get3DLRMode(void)1827 MS_BOOL HAL_MVOP_Get3DLRMode(void)
1828 {
1829 if (g_pHalMVOPCtx == NULL)
1830 {
1831 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
1832 return FALSE;
1833 }
1834 return g_pHalMVOPCtx->b3DLRMode;
1835 }
1836
HAL_MVOP_GetTimingInfoFromRegisters(MVOP_TimingInfo_FromRegisters * pMvopTimingInfo)1837 MS_BOOL HAL_MVOP_GetTimingInfoFromRegisters(MVOP_TimingInfo_FromRegisters *pMvopTimingInfo)
1838 {
1839 if(NULL == pMvopTimingInfo)
1840 {
1841 MVOP_PRINTF("HAL_MVOP_GetTimingInfoFromRegisters():pMvopTimingInfo is NULL\n");
1842 return FALSE;
1843 }
1844 if(HAL_MVOP_GetEnableState() == FALSE)
1845 {
1846 MVOP_PRINTF("MVOP is not enabled!\n");
1847 pMvopTimingInfo->bEnabled = FALSE;
1848 return FALSE;
1849 }
1850 pMvopTimingInfo->bEnabled = TRUE;
1851 pMvopTimingInfo->u16H_TotalCount = (HAL_ReadByte((VOP_FRAME_HCOUNT + 1))<< 8) | (HAL_ReadByte((VOP_FRAME_HCOUNT)));
1852 pMvopTimingInfo->u16V_TotalCount = (HAL_ReadByte((VOP_FRAME_VCOUNT + 1))<< 8) | (HAL_ReadByte((VOP_FRAME_VCOUNT)));
1853 pMvopTimingInfo->u16VBlank0_Start = (HAL_ReadByte((VOP_VB0_STR + 1))<< 8) | (HAL_ReadByte((VOP_VB0_STR)));
1854 pMvopTimingInfo->u16VBlank0_End = (HAL_ReadByte((VOP_VB0_END + 1))<< 8) | (HAL_ReadByte((VOP_VB0_END)));
1855 pMvopTimingInfo->u16VBlank1_Start = (HAL_ReadByte((VOP_VB1_STR + 1))<< 8) | (HAL_ReadByte((VOP_VB1_STR)));
1856 pMvopTimingInfo->u16VBlank1_End = (HAL_ReadByte((VOP_VB1_END + 1))<< 8) | (HAL_ReadByte((VOP_VB1_END)));
1857 pMvopTimingInfo->u16TopField_Start = (HAL_ReadByte((VOP_TF_STR + 1))<< 8) | (HAL_ReadByte((VOP_TF_STR)));
1858 pMvopTimingInfo->u16BottomField_Start = (HAL_ReadByte((VOP_BF_STR + 1))<< 8) | (HAL_ReadByte((VOP_BF_STR)));
1859 pMvopTimingInfo->u16HActive_Start = (HAL_ReadByte((VOP_HACT_STR + 1))<< 8) | (HAL_ReadByte((VOP_HACT_STR)));
1860 pMvopTimingInfo->u16TopField_VS = (HAL_ReadByte((VOP_TF_VS + 1))<< 8) | (HAL_ReadByte((VOP_TF_VS)));
1861 pMvopTimingInfo->u16BottomField_VS = (HAL_ReadByte((VOP_BF_VS + 1))<< 8) | (HAL_ReadByte((VOP_BF_VS)));
1862 pMvopTimingInfo->bInterlace = (HAL_ReadRegBit(VOP_CTRL0, BIT7) == BIT7);
1863 return TRUE;
1864 }
1865
HAL_MVOP_SetYUVBaseAdd(MS_PHY u32YOffset,MS_PHY u32UVOffset,MS_BOOL bProgressive,MS_BOOL b422pack)1866 void HAL_MVOP_SetYUVBaseAdd(MS_PHY u32YOffset, MS_PHY u32UVOffset, MS_BOOL bProgressive, MS_BOOL b422pack)
1867 {
1868 MS_PHY u64tmp = 0;
1869
1870 if (g_pHalMVOPCtx == NULL)
1871 {
1872 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
1873 return;
1874 }
1875 // Y offset
1876 u64tmp = u32YOffset >> 3;
1877 if ( !bProgressive )
1878 { //Refine Y offset for interlace repeat bottom field
1879 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
1880 {
1881 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
1882 u64tmp += 2;
1883 }
1884 else
1885 {
1886 MVOP_DBG("%d eRepeatField(%x) is TOP or NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
1887 }
1888 }
1889 HAL_WriteByte(VOP_JPG_YSTR0_L, u64tmp & 0xff);
1890 HAL_WriteByte((VOP_JPG_YSTR0_L+1), (u64tmp >> 8) & 0xff);
1891 HAL_WriteByte((VOP_JPG_YSTR0_L+2), (u64tmp >> 16) & 0xff);
1892 HAL_WriteByte((VOP_JPG_YSTR0_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
1893
1894 if (!bProgressive )
1895 { //Y offset of bottom field if interlace
1896 HAL_WriteByte(VOP_JPG_YSTR1_L, u64tmp & 0xff);
1897 HAL_WriteByte((VOP_JPG_YSTR1_L+1), (u64tmp >> 8) & 0xff);
1898 HAL_WriteByte((VOP_JPG_YSTR1_L+2), (u64tmp >> 16) & 0xff);
1899 HAL_WriteByte((VOP_JPG_YSTR1_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
1900 }
1901
1902 if (b422pack)
1903 {
1904 u32UVOffset = u32YOffset + 16; //add 16 for 128bit; add 8 for 64bit
1905 }
1906 // UV offset
1907 u64tmp = u32UVOffset >> 3;
1908 if( !bProgressive )
1909 { //Refine UV offset for interlace repeat bottom field
1910 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
1911 {
1912 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
1913 u64tmp += 2;
1914 }
1915 else
1916 {
1917 MVOP_DBG("%d eRepeatField(%x) is TOP/NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
1918 }
1919 }
1920 HAL_WriteByte(VOP_JPG_UVSTR0_L, u64tmp & 0xff);
1921 HAL_WriteByte((VOP_JPG_UVSTR0_L+1), (u64tmp >> 8) & 0xff);
1922 HAL_WriteByte((VOP_JPG_UVSTR0_L+2), (u64tmp >> 16) & 0xff);
1923 HAL_WriteByte((VOP_JPG_UVSTR0_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
1924
1925 if( !bProgressive )
1926 { //UV offset of bottom field if interlace
1927 HAL_WriteByte(VOP_JPG_UVSTR1_L, u64tmp & 0xff);
1928 HAL_WriteByte((VOP_JPG_UVSTR1_L+1), (u64tmp >> 8) & 0xff);
1929 HAL_WriteByte((VOP_JPG_UVSTR1_L+2), (u64tmp >> 16) & 0xff);
1930 HAL_WriteByte((VOP_JPG_UVSTR1_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
1931 }
1932
1933 return;
1934 }
1935
HAL_MVOP_SetYUVBaseAddMultiView(MVOP_BaseAddInput * stBaseAddInfo)1936 MS_BOOL HAL_MVOP_SetYUVBaseAddMultiView(MVOP_BaseAddInput *stBaseAddInfo)
1937 {
1938 MS_PHY u64tmpY = 0;
1939 MS_PHY u64tmpUV = 0;
1940
1941 if (stBaseAddInfo == NULL)
1942 {
1943 MVOP_DBG(MVOP_PRINTF("%s stBaseAddInfo is NULL pointer\n", __FUNCTION__);)
1944 return FALSE;
1945 }
1946 // Y offset
1947 u64tmpY = (stBaseAddInfo->u32YOffset) >> 3;
1948 // UV offset
1949 u64tmpUV = (stBaseAddInfo->u32UVOffset) >> 3;
1950
1951 switch(stBaseAddInfo->eView)
1952 {
1953 case E_MVOP_MAIN_VIEW:
1954 // Y offset
1955 HAL_WriteByte(VOP_JPG_YSTR0_L, u64tmpY & 0xff);
1956 HAL_WriteByte((VOP_JPG_YSTR0_L+1), (u64tmpY >> 8) & 0xff);
1957 HAL_WriteByte((VOP_JPG_YSTR0_L+2), (u64tmpY >> 16) & 0xff);
1958 HAL_WriteByte((VOP_JPG_YSTR0_L+3), (u64tmpY >> 24) & VOP_YUV_STR_HIBITS);
1959
1960 // UV offset
1961 HAL_WriteByte(VOP_JPG_UVSTR0_L, u64tmpUV & 0xff);
1962 HAL_WriteByte((VOP_JPG_UVSTR0_L+1), (u64tmpUV >> 8) & 0xff);
1963 HAL_WriteByte((VOP_JPG_UVSTR0_L+2), (u64tmpUV >> 16) & 0xff);
1964 HAL_WriteByte((VOP_JPG_UVSTR0_L+3), (u64tmpUV >> 24) & VOP_YUV_STR_HIBITS);
1965 break;
1966 case E_MVOP_2ND_VIEW:
1967 // Y offset
1968 HAL_WriteByte(VOP_JPG_YSTR1_L, u64tmpY & 0xff);
1969 HAL_WriteByte((VOP_JPG_YSTR1_L+1), (u64tmpY >> 8) & 0xff);
1970 HAL_WriteByte((VOP_JPG_YSTR1_L+2), (u64tmpY >> 16) & 0xff);
1971 HAL_WriteByte((VOP_JPG_YSTR1_L+3), (u64tmpY >> 24) & VOP_YUV_STR_HIBITS);
1972
1973 //UV offset
1974 HAL_WriteByte(VOP_JPG_UVSTR1_L, u64tmpUV & 0xff);
1975 HAL_WriteByte((VOP_JPG_UVSTR1_L+1), (u64tmpUV >> 8) & 0xff);
1976 HAL_WriteByte((VOP_JPG_UVSTR1_L+2), (u64tmpUV >> 16) & 0xff);
1977 HAL_WriteByte((VOP_JPG_UVSTR1_L+3), (u64tmpUV >> 24) & VOP_YUV_STR_HIBITS);
1978 break;
1979 default:
1980 break;
1981 }
1982 return TRUE;
1983 }
1984
HAL_MVOP_GetYBaseAdd(void)1985 MS_PHY HAL_MVOP_GetYBaseAdd(void)
1986 {
1987 MS_PHY u64YOffset = 0;
1988 u64YOffset = HAL_ReadByte(VOP_JPG_YSTR0_L)&0xff;
1989 u64YOffset |=((HAL_ReadByte((VOP_JPG_YSTR0_L+1))<<8)&0xff00);
1990 u64YOffset |=((HAL_ReadByte((VOP_JPG_YSTR0_L+2))<<16)&0xff0000);
1991 u64YOffset |= ((HAL_ReadByte((VOP_JPG_YSTR0_L+3)) & VOP_YUV_STR_HIBITS) <<24);
1992 return u64YOffset;
1993 }
1994
HAL_MVOP_GetUVBaseAdd(void)1995 MS_PHY HAL_MVOP_GetUVBaseAdd(void)
1996 {
1997 MS_PHY u64UVOffset = 0;
1998 u64UVOffset = HAL_ReadByte(VOP_JPG_UVSTR0_L)&0xff;
1999 u64UVOffset |=((HAL_ReadByte((VOP_JPG_UVSTR0_L+1))<<8)&0xff00);
2000 u64UVOffset |=((HAL_ReadByte((VOP_JPG_UVSTR0_L+2))<<16)&0xff0000);
2001 u64UVOffset |= ((HAL_ReadByte((VOP_JPG_UVSTR0_L+3)) & VOP_YUV_STR_HIBITS) <<24);
2002 return u64UVOffset;
2003 }
2004
HAL_MVOP_GetYBaseAddMultiView(MVOP_3DView eView)2005 MS_PHY HAL_MVOP_GetYBaseAddMultiView(MVOP_3DView eView)
2006 {
2007 MS_PHY u64YOffset = 0;
2008 switch(eView)
2009 {
2010 case E_MVOP_MAIN_VIEW:
2011 u64YOffset = HAL_ReadByte(VOP_JPG_YSTR0_L)&0xff;
2012 u64YOffset |= ((HAL_ReadByte((VOP_JPG_YSTR0_L+1))<<8)&0xff00);
2013 u64YOffset |= ((HAL_ReadByte((VOP_JPG_YSTR0_L+2))<<16)&0xff0000);
2014 u64YOffset |= ((HAL_ReadByte((VOP_JPG_YSTR0_L+3)) & VOP_YUV_STR_HIBITS) <<24);
2015 break;
2016 case E_MVOP_2ND_VIEW:
2017 u64YOffset = HAL_ReadByte(VOP_JPG_YSTR1_L)&0xff;
2018 u64YOffset |= ((HAL_ReadByte((VOP_JPG_YSTR1_L+1))<<8)&0xff00);
2019 u64YOffset |= ((HAL_ReadByte((VOP_JPG_YSTR1_L+2))<<16)&0xff0000);
2020 u64YOffset |= ((HAL_ReadByte((VOP_JPG_YSTR1_L+3))<<24)&0x7000000);
2021 break;
2022 default:
2023 u64YOffset = 0;
2024 break;
2025 }
2026 return u64YOffset;
2027 }
2028
HAL_MVOP_GetUVBaseAddMultiView(MVOP_3DView eView)2029 MS_PHY HAL_MVOP_GetUVBaseAddMultiView(MVOP_3DView eView)
2030 {
2031 MS_PHY u64UVOffset = 0;
2032 switch(eView)
2033 {
2034 case E_MVOP_MAIN_VIEW:
2035 u64UVOffset = HAL_ReadByte(VOP_JPG_UVSTR0_L)&0xff;
2036 u64UVOffset |= ((HAL_ReadByte((VOP_JPG_UVSTR0_L+1))<<8)&0xff00);
2037 u64UVOffset |= ((HAL_ReadByte((VOP_JPG_UVSTR0_L+2))<<16)&0xff0000);
2038 u64UVOffset |= ((HAL_ReadByte((VOP_JPG_UVSTR0_L+3)) & VOP_YUV_STR_HIBITS) <<24);
2039 break;
2040 case E_MVOP_2ND_VIEW:
2041 u64UVOffset = HAL_ReadByte(VOP_JPG_UVSTR1_L)&0xff;
2042 u64UVOffset |= ((HAL_ReadByte((VOP_JPG_UVSTR1_L+1))<<8)&0xff00);
2043 u64UVOffset |= ((HAL_ReadByte((VOP_JPG_UVSTR1_L+2))<<16)&0xff0000);
2044 u64UVOffset |= ((HAL_ReadByte((VOP_JPG_UVSTR1_L+3))<<24)&0x7000000);
2045 break;
2046 default:
2047 u64UVOffset = 0;
2048 break;
2049 }
2050 return u64UVOffset;
2051 }
2052
HAL_MVOP_Set3DLRAltOutput_VHalfScaling(MS_BOOL bEnable)2053 MS_BOOL HAL_MVOP_Set3DLRAltOutput_VHalfScaling(MS_BOOL bEnable)
2054 {
2055 MS_BOOL bEnDualBuff = bEnable ? ENABLE : DISABLE; //enable dual buffer
2056 MS_BOOL bEnSWDualBuff = bEnable ? DISABLE : ENABLE; //buffer controlled by HK instead of FW
2057 MS_BOOL bEnMirrMaskBase = bEnable ? DISABLE : ENABLE; //do not mask LSB
2058 MS_BOOL bEnHwFldBase = bEnable ? DISABLE : ENABLE; //hardware calculate field jump base address
2059
2060 if (g_pHalMVOPCtx == NULL)
2061 {
2062 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
2063 return FALSE;
2064 }
2065 //Set 0x27[2] = 1 (enable SW dual buffer mode)
2066 HAL_WriteRegBit(VOP_REG_WR, bEnDualBuff, VOP_BUF_DUAL);
2067
2068 //Set 0x38[8] = 0 (use SW dual buffer mode)
2069 HAL_WriteRegBit(VOP_INFO_FROM_CODEC_H, bEnSWDualBuff, VOP_INFO_FROM_CODEC_DUAL_BUFF);
2070
2071 //Set 0x3b[7] = 0 (use MVD/HVD firmware send base)
2072 HAL_WriteRegBit(VOP_MIRROR_CFG, bEnMirrMaskBase, VOP_MASK_BASE_LSB);
2073
2074 //Set 0x3b[5] = 0 (hardware calculate field jump base address)
2075 HAL_WriteRegBit(VOP_MIRROR_CFG, bEnHwFldBase, VOP_HW_FLD_BASE);
2076
2077 g_pHalMVOPCtx->b3DLRAltOutput = bEnable;
2078 return TRUE;
2079 }
2080
HAL_MVOP_Set3DLRAltOutput(MS_BOOL bEnable)2081 MS_BOOL HAL_MVOP_Set3DLRAltOutput(MS_BOOL bEnable)
2082 {
2083 //Set 0x3C[2] = 1 (enable 3D L/R dual buffer line alternative output)
2084 //it works when 0x3C[0] = 1
2085 HAL_WriteRegBit(VOP_MULTI_WIN_CFG0, bEnable, VOP_LR_LA_OUT);
2086 // bw saving not support: LA/SBS
2087 HAL_WriteRegBit(VOP_REG_DUMMY, 0, VOP_420_BW_SAVE);
2088 HAL_WriteRegBit(VOP_REG_BW_SAVE, 0, VOP_420_BW_SAVE_EX);
2089 HAL_MVOP_LoadReg();
2090
2091 g_pHalMVOPCtx->b3DLRAltOutput = bEnable;
2092 return TRUE;
2093 }
2094
HAL_MVOP_Set3DLRAltSBSOutput(MS_BOOL bEnable)2095 MS_BOOL HAL_MVOP_Set3DLRAltSBSOutput(MS_BOOL bEnable)
2096 {
2097 //it works when 0x3C[0] = 1 and 0x3C[2] = 1
2098 //Set 0x3C[3] = 1 (3D L/R line alternative read, side-by-side output)
2099 HAL_WriteRegBit(VOP_MULTI_WIN_CFG0, bEnable, VOP_LR_LA2SBS_OUT);
2100 g_pHalMVOPCtx->b3DLRAltSBSOutput = bEnable;
2101 return TRUE;
2102 }
2103
HAL_MVOP_Get3DLRAltOutput(void)2104 MS_BOOL HAL_MVOP_Get3DLRAltOutput(void)
2105 {
2106 if (g_pHalMVOPCtx == NULL)
2107 {
2108 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
2109 return FALSE;
2110 }
2111 return g_pHalMVOPCtx->b3DLRAltOutput;
2112 }
2113
HAL_MVOP_Get3DLRAltSBSOutput(void)2114 MS_BOOL HAL_MVOP_Get3DLRAltSBSOutput(void)
2115 {
2116 return g_pHalMVOPCtx->b3DLRAltSBSOutput;
2117 }
2118
HAL_MVOP_GetOutput3DType(void)2119 EN_MVOP_Output_3D_TYPE HAL_MVOP_GetOutput3DType(void)
2120 {
2121 EN_MVOP_Output_3D_TYPE en3DType = E_MVOP_OUTPUT_3D_NONE;
2122 if(g_pHalMVOPCtx->b3DLRMode)
2123 {
2124 if(g_pHalMVOPCtx->b3DLRAltSBSOutput)
2125 {
2126 en3DType = E_MVOP_OUTPUT_3D_SBS;
2127 }
2128 else
2129 {
2130 en3DType = E_MVOP_OUTPUT_3D_TB;
2131 }
2132 }
2133 else if(g_pHalMVOPCtx->b3DLRAltOutput)
2134 {
2135 en3DType = E_MVOP_OUTPUT_3D_LA;
2136 }
2137 return en3DType;
2138 }
2139
HAL_MVOP_Set3DLR2ndCfg(MS_BOOL bEnable)2140 MS_BOOL HAL_MVOP_Set3DLR2ndCfg(MS_BOOL bEnable)
2141 {
2142 //Set 0x3c[7] as 1 to enable
2143 HAL_WriteRegBit(VOP_MULTI_WIN_CFG0, bEnable, VOP_LR_DIFF_SIZE);
2144 return TRUE;
2145 }
2146
HAL_MVOP_Get3DLR2ndCfg(void)2147 MS_BOOL HAL_MVOP_Get3DLR2ndCfg(void)
2148 {
2149 MS_BOOL bEnable = FALSE;
2150 if (VOP_LR_DIFF_SIZE == (VOP_LR_DIFF_SIZE & HAL_ReadRegBit(VOP_MULTI_WIN_CFG0, VOP_LR_DIFF_SIZE)))
2151 {
2152 bEnable = TRUE;
2153 }
2154 return bEnable;
2155 }
2156
HAL_MVOP_GetMirrorMode(MVOP_DevID eID)2157 MVOP_DrvMirror HAL_MVOP_GetMirrorMode(MVOP_DevID eID)
2158 {
2159 MVOP_DrvMirror enMirror = E_VOPMIRROR_NONE;
2160 if (g_pHalMVOPCtx == NULL)
2161 {
2162 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
2163 return FALSE;
2164 }
2165 switch(eID)
2166 {
2167 case E_MVOP_DEV_0:
2168 if(g_pHalMVOPCtx->bMirrorModeVer && g_pHalMVOPCtx->bMirrorModeHor)
2169 {
2170 enMirror = E_VOPMIRROR_HVBOTH;
2171 }
2172 else if(g_pHalMVOPCtx->bMirrorModeHor)
2173 {
2174 enMirror = E_VOPMIRROR_HORIZONTALL;
2175 }
2176 else if(g_pHalMVOPCtx->bMirrorModeVer)
2177 {
2178 enMirror = E_VOPMIRROR_VERTICAL;
2179 }
2180 break;
2181 case E_MVOP_DEV_1:
2182 #if MVOP_SUPPORT_SUB
2183 if(g_pHalMVOPCtx->bSubMirrorModeVer &&g_pHalMVOPCtx-> bSubMirrorModeHor)
2184 {
2185 enMirror = E_VOPMIRROR_HVBOTH;
2186 }
2187 else if(g_pHalMVOPCtx->bSubMirrorModeHor)
2188 {
2189 enMirror = E_VOPMIRROR_HORIZONTALL;
2190 }
2191 else if(g_pHalMVOPCtx->bSubMirrorModeVer)
2192 {
2193 enMirror = E_VOPMIRROR_VERTICAL;
2194 }
2195 #endif
2196 break;
2197 default:
2198 break;
2199 }
2200 return enMirror;
2201 }
2202
HAL_MVOP_SetVerDup(MS_BOOL bEnable)2203 MS_BOOL HAL_MVOP_SetVerDup(MS_BOOL bEnable)
2204 {
2205 HAL_WriteRegBit(VOP_CTRL0, bEnable, BIT3);// V line duplicate
2206 return TRUE;
2207 }
2208
HAL_MVOP_GetVerDup(void)2209 MS_BOOL HAL_MVOP_GetVerDup(void)
2210 {
2211 return (HAL_ReadRegBit(VOP_CTRL0, BIT3) == BIT3);
2212 }
2213
HAL_MVOP_SetVerx4Dup(MS_BOOL bEnable)2214 MS_BOOL HAL_MVOP_SetVerx4Dup(MS_BOOL bEnable)
2215 {
2216 HAL_WriteRegBit(VOP_CTRL0, bEnable, BIT3);// x4 duplicate should raise V line duplicate first
2217 HAL_WriteRegBit(VOP_RGB_FMT, bEnable, BIT3);// V line x4 duplicate
2218 return TRUE;
2219 }
2220
HAL_MVOP_SetHorx4Dup(MS_BOOL bEnable)2221 MS_BOOL HAL_MVOP_SetHorx4Dup(MS_BOOL bEnable)
2222 {
2223 HAL_WriteRegBit(VOP_CTRL0, bEnable, BIT2);// x4 duplicate should raise H pixel duplicate first
2224 HAL_WriteRegBit(VOP_RGB_FMT, bEnable, BIT2);// H line x4 duplicate
2225 return TRUE;
2226 }
2227
HAL_MVOP_GetVerx4Dup(void)2228 MS_BOOL HAL_MVOP_GetVerx4Dup(void)
2229 {
2230 return ((HAL_ReadRegBit(VOP_RGB_FMT, BIT3) & HAL_ReadRegBit(VOP_CTRL0, BIT3)) == BIT3);
2231 }
2232
HAL_MVOP_GetHorx4Dup(void)2233 MS_BOOL HAL_MVOP_GetHorx4Dup(void)
2234 {
2235 return ((HAL_ReadRegBit(VOP_RGB_FMT, BIT2) & HAL_ReadRegBit(VOP_CTRL0, BIT2)) == BIT2);
2236 }
2237
HAL_MVOP_GetTopVStart(MVOP_DevID eID)2238 MS_U16 HAL_MVOP_GetTopVStart(MVOP_DevID eID)
2239 {
2240 MS_U16 u16TopVStart = 0;
2241 switch(eID)
2242 {
2243 case E_MVOP_DEV_0:
2244 u16TopVStart = HAL_Read2Byte(VOP_IMG_VSTR0)&0x1fff;
2245 break;
2246 case E_MVOP_DEV_1:
2247 #if MVOP_SUPPORT_SUB
2248 u16TopVStart = HAL_Read2Byte(SUB_REG(VOP_IMG_VSTR0))&0x1fff;
2249 #endif
2250 break;
2251 default:
2252 break;
2253 }
2254 return u16TopVStart;
2255 }
2256
HAL_MVOP_GetBottomVStart(MVOP_DevID eID)2257 MS_U16 HAL_MVOP_GetBottomVStart(MVOP_DevID eID)
2258 {
2259 MS_U16 u16BotVStart = 0;
2260 switch(eID)
2261 {
2262 case E_MVOP_DEV_0:
2263 u16BotVStart = HAL_Read2Byte(VOP_IMG_VSTR1)&0x1fff;
2264 break;
2265 case E_MVOP_DEV_1:
2266 #if MVOP_SUPPORT_SUB
2267 u16BotVStart = HAL_Read2Byte(SUB_REG(VOP_IMG_VSTR1))&0x1fff;
2268 #endif
2269 break;
2270 default:
2271 break;
2272 }
2273 return u16BotVStart;
2274 }
2275
HAL_MVOP_GetVCount(MVOP_DevID eID)2276 MS_U16 HAL_MVOP_GetVCount(MVOP_DevID eID)
2277 {
2278 MS_U16 u16VCount = 0;
2279 switch(eID)
2280 {
2281 case E_MVOP_DEV_0:
2282 u16VCount = HAL_Read2Byte(VOP_DEBUG_2A)&0x1fff;
2283 break;
2284 case E_MVOP_DEV_1:
2285 #if MVOP_SUPPORT_SUB
2286 u16VCount = HAL_Read2Byte(SUB_REG(VOP_DEBUG_2A))&0x1fff;
2287 #endif
2288 break;
2289 default:
2290 break;
2291 }
2292 return u16VCount;
2293 }
2294
HAL_MVOP_SetVC1RangeMap(MVOP_DevID eID,MVOP_VC1RangeMapInfo * stVC1RangeMapInfo)2295 MS_BOOL HAL_MVOP_SetVC1RangeMap(MVOP_DevID eID, MVOP_VC1RangeMapInfo *stVC1RangeMapInfo)
2296 {
2297 MS_U32 u8Luma = 0;
2298 MS_U32 u8Chroma = 0;
2299
2300 if (stVC1RangeMapInfo == NULL)
2301 {
2302 MVOP_DBG(MVOP_PRINTF("%s stBaseAddInfo is NULL pointer\n", __FUNCTION__);)
2303 return FALSE;
2304 }
2305
2306 // Luma value
2307 u8Luma = stVC1RangeMapInfo->u8LumaValue;
2308 // Chroma value
2309 u8Chroma = stVC1RangeMapInfo->u8ChromaValue;
2310
2311 switch(eID)
2312 {
2313 case E_MVOP_DEV_0:
2314 //set VC1 Luma value
2315 if(stVC1RangeMapInfo->bIsEnableLuma)
2316 {
2317 HAL_WriteRegBit(VOP_RAMAP_LUMA, 1, BIT7);
2318 HAL_WriteByteMask(VOP_RAMAP_LUMA, u8Luma, VOP_RAMAP_LUMA_VAL);
2319 }
2320 else //disable
2321 {
2322 HAL_WriteRegBit(VOP_RAMAP_LUMA, 0, BIT7);
2323 }
2324
2325 //set VC1 Chroma value
2326 if(stVC1RangeMapInfo->bIsEnableChroma)
2327 {
2328 HAL_WriteRegBit(VOP_RAMAP_CHROMA, 1, BIT7);
2329 HAL_WriteByteMask(VOP_RAMAP_CHROMA, u8Chroma, VOP_RAMAP_CHROMA_VAL);
2330 }
2331 else
2332 {
2333 HAL_WriteRegBit(VOP_RAMAP_CHROMA, 0, BIT7);
2334 }
2335 break;
2336 case E_MVOP_DEV_1:
2337 #if MVOP_SUPPORT_SUB
2338 //set VC1 Luma value
2339 if(stVC1RangeMapInfo->bIsEnableLuma)
2340 {
2341 HAL_WriteRegBit(SUB_REG(VOP_RAMAP_LUMA), 1, BIT7);
2342 HAL_WriteByteMask(SUB_REG(VOP_RAMAP_LUMA), u8Luma, VOP_RAMAP_LUMA_VAL);
2343 }
2344 else //disable
2345 {
2346 HAL_WriteRegBit(SUB_REG(VOP_RAMAP_LUMA), 0, BIT7);
2347 }
2348
2349 //set VC1 Chroma value
2350 if(stVC1RangeMapInfo->bIsEnableChroma)
2351 {
2352 HAL_WriteRegBit(SUB_REG(VOP_RAMAP_CHROMA), 1, BIT7);
2353 HAL_WriteByteMask(SUB_REG(VOP_RAMAP_CHROMA), u8Chroma, VOP_RAMAP_CHROMA_VAL);
2354 }
2355 else
2356 {
2357 HAL_WriteRegBit(SUB_REG(VOP_RAMAP_CHROMA), 0, BIT7);
2358 }
2359 #endif
2360 break;
2361 default:
2362 break;
2363 }
2364 return TRUE;
2365 }
2366
2367 MS_U16 g_u16SetStartX = 0;
2368 MS_U16 g_u16SetStartY = 0;
2369 MS_BOOL g_bIsY4Align = 0;
2370
HAL_MVOP_SetStartX(MVOP_DevID eID,MS_U16 u16XPos)2371 void HAL_MVOP_SetStartX(MVOP_DevID eID, MS_U16 u16XPos)
2372 {
2373 switch(eID)
2374 {
2375 case E_MVOP_DEV_0:
2376 #if 0 //tv setting
2377 u16XPos = ALIGN_UPTO_2(u16XPos);
2378 HAL_WriteByte(VOP_REG_CROP_HSTART, u16XPos & 0xff);
2379 HAL_WriteByte((VOP_REG_CROP_HSTART + 1),((u16XPos) >> (8)) & (0x1f));
2380 if(0 == u16XPos)
2381 {
2382 g_pHalMVOPCtx->u16CropXStart = 0;
2383 }
2384 else
2385 {
2386 g_pHalMVOPCtx->u16CropXStart += u16XPos;
2387 }
2388 #endif
2389 if(g_pHalMVOPCtx == NULL)
2390 {
2391 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
2392 return;
2393 }
2394 u16XPos = ALIGN_UPTO_2(u16XPos);
2395 g_pHalMVOPCtx->u16CropXStart = u16XPos;
2396 HAL_WriteByte(VOP_REG_CROP_HSTART, u16XPos);
2397 HAL_WriteByteMask((VOP_REG_CROP_HSTART + 1),((u16XPos) >> (8)) & (0x1f), 0x1f);
2398 // Write trigger
2399 HAL_MVOP_LoadReg();
2400 break;
2401 case E_MVOP_DEV_1:
2402 #if MVOP_SUPPORT_SUB
2403 #if 0 //tv setting
2404 u16XPos = ALIGN_UPTO_2(u16XPos);
2405 HAL_WriteByte(SUB_REG(VOP_REG_CROP_HSTART), u16XPos & 0xff);
2406 HAL_WriteByte(SUB_REG((VOP_REG_CROP_HSTART + 1)),((u16XPos) >> (8)) & (0x1f));
2407 if(0 == u16XPos)
2408 {
2409 g_pHalMVOPCtx->u16SubCropXStart = 0;
2410 }
2411 else
2412 {
2413 g_pHalMVOPCtx->u16SubCropXStart += u16XPos;
2414 }
2415 #endif
2416 u16XPos = ALIGN_UPTO_2(u16XPos);
2417 g_pHalMVOPCtx->u16SubCropXStart = u16XPos;
2418 HAL_WriteByte(SUB_REG(VOP_REG_CROP_HSTART), u16XPos);
2419 HAL_WriteByteMask(SUB_REG(VOP_REG_CROP_HSTART + 1),((u16XPos) >> (8)) & (0x1f), 0x1f);
2420 // Write trigger
2421 HAL_MVOP_SubLoadReg();
2422 #endif
2423 break;
2424 default:
2425 break;
2426 }
2427 }
2428
2429
HAL_MVOP_SetStartY(MVOP_DevID eID,MS_U16 u16YPos,MS_BOOL bIsInterlace)2430 void HAL_MVOP_SetStartY(MVOP_DevID eID, MS_U16 u16YPos, MS_BOOL bIsInterlace)
2431 {
2432 switch(eID)
2433 {
2434 case E_MVOP_DEV_0:
2435 #if 0
2436 HAL_WriteByteMask(VOP_REG_CROP_VSTART, u16YPos & 0xff, 0xff);
2437 HAL_WriteByteMask((VOP_REG_CROP_VSTART + 1), ((u16YPos) >> (8)) & (0x1f), 0x1f);
2438 if(0 == u16YPos)
2439 {
2440 g_pHalMVOPCtx->u16CropYStart = 0;
2441 }
2442 else
2443 {
2444 g_pHalMVOPCtx->u16CropYStart += u16YPos;
2445 }
2446 #endif
2447 if(g_pHalMVOPCtx == NULL)
2448 {
2449 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
2450 return;
2451 }
2452 g_pHalMVOPCtx->u16CropYStart = u16YPos;
2453 if(u16YPos == 0)
2454 u16YPos |= 0x6000;
2455 else
2456 u16YPos |= 0x2000;
2457
2458 HAL_WriteByte(VOP_REG_CROP_VSTART, u16YPos);
2459 HAL_WriteByteMask((VOP_REG_CROP_VSTART + 1), ((u16YPos) >> (8)) & (0x7f), 0x7f);
2460 // Write trigger
2461 HAL_MVOP_LoadReg();
2462 break;
2463 case E_MVOP_DEV_1:
2464 #if MVOP_SUPPORT_SUB
2465 #if 0
2466 HAL_WriteByteMask(SUB_REG(VOP_REG_CROP_VSTART), u16YPos & 0xff, 0xff);
2467 HAL_WriteByteMask(SUB_REG((VOP_REG_CROP_VSTART + 1)), ((u16YPos) >> (8)) & (0x1f), 0x1f);
2468 if(0 == u16YPos)
2469 {
2470 g_pHalMVOPCtx->u16SubCropYStart = 0;
2471 }
2472 else
2473 {
2474 g_pHalMVOPCtx->u16SubCropYStart += u16YPos;
2475 }
2476 #endif
2477 if(g_pHalMVOPCtx == NULL)
2478 {
2479 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
2480 return;
2481 }
2482 g_pHalMVOPCtx->u16SubCropYStart = u16YPos;
2483 if(u16YPos == 0)
2484 u16YPos |= 0x6000;
2485 else
2486 u16YPos |= 0x2000;
2487
2488 HAL_WriteByte(SUB_REG(VOP_REG_CROP_VSTART), u16YPos);
2489 HAL_WriteByteMask(SUB_REG(VOP_REG_CROP_VSTART + 1), ((u16YPos) >> (8)) & (0x7f), 0x7f);
2490 // Write trigger
2491 HAL_MVOP_SubLoadReg();
2492 #endif
2493 break;
2494 default:
2495 break;
2496 }
2497 }
2498
2499 //-----------------------------------------
2500 //STB chip set crop size is from image (0,0) ,
2501 //including startx,y
2502 //Kano hw crop before mirror
2503 //-----------------------------------------
HAL_MVOP_SetPicWidthMinus(MVOP_DevID eID,MS_U16 u16XSizes,MS_U16 u16Width)2504 void HAL_MVOP_SetPicWidthMinus(MVOP_DevID eID, MS_U16 u16XSizes, MS_U16 u16Width)
2505 {
2506 EN_MVOP_Output_3D_TYPE en3DType = E_MVOP_OUTPUT_3D_NONE;
2507
2508 switch(eID)
2509 {
2510 if(g_pHalMVOPCtx == NULL)
2511 {
2512 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
2513 return;
2514 }
2515 case E_MVOP_DEV_0:
2516 if(0 == u16XSizes)
2517 {
2518 g_pHalMVOPCtx->u16CropXSize = 0;
2519 }
2520 else
2521 {
2522 u16XSizes = u16XSizes + 1 - g_pHalMVOPCtx->u16CropXStart ;
2523 u16XSizes = ALIGN_UPTO_2(u16XSizes);
2524 g_pHalMVOPCtx->u16CropXSize = u16XSizes;
2525 }
2526 en3DType = HAL_MVOP_GetOutput3DType();
2527 MVOP_DBG(MVOP_PRINTF("[MVOP][DBG] 3D FORMAT = %d\n",en3DType);)
2528 if(en3DType == E_MVOP_OUTPUT_3D_SBS)
2529 {
2530 u16XSizes = u16XSizes >> 1;
2531 }
2532 HAL_WriteByte(VOP_REG_CROP_HSIZE, u16XSizes);
2533 HAL_WriteByteMask((VOP_REG_CROP_HSIZE + 1), ((u16XSizes) >> (8)) & (0x1f), 0x1f);
2534 // Write trigger
2535 HAL_MVOP_LoadReg();
2536 break;
2537 case E_MVOP_DEV_1:
2538 #if MVOP_SUPPORT_SUB
2539
2540 if(0 == u16XSizes)
2541 {
2542 g_pHalMVOPCtx->u16SubCropXSize = 0;
2543 }
2544 else
2545 {
2546 u16XSizes = u16XSizes + 1 - g_pHalMVOPCtx->u16SubCropXStart ;
2547 u16XSizes = ALIGN_UPTO_2(u16XSizes);
2548 g_pHalMVOPCtx->u16SubCropXSize = u16XSizes;
2549 }
2550 en3DType = HAL_MVOP_SubGetOutput3DType();
2551 MVOP_DBG(MVOP_PRINTF("[MVOP][DBG] 3D FORMAT = %d\n",en3DType);)
2552 if(en3DType == E_MVOP_OUTPUT_3D_SBS)
2553 {
2554 u16XSizes = u16XSizes >> 1;
2555 }
2556 HAL_WriteByte(SUB_REG(VOP_REG_CROP_HSIZE), u16XSizes);
2557 HAL_WriteByteMask(SUB_REG(VOP_REG_CROP_HSIZE + 1), ((u16XSizes) >> (8)) & (0x1f), 0x1f);
2558 // Write trigger
2559 HAL_MVOP_SubLoadReg();
2560 #endif
2561 break;
2562 default:
2563 break;
2564 }
2565 }
2566
HAL_MVOP_SetPicHeightMinus(MVOP_DevID eID,MS_U16 u16YSizes,MS_U16 u16Height)2567 void HAL_MVOP_SetPicHeightMinus(MVOP_DevID eID, MS_U16 u16YSizes, MS_U16 u16Height)
2568 {
2569 EN_MVOP_Output_3D_TYPE en3DType = E_MVOP_OUTPUT_3D_NONE;
2570
2571 switch(eID)
2572 {
2573 if(g_pHalMVOPCtx == NULL)
2574 {
2575 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
2576 return;
2577 }
2578 case E_MVOP_DEV_0:
2579 if(0 == u16YSizes)
2580 {
2581 g_pHalMVOPCtx->u16CropYSize = 0;
2582 }
2583 else
2584 {
2585 u16YSizes = u16YSizes + 1 - g_pHalMVOPCtx->u16CropYStart ;
2586 g_pHalMVOPCtx->u16CropYSize = u16YSizes;
2587 }
2588 en3DType = HAL_MVOP_GetOutput3DType();
2589 MVOP_DBG(MVOP_PRINTF("[MVOP][DBG] 3D FORMAT = %d\n",en3DType);)
2590 if((en3DType == E_MVOP_OUTPUT_3D_TB) || (en3DType == E_MVOP_OUTPUT_3D_LA))
2591 {
2592 u16YSizes = u16YSizes >> 1;
2593 }
2594 HAL_WriteByte(VOP_REG_CROP_VSIZE, u16YSizes);
2595 HAL_WriteByteMask((VOP_REG_CROP_VSIZE + 1), ((u16YSizes) >> (8)) & (0x1f), 0x1f);
2596 // Write trigger
2597 HAL_MVOP_LoadReg();
2598 break;
2599 case E_MVOP_DEV_1:
2600 #if MVOP_SUPPORT_SUB
2601 if(0 == u16YSizes)
2602 {
2603 g_pHalMVOPCtx->u16CropYSize = 0;
2604 }
2605 else
2606 {
2607 u16YSizes = u16YSizes + 1 - g_pHalMVOPCtx->u16CropYStart ;
2608 g_pHalMVOPCtx->u16CropYSize = u16YSizes;
2609 }
2610 en3DType = HAL_MVOP_SubGetOutput3DType();
2611 MVOP_DBG(MVOP_PRINTF("[MVOP][DBG] 3D FORMAT = %d\n",en3DType);)
2612 if((en3DType == E_MVOP_OUTPUT_3D_TB) || (en3DType == E_MVOP_OUTPUT_3D_LA))
2613 {
2614 u16YSizes = u16YSizes >> 1;
2615 }
2616 HAL_WriteByte(SUB_REG(VOP_REG_CROP_VSIZE), u16YSizes);
2617 HAL_WriteByteMask(SUB_REG(VOP_REG_CROP_VSIZE + 1), ((u16YSizes) >> (8)) & (0x1f), 0x1f);
2618 // Write trigger
2619 HAL_MVOP_SubLoadReg();
2620
2621 #endif
2622 break;
2623 default:
2624 break;
2625 }
2626 }
2627
2628
2629 /******************************************************************************/
2630 /// Set MVOP Saving BW Mode
2631 /// @ Napoli this command should be set after MDrv_MVOP_SetOutputCfg
2632 /******************************************************************************/
HAL_MVOP_Set420BWSaveMode(MS_BOOL bEnable)2633 MS_BOOL HAL_MVOP_Set420BWSaveMode(MS_BOOL bEnable)
2634 {
2635 MS_BOOL bValue = FALSE;
2636
2637 //hw limtation: 3DLA/3DSBS/422/p mode in, i mode out/i mode in, p mode out(only need to check in MCU mode)
2638 bValue = (g_pHalMVOPCtx->b3DLRAltSBSOutput || g_pHalMVOPCtx->b3DLRAltOutput /*|| g_pHalMVOPCtx->b3DLRMode*/ || g_pHalMVOPCtx->bIs422 || (g_pHalMVOPCtx->u16Hsize > 2048));
2639
2640 if(bValue)
2641 {
2642 MVOP_DBG(MVOP_PRINTF("%s Hit the limitation of saving bw, disable BW Saving mode\n", __FUNCTION__);)
2643 HAL_WriteRegBit(VOP_REG_DUMMY, 0, VOP_420_BW_SAVE);
2644 HAL_WriteRegBit(VOP_REG_BW_SAVE, 0, VOP_420_BW_SAVE_EX);
2645 HAL_MVOP_LoadReg();
2646 return FALSE;
2647 }
2648 else
2649 {
2650 HAL_WriteRegBit(VOP_REG_DUMMY, bEnable, VOP_420_BW_SAVE);
2651 if( g_pHalMVOPCtx->b3DLRMode == FALSE)
2652 {
2653 HAL_WriteRegBit(VOP_REG_BW_SAVE, bEnable, VOP_420_BW_SAVE_EX);
2654 }
2655
2656 HAL_MVOP_LoadReg();
2657 return TRUE;
2658 }
2659 }
2660
HAL_MVOP_SetEVDYUVBaseAdd(MVOP_EVDBaseAddInput * stEVDBaseAddInfo)2661 MS_BOOL HAL_MVOP_SetEVDYUVBaseAdd(MVOP_EVDBaseAddInput *stEVDBaseAddInfo)
2662 {
2663 //----------------------------------------------------
2664 // Set MSB YUV Address
2665 //----------------------------------------------------
2666
2667 MS_PHY u64tmp = 0;
2668
2669 if (g_pHalMVOPCtx == NULL)
2670 {
2671 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
2672 return FALSE;
2673 }
2674 // Y offset
2675 u64tmp = stEVDBaseAddInfo->u32MSBYOffset >> 3;
2676 if ( !stEVDBaseAddInfo->bProgressive)
2677 { //Refine Y offset for interlace repeat bottom field
2678 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
2679 {
2680 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2681 u64tmp += 2;
2682 }
2683 else
2684 {
2685 MVOP_DBG("%d eRepeatField(%x) is TOP or NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2686 }
2687 }
2688 HAL_WriteByte(VOP_JPG_YSTR0_L, u64tmp & 0xff);
2689 HAL_WriteByte((VOP_JPG_YSTR0_L+1), (u64tmp >> 8) & 0xff);
2690 HAL_WriteByte((VOP_JPG_YSTR0_H), (u64tmp >> 16) & 0xff);
2691 HAL_WriteByte((VOP_JPG_YSTR0_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2692
2693 if (!stEVDBaseAddInfo->bProgressive )
2694 { //Y offset of bottom field if interlace
2695 HAL_WriteByte(VOP_JPG_YSTR1_L, u64tmp & 0xff);
2696 HAL_WriteByte((VOP_JPG_YSTR1_L+1), (u64tmp >> 8) & 0xff);
2697 HAL_WriteByte((VOP_JPG_YSTR1_H), (u64tmp >> 16) & 0xff);
2698 HAL_WriteByte((VOP_JPG_YSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2699 }
2700
2701 if (stEVDBaseAddInfo->b422Pack)
2702 {
2703 stEVDBaseAddInfo->u32MSBUVOffset = stEVDBaseAddInfo->u32MSBYOffset + 16; //add 16 for 128bit; add 8 for 64bit
2704 }
2705 // UV offset
2706 u64tmp = stEVDBaseAddInfo->u32MSBUVOffset >> 3;
2707 if( !stEVDBaseAddInfo->bProgressive )
2708 { //Refine UV offset for interlace repeat bottom field
2709 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
2710 {
2711 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2712 u64tmp += 2;
2713 }
2714 else
2715 {
2716 MVOP_DBG("%d eRepeatField(%x) is TOP/NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2717 }
2718 }
2719 HAL_WriteByte(VOP_JPG_UVSTR0_L, u64tmp & 0xff);
2720 HAL_WriteByte((VOP_JPG_UVSTR0_L+1), (u64tmp >> 8) & 0xff);
2721 HAL_WriteByte((VOP_JPG_UVSTR0_H), (u64tmp >> 16) & 0xff);
2722 HAL_WriteByte((VOP_JPG_UVSTR0_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2723
2724 if( !stEVDBaseAddInfo->bProgressive )
2725 { //UV offset of bottom field if interlace
2726 HAL_WriteByte(VOP_JPG_UVSTR1_L, u64tmp & 0xff);
2727 HAL_WriteByte((VOP_JPG_UVSTR1_L+1), (u64tmp >> 8) & 0xff);
2728 HAL_WriteByte((VOP_JPG_UVSTR1_H), (u64tmp >> 16) & 0xff);
2729 HAL_WriteByte((VOP_JPG_UVSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2730 }
2731
2732 //----------------------------------------------------
2733 // Set MSB YUV Address
2734 //----------------------------------------------------
2735 if(stEVDBaseAddInfo->bEnLSB)
2736 {
2737 //Enable LSB
2738 HAL_WriteRegBit(VOP_EVD_10B_EN, 1, VOP_EVD_10B_Y_EN);
2739 HAL_WriteRegBit(VOP_EVD_10B_EN, 1, VOP_EVD_10B_UV_EN);
2740 HAL_WriteRegBit(VOP_REG_MASK, 0, VOP_LSB_REQ_MASK);
2741
2742 // Y offset
2743 u64tmp = stEVDBaseAddInfo->u32LSBYOffset >> 3;
2744 if ( !stEVDBaseAddInfo->bProgressive)
2745 { //Refine Y offset for interlace repeat bottom field
2746 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
2747 {
2748 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2749 u64tmp += 2;
2750 }
2751 else
2752 {
2753 MVOP_DBG("%d eRepeatField(%x) is TOP or NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2754 }
2755 }
2756 HAL_WriteByte(VOP_LSB_YSTR0_L, u64tmp & 0xff);
2757 HAL_WriteByte((VOP_LSB_YSTR0_L+1), (u64tmp >> 8) & 0xff);
2758 HAL_WriteByte((VOP_LSB_YSTR0_L), (u64tmp >> 16) & 0xff);
2759 HAL_WriteByte((VOP_LSB_YSTR0_L+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2760
2761 if (!stEVDBaseAddInfo->bProgressive )
2762 { //Y offset of bottom field if interlace
2763 HAL_WriteByte(VOP_LSB_YSTR1_L, u64tmp & 0xff);
2764 HAL_WriteByte((VOP_LSB_YSTR1_L+1), (u64tmp >> 8) & 0xff);
2765 HAL_WriteByte((VOP_LSB_YSTR1_H), (u64tmp >> 16) & 0xff);
2766 HAL_WriteByte((VOP_LSB_YSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2767 }
2768
2769 if (stEVDBaseAddInfo->b422Pack)
2770 {
2771 stEVDBaseAddInfo->u32LSBUVOffset = stEVDBaseAddInfo->u32LSBYOffset + 16; //add 16 for 128bit; add 8 for 64bit
2772 }
2773 // UV offset
2774 u64tmp = stEVDBaseAddInfo->u32LSBUVOffset >> 3;
2775 if( !stEVDBaseAddInfo->bProgressive )
2776 { //Refine UV offset for interlace repeat bottom field
2777 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
2778 {
2779 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2780 u64tmp += 2;
2781 }
2782 else
2783 {
2784 MVOP_DBG("%d eRepeatField(%x) is TOP/NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
2785 }
2786 }
2787 HAL_WriteByte(VOP_LSB_UVSTR0_L, u64tmp & 0xff);
2788 HAL_WriteByte((VOP_LSB_UVSTR0_L+1), (u64tmp >> 8) & 0xff);
2789 HAL_WriteByte((VOP_LSB_UVSTR0_H), (u64tmp >> 16) & 0xff);
2790 HAL_WriteByte((VOP_LSB_UVSTR0_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2791
2792 if( !stEVDBaseAddInfo->bProgressive )
2793 { //UV offset of bottom field if interlace
2794 HAL_WriteByte(VOP_LSB_UVSTR1_L, u64tmp & 0xff);
2795 HAL_WriteByte((VOP_LSB_UVSTR1_L+1), (u64tmp >> 8) & 0xff);
2796 HAL_WriteByte((VOP_LSB_UVSTR1_H), (u64tmp >> 16) & 0xff);
2797 HAL_WriteByte((VOP_LSB_UVSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
2798 }
2799 }
2800
2801 return TRUE;
2802 }
2803
2804 /******************************************************************************/
2805 /// Set MVOP repeat previous frame IF VDEC can not finish vsync.
2806 /// this command should be set disable as call VDEC Exit.
2807 /******************************************************************************/
HAL_MVOP_SetRptPreVsyncFrame(MVOP_DevID eID,MS_BOOL bEnable)2808 void HAL_MVOP_SetRptPreVsyncFrame(MVOP_DevID eID, MS_BOOL bEnable)
2809 {
2810 switch(eID)
2811 {
2812 case E_MVOP_DEV_0:
2813 {
2814 g_pHalMVOPCtx->bRptPreVsync = bEnable;
2815 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, BIT3);
2816 break;
2817 }
2818 case E_MVOP_DEV_1:
2819 {
2820 #if MVOP_SUPPORT_SUB
2821 g_pHalMVOPCtx->bSubRptPreVsync = bEnable;
2822 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, BIT3);
2823 #endif
2824 break;
2825 }
2826 default:
2827 MVOP_PRINTF("[Warning] MVOP_DevID not support!\n");
2828 break;
2829 }
2830 }
2831
HAL_MVOP_PowerStateSuspend(void)2832 void HAL_MVOP_PowerStateSuspend(void)
2833 {
2834 MS_BOOL bFirstDrvInstant = FALSE;
2835 MVOP_HalInitCtxResults eRet = _HAL_MVOP_InitContext(&bFirstDrvInstant);
2836 if(eRet == E_MVOP_INIT_FAIL)
2837 {
2838 MVOP_DBG(MVOP_PRINTF("[%s] MVOP Context Init failed!\n",__FUNCTION__);)
2839 return;
2840 }
2841 g_pHalMVOPCtx->bIsInit = 0;
2842 #if MVOP_SUPPORT_SUB
2843 g_pHalMVOPCtx->bSubIsInit = 0;
2844 #endif
2845 }
2846
HAL_MVOP_GetHandShakeMode(MVOP_DevID eID)2847 MVOP_HSMode HAL_MVOP_GetHandShakeMode(MVOP_DevID eID)
2848 {
2849 MVOP_HSMode eRet = E_MVOP_HS_NOT_SUPPORT;
2850
2851 switch(eID)
2852 {
2853 case E_MVOP_DEV_0:
2854 if(HAL_ReadRegBit(VOP_HANDSHAKE, BIT0))
2855 {
2856 eRet = E_MVOP_HS_ENABLE;
2857 }
2858 else
2859 {
2860 eRet = E_MVOP_HS_DISABLE;
2861 }
2862 break;
2863 case E_MVOP_DEV_1:
2864 #if MVOP_SUPPORT_SUB
2865 if(HAL_ReadRegBit(SUB_REG(VOP_HANDSHAKE), BIT0))
2866 {
2867 eRet = E_MVOP_HS_ENABLE;
2868 }
2869 else
2870 {
2871 eRet = E_MVOP_HS_DISABLE;
2872 }
2873 #endif
2874 break;
2875 default:
2876 eRet = E_MVOP_HS_INVALID_PARAM;
2877 break;
2878 }
2879 return eRet;
2880 }
2881
HAL_MVOP_CheckSTCCW(void)2882 MS_BOOL HAL_MVOP_CheckSTCCW(void)
2883 {
2884 MS_U16 u16STC_CW_L = 0;
2885 MS_U16 u16STC_CW_H = 0;
2886 MS_BOOL u16STC_CW_SEL = 0;
2887 MS_BOOL u16TSP_CLK_EN = 0;
2888
2889 u16STC_CW_L = HAL_Read2Byte(REG_STC0_CW_L)&0xffff;
2890 u16STC_CW_H = HAL_Read2Byte(REG_STC0_CW_H)&0xffff;
2891
2892 u16STC_CW_SEL = (HAL_ReadRegBit(REG_STC_CW_SLE_L, BIT1) == BIT1);
2893 u16TSP_CLK_EN = !(HAL_ReadRegBit(REG_TSP_CLK, BIT0) == BIT0);
2894
2895 if((((u16STC_CW_L || u16STC_CW_H) == 0) && (u16STC_CW_SEL == 0)) || ((u16STC_CW_SEL == 1) && (u16TSP_CLK_EN == 0)))
2896 return FALSE;
2897 else
2898 return TRUE;
2899
2900 }
2901
2902 #define MIU1_REG_BASE 0x0600
HAL_MVOP_GetIsMiuIPControl(HALMVOPMIUCLIENTINFO stInfo)2903 MS_BOOL HAL_MVOP_GetIsMiuIPControl(HALMVOPMIUCLIENTINFO stInfo)
2904 {
2905 MS_U32 u32RegMiu = 0;
2906 MS_U16 u16Mask = 0;
2907 MS_BOOL bRet = FALSE;
2908
2909 u32RegMiu = MIU1_REG_BASE + (0xF0+(stInfo.u8Gp * 2));
2910 if(stInfo.u8BitPos < 8)
2911 {
2912 u16Mask = 1<<stInfo.u8BitPos;
2913 }
2914 else
2915 {
2916 u16Mask = 1<<(stInfo.u8BitPos-8);
2917 u32RegMiu += 1;
2918 }
2919 MVOP_DBG(MVOP_PRINTF("[%s] u32RegMiu = 0x%lx, u16Mask = 0x%x\n",__FUNCTION__, u32RegMiu,u16Mask);)
2920 if(HAL_ReadRegBit(u32RegMiu, u16Mask))
2921 {
2922 bRet = TRUE;
2923 }
2924
2925 return bRet;
2926 }
2927
HAL_MVOP_SelMIU(MVOP_DevID eDevID,HALMVOPMIUSEL eMiuMSB0,HALMVOPMIUSEL eMiuMSB1,HALMVOPMIUSEL eMiuLSB0,HALMVOPMIUSEL eMiuLSB1)2928 void HAL_MVOP_SelMIU(MVOP_DevID eDevID, HALMVOPMIUSEL eMiuMSB0, HALMVOPMIUSEL eMiuMSB1, HALMVOPMIUSEL eMiuLSB0, HALMVOPMIUSEL eMiuLSB1)
2929 {
2930 MS_U8 u8MSBVlue = 0;
2931 MS_U8 u8LSBVlue = 0;
2932
2933 if(eMiuMSB0 != eMiuMSB1)
2934 HAL_WriteRegBit(VOP_MIU_SEL, TRUE, BIT0);
2935 else
2936 HAL_WriteRegBit(VOP_MIU_SEL, FALSE, BIT0);
2937
2938 if(eMiuLSB0 != eMiuLSB1)
2939 HAL_WriteRegBit(VOP_MIU_SEL, TRUE, BIT1);
2940 else
2941 HAL_WriteRegBit(VOP_MIU_SEL, FALSE, BIT1);
2942
2943 u8MSBVlue |= (eMiuMSB0 << 4);
2944 u8MSBVlue |= (eMiuMSB1 << 6);
2945
2946 u8LSBVlue |= (eMiuLSB0 << 4);
2947 u8LSBVlue |= (eMiuLSB1 << 6);
2948
2949 switch(eDevID)
2950 {
2951 case E_MVOP_DEV_0:
2952 {
2953 // MSB
2954 HAL_WriteByteMask(VOP_MIU_SEL, u8MSBVlue, VOP_MSB_BUF0_MIU_SEL | VOP_MSB_BUF1_MIU_SEL);
2955 // LSB
2956 HAL_WriteByteMask(VOP_MIU_SEL_LSB, u8LSBVlue, VOP_LSB_BUF0_MIU_SEL | VOP_LSB_BUF1_MIU_SEL);
2957 break;
2958 }
2959 #if MVOP_SUPPORT_SUB
2960 case E_MVOP_DEV_1:
2961 {
2962 // MSB
2963 HAL_WriteByteMask(SUB_REG(VOP_MIU_SEL), u8MSBVlue, VOP_MSB_BUF0_MIU_SEL | VOP_MSB_BUF1_MIU_SEL);
2964 // LSB
2965 HAL_WriteByteMask(SUB_REG(VOP_MIU_SEL_LSB), u8LSBVlue, VOP_LSB_BUF0_MIU_SEL | VOP_LSB_BUF1_MIU_SEL);
2966 break;
2967 }
2968 #endif
2969 default:
2970 break;
2971 }
2972 }
2973
HAL_MVOP_GetIsOnlyMiuIPControl(void)2974 MS_BOOL HAL_MVOP_GetIsOnlyMiuIPControl(void)
2975 {
2976 return TRUE;
2977 }
2978
HAL_MVOP_SetDefaultClk(MVOP_DevID eDevID)2979 HALMVOPFREQUENCY HAL_MVOP_SetDefaultClk(MVOP_DevID eDevID)
2980 {
2981 HALMVOPFREQUENCY eRet = HALMVOP_160MHZ;
2982 switch(eDevID)
2983 {
2984 case E_MVOP_DEV_0:
2985 {
2986 if(g_pHalMVOPCtx->bIsXcTrig == FALSE)
2987 {
2988 MVOP_PRINTF("[%s] HALMVOP_SYNCMODE\n",__FUNCTION__);
2989 eRet = HALMVOP_SYNCMODE;
2990 }
2991 break;
2992 }
2993 #if MVOP_SUPPORT_SUB
2994 case E_MVOP_DEV_1:
2995 {
2996 if(g_pHalMVOPCtx->bSubIsXcTrig == FALSE)
2997 {
2998 MVOP_PRINTF("[%s] HALMVOP_SYNCMODE\n",__FUNCTION__);
2999 eRet = HALMVOP_SYNCMODE;
3000 }
3001 break;
3002 }
3003 #endif
3004 default:
3005 break;
3006 }
3007
3008 MVOP_PRINTF("[%s] clock = %d\n",__FUNCTION__,eRet);
3009 return eRet;
3010 }
3011
HAL_MVOP_GetMaxFramerate(MVOP_DevID eDevID,MVOP_GetMaxFps * stStreamInfo)3012 void HAL_MVOP_GetMaxFramerate(MVOP_DevID eDevID, MVOP_GetMaxFps* stStreamInfo)
3013 {
3014 MS_U64 u64MaxClk = 0;
3015 MS_U16 u16HsizeTiming = 0;
3016 MS_U16 u16VsizeTiming = 0;
3017
3018 if(NULL == stStreamInfo)
3019 {
3020 MVOP_PRINTF("[%s] Input parameter is NULL!\n",__FUNCTION__);
3021 return;
3022 }
3023
3024 switch(eDevID)
3025 {
3026 case E_MVOP_DEV_0:
3027 #if MVOP_SUPPORT_SUB
3028 case E_MVOP_DEV_1:
3029 #endif
3030 {
3031 if(_HAL_MVOP_IsSupport4k2k2P())
3032 {
3033 u16HsizeTiming = stStreamInfo->u16HSize >> 1;
3034 }
3035 else
3036 {
3037 u16HsizeTiming = stStreamInfo->u16HSize;
3038 u16HsizeTiming = ALIGN_UPTO_2(u16HsizeTiming);
3039 }
3040 if(stStreamInfo->b3DSBS)
3041 {
3042 u16HsizeTiming *= 2;
3043 }
3044 if(stStreamInfo->u16HSize > 720)
3045 {
3046 u16HsizeTiming += MVOP_HBlank_HD;
3047 }
3048 else
3049 {
3050 u16HsizeTiming += MVOP_HBlank_SD;
3051 }
3052
3053 u64MaxClk = HAL_MVOP_GetMaximumClk();
3054 if(stStreamInfo->b3DTB)
3055 {
3056 u16VsizeTiming = stStreamInfo->u16VSize*2 + MVOP_VBlank;
3057 }
3058 else
3059 {
3060 u16VsizeTiming = stStreamInfo->u16VSize + MVOP_VBlank;
3061 }
3062
3063 stStreamInfo->u32Framerate = (u64MaxClk / u16HsizeTiming / u16VsizeTiming)*1000;
3064 }
3065 break;
3066 default:
3067 break;
3068 }
3069
3070 }
3071
HAL_MVOP_GetIsSendingData(MVOP_DevID eDevID)3072 MS_BOOL HAL_MVOP_GetIsSendingData(MVOP_DevID eDevID)
3073 {
3074 MS_U8 u8IsSend = 0;
3075
3076 if(eDevID == E_MVOP_DEV_0)
3077 {
3078 u8IsSend = HAL_ReadByte(VOP_DEBUG_2D_H) & VOP_DMA_STATUS;
3079 if(u8IsSend)
3080 return TRUE;
3081 else
3082 return FALSE;
3083 }
3084 else
3085 {
3086 MVOP_PRINTF("[Warning] not support device %d\n",eDevID);
3087 return FALSE;
3088 }
3089 }
3090
3091 /******************************************************************************/
3092 /// Set MVOP Handshake Mode, XC should be synchronous with MVOP.
3093 /// this command should be before mvop enable.(before 1st frame)
3094 /******************************************************************************/
HAL_MVOP_SetTimingFromXC(MVOP_DevID eID,MS_BOOL bEnable)3095 void HAL_MVOP_SetTimingFromXC(MVOP_DevID eID, MS_BOOL bEnable)
3096 {
3097 switch(eID)
3098 {
3099 MVOP_DBG(MVOP_PRINTF("[MVOP] HAL_MVOP_SetTimingFromXC = %d\n",bEnable);)
3100 case E_MVOP_DEV_0:
3101 {
3102 g_pHalMVOPCtx->bIsXcTrig = bEnable;
3103 if(bEnable)
3104 {
3105 HAL_WriteByteMask(VOP_HANDSHAKE, 0x06, VOP_TRIG_FROM_XC|VOP_VSUNC_FROM_XC);
3106 //HAL_WriteRegBit(VOP_CTRL1, 0, BIT4); // disable inverse the field to IP - not in kano
3107
3108 }
3109 else
3110 {
3111 HAL_WriteByteMask(VOP_HANDSHAKE, 0x00, VOP_TRIG_FROM_XC|VOP_VSUNC_FROM_XC);
3112 //HAL_WriteRegBit(VOP_CTRL1, 1, BIT4); // inverse the field to IP - not in kano
3113 }
3114 HAL_MVOP_LoadReg();
3115 break;
3116 }
3117 case E_MVOP_DEV_1:
3118 {
3119 #if MVOP_SUPPORT_SUB
3120 g_pHalMVOPCtx->bSubIsXcTrig = bEnable;
3121 if(bEnable)
3122 {
3123 HAL_WriteByteMask(SUB_REG(VOP_HANDSHAKE), 0x06, VOP_TRIG_FROM_XC|VOP_VSUNC_FROM_XC);
3124 }
3125 else
3126 {
3127 HAL_WriteByteMask(SUB_REG(VOP_HANDSHAKE), 0x00, VOP_TRIG_FROM_XC|VOP_VSUNC_FROM_XC);
3128 }
3129 HAL_MVOP_SubLoadReg();
3130 #endif
3131 break;
3132 }
3133 default:
3134 MVOP_PRINTF("[Warning] MVOP_DevID not support!\n");
3135 break;
3136 }
3137 }
3138
HAL_MVOP_ResetReg(MVOP_DevID eDevID,MS_U16 u16ECONumber)3139 void HAL_MVOP_ResetReg(MVOP_DevID eDevID, MS_U16 u16ECONumber)
3140 {
3141
3142 switch(eDevID)
3143 {
3144 case E_MVOP_DEV_0:
3145 {
3146 #if ENABLE_3D_LR_MODE
3147 HAL_MVOP_Enable3DLR(DISABLE);
3148 #endif
3149 #if SUPPORT_3DLR_ALT_SBS
3150 HAL_MVOP_Set3DLRAltOutput(DISABLE);
3151 HAL_MVOP_Set3DLRAltSBSOutput(DISABLE);
3152 #endif
3153
3154 /*****************************************************/
3155 // Reset MVOP setting
3156 HAL_WriteByteMask(VOP_TST_IMG, 0x00, BIT2 | BIT1 | BIT0);//reset test pattern or BG
3157 HAL_WriteRegBit(VOP_TST_IMG, BIT6, BIT6);//reset test pattern or BG
3158 HAL_MVOP_Set3DLRAltOutput_VHalfScaling(DISABLE); //reset to default: disable 3D L/R alternative output.
3159 HAL_MVOP_Set3DLR2ndCfg(DISABLE); //reset to default: disable 3D L/R 2nd pitch.
3160 HAL_MVOP_SetRgbFormat(E_MVOP_RGB_NONE); //reset rgb format
3161 HAL_WriteRegBit(VOP_CTRL1, 0, VOP_MVD_VS_MD); //default use original vsync
3162 //stb series: default hsk
3163 //HAL_WriteRegBit(VOP_REG_422_OUT_EN, 1, BIT0); //kano ip2 444
3164 //apple for debug
3165 HAL_WriteRegBit(VOP_HANDSHAKE, 1, VOP_HANDSHAKE_MODE);
3166 g_pHalMVOPCtx->bIsHS = TRUE;
3167 HAL_MVOP_SetTimingFromXC(E_MVOP_DEV_0, TRUE);
3168 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, ENABLE, VOP_HK_MASK); //default hsk mode bk background
3169
3170 // Kano hsk default 2p
3171 HAL_MVOP_SetEnable4k2k2P(TRUE);
3172
3173 HAL_MVOP_SetBlackBG();//set MVOP test pattern to black
3174 HAL_WriteRegBit(VOP_REG_STRIP_ALIGN, 0, BIT0);// clear extend strip len bit by default
3175 HAL_WriteByteMask(VOP_MIU_IF, VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);// set mvop to 128bit_i128 interface
3176 HAL_WriteRegBit(VOP_INPUT_SWITCH1, 0, BIT2|BIT3);// Disable H264 or RM Input
3177
3178 HAL_WriteRegBit(VOP_REG_WR, 0, BIT1);//8*32 tile format
3179 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, 0, VOP_REF_SELF_FLD);
3180
3181 g_pHalMVOPCtx->bIs422 = 0;// Clear 422 Flag
3182 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 0, EVD_ENABLE);// EVD mode disable
3183 g_pHalMVOPCtx->bIsH265 = 0;
3184 HAL_WriteRegBit(VOP_INT_TYPE, 0, VOP_EVD_INT_SEP);// Clear evd Flag for interlace mode setting
3185
3186 HAL_WriteRegBit(VOP_REG_MASK, 0, VOP_LSB_REQ_MASK);//10 bits bw control by vdec fw
3187 HAL_WriteRegBit(VOP_EVD_10B_EN, 0, VOP_EVD_10B_Y_EN);
3188 HAL_WriteRegBit(VOP_EVD_10B_EN, 0, VOP_EVD_10B_UV_EN);
3189 HAL_WriteRegBit(VOP_UV_SHIFT, 1, VOP_GCLK_MIU_ON);
3190
3191 HAL_WriteRegBit(VOP_REG_DUMMY, 1, VOP_420_BW_SAVE);
3192 HAL_WriteRegBit(VOP_REG_BW_SAVE, 1, VOP_420_BW_SAVE_EX);
3193 HAL_MVOP_LoadReg(); //kano patch, mantis: 0997677
3194 g_pHalMVOPCtx->bNewVSyncMode = FALSE;// Disable New Vsync Mode
3195
3196 /* only for STB DC */
3197 // Handshake mode chip need to set from MVD: Kappa (maybe fix in after project)
3198 HAL_MVOP_SetFDMaskFromMVD(ENABLE);
3199 // Use frame sync (CLK_DC1 domain) to reset CLK_DC0 and CLK_MIU domain every frame
3200 HAL_WriteRegBit(VOP_REG_FRAME_RST+1, 0, BIT7); // reg_frame_rst = 0
3201
3202 // Warning: set from tv, clippers HAL_MVOP_SetFieldInverse(ENABLE, DISABLE);
3203 HAL_MVOP_SetFieldInverse(ENABLE, ENABLE);
3204 // Warning: kappa U02 need to bypass field from mvd to xc for FCR.
3205 HAL_WriteRegBit(VOP_REG_DUMMY_3D_1, 1, VOP_RGB_FILED_BYPASS);
3206
3207 //Change MIU BW Default Value to 0x241C (after Einstein)
3208 //FIFO threshold
3209 HAL_WriteByte(VOP_DMA0, 0x08);
3210 //burst and priority
3211 HAL_WriteByte(VOP_DMA1, 0x22);
3212 HAL_WriteByte(VOP_BURST_CTRL0, 0x02);
3213 HAL_WriteByte(VOP_BURST_CTRL1, 0x00);
3214 // All codec use WISHBONE(R2) interface in muji
3215 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 1, VOP_R2_WISHBONE);
3216 // Disable 10 bits from codec
3217 HAL_WriteRegBit(VOP_INFO_FROM_CODEC_H, 0, VOP_INFO_FROM_CODEC_10BIT);
3218 //// clippers crop sw patch /////
3219 HAL_WriteRegBit(VOP_REG_SINGLE_3D_L, 0, VOP_FORCE_SKIP);
3220 HAL_WriteByteMask(VOP_REG_SINGLE_3D_L, 0, VOP_SKIP_SIZE_LVIEW);
3221 HAL_WriteByteMask(VOP_REG_SINGLE_3D_H, 0, VOP_SKIP_SIZE_RVIEW);
3222 HAL_WriteRegBit(VOP_REG_ENABLE_SKIP, 0, VOP_SKIP_LVIEW);
3223 HAL_WriteRegBit(VOP_REG_ENABLE_SKIP, 0, VOP_SKIP_RVIEW);
3224 g_pHalMVOPCtx->u16CropXStart = 0;
3225 g_pHalMVOPCtx->u16CropYStart = 0;
3226 g_pHalMVOPCtx->u16CropXSize = 0;
3227 g_pHalMVOPCtx->u16CropYSize = 0;
3228 g_pHalMVOPCtx->bIsSetCrop = FALSE;
3229 g_pHalMVOPCtx->u32MVOPFixClk = 0;
3230 // MIU select from WB
3231 HAL_WriteByteMask(VOP_INFO_FROM_CODEC_H, 0x30, VOP_INFO_FROM_CODEC_MIU_BUF0_SEL|VOP_INFO_FROM_CODEC_MIU_BUF1_SEL);
3232 HAL_WriteRegBit(VOP_UV_SHIFT, 0, VOP_GCLK_MIU_ON);// yc seperate can not enable
3233 g_pHalMVOPCtx->eInterlaceType = E_MVOP_PRO;
3234 HAL_WriteByte(VOP_REG_BLK_VCNT_L, 0x00);//mantis: 0986938
3235 HAL_WriteByteMask(VOP_REG_BLK_VCNT_H, 0x01, BIT0);
3236 HAL_WriteRegBit(VOP_INPUT_SWITCH0, 0, VOP_TILE_32x32);
3237 HAL_MVOP_LoadReg();
3238 /*****************************************************/
3239 break;
3240 }
3241 #if MVOP_SUPPORT_SUB
3242 case E_MVOP_DEV_1:
3243 {
3244 #if ENABLE_3D_LR_MODE
3245 HAL_MVOP_SubEnable3DLR(DISABLE);
3246 #endif
3247 #if SUPPORT_3DLR_ALT_SBS
3248 HAL_MVOP_SubSet3DLRAltOutput(DISABLE);
3249 HAL_MVOP_SubSet3DLRAltSBSOutput(DISABLE);
3250 #endif
3251 HAL_MVOP_SubEnableMVDInterface(FALSE);
3252
3253 /*****************************************************/
3254 // Reset MVOP setting
3255 HAL_WriteByteMask(SUB_REG(VOP_TST_IMG), 0x00, BIT2 | BIT1 | BIT0);//reset test pattern or BG
3256 HAL_WriteRegBit(SUB_REG(VOP_TST_IMG), BIT6, BIT6);//reset test pattern or BG
3257 HAL_MVOP_SubSetRgbFormat(E_MVOP_RGB_NONE);
3258 HAL_WriteRegBit(SUB_REG(VOP_CTRL1), 0, VOP_MVD_VS_MD); //default use original vsync
3259 //stb series: default hsk
3260 //HAL_WriteRegBit(SUB_REG(VOP_REG_422_OUT_EN), 1, BIT0); //kano ip2 444
3261 HAL_WriteRegBit(SUB_REG(VOP_HANDSHAKE), 1, VOP_HANDSHAKE_MODE);
3262 g_pHalMVOPCtx->bSubIsHS = TRUE;
3263 HAL_MVOP_SetTimingFromXC(E_MVOP_DEV_1, TRUE);
3264 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), ENABLE, VOP_HK_MASK); //default hsk mode bk background
3265 // Kano hsk default 2p
3266 HAL_MVOP_SubSetEnable4k2k2P(TRUE);
3267
3268 // Only for Monaco: Enable deciding bot by top address + 2
3269 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), 1, VOP_FIELD_FROM_ADDR);
3270 HAL_MVOP_SubSetMonoMode(FALSE);// Reset Mono mode
3271 HAL_MVOP_SubSetBlackBG();//set MVOP test pattern to black
3272 HAL_WriteRegBit(SUB_REG(VOP_REG_STRIP_ALIGN), 0, BIT0);// clear extend strip len bit by default
3273 HAL_WriteByteMask(SUB_REG(VOP_MIU_IF), VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);// set mvop to 128bit_i128 interface
3274 /* only for STB DC */
3275 HAL_MVOP_SubSetFDMaskFromMVD(ENABLE);
3276 // Use frame sync (CLK_DC1 domain) to reset CLK_DC0 and CLK_MIU domain every frame
3277 HAL_WriteRegBit(SUB_REG(VOP_REG_FRAME_RST+1), 0, BIT7); // reg_frame_rst = 0
3278
3279 // Warning: set from tv, clippers HAL_MVOP_SetFieldInverse(ENABLE, DISABLE);
3280 HAL_MVOP_SubSetFieldInverse(ENABLE, ENABLE);
3281 // Warning: kappa U02 need to bypass field from mvd to xc for FCR.
3282 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY_3D_1), 1, VOP_RGB_FILED_BYPASS);
3283
3284 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH1), 0, BIT2|BIT3);// Disable H264 or RM Input
3285 g_pHalMVOPCtx->bSubIs422 = 0;// Clear 422 Flag
3286 g_pHalMVOPCtx->bSubIsH265 = 0;// Clear evd Flag for interlace mode setting
3287 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 0, EVD_ENABLE);
3288 HAL_WriteRegBit(SUB_REG(VOP_INT_TYPE), 0, VOP_EVD_INT_SEP);
3289
3290 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT1);//8*32 tile format
3291 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD);
3292
3293 HAL_WriteRegBit(SUB_REG(VOP_REG_MASK), 0, VOP_LSB_REQ_MASK);//10 bits bw control by vdec fw
3294 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 0, VOP_EVD_10B_Y_EN);
3295 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 0, VOP_EVD_10B_UV_EN);
3296 // Disable 420 BW Saving mode
3297 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), 1, VOP_420_BW_SAVE);
3298 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), 1, VOP_420_BW_SAVE_EX);
3299 HAL_MVOP_SubLoadReg(); //kano patch, mantis: 0997677
3300 // VP9 MODE disable
3301 //HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 0, VOP_R2_WISHBONE);
3302 HAL_WriteRegBit(SUB_REG(VOP_MPG_JPG_SWITCH), 0, VOP_DRAM_RD_MODE);
3303
3304 g_pHalMVOPCtx->bSubNewVSyncMode = FALSE;// Disable New Vsync Mode
3305 HAL_WriteRegBit(SUB_REG(VOP_INFO_FROM_CODEC_H), 1, VOP_INFO_FROM_CODEC_DS_IDX);// Sub mvop ds idx from DIU
3306 // All codec use WISHBONE(R2) interface in muji
3307 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 1, VOP_R2_WISHBONE);
3308 // Disable 10 bits from codec
3309 HAL_WriteRegBit(SUB_REG(VOP_INFO_FROM_CODEC_H), 0, VOP_INFO_FROM_CODEC_10BIT);
3310 g_pHalMVOPCtx->u16SubCropXStart = 0;
3311 g_pHalMVOPCtx->u16CropYStart = 0;
3312 g_pHalMVOPCtx->u16CropXSize = 0;
3313 g_pHalMVOPCtx->u16CropYSize = 0;
3314 g_pHalMVOPCtx->bSubIsSetCrop = FALSE;
3315 g_pHalMVOPCtx->u32SubMVOPFixClk = 0;
3316 // MIU select from WB
3317 HAL_WriteByteMask(SUB_REG(VOP_INFO_FROM_CODEC_H), 0x30, VOP_INFO_FROM_CODEC_MIU_BUF0_SEL|VOP_INFO_FROM_CODEC_MIU_BUF1_SEL);
3318 HAL_WriteRegBit(SUB_REG(VOP_UV_SHIFT), 0, VOP_GCLK_MIU_ON);// yc seperate can not enable
3319 g_pHalMVOPCtx->eSubInterlaceType = E_MVOP_PRO;
3320 HAL_WriteByte(SUB_REG(VOP_REG_BLK_VCNT_L), 0x00);//mantis: 0986938
3321 HAL_WriteByteMask(SUB_REG(VOP_REG_BLK_VCNT_H), 0x01, BIT0);
3322 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 0, VOP_TILE_32x32);
3323 HAL_MVOP_SubLoadReg();
3324 /*****************************************************/
3325 break;
3326 }
3327 #endif
3328 default:
3329 MVOP_PRINTF("[%s] Input Device ID is Error!\n",__FUNCTION__);
3330 break;
3331 }
3332 }
3333
3334 /******************************************************************************/
3335 /// Set MVOP Handshake Mode, XC should be synchronous with MVOP.
3336 /// this command should be before mvop enable.(before 1st frame)
3337 /// kano hsk disable, xc gen timing need to disable.
3338 /******************************************************************************/
HAL_MVOP_SetHandShakeMode(MVOP_DevID eID,MS_BOOL bEnable,MS_U8 u8Framerate)3339 void HAL_MVOP_SetHandShakeMode(MVOP_DevID eID, MS_BOOL bEnable, MS_U8 u8Framerate)
3340 {
3341 switch(eID)
3342 {
3343 case E_MVOP_DEV_0:
3344 {
3345 if(!((bEnable == FALSE) && (g_pHalMVOPCtx->bIsHS == FALSE))) //prevent switch VOP_CTRL0 (mvop enable), for MHEG5 verify
3346 {
3347 MVOP_DBG(MVOP_PRINTF("[MVOP][DBG] HAL_MVOP_SetHandShakeMode = %d\n",bEnable);)
3348 HAL_WriteRegBit(VOP_CTRL0, 0, BIT0);
3349 g_pHalMVOPCtx->bIsHS = bEnable;
3350 HAL_WriteRegBit(VOP_HANDSHAKE, bEnable, VOP_HANDSHAKE_MODE);
3351 if(bEnable == FALSE)
3352 {
3353 HAL_MVOP_SetTimingFromXC(E_MVOP_DEV_0, FALSE);
3354 }
3355 HAL_WriteRegBit(VOP_CTRL0, bEnable, BIT4);
3356 HAL_WriteRegBit(VOP_MIRROR_CFG_HI, bEnable, VOP_HK_MASK); //bk background
3357 HAL_WriteRegBit(VOP_CTRL0, 1, BIT0);
3358 HAL_MVOP_LoadReg();
3359 }
3360 break;
3361 }
3362 case E_MVOP_DEV_1:
3363 {
3364 #if MVOP_SUPPORT_SUB
3365 if(!((bEnable == FALSE) && (g_pHalMVOPCtx->bSubIsHS == FALSE))) //prevent switch VOP_CTRL0 (mvop enable), for MHEG5 verify
3366 {
3367 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), 0, BIT0);
3368 g_pHalMVOPCtx->bSubIsHS = bEnable;
3369 HAL_WriteRegBit(SUB_REG(VOP_HANDSHAKE), bEnable, VOP_HANDSHAKE_MODE);
3370 if(bEnable == FALSE)
3371 {
3372 HAL_MVOP_SetTimingFromXC(E_MVOP_DEV_1, FALSE);
3373 }
3374 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), bEnable, BIT4);
3375 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), bEnable, VOP_HK_MASK); //bk background
3376 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), 1, BIT0);
3377 HAL_MVOP_SubLoadReg();
3378 }
3379 #endif
3380 break;
3381 }
3382 default:
3383 MVOP_PRINTF("[Warning] MVOP_DevID not support!\n");
3384 break;
3385 }
3386 }
3387
HAL_MVOP_SetCropforXC(MVOP_DevID eID,MVOP_XCGetCrop * stXCCrop,MS_U16 u16Width,MS_U16 u16Height)3388 void HAL_MVOP_SetCropforXC(MVOP_DevID eID, MVOP_XCGetCrop* stXCCrop, MS_U16 u16Width, MS_U16 u16Height)
3389 {
3390 MVOP_DBG(MVOP_PRINTF("%s [crop info] xst: 0x%x yst: 0x%x xsize: 0x%x ysize: 0x%x Width: 0x%x Height: 0x%x\n", __FUNCTION__,
3391 stXCCrop->u16XStart, stXCCrop->u16XSize, stXCCrop->u16YStart, stXCCrop->u16YSize, u16Width, u16Height);)
3392
3393 EN_MVOP_Output_3D_TYPE en3DType = E_MVOP_OUTPUT_3D_NONE;
3394
3395 switch(eID)
3396 {
3397 case E_MVOP_DEV_0:
3398 {
3399 if((stXCCrop->u16XStart + stXCCrop->u16XSize) > u16Width)
3400 {
3401 MVOP_PRINTF("[Warning] crop x size or start out of boundary.");
3402 return;
3403 }
3404
3405 if((stXCCrop->u16YStart + stXCCrop->u16YSize) > u16Height)
3406 {
3407 MVOP_PRINTF("[Warning] crop y size or start out of boundary.");
3408 return;
3409 }
3410
3411 g_pHalMVOPCtx->u16CropXStart = stXCCrop->u16XStart;
3412 en3DType = HAL_MVOP_GetOutput3DType();
3413 MVOP_DBG(MVOP_PRINTF("%s 3D FORMAT = %d\n", __FUNCTION__, en3DType);)
3414 if(en3DType == E_MVOP_OUTPUT_3D_SBS)
3415 {
3416 stXCCrop->u16XSize = stXCCrop->u16XSize >> 1;
3417 }
3418 g_pHalMVOPCtx->u16CropXSize = stXCCrop->u16XSize;
3419 g_pHalMVOPCtx->u16CropYStart = stXCCrop->u16YStart;
3420 if(stXCCrop->u16YStart == 0)
3421 stXCCrop->u16YStart |= 0x6000;
3422 else
3423 stXCCrop->u16YStart |= 0x2000;
3424
3425 if((en3DType == E_MVOP_OUTPUT_3D_TB) || (en3DType == E_MVOP_OUTPUT_3D_LA))
3426 {
3427 stXCCrop->u16YSize = stXCCrop->u16YSize >> 1;
3428 }
3429 g_pHalMVOPCtx->u16CropYSize = stXCCrop->u16YSize;
3430 break;
3431 }
3432 case E_MVOP_DEV_1:
3433 {
3434 #if MVOP_SUPPORT_SUB
3435
3436 if((stXCCrop->u16XStart + stXCCrop->u16XSize) > u16Width)
3437 {
3438 MVOP_PRINTF("[Warning] crop x size or start out of boundary.");
3439 return;
3440 }
3441
3442 if((stXCCrop->u16YStart + stXCCrop->u16YSize) > u16Height)
3443 {
3444 MVOP_PRINTF("[Warning] crop y size or start out of boundary.");
3445 return;
3446 }
3447
3448 g_pHalMVOPCtx->u16SubCropXStart = stXCCrop->u16XStart;
3449 en3DType = HAL_MVOP_SubGetOutput3DType();
3450 MVOP_DBG(MVOP_PRINTF("%s 3D FORMAT = %d\n", __FUNCTION__, en3DType);)
3451 if(en3DType == E_MVOP_OUTPUT_3D_SBS)
3452 {
3453 stXCCrop->u16XSize = stXCCrop->u16XSize >> 1;
3454 }
3455 g_pHalMVOPCtx->u16SubCropXSize = stXCCrop->u16XSize;
3456 g_pHalMVOPCtx->u16SubCropYStart = stXCCrop->u16YStart;
3457 if(stXCCrop->u16YStart == 0)
3458 stXCCrop->u16YStart |= 0x6000;
3459 else
3460 stXCCrop->u16YStart |= 0x2000;
3461
3462 if((en3DType == E_MVOP_OUTPUT_3D_TB) || (en3DType == E_MVOP_OUTPUT_3D_LA))
3463 {
3464 stXCCrop->u16YSize = stXCCrop->u16YSize >> 1;
3465 }
3466 g_pHalMVOPCtx->u16SubCropYSize = stXCCrop->u16YSize;
3467 #endif
3468 break;
3469 }
3470 default:
3471 MVOP_PRINTF("[Warning] MVOP_DevID not support!\n");
3472 break;
3473 }
3474 MVOP_PRINTF("[Debug][Crop to XC] xsize = %d, ysize = %d, xstart = %d, ystart=%d\n",stXCCrop->u16XSize,stXCCrop->u16YSize,stXCCrop->u16XStart,stXCCrop->u16YStart);
3475 return;
3476 }
3477
3478
3479
HAL_MVOP_SupportFRCOutputFPS(MVOP_DevID eID)3480 MS_BOOL HAL_MVOP_SupportFRCOutputFPS(MVOP_DevID eID)
3481 {
3482 MS_BOOL bRet = FALSE;
3483 switch(eID)
3484 {
3485 case E_MVOP_DEV_0:
3486 bRet = TRUE;
3487 break;
3488 #if MVOP_SUPPORT_SUB
3489 case E_MVOP_DEV_1:
3490 bRet = TRUE;
3491 break;
3492 #endif
3493 default:
3494 break;
3495 }
3496 return bRet;
3497 }
3498
HAL_MVOP_GetIsCurrentHSK(MVOP_DevID eID)3499 MS_BOOL HAL_MVOP_GetIsCurrentHSK(MVOP_DevID eID)
3500 {
3501 MS_BOOL bRet = FALSE;
3502 switch(eID)
3503 {
3504 case E_MVOP_DEV_0:
3505 bRet = g_pHalMVOPCtx->bIsHS;
3506 break;
3507 case E_MVOP_DEV_1:
3508 #if MVOP_SUPPORT_SUB
3509 bRet = g_pHalMVOPCtx->bSubIsHS;
3510 #endif
3511 break;
3512 default:
3513 bRet = E_MVOP_HS_INVALID_PARAM;
3514 break;
3515 }
3516 return bRet;
3517 }
3518
3519
HAL_MVOP_GetIsCurrentXCGenTiming(MVOP_DevID eID)3520 MS_BOOL HAL_MVOP_GetIsCurrentXCGenTiming(MVOP_DevID eID)
3521 {
3522 MS_BOOL bRet = FALSE;
3523 switch(eID)
3524 {
3525 case E_MVOP_DEV_0:
3526 bRet = g_pHalMVOPCtx->bIsXcTrig;
3527 break;
3528 case E_MVOP_DEV_1:
3529 #if MVOP_SUPPORT_SUB
3530 bRet = g_pHalMVOPCtx->bSubIsXcTrig;
3531 #endif
3532 break;
3533 default:
3534 bRet = E_MVOP_HS_INVALID_PARAM;
3535 break;
3536 }
3537 return bRet;
3538 }
3539
HAL_MVOP_SetFixClk(MVOP_DevID eID,MS_U32 u32MVOPClk)3540 HALMVOPFREQUENCY HAL_MVOP_SetFixClk(MVOP_DevID eID, MS_U32 u32MVOPClk)
3541 {
3542 HALMVOPFREQUENCY eRet = HALMVOP_160MHZ;
3543
3544 if(u32MVOPClk > HALMVOP_320MHZ*2)
3545 {
3546 MVOP_PRINTF("[Warning] MVOP clock out of spec(640MHz), set freerun mode.\n");
3547 eRet = HALMVOP_FREERUNMODE;
3548 }
3549 #if 0
3550 else if(u32MVOPClk <= HALMVOP_320MHZ*2 && u32MVOPClk > HALMVOP_320MHZ)
3551 {
3552 eRet = u32MVOPClk;
3553 }
3554 else if(u32MVOPClk <= HALMVOP_320MHZ && u32MVOPClk > HALMVOP_192MHZ)
3555 {
3556 eRet = u32MVOPClk;
3557 }
3558 #endif
3559 else if(u32MVOPClk <= HALMVOP_192MHZ && u32MVOPClk > HALMVOP_160MHZ)
3560 {
3561 eRet = HALMVOP_192MHZ;
3562 }
3563 else if(u32MVOPClk <= HALMVOP_160MHZ && u32MVOPClk > HALMVOP_144MHZ)
3564 {
3565 eRet = HALMVOP_160MHZ;
3566 }
3567 else if(u32MVOPClk <= HALMVOP_144MHZ && u32MVOPClk > HALMVOP_123MHZ)
3568 {
3569 eRet = HALMVOP_144MHZ;
3570 }
3571 else if(u32MVOPClk <= HALMVOP_123MHZ && u32MVOPClk > HALMVOP_108MHZ)
3572 {
3573 eRet = HALMVOP_123MHZ;
3574 }
3575 else
3576 {
3577 eRet = HALMVOP_108MHZ;
3578 }
3579
3580 MVOP_DBG(MVOP_PRINTF("[MVOP] MVOP clock set as %ld\n",eRet););
3581 if(eID == E_MVOP_DEV_0)
3582 {
3583 if(eRet > HALMVOP_192MHZ)
3584 {
3585 g_pHalMVOPCtx->u32MVOPFixClk = HAL_MVOP_GetMaximumClk();
3586 }
3587 else
3588 {
3589 g_pHalMVOPCtx->u32MVOPFixClk = eRet;
3590 }
3591 }
3592 #if MVOP_SUPPORT_SUB
3593 else if(eID == E_MVOP_DEV_1)
3594 {
3595 if(eRet > HALMVOP_192MHZ)
3596 {
3597 g_pHalMVOPCtx->u32SubMVOPFixClk = HAL_MVOP_GetMaximumClk();
3598 }
3599 else
3600 {
3601 g_pHalMVOPCtx->u32SubMVOPFixClk = eRet;
3602 }
3603 }
3604 #endif
3605 return eRet;
3606 }
3607
3608
3609 #if 0
3610 void HAL_SetSCFEMIUIPSel(MVOP_SCIPSel *stIPSel)
3611 {
3612 if(NULL == stIPSel)
3613 {
3614 HAL_WriteRegBit(REG_MIU_SEL_FROM_IP, 1, MVOP_MIU_IP_SEL); //mvop
3615 HAL_WriteRegBit(REG_MIU_SEL_FROM_IP, 1, MFDEC0_MIU_IP_SEL); //mfdec0
3616 HAL_WriteRegBit(REG_MIU_SEL_FROM_IP, 1, MFDEC1_MIU_IP_SEL); //mfdec1
3617 }
3618 else
3619 {
3620 HAL_WriteRegBit(REG_MIU_SEL_FROM_IP, stIPSel->bMVOP0, MVOP_MIU_IP_SEL); //mvop
3621 HAL_WriteRegBit(REG_MIU_SEL_FROM_IP, stIPSel->bMFDEC0, MFDEC0_MIU_IP_SEL); //mfdec0
3622 HAL_WriteRegBit(REG_MIU_SEL_FROM_IP, stIPSel->bMFDEC1, MFDEC1_MIU_IP_SEL); //mfdec1
3623 }
3624
3625 }
3626 #endif
3627
HAL_MVOP_SetInterlaceType(MVOP_DevID eDevID,MS_U16 u16ECONumber,MS_U8 u8Interlace)3628 void HAL_MVOP_SetInterlaceType(MVOP_DevID eDevID, MS_U16 u16ECONumber, MS_U8 u8Interlace)
3629 {
3630 MVOP_DBG(MVOP_PRINTF("%s u8Interlace = %d\n", __FUNCTION__ ,u8Interlace);)
3631 switch(u8Interlace)
3632 {
3633 case 0:
3634 g_pHalMVOPCtx->eInterlaceType = E_MVOP_PRO;
3635 break;
3636 case 0x1:
3637 if(g_pHalMVOPCtx->bIsH265)
3638 {
3639 g_pHalMVOPCtx->eInterlaceType = E_MVOP_INT_TB_SEP_FRAME;
3640 }
3641 else
3642 {
3643 g_pHalMVOPCtx->eInterlaceType = E_MVOP_INT_TB_ONE_FRAME;
3644 }
3645 break;
3646 case 0x2:
3647 if(g_pHalMVOPCtx->bIsH265)
3648 {
3649 g_pHalMVOPCtx->eInterlaceType = E_MVOP_INT_TB_ONE_FRAME;
3650 }
3651 else
3652 {
3653 g_pHalMVOPCtx->eInterlaceType = E_MVOP_INT_TB_SEP_FRAME;
3654 }
3655 break;
3656 default:
3657 g_pHalMVOPCtx->eInterlaceType = E_MVOP_PRO;
3658 break;
3659 }
3660
3661 switch(eDevID)
3662 {
3663 case E_MVOP_DEV_0:
3664 if((g_pHalMVOPCtx->eInterlaceType == E_MVOP_INT_TB_SEP_FRAME) && (g_pHalMVOPCtx->bIsH265))
3665 {
3666 HAL_WriteRegBit(VOP_INT_TYPE, 1, VOP_EVD_INT_SEP);
3667 }
3668 else if((g_pHalMVOPCtx->eInterlaceType == E_MVOP_INT_TB_ONE_FRAME) && (g_pHalMVOPCtx->bIsH265))
3669 {
3670 HAL_WriteRegBit(VOP_INT_TYPE, 0, VOP_EVD_INT_SEP);
3671 HAL_WriteRegBit(VOP_MIRROR_CFG, 0, VOP_FIELD_FROM_ADDR);
3672 }
3673 HAL_MVOP_LoadReg();
3674 break;
3675 #if MVOP_SUPPORT_SUB
3676 case E_MVOP_DEV_1:
3677 if((g_pHalMVOPCtx->eSubInterlaceType == E_MVOP_INT_TB_SEP_FRAME) && (g_pHalMVOPCtx->bSubIsH265))
3678 {
3679 HAL_WriteRegBit(SUB_REG(VOP_INT_TYPE), 1, VOP_EVD_INT_SEP);
3680 }
3681 else if((g_pHalMVOPCtx->eSubInterlaceType == E_MVOP_INT_TB_ONE_FRAME) && (g_pHalMVOPCtx->bSubIsH265))
3682 {
3683 HAL_WriteRegBit(SUB_REG(VOP_INT_TYPE), 0, VOP_EVD_INT_SEP);
3684 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), 0, VOP_FIELD_FROM_ADDR);
3685 }
3686 HAL_MVOP_SubLoadReg();
3687 break;
3688 #endif
3689 default:
3690 MVOP_PRINTF("[Warning][%s] MVOP_DevID not support\n",__FUNCTION__);
3691 break;
3692 }
3693 }
3694
3695 #ifdef UFO_MVOP_GET_IS_MVOP_AUTO_GEN_BLACK
HAL_MVOP_GetIsMVOPSupportBLKBackground(MVOP_DevID eID)3696 MS_BOOL HAL_MVOP_GetIsMVOPSupportBLKBackground(MVOP_DevID eID)
3697 {
3698 MS_BOOL bRet = FALSE;
3699 switch(eID)
3700 {
3701 case E_MVOP_DEV_0:
3702 bRet = FALSE;
3703 break;
3704 case E_MVOP_DEV_1:
3705 #if MVOP_SUPPORT_SUB
3706 bRet = FALSE;
3707 #endif
3708 break;
3709 default:
3710 bRet = E_MVOP_HS_INVALID_PARAM;
3711 break;
3712 }
3713 return bRet;
3714 }
3715 #endif
3716
HAL_MVOP_ReadBank(MVOP_DevID eID,MS_U16 u16Length)3717 MS_U16 HAL_MVOP_ReadBank(MVOP_DevID eID ,MS_U16 u16Length)
3718 {
3719 MS_U16 u16Reg = 0;
3720 if(eID == E_MVOP_DEV_0)
3721 {
3722 u16Reg = HAL_Read2Byte(MVOP_REG_BASE + (u16Length << 1));
3723 }
3724 #ifdef MVOP_SUPPORT_SUB
3725 else if(eID == E_MVOP_DEV_1)
3726 {
3727 u16Reg = HAL_Read2Byte(SUB_REG(MVOP_REG_BASE + (u16Length << 1)));
3728 }
3729 #endif
3730 return u16Reg;
3731 }
3732
HAL_MVOP_WriteBank(MVOP_DevID eID,MS_U16 u16Length,MS_U16 u16Data)3733 void HAL_MVOP_WriteBank(MVOP_DevID eID ,MS_U16 u16Length,MS_U16 u16Data)
3734 {
3735 if(eID == E_MVOP_DEV_0)
3736 {
3737 HAL_Write2Byte(MVOP_REG_BASE + (u16Length << 1),u16Data);
3738 }
3739 #ifdef MVOP_SUPPORT_SUB
3740 else if(eID == E_MVOP_DEV_1)
3741 {
3742 HAL_Write2Byte(SUB_REG(MVOP_REG_BASE + (u16Length << 1)),u16Data);
3743 }
3744 #endif
3745 }
3746
HAL_MVOP_ReadClkBank(MS_U16 u16Length)3747 MS_U16 HAL_MVOP_ReadClkBank(MS_U16 u16Length)
3748 {
3749 MS_U16 u16Reg = 0;
3750
3751 if(u16Length < 3) // stc cw
3752 {
3753 u16Reg = HAL_Read2Byte(REG_STC_CW_SLE_L + (u16Length << 1));
3754
3755 }
3756 else if(u16Length < 7) // dc clk
3757 {
3758 u16Length -= 3;
3759 u16Reg = HAL_Read2Byte(REG_CKG_DC0 + (u16Length << 1)); // main/sub sram
3760 }
3761 else // freerun/sync clk
3762 {
3763 u16Length -= 7;
3764 u16Reg = HAL_Read2Byte(REG_UPDATE_DC0_CW + (u16Length << 1));
3765 }
3766
3767 //printk("[read][%x] u16Reg = 0x%x\n",u16Length,u16Reg);
3768 return u16Reg;
3769 }
3770
HAL_MVOP_WriteClkBank(MS_U16 u16Length,MS_U16 u16Data)3771 void HAL_MVOP_WriteClkBank(MS_U16 u16Length,MS_U16 u16Data)
3772 {
3773
3774 //printk("[write][%x] u16Reg = 0x%x\n",u16Length,u16Data);
3775
3776 if(u16Length < 3) // stc cw
3777 {
3778 HAL_Write2Byte(REG_STC_CW_SLE_L + (u16Length << 1), u16Data);
3779 }
3780 else if(u16Length < 7) // dc clk
3781 {
3782 u16Length -= 3;
3783 HAL_Write2Byte(REG_CKG_DC0 + (u16Length << 1), u16Data);
3784 }
3785 else // freerun/sync clk
3786 {
3787 u16Length -= 7;
3788 HAL_Write2Byte(REG_UPDATE_DC0_CW + (u16Length << 1), u16Data);
3789 }
3790 HAL_WriteRegBit(REG_UPDATE_DC0_CW, TRUE, UPDATE_DC0_SYNC_CW);
3791 HAL_WriteRegBit(REG_UPDATE_DC0_CW, FALSE, UPDATE_DC0_SYNC_CW);
3792
3793 }
3794
HAL_MVOP_SetSramPower(MVOP_DevID eID,MS_BOOL bEnable)3795 void HAL_MVOP_SetSramPower(MVOP_DevID eID ,MS_BOOL bEnable)
3796 {
3797 switch(eID)
3798 {
3799 case E_MVOP_DEV_0:
3800 #if MVOP_SUPPORT_SUB
3801 if((bEnable== FALSE) && (g_pHalMVOPCtx->bIsSubEnable == FALSE)) //check sub disable -> mfdec sram disable
3802 {
3803 //HAL_WriteRegBit(VOP_DC_STRIP_H, 1, MFDEC_SRAM_SD_MASK);
3804 HAL_WriteRegBit(VOP_DC_STRIP_H, 1, VOP_SRAM_SD_MASK);
3805 }
3806 else
3807 {
3808 //HAL_WriteRegBit(VOP_DC_STRIP_H, 0, MFDEC_SRAM_SD_MASK);
3809 HAL_WriteRegBit(VOP_DC_STRIP_H, 0, VOP_SRAM_SD_MASK);
3810 }
3811 #else
3812 HAL_WriteRegBit(VOP_DC_STRIP_H, !bEnable, VOP_SRAM_SD_MASK);
3813 #endif
3814 break;
3815 #if MVOP_SUPPORT_SUB
3816 case E_MVOP_DEV_1:
3817 if((bEnable== FALSE) && (g_pHalMVOPCtx->bIsEnable == FALSE))
3818 {
3819 //HAL_WriteRegBit(VOP_DC_STRIP_H, 1, MFDEC_SRAM_SD_MASK);
3820 HAL_WriteRegBit(VOP_DC_STRIP_H, 1, VOP_SRAM_SD_MASK);
3821 HAL_WriteRegBit(SUB_REG(VOP_DC_STRIP_H), 1, VOP_SRAM_SD_MASK);
3822 }
3823 else
3824 {
3825 //HAL_WriteRegBit(VOP_DC_STRIP_H, 0, MFDEC_SRAM_SD_MASK);
3826 HAL_WriteRegBit(VOP_DC_STRIP_H, 0, VOP_SRAM_SD_MASK); //main need to enable, if sub enable.
3827 HAL_WriteRegBit(SUB_REG(VOP_DC_STRIP_H), 0, VOP_SRAM_SD_MASK);
3828 }
3829 break;
3830 #endif
3831 default:
3832 break;
3833 }
3834 return;
3835 }
3836
HAL_MVOP_Exit(MVOP_DevID eID)3837 void HAL_MVOP_Exit(MVOP_DevID eID)
3838 {
3839 switch(eID)
3840 {
3841 case E_MVOP_DEV_0:
3842 g_pHalMVOPCtx->bIsInit = 0;
3843 break;
3844 #if MVOP_SUPPORT_SUB
3845 case E_MVOP_DEV_1:
3846 g_pHalMVOPCtx->bSubIsInit = 0;
3847 break;
3848 #endif
3849 default:
3850 break;
3851 }
3852 return;
3853 }
3854
HAL_MVOP_UVSwapEnable(MVOP_DevID eID,MS_BOOL bEnable)3855 void HAL_MVOP_UVSwapEnable(MVOP_DevID eID, MS_BOOL bEnable)
3856 {
3857 switch(eID)
3858 {
3859 case E_MVOP_DEV_0:
3860 HAL_WriteRegBit(VOP_TST_IMG, bEnable, VOP_UV_SWAP);
3861 break;
3862 #if MVOP_SUPPORT_SUB
3863 case E_MVOP_DEV_1:
3864 HAL_WriteRegBit(SUB_REG(VOP_TST_IMG), bEnable, VOP_UV_SWAP);
3865 break;
3866 #endif
3867 default:
3868 break;
3869 }
3870 return;
3871 }
3872
HAL_MVOP_SetECONumber(MS_U16 u16ECOVersion)3873 void HAL_MVOP_SetECONumber(MS_U16 u16ECOVersion)
3874 {
3875 if (g_pHalMVOPCtx == NULL)
3876 {
3877 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
3878 return;
3879 }
3880 g_pHalMVOPCtx->u16ECONum = u16ECOVersion;
3881 }
3882
3883 /////////////////////// Sub MVOP ////////////////////////
3884 #if MVOP_SUPPORT_SUB
HAL_MVOP_SubRegSetBase(MS_VIRT u32Base)3885 void HAL_MVOP_SubRegSetBase(MS_VIRT u32Base)
3886 {
3887 u32RiuBaseAdd = u32Base;
3888 }
3889
HAL_MVOP_SubInitMirrorMode(MS_BOOL bMir)3890 void HAL_MVOP_SubInitMirrorMode(MS_BOOL bMir)
3891 {
3892 //set bit[3:7] to support mirror mode
3893 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), bMir, VOP_MIRROR_CFG_ENABLE);
3894 }
3895
HAL_MVOP_SubInit(void)3896 void HAL_MVOP_SubInit(void)
3897 {
3898 MVOP_HalInitCtxResults eRet;
3899 MS_BOOL pbFirstDrvInstant;
3900
3901 eRet = _HAL_MVOP_InitContext(&pbFirstDrvInstant);
3902 if(eRet == E_MVOP_INIT_FAIL)
3903 {
3904 MVOP_DBG(MVOP_PRINTF("[%s] MVOP Context Init failed!\n",__FUNCTION__);)
3905 return;
3906 }
3907 else if(eRet == E_MVOP_INIT_ALREADY_EXIST)
3908 {
3909 if(g_pHalMVOPCtx->bSubIsInit)
3910 {
3911 MVOP_DBG(MVOP_PRINTF("[%s] Sub MVOP Context has Initialized!\n",__FUNCTION__);)
3912 return;
3913 }
3914 }
3915 HAL_MVOP_SubInitMirrorMode(TRUE);
3916 //Enable dynamic clock gating
3917 //Note: cannot enable VOP_GCLK_VCLK_ON, or hsync cannot be sent out.
3918 HAL_WriteByteMask(SUB_REG(VOP_GCLK), VOP_GCLK_MIU_ON, VOP_GCLK_MIU_ON|VOP_GCLK_VCLK_ON);
3919 g_pHalMVOPCtx->bSubIsInit = 1;
3920 }
HAL_MVOP_SubSetVerticalMirrorMode(MS_BOOL bEnable)3921 void HAL_MVOP_SubSetVerticalMirrorMode(MS_BOOL bEnable)
3922 {
3923 if (g_pHalMVOPCtx == NULL)
3924 {
3925 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
3926 return;
3927 }
3928 if (VOP_MIRROR_CFG_ENABLE != HAL_ReadRegBit(SUB_REG(VOP_MIRROR_CFG), VOP_MIRROR_CFG_ENABLE))
3929 {
3930 //MVOP_PRINTF("Setup mirror mode\n");
3931 HAL_MVOP_SubInitMirrorMode(TRUE);
3932 }
3933
3934 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), bEnable, VOP_MIRROR_CFG_VEN);
3935 g_pHalMVOPCtx->bSubMirrorModeVer = bEnable;
3936 }
3937
HAL_MVOP_SubSetHorizontallMirrorMode(MS_BOOL bEnable)3938 void HAL_MVOP_SubSetHorizontallMirrorMode(MS_BOOL bEnable)
3939 {
3940 if (g_pHalMVOPCtx == NULL)
3941 {
3942 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
3943 return;
3944 }
3945 if (VOP_MIRROR_CFG_ENABLE != HAL_ReadRegBit(SUB_REG(VOP_MIRROR_CFG), VOP_MIRROR_CFG_ENABLE))
3946 {
3947 //MVOP_PRINTF("Setup mirror mode\n");
3948 HAL_MVOP_SubInitMirrorMode(TRUE);
3949 }
3950
3951 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), bEnable, VOP_MIRROR_CFG_HEN);
3952 g_pHalMVOPCtx->bSubMirrorModeHor = bEnable;
3953 }
3954
HAL_MVOP_SubSetFieldInverse(MS_BOOL b2MVD,MS_BOOL b2IP)3955 void HAL_MVOP_SubSetFieldInverse(MS_BOOL b2MVD, MS_BOOL b2IP)
3956 {
3957 // Set fld inv & ofld_inv
3958 HAL_WriteRegBit(SUB_REG(VOP_CTRL0+1), b2MVD, BIT3); //inverse the field to MVD
3959 HAL_WriteRegBit(SUB_REG(VOP_CTRL0+1), b2IP, BIT4); //inverse the field to IP
3960 }
3961
HAL_MVOP_SubSetChromaWeighting(MS_BOOL bEnable)3962 void HAL_MVOP_SubSetChromaWeighting(MS_BOOL bEnable)
3963 {
3964 HAL_WriteRegBit(SUB_REG(VOP_REG_WEIGHT_CTRL), bEnable, BIT1);
3965 }
3966
3967 //load new value into active registers 0x20-0x26
HAL_MVOP_SubLoadReg(void)3968 void HAL_MVOP_SubLoadReg(void)
3969 {
3970 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT0);
3971 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT0);
3972
3973 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT4);
3974 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT4);
3975 }
3976
HAL_MVOP_SubSetMIUReqMask(MS_BOOL bEnable)3977 void HAL_MVOP_SubSetMIUReqMask(MS_BOOL bEnable)
3978 {
3979 #if 0
3980 if (bEnable)
3981 { // mask MVOP2MI to protect MIU
3982 HAL_MIU_SubSetReqMask(SUBMVOP_R, 1);
3983 MsOS_DelayTask(1);
3984 }
3985 else
3986 { // unmask MVOP2MI
3987 MsOS_DelayTask(1);
3988 HAL_MIU_SubSetReqMask(SUBMVOP_R, 0);
3989 }
3990 #endif
3991 MS_U8 u8Miu;
3992 if(HAL_MVOP_GetIsOnlyMiuIPControl() == TRUE)
3993 {
3994 // mask msb mvop
3995 u8Miu = (HAL_ReadByte(SUB_REG(VOP_MIU_SEL)) & VOP_MSB_BUF0_MIU_SEL) >> 4;
3996 }
3997 else
3998 {
3999 u8Miu = SUBVOP_ON_MIU1;
4000 }
4001 eMIUClientID eClientID = MIU_CLIENT_MVOP1_R;
4002 //MVOP_PRINTF("Enter %s bEnable=%x ReqMask=0x%x, 0x%x, u8Miu=%x\n", __FUNCTION__, bEnable,
4003 // HAL_ReadByte(0x1266), HAL_ReadByte(0x0666), u8Miu);
4004
4005 if (bEnable)
4006 { // mask MVOP2MI to protect MIU
4007 MDrv_MIU_MaskReq(u8Miu, eClientID);
4008 MsOS_DelayTask(1);
4009 }
4010 else
4011 { // unmask MVOP2MI
4012 MsOS_DelayTask(1);
4013 MDrv_MIU_UnMaskReq(u8Miu, eClientID);
4014 }
4015
4016 //MVOP_PRINTF(">Exit %s bEnable=%x ReqMask=0x%x, 0x%x, u8Miu=%x\n", __FUNCTION__, bEnable,
4017 // HAL_ReadByte(0x1266), HAL_ReadByte(0x0666), u8Miu);
4018 }
4019
HAL_MVOP_SubRst(void)4020 void HAL_MVOP_SubRst(void)
4021 {
4022 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), 0, BIT0);
4023 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), 1, BIT0);
4024
4025 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), 0, BIT4);
4026 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), 1, BIT4);
4027
4028 g_pHalMVOPCtx->bIsSubEnable = 1;
4029 }
4030
HAL_MVOP_SubEnable(MS_BOOL bEnable,MS_U8 u8Framerate)4031 void HAL_MVOP_SubEnable(MS_BOOL bEnable, MS_U8 u8Framerate)
4032 {
4033 MS_U8 regval;
4034
4035 regval = HAL_ReadByte(SUB_REG(VOP_CTRL0));
4036
4037 if ( bEnable )
4038 {
4039 regval |= 0x1;
4040 }
4041 else
4042 {
4043 regval &= ~0x1;
4044 }
4045
4046 g_pHalMVOPCtx->bIsSubEnable = bEnable;
4047
4048 HAL_WriteByte(SUB_REG(VOP_CTRL0), regval);
4049 }
4050
HAL_MVOP_SubGetEnableState(void)4051 MS_BOOL HAL_MVOP_SubGetEnableState(void)
4052 {
4053 return (HAL_ReadRegBit(SUB_REG(VOP_CTRL0), BIT0));
4054 }
4055
HAL_MVOP_SubGetMaxFreerunClk()4056 HALMVOPFREQUENCY HAL_MVOP_SubGetMaxFreerunClk()
4057 {
4058 return HALMVOP_160MHZ;
4059 }
4060
HAL_MVOP_SubGet4k2kClk(void)4061 HALMVOPFREQUENCY HAL_MVOP_SubGet4k2kClk(void)
4062 {
4063 return HALMVOP_NOT_SUPPORT;
4064 }
4065
4066 //FIXME
HAL_MVOP_SubSetFrequency(HALMVOPFREQUENCY enFrequency)4067 void HAL_MVOP_SubSetFrequency(HALMVOPFREQUENCY enFrequency)
4068 {
4069 // clear
4070 HAL_WriteByteMask(REG_CKG_SUB_DC0, 0, CKG_SUB_DC0_MASK);
4071 switch(enFrequency)
4072 {
4073 case HALMVOP_SYNCMODE:
4074 HAL_WriteByteMask(REG_CKG_SUB_DC0, CKG_SUB_DC0_SYNCHRONOUS, CKG_SUB_DC0_MASK);
4075 break;
4076 case HALMVOP_FREERUNMODE:
4077 HAL_WriteByteMask(REG_CKG_SUB_DC0, CKG_SUB_DC0_FREERUN, CKG_SUB_DC0_MASK);
4078 break;
4079 case HALMVOP_320MHZ:
4080 //K6LITE not support 4k2k
4081 //HAL_WriteByteMask(REG_CKG_SUB_DC0, CKG_SUB_DC0_320MHZ, CKG_SUB_DC0_MASK);
4082 MVOP_PRINTF("Attention! not support 320MHz!\n");
4083 break;
4084 case HALMVOP_108MHZ:
4085 HAL_WriteByteMask(REG_CKG_SUB_DC0, CKG_SUB_DC0_108MHZ, CKG_SUB_DC0_MASK);
4086 break;
4087 case HALMVOP_123MHZ:
4088 HAL_WriteByteMask(REG_CKG_SUB_DC0, CKG_SUB_DC0_123MHZ, CKG_SUB_DC0_MASK);
4089 break;
4090 case HALMVOP_144MHZ:
4091 HAL_WriteByteMask(REG_CKG_SUB_DC0, CKG_SUB_DC0_144MHZ, CKG_SUB_DC0_MASK);
4092 break;
4093 case HALMVOP_160MHZ:
4094 HAL_WriteByteMask(REG_CKG_SUB_DC0, CKG_SUB_DC0_160MHZ, CKG_SUB_DC0_MASK);
4095 break;
4096 case HALMVOP_192MHZ:
4097 HAL_WriteByteMask(REG_CKG_SUB_DC0, CKG_SUB_DC0_192MHZ, CKG_SUB_DC0_MASK);
4098 break;
4099 default:
4100 HAL_WriteByteMask(REG_CKG_SUB_DC0, CKG_SUB_DC0_160MHZ, CKG_SUB_DC0_MASK);
4101 MVOP_PRINTF("Attention! In HAL_MVOP_SetFrequency default 160MHz!\n");
4102 break;
4103 }
4104 }
4105
HAL_MVOP_SubSetOutputInterlace(MS_BOOL bEnable,MS_U16 u16ECOVersion)4106 void HAL_MVOP_SubSetOutputInterlace(MS_BOOL bEnable, MS_U16 u16ECOVersion)
4107 {
4108 MS_U8 regval;
4109
4110 regval = HAL_ReadByte(SUB_REG(VOP_CTRL0));
4111
4112 if ( bEnable )
4113 {
4114 regval |= 0x80;
4115 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), 0, VOP_420_BW_SAVE_EX);
4116 }
4117 else
4118 {
4119 regval &= ~0x80;
4120 }
4121
4122 //Kano patch for GOP
4123 HAL_WriteRegBit(SUB_REG(VOP_TST_IMG), bEnable, VOP_SC_VS_INV);
4124 HAL_WriteByte(SUB_REG(VOP_CTRL0), regval);
4125 }
4126
HAL_MVOP_SubSetPattern(MVOP_Pattern enMVOPPattern)4127 void HAL_MVOP_SubSetPattern(MVOP_Pattern enMVOPPattern)
4128 {
4129 HAL_WriteByteMask(SUB_REG(VOP_TST_IMG), enMVOPPattern, BIT2 | BIT1 | BIT0);
4130 }
4131
HAL_MVOP_SubSetTileFormat(MVOP_TileFormat eTileFmt)4132 MS_BOOL HAL_MVOP_SubSetTileFormat(MVOP_TileFormat eTileFmt)
4133 {
4134 if (eTileFmt == E_MVOP_TILE_8x32)
4135 {
4136 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT1);
4137 return TRUE;
4138 }
4139 else if (eTileFmt == E_MVOP_TILE_16x32)
4140 {
4141 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT1);
4142 return TRUE;
4143 }
4144 else if (eTileFmt == E_MVOP_TILE_32x16)
4145 {
4146 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT1);
4147 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 1, EVD_ENABLE);
4148 return TRUE;
4149 }
4150 else if (eTileFmt == E_MVOP_TILE_32x32)
4151 {
4152 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT1);
4153 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 0, EVD_ENABLE);
4154 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 1, VOP_TILE_32x32);
4155 return TRUE;
4156 }
4157 else
4158 {
4159 return FALSE;
4160 }
4161 }
4162
HAL_MVOP_SubSetRgbFormat(MVOP_RgbFormat eRgbFmt)4163 MS_BOOL HAL_MVOP_SubSetRgbFormat(MVOP_RgbFormat eRgbFmt)
4164 {
4165 MS_BOOL bRet = FALSE;
4166
4167 if (g_pHalMVOPCtx == NULL)
4168 {
4169 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
4170 return FALSE;
4171 }
4172 if (eRgbFmt == E_MVOP_RGB_NONE)
4173 {
4174 HAL_WriteByteMask(SUB_REG(VOP_RGB_FMT), 0, VOP_RGB_FMT_SEL);
4175 bRet = TRUE;
4176 }
4177 else if (eRgbFmt == E_MVOP_RGB_565)
4178 {
4179 HAL_WriteByteMask(SUB_REG(VOP_RGB_FMT), VOP_RGB_FMT_565, VOP_RGB_FMT_SEL);
4180 bRet = TRUE;
4181 }
4182 else if (eRgbFmt == E_MVOP_RGB_888)
4183 {
4184 HAL_WriteByteMask(SUB_REG(VOP_RGB_FMT), VOP_RGB_FMT_888, VOP_RGB_FMT_SEL);
4185 bRet = TRUE;
4186 }
4187
4188 if (bRet == TRUE)
4189 {
4190 g_pHalMVOPCtx->eSubRgbFmt = eRgbFmt;
4191 }
4192 return bRet;
4193 }
4194
HAL_MVOP_SubSetBlackBG(void)4195 void HAL_MVOP_SubSetBlackBG(void)
4196 {
4197 MS_U8 regval;
4198
4199 //set MVOP test pattern to black
4200 HAL_WriteByte(SUB_REG(VOP_TST_IMG + 1), 0x10);
4201 HAL_WriteByte(SUB_REG(VOP_U_PAT ), 0x80);
4202 HAL_WriteByte(SUB_REG(VOP_U_PAT + 1), 0x80);
4203
4204 regval = HAL_ReadByte(SUB_REG(VOP_TST_IMG));
4205 HAL_WriteByteMask(SUB_REG(VOP_TST_IMG), 0x02, BIT2 | BIT1 | BIT0);
4206 HAL_WriteByteMask(SUB_REG(VOP_TST_IMG), 0x00, BIT2 | BIT1 | BIT0);
4207 HAL_WriteByteMask(SUB_REG(VOP_TST_IMG), regval, BIT2 | BIT1 | BIT0);
4208 }
4209
HAL_MVOP_SubSetCropWindow(MVOP_InputCfg * pparam)4210 void HAL_MVOP_SubSetCropWindow(MVOP_InputCfg *pparam)
4211 {
4212 #if 1
4213 UNUSED(pparam);
4214 #else // enable it when test code is ready
4215 MS_U32 x, y;
4216 MS_U32 u32offset;
4217
4218 if(!pparam)
4219 {
4220 return;
4221 }
4222 //set MVOP test pattern to black
4223 HAL_MVOP_SubSetBlackBG();
4224 #if 0
4225 if((pparam->enVideoType == MVOP_H264) && (pparam->u16StripSize == 1920))
4226 {
4227 pparam->u16StripSize = 1952;
4228 }
4229 #endif
4230 if((pparam->enVideoType == MVOP_MPG) || (pparam->enVideoType == MVOP_MPEG4))
4231 {
4232 pparam->u16CropX = (pparam->u16CropX >> 3) << 3; // 8 bytes align
4233 pparam->u16CropY = (pparam->u16CropY >> 6) << 6; // 64 bytes align
4234 }
4235 else if((pparam->enVideoType == MVOP_H264) || (pparam->enVideoType == MVOP_RM))
4236 {
4237 pparam->u16CropX = (pparam->u16CropX >> 4) << 4; // 16 bytes align
4238 pparam->u16CropY = (pparam->u16CropY >> 6) << 6; // 64 bytes align
4239 }
4240 else
4241 {
4242 MS_ASSERT(0);
4243 }
4244
4245 x = (MS_U32)pparam->u16CropX;
4246 y = (MS_U32)pparam->u16CropY;
4247
4248 // y offset
4249 u32offset = ((y * pparam->u16StripSize + (x << 5)) >> 3);
4250 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L ), (MS_U8)(u32offset));
4251 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L + 1), (MS_U8)(u32offset >> 8));
4252 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_H ), (MS_U8)(u32offset >> 16));
4253 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_H + 1), (MS_U8)((u32offset >> 24) & VOP_YUV_STR_HIBITS));
4254
4255 // uv offset
4256 u32offset = ((y >> 1) * pparam->u16StripSize + (x << 5)) >> 3;
4257 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L ), (MS_U8)(u32offset));
4258 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L + 1), (MS_U8)(u32offset >> 8));
4259 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_H ), (MS_U8)(u32offset >> 16));
4260 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_H + 1), (MS_U8)((u32offset >> 24) & VOP_YUV_STR_HIBITS));
4261
4262 pparam->u16CropWidth= (pparam->u16CropWidth >> 3) << 3;
4263 // HSize, VSize
4264 HAL_WriteByte(SUB_REG(VOP_JPG_HSIZE ), LOWBYTE(pparam->u16CropWidth ));
4265 HAL_WriteByte(SUB_REG(VOP_JPG_HSIZE + 1), HIGHBYTE(pparam->u16CropWidth ));
4266 HAL_WriteByte(SUB_REG(VOP_JPG_VSIZE ), LOWBYTE(pparam->u16CropHeight));
4267 HAL_WriteByte(SUB_REG(VOP_JPG_VSIZE + 1), HIGHBYTE(pparam->u16CropHeight ));
4268
4269 HAL_WriteByteMask(SUB_REG(VOP_MPG_JPG_SWITCH), BIT0, BIT1|BIT0);
4270
4271 // clear extend strip len bit by default
4272 HAL_WriteRegBit(SUB_REG(VOP_REG_STRIP_ALIGN), 0, BIT0);
4273 if((pparam->enVideoType == MVOP_MPG) || (pparam->enVideoType == MVOP_MPEG4))
4274 {
4275 // Disable H264 or RM Input
4276 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH), 0, BIT2|BIT3);
4277 //8*32 tile format
4278 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT1);
4279 }
4280 else if((pparam->enVideoType == MVOP_H264) || (pparam->enVideoType == MVOP_RM))
4281 {
4282 //16*32 tile format
4283 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT1);
4284 // SVD mode enable
4285 HAL_WriteByteMask(SUB_REG(VOP_INPUT_SWITCH), BIT3, BIT2|BIT3);
4286 // set mvop to 128bit_i128 interface
4287 HAL_WriteByteMask(SUB_REG(VOP_MIU_IF), VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
4288 }
4289 HAL_MVOP_SubLoadReg();
4290 #endif
4291 }
4292
HAL_MVOP_SubSetRepeatField(MVOP_RptFldMode eMode)4293 void HAL_MVOP_SubSetRepeatField(MVOP_RptFldMode eMode)
4294 {
4295 if (g_pHalMVOPCtx == NULL)
4296 {
4297 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
4298 return;
4299 }
4300 g_pHalMVOPCtx->eSubRepeatField = eMode;
4301 }
4302
HAL_MVOP_SubSetFDMaskFromMVD(MS_BOOL bEnable)4303 void HAL_MVOP_SubSetFDMaskFromMVD(MS_BOOL bEnable)
4304 {
4305 HAL_WriteRegBit(SUB_REG(VOP_REG_FD_MASK_SEL), bEnable, BIT5); //FD MASK from MVD
4306 }
4307
HAL_MVOP_SubSetInputMode(VOPINPUTMODE mode,MVOP_InputCfg * pparam,MS_U16 u16ECOVersion)4308 void HAL_MVOP_SubSetInputMode( VOPINPUTMODE mode, MVOP_InputCfg *pparam, MS_U16 u16ECOVersion )
4309 {
4310 MS_U8 regval;
4311 MS_U16 u16strip, u16strip_lsb;
4312
4313 if (g_pHalMVOPCtx == NULL)
4314 {
4315 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
4316 return;
4317 }
4318
4319 #if 0
4320 /*****************************************************/
4321 // Reset MVOP setting
4322 HAL_WriteByte(SUB_REG(VOP_TST_IMG), 0x40);
4323 HAL_MVOP_SubSetRgbFormat(E_MVOP_RGB_NONE);
4324 HAL_WriteRegBit(SUB_REG(VOP_CTRL1), 0, VOP_MVD_VS_MD); //default use original vsync
4325 // Only for Monaco: Enable deciding bot by top address + 2
4326 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), 1, VOP_FIELD_FROM_ADDR);
4327
4328 //set MVOP test pattern to black
4329 HAL_MVOP_SubSetBlackBG();
4330
4331 //regval = HAL_ReadByte(SUB_REG(VOP_MPG_JPG_SWITCH);
4332 regval = 0;
4333 regval |= ( mode & 0x3 );
4334
4335 // clear extend strip len bit by default
4336 HAL_WriteRegBit(SUB_REG(VOP_REG_STRIP_ALIGN), 0, BIT0);
4337
4338 // set mvop to 128bit_i128 interface
4339 HAL_WriteByteMask(SUB_REG(VOP_MIU_IF), VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
4340
4341 // Disable H264 or RM Input
4342 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH), 0, BIT2|BIT3);
4343 //8*32 tile format
4344 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 0, BIT1);
4345 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 0, VOP_REF_SELF_FLD);
4346 HAL_MVOP_SubSetFieldInverse(ENABLE, ENABLE);
4347 #endif
4348 regval = 0;
4349 regval |= ( mode & 0x3 );
4350
4351 if ( mode == VOPINPUT_HARDWIRE )
4352 {
4353 HAL_WriteByte(SUB_REG(VOP_MPG_JPG_SWITCH), regval);
4354 }
4355 else if ( mode == VOPINPUT_HARDWIRECLIP )
4356 {
4357 HAL_WriteByte(SUB_REG(VOP_MPG_JPG_SWITCH), regval);
4358
4359 // HSize, VSize
4360 HAL_WriteByte(SUB_REG(VOP_JPG_HSIZE ), LOWBYTE( pparam->u16HSize ));
4361 HAL_WriteByte(SUB_REG(VOP_JPG_HSIZE + 1), HIGHBYTE( pparam->u16HSize ));
4362 HAL_WriteByte(SUB_REG(VOP_JPG_VSIZE ), LOWBYTE( pparam->u16VSize ));
4363 HAL_WriteByte(SUB_REG(VOP_JPG_VSIZE + 1), HIGHBYTE( pparam->u16VSize ));
4364 }
4365 else if (mode == VOPINPUT_MCUCTRL)
4366 {
4367 g_pHalMVOPCtx->bSubMirrorMode = (g_pHalMVOPCtx->bSubMirrorModeVer||g_pHalMVOPCtx->bSubMirrorModeHor);
4368 if ( pparam->bProgressive )
4369 regval |= 0x4;
4370 else
4371 {
4372 regval &= ~0x4;
4373 regval |= 0x1; //reg_dc_md=b'11 for interlace input
4374 if (E_MVOP_RPTFLD_NONE == g_pHalMVOPCtx->eSubRepeatField)
4375 {
4376 MVOP_DBG("%s normal NOT repeat field %x\n", __FUNCTION__, g_pHalMVOPCtx->eSubRepeatField);
4377 //To support mcu mode interlace, need to set h'3B[9]=1,
4378 //h'11[12]=0, and Y1/UV1 address equal to Y0/UV0 address.
4379 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG_HI), 1, VOP_REF_SELF_FLD);
4380 //HAL_MVOP_SubSetFieldInverse(ENABLE, DISABLE); //do not inverse in kano: mvop gen timing + hsk mode
4381 // mheg5, mcu mode for i mode, do not bypass, 0x11[6] = 0: mvop t/b toggle
4382 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY_3D_1), 0, VOP_RGB_FILED_BYPASS);
4383 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), 0, VOP_EXTFLD_EN);
4384 }
4385 }
4386 // disable from wb
4387 //HAL_WriteRegBit(SUB_REG(VOP_REG_MFDEC_2_L), 0, VOP_MF_FROM_WB);
4388 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 0, VOP_R2_WISHBONE);
4389 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), 0, VOP_32x32_WB);
4390
4391 if ( pparam->bYUV422 )
4392 regval |= 0x10;
4393 else
4394 regval &= ~0x10;
4395
4396 if ( pparam->b422pack )
4397 regval |= 0x80;
4398
4399 if ( pparam->bDramRdContd == 1 )
4400 regval |= 0x20;
4401 else
4402 regval &= ~0x20;
4403
4404 // for backward compatable to saturn
4405 // [3] UV-7bit mode don't care
4406 // [5] dram_rd_md =0
4407 // [6] Fld don't care
4408 // [7] 422pack don'care
4409 HAL_WriteByte(SUB_REG(VOP_MPG_JPG_SWITCH), regval);
4410 g_pHalMVOPCtx->bSubIs422 = pparam->bYUV422;
4411 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), !pparam->bYUV422, VOP_420_BW_SAVE);
4412 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), !pparam->bYUV422, VOP_420_BW_SAVE_EX);
4413
4414 if (pparam->u16StripSize == 0)
4415 {
4416 if (pparam->bSD)
4417 {
4418 u16strip = 720;
4419 u16strip_lsb = 720;
4420 }
4421 else
4422 {
4423 u16strip = 1920;
4424 u16strip_lsb = 1920;
4425 }
4426 }
4427 else
4428 {
4429 u16strip = pparam->u16StripSize;
4430 u16strip_lsb = pparam->u16StripSize;
4431 }
4432
4433 // set dc_strip[7:0]
4434 if (pparam->bDramRdContd == 0)
4435 {
4436 u16strip = (u16strip + 31) / 32 * 32; //need align for monaco
4437 u16strip = u16strip/8;
4438 u16strip_lsb = (u16strip_lsb+127)/128;
4439 u16strip_lsb *= 4;
4440 }
4441 else
4442 {
4443 if ( pparam->b422pack )
4444 {
4445 if (E_MVOP_RGB_888 == g_pHalMVOPCtx->eSubRgbFmt)
4446 {
4447 u16strip *= 2;
4448 }
4449
4450 if ((u16strip < 1024) || g_pHalMVOPCtx->bSubMirrorMode)
4451 {
4452 u16strip = u16strip/4;
4453 // dont extend strip len
4454 HAL_WriteRegBit(SUB_REG(VOP_REG_STRIP_ALIGN), 0, BIT0);
4455 }
4456 else
4457 {
4458 u16strip = u16strip/8;
4459 // extend strip len to 2048
4460 HAL_WriteRegBit(SUB_REG(VOP_REG_STRIP_ALIGN), 1, BIT0);
4461 }
4462 }
4463 else
4464 {
4465 u16strip = u16strip/8;
4466 }
4467 }
4468
4469 if (u16strip >= 256 )
4470 {
4471 HAL_WriteByte(SUB_REG(VOP_DC_STRIP_H), (u16strip>>8));
4472 //reg_dc_strip_h[2:0] = reg_dc_strip[10:8]
4473 }
4474 else
4475 {
4476 HAL_WriteByteMask(SUB_REG(VOP_DC_STRIP_H), 0, BIT0 | BIT1 | BIT2);
4477 }
4478
4479 regval = u16strip;
4480 HAL_WriteByte(SUB_REG(VOP_DC_STRIP), regval);
4481 //LSB strip
4482 HAL_WriteByte(SUB_REG(VOP_DC_STRIP_LSB), u16strip_lsb & 0x3ff);
4483
4484 HAL_MVOP_SubSetYUVBaseAdd(pparam->u32YOffset, pparam->u32UVOffset,
4485 pparam->bProgressive, pparam->b422pack);
4486
4487 if (E_MVOP_RPTFLD_NONE != g_pHalMVOPCtx->eSubRepeatField)
4488 {
4489 MVOP_DBG("%s reset eRepeatField=%x ==>", __FUNCTION__, g_pHalMVOPCtx->eSubRepeatField);
4490 //To output the same field for single field input,
4491 //do NOT set h'3B[9]=1 and h'11[12]=0
4492 g_pHalMVOPCtx->eSubRepeatField = E_MVOP_RPTFLD_NONE; //reset the flag to repeat field
4493 MVOP_DBG(" %x\n", g_pHalMVOPCtx->eSubRepeatField);
4494 }
4495
4496 // HSize
4497 MS_U16 u16HSize = ALIGN_UPTO_16(pparam->u16HSize);
4498 if (u16HSize != pparam->u16HSize)
4499 {
4500 MVOP_DBG(MVOP_PRINTF("\n\n Change HSize %d to %d\n", pparam->u16HSize, u16HSize);)
4501 }
4502 HAL_WriteByte(SUB_REG(VOP_JPG_HSIZE ), LOWBYTE( u16HSize ));
4503 HAL_WriteByte(SUB_REG(VOP_JPG_HSIZE + 1), HIGHBYTE( u16HSize ));
4504
4505 // VSize
4506 MS_U16 u16VSize = pparam->u16VSize;
4507 if (g_pHalMVOPCtx->bSubMirrorModeVer)
4508 {
4509 u16VSize = ALIGN_UPTO_4(pparam->u16VSize);
4510 MVOP_DBG(MVOP_PRINTF("\n\n Change VSize %d to %d\n", pparam->u16VSize, u16VSize);)
4511 }
4512 HAL_WriteByte(SUB_REG(VOP_JPG_VSIZE ), LOWBYTE( u16VSize ));
4513 HAL_WriteByte(SUB_REG(VOP_JPG_VSIZE + 1), HIGHBYTE( u16VSize ));
4514 }
4515
4516 HAL_MVOP_SubLoadReg();
4517 }
4518
4519
HAL_MVOP_SubEnableUVShift(MS_BOOL bEnable)4520 void HAL_MVOP_SubEnableUVShift(MS_BOOL bEnable)
4521 {
4522 MS_U8 regval;
4523
4524 regval = HAL_ReadByte(SUB_REG(VOP_MPG_JPG_SWITCH));
4525
4526 if (((regval & BIT4) == BIT4) && ((regval & 0x3)== 0x2))
4527 { // 422 with MCU control mode
4528 if (bEnable)
4529 {
4530 MS_ASSERT(0);
4531 }
4532 }
4533
4534 // output 420 and interlace
4535 //[IP - Sheet] : Main Page --- 420CUP
4536 //[Project] : Titania2
4537 //[Description]: Chroma artifacts when 420to422 is applied duplicate method.
4538 //[Root cause]: Apply 420to422 average algorithm to all DTV input cases.
4539 //The average algorithm must cooperate with MVOP.
4540 HAL_WriteByteMask(SUB_REG(VOP_UV_SHIFT), (bEnable)?1:0, 0x3);
4541 }
4542
4543 static MS_BOOL _bSubEnable60P = false;
HAL_MVOP_SubSetEnable60P(MS_BOOL bEnable)4544 void HAL_MVOP_SubSetEnable60P(MS_BOOL bEnable)
4545 {
4546 _bSubEnable60P = bEnable;
4547 }
4548
4549 static MS_BOOL _bSubEnable4k2kClk = false;
HAL_MVOP_SubSetEnable4k2kClk(MS_BOOL bEnable)4550 void HAL_MVOP_SubSetEnable4k2kClk(MS_BOOL bEnable)
4551 {
4552 _bSubEnable4k2kClk = bEnable;
4553 }
4554
4555
HAL_MVOP_SubSetEnable4k2k2P(MS_BOOL bEnable)4556 void HAL_MVOP_SubSetEnable4k2k2P(MS_BOOL bEnable)
4557 {
4558 g_pHalMVOPCtx->bSubIs2p = bEnable;
4559 HAL_WriteRegBit(SUB_REG(VOP_REG_4K2K_2P), bEnable, VOP_4K2K_2P);
4560
4561 }
4562
HAL_MVOP_SubEnableFreerunMode(MS_BOOL bEnable)4563 void HAL_MVOP_SubEnableFreerunMode(MS_BOOL bEnable)
4564 {
4565 if (g_pHalMVOPCtx == NULL)
4566 {
4567 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
4568 return;
4569 }
4570 g_pHalMVOPCtx->bSubEnableFreerunMode = bEnable;
4571 }
4572
HAL_MVOP_SubSetOutputTiming(MVOP_Timing * ptiming)4573 void HAL_MVOP_SubSetOutputTiming( MVOP_Timing *ptiming )
4574 {
4575 MS_U8 regval;
4576
4577 HAL_WriteByte(SUB_REG(VOP_FRAME_VCOUNT ), LOWBYTE( ptiming->u16V_TotalCount ));
4578 HAL_WriteByte(SUB_REG(VOP_FRAME_VCOUNT + 1), HIGHBYTE( ptiming->u16V_TotalCount ));
4579 HAL_WriteByte(SUB_REG(VOP_FRAME_HCOUNT ), LOWBYTE( ptiming->u16H_TotalCount ));
4580 HAL_WriteByte(SUB_REG(VOP_FRAME_HCOUNT + 1), HIGHBYTE( ptiming->u16H_TotalCount ));
4581
4582 HAL_WriteByte(SUB_REG(VOP_VB0_STR ), LOWBYTE( ptiming->u16VBlank0_Start ));
4583 HAL_WriteByte(SUB_REG(VOP_VB0_STR + 1), HIGHBYTE( ptiming->u16VBlank0_Start ));
4584 HAL_WriteByte(SUB_REG(VOP_VB0_END ), LOWBYTE( ptiming->u16VBlank0_End ));
4585 HAL_WriteByte(SUB_REG(VOP_VB0_END + 1), HIGHBYTE( ptiming->u16VBlank0_End ));
4586 HAL_WriteByte(SUB_REG(VOP_VB1_STR ), LOWBYTE( ptiming->u16VBlank1_Start ));
4587 HAL_WriteByte(SUB_REG(VOP_VB1_STR + 1), HIGHBYTE( ptiming->u16VBlank1_Start ));
4588 HAL_WriteByte(SUB_REG(VOP_VB1_END ), LOWBYTE( ptiming->u16VBlank1_End ));
4589 HAL_WriteByte(SUB_REG(VOP_VB1_END + 1), HIGHBYTE( ptiming->u16VBlank1_End ));
4590 HAL_WriteByte(SUB_REG(VOP_TF_STR ), LOWBYTE( ptiming->u16TopField_Start ));
4591 HAL_WriteByte(SUB_REG(VOP_TF_STR + 1), HIGHBYTE( ptiming->u16TopField_Start ));
4592 HAL_WriteByte(SUB_REG(VOP_BF_STR ), LOWBYTE( ptiming->u16BottomField_Start ));
4593 HAL_WriteByte(SUB_REG(VOP_BF_STR + 1), HIGHBYTE( ptiming->u16BottomField_Start ));
4594 HAL_WriteByte(SUB_REG(VOP_HACT_STR ), LOWBYTE( ptiming->u16HActive_Start ));
4595 HAL_WriteByte(SUB_REG(VOP_HACT_STR + 1), HIGHBYTE( ptiming->u16HActive_Start ));
4596
4597 HAL_WriteByte(SUB_REG(VOP_TF_VS ), LOWBYTE( ptiming->u16TopField_VS ));
4598 HAL_WriteByte(SUB_REG(VOP_TF_VS + 1), HIGHBYTE( ptiming->u16TopField_VS ));
4599 HAL_WriteByte(SUB_REG(VOP_BF_VS ), LOWBYTE( ptiming->u16BottomField_VS ));
4600 HAL_WriteByte(SUB_REG(VOP_BF_VS + 1), HIGHBYTE( ptiming->u16BottomField_VS ));
4601
4602 //if(((ptiming->u16V_TotalCount > 2160) || (ptiming->u16H_TotalCount > 3840)) && (ptiming->u8Framerate >= 30))
4603 if((!g_pHalMVOPCtx->bSubIsXcTrig) && (g_pHalMVOPCtx->bSubIsHS))
4604 {
4605 g_pHalMVOPCtx->bSubNewVSyncMode = TRUE;
4606 }
4607
4608 if (g_pHalMVOPCtx->bSubNewVSyncMode)
4609 {
4610 #define SUB_NEW_VSYNC_MODE_ADVANCE_LINECNT 30
4611 MVOP_DBG(MVOP_PRINTF("MVOP use new vync mode, forwarding %d lines\n",SUB_NEW_VSYNC_MODE_ADVANCE_LINECNT);)
4612
4613 MS_U16 u16BottomField_VS2MVD = ptiming->u16BottomField_VS - SUB_NEW_VSYNC_MODE_ADVANCE_LINECNT;
4614 MVOP_DBG(MVOP_PRINTF("BottomField VS ori=0x%x, new=0x%x\n", ptiming->u16BottomField_VS, u16BottomField_VS2MVD);)
4615 HAL_WriteByte(SUB_REG(VOP_BF_VS_MVD), LOWBYTE( u16BottomField_VS2MVD ));
4616 HAL_WriteByte(SUB_REG((VOP_BF_VS_MVD + 1)), HIGHBYTE( u16BottomField_VS2MVD ));
4617
4618 MS_U16 u16TopField_VS2MVD = ptiming->u16V_TotalCount - SUB_NEW_VSYNC_MODE_ADVANCE_LINECNT;
4619 MVOP_DBG(MVOP_PRINTF("TopField VS Vtt=0x%x, new=0x%x\n", ptiming->u16V_TotalCount, u16TopField_VS2MVD);)
4620 HAL_WriteByte(SUB_REG(VOP_TF_VS_MVD), LOWBYTE( u16TopField_VS2MVD ));
4621 HAL_WriteByte(SUB_REG((VOP_TF_VS_MVD + 1)), HIGHBYTE( u16TopField_VS2MVD ));
4622
4623 HAL_WriteRegBit(SUB_REG(VOP_GCLK), 0, VOP_GCLK_MIU_ON);
4624
4625 HAL_WriteRegBit(SUB_REG(VOP_CTRL1), 1, VOP_MVD_VS_MD); //Use new vsync
4626
4627 g_pHalMVOPCtx->bSubNewVSyncMode = FALSE; //restore to original mode
4628 }
4629
4630
4631 // + S3, set default IMG_HSTR, IMG_VSTR0, IMG_VSTR1
4632 #ifdef _SUPPORT_IMG_OFFSET_
4633 HAL_WriteByte(SUB_REG(VOP_IMG_HSTR ), LOWBYTE( ptiming->u16HImg_Start));
4634 HAL_WriteByte(SUB_REG(VOP_IMG_HSTR + 1), HIGHBYTE( ptiming->u16HImg_Start ));
4635 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR0 ), LOWBYTE( ptiming->u16VImg_Start0));
4636 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR0+ 1), HIGHBYTE( ptiming->u16VImg_Start0 ));
4637 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR1 ), LOWBYTE( ptiming->u16VImg_Start1 ));
4638 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR1+ 1), HIGHBYTE( ptiming->u16VImg_Start1 ));
4639 #else
4640 HAL_WriteByte(SUB_REG(VOP_IMG_HSTR ), LOWBYTE( ptiming->u16HActive_Start ));
4641 HAL_WriteByte(SUB_REG(VOP_IMG_HSTR + 1), HIGHBYTE( ptiming->u16HActive_Start ));
4642 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR0 ), LOWBYTE( ptiming->u16VBlank0_End ));
4643 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR0+ 1), HIGHBYTE( ptiming->u16VBlank0_End ));
4644 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR1 ), LOWBYTE( ptiming->u16VBlank1_End ));
4645 HAL_WriteByte(SUB_REG(VOP_IMG_VSTR1+ 1), HIGHBYTE( ptiming->u16VBlank1_End ));
4646 #endif
4647 // select mvop output from frame color(black)
4648 HAL_WriteByte(SUB_REG(VOP_TST_IMG + 1), 0x10);
4649 HAL_WriteByte(SUB_REG(VOP_U_PAT ), 0x80);
4650 HAL_WriteByte(SUB_REG(VOP_U_PAT + 1), 0x80);
4651 // set mvop src to test pattern
4652 regval = HAL_ReadByte(SUB_REG(VOP_TST_IMG));
4653 HAL_WriteByteMask(SUB_REG(VOP_TST_IMG), 0x02, BIT2 | BIT1 | BIT0);
4654 // make changed registers take effect
4655 HAL_MVOP_SubLoadReg();
4656
4657 HAL_MVOP_SubSetMIUReqMask(TRUE);
4658 // reset mvop to avoid timing change cause mvop hang-up
4659 HAL_MVOP_SubRst();
4660 HAL_MVOP_SubSetMIUReqMask(FALSE);
4661
4662 // select mvop output from mvd
4663 HAL_WriteByteMask(SUB_REG(VOP_TST_IMG), 0x00, BIT2 | BIT1 | BIT0);
4664 HAL_WriteByteMask(SUB_REG(VOP_TST_IMG), regval, BIT2 | BIT1 | BIT0);
4665 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), ptiming->bHDuplicate, BIT2);// H pixel duplicate
4666
4667 g_pHalMVOPCtx->u16SubHsize = ptiming->u16Width;
4668 //for supporting out of spec, line buffer only 2048
4669 if(ptiming->u16Width > 2048)
4670 {
4671 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), 0, VOP_420_BW_SAVE);
4672 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), 0, VOP_420_BW_SAVE_EX);
4673 }
4674 #if 0
4675 MVOP_DBG(MVOP_PRINTF("\nMVOP SetOutputTiming\n");)
4676 MVOP_DBG(MVOP_PRINTF(" VTot=%u,\t",ptiming->u16V_TotalCount);)
4677 MVOP_DBG(MVOP_PRINTF(" HTot=%u,\t",ptiming->u16H_TotalCount);)
4678 MVOP_DBG(MVOP_PRINTF(" I/P=%u\n",ptiming->bInterlace);)
4679 MVOP_DBG(MVOP_PRINTF(" W=%u,\t",ptiming->u16Width);)
4680 MVOP_DBG(MVOP_PRINTF(" H=%u,\t",ptiming->u16Height);)
4681 MVOP_DBG(MVOP_PRINTF(" FRate=%u,\t",ptiming->u8Framerate);)
4682 MVOP_DBG(MVOP_PRINTF(" HFreq=%u\n",ptiming->u16H_Freq);)
4683 MVOP_DBG(MVOP_PRINTF(" Num=0x%x,\t",ptiming->u16Num);)
4684 MVOP_DBG(MVOP_PRINTF(" Den=0x%x,\t",ptiming->u16Den);)
4685 MVOP_DBG(MVOP_PRINTF(" u16ExpFRate=%u #\n\n", ptiming->u16ExpFrameRate);)
4686 #endif
4687 }
4688
HAL_MVOP_SubSetDCClk(MS_U8 clkNum,MS_BOOL bEnable)4689 void HAL_MVOP_SubSetDCClk(MS_U8 clkNum, MS_BOOL bEnable)
4690 {
4691 MS_ASSERT( (clkNum==0) || (clkNum==1) );
4692 if (clkNum==0)
4693 {
4694 HAL_WriteRegBit(REG_CKG_SUB_DC0, !bEnable, CKG_SUB_DC0_GATED);
4695 }
4696 }
4697
HAL_MVOP_SubSetDCSRAMClk(MS_U8 clkNum,MS_BOOL bEnable)4698 void HAL_MVOP_SubSetDCSRAMClk(MS_U8 clkNum, MS_BOOL bEnable)
4699 {
4700 MS_ASSERT( (clkNum==0) || (clkNum==1) );
4701 if (clkNum==0)
4702 {
4703 if(bEnable)
4704 HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x40, CKG_DC1_SRAM); //Dc1 enable & dc1_mfdec_en =0 57[7:4]= 0x4, others 57[7:4]=0x0
4705 else
4706 HAL_WriteByteMask(REG_CKG_DC_SRAM, 0x0, CKG_DC1_SRAM);
4707 }
4708 }
4709
HAL_MVOP_SubSetSynClk(MVOP_Timing * ptiming)4710 void HAL_MVOP_SubSetSynClk(MVOP_Timing *ptiming)
4711 {
4712 if (g_pHalMVOPCtx == NULL)
4713 {
4714 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
4715 return;
4716 }
4717 if(g_pHalMVOPCtx->u32SubMVOPFixClk != 0)
4718 {
4719 HAL_MVOP_SubSetFrequency(g_pHalMVOPCtx->u32SubMVOPFixClk);
4720 if(g_pHalMVOPCtx->bSub3DLRMode)//4k1k mvc
4721 {
4722 //burst and priority
4723 HAL_WriteByte(SUB_REG(VOP_DMA1), 0x26);
4724 HAL_WriteByte(SUB_REG(VOP_BURST_CTRL0), 0x05);
4725 HAL_WriteByte(SUB_REG(VOP_BURST_CTRL1), 0x00);
4726 }
4727 }
4728 else if(g_pHalMVOPCtx->bSubEnableFreerunMode)
4729 {
4730 MS_U64 u64mpll_clock = MPLL_CLOCK << 27 ;
4731 do_div(u64mpll_clock, ((MS_U32)ptiming->u16H_TotalCount * (MS_U32)ptiming->u16V_TotalCount * (MS_U32)ptiming->u8Framerate));
4732 MS_U32 u32FreerunClk = (MS_U32)u64mpll_clock;
4733 HAL_MVOP_SubSetFrequency(HALMVOP_FREERUNMODE);
4734 HAL_WriteByte((REG_DC1_FREERUN_CW_L ), LOWBYTE((MS_U16)u32FreerunClk));
4735 HAL_WriteByte((REG_DC1_FREERUN_CW_L+1), HIGHBYTE((MS_U16)u32FreerunClk));
4736 HAL_WriteByte((REG_DC1_FREERUN_CW_H ), LOWBYTE((MS_U16)(u32FreerunClk >> 16)));
4737 HAL_WriteByte((REG_DC1_FREERUN_CW_H+1), HIGHBYTE((MS_U16)(u32FreerunClk >> 16)));
4738 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_FREERUN_CW);
4739 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_FREERUN_CW);
4740 }
4741 else if (_bSubEnable60P)
4742 {
4743 HAL_MVOP_SubSetFrequency(HAL_MVOP_SubGetMaxFreerunClk());
4744 HAL_WriteRegBit(SUB_REG(VOP_REG_FRAME_RST), 0, BIT15); // reg_frame_rst = 0
4745
4746 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), DISABLE, VOP_FSYNC_EN); // frame sync disable
4747
4748 if(g_pHalMVOPCtx->bSub3DLRMode)//4k1k mvc
4749 {
4750 //burst and priority
4751 HAL_WriteByte(SUB_REG(VOP_DMA1), 0x26);
4752 HAL_WriteByte(SUB_REG(VOP_BURST_CTRL0), 0x05);
4753 HAL_WriteByte(SUB_REG(VOP_BURST_CTRL1), 0x00);
4754 }
4755 }
4756 else if (_bSubEnable4k2kClk)
4757 {
4758 HAL_MVOP_SubSetFrequency(HAL_MVOP_SubGet4k2kClk());
4759
4760 HAL_WriteRegBit(SUB_REG(VOP_REG_FRAME_RST), 0, BIT15); // reg_frame_rst = 0
4761
4762 HAL_WriteRegBit(SUB_REG(VOP_CTRL0), DISABLE, VOP_FSYNC_EN); // frame sync disable
4763 }
4764 else
4765 {
4766 HAL_MVOP_SubSetFrequency(HALMVOP_SYNCMODE);
4767 HAL_WriteByte((REG_DC1_NUM ), LOWBYTE( ptiming->u16Num));
4768 HAL_WriteByte((REG_DC1_NUM+1), HIGHBYTE(ptiming->u16Num));
4769 HAL_WriteByte((REG_DC1_DEN ), LOWBYTE( ptiming->u16Den));
4770 HAL_WriteByte((REG_DC1_DEN+1), HIGHBYTE(ptiming->u16Den));
4771 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 1, UPDATE_DC1_SYNC_CW);
4772 HAL_WriteRegBit(REG_UPDATE_DC1_CW, 0, UPDATE_DC1_SYNC_CW);
4773 }
4774 }
4775
4776
HAL_MVOP_SubSetMonoMode(MS_BOOL bEnable)4777 void HAL_MVOP_SubSetMonoMode(MS_BOOL bEnable)
4778 {
4779 if(bEnable)
4780 {
4781 HAL_WriteByte(SUB_REG(VOP_U_PAT ), 0x80);
4782 HAL_WriteByte(SUB_REG(VOP_U_PAT+1), 0x80);
4783
4784 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH1), 1, BIT1); // Mono mode enable
4785 }
4786 else
4787 {
4788 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH1), 0, BIT1); //Mono mode disable
4789 }
4790 }
4791
4792 /******************************************************************************/
4793 /// Set MVOP for H264 Hardwire Mode
4794 /******************************************************************************/
HAL_MVOP_SubSetH264HardwireMode(MS_U16 u16ECOVersion)4795 void HAL_MVOP_SubSetH264HardwireMode(MS_U16 u16ECOVersion)
4796 {
4797 // Hardwire mode
4798 HAL_WriteByte(SUB_REG(VOP_MPG_JPG_SWITCH), 0x00);
4799
4800 HAL_WriteRegBit(SUB_REG(VOP_REG_STRIP_ALIGN), 0, BIT0);
4801
4802 //16*32 tile format
4803 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT1);
4804
4805 // SVD mode enable
4806 HAL_WriteByteMask(SUB_REG(VOP_INPUT_SWITCH1), BIT3, BIT2|BIT3);
4807
4808
4809 // set mvop to 64bit interface
4810 HAL_WriteByteMask(SUB_REG(VOP_MIU_IF), VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
4811 // Only for Monaco: Disable deciding bot by top address + 2
4812 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), 0, VOP_FIELD_FROM_ADDR);
4813
4814 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), 1, VOP_32x32_WB); //32x32 from wb
4815
4816 // Write trigger
4817 HAL_MVOP_SubLoadReg();
4818 }
4819
HAL_MVOP_SubEnableMVDInterface(MS_BOOL bEnable)4820 void HAL_MVOP_SubEnableMVDInterface(MS_BOOL bEnable)
4821 {
4822 MS_BOOL bMVOPMain2MVD = TRUE;
4823 bMVOPMain2MVD = (bEnable) ? FALSE : TRUE;
4824
4825 //This bit is only valid in main mvop bank.
4826 //Select which mvop interrupt that mvd f/w recieve: 1 for main; 0 for sub.
4827 HAL_WriteByteMask(VOP_INPUT_SWITCH1, bMVOPMain2MVD, VOP_MVD_EN);
4828
4829 //No need to "Write trigger" since HAL_MVOP_SubSetInputMode() will do it later.
4830 //HAL_MVOP_SubLoadReg();
4831 }
4832
4833 /******************************************************************************/
4834 /// Set MVOP for RM Hardwire Mode
4835 /******************************************************************************/
HAL_MVOP_SubSetRMHardwireMode(MS_U16 u16ECOVersion)4836 void HAL_MVOP_SubSetRMHardwireMode(MS_U16 u16ECOVersion)
4837 {
4838 HAL_MVOP_SubSetH264HardwireMode(u16ECOVersion);
4839 }
4840
4841 /******************************************************************************/
4842 /// Set MVOP for JPEG Hardwire Mode
4843 /******************************************************************************/
HAL_MVOP_SubSetJpegHardwireMode(MS_U16 u16ECOVersion)4844 void HAL_MVOP_SubSetJpegHardwireMode(MS_U16 u16ECOVersion)
4845 {
4846 MS_U8 regval = 0x00;
4847
4848 //Hardwire mode//
4849 //Use HVD interface//
4850 HAL_MVOP_SubSetH264HardwireMode(u16ECOVersion);
4851
4852 regval |= 0x80; // packmode
4853 regval |= 0x20; // Dram Rd Contd
4854 regval |= 0x10; // reg_img422
4855 HAL_WriteByte(SUB_REG(VOP_MPG_JPG_SWITCH), regval);
4856 /* There is no hardwire:mvd2dc_img422/hvd2dc_img422 0x20[4] in sub mvop*/
4857 HAL_WriteByteMask(SUB_REG(VOP_INFO_FROM_CODEC_L), 0, VOP_INFO_FROM_CODEC_422_FMT);
4858 g_pHalMVOPCtx->bSubIs422 = 1;
4859 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), 0, VOP_420_BW_SAVE);
4860 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), 0, VOP_420_BW_SAVE_EX);
4861 HAL_WriteByteMask(SUB_REG(VOP_INFO_FROM_CODEC_H), 0x00, VOP_INFO_FROM_CODEC_MIU_BUF0_SEL|VOP_INFO_FROM_CODEC_MIU_BUF1_SEL);
4862
4863 // Write trigger
4864 HAL_MVOP_SubLoadReg();
4865 }
4866 /******************************************************************************/
4867 /// Set MVOP for EVD Hardwire Mode
4868 /******************************************************************************/
HAL_MVOP_SubSetEVDHardwireMode(MS_U16 u16ECOVersion)4869 void HAL_MVOP_SubSetEVDHardwireMode(MS_U16 u16ECOVersion)
4870 {
4871 // Hardwire mode
4872 HAL_WriteByte(SUB_REG(VOP_MPG_JPG_SWITCH), 0x00);
4873
4874 HAL_WriteRegBit(SUB_REG(VOP_REG_STRIP_ALIGN), 0, BIT0);
4875
4876 //16*32 tile format
4877 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), 1, BIT1);
4878
4879 // EVD use HVD interface
4880 //HAL_WriteByteMask(SUB_REG(VOP_INPUT_SWITCH1), BIT3, BIT2|BIT3);
4881
4882 // EVD mode enable
4883 HAL_WriteRegBit(SUB_REG(VOP_INPUT_SWITCH0), 1, EVD_ENABLE);
4884
4885 // set mvop to 128bit_i128 interface
4886 HAL_WriteByteMask(SUB_REG(VOP_MIU_IF), VOP_MIU_128BIT, VOP_MIU_128BIT|VOP_MIU_128B_I64);
4887
4888 // set evd flag for interlace mode setting
4889 g_pHalMVOPCtx->bSubIsH265 = 1;
4890
4891 // 10 bits from wb
4892 HAL_WriteRegBit(SUB_REG(VOP_INFO_FROM_CODEC_H), 1, VOP_INFO_FROM_CODEC_10BIT);
4893 HAL_WriteByteMask(SUB_REG(VOP_REG_MASK), 0, VOP_LSB_REQ_MASK);
4894
4895 // Write trigger
4896 HAL_MVOP_SubLoadReg();
4897 }
4898
4899 /******************************************************************************/
4900 /// Set MVOP for VP9 Hardwire Mode
4901 /******************************************************************************/
HAL_MVOP_SubSetVP9HardwireMode(MS_U16 u16ECOVersion)4902 void HAL_MVOP_SubSetVP9HardwireMode(MS_U16 u16ECOVersion)
4903 {
4904 HAL_MVOP_SubSetEVDHardwireMode(u16ECOVersion);
4905 }
4906
4907
4908 ///Enable 3D L/R dual buffer mode
HAL_MVOP_SubEnable3DLR(MS_BOOL bEnable)4909 MS_BOOL HAL_MVOP_SubEnable3DLR(MS_BOOL bEnable)
4910 {
4911 if (g_pHalMVOPCtx == NULL)
4912 {
4913 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
4914 return FALSE;
4915 }
4916 HAL_WriteRegBit(SUB_REG(VOP_MULTI_WIN_CFG0), bEnable, VOP_LR_BUF_MODE);
4917 g_pHalMVOPCtx->bSub3DLRMode = bEnable;
4918 if(bEnable)
4919 {
4920 //only for monaco: do not wait for data ready.
4921 HAL_WriteByteMask(SUB_REG(VOP_NOT_WAIT_READ_DATA), 2, VOP_NOT_WAIT_RDLAT);
4922 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), 0, VOP_420_BW_SAVE_EX);
4923 }
4924 else
4925 {
4926 HAL_WriteByteMask(SUB_REG(VOP_NOT_WAIT_READ_DATA), 0, VOP_NOT_WAIT_RDLAT);
4927 }
4928 return TRUE;
4929 }
4930
4931 ///Get if 3D L/R mode is enabled
HAL_MVOP_SubGet3DLRMode(void)4932 MS_BOOL HAL_MVOP_SubGet3DLRMode(void)
4933 {
4934 if (g_pHalMVOPCtx == NULL)
4935 {
4936 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
4937 return FALSE;
4938 }
4939 return g_pHalMVOPCtx->bSub3DLRMode;
4940 }
4941
HAL_MVOP_SubGetTimingInfoFromRegisters(MVOP_TimingInfo_FromRegisters * pMvopTimingInfo)4942 MS_BOOL HAL_MVOP_SubGetTimingInfoFromRegisters(MVOP_TimingInfo_FromRegisters *pMvopTimingInfo)
4943 {
4944 if(NULL == pMvopTimingInfo)
4945 {
4946 MVOP_PRINTF("HAL_MVOP_SubGetTimingInfoFromRegisters():pMvopTimingInfo is NULL\n");
4947 return FALSE;
4948 }
4949 if(HAL_MVOP_SubGetEnableState() == FALSE)
4950 {
4951 MVOP_PRINTF("MVOP is not enabled!\n");
4952 pMvopTimingInfo->bEnabled = FALSE;
4953 return FALSE;
4954 }
4955 pMvopTimingInfo->bEnabled = TRUE;
4956 pMvopTimingInfo->u16H_TotalCount = (HAL_ReadByte(SUB_REG(VOP_FRAME_HCOUNT + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_FRAME_HCOUNT)));
4957 pMvopTimingInfo->u16V_TotalCount = (HAL_ReadByte(SUB_REG(VOP_FRAME_VCOUNT + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_FRAME_VCOUNT)));
4958 pMvopTimingInfo->u16VBlank0_Start = (HAL_ReadByte(SUB_REG(VOP_VB0_STR + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_VB0_STR)));
4959 pMvopTimingInfo->u16VBlank0_End = (HAL_ReadByte(SUB_REG(VOP_VB0_END + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_VB0_END)));
4960 pMvopTimingInfo->u16VBlank1_Start = (HAL_ReadByte(SUB_REG(VOP_VB1_STR + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_VB1_STR)));
4961 pMvopTimingInfo->u16VBlank1_End = (HAL_ReadByte(SUB_REG(VOP_VB1_END + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_VB1_END)));
4962 pMvopTimingInfo->u16TopField_Start = (HAL_ReadByte(SUB_REG(VOP_TF_STR + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_TF_STR)));
4963 pMvopTimingInfo->u16BottomField_Start = (HAL_ReadByte(SUB_REG(VOP_BF_STR + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_BF_STR)));
4964 pMvopTimingInfo->u16HActive_Start = (HAL_ReadByte(SUB_REG(VOP_HACT_STR + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_HACT_STR)));
4965 pMvopTimingInfo->u16TopField_VS = (HAL_ReadByte(SUB_REG(VOP_TF_VS + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_TF_VS)));
4966 pMvopTimingInfo->u16BottomField_VS = (HAL_ReadByte(SUB_REG(VOP_BF_VS + 1)<< 8)) | (HAL_ReadByte(SUB_REG(VOP_BF_VS)));
4967 pMvopTimingInfo->bInterlace = (HAL_ReadRegBit(SUB_REG(VOP_CTRL0), BIT7) == BIT7);
4968 return TRUE;
4969 }
4970
HAL_MVOP_SubSetYUVBaseAdd(MS_PHY u32YOffset,MS_PHY u32UVOffset,MS_BOOL bProgressive,MS_BOOL b422pack)4971 void HAL_MVOP_SubSetYUVBaseAdd(MS_PHY u32YOffset, MS_PHY u32UVOffset, MS_BOOL bProgressive, MS_BOOL b422pack)
4972 {
4973 MS_PHY u64tmp = 0;
4974
4975 if (g_pHalMVOPCtx == NULL)
4976 {
4977 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
4978 return;
4979 }
4980 // Y offset
4981 u64tmp = u32YOffset >> 3;
4982 if ( !bProgressive )
4983 { //Refine Y offset for interlace repeat bottom field
4984 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eSubRepeatField)
4985 {
4986 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eSubRepeatField);
4987 u64tmp += 2;
4988 }
4989 else
4990 {
4991 MVOP_DBG("%d eRepeatField(%x) is TOP or NONE.\n", __LINE__, g_pHalMVOPCtx->eSubRepeatField);
4992 }
4993 }
4994 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L), u64tmp & 0xff);
4995 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L+1), (u64tmp >> 8) & 0xff);
4996 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L+2), (u64tmp >> 16) & 0xff);
4997 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
4998
4999 if (!bProgressive )
5000 { //Y offset of bottom field if interlace
5001 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_L), u64tmp & 0xff);
5002 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_L+1), (u64tmp >> 8) & 0xff);
5003 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_L+2), (u64tmp >> 16) & 0xff);
5004 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5005 }
5006
5007 if (b422pack)
5008 {
5009 if (HAL_ReadRegBit(SUB_REG(VOP_MIU_IF), VOP_MIU_128B_I64) != VOP_MIU_128B_I64) //128-bit
5010 {
5011 u32UVOffset = u32YOffset + 16; //add 16 for 128bit; add 8 for 64bit
5012 }
5013 else //64-bit
5014 {
5015 u32UVOffset = u32YOffset + 8; //add 16 for 128bit; add 8 for 64bit
5016 }
5017 }
5018 // UV offset
5019 u64tmp = u32UVOffset >> 3;
5020 if( !bProgressive )
5021 { //Refine UV offset for interlace repeat bottom field
5022 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eSubRepeatField)
5023 {
5024 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eSubRepeatField);
5025 u64tmp += 2;
5026 }
5027 else
5028 {
5029 MVOP_DBG("%d eRepeatField(%x) is TOP/NONE.\n", __LINE__, g_pHalMVOPCtx->eSubRepeatField);
5030 }
5031 }
5032 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L), u64tmp & 0xff);
5033 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L+1), (u64tmp >> 8) & 0xff);
5034 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L+2), (u64tmp >> 16) & 0xff);
5035 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5036
5037 if( !bProgressive )
5038 { //UV offset of bottom field if interlace
5039 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_L), u64tmp & 0xff);
5040 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_L+1), (u64tmp >> 8) & 0xff);
5041 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_L+2), (u64tmp >> 16) & 0xff);
5042 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_L+3), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5043 }
5044
5045 return;
5046 }
5047
HAL_MVOP_SubGetYBaseAdd(void)5048 MS_PHY HAL_MVOP_SubGetYBaseAdd(void)
5049 {
5050 MS_PHY u64YOffset;
5051 u64YOffset = HAL_ReadByte(SUB_REG(VOP_JPG_YSTR0_L))&0xff;
5052 u64YOffset |=((HAL_ReadByte(SUB_REG(VOP_JPG_YSTR0_L+1))<<8)&0xff00);
5053 u64YOffset |=((HAL_ReadByte(SUB_REG(VOP_JPG_YSTR0_L+2))<<16)&0xff0000);
5054 u64YOffset |= ((HAL_ReadByte(SUB_REG(VOP_JPG_YSTR0_L+3)) & VOP_YUV_STR_HIBITS) <<24);
5055 return u64YOffset;
5056 }
5057
HAL_MVOP_SubGetUVBaseAdd(void)5058 MS_PHY HAL_MVOP_SubGetUVBaseAdd(void)
5059 {
5060 MS_PHY u64UVOffset;
5061 u64UVOffset = HAL_ReadByte(SUB_REG(VOP_JPG_UVSTR0_L))&0xff;
5062 u64UVOffset |=((HAL_ReadByte(SUB_REG(VOP_JPG_UVSTR0_L+1))<<8)&0xff00);
5063 u64UVOffset |=((HAL_ReadByte(SUB_REG(VOP_JPG_UVSTR0_L+2))<<16)&0xff0000);
5064 u64UVOffset |= ((HAL_ReadByte(SUB_REG(VOP_JPG_UVSTR0_L+3)) & VOP_YUV_STR_HIBITS) <<24);
5065 return u64UVOffset;
5066 }
5067
5068 /******************************************************************************/
5069 /// Set MVOP Saving BW Mode
5070 /// @ Napoli this command should be set after MDrv_MVOP_SubSetOutputCfg
5071 /******************************************************************************/
HAL_MVOP_SubSet420BWSaveMode(MS_BOOL bEnable,MS_U16 u16ECOVersion)5072 MS_BOOL HAL_MVOP_SubSet420BWSaveMode(MS_BOOL bEnable, MS_U16 u16ECOVersion)
5073 {
5074 UNUSED(u16ECOVersion);
5075 MS_BOOL bValue = FALSE;
5076
5077 //hw limtation: 3DLA/3DSBS/422/p mode in, i mode out/i mode in, p mode out(only need to check in MCU mode)
5078 bValue = (g_pHalMVOPCtx->bSub3DLRAltSBSOutput || g_pHalMVOPCtx->bSub3DLRAltOutput/* || g_pHalMVOPCtx->bSub3DLRMode */|| g_pHalMVOPCtx->bSubIs422 || (g_pHalMVOPCtx->u16SubHsize > 2048));
5079
5080 if(bValue)
5081 {
5082 MVOP_DBG(MVOP_PRINTF("%s Hit the limitation of saving bw, disable BW Saving mode\n", __FUNCTION__);)
5083 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), 0, VOP_420_BW_SAVE);
5084 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), 0, VOP_420_BW_SAVE_EX);
5085 HAL_MVOP_SubLoadReg();
5086 return FALSE;
5087 }
5088 else
5089 {
5090 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), bEnable, VOP_420_BW_SAVE);
5091 if( g_pHalMVOPCtx->bSub3DLRMode == FALSE)
5092 {
5093 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), bEnable, VOP_420_BW_SAVE_EX);
5094 }
5095 HAL_MVOP_SubLoadReg();
5096 return TRUE;
5097 }
5098 }
5099
HAL_MVOP_SubSetEVDYUVBaseAdd(MVOP_EVDBaseAddInput * stEVDBaseAddInfo)5100 MS_BOOL HAL_MVOP_SubSetEVDYUVBaseAdd(MVOP_EVDBaseAddInput *stEVDBaseAddInfo)
5101 {
5102 //----------------------------------------------------
5103 // Set MSB YUV Address
5104 //----------------------------------------------------
5105
5106 MS_PHY u64tmp = 0;
5107
5108 if (g_pHalMVOPCtx == NULL)
5109 {
5110 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
5111 return FALSE;
5112 }
5113 // Y offset
5114 u64tmp = stEVDBaseAddInfo->u32MSBYOffset >> 3;
5115 if ( !stEVDBaseAddInfo->bProgressive)
5116 { //Refine Y offset for interlace repeat bottom field
5117 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
5118 {
5119 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
5120 u64tmp += 2;
5121 }
5122 else
5123 {
5124 MVOP_DBG("%d eRepeatField(%x) is TOP or NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
5125 }
5126 }
5127 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L), u64tmp & 0xff);
5128 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_L+1), (u64tmp >> 8) & 0xff);
5129 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_H), (u64tmp >> 16) & 0xff);
5130 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR0_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5131
5132 if (!stEVDBaseAddInfo->bProgressive )
5133 { //Y offset of bottom field if interlace
5134 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_L), u64tmp & 0xff);
5135 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_L+1), (u64tmp >> 8) & 0xff);
5136 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_H), (u64tmp >> 16) & 0xff);
5137 HAL_WriteByte(SUB_REG(VOP_JPG_YSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5138 }
5139
5140 if (stEVDBaseAddInfo->b422Pack)
5141 {
5142 stEVDBaseAddInfo->u32MSBUVOffset = stEVDBaseAddInfo->u32MSBYOffset + 16; //add 16 for 128bit; add 8 for 64bit
5143 }
5144 // UV offset
5145 u64tmp = stEVDBaseAddInfo->u32MSBUVOffset >> 3;
5146 if( !stEVDBaseAddInfo->bProgressive )
5147 { //Refine UV offset for interlace repeat bottom field
5148 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
5149 {
5150 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
5151 u64tmp += 2;
5152 }
5153 else
5154 {
5155 MVOP_DBG("%d eRepeatField(%x) is TOP/NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
5156 }
5157 }
5158 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L), u64tmp & 0xff);
5159 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_L+1), (u64tmp >> 8) & 0xff);
5160 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_H), (u64tmp >> 16) & 0xff);
5161 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR0_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5162
5163 if( !stEVDBaseAddInfo->bProgressive )
5164 { //UV offset of bottom field if interlace
5165 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_L), u64tmp & 0xff);
5166 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_L+1), (u64tmp >> 8) & 0xff);
5167 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_H), (u64tmp >> 16) & 0xff);
5168 HAL_WriteByte(SUB_REG(VOP_JPG_UVSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5169 }
5170
5171 //----------------------------------------------------
5172 // Set MSB YUV Address
5173 //----------------------------------------------------
5174 if(stEVDBaseAddInfo->bEnLSB)
5175 {
5176 //Enable LSB
5177 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 1, VOP_EVD_10B_Y_EN);
5178 HAL_WriteRegBit(SUB_REG(VOP_EVD_10B_EN), 1, VOP_EVD_10B_UV_EN);
5179 HAL_WriteRegBit(SUB_REG(VOP_REG_MASK), 0, VOP_LSB_REQ_MASK);
5180
5181 // Y offset
5182 u64tmp = stEVDBaseAddInfo->u32LSBYOffset >> 3;
5183 if ( !stEVDBaseAddInfo->bProgressive)
5184 { //Refine Y offset for interlace repeat bottom field
5185 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
5186 {
5187 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
5188 u64tmp += 2;
5189 }
5190 else
5191 {
5192 MVOP_DBG("%d eRepeatField(%x) is TOP or NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
5193 }
5194 }
5195 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR0_L), u64tmp & 0xff);
5196 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR0_L+1), (u64tmp >> 8) & 0xff);
5197 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR0_L), (u64tmp >> 16) & 0xff);
5198 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR0_L+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5199
5200 if (!stEVDBaseAddInfo->bProgressive )
5201 { //Y offset of bottom field if interlace
5202 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR1_L), u64tmp & 0xff);
5203 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR1_L+1), (u64tmp >> 8) & 0xff);
5204 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR1_H), (u64tmp >> 16) & 0xff);
5205 HAL_WriteByte(SUB_REG(VOP_LSB_YSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5206 }
5207
5208 if (stEVDBaseAddInfo->b422Pack)
5209 {
5210 stEVDBaseAddInfo->u32LSBUVOffset = stEVDBaseAddInfo->u32LSBYOffset + 16; //add 16 for 128bit; add 8 for 64bit
5211 }
5212 // UV offset
5213 u64tmp = stEVDBaseAddInfo->u32LSBUVOffset >> 3;
5214 if( !stEVDBaseAddInfo->bProgressive )
5215 { //Refine UV offset for interlace repeat bottom field
5216 if (E_MVOP_RPTFLD_BOT == g_pHalMVOPCtx->eRepeatField)
5217 {
5218 MVOP_DBG("%d eRepeatField(%x) is bottom!\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
5219 u64tmp += 2;
5220 }
5221 else
5222 {
5223 MVOP_DBG("%d eRepeatField(%x) is TOP/NONE.\n", __LINE__, g_pHalMVOPCtx->eRepeatField);
5224 }
5225 }
5226 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR0_L), u64tmp & 0xff);
5227 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR0_L+1), (u64tmp >> 8) & 0xff);
5228 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR0_H), (u64tmp >> 16) & 0xff);
5229 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR0_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5230
5231 if( !stEVDBaseAddInfo->bProgressive )
5232 { //UV offset of bottom field if interlace
5233 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR1_L), u64tmp & 0xff);
5234 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR1_L+1), (u64tmp >> 8) & 0xff);
5235 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR1_H), (u64tmp >> 16) & 0xff);
5236 HAL_WriteByte(SUB_REG(VOP_LSB_UVSTR1_H+1), (u64tmp >> 24) & VOP_YUV_STR_HIBITS);
5237 }
5238 }
5239
5240 return TRUE;
5241 }
5242
HAL_MVOP_SubCheckSTCCW(void)5243 MS_BOOL HAL_MVOP_SubCheckSTCCW(void)
5244 {
5245 MS_U16 u16STC_CW_L = 0;
5246 MS_U16 u16STC_CW_H = 0;
5247
5248 MS_BOOL u16STC_CW_SEL = 0;
5249 MS_BOOL u16TSP_CLK_EN = 0;
5250
5251 u16STC_CW_L = HAL_Read2Byte(REG_STC1_CW_L)&0xffff;
5252 u16STC_CW_H = HAL_Read2Byte(REG_STC1_CW_H)&0xffff;
5253
5254 u16STC_CW_SEL = (HAL_ReadRegBit(REG_STC_CW_SLE_H, BIT1) == BIT1);
5255 u16TSP_CLK_EN = !(HAL_ReadRegBit(REG_TSP_CLK, BIT0) == BIT0);
5256
5257 if((((u16STC_CW_L || u16STC_CW_H) == 0) && (u16STC_CW_SEL == 0)) || ((u16STC_CW_SEL == 1) && (u16TSP_CLK_EN == 0)))
5258 return FALSE;
5259 else
5260 return TRUE;
5261
5262 }
5263
HAL_MVOP_SubSetVSyncMode(MS_U8 u8Mode)5264 void HAL_MVOP_SubSetVSyncMode(MS_U8 u8Mode)
5265 {
5266 if (g_pHalMVOPCtx == NULL)
5267 {
5268 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
5269 return;
5270 }
5271 if (1==u8Mode)
5272 {
5273 g_pHalMVOPCtx->bSubNewVSyncMode = TRUE;
5274 }
5275 else
5276 {
5277 g_pHalMVOPCtx->bSubNewVSyncMode = FALSE;
5278 }
5279 }
5280
HAL_MVOP_SubSet3DLRAltOutput_VHalfScaling(MS_BOOL bEnable)5281 MS_BOOL HAL_MVOP_SubSet3DLRAltOutput_VHalfScaling(MS_BOOL bEnable)
5282 {
5283 MS_BOOL bEnDualBuff = bEnable ? ENABLE : DISABLE; //enable dual buffer
5284 MS_BOOL bEnSWDualBuff = bEnable ? DISABLE : ENABLE; //buffer controlled by HK instead of FW
5285 MS_BOOL bEnMirrMaskBase = bEnable ? DISABLE : ENABLE; //do not mask LSB
5286 MS_BOOL bEnHwFldBase = bEnable ? DISABLE : ENABLE; //hardware calculate field jump base address
5287 if (g_pHalMVOPCtx == NULL)
5288 {
5289 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
5290 return FALSE;
5291 }
5292 //Set 0x27[2] = 1 (enable SW dual buffer mode)
5293 HAL_WriteRegBit(SUB_REG(VOP_REG_WR), bEnDualBuff, VOP_BUF_DUAL);
5294
5295 //Set 0x38[8] = 0 (use SW dual buffer mode)
5296 HAL_WriteRegBit(SUB_REG(VOP_INFO_FROM_CODEC_H), bEnSWDualBuff, VOP_INFO_FROM_CODEC_DUAL_BUFF);
5297
5298 //Set 0x3b[7] = 0 (use MVD/HVD firmware send base)
5299 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), bEnMirrMaskBase, VOP_MASK_BASE_LSB);
5300
5301 //Set 0x3b[5] = 0 (hardware calculate field jump base address)
5302 HAL_WriteRegBit(SUB_REG(VOP_MIRROR_CFG), bEnHwFldBase, VOP_HW_FLD_BASE);
5303 g_pHalMVOPCtx->bSub3DLRAltOutput = bEnable;
5304 return TRUE;
5305 }
5306
HAL_MVOP_SubSet3DLRAltOutput(MS_BOOL bEnable)5307 MS_BOOL HAL_MVOP_SubSet3DLRAltOutput(MS_BOOL bEnable)
5308 {
5309 //Set 0x3C[2] = 1 (enable 3D L/R dual buffer line alternative output)
5310 //it works when 0x3C[0] = 1
5311 HAL_WriteRegBit(SUB_REG(VOP_MULTI_WIN_CFG0), bEnable, VOP_LR_LA_OUT);
5312 // bw saving not support: LA/SBS
5313 HAL_WriteRegBit(SUB_REG(VOP_REG_DUMMY), 0, VOP_420_BW_SAVE);
5314 HAL_WriteRegBit(SUB_REG(VOP_REG_BW_SAVE), 0, VOP_420_BW_SAVE_EX);
5315 HAL_MVOP_LoadReg();
5316
5317 g_pHalMVOPCtx->bSub3DLRAltOutput = bEnable;
5318 return TRUE;
5319 }
5320
HAL_MVOP_SubSet3DLRAltSBSOutput(MS_BOOL bEnable)5321 MS_BOOL HAL_MVOP_SubSet3DLRAltSBSOutput(MS_BOOL bEnable)
5322 {
5323 //it works when 0x3C[0] = 1 and 0x3C[2] = 1
5324 //Set 0x3C[3] = 1 (3D L/R line alternative read, side-by-side output)
5325 HAL_WriteRegBit(SUB_REG(VOP_MULTI_WIN_CFG0), bEnable, VOP_LR_LA2SBS_OUT);
5326 g_pHalMVOPCtx->bSub3DLRAltSBSOutput = bEnable;
5327 return TRUE;
5328 }
5329
HAL_MVOP_SubGet3DLRAltOutput(void)5330 MS_BOOL HAL_MVOP_SubGet3DLRAltOutput(void)
5331 {
5332 if (g_pHalMVOPCtx == NULL)
5333 {
5334 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
5335 return FALSE;
5336 }
5337 return g_pHalMVOPCtx->bSub3DLRAltOutput;
5338 }
5339
HAL_MVOP_SubGet3DLRAltSBSOutput(void)5340 MS_BOOL HAL_MVOP_SubGet3DLRAltSBSOutput(void)
5341 {
5342 return g_pHalMVOPCtx->bSub3DLRAltSBSOutput;
5343 }
5344
HAL_MVOP_SubGetOutput3DType(void)5345 EN_MVOP_Output_3D_TYPE HAL_MVOP_SubGetOutput3DType(void)
5346 {
5347 EN_MVOP_Output_3D_TYPE en3DType = E_MVOP_OUTPUT_3D_NONE;
5348 if(g_pHalMVOPCtx->bSub3DLRMode)
5349 {
5350 if(g_pHalMVOPCtx->bSub3DLRAltSBSOutput)
5351 {
5352 en3DType = E_MVOP_OUTPUT_3D_SBS;
5353 }
5354 else
5355 {
5356 en3DType = E_MVOP_OUTPUT_3D_TB;
5357 }
5358 }
5359 else if(g_pHalMVOPCtx->bSub3DLRAltOutput)
5360 {
5361 en3DType = E_MVOP_OUTPUT_3D_LA;
5362 }
5363 return en3DType;
5364 }
5365
5366
5367 #endif
5368
5369
5370 #define MVOP_INT_UF BIT0
5371 #define MVOP_INT_OF BIT1
5372 #define MVOP_INT_VSYNC BIT2
5373 #define MVOP_INT_HSYNC BIT3
5374 #define MVOP_INT_RDY BIT4
5375 #define MVOP_INT_FLD BIT5
5376 #define MVOP_INT_ALL (BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)
5377
5378 const MS_U16 u16MvopRegBase[2] = { MVOP_REG_BASE, MVOP_SUB_REG_BASE};
5379 #define MAP_REG(_id, _reg) ((_reg) - MVOP_REG_BASE + u16MvopRegBase[(_id)])
5380
HAL_MVOP_IntEnableMask(MVOP_DevID eID,MS_U8 eIntType)5381 MS_BOOL HAL_MVOP_IntEnableMask(MVOP_DevID eID, MS_U8 eIntType)
5382 {
5383 MS_BOOL bRet = TRUE;
5384 MS_U16 u16Reg = MAP_REG( eID, VOP_INT_MASK);
5385 MS_U8 u8Mask = 0;
5386
5387 u8Mask = HAL_ReadByte(u16Reg);
5388
5389 if (E_MVOP_INT_NONE != eIntType)
5390 {
5391 u8Mask = (E_MVOP_INT_VSYNC == (eIntType&E_MVOP_INT_VSYNC)) ?
5392 (u8Mask & ~MVOP_INT_VSYNC) : (u8Mask);
5393 u8Mask = (E_MVOP_INT_HSYNC == (eIntType&E_MVOP_INT_HSYNC)) ?
5394 (u8Mask & ~MVOP_INT_HSYNC) : (u8Mask);
5395 u8Mask = (E_MVOP_INT_FDCHNG == (eIntType&E_MVOP_INT_FDCHNG)) ?
5396 (u8Mask & ~MVOP_INT_FLD) : (u8Mask);
5397 u8Mask = (E_MVOP_INT_RDY == (eIntType&E_MVOP_INT_RDY)) ?
5398 (u8Mask & ~MVOP_INT_RDY) : (u8Mask);
5399 u8Mask = (E_MVOP_INT_BUFF_UF == (eIntType&E_MVOP_INT_BUFF_UF)) ?
5400 (u8Mask & ~MVOP_INT_UF) : (u8Mask);
5401 u8Mask = (E_MVOP_INT_BUFF_OF == (eIntType&E_MVOP_INT_BUFF_OF)) ?
5402 (u8Mask & ~MVOP_INT_OF) : (u8Mask);
5403 }
5404 else //mask all
5405 {
5406 u8Mask |= MVOP_INT_ALL;
5407 }
5408
5409 //MVOP_PRINTF("u8Mask %x ", u8Mask);
5410 HAL_WriteByteMask(u16Reg, u8Mask, MVOP_INT_ALL);
5411 //u8Mask = HAL_ReadByte(u16Reg);
5412 //MVOP_PRINTF("==> %x \n", u8Mask);
5413 return bRet;
5414 }
5415
HAL_MVOP_IntGetStatus(MVOP_DevID eID)5416 MS_U8 HAL_MVOP_IntGetStatus(MVOP_DevID eID)
5417 {
5418 MS_U8 u8IntVal = 0;
5419 MS_U8 u8IntType = E_MVOP_INT_NONE;
5420 MS_U16 u16Reg = MAP_REG(eID, (VOP_INT_MASK+1));
5421
5422 u8IntVal = HAL_ReadByte(u16Reg) & MVOP_INT_ALL;
5423 //MVOP_PRINTF("u8IntVal %x\n", u8IntVal);
5424 if ((u8IntVal & MVOP_INT_VSYNC) == MVOP_INT_VSYNC)
5425 {
5426 u8IntType |= E_MVOP_INT_VSYNC;
5427 }
5428 if ((u8IntVal & MVOP_INT_HSYNC) == MVOP_INT_HSYNC)
5429 {
5430 u8IntType |= E_MVOP_INT_HSYNC;
5431 }
5432 if ((u8IntVal & MVOP_INT_FLD) == MVOP_INT_FLD)
5433 {
5434 u8IntType |= E_MVOP_INT_FDCHNG;
5435 }
5436 if ((u8IntVal & MVOP_INT_RDY) == MVOP_INT_RDY)
5437 {
5438 u8IntType |= E_MVOP_INT_RDY;
5439 }
5440 if ((u8IntVal & MVOP_INT_UF) == MVOP_INT_UF)
5441 {
5442 u8IntType |= E_MVOP_INT_BUFF_UF;
5443 }
5444 if ((u8IntVal & MVOP_INT_OF) == MVOP_INT_OF)
5445 {
5446 u8IntType |= E_MVOP_INT_BUFF_OF;
5447 }
5448 return u8IntType;
5449 }
5450
5451 #if 0
5452 void HAL_MVOP_SetStartX(MS_U16 u16Length)
5453 {
5454 if(g_pHalMVOPCtx == NULL)
5455 {
5456 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
5457 return;
5458 }
5459 g_pHalMVOPCtx->g_u16SetStartX = u16Length;
5460 HAL_WriteByte(VOP_REG_CROP_HSTART, u16Length & 0xff);
5461 HAL_WriteByte((VOP_REG_CROP_HSTART + 1),((u16Length) >> (8)) & (0x1f));
5462 // Write trigger
5463 HAL_MVOP_LoadReg();
5464 }
5465
5466
5467 void HAL_MVOP_SetStartY(MS_U16 u16Length, MS_BOOL bIs4Align)
5468 {
5469 if(g_pHalMVOPCtx == NULL)
5470 {
5471 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
5472 return;
5473 }
5474 g_pHalMVOPCtx->g_u16SetStartY = u16Length;
5475 g_pHalMVOPCtx->g_bIsY4Align = bIs4Align;
5476 HAL_WriteByte(VOP_REG_CROP_VSTART, u16Length & 0xff);
5477 HAL_WriteByte((VOP_REG_CROP_VSTART + 1), ((u16Length) >> (8)) & (0x1f));
5478 // Write trigger
5479 HAL_MVOP_LoadReg();
5480 }
5481
5482
5483 void HAL_MVOP_SetPicWidthMinus(MS_U16 u16Sizes)
5484 {
5485 if(g_pHalMVOPCtx == NULL)
5486 {
5487 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
5488 return;
5489 }
5490 if(u16Sizes == 0)
5491 {
5492 HAL_WriteByte(VOP_REG_CROP_HSIZE, u16Sizes);
5493 HAL_WriteByte((VOP_REG_CROP_HSIZE + 1), u16Sizes);
5494 }
5495 else
5496 {
5497 u16Sizes = u16Sizes + 1 - g_pHalMVOPCtx->g_u16SetStartX ;
5498 HAL_WriteByte(VOP_REG_CROP_HSIZE, u16Sizes & 0xff);
5499 HAL_WriteByte((VOP_REG_CROP_HSIZE + 1), ((u16Sizes) >> (8)) & (0x1f));
5500 }
5501 g_pHalMVOPCtx->g_u16SetXSize= u16Sizes;
5502 // Write trigger
5503 HAL_MVOP_LoadReg();
5504 }
5505
5506 void HAL_MVOP_SetPicHeightMinus(MS_U16 u16Sizes)
5507 {
5508 MS_U32 u32YOffset=0;
5509 MS_U32 u32UVOffset=0;
5510 MS_BOOL bIsInterlace = 0;
5511
5512 if(g_pHalMVOPCtx == NULL)
5513 {
5514 MVOP_DBG(MVOP_PRINTF("%s g_pHalMVOPCtx is NULL pointer\n", __FUNCTION__);)
5515 return;
5516 }
5517
5518 if(u16Sizes == 0)
5519 {
5520 HAL_WriteByte(VOP_REG_CROP_VSIZE, u16Sizes);
5521 HAL_WriteByte((VOP_REG_CROP_VSIZE + 1), u16Sizes);
5522 }
5523 else
5524 {
5525 u16Sizes = u16Sizes + 1 - g_pHalMVOPCtx->g_u16SetStartY ;
5526 if(g_pHalMVOPCtx->g_bIsY4Align)
5527 u16Sizes -= 2;
5528
5529 HAL_WriteByte(VOP_REG_CROP_VSIZE, (u16Sizes) & 0xff);
5530 HAL_WriteByte((VOP_REG_CROP_VSIZE + 1), ((u16Sizes) >> (8)) & (0x1f));
5531 }
5532 g_pHalMVOPCtx->g_u16SetYSize= u16Sizes;
5533 //***********************************************************************************//
5534 //@clippers crop sw patch
5535 // Synchronization: video broken, looks like pitch incorrect.
5536 // Hit condition: (g_pHalMVOPCtx->g_u16SetStartX%16)+(g_pHalMVOPCtx->g_u16SetXSize%16) > 16
5537 // Fix: after monet
5538 // Limitation: have to set MDrv_MVOP_SetImageWidthHight after:
5539 // MDrv_MVOP_SetInputCfg / MDrv_MVOP_SetOutputCfg / MDrv_MVOP_SetBaseAdd / MDrv_MVOP_SetStartPos
5540 //***********************************************************************************//
5541 if((g_pHalMVOPCtx->g_u16SetXSize == 0) && (g_pHalMVOPCtx->g_u16SetYSize == 0))
5542 {
5543 HAL_WriteRegBit(VOP_REG_SINGLE_3D_L, 0, VOP_FORCE_SKIP);
5544 HAL_WriteByteMask(VOP_REG_SINGLE_3D_L, 0, VOP_SKIP_SIZE_LVIEW);
5545 HAL_WriteByteMask(VOP_REG_SINGLE_3D_H, 0, VOP_SKIP_SIZE_RVIEW);
5546 HAL_WriteRegBit(VOP_REG_ENABLE_SKIP, 0, VOP_SKIP_LVIEW);
5547 HAL_WriteRegBit(VOP_REG_ENABLE_SKIP, 0, VOP_SKIP_RVIEW);
5548 if(g_pHalMVOPCtx->g_bIsSetCrop == TRUE)
5549 {
5550 u32YOffset = HAL_MVOP_GetYBaseAdd() +4;
5551 u32UVOffset = HAL_MVOP_GetUVBaseAdd() +4;
5552 bIsInterlace = HAL_ReadRegBit(VOP_CTRL0, BIT7);
5553 HAL_MVOP_SetYUVBaseAdd(u32YOffset<<3, u32UVOffset<<3, !bIsInterlace,g_pHalMVOPCtx->bIs422);
5554 g_pHalMVOPCtx->g_bIsSetCrop = FALSE;
5555 }
5556 HAL_MVOP_LoadReg();
5557 return;
5558 }
5559 MVOP_DBG("[Warning] clippers crop may hit hw bug: g_u16SetStartX = %d, g_u16SetXSize = %d\n",g_pHalMVOPCtx->g_u16SetStartX,g_pHalMVOPCtx->g_u16SetXSize);
5560 if(((g_pHalMVOPCtx->g_u16SetStartX%16)+(g_pHalMVOPCtx->g_u16SetXSize%16) > 16) && (g_pHalMVOPCtx->bIs422))
5561 {
5562 HAL_WriteRegBit(VOP_REG_SINGLE_3D_L, 1, VOP_FORCE_SKIP);
5563 HAL_WriteByteMask(VOP_REG_SINGLE_3D_L, (g_pHalMVOPCtx->g_u16SetStartX%16), VOP_SKIP_SIZE_LVIEW);
5564 HAL_WriteByteMask(VOP_REG_SINGLE_3D_H, (g_pHalMVOPCtx->g_u16SetStartX%16), VOP_SKIP_SIZE_RVIEW);
5565 HAL_WriteRegBit(VOP_REG_ENABLE_SKIP, 1, VOP_SKIP_LVIEW);
5566 HAL_WriteRegBit(VOP_REG_ENABLE_SKIP, 1, VOP_SKIP_RVIEW);
5567 if(g_pHalMVOPCtx->g_bIsSetCrop == FALSE)
5568 {
5569 u32YOffset = HAL_MVOP_GetYBaseAdd();
5570 u32UVOffset = HAL_MVOP_GetUVBaseAdd();
5571 if((u32YOffset < 4) || (u32UVOffset < 4))
5572 return;
5573
5574 u32YOffset -= 4;
5575 u32UVOffset -= 4;
5576 bIsInterlace = HAL_ReadRegBit(VOP_CTRL0, BIT7);
5577 HAL_MVOP_SetYUVBaseAdd(u32YOffset<<3, u32UVOffset<<3, !bIsInterlace,g_pHalMVOPCtx->bIs422);
5578 g_pHalMVOPCtx->g_bIsSetCrop = TRUE;
5579 }
5580 }
5581 // Write trigger
5582 HAL_MVOP_LoadReg();
5583 }
5584 #endif
HAL_MVOP_MaskDBRegCtrl(MVOP_DevID eID,MS_BOOL bEnable,MVOPMSAKDBREGCTRL eModeCtrl)5585 void HAL_MVOP_MaskDBRegCtrl(MVOP_DevID eID, MS_BOOL bEnable ,MVOPMSAKDBREGCTRL eModeCtrl)
5586 {
5587 MS_U8 regval;
5588 MS_U8 u8Arg;
5589
5590 if (eModeCtrl> E_MVOP_INV_OP_VS)
5591 {
5592 return;
5593 }
5594 #if 0
5595 else if (eModeCtrl >= E_MVOP_CHKSUM_422_SWAP)
5596 {
5597 regval = HAL_ReadByte(MVOP_MASK_DB_REG1);
5598 }
5599 else
5600 {
5601 regval = HAL_ReadByte(MVOP_MASK_DB_REG0);
5602 }
5603 #endif
5604
5605 switch(eID)
5606 {
5607 case E_MVOP_DEV_0:
5608 {
5609 switch(eModeCtrl)
5610 {
5611 case E_MVOP_MASK_DB_REG:
5612 //u8Arg = MVOP_MASK_DB_REG;
5613 break;
5614 case E_MVOP_EN_DB_REG:
5615 //u8Arg = MVOP_EN_DB_REG;
5616 break;
5617 case E_MVOP_DEBUG_SEL:
5618 //u8Arg = MVOP_DEBUG_SEL;
5619 break;
5620 case E_MVOP_UPDATE_SEL:
5621 //u8Arg = MVOP_UPDATE_SEL;
5622 break;
5623 case E_MVOP_RST_START_SEL:
5624 //u8Arg = MVOP_RST_START_SEL;
5625 break;
5626 case E_MVOP_SC_VSYNC_SEL:
5627 //u8Arg = MVOP_SC_VSYNC_SEL;
5628 break;
5629 case E_MVOP_READ_IP_BASE_SEL:
5630 //u8Arg = MVOP_READ_IP_BASE_SEL;
5631 break;
5632 case E_MVOP_CHKSUM_422_SWAP:
5633 //u8Arg = MVOP_CHKSUM_422_SWAP;
5634 break;
5635 case E_MVOP_CHKSUM_FULL_C:
5636 //u8Arg = MVOP_CHKSUM_FULL_C;
5637 break;
5638 case E_MVOP_OFF_LATCH_CRC:
5639 //u8Arg = MVOP_OFF_LATCH_CRC;
5640 break;
5641 case E_MVOP_SEL_OP_FIELD:
5642 {
5643 u8Arg = VOP_MVD_VS_MD;
5644 regval = HAL_ReadByte(VOP_CTRL0);
5645 if ( bEnable )
5646 {
5647 regval &= ~u8Arg;
5648 }
5649 else
5650 {
5651 regval |= u8Arg;
5652 }
5653 HAL_WriteByte(VOP_CTRL0, regval);
5654
5655 u8Arg = VOP_RGB_FILED_BYPASS;
5656 regval = HAL_ReadByte(VOP_REG_DUMMY_3D_1);
5657 if ( bEnable )
5658 {
5659 regval &= ~u8Arg;
5660 }
5661 else
5662 {
5663 regval |= u8Arg;
5664 }
5665 HAL_WriteByte(VOP_REG_DUMMY_3D_1, regval);
5666 //xc use bob mode(only use one field de-interlace)
5667 // xc receive top/bot toggle signal, but only one field
5668 #if 0
5669 // xc receive top/bot toggle signal, but only one field
5670 u8Arg = VOP_REF_SELF_FLD;
5671 regval = HAL_ReadByte(VOP_MIRROR_CFG_HI);
5672 if ( bEnable )
5673 {
5674 regval |= u8Arg;
5675 }
5676 else
5677 {
5678 regval &= ~u8Arg;
5679 }
5680 HAL_WriteByte(VOP_MIRROR_CFG_HI, regval);
5681 //if hardwired mode
5682 if(BIT2 != HAL_ReadRegBit(VOP_MPG_JPG_SWITCH, BIT2))
5683 {
5684 if ( bEnable )
5685 {
5686 HAL_WriteRegBit(VOP_INFO_FROM_CODEC_L, 0, VOP_INFO_FROM_CODEC_FIELD);
5687 }
5688 else
5689 {
5690 HAL_WriteRegBit(VOP_INFO_FROM_CODEC_L, 1, VOP_INFO_FROM_CODEC_FIELD);
5691 }
5692 }
5693 #endif
5694 HAL_MVOP_LoadReg();
5695 break;
5696 }
5697 case E_MVOP_INV_OP_FIELD:
5698 //u8Arg = MVOP_INV_OP_FIELD;
5699 break;
5700 case E_MVOP_INV_OP_VS:
5701 //u8Arg = MVOP_INV_OP_VS;
5702 break;
5703 default:
5704 //u8Arg = 0x0;
5705 break;
5706
5707 }
5708 break;
5709 }
5710 #if MVOP_SUPPORT_SUB
5711 case E_MVOP_DEV_1:
5712 {
5713 switch(eModeCtrl)
5714 {
5715 case E_MVOP_MASK_DB_REG:
5716 //u8Arg = MVOP_MASK_DB_REG;
5717 break;
5718 case E_MVOP_EN_DB_REG:
5719 //u8Arg = MVOP_EN_DB_REG;
5720 break;
5721 case E_MVOP_DEBUG_SEL:
5722 //u8Arg = MVOP_DEBUG_SEL;
5723 break;
5724 case E_MVOP_UPDATE_SEL:
5725 //u8Arg = MVOP_UPDATE_SEL;
5726 break;
5727 case E_MVOP_RST_START_SEL:
5728 //u8Arg = MVOP_RST_START_SEL;
5729 break;
5730 case E_MVOP_SC_VSYNC_SEL:
5731 //u8Arg = MVOP_SC_VSYNC_SEL;
5732 break;
5733 case E_MVOP_READ_IP_BASE_SEL:
5734 //u8Arg = MVOP_READ_IP_BASE_SEL;
5735 break;
5736 case E_MVOP_CHKSUM_422_SWAP:
5737 //u8Arg = MVOP_CHKSUM_422_SWAP;
5738 break;
5739 case E_MVOP_CHKSUM_FULL_C:
5740 //u8Arg = MVOP_CHKSUM_FULL_C;
5741 break;
5742 case E_MVOP_OFF_LATCH_CRC:
5743 //u8Arg = MVOP_OFF_LATCH_CRC;
5744 break;
5745 case E_MVOP_SEL_OP_FIELD:
5746 {
5747 u8Arg = VOP_MVD_VS_MD;
5748 regval = HAL_ReadByte(SUB_REG(VOP_CTRL0));
5749 if ( bEnable )
5750 {
5751 regval &= ~u8Arg;
5752 }
5753 else
5754 {
5755 regval |= u8Arg;
5756 }
5757 HAL_WriteByte(SUB_REG(VOP_CTRL0), regval);
5758
5759 u8Arg = VOP_RGB_FILED_BYPASS;
5760 regval = HAL_ReadByte(SUB_REG(VOP_REG_DUMMY_3D_1));
5761 if ( bEnable )
5762 {
5763 regval &= ~u8Arg;
5764 }
5765 else
5766 {
5767 regval |= u8Arg;
5768 }
5769 HAL_WriteByte(SUB_REG(VOP_REG_DUMMY_3D_1), regval);
5770 //xc use bob mode(only use one field de-interlace)
5771 // xc receive top/bot toggle signal, but only one field
5772 #if 0
5773 // xc receive top/bot toggle signal, but only one field
5774 u8Arg = VOP_REF_SELF_FLD;
5775 regval = HAL_ReadByte(VOP_MIRROR_CFG_HI);
5776 if ( bEnable )
5777 {
5778 regval |= u8Arg;
5779 }
5780 else
5781 {
5782 regval &= ~u8Arg;
5783 }
5784 HAL_WriteByte(VOP_MIRROR_CFG_HI, regval);
5785 //if hardwired mode
5786 if(BIT2 != HAL_ReadRegBit(VOP_MPG_JPG_SWITCH, BIT2))
5787 {
5788 if ( bEnable )
5789 {
5790 HAL_WriteRegBit(VOP_INFO_FROM_CODEC_L, 0, VOP_INFO_FROM_CODEC_FIELD);
5791 }
5792 else
5793 {
5794 HAL_WriteRegBit(VOP_INFO_FROM_CODEC_L, 1, VOP_INFO_FROM_CODEC_FIELD);
5795 }
5796 }
5797 #endif
5798 HAL_MVOP_SubLoadReg();
5799 break;
5800 }
5801 case E_MVOP_INV_OP_FIELD:
5802 //u8Arg = MVOP_INV_OP_FIELD;
5803 break;
5804 case E_MVOP_INV_OP_VS:
5805 //u8Arg = MVOP_INV_OP_VS;
5806 break;
5807 default:
5808 //u8Arg = 0x0;
5809 break;
5810
5811 }
5812 break;
5813 }
5814 #endif
5815 default:
5816 break;
5817 }
5818 #if 0
5819 if ( bEnable )
5820 {
5821 regval |= u8Arg;
5822 }
5823 else
5824 {
5825 regval &= ~u8Arg;
5826 }
5827 if (eModeCtrl >= E_MVOP_CHKSUM_422_SWAP)
5828 {
5829 HAL_WriteByte(MVOP_MASK_DB_REG1, regval);
5830 }
5831 else
5832 {
5833 HAL_WriteByte(MVOP_MASK_DB_REG0, regval);
5834 }
5835 #endif
5836
5837
5838 }
5839
5840
5841 //patch for Kappa
HAL_MVOP_SetDeb2MVDFrameModeCtrl(MVOP_DevID eID,MS_BOOL bEnable,MVOPDEB2MVDFRAMECTRL eModeCtrl)5842 void HAL_MVOP_SetDeb2MVDFrameModeCtrl(MVOP_DevID eID, MS_BOOL bEnable, MVOPDEB2MVDFRAMECTRL eModeCtrl)
5843 {
5844 MS_U8 regval;
5845 MS_U8 u8Arg;
5846
5847 switch(eID)
5848 {
5849 case E_MVOP_DEV_0:
5850 {
5851 regval = HAL_ReadByte(VOP_INFO_FROM_CODEC_L);
5852 switch (eModeCtrl)
5853 {
5854 case E_MVOP_DEB2MVD_FRAME_MODE:
5855 u8Arg = 0x0;
5856 break;
5857 case E_MVOP_DEB2MVD_FIELD_INV:
5858 u8Arg = 0x0;
5859 break;
5860 case E_MVOP_SIZE_FROM_MVD:
5861 u8Arg = VOP_INFO_FROM_CODEC_SIZE;
5862 if (bEnable)
5863 {
5864 //crop = 0, then size could be from vdec.
5865 HAL_MVOP_SetPicWidthMinus(E_MVOP_DEV_0, 0, 0);
5866 HAL_MVOP_SetPicHeightMinus(E_MVOP_DEV_0, 0, 0);
5867 }
5868 break;
5869 case E_MVOP_SEQ_FROM_MVD:
5870 u8Arg = 0x0;
5871 break;
5872 default:
5873 u8Arg = 0x0;
5874 break;
5875 }
5876
5877 if (bEnable)
5878 {
5879 regval |= u8Arg;
5880 }
5881 else
5882 {
5883 regval &= ~u8Arg;
5884 }
5885
5886 HAL_WriteByte(VOP_INFO_FROM_CODEC_L, regval);
5887
5888 // Write trigger
5889 HAL_MVOP_LoadReg();
5890 }
5891 break;
5892 #if MVOP_SUPPORT_SUB
5893 case E_MVOP_DEV_1:
5894 {
5895 regval = HAL_ReadByte(SUB_REG(VOP_INFO_FROM_CODEC_L));
5896 switch (eModeCtrl)
5897 {
5898 case E_MVOP_DEB2MVD_FRAME_MODE:
5899 u8Arg = 0x0;
5900 break;
5901 case E_MVOP_DEB2MVD_FIELD_INV:
5902 u8Arg = 0x0;
5903 break;
5904 case E_MVOP_SIZE_FROM_MVD:
5905 u8Arg = VOP_INFO_FROM_CODEC_SIZE;
5906 if (bEnable)
5907 {
5908 //crop = 0, then size could be from vdec.
5909 HAL_MVOP_SetPicWidthMinus(SUB_REG(E_MVOP_DEV_0), 0, 0);
5910 HAL_MVOP_SetPicHeightMinus(SUB_REG(E_MVOP_DEV_0), 0, 0);
5911 }
5912 break;
5913 case E_MVOP_SEQ_FROM_MVD:
5914 u8Arg = 0x0;
5915 break;
5916 default:
5917 u8Arg = 0x0;
5918 break;
5919 }
5920
5921 if (bEnable)
5922 {
5923 regval |= u8Arg;
5924 }
5925 else
5926 {
5927 regval &= ~u8Arg;
5928 }
5929
5930 HAL_WriteByte(SUB_REG(VOP_INFO_FROM_CODEC_L), regval);
5931
5932 // Write trigger
5933 HAL_MVOP_SubLoadReg();
5934 }
5935 break;
5936 #endif
5937 default:
5938 break;
5939 }
5940
5941 }
5942
5943 // for kappa
HAL_MVOP_BaseFromIPCtrl(MVOP_DevID eID,MS_BOOL bEnable,MVOPBASEFROMIPCTRL eModeCtrl)5944 void HAL_MVOP_BaseFromIPCtrl(MVOP_DevID eID, MS_BOOL bEnable ,MVOPBASEFROMIPCTRL eModeCtrl )
5945 {
5946 MS_U8 regval;
5947 MS_U8 u8Arg;
5948
5949 if ( eModeCtrl>
5950 #if NO_MVOP_PATCH
5951 E_MVOP_FD_MASK_INV)
5952 #else
5953 E_MVOP_SIZE_FROM_MVD_PATCH)
5954 #endif
5955 {
5956 return;
5957 }
5958 else if (eModeCtrl >= E_MVOP_FMT_FROM_MVD)
5959 {
5960 regval = HAL_ReadByte(VOP_FD_MASK); // ox30
5961 }
5962 else
5963 {
5964 regval = HAL_ReadByte(VOP_INFO_FROM_CODEC_L); //0x38
5965 }
5966
5967 switch(eModeCtrl)
5968 {
5969 case E_MVOP_BASE_FROM_IP:
5970 u8Arg = 0x0;
5971 break;
5972 case E_MVOP_SRC_FROM_MVD:
5973 u8Arg = 0x0;
5974 break;
5975 case E_MVOP_FIELD_FROM_MVD:
5976 u8Arg = 0x0;
5977 break;
5978 case E_MVOP_FIELD_FROM_MVD_INV:
5979 u8Arg = 0x0;
5980 break;
5981 case E_MVOP_PITCH_FROM_IP:
5982 u8Arg = 0x0;
5983 break;
5984 case E_MVOP_FMT_FROM_MVD:
5985 u8Arg = 0x0;
5986 break;
5987 case E_MVOP_FD_MASK_CLR:
5988 u8Arg = VOP_FD_MASK_CLR;
5989 break;
5990 case E_MVOP_FD_MASK_INV:
5991 u8Arg = VOP_FD_MASK_INV;
5992 break;
5993 #if (NO_MVOP_PATCH == 0)
5994 case E_MVOP_SIZE_FROM_MVD_PATCH:
5995 u8Arg = 0x0;
5996 break;
5997 case E_MVOP_SEQ_FROM_MVD_PATCH:
5998 u8Arg = 0x0;
5999 break;
6000 #endif
6001 default:
6002 u8Arg = 0x0;
6003 break;
6004
6005 }
6006 if ( bEnable )
6007 {
6008 regval |= u8Arg;
6009 }
6010 else
6011 {
6012 regval &= ~u8Arg;
6013 }
6014 if (eModeCtrl >= E_MVOP_FMT_FROM_MVD)
6015 {
6016 HAL_WriteByte(VOP_FD_MASK, regval);
6017 }
6018 else
6019 {
6020 HAL_WriteByte(VOP_INFO_FROM_CODEC_L, regval);
6021 }
6022
6023
6024 }
6025
HAL_MVOP_SetMFDECInfo(MVOP_DevID eID,HALMVOPMFDECINFO * pMFDECInfo)6026 void HAL_MVOP_SetMFDECInfo(MVOP_DevID eID, HALMVOPMFDECINFO *pMFDECInfo)
6027 {
6028 }
6029
6030