1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _HALMAC_TYPE_H_
3 #define _HALMAC_TYPE_H_
4
5 #include "halmac_2_platform.h"
6 #include "halmac_hw_cfg.h"
7 #include "halmac_fw_info.h"
8
9
10 #define IN
11 #define OUT
12 #define INOUT
13 #define VOID void
14
15 #define HALMAC_SCAN_CH_NUM_MAX 28
16 #define HALMAC_BCN_IE_BMP_SIZE 24 /* ID0~ID191, 192/8=24 */
17 #define HALMAC_PHY_PARAMETER_SIZE 12
18 #define HALMAC_PHY_PARAMETER_MAX_NUM 128
19 #define HALMAC_MAX_SSID_LEN 32
20 #define HALMAC_SUPPORT_NLO_NUM 16
21 #define HALMAC_SUPPORT_PROBE_REQ_NUM 8
22 #define HALMC_DDMA_POLLING_COUNT 1000
23 #define API_ARRAY_SIZE 32
24
25 /* platform api */
26 #define PLATFORM_SDIO_CMD52_READ pHalmac_adapter->pHalmac_platform_api->SDIO_CMD52_READ
27 #define PLATFORM_SDIO_CMD53_READ_8 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_READ_8
28 #define PLATFORM_SDIO_CMD53_READ_16 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_READ_16
29 #define PLATFORM_SDIO_CMD53_READ_32 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_READ_32
30 #define PLATFORM_SDIO_CMD52_WRITE pHalmac_adapter->pHalmac_platform_api->SDIO_CMD52_WRITE
31 #define PLATFORM_SDIO_CMD53_WRITE_8 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_WRITE_8
32 #define PLATFORM_SDIO_CMD53_WRITE_16 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_WRITE_16
33 #define PLATFORM_SDIO_CMD53_WRITE_32 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_WRITE_32
34
35 #define PLATFORM_REG_READ_8 pHalmac_adapter->pHalmac_platform_api->REG_READ_8
36 #define PLATFORM_REG_READ_16 pHalmac_adapter->pHalmac_platform_api->REG_READ_16
37 #define PLATFORM_REG_READ_32 pHalmac_adapter->pHalmac_platform_api->REG_READ_32
38 #define PLATFORM_REG_WRITE_8 pHalmac_adapter->pHalmac_platform_api->REG_WRITE_8
39 #define PLATFORM_REG_WRITE_16 pHalmac_adapter->pHalmac_platform_api->REG_WRITE_16
40 #define PLATFORM_REG_WRITE_32 pHalmac_adapter->pHalmac_platform_api->REG_WRITE_32
41
42 #define PLATFORM_SEND_RSVD_PAGE pHalmac_adapter->pHalmac_platform_api->SEND_RSVD_PAGE
43 #define PLATFORM_SEND_H2C_PKT pHalmac_adapter->pHalmac_platform_api->SEND_H2C_PKT
44
45 #define PLATFORM_RTL_FREE pHalmac_adapter->pHalmac_platform_api->RTL_FREE
46 #define PLATFORM_RTL_MALLOC pHalmac_adapter->pHalmac_platform_api->RTL_MALLOC
47 #define PLATFORM_RTL_MEMCPY pHalmac_adapter->pHalmac_platform_api->RTL_MEMCPY
48 #define PLATFORM_RTL_MEMSET pHalmac_adapter->pHalmac_platform_api->RTL_MEMSET
49 #define PLATFORM_RTL_DELAY_US pHalmac_adapter->pHalmac_platform_api->RTL_DELAY_US
50
51 #define PLATFORM_MUTEX_INIT pHalmac_adapter->pHalmac_platform_api->MUTEX_INIT
52 #define PLATFORM_MUTEX_DEINIT pHalmac_adapter->pHalmac_platform_api->MUTEX_DEINIT
53 #define PLATFORM_MUTEX_LOCK pHalmac_adapter->pHalmac_platform_api->MUTEX_LOCK
54 #define PLATFORM_MUTEX_UNLOCK pHalmac_adapter->pHalmac_platform_api->MUTEX_UNLOCK
55
56 #define PLATFORM_EVENT_INDICATION pHalmac_adapter->pHalmac_platform_api->EVENT_INDICATION
57
58
59 #if HALMAC_DBG_MSG_ENABLE
60 #define PLATFORM_MSG_PRINT pHalmac_adapter->pHalmac_platform_api->MSG_PRINT
61 #else
62 #define PLATFORM_MSG_PRINT(pDriver_adapter, msg_type, msg_level, fmt, ...)
63 #endif
64
65 #if HALMAC_PLATFORM_TESTPROGRAM
66 #define PLATFORM_WRITE_DATA_SDIO_ADDR pHalmac_adapter->pHalmac_platform_api->WRITE_DATA_SDIO_ADDR
67 #define PLATFORM_WRITE_DATA_USB_BULKOUT_ID pHalmac_adapter->pHalmac_platform_api->WRITE_DATA_USB_BULKOUT_ID
68 #define PLATFORM_WRITE_DATA_PCIE_QUEUE pHalmac_adapter->pHalmac_platform_api->WRITE_DATA_PCIE_QUEUE
69 #define PLATFORM_READ_DATA pHalmac_adapter->pHalmac_platform_api->READ_DATA
70 #endif
71
72 #define HALMAC_REG_READ_8 pHalmac_api->halmac_reg_read_8
73 #define HALMAC_REG_READ_16 pHalmac_api->halmac_reg_read_16
74 #define HALMAC_REG_READ_32 pHalmac_api->halmac_reg_read_32
75 #define HALMAC_REG_WRITE_8 pHalmac_api->halmac_reg_write_8
76 #define HALMAC_REG_WRITE_16 pHalmac_api->halmac_reg_write_16
77 #define HALMAC_REG_WRITE_32 pHalmac_api->halmac_reg_write_32
78
79 /* Swap Little-endian <-> Big-endia*/
80 #define SWAP32(x) ((u32)( \
81 (((u32)(x) & (u32)0x000000ff) << 24) | \
82 (((u32)(x) & (u32)0x0000ff00) << 8) | \
83 (((u32)(x) & (u32)0x00ff0000) >> 8) | \
84 (((u32)(x) & (u32)0xff000000) >> 24)))
85
86 #define SWAP16(x) ((u16)( \
87 (((u16)(x) & (u16)0x00ff) << 8) | \
88 (((u16)(x) & (u16)0xff00) >> 8)))
89
90 /*1->Little endian 0->Big endian*/
91 #if HALMAC_SYSTEM_ENDIAN
92 #ifndef rtk_le16_to_cpu
93 #define rtk_cpu_to_le32(x) ((u32)(x))
94 #define rtk_le32_to_cpu(x) ((u32)(x))
95 #define rtk_cpu_to_le16(x) ((u16)(x))
96 #define rtk_le16_to_cpu(x) ((u16)(x))
97 #define rtk_cpu_to_be32(x) SWAP32((x))
98 #define rtk_be32_to_cpu(x) SWAP32((x))
99 #define rtk_cpu_to_be16(x) SWAP16((x))
100 #define rtk_be16_to_cpu(x) SWAP16((x))
101 #endif
102 #else
103 #ifndef rtk_le16_to_cpu
104 #define rtk_cpu_to_le32(x) SWAP32((x))
105 #define rtk_le32_to_cpu(x) SWAP32((x))
106 #define rtk_cpu_to_le16(x) SWAP16((x))
107 #define rtk_le16_to_cpu(x) SWAP16((x))
108 #define rtk_cpu_to_be32(x) ((u32)(x))
109 #define rtk_be32_to_cpu(x) ((u32)(x))
110 #define rtk_cpu_to_be16(x) ((u16)(x))
111 #define rtk_be16_to_cpu(x) ((u16)(x))
112 #endif
113 #endif
114
115 #define HALMAC_ALIGN(x, a) HALMAC_ALIGN_MASK(x, (a) - 1)
116 #define HALMAC_ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask))
117
118 /* #if !HALMAC_PLATFORM_WINDOWS */
119 #if !((HALMAC_PLATFORM_WINDOWS == 1) && (HALMAC_PLATFORM_TESTPROGRAM == 0))
120
121 /* Byte Swapping routine */
122 #ifndef EF1Byte
123 #define EF1Byte (u8)
124 #endif
125
126 #ifndef EF2Byte
127 #define EF2Byte rtk_le16_to_cpu
128 #endif
129
130 #ifndef EF4Byte
131 #define EF4Byte rtk_le32_to_cpu
132 #endif
133
134 /* Example:
135 * BIT_LEN_MASK_32(0) => 0x00000000
136 * BIT_LEN_MASK_32(1) => 0x00000001
137 * BIT_LEN_MASK_32(2) => 0x00000003
138 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
139 */
140 #ifndef BIT_LEN_MASK_32
141 #define BIT_LEN_MASK_32(__BitLen) \
142 (0xFFFFFFFF >> (32 - (__BitLen)))
143 #endif
144
145 /* Example:
146 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
147 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
148 */
149 #ifndef BIT_OFFSET_LEN_MASK_32
150 #define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) \
151 (BIT_LEN_MASK_32(__BitLen) << (__BitOffset))
152 #endif
153
154 /* Return 4-byte value in host byte ordering from
155 * 4-byte pointer in litten-endian system
156 */
157 #ifndef LE_P4BYTE_TO_HOST_4BYTE
158 #define LE_P4BYTE_TO_HOST_4BYTE(__pStart) \
159 (EF4Byte(*((u32 *)(__pStart))))
160 #endif
161
162
163 /* Translate subfield (continuous bits in little-endian) of
164 * 4-byte value in litten byte to 4-byte value in host byte ordering
165 */
166 #ifndef LE_BITS_TO_4BYTE
167 #define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
168 ( \
169 (LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset)) \
170 & \
171 BIT_LEN_MASK_32(__BitLen) \
172 )
173 #endif
174
175 /* Mask subfield (continuous bits in little-endian) of 4-byte
176 * value in litten byte oredering and return the result in 4-byte
177 * value in host byte ordering
178 */
179 #ifndef LE_BITS_CLEARED_TO_4BYTE
180 #define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
181 ( \
182 LE_P4BYTE_TO_HOST_4BYTE(__pStart) \
183 & \
184 (~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen)) \
185 )
186 #endif
187
188 /* Set subfield of little-endian 4-byte value to specified value */
189 #ifndef SET_BITS_TO_LE_4BYTE
190 #define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \
191 do { \
192 *((u32 *)(__pStart)) = \
193 EF4Byte( \
194 LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
195 | \
196 ((((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset)) \
197 ); \
198 } while (0)
199 #endif
200
201 #ifndef HALMAC_BIT_OFFSET_VAL_MASK_32
202 #define HALMAC_BIT_OFFSET_VAL_MASK_32(__BitVal, __BitOffset) \
203 (__BitVal << (__BitOffset))
204 #endif
205
206 #ifndef SET_MEM_OP
207 #define SET_MEM_OP(Dw, Value32, Mask, Shift) \
208 (((Dw) & ~((Mask) << (Shift))) | (((Value32) & (Mask)) << (Shift)))
209 #endif
210
211 #ifndef HALMAC_SET_DESC_FIELD_CLR
212 #define HALMAC_SET_DESC_FIELD_CLR(Dw, Value32, Mask, Shift) \
213 (Dw = (rtk_cpu_to_le32(SET_MEM_OP(rtk_cpu_to_le32(Dw), Value32, Mask, Shift))))
214 #endif
215
216 #ifndef HALMAC_SET_DESC_FIELD_NO_CLR
217 #define HALMAC_SET_DESC_FIELD_NO_CLR(Dw, Value32, Mask, Shift) \
218 (Dw |= (rtk_cpu_to_le32(((Value32) & (Mask)) << (Shift))))
219 #endif
220
221 #ifndef HALMAC_GET_DESC_FIELD
222 #define HALMAC_GET_DESC_FIELD(Dw, Mask, Shift) \
223 ((rtk_le32_to_cpu(Dw) >> (Shift)) & (Mask))
224 #endif
225
226 #define HALMAC_SET_BD_FIELD_CLR HALMAC_SET_DESC_FIELD_CLR
227 #define HALMAC_SET_BD_FIELD_NO_CLR HALMAC_SET_DESC_FIELD_NO_CLR
228 #define HALMAC_GET_BD_FIELD HALMAC_GET_DESC_FIELD
229
230 #ifndef GET_H2C_FIELD
231 #define GET_H2C_FIELD LE_BITS_TO_4BYTE
232 #endif
233
234 #ifndef SET_H2C_FIELD_CLR
235 #define SET_H2C_FIELD_CLR SET_BITS_TO_LE_4BYTE
236 #endif
237
238 #ifndef SET_H2C_FIELD_NO_CLR
239 #define SET_H2C_FIELD_NO_CLR SET_BITS_TO_LE_4BYTE
240 #endif
241
242 #ifndef GET_C2H_FIELD
243 #define GET_C2H_FIELD LE_BITS_TO_4BYTE
244 #endif
245
246 #ifndef SET_C2H_FIELD_CLR
247 #define SET_C2H_FIELD_CLR SET_BITS_TO_LE_4BYTE
248 #endif
249
250 #ifndef SET_C2H_FIELD_NO_CLR
251 #define SET_C2H_FIELD_NO_CLR SET_BITS_TO_LE_4BYTE
252 #endif
253
254 #endif /* #if !HALMAC_PLATFORM_WINDOWS */
255
256 #ifndef BIT
257 #define BIT(x) (1 << (x))
258 #endif
259
260 /* HALMAC API return status*/
261 typedef enum _HALMAC_RET_STATUS {
262 HALMAC_RET_SUCCESS = 0x00,
263 HALMAC_RET_SUCCESS_ENQUEUE = 0x01,
264 HALMAC_RET_PLATFORM_API_NULL = 0x02,
265 HALMAC_RET_EFUSE_SIZE_INCORRECT = 0x03,
266 HALMAC_RET_MALLOC_FAIL = 0x04,
267 HALMAC_RET_ADAPTER_INVALID = 0x05,
268 HALMAC_RET_ITF_INCORRECT = 0x06,
269 HALMAC_RET_DLFW_FAIL = 0x07,
270 HALMAC_RET_PORT_NOT_SUPPORT = 0x08,
271 HALMAC_RET_TRXMODE_NOT_SUPPORT = 0x09,
272 HALMAC_RET_INIT_LLT_FAIL = 0x0A,
273 HALMAC_RET_POWER_STATE_INVALID = 0x0B,
274 HALMAC_RET_H2C_ACK_NOT_RECEIVED = 0x0C,
275 HALMAC_RET_DL_RSVD_PAGE_FAIL = 0x0D,
276 HALMAC_RET_EFUSE_R_FAIL = 0x0E,
277 HALMAC_RET_EFUSE_W_FAIL = 0x0F,
278 HALMAC_RET_H2C_SW_RES_FAIL = 0x10,
279 HALMAC_RET_SEND_H2C_FAIL = 0x11,
280 HALMAC_RET_PARA_NOT_SUPPORT = 0x12,
281 HALMAC_RET_PLATFORM_API_INCORRECT = 0x13,
282 HALMAC_RET_ENDIAN_ERR = 0x14,
283 HALMAC_RET_FW_SIZE_ERR = 0x15,
284 HALMAC_RET_TRX_MODE_NOT_SUPPORT = 0x16,
285 HALMAC_RET_FAIL = 0x17,
286 HALMAC_RET_CHANGE_PS_FAIL = 0x18,
287 HALMAC_RET_CFG_PARA_FAIL = 0x19,
288 HALMAC_RET_UPDATE_PROBE_FAIL = 0x1A,
289 HALMAC_RET_SCAN_FAIL = 0x1B,
290 HALMAC_RET_STOP_SCAN_FAIL = 0x1C,
291 HALMAC_RET_BCN_PARSER_CMD_FAIL = 0x1D,
292 HALMAC_RET_POWER_ON_FAIL = 0x1E,
293 HALMAC_RET_POWER_OFF_FAIL = 0x1F,
294 HALMAC_RET_RX_AGG_MODE_FAIL = 0x20,
295 HALMAC_RET_DATA_BUF_NULL = 0x21,
296 HALMAC_RET_DATA_SIZE_INCORRECT = 0x22,
297 HALMAC_RET_QSEL_INCORRECT = 0x23,
298 HALMAC_RET_DMA_MAP_INCORRECT = 0x24,
299 HALMAC_RET_SEND_ORIGINAL_H2C_FAIL = 0x25,
300 HALMAC_RET_DDMA_FAIL = 0x26,
301 HALMAC_RET_FW_CHECKSUM_FAIL = 0x27,
302 HALMAC_RET_PWRSEQ_POLLING_FAIL = 0x28,
303 HALMAC_RET_PWRSEQ_CMD_INCORRECT = 0x29,
304 HALMAC_RET_WRITE_DATA_FAIL = 0x2A,
305 HALMAC_RET_DUMP_FIFOSIZE_INCORRECT = 0x2B,
306 HALMAC_RET_NULL_POINTER = 0x2C,
307 HALMAC_RET_PROBE_NOT_FOUND = 0x2D,
308 HALMAC_RET_FW_NO_MEMORY = 0x2E,
309 HALMAC_RET_H2C_STATUS_ERR = 0x2F,
310 HALMAC_RET_GET_H2C_SPACE_ERR = 0x30,
311 HALMAC_RET_H2C_SPACE_FULL = 0x31,
312 HALMAC_RET_DATAPACK_NO_FOUND = 0x32,
313 HALMAC_RET_CANNOT_FIND_H2C_RESOURCE = 0x33,
314 HALMAC_RET_TX_DMA_ERR = 0x34,
315 HALMAC_RET_RX_DMA_ERR = 0x35,
316 HALMAC_RET_CHIP_NOT_SUPPORT = 0x36,
317 HALMAC_RET_FREE_SPACE_NOT_ENOUGH = 0x37,
318 HALMAC_RET_CH_SW_SEQ_WRONG = 0x38,
319 HALMAC_RET_CH_SW_NO_BUF = 0x39,
320 HALMAC_RET_SW_CASE_NOT_SUPPORT = 0x3A,
321 HALMAC_RET_CONVERT_SDIO_OFFSET_FAIL = 0x3B,
322 HALMAC_RET_INVALID_SOUNDING_SETTING = 0x3C,
323 HALMAC_RET_GEN_INFO_NOT_SENT = 0x3D,
324 HALMAC_RET_STATE_INCORRECT = 0x3E,
325 HALMAC_RET_H2C_BUSY = 0x3F,
326 HALMAC_RET_INVALID_FEATURE_ID = 0x40,
327 HALMAC_RET_BUFFER_TOO_SMALL = 0x41,
328 HALMAC_RET_ZERO_LEN_RSVD_PACKET = 0x42,
329 HALMAC_RET_BUSY_STATE = 0x43,
330 HALMAC_RET_ERROR_STATE = 0x44,
331 HALMAC_RET_API_INVALID = 0x45,
332 HALMAC_RET_POLLING_BCN_VALID_FAIL = 0x46,
333 HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL = 0x47,
334 HALMAC_RET_EEPROM_PARSING_FAIL = 0x48,
335 HALMAC_RET_EFUSE_NOT_ENOUGH = 0x49,
336 HALMAC_RET_WRONG_ARGUMENT = 0x4A,
337 HALMAC_RET_NOT_SUPPORT = 0x4B,
338 HALMAC_RET_C2H_NOT_HANDLED = 0x4C,
339 HALMAC_RET_PARA_SENDING = 0x4D,
340 HALMAC_RET_CFG_DLFW_SIZE_FAIL = 0x4E,
341 HALMAC_RET_CFG_TXFIFO_PAGE_FAIL = 0x4F,
342 HALMAC_RET_SWITCH_CASE_ERROR = 0x50,
343 HALMAC_RET_EFUSE_BANK_INCORRECT = 0x51,
344 HALMAC_RET_SWITCH_EFUSE_BANK_FAIL = 0x52,
345 HALMAC_RET_USB_MODE_UNCHANGE = 0x53,
346 HALMAC_RET_NO_DLFW = 0x54,
347 HALMAC_RET_USB2_3_SWITCH_UNSUPPORT = 0x55,
348 } HALMAC_RET_STATUS;
349
350 typedef enum _HALMAC_MAC_CLOCK_HW_DEF {
351 HALMAC_MAC_CLOCK_HW_DEF_80M = 0,
352 HALMAC_MAC_CLOCK_HW_DEF_40M = 1,
353 HALMAC_MAC_CLOCK_HW_DEF_20M = 2,
354 } HALMAC_MAC_CLOCK_HW_DEF;
355
356 /* Rx aggregation parameters */
357 typedef enum _HALMAC_NORMAL_RXAGG_TH_TO {
358 HALMAC_NORMAL_RXAGG_THRESHOLD = 0xFF,
359 HALMAC_NORMAL_RXAGG_TIMEOUT = 0x01,
360 } HALMAC_NORMAL_RXAGG_TH_TO;
361
362 typedef enum _HALMAC_LOOPBACK_RXAGG_TH_TO {
363 HALMAC_LOOPBACK_RXAGG_THRESHOLD = 0xFF,
364 HALMAC_LOOPBACK_RXAGG_TIMEOUT = 0x01,
365 } HALMAC_LOOPBACK_RXAGG_TH_TO;
366
367 /* Chip ID*/
368 typedef enum _HALMAC_CHIP_ID {
369 HALMAC_CHIP_ID_8822B = 0,
370 HALMAC_CHIP_ID_8821C = 1,
371 HALMAC_CHIP_ID_8824B = 2,
372 HALMAC_CHIP_ID_8197F = 3,
373 HALMAC_CHIP_ID_UNDEFINE = 0x7F,
374 } HALMAC_CHIP_ID;
375
376 typedef enum _HALMAC_CHIP_ID_HW_DEF {
377 HALMAC_CHIP_ID_HW_DEF_8723A = 0x01,
378 HALMAC_CHIP_ID_HW_DEF_8188E = 0x02,
379 HALMAC_CHIP_ID_HW_DEF_8881A = 0x03,
380 HALMAC_CHIP_ID_HW_DEF_8812A = 0x04,
381 HALMAC_CHIP_ID_HW_DEF_8821A = 0x05,
382 HALMAC_CHIP_ID_HW_DEF_8723B = 0x06,
383 HALMAC_CHIP_ID_HW_DEF_8192E = 0x07,
384 HALMAC_CHIP_ID_HW_DEF_8814A = 0x08,
385 HALMAC_CHIP_ID_HW_DEF_8821C = 0x09,
386 HALMAC_CHIP_ID_HW_DEF_8822B = 0x0A,
387 HALMAC_CHIP_ID_HW_DEF_8703B = 0x0B,
388 HALMAC_CHIP_ID_HW_DEF_8188F = 0x0C,
389 HALMAC_CHIP_ID_HW_DEF_8192F = 0x0D,
390 HALMAC_CHIP_ID_HW_DEF_8197F = 0x0E,
391 HALMAC_CHIP_ID_HW_DEF_8723D = 0x0F,
392 HALMAC_CHIP_ID_HW_DEF_UNDEFINE = 0x7F,
393 HALMAC_CHIP_ID_HW_DEF_PS = 0xEA,
394 } HALMAC_CHIP_ID_HW_DEF;
395
396 /* Chip Version*/
397 typedef enum _HALMAC_CHIP_VER {
398 HALMAC_CHIP_VER_A_CUT = 0x00,
399 HALMAC_CHIP_VER_B_CUT = 0x01,
400 HALMAC_CHIP_VER_C_CUT = 0x02,
401 HALMAC_CHIP_VER_D_CUT = 0x03,
402 HALMAC_CHIP_VER_E_CUT = 0x04,
403 HALMAC_CHIP_VER_F_CUT = 0x05,
404 HALMAC_CHIP_VER_TEST = 0xFF,
405 HALMAC_CHIP_VER_UNDEFINE = 0x7FFF,
406 } HALMAC_CHIP_VER;
407
408 /* Network type select */
409 typedef enum _HALMAC_NETWORK_TYPE_SELECT {
410 HALMAC_NETWORK_NO_LINK = 0,
411 HALMAC_NETWORK_ADHOC = 1,
412 HALMAC_NETWORK_INFRASTRUCTURE = 2,
413 HALMAC_NETWORK_AP = 3,
414 HALMAC_NETWORK_UNDEFINE = 0x7F,
415 } HALMAC_NETWORK_TYPE_SELECT;
416
417 /* Transfer mode select */
418 typedef enum _HALMAC_TRNSFER_MODE_SELECT {
419 HALMAC_TRNSFER_NORMAL = 0x0,
420 HALMAC_TRNSFER_LOOPBACK_DIRECT = 0xB,
421 HALMAC_TRNSFER_LOOPBACK_DELAY = 0x3,
422 HALMAC_TRNSFER_UNDEFINE = 0x7F,
423 } HALMAC_TRNSFER_MODE_SELECT;
424
425 /* Queue select */
426 typedef enum _HALMAC_DMA_MAPPING {
427 HALMAC_DMA_MAPPING_EXTRA = 0,
428 HALMAC_DMA_MAPPING_LOW = 1,
429 HALMAC_DMA_MAPPING_NORMAL = 2,
430 HALMAC_DMA_MAPPING_HIGH = 3,
431 HALMAC_DMA_MAPPING_UNDEFINE = 0x7F,
432 } HALMAC_DMA_MAPPING;
433
434 /* TXDESC queue select TID */
435 typedef enum _HALMAC_TXDESC_QUEUE_TID {
436 HALMAC_TXDESC_QSEL_TID0 = 0,
437 HALMAC_TXDESC_QSEL_TID1 = 1,
438 HALMAC_TXDESC_QSEL_TID2 = 2,
439 HALMAC_TXDESC_QSEL_TID3 = 3,
440 HALMAC_TXDESC_QSEL_TID4 = 4,
441 HALMAC_TXDESC_QSEL_TID5 = 5,
442 HALMAC_TXDESC_QSEL_TID6 = 6,
443 HALMAC_TXDESC_QSEL_TID7 = 7,
444 HALMAC_TXDESC_QSEL_TID8 = 8,
445 HALMAC_TXDESC_QSEL_TID9 = 9,
446 HALMAC_TXDESC_QSEL_TIDA = 10,
447 HALMAC_TXDESC_QSEL_TIDB = 11,
448 HALMAC_TXDESC_QSEL_TIDC = 12,
449 HALMAC_TXDESC_QSEL_TIDD = 13,
450 HALMAC_TXDESC_QSEL_TIDE = 14,
451 HALMAC_TXDESC_QSEL_TIDF = 15,
452
453 HALMAC_TXDESC_QSEL_BEACON = 0x10,
454 HALMAC_TXDESC_QSEL_HIGH = 0x11,
455 HALMAC_TXDESC_QSEL_MGT = 0x12,
456 HALMAC_TXDESC_QSEL_H2C_CMD = 0x13,
457
458 HALMAC_TXDESC_QSEL_UNDEFINE = 0x7F,
459 } HALMAC_TXDESC_QUEUE_TID;
460
461 typedef enum _HALMAC_PTCL_QUEUE {
462 HALMAC_PTCL_QUEUE_VO = 0x0,
463 HALMAC_PTCL_QUEUE_VI = 0x1,
464 HALMAC_PTCL_QUEUE_BE = 0x2,
465 HALMAC_PTCL_QUEUE_BK = 0x3,
466 HALMAC_PTCL_QUEUE_MG = 0x4,
467 HALMAC_PTCL_QUEUE_HI = 0x5,
468 HALMAC_PTCL_QUEUE_NUM = 0x6,
469 HALMAC_PTCL_QUEUE_UNDEFINE = 0x7F,
470 } HALMAC_PTCL_QUEUE;
471
472 typedef enum {
473 HALMAC_QUEUE_SELECT_VO = HALMAC_TXDESC_QSEL_TID6,
474 HALMAC_QUEUE_SELECT_VI = HALMAC_TXDESC_QSEL_TID4,
475 HALMAC_QUEUE_SELECT_BE = HALMAC_TXDESC_QSEL_TID0,
476 HALMAC_QUEUE_SELECT_BK = HALMAC_TXDESC_QSEL_TID1,
477 HALMAC_QUEUE_SELECT_VO_V2 = HALMAC_TXDESC_QSEL_TID7,
478 HALMAC_QUEUE_SELECT_VI_V2 = HALMAC_TXDESC_QSEL_TID5,
479 HALMAC_QUEUE_SELECT_BE_V2 = HALMAC_TXDESC_QSEL_TID3,
480 HALMAC_QUEUE_SELECT_BK_V2 = HALMAC_TXDESC_QSEL_TID2,
481 HALMAC_QUEUE_SELECT_BCN = HALMAC_TXDESC_QSEL_BEACON,
482 HALMAC_QUEUE_SELECT_HIGH = HALMAC_TXDESC_QSEL_HIGH,
483 HALMAC_QUEUE_SELECT_MGNT = HALMAC_TXDESC_QSEL_MGT,
484 HALMAC_QUEUE_SELECT_CMD = HALMAC_TXDESC_QSEL_H2C_CMD,
485 HALMAC_QUEUE_SELECT_UNDEFINE = 0x7F,
486 } HALMAC_QUEUE_SELECT;
487
488
489 /* USB burst size */
490 typedef enum _HALMAC_USB_BURST_SIZE {
491 HALMAC_USB_BURST_SIZE_3_0 = 0x0,
492 HALMAC_USB_BURST_SIZE_2_0_HSPEED = 0x1,
493 HALMAC_USB_BURST_SIZE_2_0_FSPEED = 0x2,
494 HALMAC_USB_BURST_SIZE_2_0_OTHERS = 0x3,
495 HALMAC_USB_BURST_SIZE_UNDEFINE = 0x7F,
496 } HALMAC_USB_BURST_SIZE;
497
498 /* HAL API function parameters*/
499 typedef enum _HALMAC_INTERFACE {
500 HALMAC_INTERFACE_PCIE = 0x0,
501 HALMAC_INTERFACE_USB = 0x1,
502 HALMAC_INTERFACE_SDIO = 0x2,
503 HALMAC_INTERFACE_UNDEFINE = 0x7F,
504 } HALMAC_INTERFACE;
505
506 typedef enum _HALMAC_RX_AGG_MODE {
507 HALMAC_RX_AGG_MODE_NONE = 0x0,
508 HALMAC_RX_AGG_MODE_DMA = 0x1,
509 HALMAC_RX_AGG_MODE_USB = 0x2,
510 HALMAC_RX_AGG_MODE_UNDEFINE = 0x7F,
511 } HALMAC_RX_AGG_MODE;
512 typedef struct _HALMAC_RXAGG_TH {
513 u8 drv_define;
514 u8 timeout;
515 u8 size;
516 } HALMAC_RXAGG_TH, *PHALMAC_RXAGG_TH;
517
518 typedef struct _HALMAC_RXAGG_CFG {
519 HALMAC_RX_AGG_MODE mode;
520 HALMAC_RXAGG_TH threshold;
521 } HALMAC_RXAGG_CFG, *PHALMAC_RXAGG_CFG;
522
523
524 typedef enum _HALMAC_MAC_POWER {
525 HALMAC_MAC_POWER_OFF = 0x0,
526 HALMAC_MAC_POWER_ON = 0x1,
527 HALMAC_MAC_POWER_UNDEFINE = 0x7F,
528 } HALMAC_MAC_POWER;
529
530 typedef enum _HALMAC_PS_STATE {
531 HALMAC_PS_STATE_ACT = 0x0,
532 HALMAC_PS_STATE_LPS = 0x1,
533 HALMAC_PS_STATE_IPS = 0x2,
534 HALMAC_PS_STATE_UNDEFINE = 0x7F,
535 } HALMAC_PS_STATE;
536
537 typedef enum _HALMAC_TRX_MODE {
538 HALMAC_TRX_MODE_NORMAL = 0x0,
539 HALMAC_TRX_MODE_TRXSHARE = 0x1,
540 HALMAC_TRX_MODE_WMM = 0x2,
541 HALMAC_TRX_MODE_P2P = 0x3,
542 HALMAC_TRX_MODE_LOOPBACK = 0x4,
543 HALMAC_TRX_MODE_DELAY_LOOPBACK = 0x5,
544 HALMAC_TRX_MODE_UNDEFINE = 0x7F,
545 } HALMAC_TRX_MODE;
546
547 typedef enum _HALMAC_WIRELESS_MODE {
548 HALMAC_WIRELESS_MODE_B = 0x0,
549 HALMAC_WIRELESS_MODE_G = 0x1,
550 HALMAC_WIRELESS_MODE_N = 0x2,
551 HALMAC_WIRELESS_MODE_AC = 0x3,
552 HALMAC_WIRELESS_MODE_UNDEFINE = 0x7F,
553 } HALMAC_WIRELESS_MODE;
554
555 typedef enum _HALMAC_BW {
556 HALMAC_BW_20 = 0x00,
557 HALMAC_BW_40 = 0x01,
558 HALMAC_BW_80 = 0x02,
559 HALMAC_BW_160 = 0x03,
560 HALMAC_BW_5 = 0x04,
561 HALMAC_BW_10 = 0x05,
562 HALMAC_BW_MAX = 0x06,
563 HALMAC_BW_UNDEFINE = 0x7F,
564 } HALMAC_BW;
565
566
567 typedef enum _HALMAC_EFUSE_READ_CFG {
568 HALMAC_EFUSE_R_AUTO = 0x00,
569 HALMAC_EFUSE_R_DRV = 0x01,
570 HALMAC_EFUSE_R_FW = 0x02,
571 HALMAC_EFUSE_R_UNDEFINE = 0x7F,
572 } HALMAC_EFUSE_READ_CFG;
573
574
575 typedef struct _HALMAC_TX_DESC {
576 u32 Dword0;
577 u32 Dword1;
578 u32 Dword2;
579 u32 Dword3;
580 u32 Dword4;
581 u32 Dword5;
582 u32 Dword6;
583 u32 Dword7;
584 u32 Dword8;
585 u32 Dword9;
586 u32 Dword10;
587 u32 Dword11;
588 } HALMAC_TX_DESC, *PHALMAC_TX_DESC;
589
590 typedef struct _HALMAC_RX_DESC {
591 u32 Dword0;
592 u32 Dword1;
593 u32 Dword2;
594 u32 Dword3;
595 u32 Dword4;
596 u32 Dword5;
597 } HALMAC_RX_DESC, *PHALMAC_RX_DESC;
598
599 typedef struct _HALMAC_FWLPS_OPTION {
600 u8 mode;
601 u8 clk_request;
602 u8 rlbm;
603 u8 smart_ps;
604 u8 awake_interval;
605 u8 all_queue_uapsd;
606 u8 pwr_state;
607 u8 low_pwr_rx_beacon;
608 u8 ant_auto_switch;
609 u8 ps_allow_bt_high_Priority;
610 u8 protect_bcn;
611 u8 silence_period;
612 u8 fast_bt_connect;
613 u8 two_antenna_en;
614 u8 adopt_user_Setting;
615 u8 drv_bcn_early_shift;
616 u8 enter_32K;
617 } HALMAC_FWLPS_OPTION, *PHALMAC_FWLPS_OPTION;
618
619 typedef struct _HALMAC_FWIPS_OPTION {
620 u8 adopt_user_Setting;
621 } HALMAC_FWIPS_OPTION, *PHALMAC_FWIPS_OPTION;
622
623 typedef struct _HALMAC_WOWLAN_OPTION {
624 u8 adopt_user_Setting;
625 } HALMAC_WOWLAN_OPTION, *PHALMAC_WOWLAN_OPTION;
626
627 typedef struct _HALMAC_BCN_IE_INFO {
628 u8 func_en;
629 u8 size_th;
630 u8 timeout;
631 u8 ie_bmp[HALMAC_BCN_IE_BMP_SIZE];
632 } HALMAC_BCN_IE_INFO, *PHALMAC_BCN_IE_INFO;
633
634 typedef enum _HALMAC_REG_TYPE {
635 HALMAC_REG_TYPE_MAC = 0x0,
636 HALMAC_REG_TYPE_BB = 0x1,
637 HALMAC_REG_TYPE_RF = 0x2,
638 HALMAC_REG_TYPE_UNDEFINE = 0x7F,
639 } HALMAC_REG_TYPE;
640
641 typedef enum _HALMAC_PARAMETER_CMD {
642 /* HALMAC_PARAMETER_CMD_LLT = 0x1, */
643 /* HALMAC_PARAMETER_CMD_R_EFUSE = 0x2, */
644 /* HALMAC_PARAMETER_CMD_EFUSE_PATCH = 0x3, */
645 HALMAC_PARAMETER_CMD_MAC_W8 = 0x4,
646 HALMAC_PARAMETER_CMD_MAC_W16 = 0x5,
647 HALMAC_PARAMETER_CMD_MAC_W32 = 0x6,
648 HALMAC_PARAMETER_CMD_RF_W = 0x7,
649 HALMAC_PARAMETER_CMD_BB_W8 = 0x8,
650 HALMAC_PARAMETER_CMD_BB_W16 = 0x9,
651 HALMAC_PARAMETER_CMD_BB_W32 = 0XA,
652 HALMAC_PARAMETER_CMD_DELAY_US = 0X10,
653 HALMAC_PARAMETER_CMD_DELAY_MS = 0X11,
654 HALMAC_PARAMETER_CMD_END = 0XFF,
655 } HALMAC_PARAMETER_CMD;
656
657 typedef union _HALMAC_PARAMETER_CONTENT {
658 struct _MAC_REG_W {
659 u32 value;
660 u32 msk;
661 u16 offset;
662 u8 msk_en;
663 } MAC_REG_W;
664 struct _BB_REG_W {
665 u32 value;
666 u32 msk;
667 u16 offset;
668 u8 msk_en;
669 } BB_REG_W;
670 struct _RF_REG_W {
671 u32 value;
672 u32 msk;
673 u8 offset;
674 u8 msk_en;
675 u8 rf_path;
676 } RF_REG_W;
677 struct _DELAY_TIME {
678 u32 rsvd1;
679 u32 rsvd2;
680 u16 delay_time;
681 u8 rsvd3;
682 } DELAY_TIME;
683 } HALMAC_PARAMETER_CONTENT, *PHALMAC_PARAMETER_CONTENT;
684
685 typedef struct _HALMAC_PHY_PARAMETER_INFO {
686 HALMAC_PARAMETER_CMD cmd_id;
687 HALMAC_PARAMETER_CONTENT content;
688 } HALMAC_PHY_PARAMETER_INFO, *PHALMAC_PHY_PARAMETER_INFO;
689
690 typedef struct _HALMAC_H2C_INFO {
691 u16 h2c_seq_num; /* H2C sequence number */
692 u8 in_use; /* 0 : empty 1 : used */
693 HALMAC_H2C_RETURN_CODE status;
694 } HALMAC_H2C_INFO, *PHALMAC_H2C_INFO;
695
696 typedef struct _HALMAC_PG_EFUSE_INFO {
697 u8 *pEfuse_map;
698 u32 efuse_map_size;
699 u8 *pEfuse_mask;
700 u32 efuse_mask_size;
701 } HALMAC_PG_EFUSE_INFO, *PHALMAC_PG_EFUSE_INFO;
702
703 typedef struct _HALMAC_TXAGG_BUFF_INFO {
704 u8 *pTx_agg_buf;
705 u8 *pCurr_pkt_buf;
706 u32 avai_buf_size;
707 u32 total_pkt_size;
708 u8 agg_num;
709 } HALMAC_TXAGG_BUFF_INFO, *PHALMAC_TXAGG_BUFF_INFO;
710
711 typedef struct _HALMAC_CONFIG_PARA_INFO {
712 u32 para_buf_size; /* Parameter buffer size */
713 u8 *pCfg_para_buf; /* Buffer for config parameter */
714 u8 *pPara_buf_w; /* Write pointer of the parameter buffer */
715 u32 para_num; /* Parameter numbers in parameter buffer */
716 u32 avai_para_buf_size; /* Free size of parameter buffer */
717 u32 offset_accumulation;
718 u32 value_accumulation;
719 HALMAC_DATA_TYPE data_type; /*DataType which is passed to FW*/
720 u8 datapack_segment; /*DataPack Segment, from segment0...*/
721 u8 full_fifo_mode; /* Used full tx fifo to save cfg parameter */
722 } HALMAC_CONFIG_PARA_INFO, *PHALMAC_CONFIG_PARA_INFO;
723
724 typedef struct _HALMAC_HW_CONFIG_INFO {
725 u32 efuse_size; /* Record efuse size */
726 u32 eeprom_size; /* Record eeprom size */
727 u32 bt_efuse_size; /* Record BT efuse size */
728 u32 tx_fifo_size; /* Record tx fifo size */
729 u32 rx_fifo_size; /* Record rx fifo size */
730 u8 txdesc_size; /* Record tx desc size */
731 u8 rxdesc_size; /* Record rx desc size */
732 u8 cam_entry_num; /* Record CAM entry number */
733 } HALMAC_HW_CONFIG_INFO, *PHALMAC_HW_CONFIG_INFO;
734
735 typedef struct _HALMAC_SDIO_FREE_SPACE {
736 u16 high_queue_number; /* Free space of HIQ */
737 u16 normal_queue_number; /* Free space of MIDQ */
738 u16 low_queue_number; /* Free space of LOWQ */
739 u16 public_queue_number; /* Free space of PUBQ */
740 u16 extra_queue_number; /* Free space of EXBQ */
741 u8 ac_oqt_number;
742 u8 non_ac_oqt_number;
743 } HALMAC_SDIO_FREE_SPACE, *PHALMAC_SDIO_FREE_SPACE;
744
745 typedef enum _HAL_FIFO_SEL {
746 HAL_FIFO_SEL_TX,
747 HAL_FIFO_SEL_RX,
748 HAL_FIFO_SEL_RSVD_PAGE,
749 HAL_FIFO_SEL_REPORT,
750 HAL_FIFO_SEL_LLT,
751 } HAL_FIFO_SEL;
752
753 typedef enum _HALMAC_DRV_INFO {
754 HALMAC_DRV_INFO_NONE, /* No information is appended in rx_pkt */
755 HALMAC_DRV_INFO_PHY_STATUS, /* PHY status is appended after rx_desc */
756 HALMAC_DRV_INFO_PHY_SNIFFER, /* PHY status and sniffer info are appended after rx_desc */
757 HALMAC_DRV_INFO_PHY_PLCP, /* PHY status and plcp header are appended after rx_desc */
758 HALMAC_DRV_INFO_UNDEFINE,
759 } HALMAC_DRV_INFO;
760
761 typedef struct _HALMAC_BT_COEX_CMD {
762 u8 element_id;
763 u8 op_code;
764 u8 op_code_ver;
765 u8 req_num;
766 u8 data0;
767 u8 data1;
768 u8 data2;
769 u8 data3;
770 u8 data4;
771 } HALMAC_BT_COEX_CMD, *PHALMAC_BT_COEX_CMD;
772
773 typedef enum _HALMAC_PRI_CH_IDX {
774 HALMAC_CH_IDX_UNDEFINE = 0,
775 HALMAC_CH_IDX_1 = 1,
776 HALMAC_CH_IDX_2 = 2,
777 HALMAC_CH_IDX_3 = 3,
778 HALMAC_CH_IDX_4 = 4,
779 HALMAC_CH_IDX_MAX = 5,
780 } HALMAC_PRI_CH_IDX;
781
782 typedef struct _HALMAC_CH_INFO {
783 HALMAC_CS_ACTION_ID action_id;
784 HALMAC_BW bw;
785 HALMAC_PRI_CH_IDX pri_ch_idx;
786 u8 channel;
787 u8 timeout;
788 u8 extra_info;
789 } HALMAC_CH_INFO, *PHALMAC_CH_INFO;
790
791 typedef struct _HALMAC_CH_EXTRA_INFO {
792 u8 extra_info;
793 HALMAC_CS_EXTRA_ACTION_ID extra_action_id;
794 u8 extra_info_size;
795 u8 *extra_info_data;
796 } HALMAC_CH_EXTRA_INFO, *PHALMAC_CH_EXTRA_INFO;
797
798 typedef enum _HALMAC_CS_PERIODIC_OPTION {
799 HALMAC_CS_PERIODIC_NONE,
800 HALMAC_CS_PERIODIC_NORMAL,
801 HALMAC_CS_PERIODIC_2_PHASE,
802 HALMAC_CS_PERIODIC_SEAMLESS,
803 } HALMAC_CS_PERIODIC_OPTION;
804
805 typedef struct _HALMAC_CH_SWITCH_OPTION {
806 HALMAC_BW dest_bw;
807 HALMAC_CS_PERIODIC_OPTION periodic_option;
808 HALMAC_PRI_CH_IDX dest_pri_ch_idx;
809 /* u32 tsf_high; */
810 u32 tsf_low;
811 u8 switch_en;
812 u8 dest_ch_en;
813 u8 absolute_time_en;
814 u8 dest_ch;
815 u8 normal_period;
816 u8 normal_cycle;
817 u8 phase_2_period;
818 } HALMAC_CH_SWITCH_OPTION, *PHALMAC_CH_SWITCH_OPTION;
819
820 typedef struct _HALMAC_FW_VERSION {
821 u16 version;
822 u8 sub_version;
823 u8 sub_index;
824 } HALMAC_FW_VERSION, *PHALMAC_FW_VERSION;
825
826 typedef enum _HALMAC_RF_TYPE {
827 HALMAC_RF_1T2R = 0,
828 HALMAC_RF_2T4R = 1,
829 HALMAC_RF_2T2R = 2,
830 HALMAC_RF_2T3R = 3,
831 HALMAC_RF_1T1R = 4,
832 HALMAC_RF_2T2R_GREEN = 5,
833 HALMAC_RF_3T3R = 6,
834 HALMAC_RF_3T4R = 7,
835 HALMAC_RF_4T4R = 8,
836 HALMAC_RF_MAX_TYPE = 0xF,
837 } HALMAC_RF_TYPE;
838
839 typedef struct _HALMAC_GENERAL_INFO {
840 u8 rfe_type;
841 HALMAC_RF_TYPE rf_type;
842 } HALMAC_GENERAL_INFO, *PHALMAC_GENERAL_INFO;
843
844 typedef struct _HALMAC_PWR_TRACKING_PARA {
845 u8 enable;
846 u8 tx_pwr_index;
847 u8 pwr_tracking_offset_value;
848 u8 tssi_value;
849 } HALMAC_PWR_TRACKING_PARA, *PHALMAC_PWR_TRACKING_PARA;
850
851 typedef struct _HALMAC_PWR_TRACKING_OPTION {
852 u8 type;
853 u8 bbswing_index;
854 HALMAC_PWR_TRACKING_PARA pwr_tracking_para[4]; /* pathA, pathB, pathC, pathD */
855 } HALMAC_PWR_TRACKING_OPTION, *PHALMAC_PWR_TRACKING_OPTION;
856
857 typedef struct _HALMAC_NLO_CFG {
858 u8 num_of_ssid;
859 u8 num_of_hidden_ap;
860 u8 rsvd[2];
861 u32 pattern_check;
862 u32 rsvd1;
863 u32 rsvd2;
864 u8 ssid_len[HALMAC_SUPPORT_NLO_NUM];
865 u8 ChiperType[HALMAC_SUPPORT_NLO_NUM];
866 u8 rsvd3[HALMAC_SUPPORT_NLO_NUM];
867 u8 loc_probeReq[HALMAC_SUPPORT_PROBE_REQ_NUM];
868 u8 rsvd4[56];
869 u8 ssid[HALMAC_SUPPORT_NLO_NUM][HALMAC_MAX_SSID_LEN];
870 } HALMAC_NLO_CFG, *PHALMAC_NLO_CFG;
871
872
873 typedef enum _HALMAC_DATA_RATE {
874 HALMAC_CCK1,
875 HALMAC_CCK2,
876 HALMAC_CCK5_5,
877 HALMAC_CCK11,
878 HALMAC_OFDM6,
879 HALMAC_OFDM9,
880 HALMAC_OFDM12,
881 HALMAC_OFDM18,
882 HALMAC_OFDM24,
883 HALMAC_OFDM36,
884 HALMAC_OFDM48,
885 HALMAC_OFDM54,
886 HALMAC_MCS0,
887 HALMAC_MCS1,
888 HALMAC_MCS2,
889 HALMAC_MCS3,
890 HALMAC_MCS4,
891 HALMAC_MCS5,
892 HALMAC_MCS6,
893 HALMAC_MCS7,
894 HALMAC_MCS8,
895 HALMAC_MCS9,
896 HALMAC_MCS10,
897 HALMAC_MCS11,
898 HALMAC_MCS12,
899 HALMAC_MCS13,
900 HALMAC_MCS14,
901 HALMAC_MCS15,
902 HALMAC_MCS16,
903 HALMAC_MCS17,
904 HALMAC_MCS18,
905 HALMAC_MCS19,
906 HALMAC_MCS20,
907 HALMAC_MCS21,
908 HALMAC_MCS22,
909 HALMAC_MCS23,
910 HALMAC_MCS24,
911 HALMAC_MCS25,
912 HALMAC_MCS26,
913 HALMAC_MCS27,
914 HALMAC_MCS28,
915 HALMAC_MCS29,
916 HALMAC_MCS30,
917 HALMAC_MCS31,
918 HALMAC_VHT_NSS1_MCS0,
919 HALMAC_VHT_NSS1_MCS1,
920 HALMAC_VHT_NSS1_MCS2,
921 HALMAC_VHT_NSS1_MCS3,
922 HALMAC_VHT_NSS1_MCS4,
923 HALMAC_VHT_NSS1_MCS5,
924 HALMAC_VHT_NSS1_MCS6,
925 HALMAC_VHT_NSS1_MCS7,
926 HALMAC_VHT_NSS1_MCS8,
927 HALMAC_VHT_NSS1_MCS9,
928 HALMAC_VHT_NSS2_MCS0,
929 HALMAC_VHT_NSS2_MCS1,
930 HALMAC_VHT_NSS2_MCS2,
931 HALMAC_VHT_NSS2_MCS3,
932 HALMAC_VHT_NSS2_MCS4,
933 HALMAC_VHT_NSS2_MCS5,
934 HALMAC_VHT_NSS2_MCS6,
935 HALMAC_VHT_NSS2_MCS7,
936 HALMAC_VHT_NSS2_MCS8,
937 HALMAC_VHT_NSS2_MCS9,
938 HALMAC_VHT_NSS3_MCS0,
939 HALMAC_VHT_NSS3_MCS1,
940 HALMAC_VHT_NSS3_MCS2,
941 HALMAC_VHT_NSS3_MCS3,
942 HALMAC_VHT_NSS3_MCS4,
943 HALMAC_VHT_NSS3_MCS5,
944 HALMAC_VHT_NSS3_MCS6,
945 HALMAC_VHT_NSS3_MCS7,
946 HALMAC_VHT_NSS3_MCS8,
947 HALMAC_VHT_NSS3_MCS9,
948 HALMAC_VHT_NSS4_MCS0,
949 HALMAC_VHT_NSS4_MCS1,
950 HALMAC_VHT_NSS4_MCS2,
951 HALMAC_VHT_NSS4_MCS3,
952 HALMAC_VHT_NSS4_MCS4,
953 HALMAC_VHT_NSS4_MCS5,
954 HALMAC_VHT_NSS4_MCS6,
955 HALMAC_VHT_NSS4_MCS7,
956 HALMAC_VHT_NSS4_MCS8,
957 HALMAC_VHT_NSS4_MCS9
958 } HALMAC_DATA_RATE;
959
960 typedef enum _HALMAC_RF_PATH {
961 HALMAC_RF_PATH_A,
962 HALMAC_RF_PATH_B,
963 HALMAC_RF_PATH_C,
964 HALMAC_RF_PATH_D
965 } HALMAC_RF_PATH;
966
967 typedef enum _HALMAC_SND_PKT_SEL {
968 HALMAC_UNI_NDPA,
969 HALMAC_BMC_NDPA,
970 HALMAC_NON_FINAL_BFRPRPOLL,
971 HALMAC_FINAL_BFRPTPOLL,
972 } HALMAC_SND_PKT_SEL;
973
974 #if HALMAC_PLATFORM_TESTPROGRAM
975
976 typedef enum _HALMAC_PWR_SEQ_ID {
977 HALMAC_PWR_SEQ_ENABLE,
978 HALMAC_PWR_SEQ_DISABLE,
979 HALMAC_PWR_SEQ_ENTER_LPS,
980 HALMAC_PWR_SEQ_ENTER_DEEP_LPS,
981 HALMAC_PWR_SEQ_LEAVE_LPS,
982 HALMAC_PWR_SEQ_MAX
983 } HALMAC_PWR_SEQ_ID;
984
985 typedef enum _HAL_TX_ID {
986 HAL_TX_ID_VO,
987 HAL_TX_ID_VI,
988 HAL_TX_ID_BE,
989 HAL_TX_ID_BK,
990 HAL_TX_ID_BCN,
991 HAL_TX_ID_H2C,
992 HAL_TX_ID_MAX
993 } HAL_TX_ID;
994
995 typedef enum _HAL_QSEL {
996 HAL_QSEL_TID0,
997 HAL_QSEL_TID1,
998 HAL_QSEL_TID2,
999 HAL_QSEL_TID3,
1000 HAL_QSEL_TID4,
1001 HAL_QSEL_TID5,
1002 HAL_QSEL_TID6,
1003 HAL_QSEL_TID7,
1004
1005 HAL_QSEL_BEACON = 0x10,
1006 HAL_QSEL_HIGH = 0x11,
1007 HAL_QSEL_MGT = 0x12,
1008 HAL_QSEL_CMD = 0x13
1009 } HAL_QSEL;
1010
1011 typedef enum _HAL_RTS_MODE {
1012 HAL_RTS_MODE_NONE,
1013 HAL_RTS_MODE_CTS2SELF,
1014 HAL_RTS_MODE_RTS,
1015 } HAL_RTS_MODE;
1016
1017 typedef enum _HAL_DATA_BW {
1018 HAL_DATA_BW_20M,
1019 HAL_DATA_BW_40M,
1020 HAL_DATA_BW_80M,
1021 HAL_DATA_BW_160M,
1022 } HAL_DATA_BW;
1023
1024 typedef enum _HAL_RTS_SHORT {
1025 HAL_RTS_SHORT_SHORT,
1026 HAL_RTS_SHORT_LONG,
1027 } HAL_RTS_SHORT;
1028
1029 typedef enum _HAL_SECURITY_TYPE {
1030 HAL_SECURITY_TYPE_NONE = 0,
1031 HAL_SECURITY_TYPE_WEP40 = 1,
1032 HAL_SECURITY_TYPE_WEP104 = 2,
1033 HAL_SECURITY_TYPE_TKIP = 3,
1034 HAL_SECURITY_TYPE_AES128 = 4,
1035 HAL_SECURITY_TYPE_WAPI = 5,
1036 HAL_SECURITY_TYPE_AES256 = 6,
1037 HAL_SECURITY_TYPE_GCMP128 = 7,
1038 HAL_SECURITY_TYPE_GCMP256 = 8,
1039 HAL_SECURITY_TYPE_GCMSMS4 = 9,
1040 HAL_SECURITY_TYPE_BIP = 10,
1041 HAL_SECURITY_TYPE_UNDEFINE = 0x7F,
1042 } HAL_SECURITY_TYPE;
1043
1044 typedef enum _HAL_SECURITY_METHOD {
1045 HAL_SECURITY_METHOD_HW = 0,
1046 HAL_SECURITY_METHOD_SW = 1,
1047 HAL_SECURITY_METHOD_UNDEFINE = 0x7F,
1048 } HAL_SECURITY_METHOD;
1049
1050 typedef struct _HAL_SECURITY_INFO {
1051 HAL_SECURITY_TYPE type;
1052 HAL_SECURITY_METHOD tx_method;
1053 HAL_SECURITY_METHOD rx_method;
1054 } HAL_SECURITY_INFO, *PHAL_SECURITY_INFO;
1055
1056 typedef struct _HAL_TXDESC_INFO {
1057 u32 txdesc_length;
1058 u32 packet_size; /* payload + wlheader */
1059 HAL_TX_ID tx_id;
1060 HALMAC_DATA_RATE data_rate;
1061 HAL_RTS_MODE rts_mode;
1062 HAL_DATA_BW data_bw;
1063 HAL_RTS_SHORT rts_short;
1064 HAL_SECURITY_TYPE security_type;
1065 HAL_SECURITY_METHOD encryption_method;
1066 u16 seq_num;
1067 u8 retry_limit_en;
1068 u8 retry_limit_number;
1069 u8 rts_threshold;
1070 u8 qos;
1071 u8 ht;
1072 u8 ampdu;
1073 u8 early_mode;
1074 u8 bm_cast;
1075 u8 data_short;
1076 u8 mac_id;
1077 } HAL_TXDESC_INFO, *PHAL_TXDESC_INFO;
1078
1079 typedef struct _HAL_RXDESC_INFO {
1080 u8 c2h;
1081 u8 *pWifi_pkt;
1082 u32 packet_size;
1083 u8 crc_err;
1084 u8 icv_err;
1085 } HAL_RXDESC_INFO, *PHAL_RXDESC_INFO;
1086
1087 typedef struct _HAL_TXDESC_PARSER {
1088 u8 txdesc_len;
1089 u16 txpkt_size;
1090 } HAL_TXDESC_PARSER, *PHAL_TXDESC_PARSER;
1091
1092 typedef struct _HAL_RXDESC_PARSER {
1093 u32 driver_info_size;
1094 u16 rxpkt_size;
1095 u8 rxdesc_len;
1096 u8 c2h;
1097 u8 crc_err;
1098 u8 icv_err;
1099 } HAL_RXDESC_PARSER, *PHAL_RXDESC_PARSER;
1100
1101 typedef struct _HAL_RF_REG_INFO {
1102 HALMAC_RF_PATH rf_path;
1103 u32 offset;
1104 u32 bit_mask;
1105 u32 data;
1106 } HAL_RF_REG_INFO, *PHAL_RF_REG_INFO;
1107
1108 typedef struct _HALMAC_SDIO_HIMR_INFO {
1109 u8 rx_request;
1110 u8 aval_msk;
1111 } HALMAC_SDIO_HIMR_INFO, *PHALMAC_SDIO_HIMR_INFO;
1112
1113 typedef struct _HALMAC_BEACON_INFO {
1114 } HALMAC_BEACON_INFO, *PHALMAC_BEACON_INFO;
1115
1116 typedef struct _HALMAC_MGNT_INFO {
1117 u8 mu_enable;
1118 u8 bip;
1119 u8 unicast;
1120 u32 packet_size;
1121 } HALMAC_MGNT_INFO, *PHALMAC_MGNT_INFO;
1122
1123 typedef struct _HALMAC_CTRL_INFO {
1124 u8 snd_enable;
1125 HALMAC_SND_PKT_SEL snd_pkt_sel; /* 0:unicast ndpa 1:broadcast ndpa 3:non-final BF Rpt Poll 4:final BF Rpt Poll */
1126 u8 *pPacket_desc;
1127 u32 desc_size;
1128 u16 seq_num;
1129 u8 bw;
1130 u16 paid;
1131 } HALMAC_CTRL_INFO, *PHALMAC_CTRL_INFO;
1132
1133 typedef struct _HALMAC_HIGH_QUEUE_INFO {
1134 u8 *pPacket_desc;
1135 u32 desc_size;
1136 } HALMAC_HIGH_QUEUE_INFO, *PHALMAC_HIGH_QUEUE_INFO;
1137
1138 typedef struct _HALMAC_CHIP_TYPE {
1139 HALMAC_CHIP_ID chip_id;
1140 HALMAC_CHIP_VER chip_version;
1141 } HALMAC_CHIP_TYPE, *PHALMAC_CHIP_TYPE;
1142
1143 typedef struct _HALMAC_CAM_ENTRY_FORMAT {
1144 u16 key_id : 2;
1145 u16 type : 3;
1146 u16 mic : 1;
1147 u16 grp : 1;
1148 u16 spp_mode : 1;
1149 u16 rpt_md : 1;
1150 u16 ext_sectype : 1;
1151 u16 mgnt : 1;
1152 u16 rsvd1 : 4;
1153 u16 valid : 1;
1154 u8 mac_address[6];
1155 u32 key[4];
1156 u32 rsvd[2];
1157 } HALMAC_CAM_ENTRY_FORMAT, *PHALMAC_CAM_ENTRY_FORMAT;
1158
1159 typedef struct _HALMAC_CAM_ENTRY_INFO {
1160 HAL_SECURITY_TYPE security_type;
1161 u32 key[4];
1162 u32 key_ext[4];
1163 u8 mac_address[6];
1164 u8 unicast;
1165 u8 key_id;
1166 u8 valid;
1167 } HALMAC_CAM_ENTRY_INFO, *PHALMAC_CAM_ENTRY_INFO;
1168
1169 #endif /* End of test program */
1170
1171 typedef enum _HALMAC_DBG_MSG_INFO {
1172 HALMAC_DBG_ERR,
1173 HALMAC_DBG_WARN,
1174 HALMAC_DBG_TRACE,
1175 } HALMAC_DBG_MSG_INFO;
1176
1177 typedef enum _HALMAC_DBG_MSG_TYPE {
1178 HALMAC_MSG_INIT,
1179 HALMAC_MSG_EFUSE,
1180 HALMAC_MSG_FW,
1181 HALMAC_MSG_H2C,
1182 HALMAC_MSG_PWR,
1183 HALMAC_MSG_SND,
1184 HALMAC_MSG_COMMON,
1185 } HALMAC_DBG_MSG_TYPE;
1186
1187 typedef enum _HALMAC_CMD_PROCESS_STATUS {
1188 HALMAC_CMD_PROCESS_IDLE = 0x01, /* Init status */
1189 HALMAC_CMD_PROCESS_SENDING = 0x02, /* Wait ack */
1190 HALMAC_CMD_PROCESS_RCVD = 0x03, /* Rcvd ack */
1191 HALMAC_CMD_PROCESS_DONE = 0x04, /* Event done */
1192 HALMAC_CMD_PROCESS_ERROR = 0x05, /* Return code error */
1193 HALMAC_CMD_PROCESS_UNDEFINE = 0x7F,
1194 } HALMAC_CMD_PROCESS_STATUS;
1195
1196 typedef enum _HALMAC_FEATURE_ID {
1197 HALMAC_FEATURE_CFG_PARA, /* Support */
1198 HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE, /* Support */
1199 HALMAC_FEATURE_DUMP_LOGICAL_EFUSE, /* Support */
1200 HALMAC_FEATURE_UPDATE_PACKET, /* Support */
1201 HALMAC_FEATURE_UPDATE_DATAPACK,
1202 HALMAC_FEATURE_RUN_DATAPACK,
1203 HALMAC_FEATURE_CHANNEL_SWITCH, /* Support */
1204 HALMAC_FEATURE_IQK, /* Support */
1205 HALMAC_FEATURE_POWER_TRACKING, /* Support */
1206 HALMAC_FEATURE_PSD, /* Support */
1207 HALMAC_FEATURE_ALL, /* Support, only for reset */
1208 } HALMAC_FEATURE_ID;
1209
1210 typedef enum _HALMAC_DRV_RSVD_PG_NUM {
1211 HALMAC_RSVD_PG_NUM16, /* 2K */
1212 HALMAC_RSVD_PG_NUM24, /* 3K */
1213 HALMAC_RSVD_PG_NUM32, /* 4K */
1214 } HALMAC_DRV_RSVD_PG_NUM;
1215
1216
1217 /* Platform API setting */
1218 typedef struct _HALMAC_PLATFORM_API {
1219 /* R/W register */
1220 u8 (*SDIO_CMD52_READ)(VOID *pDriver_adapter, u32 offset);
1221 u8 (*SDIO_CMD53_READ_8)(VOID *pDriver_adapter, u32 offset);
1222 u16 (*SDIO_CMD53_READ_16)(VOID *pDriver_adapter, u32 offset);
1223 u32 (*SDIO_CMD53_READ_32)(VOID *pDriver_adapter, u32 offset);
1224 VOID (*SDIO_CMD52_WRITE)(VOID *pDriver_adapter, u32 offset, u8 value);
1225 VOID (*SDIO_CMD53_WRITE_8)(VOID *pDriver_adapter, u32 offset, u8 value);
1226 VOID (*SDIO_CMD53_WRITE_16)(VOID *pDriver_adapter, u32 offset, u16 value);
1227 VOID (*SDIO_CMD53_WRITE_32)(VOID *pDriver_adapter, u32 offset, u32 value);
1228 u8 (*REG_READ_8)(VOID *pDriver_adapter, u32 offset);
1229 u16 (*REG_READ_16)(VOID *pDriver_adapter, u32 offset);
1230 u32 (*REG_READ_32)(VOID *pDriver_adapter, u32 offset);
1231 VOID (*REG_WRITE_8)(VOID *pDriver_adapter, u32 offset, u8 value);
1232 VOID (*REG_WRITE_16)(VOID *pDriver_adapter, u32 offset, u16 value);
1233 VOID (*REG_WRITE_32)(VOID *pDriver_adapter, u32 offset, u32 value);
1234
1235 /* send pBuf to reserved page, the tx_desc is not included in pBuf, driver need to fill tx_desc with qsel = bcn */
1236 u8 (*SEND_RSVD_PAGE)(VOID *pDriver_adapter, u8 *pBuf, u32 size);
1237 /* send pBuf to h2c queue, the tx_desc is not included in pBuf, driver need to fill tx_desc with qsel = h2c */
1238 u8 (*SEND_H2C_PKT)(VOID *pDriver_adapter, u8 *pBuf, u32 size);
1239
1240 u8 (*RTL_FREE)(VOID *pDriver_adapter, VOID *pBuf, u32 size);
1241 VOID* (*RTL_MALLOC)(VOID *pDriver_adapter, u32 size);
1242 u8 (*RTL_MEMCPY)(VOID *pDriver_adapter, VOID *dest, VOID *src, u32 size);
1243 u8 (*RTL_MEMSET)(VOID *pDriver_adapter, VOID *pAddress, u8 value, u32 size);
1244 VOID (*RTL_DELAY_US)(VOID *pDriver_adapter, u32 us);
1245
1246 u8 (*MUTEX_INIT)(VOID *pDriver_adapter, HALMAC_MUTEX *pMutex);
1247 u8 (*MUTEX_DEINIT)(VOID *pDriver_adapter, HALMAC_MUTEX *pMutex);
1248 u8 (*MUTEX_LOCK)(VOID *pDriver_adapter, HALMAC_MUTEX *pMutex);
1249 u8 (*MUTEX_UNLOCK)(VOID *pDriver_adapter, HALMAC_MUTEX *pMutex);
1250
1251 u8 (*MSG_PRINT)(VOID *pDriver_adapter, u32 msg_type, u8 msg_level, s8 *fmt, ...);
1252
1253 u8 (*EVENT_INDICATION)(VOID *pDriver_adapter, HALMAC_FEATURE_ID feature_id, HALMAC_CMD_PROCESS_STATUS process_status, u8 *buf, u32 size);
1254
1255 #if HALMAC_PLATFORM_TESTPROGRAM
1256 VOID* (*PCI_ALLOC_COMM_BUFF)(VOID *pDriver_adapter, u32 size, u32 *physical_addr, u8 cache_en);
1257 VOID (*PCI_FREE_COMM_BUFF)(VOID *pDriver_adapter, u32 size, u32 physical_addr, VOID *virtual_addr, u8 cache_en);
1258 u8 (*WRITE_DATA_SDIO_ADDR)(VOID *pDriver_adapter, u8 *pBuf, u32 size, u32 addr);
1259 u8 (*WRITE_DATA_USB_BULKOUT_ID)(VOID *pDriver_adapter, u8 *pBuf, u32 size, u8 bulkout_id);
1260 u8 (*WRITE_DATA_PCIE_QUEUE)(VOID *pDriver_adapter, u8 *pBuf, u32 size, u8 queue);
1261 u8 (*READ_DATA)(VOID *pDriver_adapter, u8 *pBuf, u32 *read_length);
1262 #endif
1263 } HALMAC_PLATFORM_API, *PHALMAC_PLATFORM_API;
1264
1265 /*1->Little endian 0->Big endian*/
1266 #if HALMAC_SYSTEM_ENDIAN
1267
1268 /* User can not use members in Address_L_H, use Address[6] is mandatory */
1269 typedef union _HALMAC_WLAN_ADDR {
1270 u8 Address[6]; /* WLAN address (MACID, BSSID, Brodcast ID). Address[0] is lowest, Address[5] is highest*/
1271 struct {
1272 union {
1273 u32 Address_Low;
1274 u8 Address_Low_B[4];
1275 };
1276 union {
1277 u16 Address_High;
1278 u8 Address_High_B[2];
1279 };
1280 } Address_L_H;
1281 } HALMAC_WLAN_ADDR, *PHALMAC_WLAN_ADDR;
1282
1283 #else
1284
1285 /* User can not use members in Address_L_H, use Address[6] is mandatory */
1286 typedef union _HALMAC_WLAN_ADDR {
1287 u8 Address[6]; /* WLAN address (MACID, BSSID, Brodcast ID). Address[0] is lowest, Address[5] is highest*/
1288 struct {
1289 union {
1290 u32 Address_Low;
1291 u8 Address_Low_B[4];
1292 };
1293 union {
1294 u16 Address_High;
1295 u8 Address_High_B[2];
1296 };
1297 } Address_L_H;
1298 } HALMAC_WLAN_ADDR, *PHALMAC_WLAN_ADDR;
1299
1300 #endif
1301
1302 typedef enum _HALMAC_SND_ROLE {
1303 HAL_BFER = 0,
1304 HAL_BFEE = 1,
1305 } HALMAC_SND_ROLE;
1306
1307 typedef enum _HALMAC_CSI_SEG_LEN {
1308 HAL_CSI_SEG_4K = 0,
1309 HAL_CSI_SEG_8K = 1,
1310 HAL_CSI_SEG_11K = 2,
1311 } HALMAC_CSI_SEG_LEN;
1312
1313
1314 typedef struct _HALMAC_CFG_MUMIMO_PARA {
1315 HALMAC_SND_ROLE role;
1316 u8 sounding_sts[6];
1317 u16 grouping_bitmap;
1318 u8 mu_tx_en;
1319 u32 given_gid_tab[2];
1320 u32 given_user_pos[4];
1321 } HALMAC_CFG_MUMIMO_PARA, *PHALMAC_CFG_MUMIMO_PARA;
1322
1323 typedef struct _HALMAC_SU_BFER_INIT_PARA {
1324 u8 userid;
1325 u16 paid;
1326 u16 csi_para;
1327 PHALMAC_WLAN_ADDR pbfer_address;
1328 } HALMAC_SU_BFER_INIT_PARA, *PHALMAC_SU_BFER_INIT_PARA;
1329
1330 typedef struct _HALMAC_MU_BFEE_INIT_PARA {
1331 u8 userid;
1332 u16 paid;
1333 u32 user_position_l;
1334 u32 user_position_h;
1335 } HALMAC_MU_BFEE_INIT_PARA, *PHALMAC_MU_BFEE_INIT_PARA;
1336
1337 typedef struct _HALMAC_MU_BFER_INIT_PARA {
1338 u16 paid;
1339 u16 csi_para;
1340 u16 my_aid;
1341 HALMAC_CSI_SEG_LEN csi_length_sel;
1342 PHALMAC_WLAN_ADDR pbfer_address;
1343 } HALMAC_MU_BFER_INIT_PARA, *PHALMAC_MU_BFER_INIT_PARA;
1344
1345 typedef struct _HALMAC_SND_INFO {
1346 u16 paid;
1347 u8 userid;
1348 HALMAC_DATA_RATE ndpa_rate;
1349 u16 csi_para;
1350 u16 my_aid;
1351 HALMAC_DATA_RATE csi_rate;
1352 HALMAC_CSI_SEG_LEN csi_length_sel;
1353 HALMAC_SND_ROLE role;
1354 HALMAC_WLAN_ADDR bfer_address;
1355 HALMAC_BW bw;
1356 u8 txbf_en;
1357 PHALMAC_SU_BFER_INIT_PARA pSu_bfer_init;
1358 PHALMAC_MU_BFER_INIT_PARA pMu_bfer_init;
1359 PHALMAC_MU_BFEE_INIT_PARA pMu_bfee_init;
1360 } HALMAC_SND_INFO, *PHALMAC_SND_INFO;
1361
1362 typedef struct _HALMAC_CS_INFO {
1363 u8 *ch_info_buf;
1364 u8 *ch_info_buf_w;
1365 u8 extra_info_en;
1366 u32 buf_size; /* buffer size */
1367 u32 avai_buf_size; /* buffer size */
1368 u32 total_size;
1369 u32 accu_timeout;
1370 u32 ch_num;
1371 } HALMAC_CS_INFO, *PHALMAC_CS_INFO;
1372
1373 typedef struct _HALMAC_RESTORE_INFO {
1374 u32 mac_register;
1375 u32 value;
1376 u8 length;
1377 } HALMAC_RESTORE_INFO, *PHALMAC_RESTORE_INFO;
1378
1379 typedef struct _HALMAC_EVENT_TRIGGER {
1380 u32 physical_efuse_map : 1;
1381 u32 logical_efuse_map : 1;
1382 u32 rsvd1 : 28;
1383 } HALMAC_EVENT_TRIGGER, *PHALMAC_EVENT_TRIGGER;
1384
1385 typedef struct _HALMAC_H2C_HEADER_INFO {
1386 u16 sub_cmd_id;
1387 u16 content_size;
1388 u8 ack;
1389 } HALMAC_H2C_HEADER_INFO, *PHALMAC_H2C_HEADER_INFO;
1390
1391 typedef enum _HALMAC_DLFW_STATE {
1392 HALMAC_DLFW_NONE = 0,
1393 HALMAC_DLFW_DONE = 1,
1394 HALMAC_GEN_INFO_SENT = 2,
1395 HALMAC_DLFW_UNDEFINED = 0x7F,
1396 } HALMAC_DLFW_STATE;
1397
1398 typedef enum _HALMAC_EFUSE_CMD_CONSTRUCT_STATE {
1399 HALMAC_EFUSE_CMD_CONSTRUCT_IDLE = 0,
1400 HALMAC_EFUSE_CMD_CONSTRUCT_BUSY = 1,
1401 HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT = 2,
1402 HALMAC_EFUSE_CMD_CONSTRUCT_STATE_NUM = 3,
1403 HALMAC_EFUSE_CMD_CONSTRUCT_UNDEFINED = 0x7F,
1404 } HALMAC_EFUSE_CMD_CONSTRUCT_STATE;
1405
1406 typedef enum _HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE {
1407 HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE = 0,
1408 HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING = 1,
1409 HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT = 2,
1410 HALMAC_CFG_PARA_CMD_CONSTRUCT_NUM = 3,
1411 HALMAC_CFG_PARA_CMD_CONSTRUCT_UNDEFINED = 0x7F,
1412 } HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE;
1413
1414 typedef enum _HALMAC_SCAN_CMD_CONSTRUCT_STATE {
1415 HALMAC_SCAN_CMD_CONSTRUCT_IDLE = 0,
1416 HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED = 1,
1417 HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING = 2,
1418 HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT = 3,
1419 HALMAC_SCAN_CMD_CONSTRUCT_STATE_NUM = 4,
1420 HALMAC_SCAN_CMD_CONSTRUCT_UNDEFINED = 0x7F,
1421 } HALMAC_SCAN_CMD_CONSTRUCT_STATE;
1422
1423 typedef enum _HALMAC_API_STATE {
1424 HALMAC_API_STATE_INIT = 0,
1425 HALMAC_API_STATE_HALT = 1,
1426 HALMAC_API_STATE_UNDEFINED = 0x7F,
1427 } HALMAC_API_STATE;
1428
1429 typedef struct _HALMAC_EFUSE_STATE_SET {
1430 HALMAC_EFUSE_CMD_CONSTRUCT_STATE efuse_cmd_construct_state;
1431 HALMAC_CMD_PROCESS_STATUS process_status;
1432 u8 fw_return_code;
1433 u16 seq_num;
1434 } HALMAC_EFUSE_STATE_SET, *PHALMAC_EFUSE_STATE_SET;
1435
1436 typedef struct _HALMAC_CFG_PARA_STATE_SET {
1437 HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE cfg_para_cmd_construct_state;
1438 HALMAC_CMD_PROCESS_STATUS process_status;
1439 u8 fw_return_code;
1440 u16 seq_num;
1441 } HALMAC_CFG_PARA_STATE_SET, *PHALMAC_CFG_PARA_STATE_SET;
1442
1443 typedef struct _HALMAC_SCAN_STATE_SET {
1444 HALMAC_SCAN_CMD_CONSTRUCT_STATE scan_cmd_construct_state;
1445 HALMAC_CMD_PROCESS_STATUS process_status;
1446 u8 fw_return_code;
1447 u16 seq_num;
1448 } HALMAC_SCAN_STATE_SET, *PHALMAC_SCAN_STATE_SET;
1449
1450 typedef struct _HALMAC_UPDATE_PACKET_STATE_SET {
1451 HALMAC_CMD_PROCESS_STATUS process_status;
1452 u8 fw_return_code;
1453 u16 seq_num;
1454 } HALMAC_UPDATE_PACKET_STATE_SET, *PHALMAC_UPDATE_PACKET_STATE_SET;
1455
1456 typedef struct _HALMAC_IQK_STATE_SET {
1457 HALMAC_CMD_PROCESS_STATUS process_status;
1458 u8 fw_return_code;
1459 u16 seq_num;
1460 } HALMAC_IQK_STATE_SET, *PHALMAC_IQK_STATE_SET;
1461
1462 typedef struct _HALMAC_POWER_TRACKING_STATE_SET {
1463 HALMAC_CMD_PROCESS_STATUS process_status;
1464 u8 fw_return_code;
1465 u16 seq_num;
1466 } HALMAC_POWER_TRACKING_STATE_SET, *PHALMAC_POWER_TRACKING_STATE_SET;
1467
1468 typedef struct _HALMAC_PSD_STATE_SET {
1469 HALMAC_CMD_PROCESS_STATUS process_status;
1470 u16 data_size;
1471 u16 segment_size;
1472 u8 *pData;
1473 u8 fw_return_code;
1474 u16 seq_num;
1475 } HALMAC_PSD_STATE_SET, *PHALMAC_PSD_STATE_SET;
1476
1477 typedef struct _HALMAC_STATE {
1478 HALMAC_EFUSE_STATE_SET efuse_state_set; /* State machine + cmd process status */
1479 HALMAC_CFG_PARA_STATE_SET cfg_para_state_set; /* State machine + cmd process status */
1480 HALMAC_SCAN_STATE_SET scan_state_set; /* State machine + cmd process status */
1481 HALMAC_UPDATE_PACKET_STATE_SET update_packet_set; /* cmd process status */
1482 HALMAC_IQK_STATE_SET iqk_set; /* cmd process status */
1483 HALMAC_POWER_TRACKING_STATE_SET power_tracking_set; /* cmd process status */
1484 HALMAC_PSD_STATE_SET psd_set; /* cmd process status */
1485 HALMAC_API_STATE api_state; /* Halmac api state */
1486 HALMAC_MAC_POWER mac_power; /* 0 : power off, 1 : power on*/
1487 HALMAC_PS_STATE ps_state; /* power saving state */
1488 HALMAC_DLFW_STATE dlfw_state; /* download FW state */
1489 } HALMAC_STATE, *PHALMAC_STATE;
1490
1491 typedef struct _HALMAC_VER {
1492 u8 major_ver;
1493 u8 prototype_ver;
1494 u8 minor_ver;
1495 } HALMAC_VER, *PHALMAC_VER;
1496
1497
1498 typedef enum _HALMAC_API_ID {
1499 /*stuff, need to be the 1st*/
1500 HALMAC_API_STUFF = 0x0,
1501 /*stuff, need to be the 1st*/
1502 HALMAC_API_MAC_POWER_SWITCH = 0x1,
1503 HALMAC_API_DOWNLOAD_FIRMWARE = 0x2,
1504 HALMAC_API_CFG_MAC_ADDR = 0x3,
1505 HALMAC_API_CFG_BSSID = 0x4,
1506 HALMAC_API_CFG_MULTICAST_ADDR = 0x5,
1507 HALMAC_API_PRE_INIT_SYSTEM_CFG = 0x6,
1508 HALMAC_API_INIT_SYSTEM_CFG = 0x7,
1509 HALMAC_API_INIT_TRX_CFG = 0x8,
1510 HALMAC_API_CFG_RX_AGGREGATION = 0x9,
1511 HALMAC_API_INIT_PROTOCOL_CFG = 0xA,
1512 HALMAC_API_INIT_EDCA_CFG = 0xB,
1513 HALMAC_API_CFG_OPERATION_MODE = 0xC,
1514 HALMAC_API_CFG_CH_BW = 0xD,
1515 HALMAC_API_CFG_BW = 0xE,
1516 HALMAC_API_INIT_WMAC_CFG = 0xF,
1517 HALMAC_API_INIT_MAC_CFG = 0x10,
1518 HALMAC_API_INIT_SDIO_CFG = 0x11,
1519 HALMAC_API_INIT_USB_CFG = 0x12,
1520 HALMAC_API_INIT_PCIE_CFG = 0x13,
1521 HALMAC_API_INIT_INTERFACE_CFG = 0x14,
1522 HALMAC_API_DEINIT_SDIO_CFG = 0x15,
1523 HALMAC_API_DEINIT_USB_CFG = 0x16,
1524 HALMAC_API_DEINIT_PCIE_CFG = 0x17,
1525 HALMAC_API_DEINIT_INTERFACE_CFG = 0x18,
1526 HALMAC_API_GET_EFUSE_SIZE = 0x19,
1527 HALMAC_API_DUMP_EFUSE_MAP = 0x1A,
1528 HALMAC_API_WRITE_EFUSE = 0x1B,
1529 HALMAC_API_READ_EFUSE = 0x1C,
1530 HALMAC_API_GET_LOGICAL_EFUSE_SIZE = 0x1D,
1531 HALMAC_API_DUMP_LOGICAL_EFUSE_MAP = 0x1E,
1532 HALMAC_API_WRITE_LOGICAL_EFUSE = 0x1F,
1533 HALMAC_API_READ_LOGICAL_EFUSE = 0x20,
1534 HALMAC_API_PG_EFUSE_BY_MAP = 0x21,
1535 HALMAC_API_GET_C2H_INFO = 0x22,
1536 HALMAC_API_CFG_FWLPS_OPTION = 0x23,
1537 HALMAC_API_CFG_FWIPS_OPTION = 0x24,
1538 HALMAC_API_ENTER_WOWLAN = 0x25,
1539 HALMAC_API_LEAVE_WOWLAN = 0x26,
1540 HALMAC_API_ENTER_PS = 0x27,
1541 HALMAC_API_LEAVE_PS = 0x28,
1542 HALMAC_API_H2C_LB = 0x29,
1543 HALMAC_API_DEBUG = 0x2A,
1544 HALMAC_API_CFG_PARAMETER = 0x2B,
1545 HALMAC_API_UPDATE_PACKET = 0x2C,
1546 HALMAC_API_BCN_IE_FILTER = 0x2D,
1547 HALMAC_API_REG_READ_8 = 0x2E,
1548 HALMAC_API_REG_WRITE_8 = 0x2F,
1549 HALMAC_API_REG_READ_16 = 0x30,
1550 HALMAC_API_REG_WRITE_16 = 0x31,
1551 HALMAC_API_REG_READ_32 = 0x32,
1552 HALMAC_API_REG_WRITE_32 = 0x33,
1553 HALMAC_API_TX_ALLOWED_SDIO = 0x34,
1554 HALMAC_API_SET_BULKOUT_NUM = 0x35,
1555 HALMAC_API_GET_SDIO_TX_ADDR = 0x36,
1556 HALMAC_API_GET_USB_BULKOUT_ID = 0x37,
1557 HALMAC_API_TIMER_2S = 0x38,
1558 HALMAC_API_FILL_TXDESC_CHECKSUM = 0x39,
1559 HALMAC_API_SEND_ORIGINAL_H2C = 0x3A,
1560 HALMAC_API_UPDATE_DATAPACK = 0x3B,
1561 HALMAC_API_RUN_DATAPACK = 0x3C,
1562 HALMAC_API_CFG_DRV_INFO = 0x3D,
1563 HALMAC_API_SEND_BT_COEX = 0x3E,
1564 HALMAC_API_VERIFY_PLATFORM_API = 0x3F,
1565 HALMAC_API_GET_FIFO_SIZE = 0x40,
1566 HALMAC_API_DUMP_FIFO = 0x41,
1567 HALMAC_API_CFG_TXBF = 0x42,
1568 HALMAC_API_CFG_MUMIMO = 0x43,
1569 HALMAC_API_CFG_SOUNDING = 0x44,
1570 HALMAC_API_DEL_SOUNDING = 0x45,
1571 HALMAC_API_SU_BFER_ENTRY_INIT = 0x46,
1572 HALMAC_API_SU_BFEE_ENTRY_INIT = 0x47,
1573 HALMAC_API_MU_BFER_ENTRY_INIT = 0x48,
1574 HALMAC_API_MU_BFEE_ENTRY_INIT = 0x49,
1575 HALMAC_API_SU_BFER_ENTRY_DEL = 0x4A,
1576 HALMAC_API_SU_BFEE_ENTRY_DEL = 0x4B,
1577 HALMAC_API_MU_BFER_ENTRY_DEL = 0x4C,
1578 HALMAC_API_MU_BFEE_ENTRY_DEL = 0x4D,
1579
1580 HALMAC_API_ADD_CH_INFO = 0x4E,
1581 HALMAC_API_ADD_EXTRA_CH_INFO = 0x4F,
1582 HALMAC_API_CTRL_CH_SWITCH = 0x50,
1583 HALMAC_API_CLEAR_CH_INFO = 0x51,
1584
1585 HALMAC_API_SEND_GENERAL_INFO = 0x52,
1586 HALMAC_API_START_IQK = 0x53,
1587 HALMAC_API_CTRL_PWR_TRACKING = 0x54,
1588 HALMAC_API_PSD = 0x55,
1589 HALMAC_API_CFG_TX_AGG_ALIGN = 0x56,
1590
1591 HALMAC_API_QUERY_STATE = 0x57,
1592 HALMAC_API_RESET_FEATURE = 0x58,
1593 HALMAC_API_CHECK_FW_STATUS = 0x59,
1594 HALMAC_API_DUMP_FW_DMEM = 0x5A,
1595 HALMAC_API_CFG_MAX_DL_SIZE = 0x5B,
1596
1597 HALMAC_API_INIT_OBJ = 0x5C,
1598 HALMAC_API_DEINIT_OBJ = 0x5D,
1599 HALMAC_API_CFG_LA_MODE = 0x5E,
1600 HALMAC_API_GET_HW_VALUE = 0x5F,
1601 HALMAC_API_SET_HW_VALUE = 0x60,
1602 HALMAC_API_CFG_DRV_RSVD_PG_NUM = 0x61,
1603 HALMAC_API_SWITCH_EFUSE_BANK = 0x62,
1604 HALMAC_API_WRITE_EFUSE_BT = 0x63,
1605 HALMAC_API_DUMP_EFUSE_MAP_BT = 0x64,
1606 HALMAC_API_MAX
1607 } HALMAC_API_ID;
1608
1609
1610 typedef struct _HALMAC_API_RECORD {
1611 HALMAC_API_ID api_array[API_ARRAY_SIZE];
1612 u8 array_wptr;
1613 } HALMAC_API_RECORD, *PHALMAC_API_RECORD;
1614
1615 typedef enum _HALMAC_LA_MODE {
1616 HALMAC_LA_MODE_DISABLE = 0,
1617 HALMAC_LA_MODE_PARTIAL = 1,
1618 HALMAC_LA_MODE_FULL = 2,
1619 HALMAC_LA_MODE_UNDEFINE = 0x7F,
1620 } HALMAC_LA_MODE;
1621
1622 typedef enum _HALMAC_USB_MODE {
1623 HALMAC_USB_MODE_U2 = 1,
1624 HALMAC_USB_MODE_U3 = 2,
1625 } HALMAC_USB_MODE;
1626
1627 typedef enum _HALMAC_HW_ID {
1628 HALMAC_HW_RQPN_MAPPING = 0,
1629 HALMAC_HW_EFUSE_SIZE = 1,
1630 HALMAC_HW_EEPROM_SIZE = 2,
1631 HALMAC_HW_TXFIFO_SIZE = 3,
1632 HALMAC_HW_RSVD_PG_BNDY = 4,
1633 HALMAC_HW_CAM_ENTRY_NUM = 5,
1634 HALMAC_HW_HRPWM = 6,
1635 HALMAC_HW_HCPWM = 7,
1636 HALMAC_HW_HRPWM2 = 8,
1637 HALMAC_HW_HCPWM2 = 9,
1638 HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE = 10,
1639 HALMAC_HW_TXFF_ALLOCATION = 11,
1640 HALMAC_HW_USB_MODE = 12,
1641 HALMAC_HW_SEQ_EN = 13,
1642 HALMAC_HW_BANDWIDTH = 14,
1643 HALMAC_HW_CHANNEL = 15,
1644 HALMAC_HW_PRI_CHANNEL_IDX = 16,
1645 HALMAC_HW_EN_BB_RF = 17,
1646 HALMAC_HW_BT_BANK_EFUSE_SIZE = 18,
1647 HALMAC_HW_BT_BANK1_EFUSE_SIZE = 19,
1648 HALMAC_HW_BT_BANK2_EFUSE_SIZE = 20,
1649 HALMAC_HW_ID_UNDEFINE = 0x7F,
1650 } HALMAC_HW_ID;
1651 typedef enum _HALMAC_EFUSE_BANK {
1652 HALMAC_EFUSE_BANK_WIFI = 0,
1653 HALMAC_EFUSE_BANK_BT = 1,
1654 HALMAC_EFUSE_BANK_BT_1 = 2,
1655 HALMAC_EFUSE_BANK_BT_2 = 3,
1656 HALMAC_EFUSE_BANK_MAX,
1657 HALMAC_EFUSE_BANK_UNDEFINE = 0X7F,
1658 } HALMAC_EFUSE_BANK;
1659
1660 typedef struct _HALMAC_TXFF_ALLOCATION {
1661 u16 tx_fifo_pg_num;
1662 u16 rsvd_pg_num;
1663 u16 rsvd_drv_pg_num;
1664 u16 ac_q_pg_num;
1665 u16 high_queue_pg_num;
1666 u16 low_queue_pg_num;
1667 u16 normal_queue_pg_num;
1668 u16 extra_queue_pg_num;
1669 u16 pub_queue_pg_num;
1670 u16 rsvd_pg_bndy;
1671 u16 rsvd_drv_pg_bndy;
1672 u16 rsvd_h2c_extra_info_pg_bndy;
1673 u16 rsvd_h2c_queue_pg_bndy;
1674 u16 rsvd_cpu_instr_pg_bndy;
1675 u16 rsvd_fw_txbuff_pg_bndy;
1676 HALMAC_LA_MODE la_mode;
1677 } HALMAC_TXFF_ALLOCATION, *PHALMAC_TXFF_ALLOCATION;
1678
1679 typedef struct _HALMAC_RQPN_MAP {
1680 HALMAC_DMA_MAPPING dma_map_vo;
1681 HALMAC_DMA_MAPPING dma_map_vi;
1682 HALMAC_DMA_MAPPING dma_map_be;
1683 HALMAC_DMA_MAPPING dma_map_bk;
1684 HALMAC_DMA_MAPPING dma_map_mg;
1685 HALMAC_DMA_MAPPING dma_map_hi;
1686 } HALMAC_RQPN_MAP, *PHALMAC_RQPN_MAP;
1687
1688 /* Hal mac adapter */
1689 typedef struct _HALMAC_ADAPTER {
1690 HALMAC_DMA_MAPPING halmac_ptcl_queue[HALMAC_PTCL_QUEUE_NUM]; /* Dma mapping of protocol queues */
1691 HALMAC_FWLPS_OPTION fwlps_option; /* low power state option */
1692 HALMAC_WLAN_ADDR pHal_mac_addr[2]; /* mac address information, suppot 2 ports */
1693 HALMAC_WLAN_ADDR pHal_bss_addr[2]; /* bss address information, suppot 2 ports */
1694 HALMAC_MUTEX h2c_seq_mutex; /* Protect h2c_packet_seq packet*/
1695 HALMAC_MUTEX EfuseMutex; /* Protect Efuse map memory of halmac_adapter */
1696 HALMAC_CONFIG_PARA_INFO config_para_info;
1697 HALMAC_CS_INFO ch_sw_info;
1698 HALMAC_EVENT_TRIGGER event_trigger;
1699 HALMAC_HW_CONFIG_INFO hw_config_info; /* HW related information */
1700 HALMAC_SDIO_FREE_SPACE sdio_free_space;
1701 HALMAC_SND_INFO snd_info;
1702 VOID *pHalAdapter_backup; /* Backup HalAdapter address */
1703 VOID *pDriver_adapter; /* Driver or FW adapter address. Do not write this memory*/
1704 u8 *pHalEfuse_map;
1705 VOID *pHalmac_api; /* Record function pointer of halmac api */
1706 PHALMAC_PLATFORM_API pHalmac_platform_api; /* Record function pointer of platform api */
1707 u32 efuse_end; /* Record efuse used memory */
1708 u32 h2c_buf_free_space;
1709 u32 h2c_buff_size;
1710 u32 max_download_size;
1711 HALMAC_CHIP_ID chip_id; /* Chip ID, 8822B, 8821C... */
1712 HALMAC_CHIP_VER chip_version; /* A cut, B cut... */
1713 HALMAC_FW_VERSION fw_version;
1714 HALMAC_STATE halmac_state;
1715 HALMAC_INTERFACE halmac_interface; /* Interface information, get from driver */
1716 HALMAC_TRX_MODE trx_mode; /* Noraml, WMM, P2P, LoopBack... */
1717 HALMAC_TXFF_ALLOCATION txff_allocation;
1718 u8 h2c_packet_seq; /* current h2c packet sequence number */
1719 u16 ack_h2c_packet_seq; /*the acked h2c packet sequence number */
1720 u8 hal_efuse_map_valid;
1721 u8 efuse_segment_size;
1722 u8 rpwm_record; /* record rpwm value */
1723 u8 low_clk; /*LPS 32K or IPS 32K*/
1724 u8 halmac_bulkout_num; /* USB bulkout num */
1725 HALMAC_API_RECORD api_record; /* API record */
1726 u8 gen_info_valid;
1727 HALMAC_GENERAL_INFO general_info;
1728 #if HALMAC_PLATFORM_TESTPROGRAM
1729 HALMAC_TXAGG_BUFF_INFO halmac_tx_buf_info[4];
1730 HALMAC_MUTEX agg_buff_mutex; /*used for tx_agg_buffer */
1731 u8 max_agg_num;
1732 u8 send_bcn_reg_cr_backup;
1733 #endif
1734 } HALMAC_ADAPTER, *PHALMAC_ADAPTER;
1735
1736
1737 /* Fuction pointer of Hal mac API */
1738 typedef struct _HALMAC_API {
1739 HALMAC_RET_STATUS (*halmac_mac_power_switch)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_MAC_POWER halmac_power);
1740 HALMAC_RET_STATUS (*halmac_download_firmware)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size);
1741 HALMAC_RET_STATUS (*halmac_get_fw_version)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_FW_VERSION pFw_version);
1742 HALMAC_RET_STATUS (*halmac_cfg_mac_addr)(PHALMAC_ADAPTER pHalmac_adapter, u8 halmac_port, PHALMAC_WLAN_ADDR pHal_address);
1743 HALMAC_RET_STATUS (*halmac_cfg_bssid)(PHALMAC_ADAPTER pHalmac_adapter, u8 halmac_port, PHALMAC_WLAN_ADDR pHal_address);
1744 HALMAC_RET_STATUS (*halmac_cfg_multicast_addr)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_WLAN_ADDR pHal_address);
1745 HALMAC_RET_STATUS (*halmac_pre_init_system_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
1746 HALMAC_RET_STATUS (*halmac_init_system_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
1747 HALMAC_RET_STATUS (*halmac_init_trx_cfg)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_TRX_MODE Mode);
1748 HALMAC_RET_STATUS (*halmac_init_h2c)(PHALMAC_ADAPTER pHalmac_adapter);
1749 HALMAC_RET_STATUS (*halmac_cfg_rx_aggregation)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_RXAGG_CFG phalmac_rxagg_cfg);
1750 HALMAC_RET_STATUS (*halmac_init_protocol_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
1751 HALMAC_RET_STATUS (*halmac_init_edca_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
1752 HALMAC_RET_STATUS (*halmac_cfg_operation_mode)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_WIRELESS_MODE wireless_mode);
1753 HALMAC_RET_STATUS (*halmac_cfg_ch_bw)(PHALMAC_ADAPTER pHalmac_adapter, u8 channel, HALMAC_PRI_CH_IDX pri_ch_idx, HALMAC_BW bw);
1754 HALMAC_RET_STATUS (*halmac_cfg_bw)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_BW bw);
1755 HALMAC_RET_STATUS (*halmac_init_wmac_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
1756 HALMAC_RET_STATUS (*halmac_init_mac_cfg)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_TRX_MODE Mode);
1757 HALMAC_RET_STATUS (*halmac_init_sdio_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
1758 HALMAC_RET_STATUS (*halmac_init_usb_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
1759 HALMAC_RET_STATUS (*halmac_init_pcie_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
1760 HALMAC_RET_STATUS (*halmac_init_interface_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
1761 HALMAC_RET_STATUS (*halmac_deinit_sdio_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
1762 HALMAC_RET_STATUS (*halmac_deinit_usb_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
1763 HALMAC_RET_STATUS (*halmac_deinit_pcie_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
1764 HALMAC_RET_STATUS (*halmac_deinit_interface_cfg)(PHALMAC_ADAPTER pHalmac_adapter);
1765 HALMAC_RET_STATUS (*halmac_get_efuse_size)(PHALMAC_ADAPTER pHalmac_adapter, u32 *halmac_size);
1766 HALMAC_RET_STATUS (*halmac_get_efuse_available_size)(PHALMAC_ADAPTER pHalmac_adapter, u32 *halmac_size);
1767 HALMAC_RET_STATUS (*halmac_dump_efuse_map)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_EFUSE_READ_CFG cfg);
1768 HALMAC_RET_STATUS (*halmac_dump_efuse_map_bt)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_EFUSE_BANK halmac_efues_bank, u32 bt_efuse_map_size, u8 *pBT_efuse_map);
1769 HALMAC_RET_STATUS (*halmac_write_efuse)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 halmac_value);
1770 HALMAC_RET_STATUS (*halmac_read_efuse)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 *pValue);
1771 HALMAC_RET_STATUS (*halmac_switch_efuse_bank)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_EFUSE_BANK halmac_efues_bank);
1772 HALMAC_RET_STATUS (*halmac_write_efuse_bt)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 halmac_value, HALMAC_EFUSE_BANK halmac_efues_bank);
1773 HALMAC_RET_STATUS (*halmac_get_logical_efuse_size)(PHALMAC_ADAPTER pHalmac_adapter, u32 *halmac_size);
1774 HALMAC_RET_STATUS (*halmac_dump_logical_efuse_map)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_EFUSE_READ_CFG cfg);
1775 HALMAC_RET_STATUS (*halmac_write_logical_efuse)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 halmac_value);
1776 HALMAC_RET_STATUS (*halmac_read_logical_efuse)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 *pValue);
1777 HALMAC_RET_STATUS (*halmac_pg_efuse_by_map)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_PG_EFUSE_INFO pPg_efuse_info, HALMAC_EFUSE_READ_CFG cfg);
1778 HALMAC_RET_STATUS (*halmac_get_c2h_info)(PHALMAC_ADAPTER pHalmac_adapter, u8 *halmac_buf, u32 halmac_size);
1779 HALMAC_RET_STATUS (*halmac_cfg_fwlps_option)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_FWLPS_OPTION pLps_option);
1780 HALMAC_RET_STATUS (*halmac_cfg_fwips_option)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_FWIPS_OPTION pIps_option);
1781 HALMAC_RET_STATUS (*halmac_enter_wowlan)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_WOWLAN_OPTION pWowlan_option);
1782 HALMAC_RET_STATUS (*halmac_leave_wowlan)(PHALMAC_ADAPTER pHalmac_adapter);
1783 HALMAC_RET_STATUS (*halmac_enter_ps)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_PS_STATE ps_state);
1784 HALMAC_RET_STATUS (*halmac_leave_ps)(PHALMAC_ADAPTER pHalmac_adapter);
1785 HALMAC_RET_STATUS (*halmac_h2c_lb)(PHALMAC_ADAPTER pHalmac_adapter);
1786 HALMAC_RET_STATUS (*halmac_debug)(PHALMAC_ADAPTER pHalmac_adapter);
1787 HALMAC_RET_STATUS (*halmac_cfg_parameter)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_PHY_PARAMETER_INFO para_info, u8 full_fifo);
1788 HALMAC_RET_STATUS (*halmac_update_packet)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_PACKET_ID pkt_id, u8 *pkt, u32 pkt_size);
1789 HALMAC_RET_STATUS (*halmac_bcn_ie_filter)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_BCN_IE_INFO pBcn_ie_info);
1790 u8 (*halmac_reg_read_8)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset);
1791 HALMAC_RET_STATUS (*halmac_reg_write_8)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 halmac_data);
1792 u16 (*halmac_reg_read_16)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset);
1793 HALMAC_RET_STATUS (*halmac_reg_write_16)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u16 halmac_data);
1794 u32 (*halmac_reg_read_32)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset);
1795 HALMAC_RET_STATUS (*halmac_reg_write_32)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u32 halmac_data);
1796 HALMAC_RET_STATUS (*halmac_tx_allowed_sdio)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHalmac_buf, u32 halmac_size);
1797 HALMAC_RET_STATUS (*halmac_set_bulkout_num)(PHALMAC_ADAPTER pHalmac_adapter, u8 bulkout_num);
1798 HALMAC_RET_STATUS (*halmac_get_sdio_tx_addr)(PHALMAC_ADAPTER pHalmac_adapter, u8 *halmac_buf, u32 halmac_size, u32 *pcmd53_addr);
1799 HALMAC_RET_STATUS (*halmac_get_usb_bulkout_id)(PHALMAC_ADAPTER pHalmac_adapter, u8 *halmac_buf, u32 halmac_size, u8 *bulkout_id);
1800 HALMAC_RET_STATUS (*halmac_timer_2s)(PHALMAC_ADAPTER pHalmac_adapter);
1801 HALMAC_RET_STATUS (*halmac_fill_txdesc_checksum)(PHALMAC_ADAPTER pHalmac_adapter, u8 *cur_desc);
1802 HALMAC_RET_STATUS (*halmac_update_datapack)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_DATA_TYPE halmac_data_type, PHALMAC_PHY_PARAMETER_INFO para_info);
1803 HALMAC_RET_STATUS (*halmac_run_datapack)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_DATA_TYPE halmac_data_type);
1804 HALMAC_RET_STATUS (*halmac_cfg_drv_info)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_DRV_INFO halmac_drv_info);
1805 HALMAC_RET_STATUS (*halmac_send_bt_coex)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBt_buf, u32 bt_size, u8 ack);
1806 HALMAC_RET_STATUS (*halmac_verify_platform_api)(PHALMAC_ADAPTER pHalmac_adapte);
1807 u32 (*halmac_get_fifo_size)(PHALMAC_ADAPTER pHalmac_adapter, HAL_FIFO_SEL halmac_fifo_sel);
1808 HALMAC_RET_STATUS (*halmac_dump_fifo)(PHALMAC_ADAPTER pHalmac_adapter, HAL_FIFO_SEL halmac_fifo_sel, u8 *pFifo_map, u32 halmac_fifo_dump_size);
1809 HALMAC_RET_STATUS (*halmac_cfg_txbf)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid, HALMAC_BW bw, u8 txbf_en);
1810 HALMAC_RET_STATUS (*halmac_cfg_mumimo)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CFG_MUMIMO_PARA pCfgmu);
1811 HALMAC_RET_STATUS (*halmac_cfg_sounding)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_SND_ROLE role, HALMAC_DATA_RATE datarate);
1812 HALMAC_RET_STATUS (*halmac_del_sounding)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_SND_ROLE role);
1813 HALMAC_RET_STATUS (*halmac_su_bfer_entry_init)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_SU_BFER_INIT_PARA pSu_bfer_init);
1814 HALMAC_RET_STATUS (*halmac_su_bfee_entry_init)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid, u16 paid);
1815 HALMAC_RET_STATUS (*halmac_mu_bfer_entry_init)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_MU_BFER_INIT_PARA pMu_bfer_init);
1816 HALMAC_RET_STATUS (*halmac_mu_bfee_entry_init)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_MU_BFEE_INIT_PARA pMu_bfee_init);
1817 HALMAC_RET_STATUS (*halmac_su_bfer_entry_del)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid);
1818 HALMAC_RET_STATUS (*halmac_su_bfee_entry_del)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid);
1819 HALMAC_RET_STATUS (*halmac_mu_bfer_entry_del)(PHALMAC_ADAPTER pHalmac_adapter);
1820 HALMAC_RET_STATUS (*halmac_mu_bfee_entry_del)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid);
1821 HALMAC_RET_STATUS (*halmac_add_ch_info)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CH_INFO pCh_info);
1822 HALMAC_RET_STATUS (*halmac_add_extra_ch_info)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CH_EXTRA_INFO pCh_extra_info);
1823 HALMAC_RET_STATUS (*halmac_ctrl_ch_switch)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CH_SWITCH_OPTION pCs_option);
1824 HALMAC_RET_STATUS (*halmac_clear_ch_info)(PHALMAC_ADAPTER pHalmac_adapter);
1825 HALMAC_RET_STATUS (*halmac_send_general_info)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_GENERAL_INFO pgGeneral_info);
1826 HALMAC_RET_STATUS (*halmac_start_iqk)(PHALMAC_ADAPTER pHalmac_adapter, u8 clear);
1827 HALMAC_RET_STATUS (*halmac_ctrl_pwr_tracking)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_PWR_TRACKING_OPTION pPwr_tracking_opt);
1828 HALMAC_RET_STATUS (*halmac_psd)(PHALMAC_ADAPTER pHalmac_adapter, u16 start_psd, u16 end_psd);
1829 HALMAC_RET_STATUS (*halmac_cfg_tx_agg_align)(PHALMAC_ADAPTER pHalmac_adapter, u8 enable, u16 align_size);
1830 HALMAC_RET_STATUS (*halmac_query_status)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_FEATURE_ID feature_id, HALMAC_CMD_PROCESS_STATUS *pProcess_status, u8 *data, u32 *size);
1831 HALMAC_RET_STATUS (*halmac_reset_feature)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_FEATURE_ID feature_id);
1832 HALMAC_RET_STATUS (*halmac_check_fw_status)(PHALMAC_ADAPTER pHalmac_adapter, u8 *fw_status);
1833 HALMAC_RET_STATUS (*halmac_dump_fw_dmem)(PHALMAC_ADAPTER pHalmac_adapter, u8 *dmem, u32 *size);
1834 HALMAC_RET_STATUS (*halmac_cfg_max_dl_size)(PHALMAC_ADAPTER pHalmac_adapter, u32 size);
1835 HALMAC_RET_STATUS (*halmac_cfg_la_mode)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_LA_MODE la_mode);
1836 HALMAC_RET_STATUS (*halmac_get_hw_value)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_HW_ID hw_id, VOID *pvalue);
1837 HALMAC_RET_STATUS (*halmac_set_hw_value)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_HW_ID hw_id, VOID *pvalue);
1838 HALMAC_RET_STATUS (*halmac_cfg_drv_rsvd_pg_num)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_DRV_RSVD_PG_NUM pg_num);
1839 HALMAC_RET_STATUS (*halmac_get_chip_version)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_VER *version);
1840 HALMAC_RET_STATUS (*halmac_chk_txdesc)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHalmac_buf, u32 halmac_size);
1841 #if HALMAC_PLATFORM_TESTPROGRAM
1842 HALMAC_RET_STATUS (*halmac_gen_txdesc)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pPcket_buffer, PHAL_TXDESC_INFO pTxdesc_info);
1843 HALMAC_RET_STATUS (*halmac_txdesc_parser)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pTxdesc, PHAL_TXDESC_PARSER pTxdesc_parser);
1844 HALMAC_RET_STATUS (*halmac_rxdesc_parser)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pRxdesc, PHAL_RXDESC_PARSER pRxdesc_parser);
1845 HALMAC_RET_STATUS (*halmac_get_txdesc_size)(PHALMAC_ADAPTER pHalmac_adapter, PHAL_TXDESC_INFO pTxdesc_info, u32 *size);
1846 HALMAC_RET_STATUS (*halmac_send_packet)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 size, PHAL_TXDESC_INFO pTxdesc_Info);
1847 HALMAC_RET_STATUS (*halmac_get_pcie_packet)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 *size);
1848 HALMAC_RET_STATUS (*halmac_gen_txagg_desc)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pPcket_buffer, u32 agg_num);
1849 HALMAC_RET_STATUS (*halmac_parse_packet)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, PHAL_RXDESC_INFO pRxdesc_info, u8 **next_pkt);
1850 u32 (*halmac_bb_reg_read)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 len);
1851 HALMAC_RET_STATUS (*halmac_bb_reg_write)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u32 halmac_data, u8 len);
1852 u32 (*halmac_rf_reg_read)(PHALMAC_ADAPTER pHalmac_adapter, PHAL_RF_REG_INFO pRf_reg_info);
1853 HALMAC_RET_STATUS (*halmac_rf_reg_write)(PHALMAC_ADAPTER pHalmac_adapter, PHAL_RF_REG_INFO pRf_reg_info);
1854 HALMAC_RET_STATUS (*halmac_init_antenna_selection)(PHALMAC_ADAPTER pHalmac_adapter);
1855 HALMAC_RET_STATUS (*halmac_bb_preconfig)(PHALMAC_ADAPTER pHalmac_adapter);
1856 HALMAC_RET_STATUS (*halmac_init_crystal_capacity)(PHALMAC_ADAPTER pHalmac_adapter);
1857 HALMAC_RET_STATUS (*halmac_trx_antenna_setting)(PHALMAC_ADAPTER pHalmac_adapter);
1858 HALMAC_RET_STATUS (*halmac_himr_setting_sdio)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_SDIO_HIMR_INFO sdio_himr_sdio);
1859 HALMAC_RET_STATUS (*halmac_config_security)(PHALMAC_ADAPTER pHalmac_adapter, PHAL_SECURITY_INFO pSecurity_info);
1860 HALMAC_RET_STATUS (*halmac_write_cam)(PHALMAC_ADAPTER pHalmac_adapter, u32 entry_index, PHALMAC_CAM_ENTRY_INFO pCam_entry_info);
1861 HALMAC_RET_STATUS (*halmac_read_cam)(PHALMAC_ADAPTER pHalmac_adapter, u32 entry_index, PHALMAC_CAM_ENTRY_FORMAT pContent);
1862 HALMAC_RET_STATUS (*halmac_dump_cam_table)(PHALMAC_ADAPTER pHalmac_adapter, u32 entry_num, PHALMAC_CAM_ENTRY_FORMAT pCam_table);
1863 HALMAC_RET_STATUS (*halmac_load_cam_table)(PHALMAC_ADAPTER pHalmac_adapter, u8 entry_num, PHALMAC_CAM_ENTRY_FORMAT pCam_table);
1864 HALMAC_RET_STATUS (*halmac_send_beacon)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 size, PHALMAC_BEACON_INFO pbeacon_info);
1865 HALMAC_RET_STATUS (*halmac_get_management_txdesc)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 *pSize, PHALMAC_MGNT_INFO pmgnt_info);
1866 HALMAC_RET_STATUS (*halmac_send_control)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 size, PHALMAC_CTRL_INFO pctrl_info);
1867 HALMAC_RET_STATUS (*halmac_send_hiqueue)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBuf, u32 size, PHALMAC_HIGH_QUEUE_INFO pHigh_info);
1868 HALMAC_RET_STATUS (*halmac_run_pwrseq)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_PWR_SEQ_ID seq);
1869 HALMAC_RET_STATUS (*halmac_media_status_rpt)(PHALMAC_ADAPTER pHalmac_adapter, u8 op_mode, u8 mac_id_ind, u8 mac_id, u8 mac_id_end);
1870 HALMAC_RET_STATUS (*halmac_stop_beacon)(PHALMAC_ADAPTER pHalmac_adapter);
1871 HALMAC_RET_STATUS (*halmac_check_trx_status)(PHALMAC_ADAPTER pHalmac_adapter);
1872 HALMAC_RET_STATUS (*halmac_set_agg_num)(PHALMAC_ADAPTER pHalmac_adapter, u8 agg_num);
1873 HALMAC_RET_STATUS (*halmac_timer_10ms)(PHALMAC_ADAPTER pHalmac_adapter);
1874 HALMAC_RET_STATUS (*halmac_download_firmware_fpag)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size, u32 iram_address);
1875 HALMAC_RET_STATUS (*halmac_download_rom_fpga)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size, u32 rom_address);
1876 HALMAC_RET_STATUS (*halmac_download_flash)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size, u32 rom_address);
1877 HALMAC_RET_STATUS (*halmac_erase_flash)(PHALMAC_ADAPTER pHalmac_adapter);
1878 HALMAC_RET_STATUS (*halmac_check_flash)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size);
1879 HALMAC_RET_STATUS (*halmac_send_nlo)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_NLO_CFG pNlo_cfg);
1880 HALMAC_RET_STATUS (*halmac_get_chip_type)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CHIP_TYPE pChip_type);
1881 u32 (*halmac_get_rx_agg_num)(PHALMAC_ADAPTER pHalmac_adapter, u32 pkt_size, u8 *pPkt_buff);
1882 #endif
1883 } HALMAC_API, *PHALMAC_API;
1884
1885 #define HALMAC_GET_API(phalmac_adapter) ((PHALMAC_API)phalmac_adapter->pHalmac_api)
1886
1887 static HALMAC_INLINE HALMAC_RET_STATUS
halmac_adapter_validate(PHALMAC_ADAPTER pHalmac_adapter)1888 halmac_adapter_validate(
1889 PHALMAC_ADAPTER pHalmac_adapter
1890 )
1891 {
1892 if ((NULL == pHalmac_adapter) || (pHalmac_adapter->pHalAdapter_backup != pHalmac_adapter))
1893 return HALMAC_RET_ADAPTER_INVALID;
1894
1895 return HALMAC_RET_SUCCESS;
1896 }
1897
1898 static HALMAC_INLINE HALMAC_RET_STATUS
halmac_api_validate(PHALMAC_ADAPTER pHalmac_adapter)1899 halmac_api_validate(
1900 PHALMAC_ADAPTER pHalmac_adapter
1901 )
1902 {
1903 if (HALMAC_API_STATE_INIT != pHalmac_adapter->halmac_state.api_state)
1904 return HALMAC_RET_API_INVALID;
1905
1906 return HALMAC_RET_SUCCESS;
1907 }
1908
1909 static HALMAC_INLINE HALMAC_RET_STATUS
halmac_fw_validate(PHALMAC_ADAPTER pHalmac_adapter)1910 halmac_fw_validate(
1911 PHALMAC_ADAPTER pHalmac_adapter
1912 )
1913 {
1914 if (HALMAC_DLFW_DONE != pHalmac_adapter->halmac_state.dlfw_state && HALMAC_GEN_INFO_SENT != pHalmac_adapter->halmac_state.dlfw_state)
1915 return HALMAC_RET_NO_DLFW;
1916
1917 return HALMAC_RET_SUCCESS;
1918 }
1919
1920 #endif
1921