1Build Options 2============= 3 4The TF-A build system supports the following build options. Unless mentioned 5otherwise, these options are expected to be specified at the build command 6line and are not to be modified in any component makefiles. Note that the 7build system doesn't track dependency for build options. Therefore, if any of 8the build options are changed from a previous build, a clean build must be 9performed. 10 11.. _build_options_common: 12 13Common build options 14-------------------- 15 16- ``AARCH32_INSTRUCTION_SET``: Choose the AArch32 instruction set that the 17 compiler should use. Valid values are T32 and A32. It defaults to T32 due to 18 code having a smaller resulting size. 19 20- ``AARCH32_SP`` : Choose the AArch32 Secure Payload component to be built as 21 as the BL32 image when ``ARCH=aarch32``. The value should be the path to the 22 directory containing the SP source, relative to the ``bl32/``; the directory 23 is expected to contain a makefile called ``<aarch32_sp-value>.mk``. 24 25- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return 26 zero at all but the highest implemented exception level. External 27 memory-mapped debug accesses are unaffected by this control. 28 The default value is 1 for all platforms. 29 30- ``ARCH`` : Choose the target build architecture for TF-A. It can take either 31 ``aarch64`` or ``aarch32`` as values. By default, it is defined to 32 ``aarch64``. 33 34- ``ARM_ARCH_FEATURE``: Optional Arm Architecture build option which specifies 35 one or more feature modifiers. This option has the form ``[no]feature+...`` 36 and defaults to ``none``. It translates into compiler option 37 ``-march=armvX[.Y]-a+[no]feature+...``. See compiler's documentation for the 38 list of supported feature modifiers. 39 40- ``ARM_ARCH_MAJOR``: The major version of Arm Architecture to target when 41 compiling TF-A. Its value must be numeric, and defaults to 8 . See also, 42 *Armv8 Architecture Extensions* and *Armv7 Architecture Extensions* in 43 :ref:`Firmware Design`. 44 45- ``ARM_ARCH_MINOR``: The minor version of Arm Architecture to target when 46 compiling TF-A. Its value must be a numeric, and defaults to 0. See also, 47 *Armv8 Architecture Extensions* in :ref:`Firmware Design`. 48 49- ``ARM_BL2_SP_LIST_DTS``: Path to DTS file snippet to override the hardcoded 50 SP nodes in tb_fw_config. 51 52- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the 53 SPMC Core manifest. Valid when ``SPD=spmd`` is selected. 54 55- ``BL2``: This is an optional build option which specifies the path to BL2 56 image for the ``fip`` target. In this case, the BL2 in the TF-A will not be 57 built. 58 59- ``BL2U``: This is an optional build option which specifies the path to 60 BL2U image. In this case, the BL2U in TF-A will not be built. 61 62- ``RESET_TO_BL2``: Boolean option to enable BL2 entrypoint as the CPU reset 63 vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 64 entrypoint) or 1 (CPU reset to BL2 entrypoint). 65 The default value is 0. 66 67- ``BL2_RUNS_AT_EL3``: This is an implicit flag to denote that BL2 runs at EL3. 68 While it is explicitly set to 1 when RESET_TO_BL2 is set to 1 it can also be 69 true in a 4-world system where RESET_TO_BL2 is 0. 70 71- ``BL2_INV_DCACHE``: This is an optional build option which control dcache 72 invalidation upon BL2 entry. Some platform cannot handle cache operations 73 during entry as the coherency unit is not yet initialized. This may cause 74 crashing. Leaving this option to '1' (default) will allow the operation. 75 This option is only relevant when BL2 is set to run at EL3. 76 77- ``BL2_ENABLE_SP_LOAD``: Boolean option to enable loading SP packages from the 78 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided. 79 80- ``BL2_IN_XIP_MEM``: In some use-cases BL2 will be stored in eXecute In Place 81 (XIP) memory, like BL1. In these use-cases, it is necessary to initialize 82 the RW sections in RAM, while leaving the RO sections in place. This option 83 enable this use-case. For now, this option is only supported 84 when RESET_TO_BL2 is set to '1'. 85 86- ``BL31``: This is an optional build option which specifies the path to 87 BL31 image for the ``fip`` target. In this case, the BL31 in TF-A will not 88 be built. 89 90- ``BL31_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 91 file that contains the BL31 private key in PEM format or a PKCS11 URI. If 92 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 93 94- ``BL32``: This is an optional build option which specifies the path to 95 BL32 image for the ``fip`` target. In this case, the BL32 in TF-A will not 96 be built. 97 98- ``BL32_EXTRA1``: This is an optional build option which specifies the path to 99 Trusted OS Extra1 image for the ``fip`` target. 100 101- ``BL32_EXTRA2``: This is an optional build option which specifies the path to 102 Trusted OS Extra2 image for the ``fip`` target. 103 104- ``BL32_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 105 file that contains the BL32 private key in PEM format or a PKCS11 URI. If 106 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 107 108- ``RMM``: This is an optional build option used when ``ENABLE_RMM`` is set. 109 It specifies the path to RMM binary for the ``fip`` target. If the RMM option 110 is not specified, TF-A builds the TRP to load and run at R-EL2. 111 112- ``BL33``: Path to BL33 image in the host file system. This is mandatory for 113 ``fip`` target in case TF-A BL2 is used. 114 115- ``BL33_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 116 file that contains the BL33 private key in PEM format or a PKCS11 URI. If 117 ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 118 119- ``BRANCH_PROTECTION``: Numeric value to enable ARMv8.3 Pointer Authentication 120 and ARMv8.5 Branch Target Identification support for TF-A BL images themselves. 121 If enabled, it is needed to use a compiler that supports the option 122 ``-mbranch-protection``. The value of the ``-march`` (via ``ARM_ARCH_MINOR`` 123 and ``ARM_ARCH_MAJOR``) option will control which instructions will be 124 emitted (HINT space or not). Selects the branch protection features to use: 125- 0: Default value turns off all types of branch protection (FEAT_STATE_DISABLED) 126- 1: Enables all types of branch protection features 127- 2: Return address signing to its standard level 128- 3: Extend the signing to include leaf functions 129- 4: Turn on branch target identification mechanism 130- 5: Enables all types of branch protection features, only if present in 131 hardware (FEAT_STATE_CHECK). 132 133 The table below summarizes ``BRANCH_PROTECTION`` values, GCC compilation options 134 and resulting PAuth/BTI features. 135 136 +-------+--------------+-------+-----+ 137 | Value | GCC option | PAuth | BTI | 138 +=======+==============+=======+=====+ 139 | 0 | none | N | N | 140 +-------+--------------+-------+-----+ 141 | 1 | standard | Y | Y | 142 +-------+--------------+-------+-----+ 143 | 2 | pac-ret | Y | N | 144 +-------+--------------+-------+-----+ 145 | 3 | pac-ret+leaf | Y | N | 146 +-------+--------------+-------+-----+ 147 | 4 | bti | N | Y | 148 +-------+--------------+-------+-----+ 149 | 5 | dynamic | Y | Y | 150 +-------+--------------+-------+-----+ 151 152 This option defaults to 0. 153 Note that Pointer Authentication is enabled for Non-secure world 154 irrespective of the value of this option if the CPU supports it. 155 156- ``BUILD_MESSAGE_TIMESTAMP``: String used to identify the time and date of the 157 compilation of each build. It must be set to a C string (including quotes 158 where applicable). Defaults to a string that contains the time and date of 159 the compilation. 160 161- ``BUILD_STRING``: Input string for VERSION_STRING, which allows the TF-A 162 build to be uniquely identified. Defaults to the current git commit id. 163 164- ``BUILD_BASE``: Output directory for the build. Defaults to ``./build`` 165 166- ``CFLAGS``: Extra user options appended on the compiler's command line in 167 addition to the options set by the build system. 168 169- ``COLD_BOOT_SINGLE_CPU``: This option indicates whether the platform may 170 release several CPUs out of reset. It can take either 0 (several CPUs may be 171 brought up) or 1 (only one CPU will ever be brought up during cold reset). 172 Default is 0. If the platform always brings up a single CPU, there is no 173 need to distinguish between primary and secondary CPUs and the boot path can 174 be optimised. The ``plat_is_my_cpu_primary()`` and 175 ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need 176 to be implemented in this case. 177 178- ``COT``: When Trusted Boot is enabled, selects the desired chain of trust. 179 Defaults to ``tbbr``. 180 181- ``CRASH_REPORTING``: A non-zero value enables a console dump of processor 182 register state when an unexpected exception occurs during execution of 183 BL31. This option defaults to the value of ``DEBUG`` - i.e. by default 184 this is only enabled for a debug build of the firmware. 185 186- ``CREATE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 187 certificate generation tool to create new keys in case no valid keys are 188 present or specified. Allowed options are '0' or '1'. Default is '1'. 189 190- ``CTX_INCLUDE_AARCH32_REGS`` : Boolean option that, when set to 1, will cause 191 the AArch32 system registers to be included when saving and restoring the 192 CPU context. The option must be set to 0 for AArch64-only platforms (that 193 is on hardware that does not implement AArch32, or at least not at EL1 and 194 higher ELs). Default value is 1. 195 196- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP 197 registers to be included when saving and restoring the CPU context. Default 198 is 0. 199 200- ``CTX_INCLUDE_MPAM_REGS``: Boolean option that, when set to 1, will cause the 201 Memory System Resource Partitioning and Monitoring (MPAM) 202 registers to be included when saving and restoring the CPU context. 203 Default is '0'. 204 205- ``CTX_INCLUDE_NEVE_REGS``: Numeric value, when set will cause the Armv8.4-NV 206 registers to be saved/restored when entering/exiting an EL2 execution 207 context. This flag can take values 0 to 2, to align with the 208 ``ENABLE_FEAT`` mechanism. Default value is 0. 209 210- ``CTX_INCLUDE_PAUTH_REGS``: Numeric value to enable the Pointer 211 Authentication for Secure world. This will cause the ARMv8.3-PAuth registers 212 to be included when saving and restoring the CPU context as part of world 213 switch. Automatically enabled when ``BRANCH_PROTECTION`` is enabled. This flag 214 can take values 0 to 2, to align with ``ENABLE_FEAT`` mechanism. Default value 215 is 0. 216 217 Note that Pointer Authentication is enabled for Non-secure world irrespective 218 of the value of this flag if the CPU supports it. Alternatively, when 219 ``BRANCH_PROTECTION`` is enabled, this flag is superseded. 220 221- ``CTX_INCLUDE_SVE_REGS``: Boolean option that, when set to 1, will cause the 222 SVE registers to be included when saving and restoring the CPU context. Note 223 that this build option requires ``ENABLE_SVE_FOR_SWD`` to be enabled. In 224 general, it is recommended to perform SVE context management in lower ELs 225 and skip in EL3 due to the additional cost of maintaining large data 226 structures to track the SVE state. Hence, the default value is 0. 227 228- ``DEBUG``: Chooses between a debug and release build. It can take either 0 229 (release) or 1 (debug) as values. 0 is the default. 230 231- ``DECRYPTION_SUPPORT``: This build flag enables the user to select the 232 authenticated decryption algorithm to be used to decrypt firmware/s during 233 boot. It accepts 2 values: ``aes_gcm`` and ``none``. The default value of 234 this flag is ``none`` to disable firmware decryption which is an optional 235 feature as per TBBR. 236 237- ``DISABLE_BIN_GENERATION``: Boolean option to disable the generation 238 of the binary image. If set to 1, then only the ELF image is built. 239 0 is the default. 240 241- ``DISABLE_MTPMU``: Numeric option to disable ``FEAT_MTPMU`` (Multi Threaded 242 PMU). ``FEAT_MTPMU`` is an optional feature available on Armv8.6 onwards. 243 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 244 mechanism. Default is ``0``. 245 246- ``DYN_DISABLE_AUTH``: Provides the capability to dynamically disable Trusted 247 Board Boot authentication at runtime. This option is meant to be enabled only 248 for development platforms. ``TRUSTED_BOARD_BOOT`` flag must be set if this 249 flag has to be enabled. 0 is the default. 250 251- ``E``: Boolean option to make warnings into errors. Default is 1. 252 253 When specifying higher warnings levels (``W=1`` and higher), this option 254 defaults to 0. This is done to encourage contributors to use them, as they 255 are expected to produce warnings that would otherwise fail the build. New 256 contributions are still expected to build with ``W=0`` and ``E=1`` (the 257 default). 258 259- ``EARLY_CONSOLE``: This option is used to enable early traces before default 260 console is properly setup. It introduces EARLY_* traces macros, that will 261 use the non-EARLY traces macros if the flag is enabled, or do nothing 262 otherwise. To use this feature, platforms will have to create the function 263 plat_setup_early_console(). 264 Default is 0 (disabled) 265 266- ``EL3_PAYLOAD_BASE``: This option enables booting an EL3 payload instead of 267 the normal boot flow. It must specify the entry point address of the EL3 268 payload. Please refer to the "Booting an EL3 payload" section for more 269 details. 270 271- ``ENABLE_AMU_AUXILIARY_COUNTERS``: Enables support for AMU auxiliary counters 272 (also known as group 1 counters). These are implementation-defined counters, 273 and as such require additional platform configuration. Default is 0. 274 275- ``ENABLE_ASSERTIONS``: This option controls whether or not calls to ``assert()`` 276 are compiled out. For debug builds, this option defaults to 1, and calls to 277 ``assert()`` are left in place. For release builds, this option defaults to 0 278 and calls to ``assert()`` function are compiled out. This option can be set 279 independently of ``DEBUG``. It can also be used to hide any auxiliary code 280 that is only required for the assertion and does not fit in the assertion 281 itself. 282 283- ``ENABLE_BACKTRACE``: This option controls whether to enable backtrace 284 dumps or not. It is supported in both AArch64 and AArch32. However, in 285 AArch32 the format of the frame records are not defined in the AAPCS and they 286 are defined by the implementation. This implementation of backtrace only 287 supports the format used by GCC when T32 interworking is disabled. For this 288 reason enabling this option in AArch32 will force the compiler to only 289 generate A32 code. This option is enabled by default only in AArch64 debug 290 builds, but this behaviour can be overridden in each platform's Makefile or 291 in the build command line. 292 293- ``ENABLE_FEAT_AMU``: Numeric value to enable Activity Monitor Unit 294 extensions. This flag can take the values 0 to 2, to align with the 295 ``ENABLE_FEAT`` mechanism. This is an optional architectural feature 296 available on v8.4 onwards. Some v8.2 implementations also implement an AMU 297 and this option can be used to enable this feature on those systems as well. 298 This flag can take the values 0 to 2, the default is 0. 299 300- ``ENABLE_FEAT_AMUv1p1``: Numeric value to enable the ``FEAT_AMUv1p1`` 301 extension. ``FEAT_AMUv1p1`` is an optional feature available on Arm v8.6 302 onwards. This flag can take the values 0 to 2, to align with the 303 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 304 305- ``ENABLE_FEAT_CLRBHB``: Numeric value to enable the CLRBHB instruction. 306 Clear Branch History clears the branch history for the current context to 307 the extent that branch history information created before the CLRBHB instruction 308 cannot be used by code. This is an optional architectural feature available on v8.0 309 onwards and is a mandatory feature from v8.9 onwards. 310 This flag can take the values of 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 311 Default value is ``0``. 312 313- ``ENABLE_FEAT_CPA2``: Numeric value to enable the ``FEAT_CPA2`` extension. 314 It enables checked pointer arithmetic in EL3, which will result in address 315 faults in the event that a pointer arithmetic overflow error occurs. This is 316 an optional feature starting from Arm v9.4 and This flag can take values 0 to 317 2, to align with the ``ENABLE_FEAT`` mechanism. Default value is ``0``. 318 319- ``ENABLE_FEAT_CSV2_2``: Numeric value to enable the ``FEAT_CSV2_2`` 320 extension. It allows access to the SCXTNUM_EL2 (Software Context Number) 321 register during EL2 context save/restore operations. ``FEAT_CSV2_2`` is an 322 optional feature available on Arm v8.0 onwards. This flag can take values 323 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 324 Default value is ``0``. 325 326- ``ENABLE_FEAT_CSV2_3``: Numeric value to enable support for ``FEAT_CSV2_3`` 327 extension. This feature is supported in AArch64 state only and is an optional 328 feature available in Arm v8.0 implementations. 329 ``FEAT_CSV2_3`` implies the implementation of ``FEAT_CSV2_2``. 330 The flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 331 mechanism. Default value is ``0``. 332 333- ``ENABLE_FEAT_CRYPTO``: Numeric value to enable the ``FEAT_CRYPTO`` 334 extension. It allows using the SIMD crypto extension AES, SHA1 and SHA2 335 instructions for mbedtls HASH256, which speeds up the authentication process 336 of the subsequent images in BL1 and BL2. ``FEAT_CRYPTO`` is an optional 337 feature available on Arm v8 onwards. This flag can take values 338 0 to 2, to align with the ``ENABLE_FEAT`` mechanism, however, value ``2`` 339 is treated as ``0`` since there is no way to perform runtime check. 340 Default value is ``0``. 341 342- ``ENABLE_FEAT_CRYPTO_SHA3``: Numeric value to enable the ``FEAT_CRYPTO`` 343 extension. It allows using the SIMD crypto extension SHA3 instructions for 344 mbedtls HASH384 and HASH512, which speeds up the authentication process of 345 the subsequent images in BL1 and BL2. ``FEAT_CRYPTO_SHA3`` is an optional 346 feature available on Arm v8.2 onwards. This flag can take values 347 0 to 1, to align with the ``ENABLE_FEAT`` mechanism, however, value ``2`` 348 is treated as ``0`` since there is no way to perform runtime check. 349 Default value is ``0``. 350 351- ``ENABLE_FEAT_DEBUGV8P9``: Numeric value to enable ``FEAT_DEBUGV8P9`` 352 extension which allows the ability to implement more than 16 breakpoints 353 and/or watchpoints. This feature is mandatory from v8.9 and is optional 354 from v8.8. This flag can take the values of 0 to 2, to align with the 355 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 356 357- ``ENABLE_FEAT_DIT``: Numeric value to enable ``FEAT_DIT`` (Data Independent 358 Timing) extension. It allows setting the ``DIT`` bit of PSTATE in EL3. 359 ``FEAT_DIT`` is a mandatory architectural feature and is enabled from v8.4 360 and upwards. This flag can take the values 0 to 2, to align with the 361 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 362 363- ``ENABLE_FEAT_ECV``: Numeric value to enable support for the Enhanced Counter 364 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer 365 Physical Offset register) during EL2 to EL3 context save/restore operations. 366 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 367 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 368 mechanism. Default value is ``0``. 369 370- ``ENABLE_FEAT_FPMR``: Numerical value to enable support for Floating Point 371 Mode Register feature, allowing access to the FPMR register. FPMR register 372 controls the behaviors of FP8 instructions. It is an optional architectural 373 feature from v9.2 and upwards. This flag can take value of 0 to 2, to align 374 with the ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 375 376- ``ENABLE_FEAT_FGT``: Numeric value to enable support for FGT (Fine Grain Traps) 377 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained 378 Read Trap Register) during EL2 to EL3 context save/restore operations. 379 Its a mandatory architectural feature and is enabled from v8.6 and upwards. 380 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 381 mechanism. Default value is ``0``. 382 383- ``ENABLE_FEAT_FGT2``: Numeric value to enable support for FGT2 384 (Fine Grain Traps 2) feature allowing for access to Fine-grained trap 2 registers 385 during EL2 to EL3 context save/restore operations. 386 Its an optional architectural feature and is available from v8.8 and upwards. 387 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 388 mechanism. Default value is ``0``. 389 390- ``ENABLE_FEAT_FGWTE3``: Numeric value to enable support for 391 Fine Grained Write Trap EL3 (FEAT_FGWTE3), a feature that allows EL3 to 392 restrict overwriting certain EL3 registers after boot. 393 This lockdown is established by setting individual trap bits for 394 system registers that are not expected to be overwritten after boot. 395 This feature is an optional architectural feature and is available from 396 Armv9.4 onwards. This flag can take values from 0 to 2, aligning with 397 the ``ENABLE_FEAT`` mechanism. The default value is 0. 398 399 .. note:: 400 This feature currently traps access to all EL3 registers in 401 ``FGWTE3_EL3``, except for ``MDCR_EL3``, ``MPAM3_EL3``, 402 ``TPIDR_EL3``(when ``CRASH_REPORTING=1``), and 403 ``SCTLR_EL3``(when ``HW_ASSISTED_COHERENCY=0``). 404 If additional traps need to be disabled for specific platforms, 405 please contact the Arm team on `TF-A public mailing list`_. 406 407- ``ENABLE_FEAT_HDBSS``: Numeric value to enable support for HDBSS (Hardware 408 Dirty state tracking structure) by setting ``SCR_EL3.HDBSSEn`` for NS world. 409 This is an optional architectural feature and is available from v9.4 and 410 upwards. This flag can take the values 0 to 2, to align with the 411 ``ENABLE_FEAT`` mechanism. Default value is ``0``. 412 413- ``ENABLE_FEAT_HACDBS``: Numeric value to enable support for 414 HACDBS (Hardware accelerator for cleaning Dirty state) by setting 415 ``SCR_EL3.HACDBSEn`` for NS world. This is an optional architectural feature 416 and is available from v9.4 and upwards. This flag can take the values 0 to 2, 417 to align with the ``ENABLE_FEAT`` mechanism. Default value is ``0``. 418 419- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to 420 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as 421 well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a 422 mandatory architectural feature and is enabled from v8.7 and upwards. This 423 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 424 mechanism. Default value is ``0``. 425 426- ``ENABLE_FEAT_IDTE3``: Numeric value to set SCR_EL3.TID3/TID5 bits which 427 enables trapping of ID register reads by lower ELs to EL3. This allows EL3 428 to control the feature visibility to lower ELs by returning a sanitized value 429 based on current feature enablement status. Hypervisors are expected to 430 cache ID register during their boot stage. This flag can take the 431 values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 432 Default value is ``0``. This feature is EXPERIMENTAL. 433 434 .. note:: 435 This feature traps all lower EL accesses to Group 3 and Group 5 436 ID registers to EL3. This can incur a performance impact and platforms 437 should enable them only if they have a specific need. 438 439- ``ENABLE_FEAT_MOPS``: Numeric value to enable FEAT_MOPS (Standardization 440 of memory operations) when INIT_UNUSED_NS_EL2=1. 441 This feature is mandatory from v8.8 and enabling of FEAT_MOPS does not 442 require any settings from EL3 as the controls are present in EL2 registers 443 (HCRX_EL2.{MSCEn,MCE2} and SCTLR_EL2.MSCEn) and in most configurations 444 we expect EL2 to be present. But in case of INIT_UNUSED_NS_EL2=1 , 445 EL3 should configure the EL2 registers. This flag 446 can take values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 447 Default value is ``0``. 448 449- ``ENABLE_FEAT_MTE2``: Numeric value to enable Memory Tagging Extension2 450 if the platform wants to use this feature and MTE2 is enabled at ELX. 451 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 452 mechanism. Default value is ``0``. 453 454- ``ENABLE_FEAT_PAN``: Numeric value to enable the ``FEAT_PAN`` (Privileged 455 Access Never) extension. ``FEAT_PAN`` adds a bit to PSTATE, generating a 456 permission fault for any privileged data access from EL1/EL2 to virtual 457 memory address, accessible at EL0, provided (HCR_EL2.E2H=1). It is a 458 mandatory architectural feature and is enabled from v8.1 and upwards. This 459 flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 460 mechanism. Default value is ``0``. 461 462- ``ENABLE_FEAT_PAUTH_LR``: Numeric value to enable the ``FEAT_PAUTH_LR`` 463 extension. ``FEAT_PAUTH_LR`` is an optional feature available from Arm v9.4 464 onwards. This feature requires PAUTH to be enabled via the 465 ``BRANCH_PROTECTION`` flag. This flag can take the values 0 to 2, to align 466 with the ``ENABLE_FEAT`` mechanism. Default value is ``0``. 467 468- ``ENABLE_FEAT_RNG``: Numeric value to enable the ``FEAT_RNG`` extension. 469 ``FEAT_RNG`` is an optional feature available on Arm v8.5 onwards. This 470 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 471 mechanism. Default value is ``0``. 472 473- ``ENABLE_FEAT_RNG_TRAP``: Numeric value to enable the ``FEAT_RNG_TRAP`` 474 extension. This feature is only supported in AArch64 state. This flag can 475 take values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 476 Default value is ``0``. ``FEAT_RNG_TRAP`` is an optional feature from 477 Armv8.5 onwards. 478 479- ``ENABLE_FEAT_SB``: Numeric option to let the TF-A code use the ``FEAT_SB`` 480 (Speculation Barrier) instruction ``FEAT_SB`` is an optional feature and 481 defaults to ``0`` for pre-Armv8.5 CPUs, but is mandatory for Armv8.5 or 482 later CPUs. It is enabled from v8.5 and upwards and if needed can be 483 overidden from platforms explicitly. This flag can take values 0 to 2, to 484 align with the ``ENABLE_FEAT`` mechanism. Default value is ``0``. 485 486- ``ENABLE_FEAT_SEL2``: Numeric value to enable the ``FEAT_SEL2`` (Secure EL2) 487 extension. ``FEAT_SEL2`` is a mandatory feature available on Arm v8.4. 488 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 489 mechanism. Default is ``0``. 490 491- ``ENABLE_FEAT_TWED``: Numeric value to enable the ``FEAT_TWED`` (Delayed 492 trapping of WFE Instruction) extension. ``FEAT_TWED`` is a optional feature 493 available on Arm v8.6. This flag can take values 0 to 2, to align with the 494 ``ENABLE_FEAT`` mechanism. Default is ``0``. 495 496 When ``ENABLE_FEAT_TWED`` is set to ``1``, WFE instruction trapping gets 497 delayed by the amount of value in ``TWED_DELAY``. 498 499- ``ENABLE_FEAT_VHE``: Numeric value to enable the ``FEAT_VHE`` (Virtualization 500 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register 501 during EL2 context save/restore operations.``FEAT_VHE`` is a mandatory 502 architectural feature and is enabled from v8.1 and upwards. It can take 503 values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 504 Default value is ``0``. 505 506- ``ENABLE_FEAT_TCR2``: Numeric value to set the bit SCR_EL3.ENTCR2 in EL3 to 507 allow access to TCR2_EL2 (extended translation control) from EL2 as 508 well as adding TCR2_EL2 to the EL2 context save/restore operations. Its a 509 mandatory architectural feature and is enabled from v8.9 and upwards. This 510 flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 511 mechanism. Default value is ``0``. 512 513- ``ENABLE_FEAT_S2PIE``: Numeric value to enable support for FEAT_S2PIE 514 at EL2 and below, and context switch relevant registers. This flag 515 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 516 mechanism. Default value is ``0``. 517 518- ``ENABLE_FEAT_S1PIE``: Numeric value to enable support for FEAT_S1PIE 519 at EL2 and below, and context switch relevant registers. This flag 520 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 521 mechanism. Default value is ``0``. 522 523- ``ENABLE_FEAT_S2POE``: Numeric value to enable support for FEAT_S2POE 524 at EL2 and below, and context switch relevant registers. This flag 525 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 526 mechanism. Default value is ``0``. 527 528- ``ENABLE_FEAT_S1POE``: Numeric value to enable support for FEAT_S1POE 529 at EL2 and below, and context switch relevant registers. This flag 530 can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 531 mechanism. Default value is ``0``. 532 533- ``ENABLE_FEAT_GCS``: Numeric value to set the bit SCR_EL3.GCSEn in EL3 to 534 allow use of Guarded Control Stack from EL2 as well as adding the GCS 535 registers to the EL2 context save/restore operations. This flag can take 536 the values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 537 Default value is ``0``. 538 539 - ``ENABLE_FEAT_GCIE``: Boolean value to enable support for the GICv5 CPU 540 interface (see ``USE_GIC_DRIVER`` for the IRI). GICv5 and GICv3 are mutually 541 exclusive, so the ``ENABLE_FEAT`` mechanism is currently not supported. 542 Default value is ``0``. 543 544- ``ENABLE_FEAT_THE``: Numeric value to enable support for FEAT_THE 545 (Translation Hardening Extension) at EL2 and below, setting the bit 546 SCR_EL3.RCWMASKEn in EL3 to allow access to RCWMASK_EL1 and RCWSMASK_EL1 547 registers and context switch them. 548 Its an optional architectural feature and is available from v8.8 and upwards. 549 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 550 mechanism. Default value is ``0``. 551 552- ``ENABLE_FEAT_SCTLR2``: Numeric value to enable support for FEAT_SCTLR2 553 (Extension to SCTLR_ELx) at EL2 and below, setting the bit 554 SCR_EL3.SCTLR2En in EL3 to allow access to SCTLR2_ELx registers and 555 context switch them. This feature is OPTIONAL from Armv8.0 implementations 556 and mandatory in Armv8.9 implementations. 557 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 558 mechanism. Default value is ``0``. 559 560- ``ENABLE_FEAT_STEP2``: Numeric value that enables support for FEAT_STEP2 by 561 setting ``MDCR_EL3.EnSTEPOP`` so that lower ELs can access ``MDSTEPOP_EL1``. 562 This feature is optional from Armv9.4 implementations and is mandatory in 563 Armv9.5 implementations. This flag can take the values 0 to 2, to align with 564 the ``ENABLE_FEAT`` mechanism Defaults value is ``0``. 565 566- ``ENABLE_FEAT_D128``: Numeric value to enable support for FEAT_D128 567 at EL2 and below, setting the bit SCT_EL3.D128En in EL3 to allow access to 568 128 bit version of system registers like PAR_EL1, TTBR0_EL1, TTBR1_EL1, 569 TTBR0_EL2, TTBR1_EL2, TTBR0_EL12, TTBR1_EL12 , VTTBR_EL2, RCWMASK_EL1, and 570 RCWSMASK_EL1. Its an optional architectural feature and is available from 571 9.3 and upwards. 572 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 573 mechanism. Default value is ``0``. 574 575- ``ENABLE_FEAT_UINJ``: Numerical value to enable FEAT_UINJ support which 576 is hardware based injection of undefined instruction exceptions. 577 The objective of this feature is to provide higher privilege software with a 578 future proofed mechanism to inject an Undefined Instruction exception into 579 lower privilege software. It is an optional architectural feature from v9.0 580 and mandatory from v9.6. This flag can take value of 0 to 2, 581 to align with the ``FEATURE_DETECTION`` mechanism. Default value is ``0``. 582 583- ``ENABLE_LTO``: Boolean option to enable Link Time Optimization (LTO) 584 support. This option is currently only supported for AArch64. On GCC it only 585 applies to TF-A proper, and not its libraries. If LTO on libraries (except 586 the libc) is desired a platform can pass `-flto -ffat-lto-objects` as long as 587 GCC >= 14 is in use. ``ENABLE_LTO`` is enabled by default on release builds. 588 Default is 0. 589 590- ``ENABLE_FEAT_MPAM``: Numeric value to enable lower ELs to use MPAM 591 feature. MPAM is an optional Armv8.4 extension that enables various memory 592 system components and resources to define partitions; software running at 593 various ELs can assign themselves to desired partition to control their 594 performance aspects. 595 596 This flag can take values 0 to 2, to align with the ``ENABLE_FEAT`` 597 mechanism. When this option is set to ``1`` or ``2``, EL3 allows lower ELs to 598 access their own MPAM registers without trapping into EL3. This option 599 doesn't make use of partitioning in EL3, however. Platform initialisation 600 code should configure and use partitions in EL3 as required. This option 601 defaults to ``2`` since MPAM is enabled by default for NS world only. 602 The flag is automatically disabled when the target 603 architecture is AArch32. 604 605- ``ENABLE_FEAT_MPAM_PE_BW_CTRL``: This option enables Armv9.3 MPAM 606 PE-side bandwidth controls and disables traps to EL3/EL2 (when 607 ``INIT_UNUSED_NS_EL2`` = 1). The flag accepts values from 0 to 2, in 608 line with the ``ENABLE_FEAT`` mechanism, and defaults to ``0``. 609 610- ``ENABLE_FEAT_LS64_ACCDATA``: Numeric value to enable access and save and 611 restore the ACCDATA_EL1 system register, at EL2 and below. This flag can 612 take the values 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. 613 Default value is ``0``. 614 615- ``ENABLE_FEAT_AIE``: Numeric value to enable access to the (A)MAIR2 system 616 registers from non-secure world. This flag can take the values 0 to 2, to 617 align with the ``ENABLE_FEAT`` mechanism. 618 Default value is ``0``. 619 620- ``ENABLE_FEAT_PFAR``: Numeric value to enable access to the PFAR system 621 registers from non-secure world. This flag can take the values 0 to 2, to 622 align with the ``ENABLE_FEAT`` mechanism. 623 Default value is ``0``. 624 625- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power 626 Mitigation Mechanism supported by certain Arm cores, which allows the SoC 627 firmware to detect and limit high activity events to assist in SoC processor 628 power domain dynamic power budgeting and limit the triggering of whole-rail 629 (i.e. clock chopping) responses to overcurrent conditions. Defaults to ``0``. 630 631- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE) 632 support within generic code in TF-A. This option is currently only supported 633 in BL2, BL31, and BL32 (TSP) for AARCH64 binaries, and 634 in BL32 (SP_min) for AARCH32. Default is 0. 635 636- ``ENABLE_PMF``: Boolean option to enable support for optional Performance 637 Measurement Framework(PMF). Default is 0. 638 639- ``ENABLE_PSCI_STAT``: Boolean option to enable support for optional PSCI 640 functions ``PSCI_STAT_RESIDENCY`` and ``PSCI_STAT_COUNT``. Default is 0. 641 In the absence of an alternate stat collection backend, ``ENABLE_PMF`` must 642 be enabled. If ``ENABLE_PMF`` is set, the residency statistics are tracked in 643 software. 644 645- ``ENABLE_RUNTIME_INSTRUMENTATION``: Boolean option to enable runtime 646 instrumentation which injects timestamp collection points into TF-A to 647 allow runtime performance to be measured. Currently, only PSCI is 648 instrumented. Enabling this option enables the ``ENABLE_PMF`` build option 649 as well. Default is 0. 650 651- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling 652 extensions. This is an optional architectural feature for AArch64. 653 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 654 mechanism. The default is 2 but is automatically disabled when the target 655 architecture is AArch32. 656 657- ``ENABLE_SVE_FOR_NS``: Numeric value to enable Scalable Vector Extension 658 (SVE) for the Non-secure world only. SVE is an optional architectural feature 659 for AArch64. This flag can take the values 0 to 2, to align with the 660 ``ENABLE_FEAT`` mechanism. At this time, this build option cannot be used on 661 systems that have SPM_MM enabled. The default value is 2. 662 663 Note that when SVE is enabled for the Non-secure world, access 664 to SVE, SIMD and floating-point functionality from the Secure world is 665 independently controlled by build option ``ENABLE_SVE_FOR_SWD``. When enabling 666 ``CTX_INCLUDE_FPREGS`` and ``ENABLE_SVE_FOR_NS`` together, it is mandatory to 667 enable ``CTX_INCLUDE_SVE_REGS``. This is to avoid corruption of the Non-secure 668 world data in the Z-registers which are aliased by the SIMD and FP registers. 669 670- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE and FPU/SIMD functionality 671 for the Secure world. SVE is an optional architectural feature for AArch64. 672 The default is 0 and it is automatically disabled when the target architecture 673 is AArch32. 674 675 .. note:: 676 This build flag requires ``ENABLE_SVE_FOR_NS`` to be enabled. When enabling 677 ``ENABLE_SVE_FOR_SWD``, a developer must carefully consider whether 678 ``CTX_INCLUDE_SVE_REGS`` is also needed. 679 680- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection 681 checks in GCC. Allowed values are "all", "strong", "default" and "none". The 682 default value is set to "none". "strong" is the recommended stack protection 683 level if this feature is desired. "none" disables the stack protection. For 684 all values other than "none", the ``plat_get_stack_protector_canary()`` 685 platform hook needs to be implemented. The value is passed as the last 686 component of the option ``-fstack-protector-$ENABLE_STACK_PROTECTOR``. 687 688- ``ENABLE_ERRATA_ALL``: This option is used only for testing purposes, Boolean 689 option to enable the workarounds for all errata that TF-A implements. Normally 690 they should be explicitly enabled depending on each platform's needs. Not 691 recommended for release builds. This option is default set to 0. 692 693- ``ENABLE_FEAT_MORELLO`` : Numeric option to enable the Morello capability aware 694 firmware. This flag can take the values 0 to 2, to align with the 695 ``ENABLE_FEAT`` mechanism. This option is experimental and supported only with 696 LLVM CLANG toolchain and not with GCC toolchain. Capability awareness is 697 currently enabled only in BL31 firmware and not in other firmware types of 698 trusted firmware. Enabling this on regular AARCH64 system might not work. 699 700- ``ENCRYPT_BL31``: Binary flag to enable encryption of BL31 firmware. This 701 flag depends on ``DECRYPTION_SUPPORT`` build flag. 702 703- ``ENCRYPT_BL32``: Binary flag to enable encryption of Secure BL32 payload. 704 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 705 706- ``ENC_KEY``: A 32-byte (256-bit) symmetric key in hex string format. It could 707 either be SSK or BSSK depending on ``FW_ENC_STATUS`` flag. This value depends 708 on ``DECRYPTION_SUPPORT`` build flag. 709 710- ``ENC_NONCE``: A 12-byte (96-bit) encryption nonce or Initialization Vector 711 (IV) in hex string format. This value depends on ``DECRYPTION_SUPPORT`` 712 build flag. 713 714- ``ERROR_DEPRECATED``: This option decides whether to treat the usage of 715 deprecated platform APIs, helper functions or drivers within Trusted 716 Firmware as error. It can take the value 1 (flag the use of deprecated 717 APIs as error) or 0. The default is 0. 718 719- ``ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can 720 configure an Arm® Ethos™-N NPU. To use this service the target platform's 721 ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only 722 the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform 723 only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0. 724 725- ``ETHOSN_NPU_TZMP1``: boolean option to enable TZMP1 support for the 726 Arm® Ethos™-N NPU. Requires ``ETHOSN_NPU_DRIVER`` and 727 ``TRUSTED_BOARD_BOOT`` to be enabled. 728 729- ``ETHOSN_NPU_FW``: location of the NPU firmware binary 730 (```ethosn.bin```). This firmware image will be included in the FIP and 731 loaded at runtime. 732 733- ``EL3_EXCEPTION_HANDLING``: When set to ``1``, enable handling of exceptions 734 targeted at EL3. When set ``0`` (default), no exceptions are expected or 735 handled at EL3, and a panic will result. The exception to this rule is when 736 ``SPMD_SPM_AT_SEL2`` is set to ``1``, in which case, only exceptions 737 occuring during normal world execution, are trapped to EL3. Any exception 738 trapped during secure world execution are trapped to the SPMC. This is 739 supported only for AArch64 builds. 740 741- ``FAULT_INJECTION_SUPPORT``: ARMv8.4 extensions introduced support for fault 742 injection from lower ELs, and this build option enables lower ELs to use 743 Error Records accessed via System Registers to inject faults. This is 744 applicable only to AArch64 builds. 745 746 This feature is intended for testing purposes only, and is advisable to keep 747 disabled for production images. 748 749- ``FIP_NAME``: This is an optional build option which specifies the FIP 750 filename for the ``fip`` target. Default is ``fip.bin``. 751 752- ``FWU_FIP_NAME``: This is an optional build option which specifies the FWU 753 FIP filename for the ``fwu_fip`` target. Default is ``fwu_fip.bin``. 754 755- ``FW_ENC_STATUS``: Top level firmware's encryption numeric flag, values: 756 757 :: 758 759 0: Encryption is done with Secret Symmetric Key (SSK) which is common 760 for a class of devices. 761 1: Encryption is done with Binding Secret Symmetric Key (BSSK) which is 762 unique per device. 763 764 This flag depends on ``DECRYPTION_SUPPORT`` build flag. 765 766- ``GENERATE_COT``: Boolean flag used to build and execute the ``cert_create`` 767 tool to create certificates as per the Chain of Trust described in 768 :ref:`Trusted Board Boot`. The build system then calls ``fiptool`` to 769 include the certificates in the FIP and FWU_FIP. Default value is '0'. 770 771 Specify both ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=1`` to include support 772 for the Trusted Board Boot feature in the BL1 and BL2 images, to generate 773 the corresponding certificates, and to include those certificates in the 774 FIP and FWU_FIP. 775 776 Note that if ``TRUSTED_BOARD_BOOT=0`` and ``GENERATE_COT=1``, the BL1 and BL2 777 images will not include support for Trusted Board Boot. The FIP will still 778 include the corresponding certificates. This FIP can be used to verify the 779 Chain of Trust on the host machine through other mechanisms. 780 781 Note that if ``TRUSTED_BOARD_BOOT=1`` and ``GENERATE_COT=0``, the BL1 and BL2 782 images will include support for Trusted Board Boot, but the FIP and FWU_FIP 783 will not include the corresponding certificates, causing a boot failure. 784 785- ``GICV2_G0_FOR_EL3``: Unlike GICv3, the GICv2 architecture doesn't have 786 inherent support for specific EL3 type interrupts. Setting this build option 787 to ``1`` assumes GICv2 *Group 0* interrupts are expected to target EL3, both 788 by :ref:`platform abstraction layer<platform Interrupt Controller API>` and 789 :ref:`Interrupt Management Framework<Interrupt Management Framework>`. 790 This allows GICv2 platforms to enable features requiring EL3 interrupt type. 791 This also means that all GICv2 Group 0 interrupts are delivered to EL3, and 792 the Secure Payload interrupts needs to be synchronously handed over to Secure 793 EL1 for handling. The default value of this option is ``0``, which means the 794 Group 0 interrupts are assumed to be handled by Secure EL1. 795 796- ``HANDLE_EA_EL3_FIRST_NS``: When set to ``1``, External Aborts and SError 797 Interrupts, resulting from errors in NS world, will be always trapped in 798 EL3 i.e. in BL31 at runtime. When set to ``0`` (default), these exceptions 799 will be trapped in the current exception level (or in EL1 if the current 800 exception level is EL0). 801 802- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific 803 software operations are required for CPUs to enter and exit coherency. 804 However, newer systems exist where CPUs' entry to and exit from coherency 805 is managed in hardware. Such systems require software to only initiate these 806 operations, and the rest is managed in hardware, minimizing active software 807 management. In such systems, this boolean option enables TF-A to carry out 808 build and run-time optimizations during boot and power management operations. 809 This option defaults to 0 and if it is enabled, then it implies 810 ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled. 811 812 If this flag is disabled while the platform which TF-A is compiled for 813 includes cores that manage coherency in hardware, then a compilation error is 814 generated. This is based on the fact that a system cannot have, at the same 815 time, cores that manage coherency in hardware and cores that don't. In other 816 words, a platform cannot have, at the same time, cores that require 817 ``HW_ASSISTED_COHERENCY=1`` and cores that require 818 ``HW_ASSISTED_COHERENCY=0``. 819 820 Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of 821 translation library (xlat tables v2) must be used; version 1 of translation 822 library is not supported. 823 824- ``IMPDEF_SYSREG_TRAP``: Numeric value to enable the handling traps for 825 implementation defined system register accesses from lower ELs. Default 826 value is ``0``. 827 828- ``INVERTED_MEMMAP``: memmap tool print by default lower addresses at the 829 bottom, higher addresses at the top. This build flag can be set to '1' to 830 invert this behavior. Lower addresses will be printed at the top and higher 831 addresses at the bottom. 832 833- ``INIT_UNUSED_NS_EL2``: This build flag guards code that disables EL2 834 safely in scenario where NS-EL2 is present but unused. This flag is set to 0 835 by default. Platforms without NS-EL2 in use must enable this flag. 836 837- ``KEY_ALG``: This build flag enables the user to select the algorithm to be 838 used for generating the PKCS keys and subsequent signing of the certificate. 839 It accepts 5 values: ``rsa``, ``rsa_1_5``, ``ecdsa``, ``ecdsa-brainpool-regular`` 840 and ``ecdsa-brainpool-twisted``. The option ``rsa_1_5`` is the legacy PKCS#1 841 RSA 1.5 algorithm which is not TBBR compliant and is retained only for 842 compatibility. The default value of this flag is ``rsa`` which is the TBBR 843 compliant PKCS#1 RSA 2.1 scheme. 844 845- ``KEY_SIZE``: This build flag enables the user to select the key size for 846 the algorithm specified by ``KEY_ALG``. The valid values for ``KEY_SIZE`` 847 depend on the chosen algorithm and the cryptographic module. 848 849 +---------------------------+------------------------------------+ 850 | KEY_ALG | Possible key sizes | 851 +===========================+====================================+ 852 | rsa | 1024 , 2048 (default), 3072, 4096 | 853 +---------------------------+------------------------------------+ 854 | ecdsa | 256 (default), 384 | 855 +---------------------------+------------------------------------+ 856 | ecdsa-brainpool-regular | 256 (default) | 857 +---------------------------+------------------------------------+ 858 | ecdsa-brainpool-twisted | 256 (default) | 859 +---------------------------+------------------------------------+ 860 861- ``HASH_ALG``: This build flag enables the user to select the secure hash 862 algorithm. It accepts 3 values: ``sha256``, ``sha384`` and ``sha512``. 863 The default value of this flag is ``sha256``. 864 865- ``HW_CONFIG_BASE``: This option specifies the location in memory where the DTB 866 should either be loaded by BL2 or can be found by later stages. 867 868- ``LDFLAGS``: Extra user options appended to the linkers' command line in 869 addition to the one set by the build system. 870 871- ``LOG_LEVEL``: Chooses the log level, which controls the amount of console log 872 output compiled into the build. This should be one of the following: 873 874 :: 875 876 0 (LOG_LEVEL_NONE) 877 10 (LOG_LEVEL_ERROR) 878 20 (LOG_LEVEL_NOTICE) 879 30 (LOG_LEVEL_WARNING) 880 40 (LOG_LEVEL_INFO) 881 50 (LOG_LEVEL_VERBOSE) 882 883 All log output up to and including the selected log level is compiled into 884 the build. The default value is 40 in debug builds and 20 in release builds. 885 886 ``LOG_DEBUG``: Boolean option to enable support for module level internal 887 logs. There can be situation where a module has detail internal debugging 888 logs, these debugging logs may not be required to print even when log level 889 is VERBOSE. Such logs can be put under this flag. This is a file 890 level build flag. By default this should be disabled (``0``) in each file. 891 892- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot 893 feature. This flag can be enabled with ``TRUSTED_BOARD_BOOT`` in order to 894 provide trust that the code taking the measurements and recording them has 895 not been tampered with. 896 897 This option defaults to 0. 898 899- ``DISCRETE_TPM``: Boolean flag to include support for a Discrete TPM. 900 901 This option defaults to 0. 902 903- ``TPM_INTERFACE``: When ``DISCRETE_TPM=1``, this is a required flag to 904 select the TPM interface. Currently only one interface is supported: 905 906 :: 907 908 FIFO_SPI 909 910- ``MBOOT_TPM_HASH_ALG``: Build flag to select the TPM hash algorithm used during 911 Measured Boot. Currently only accepts ``sha256`` as a valid algorithm. 912 913- ``MARCH_DIRECTIVE``: used to pass a -march option from the platform build 914 options to the compiler. An example usage: 915 916 .. code:: make 917 918 MARCH_DIRECTIVE := -march=armv8.5-a 919 920- ``HARDEN_SLS``: used to pass -mharden-sls=all from the TF-A build 921 options to the compiler currently supporting only of the options. 922 GCC documentation: 923 https://gcc.gnu.org/onlinedocs/gcc/AArch64-Options.html#index-mharden-sls 924 925 An example usage: 926 927 .. code:: make 928 929 HARDEN_SLS := 1 930 931 This option defaults to 0. 932 933- ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 934 specifies a file that contains the Non-Trusted World private key in PEM 935 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and it 936 will be used to save the key. 937 938- ``NS_BL2U``: Path to NS_BL2U image in the host file system. This image is 939 optional. It is only needed if the platform makefile specifies that it 940 is required in order to build the ``fwu_fip`` target. 941 942- ``NS_TIMER_SWITCH``: (deprecated) Enable save and restore for non-secure 943 timer register contents upon world switch. It can take either 0 (don't save 944 and restore) or 1 (do save and restore). 0 is the default. An SPD may set 945 this to 1 if it wants the timer registers to be saved and restored. This 946 option has been deprecated since it breaks Linux preemption model. 947 948- ``OVERRIDE_LIBC``: This option allows platforms to override the default libc 949 for the BL image. It can be either 0 (include) or 1 (remove). The default 950 value is 0. 951 952- ``PL011_GENERIC_UART``: Boolean option to indicate the PL011 driver that 953 the underlying hardware is not a full PL011 UART but a minimally compliant 954 generic UART, which is a subset of the PL011. The driver will not access 955 any register that is not part of the SBSA generic UART specification. 956 Default value is 0 (a full PL011 compliant UART is present). 957 958- ``PLAT``: Choose a platform to build TF-A for. The chosen platform name 959 must be subdirectory of any depth under ``plat/``, and must contain a 960 platform makefile named ``platform.mk``. For example, to build TF-A for the 961 Arm Juno board, select PLAT=juno. 962 963- ``PLATFORM_REPORT_CTX_MEM_USE``: Reports the context memory allocated for 964 each core as well as the global context. The data includes the memory used 965 by each world and each privileged exception level. This build option is 966 applicable only for ``ARCH=aarch64`` builds. The default value is 0. 967 968- ``PLAT_EXTRA_LD_SCRIPT``: Allows the platform to include a custom LD script 969 snippet for any custom sections that cannot be expressed otherwise. Defaults 970 to 0. 971 972- ``PRELOADED_BL33_BASE``: This option enables booting a preloaded BL33 image 973 instead of the normal boot flow. When defined, it must specify the entry 974 point address for the preloaded BL33 image. This option is incompatible with 975 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority 976 over ``PRELOADED_BL33_BASE``. 977 978- ``PRESERVE_DSU_PMU_REGS``: This options when enabled allows the platform to 979 save/restore the DynamIQ Shared Unit's(DSU) Performance Monitoring Unit(PMU) 980 registers when the cluster goes through a power cycle. This is disabled by 981 default and platforms that require this feature have to enable them. 982 983- ``PROGRAMMABLE_RESET_ADDRESS``: This option indicates whether the reset 984 vector address can be programmed or is fixed on the platform. It can take 985 either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a 986 programmable reset address, it is expected that a CPU will start executing 987 code directly at the right address, both on a cold and warm reset. In this 988 case, there is no need to identify the entrypoint on boot and the boot path 989 can be optimised. The ``plat_get_my_entrypoint()`` platform porting interface 990 does not need to be implemented in this case. 991 992- ``PSCI_EXTENDED_STATE_ID``: As per PSCI1.0 Specification, there are 2 formats 993 possible for the PSCI power-state parameter: original and extended State-ID 994 formats. This flag if set to 1, configures the generic PSCI layer to use the 995 extended format. The default value of this flag is 0, which means by default 996 the original power-state format is used by the PSCI implementation. This flag 997 should be specified by the platform makefile and it governs the return value 998 of PSCI_FEATURES API for CPU_SUSPEND smc function id. When this option is 999 enabled on Arm platforms, the option ``ARM_RECOM_STATE_ID_ENC`` needs to be 1000 set to 1 as well. 1001 1002- ``PSCI_OS_INIT_MODE``: Boolean flag to enable support for optional PSCI 1003 OS-initiated mode. This option defaults to 0. 1004 1005- ``ARCH_FEATURE_AVAILABILITY``: Boolean flag to enable support for the 1006 optional SMCCC_ARCH_FEATURE_AVAILABILITY call. This option implicitly 1007 interacts with IMPDEF_SYSREG_TRAP and software emulation. This option 1008 defaults to 0. 1009 1010- ``ENABLE_FEAT_RAS``: Numeric flag to enable Armv8.2 RAS features. RAS 1011 features are an optional extension for pre-Armv8.2 CPUs, but are mandatory 1012 for Armv8.2 or later CPUs. NOTE: This flag enables use of IESB capability to 1013 reduce entry latency into EL3 even when RAS error handling is not performed 1014 on the platform. Hence this flag is recommended to be turned on Armv8.2 and 1015 later CPUs. This flag can take the values 0 to 2, to align with the 1016 ``ENABLE_FEAT`` mechanism. The default is 0. 1017 1018- ``RESET_TO_BL31``: Enable BL31 entrypoint as the CPU reset vector instead 1019 of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 1020 entrypoint) or 1 (CPU reset to BL31 entrypoint). 1021 The default value is 0. 1022 1023- ``RESET_TO_SP_MIN``: SP_MIN is the minimal AArch32 Secure Payload provided 1024 in TF-A. This flag configures SP_MIN entrypoint as the CPU reset vector 1025 instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 1026 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0. 1027 1028- ``RME_GPT_BITLOCK_BLOCK``: This defines the block size (in number of 512MB 1029 blocks) covered by a single bit of the bitlock structure during RME GPT 1030 operations. The lower the block size, the better opportunity for 1031 parallelising GPT operations but at the cost of more bits being needed 1032 for the bitlock structure. This numeric parameter can take the values 1033 from 0 to 512 and must be a power of 2. The value of 0 is special and 1034 and it chooses a single spinlock for all GPT L1 table entries. Default 1035 value is 1 which corresponds to block size of 512MB per bit of bitlock 1036 structure. 1037 1038- ``RME_GPT_MAX_BLOCK``: Numeric value in MB to define the maximum size of 1039 supported contiguous blocks in GPT Library. This parameter can take the 1040 values 0, 2, 32 and 512. Setting this value to 0 disables use of Contigious 1041 descriptors. Default value is 512. 1042 1043- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 1044 file that contains the ROT private key in PEM format or a PKCS11 URI and 1045 enforces public key hash generation. If ``SAVE_KEYS=1``, only a file is 1046 accepted and it will be used to save the key. 1047 1048- ``SAVE_KEYS``: This option is used when ``GENERATE_COT=1``. It tells the 1049 certificate generation tool to save the keys used to establish the Chain of 1050 Trust. Allowed options are '0' or '1'. Default is '0' (do not save). 1051 1052- ``SCP_BL2``: Path to SCP_BL2 image in the host file system. This image is optional. 1053 If a SCP_BL2 image is present then this option must be passed for the ``fip`` 1054 target. 1055 1056- ``SCP_BL2_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a 1057 file that contains the SCP_BL2 private key in PEM format or a PKCS11 URI. 1058 If ``SAVE_KEYS=1``, only a file is accepted and it will be used to save the key. 1059 1060- ``SCP_BL2U``: Path to SCP_BL2U image in the host file system. This image is 1061 optional. It is only needed if the platform makefile specifies that it 1062 is required in order to build the ``fwu_fip`` target. 1063 1064- ``SDEI_SUPPORT``: Setting this to ``1`` enables support for Software 1065 Delegated Exception Interface to BL31 image. This defaults to ``0``. 1066 1067 When set to ``1``, the build option ``EL3_EXCEPTION_HANDLING`` must also be 1068 set to ``1``. 1069 1070- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be 1071 isolated on separate memory pages. This is a trade-off between security and 1072 memory usage. See "Isolating code and read-only data on separate memory 1073 pages" section in :ref:`Firmware Design`. This flag is disabled by default 1074 and affects all BL images. 1075 1076- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS 1077 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be 1078 allocated in RAM discontiguous from the loaded firmware image. When set, the 1079 platform is expected to provide definitions for ``BL31_NOBITS_BASE`` and 1080 ``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS 1081 sections are placed in RAM immediately following the loaded firmware image. 1082 1083- ``SEPARATE_BL2_NOLOAD_REGION``: Setting this option to ``1`` allows the 1084 NOLOAD sections of BL2 (.bss, stacks, page tables) to be allocated in RAM 1085 discontiguous from loaded firmware images. When set, the platform need to 1086 provide definitions of ``BL2_NOLOAD_START`` and ``BL2_NOLOAD_LIMIT``. This 1087 flag is disabled by default and NOLOAD sections are placed in RAM immediately 1088 following the loaded firmware image. 1089 1090- ``SEPARATE_BL2_FIP``: This option enables the separation of the BL2 FIP image 1091 from the main FIP image. When this option is enabled, the BL2 FIP image is built 1092 as a separate FIP image. The default value is 0. 1093 1094- ``SEPARATE_SIMD_SECTION``: Setting this option to ``1`` allows the SIMD context 1095 data structures to be put in a dedicated memory region as decided by platform 1096 integrator. Default value is ``0`` which means the SIMD context is put in BSS 1097 section of EL3 firmware. 1098 1099- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration 1100 access requests via a standard SMCCC defined in `DEN0115`_. When combined with 1101 UEFI+ACPI this can provide a certain amount of OS forward compatibility 1102 with newer platforms that aren't ECAM compliant. 1103 1104- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A. 1105 This build option is only valid if ``ARCH=aarch64``. The value should be 1106 the path to the directory containing the SPD source, relative to 1107 ``services/spd/``; the directory is expected to contain a makefile called 1108 ``<spd-value>.mk``. The SPM Dispatcher standard service is located in 1109 services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher 1110 cannot be enabled when the ``SPM_MM`` option is enabled. 1111 1112- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can 1113 take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops 1114 execution in BL1 just before handing over to BL31. At this point, all 1115 firmware images have been loaded in memory, and the MMU and caches are 1116 turned off. Refer to the "Debugging options" section for more details. 1117 1118- ``SPMC_AT_EL3`` : This boolean option is used jointly with the SPM 1119 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 1120 component runs at the EL3 exception level. The default value is ``0`` ( 1121 disabled). This configuration supports pre-Armv8.4 platforms (aka not 1122 implementing the ``FEAT_SEL2`` extension). 1123 1124- ``SPMC_AT_EL3_SEL0_SP`` : Boolean option to enable SEL0 SP load support when 1125 ``SPMC_AT_EL3`` is enabled. The default value if ``0`` (disabled). This 1126 option cannot be enabled (``1``) when (``SPMC_AT_EL3``) is disabled. 1127 1128- ``SPMC_OPTEE`` : This boolean option is used jointly with the SPM 1129 Dispatcher option (``SPD=spmd``) and with ``SPMD_SPM_AT_SEL2=0`` to 1130 indicate that the SPMC at S-EL1 is OP-TEE and an OP-TEE specific loading 1131 mechanism should be used. 1132 1133- ``SPMD_SPM_AT_SEL2`` : This boolean option is used jointly with the SPM 1134 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC 1135 component runs at the S-EL2 exception level provided by the ``FEAT_SEL2`` 1136 extension. This is the default when enabling the SPM Dispatcher. When 1137 disabled (0) it indicates the SPMC component runs at the S-EL1 execution 1138 state or at EL3 if ``SPMC_AT_EL3`` is enabled. The latter configurations 1139 support pre-Armv8.4 platforms (aka not implementing the ``FEAT_SEL2`` 1140 extension). 1141 1142- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure 1143 Partition Manager (SPM) implementation. The default value is ``0`` 1144 (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is 1145 enabled (``SPD=spmd``). 1146 1147- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the 1148 description of secure partitions. The build system will parse this file and 1149 package all secure partition blobs into the FIP. This file is not 1150 necessarily part of TF-A tree. Only available when ``SPD=spmd``. 1151 1152- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles 1153 secure interrupts (caught through the FIQ line). Platforms can enable 1154 this directive if they need to handle such interruption. When enabled, 1155 the FIQ are handled in monitor mode and non secure world is not allowed 1156 to mask these events. Platforms that enable FIQ handling in SP_MIN shall 1157 implement the api ``sp_min_plat_fiq_handler()``. The default value is 0. 1158 1159- ``SVE_VECTOR_LEN``: SVE vector length to configure in ZCR_EL3. 1160 Platforms can configure this if they need to lower the hardware 1161 limit, for example due to asymmetric configuration or limitations of 1162 software run at lower ELs. The default is the architectural maximum 1163 of 2048 which should be suitable for most configurations, the 1164 hardware will limit the effective VL to the maximum physically supported 1165 VL. 1166 1167- ``TRNG_SUPPORT``: Setting this to ``1`` enables support for True 1168 Random Number Generator Interface to BL31 image. This defaults to ``0``. 1169 1170- ``TRUSTED_BOARD_BOOT``: Boolean flag to include support for the Trusted Board 1171 Boot feature. When set to '1', BL1 and BL2 images include support to load 1172 and verify the certificates and images in a FIP, and BL1 includes support 1173 for the Firmware Update. The default value is '0'. Generation and inclusion 1174 of certificates in the FIP and FWU_FIP depends upon the value of the 1175 ``GENERATE_COT`` option. 1176 1177 .. warning:: 1178 This option depends on ``CREATE_KEYS`` to be enabled. If the keys 1179 already exist in disk, they will be overwritten without further notice. 1180 1181- ``TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It 1182 specifies a file that contains the Trusted World private key in PEM 1183 format or a PKCS11 URI. If ``SAVE_KEYS=1``, only a file is accepted and 1184 it will be used to save the key. 1185 1186- ``TSP_INIT_ASYNC``: Choose BL32 initialization method as asynchronous or 1187 synchronous, (see "Initializing a BL32 Image" section in 1188 :ref:`Firmware Design`). It can take the value 0 (BL32 is initialized using 1189 synchronous method) or 1 (BL32 is initialized using asynchronous method). 1190 Default is 0. 1191 1192- ``TSP_NS_INTR_ASYNC_PREEMPT``: A non zero value enables the interrupt 1193 routing model which routes non-secure interrupts asynchronously from TSP 1194 to EL3 causing immediate preemption of TSP. The EL3 is responsible 1195 for saving and restoring the TSP context in this routing model. The 1196 default routing model (when the value is 0) is to route non-secure 1197 interrupts to TSP allowing it to save its context and hand over 1198 synchronously to EL3 via an SMC. 1199 1200 .. note:: 1201 When ``EL3_EXCEPTION_HANDLING`` is ``1``, ``TSP_NS_INTR_ASYNC_PREEMPT`` 1202 must also be set to ``1``. 1203 1204- ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and 1205 internal-trusted-storage) as SP in tb_fw_config device tree. 1206 1207- ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of 1208 WFE instruction. ``ENABLE_FEAT_TWED`` build option must be enabled to set 1209 this delay. It can take values in the range (0-15). Default value is ``0`` 1210 and based on this value, 2^(TWED_DELAY + 8) cycles will be delayed. 1211 Platforms need to explicitly update this value based on their requirements. 1212 1213- ``USE_ARM_LINK``: This flag determines whether to enable support for ARM 1214 linker. When the ``LINKER`` build variable points to the armlink linker, 1215 this flag is enabled automatically. To enable support for armlink, platforms 1216 will have to provide a scatter file for the BL image. Currently, Tegra 1217 platforms use the armlink support to compile BL3-1 images. 1218 1219- ``USE_COHERENT_MEM``: This flag determines whether to include the coherent 1220 memory region in the BL memory map or not (see "Use of Coherent memory in 1221 TF-A" section in :ref:`Firmware Design`). It can take the value 1 1222 (Coherent memory region is included) or 0 (Coherent memory region is 1223 excluded). Default is 1. 1224 1225- ``USE_KERNEL_DT_CONVENTION``: When this option is enabled, the hardware 1226 device tree is passed to BL33 using register x0, aligning with the expectations 1227 of the Linux kernel on Arm platforms. If this option is disabled, a different 1228 register, typically x1, may be used instead. This build option is 1229 not necessary when firmware handoff is active (that is, when TRANSFER_LIST=1 1230 is set), and it will be removed once all platforms have transitioned to that 1231 convention. 1232 1233- ``USE_DSU_DRIVER``: This flag enables DSU (DynamIQ Shared Unit) driver. 1234 The DSU driver allows save/restore of DSU PMU registers through 1235 ``PRESERVE_DSU_PMU_REGS`` build option, provides access to PMU registers at 1236 EL1 and allows platforms to configure powerdown and power settings of DSU. 1237 1238- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the 1239 firmware configuration framework. This will move the io_policies into a 1240 configuration device tree, instead of static structure in the code base. 1241 1242- ``COT_DESC_IN_DTB``: This flag determines whether to create COT descriptors 1243 at runtime using fconf. If this flag is enabled, COT descriptors are 1244 statically captured in tb_fw_config file in the form of device tree nodes 1245 and properties. Currently, COT descriptors used by BL2 are moved to the 1246 device tree and COT descriptors used by BL1 are retained in the code 1247 base statically. 1248 1249- ``SDEI_IN_FCONF``: This flag determines whether to configure SDEI setup in 1250 runtime using firmware configuration framework. The platform specific SDEI 1251 shared and private events configuration is retrieved from device tree rather 1252 than static C structures at compile time. This is only supported if 1253 SDEI_SUPPORT build flag is enabled. 1254 1255- ``SEC_INT_DESC_IN_FCONF``: This flag determines whether to configure Group 0 1256 and Group1 secure interrupts using the firmware configuration framework. The 1257 platform specific secure interrupt property descriptor is retrieved from 1258 device tree in runtime rather than depending on static C structure at compile 1259 time. 1260 1261- ``USE_ROMLIB``: This flag determines whether library at ROM will be used. 1262 This feature creates a library of functions to be placed in ROM and thus 1263 reduces SRAM usage. Refer to :ref:`Library at ROM` for further details. Default 1264 is 0. 1265 1266- ``V``: Verbose build. If assigned anything other than 0, the build commands 1267 are printed. Default is 0. 1268 1269- ``VERSION_STRING``: String used in the log output for each TF-A image. 1270 Defaults to a string formed by concatenating the version number, build type 1271 and build string. 1272 1273- ``W``: Warning level. Some compiler warning options of interest have been 1274 regrouped and put in the root Makefile. This flag can take the values 0 to 3, 1275 each level enabling more warning options. Default is 0. 1276 1277 This option is closely related to the ``E`` option, which enables 1278 ``-Werror``. 1279 1280 - ``W=0`` (default) 1281 1282 Enables a wide assortment of warnings, most notably ``-Wall`` and 1283 ``-Wextra``, as well as various bad practices and things that are likely to 1284 result in errors. Includes some compiler specific flags. No warnings are 1285 expected at this level for any build. 1286 1287 - ``W=1`` 1288 1289 Enables warnings we want the generic build to include but are too time 1290 consuming to fix at the moment. It re-enables warnings taken out for 1291 ``W=0`` builds (a few of the ``-Wextra`` additions). This level is expected 1292 to eventually be merged into ``W=0``. Some warnings are expected on some 1293 builds, but new contributions should not introduce new ones. 1294 1295 - ``W=2`` (recommended) 1296 1297 Enables warnings we want the generic build to include but cannot be enabled 1298 due to external libraries. This level is expected to eventually be merged 1299 into ``W=0``. Lots of warnings are expected, primarily from external 1300 libraries like zlib and compiler-rt, but new controbutions should not 1301 introduce new ones. 1302 1303 - ``W=3`` 1304 1305 Enables warnings that are informative but not necessary and generally too 1306 verbose and frequently ignored. A very large number of warnings are 1307 expected. 1308 1309 The exact set of warning flags depends on the compiler and TF-A warning 1310 level, however they are all succinctly set in the top-level Makefile. Please 1311 refer to the `GCC`_ or `Clang`_ documentation for more information on the 1312 individual flags. 1313 1314- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on 1315 the CPU after warm boot. This is applicable for platforms which do not 1316 require interconnect programming to enable cache coherency (eg: single 1317 cluster platforms). If this option is enabled, then warm boot path 1318 enables D-caches immediately after enabling MMU. This option defaults to 0. 1319 1320- ``ERRATA_SPECULATIVE_AT``: This flag determines whether to enable ``AT`` 1321 speculative errata workaround or not. It accepts 2 values: ``1`` and ``0``. 1322 The default value of this flag is ``0``. 1323 1324 ``AT`` speculative errata workaround disables stage1 page table walk for 1325 lower ELs (EL1 and EL0) in EL3 so that ``AT`` speculative fetch at any point 1326 produces either the correct result or failure without TLB allocation. 1327 1328 This boolean option enables errata for all below CPUs. 1329 1330 +---------+--------------+-------------------------+ 1331 | Errata | CPU | Workaround Define | 1332 +=========+==============+=========================+ 1333 | 1165522 | Cortex-A76 | ``ERRATA_A76_1165522`` | 1334 +---------+--------------+-------------------------+ 1335 | 1319367 | Cortex-A72 | ``ERRATA_A72_1319367`` | 1336 +---------+--------------+-------------------------+ 1337 | 1541130 | Cortex-A65 | ``ERRATA_A65_1541130`` | 1338 +---------+--------------+-------------------------+ 1339 | 1638571 | Cortex-A65AE | ``ERRATA_A65AE_1638571``| 1340 +---------+--------------+-------------------------+ 1341 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` | 1342 +---------+--------------+-------------------------+ 1343 | 1530923 | Cortex-A55 | ``ERRATA_A55_1530923`` | 1344 +---------+--------------+-------------------------+ 1345 | 1530924 | Cortex-A53 | ``ERRATA_A53_1530924`` | 1346 +---------+--------------+-------------------------+ 1347 1348 .. note:: 1349 This option is enabled by build only if platform sets any of above defines 1350 mentioned in ’Workaround Define' column in the table. 1351 If this option is enabled for the EL3 software then EL2 software also must 1352 implement this workaround due to the behaviour of the errata mentioned 1353 in new SDEN document which will get published soon. 1354 1355- ``RAS_TRAP_NS_ERR_REC_ACCESS``: This flag enables/disables the SCR_EL3.TERR 1356 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs. 1357 This flag is disabled by default. 1358 1359- ``OPENSSL_DIR``: This option is used to provide the path to a directory on the 1360 host machine where a custom installation of OpenSSL is located, which is used 1361 to build the certificate generation, firmware encryption and FIP tools. If 1362 this option is not set, the default OS installation will be used. 1363 1364- ``USE_SP804_TIMER``: Use the SP804 timer instead of the Generic Timer for 1365 functions that wait for an arbitrary time length (udelay and mdelay). The 1366 default value is 0. 1367 1368- ``ENABLE_BRBE_FOR_NS``: Numeric value to enable access to the branch record 1369 buffer registers from NS ELs when FEAT_BRBE is implemented. BRBE is an 1370 optional architectural feature for AArch64. This flag can take the values 1371 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0 1372 and it is automatically disabled when the target architecture is AArch32. 1373 1374- ``ENABLE_TRBE_FOR_NS``: Numeric value to enable access of trace buffer 1375 control registers from NS ELs, NS-EL2 or NS-EL1(when NS-EL2 is implemented 1376 but unused) when FEAT_TRBE is implemented. TRBE is an optional architectural 1377 feature for AArch64. This flag can take the values 0 to 2, to align with the 1378 ``ENABLE_FEAT`` mechanism. The default is 0 and it is automatically 1379 disabled when the target architecture is AArch32. 1380 1381- ``USE_SPINLOCK_CAS``: Numeric value to use FEAT_LSE atomics instead of 1382 load/store exclusive instructions with spinlocks. FEAT_LSE is a mandatory 1383 feature from v8.1, however it is only architecturally guaranteed to work on 1384 "conventional memory" which may not apply to tightly coupled memory (eg. SRAM, 1385 TF-A's usual place). Platforms must check if TF-A's memory can be targetted 1386 by atomics before enabling this feature. Expected to increase performance on 1387 systems with many cores. This flag can take the values 0 to 2, to align with 1388 the ``ENABLE_FEAT`` mechanism. The default is 0. 1389 1390- ``ENABLE_SYS_REG_TRACE_FOR_NS``: Numeric value to enable trace system 1391 registers access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented 1392 but unused). This feature is available if trace unit such as ETMv4.x, and 1393 ETE(extending ETM feature) is implemented. This flag can take the values 1394 0 to 2, to align with the ``ENABLE_FEAT`` mechanism. The default is 0. 1395 1396- ``ENABLE_TRF_FOR_NS``: Numeric value to enable trace filter control registers 1397 access from NS ELs, NS-EL2 or NS-EL1 (when NS-EL2 is implemented but unused), 1398 if FEAT_TRF is implemented. This flag can take the values 0 to 2, to align 1399 with the ``ENABLE_FEAT`` mechanism. This flag is disabled by default. 1400 1401- ``CONDITIONAL_CMO``: Boolean option to enable call to platform-defined routine 1402 ``plat_can_cmo`` which will return zero if cache management operations should 1403 be skipped and non-zero otherwise. By default, this option is disabled which 1404 means platform hook won't be checked and CMOs will always be performed when 1405 related functions are called. 1406 1407- ``ERRATA_ABI_SUPPORT``: Boolean option to enable support for Errata management 1408 firmware interface for the BL31 image. By default its disabled (``0``). 1409 1410- ``ERRATA_NON_ARM_INTERCONNECT``: Boolean option to enable support for the 1411 errata mitigation for platforms with a non-arm interconnect using the errata 1412 ABI. By default its disabled (``0``). 1413 1414- ``ENABLE_CONSOLE_GETC``: Boolean option to enable `getc()` feature in console 1415 driver(s). By default it is disabled (``0``) because it constitutes an attack 1416 vector into TF-A by potentially allowing an attacker to inject arbitrary data. 1417 This option should only be enabled on a need basis if there is a use case for 1418 reading characters from the console. 1419 1420GIC driver options 1421-------------------- 1422 1423The generic GIC driver can be included with the ``USE_GIC_DRIVER`` option. It is 1424a numeric option that can take the following values: 1425 1426 - ``0``: generic GIC driver not enabled. Any support is entirely in platform 1427 code. Strongly discouraged for GIC based interrupt controllers. 1428 1429 - ``1``: enable the use of the generic GIC driver but do not include any files 1430 or function definitions. It is then the platform's responsibility to provide 1431 these. This is useful if the platform either has a custom GIC implementation 1432 or an alternative interrupt controller design. Use of this option is strongly 1433 discouraged for standard GIC implementations. 1434 1435 - ``2``: use the GICv2 driver 1436 1437 - ``3``: use the GICv3 driver. See the next section on how to further configure 1438 it. Use this option for GICv4 implementations. Requires calling 1439 ``gic_set_gicr_frames()``. 1440 1441 - ``5``: use the EXPERIMENTAL GICv5 driver. Requires ``ENABLE_FEAT_GCIE=1``. 1442 1443 For GIC driver versions other than ``1``, deciding when to save and restore GIC 1444 context on a power domain state transition, as well as any GIC actions outside 1445 of the PSCI library's visibility are the platform's responsibility. The driver 1446 provides implementations of all necessary subroutines, they only need to be 1447 called as appropriate. 1448 1449GICv3 driver options 1450~~~~~~~~~~~~~~~~~~~~ 1451 1452``USE_GIC_DRIVER=3`` is the preferred way of including GICv3 driver files. The 1453old (deprecated) way of included them is using the directive: 1454``include drivers/arm/gic/v3/gicv3.mk`` 1455 1456The driver can be configured with the following options set in the platform 1457makefile: 1458 1459- ``GICV3_SUPPORT_GIC600``: Add support for the GIC-600 variants of GICv3. 1460 Enabling this option will add runtime detection support for the 1461 GIC-600, so is safe to select even for a GIC500 implementation. 1462 This option defaults to 0. 1463 1464- ``GICV3_SUPPORT_GIC600AE_FMU``: Add support for the Fault Management Unit 1465 for GIC-600 AE. Enabling this option will introduce support to initialize 1466 the FMU. Platforms should call the init function during boot to enable the 1467 FMU and its safety mechanisms. This option defaults to 0. 1468 1469- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip 1470 functionality. This option defaults to 0 1471 1472- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation 1473 of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore`` 1474 functions. This is required for FVP platform which need to simulate GIC save 1475 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0. 1476 1477- ``GIC_ENABLE_V4_EXTN`` : Enables GICv4 related changes in GICv3 driver. 1478 This option defaults to 0. 1479 1480- ``GIC_EXT_INTID``: When set to ``1``, GICv3 driver will support extended 1481 PPI (1056-1119) and SPI (4096-5119) range. This option defaults to 0. 1482 1483Debugging options 1484----------------- 1485 1486To compile a debug version and make the build more verbose use 1487 1488.. code:: shell 1489 1490 make PLAT=<platform> DEBUG=1 V=1 all 1491 1492AArch64 GCC 11 uses DWARF version 5 debugging symbols by default. Some tools 1493(for example Arm-DS) might not support this and may need an older version of 1494DWARF symbols to be emitted by GCC. This can be achieved by using the 1495``-gdwarf-<version>`` flag, with the version being set to 2, 3, 4 or 5. Setting 1496the version to 4 is recommended for Arm-DS. 1497 1498When debugging logic problems it might also be useful to disable all compiler 1499optimizations by using ``-O0``. 1500 1501.. warning:: 1502 Using ``-O0`` could cause output images to be larger and base addresses 1503 might need to be recalculated (see the **Memory layout on Arm development 1504 platforms** section in the :ref:`Firmware Design`). 1505 1506Extra debug options can be passed to the build system by setting ``CFLAGS`` or 1507``LDFLAGS``: 1508 1509.. code:: shell 1510 1511 CFLAGS='-O0 -gdwarf-2' \ 1512 make PLAT=<platform> DEBUG=1 V=1 all 1513 1514Note that using ``-Wl,`` style compilation driver options in ``CFLAGS`` will be 1515ignored as the linker is called directly. 1516 1517It is also possible to introduce an infinite loop to help in debugging the 1518post-BL2 phase of TF-A. This can be done by rebuilding BL1 with the 1519``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the :ref:`build_options_common` 1520section. In this case, the developer may take control of the target using a 1521debugger when indicated by the console output. When using Arm-DS, the following 1522commands can be used: 1523 1524:: 1525 1526 # Stop target execution 1527 interrupt 1528 1529 # 1530 # Prepare your debugging environment, e.g. set breakpoints 1531 # 1532 1533 # Jump over the debug loop 1534 set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 1535 1536 # Resume execution 1537 continue 1538 1539.. _build_options_experimental: 1540 1541Experimental build options 1542--------------------------- 1543 1544Common build options 1545~~~~~~~~~~~~~~~~~~~~ 1546 1547- ``DICE_PROTECTION_ENVIRONMENT``: Boolean flag to specify the measured boot 1548 backend when ``MEASURED_BOOT`` is enabled. The default value is ``0``. When 1549 set to ``1`` then measurements and additional metadata collected during the 1550 measured boot process are sent to the DICE Protection Environment for storage 1551 and processing. A certificate chain, which represents the boot state of the 1552 device, can be queried from the DPE. 1553 1554- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust 1555 for Measurement (DRTM). This feature has trust dependency on BL31 for taking 1556 the measurements and recording them as per `PSA DRTM specification`_. For 1557 platforms which use BL2 to load/authenticate BL31 ``TRUSTED_BOARD_BOOT`` can 1558 be used and for the platforms which use ``RESET_TO_BL31`` platform owners 1559 should have mechanism to authenticate BL31. This option defaults to 0. 1560 1561- ``ENABLE_RMM``: Boolean flag to enable the Realm-EL2 payload (RMM). 1562 This will take care of loading and initialising an image in Realm-EL2, and 1563 will at runtime dispatch calls from non-secure world to the RMM, if 1564 applicable. 1565 Default value is 0. Setting this flag implies that RMM must be enabled 1566 therefore, it mandates ``ENABLE_FEAT_RME`` to 1. 1567 1568- ``ENABLE_FEAT_RME``: Numeric value to enable support for the ARMv9 Realm 1569 Management Extension. This flag can take the values 0 to 2, to align with 1570 the ``ENABLE_FEAT`` mechanism. Default value is 0. 1571 This flag solely controls the architectural bits of RME, to let TF-A run 1572 in the "root" physical address space and this will setup Granule Protection 1573 Tables (GPT). Also this will make BL2 run in EL3, so it has access to the new 1574 root address space. For deploying a Realm-EL2 payload (RMM), also set 1575 ``ENABLE_RMM`` and provide an RMM image file. 1576 1577- ``ENABLE_RME``: This options will be deprecated. Please use 1578 ``ENABLE_FEAT_RME``. Until deprecated, setting this option to 1, will also 1579 set ``ENABLE_FEAT_RME`` and ``ENABLE_RMM`` to 1. 1580 1581- ``ENABLE_FEAT_MEC``: Numeric value to enable support for the ARMv9.2 Memory 1582 Encryption Contexts (MEC). This flag can take the values 0 to 2, to align 1583 with the ``ENABLE_FEAT`` mechanism. MEC supports multiple encryption 1584 contexts for Realm security state and only one encryption context for the 1585 rest of the security states. Default value is 0. 1586 1587- ``RMM_V1_COMPAT``: Boolean flag to enable support for RMM v1.x compatibility 1588 mode. When set to 0, TF-A will use the RMM-EL3 interface version required 1589 for RMMv2.0. Default value is 0. 1590 1591- ``FIRME_SUPPORT``: This option enables the FIRME service in TF-A. 1592 1593- ``RMMD_ENABLE_EL3_TOKEN_SIGN``: Numeric value to enable support for singing 1594 realm attestation token signing requests in EL3. This flag can take the 1595 values 0 and 1. The default value is ``0``. When set to ``1``, this option 1596 enables additional RMMD SMCs to push and pop requests for signing to 1597 EL3 along with platform hooks that must be implemented to service those 1598 requests and responses. 1599 1600- ``ENABLE_SME_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1601 (SME), SVE, and FPU/SIMD for the non-secure world only. These features share 1602 registers so are enabled together. Using this option without 1603 ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure 1604 world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a 1605 superset of SVE. SME is an optional architectural feature for AArch64. 1606 At this time, this build option cannot be used on systems that have 1607 SPD=spmd/SPM_MM and atempting to build with this option will fail. 1608 This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT`` 1609 mechanism. Default is 0. 1610 1611- ``ENABLE_SME2_FOR_NS``: Numeric value to enable Scalable Matrix Extension 1612 version 2 (SME2) for the non-secure world only. SME2 is an optional 1613 architectural feature for AArch64. 1614 This should be set along with ENABLE_SME_FOR_NS=1, if not, the default SME 1615 accesses will still be trapped. This flag can take the values 0 to 2, to 1616 align with the ``ENABLE_FEAT`` mechanism. Default is 0. 1617 1618- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix 1619 Extension for secure world. Used along with SVE and FPU/SIMD. 1620 ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this. 1621 Default is 0. 1622 1623- ``ENABLE_SPMD_LP`` : This boolean option is used jointly with the SPM 1624 Dispatcher option (``SPD=spmd``). When enabled (1) it indicates support 1625 for logical partitions in EL3, managed by the SPMD as defined in the 1626 FF-A v1.2 specification. This flag is disabled by default. This flag 1627 must not be used if ``SPMC_AT_EL3`` is enabled. 1628 1629- ``FEATURE_DETECTION``: Boolean option to enable the architectural features 1630 verification mechanism. This is a debug feature that compares the 1631 architectural features enabled through the feature specific build flags 1632 (ENABLE_FEAT_xxx) with the features actually available on the CPU running, 1633 and reports any discrepancies. 1634 This flag will also enable errata ordering checking for ``DEBUG`` builds. 1635 1636 It is expected that this feature is only used for flexible platforms like 1637 software emulators, or for hardware platforms at bringup time, to verify 1638 that the configured feature set matches the CPU. 1639 The ``FEATURE_DETECTION`` macro is disabled by default. 1640 1641- ``PSA_CRYPTO``: Boolean option for enabling MbedTLS PSA crypto APIs support. 1642 The platform will use PSA compliant Crypto APIs during authentication and 1643 image measurement process by enabling this option. It uses APIs defined as 1644 per the `PSA Crypto API specification`_. This feature is only supported if 1645 using MbedTLS 3.x version. It is disabled (``0``) by default. 1646 1647- ``LFA_SUPPORT``: Boolean flag to enable support for Live Firmware 1648 activation as per the specification. This option defaults to 0. 1649 1650- ``TRANSFER_LIST``: Setting this to ``1`` enables support for Firmware 1651 Handoff using Transfer List defined in `Firmware Handoff specification`_. 1652 This defaults to ``0``. Current implementation follows the Firmware Handoff 1653 specification v0.9. 1654 1655- ``USE_DEBUGFS``: When set to 1 this option exposes a virtual filesystem 1656 interface through BL31 as a SiP SMC function. 1657 Default is disabled (0). 1658 1659- ``HOB_LIST``: Setting this to ``1`` enables support for passing boot 1660 information using HOB defined in `Platform Initialization specification`_. 1661 This defaults to ``0``. 1662 1663- ``ENABLE_ACS_SMC``: When set to ``1``, this enables support for ACS SMC 1664 handler code to handle SMC calls from the Architecture Compliance Suite. The 1665 handler is intentionally empty to reserve the SMC section and allow 1666 project-specific implementations in future ACS use cases. 1667 1668Firmware update options 1669~~~~~~~~~~~~~~~~~~~~~~~ 1670 1671- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the 1672 `PSA FW update specification`_. The default value is 0. 1673 PSA firmware update implementation has few limitations, such as: 1674 1675 - BL2 is not part of the protocol-updatable images. If BL2 needs to 1676 be updated, then it should be done through another platform-defined 1677 mechanism. 1678 1679 - It assumes the platform's hardware supports CRC32 instructions. 1680 1681- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used 1682 in defining the firmware update metadata structure. This flag is by default 1683 set to '2'. 1684 1685- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each 1686 firmware bank. Each firmware bank must have the same number of images as per 1687 the `PSA FW update specification`_. 1688 This flag is used in defining the firmware update metadata structure. This 1689 flag is by default set to '1'. 1690 1691- ``PSA_FWU_METADATA_FW_STORE_DESC``: To be enabled when the FWU 1692 metadata contains image description. The default value is 1. 1693 1694 The version 2 of the FWU metadata allows for an opaque metadata 1695 structure where a platform can choose to not include the firmware 1696 store description in the metadata structure. This option indicates 1697 if the firmware store description, which provides information on 1698 the updatable images is part of the structure. 1699 1700.. _sp_live_activation_build_options: 1701 1702SP Live Activation build options 1703~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1704 1705- ``SUPPORT_SP_LIVE_ACTIVATION``: Boolean option to enable live activation of 1706 Secure Partition(s) by using common SPMD LSP helpers. Enforces all of the 1707 following dependencies are met: 1708 1709 - ``LFA_SUPPORT=1`` to enable the live activation service in BL31. 1710 - ``ENABLE_SPMD_LP=1`` allows SPMD logical secure partition to be enabled. 1711 - ``SPMD_SPM_AT_SEL2=1`` as the current implementation only supports working 1712 with an S-EL2 SPMC (for example, Hafnium) to live activate an SP; It is 1713 incompatible with EL3 SPMC. 1714 1715 This flag is experimental and currently exercised on FVP. Default value is 0. 1716 1717Negative test scenario options 1718~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1719 1720- ``TEST_IO_SHORT_READ_FI``: Boolean flag to enable a negative-test for the 1721 BL image loader. When set to ``1``, TF-A intentionally simulates a short 1722 read for the image selected by ``TEST_IO_SHORT_READ_FI_IMAGE_ID`` by reporting 1723 fewer bytes read than the image size. This exercises the "read too short" 1724 error handling path in ``load_image()`` and is intended for test/CI only. 1725 Default is ``0`` (disabled). Must not be used on production devices. 1726 1727- ``TEST_IO_SHORT_READ_FI_IMAGE_ID``: Numeric flag that selects the ``image_id`` 1728 for which the short-read fault is injected when ``TEST_IO_SHORT_READ_FI=1``. 1729 The value must match the image identifiers used by the platform image loading 1730 flow (for example ``BL31_IMAGE_ID``, ``BL33_IMAGE_ID``, etc., depending on the 1731 build and platform). Default is ``0``. 1732 1733-------------- 1734 1735*Copyright (c) 2019-2026, Arm Limited. All rights reserved.* 1736 1737.. _DEN0115: https://developer.arm.com/docs/den0115/latest 1738.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/latest/ 1739.. _PSA DRTM specification: https://developer.arm.com/documentation/den0113/a 1740.. _GCC: https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html 1741.. _Clang: https://clang.llvm.org/docs/DiagnosticsReference.html 1742.. _Firmware Handoff specification: https://github.com/FirmwareHandoff/firmware_handoff/releases/tag/v0.9 1743.. _PSA Crypto API specification: https://armmbed.github.io/mbed-crypto/html/ 1744.. _Platform Initialization specification: https://uefi.org/specs/PI/1.8/index.html 1745.. _TF-A public mailing list: https://lists.trustedfirmware.org/mailman3/lists/tf-a.lists.trustedfirmware.org/ 1746