1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _FG_RK8XX_H_ 8 #define _FG_RK8XX_H_ 9 10 /* register definition */ 11 #define SECONDS_REG 0X00 12 #define VB_MON_REG 0x21 13 #define THERMAL_REG 0x22 14 #define SUP_STS_REG 0xA0 15 #define USB_CTRL_REG 0xA1 16 #define CHRG_CTRL_REG1 0xA3 17 #define CHRG_CTRL_REG2 0xA4 18 #define CHRG_CTRL_REG3 0xA5 19 #define BAT_CTRL_REG 0xA6 20 #define BAT_HTS_TS_REG 0xA8 21 #define BAT_LTS_TS_REG 0xA9 22 #define TS_CTRL_REG 0xAC 23 #define ADC_CTRL_REG 0xAD 24 #define GGCON_REG 0xB0 25 #define GGSTS_REG 0xB1 26 #define ZERO_CUR_ADC_REGH 0xB2 27 #define ZERO_CUR_ADC_REGL 0xB3 28 #define GASCNT_CAL_REG3 0xB4 29 #define GASCNT_CAL_REG2 0xB5 30 #define GASCNT_CAL_REG1 0xB6 31 #define GASCNT_CAL_REG0 0xB7 32 #define GASCNT_REG3 0xB8 33 #define GASCNT_REG2 0xB9 34 #define GASCNT_REG1 0xBA 35 #define GASCNT_REG0 0xBB 36 #define BAT_CUR_AVG_REGH 0xBC 37 #define BAT_CUR_AVG_REGL 0xBD 38 #define TS_ADC_REGH 0xBE 39 #define TS_ADC_REGL 0xBF 40 #define RK818_TS2_ADC_REGH 0xC0 41 #define RK818_TS2_ADC_REGL 0xC1 42 #define RK816_USB_ADC_REGH 0xC0 43 #define RK816_USB_ADC_REGL 0xC1 44 #define BAT_OCV_REGH 0xC2 45 #define BAT_OCV_REGL 0xC3 46 #define BAT_VOL_REGH 0xC4 47 #define BAT_VOL_REGL 0xC5 48 #define RELAX_ENTRY_THRES_REGH 0xC6 49 #define RELAX_ENTRY_THRES_REGL 0xC7 50 #define RELAX_EXIT_THRES_REGH 0xC8 51 #define RELAX_EXIT_THRES_REGL 0xC9 52 #define RELAX_VOL1_REGH 0xCA 53 #define RELAX_VOL1_REGL 0xCB 54 #define RELAX_VOL2_REGH 0xCC 55 #define RELAX_VOL2_REGL 0xCD 56 #define RELAX_CUR1_REGH 0xCE 57 #define RELAX_CUR1_REGL 0xCF 58 #define RELAX_CUR2_REGH 0xD0 59 #define RELAX_CUR2_REGL 0xD1 60 #define CAL_OFFSET_REGH 0xD2 61 #define CAL_OFFSET_REGL 0xD3 62 #define NON_ACT_TIMER_CNT_REG 0xD4 63 #define VCALIB0_REGH 0xD5 64 #define VCALIB0_REGL 0xD6 65 #define VCALIB1_REGH 0xD7 66 #define VCALIB1_REGL 0xD8 67 #define FCC_GASCNT_REG3 0xD9 68 #define FCC_GASCNT_REG2 0xDA 69 #define FCC_GASCNT_REG1 0xDB 70 #define FCC_GASCNT_REG0 0xDC 71 #define IOFFSET_REGH 0xDD 72 #define IOFFSET_REGL 0xDE 73 #define SLEEP_CON_SAMP_CUR_REG 0xDF 74 #define SOC_REG 0xE0 75 #define REMAIN_CAP_REG3 0xE1 76 #define REMAIN_CAP_REG2 0xE2 77 #define REMAIN_CAP_REG1 0xE3 78 #define REMAIN_CAP_REG0 0xE4 79 #define UPDAT_LEVE_REG 0xE5 80 #define NEW_FCC_REG3 0xE6 81 #define NEW_FCC_REG2 0xE7 82 #define NEW_FCC_REG1 0xE8 83 #define NEW_FCC_REG0 0xE9 84 #define NON_ACT_TIMER_CNT_SAVE_REG 0xEA 85 #define OCV_VOL_VALID_REG 0xEB 86 #define REBOOT_CNT_REG 0xEC 87 #define POFFSET_REG 0xED 88 #define MISC_MARK_REG 0xEE 89 #define HALT_CNT_REG 0xEF 90 #define DATA15_REG 0xEF 91 #define DATA16_REG 0xF0 92 #define DATA17_REG 0xF1 93 #define DATA18_REG 0xF2 94 95 #endif 96