1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright 2020-2021, 2023-2025 NXP 4 */ 5 #ifndef S32CC_CLK_REGS_H 6 #define S32CC_CLK_REGS_H 7 8 #include <lib/utils_def.h> 9 10 #define FXOSC_BASE_ADDR (0x40050000UL) 11 #define ARMPLL_BASE_ADDR (0x40038000UL) 12 #define PERIPHPLL_BASE_ADDR (0x4003C000UL) 13 #define ARM_DFS_BASE_ADDR (0x40054000UL) 14 #define PERIPH_DFS_BASE_ADDR (0x40058000UL) 15 #define CGM0_BASE_ADDR (0x40030000UL) 16 #define CGM1_BASE_ADDR (0x40034000UL) 17 #define DDRPLL_BASE_ADDR (0x40044000UL) 18 #define MC_ME_BASE_ADDR (0x40088000UL) 19 #define MC_RGM_BASE_ADDR (0x40078000UL) 20 #define RDC_BASE_ADDR (0x40080000UL) 21 #define MC_CGM5_BASE_ADDR (0x40068000UL) 22 23 /* FXOSC */ 24 #define FXOSC_CTRL(FXOSC) ((FXOSC) + 0x0UL) 25 #define FXOSC_CTRL_OSC_BYP BIT_32(31U) 26 #define FXOSC_CTRL_COMP_EN BIT_32(24U) 27 #define FXOSC_CTRL_EOCV_OFFSET 16U 28 #define FXOSC_CTRL_EOCV_MASK GENMASK_32(23U, FXOSC_CTRL_EOCV_OFFSET) 29 #define FXOSC_CTRL_EOCV(VAL) (FXOSC_CTRL_EOCV_MASK & \ 30 ((uint32_t)(VAL) << FXOSC_CTRL_EOCV_OFFSET)) 31 #define FXOSC_CTRL_GM_SEL_OFFSET 4U 32 #define FXOSC_CTRL_GM_SEL_MASK GENMASK_32(7U, FXOSC_CTRL_GM_SEL_OFFSET) 33 #define FXOSC_CTRL_GM_SEL(VAL) (FXOSC_CTRL_GM_SEL_MASK & \ 34 ((uint32_t)(VAL) << FXOSC_CTRL_GM_SEL_OFFSET)) 35 #define FXOSC_CTRL_OSCON BIT_32(0U) 36 37 #define FXOSC_STAT(FXOSC) ((FXOSC) + 0x4UL) 38 #define FXOSC_STAT_OSC_STAT BIT_32(31U) 39 40 /* PLL */ 41 #define PLLDIG_PLLCR(PLL) ((PLL) + 0x0UL) 42 #define PLLDIG_PLLCR_PLLPD BIT_32(31U) 43 44 #define PLLDIG_PLLSR(PLL) ((PLL) + 0x4UL) 45 #define PLLDIG_PLLSR_LOCK BIT_32(2U) 46 47 #define PLLDIG_PLLDV(PLL) ((PLL) + 0x8UL) 48 #define PLLDIG_PLLDV_RDIV_OFFSET 12U 49 #define PLLDIG_PLLDV_RDIV_MASK GENMASK_32(14U, PLLDIG_PLLDV_RDIV_OFFSET) 50 #define PLLDIG_PLLDV_RDIV_SET(VAL) (PLLDIG_PLLDV_RDIV_MASK & \ 51 ((VAL) << PLLDIG_PLLDV_RDIV_OFFSET)) 52 #define PLLDIG_PLLDV_RDIV(VAL) (((VAL) & PLLDIG_PLLDV_RDIV_MASK) >> \ 53 PLLDIG_PLLDV_RDIV_OFFSET) 54 #define PLLDIG_PLLDV_MFI_MASK GENMASK_32(7U, 0U) 55 #define PLLDIG_PLLDV_MFI(DIV) (PLLDIG_PLLDV_MFI_MASK & (DIV)) 56 57 #define PLLDIG_PLLFD(PLL) ((PLL) + 0x10UL) 58 #define PLLDIG_PLLFD_SMDEN BIT_32(30U) 59 #define PLLDIG_PLLFD_MFN_MASK GENMASK_32(14U, 0U) 60 #define PLLDIG_PLLFD_MFN_SET(VAL) (PLLDIG_PLLFD_MFN_MASK & (VAL)) 61 62 #define PLLDIG_PLLCLKMUX(PLL) ((PLL) + 0x20UL) 63 64 #define PLLDIG_PLLODIV(PLL, N) ((PLL) + 0x80UL + ((N) * 0x4UL)) 65 #define PLLDIG_PLLODIV_DE BIT_32(31U) 66 #define PLLDIG_PLLODIV_DIV_OFFSET 16U 67 #define PLLDIG_PLLODIV_DIV_MASK GENMASK_32(23U, PLLDIG_PLLODIV_DIV_OFFSET) 68 #define PLLDIG_PLLODIV_DIV(VAL) (((VAL) & PLLDIG_PLLODIV_DIV_MASK) >> \ 69 PLLDIG_PLLODIV_DIV_OFFSET) 70 #define PLLDIG_PLLODIV_DIV_SET(VAL) (PLLDIG_PLLODIV_DIV_MASK & ((VAL) << \ 71 PLLDIG_PLLODIV_DIV_OFFSET)) 72 73 /* MMC_CGM */ 74 #define CGM_MUXn_CSC(CGM_ADDR, MUX) ((CGM_ADDR) + 0x300UL + ((MUX) * 0x40UL)) 75 #define MC_CGM_MUXn_CSC_SELCTL_OFFSET 24U 76 #define MC_CGM_MUXn_CSC_SELCTL_MASK GENMASK_32(29U, MC_CGM_MUXn_CSC_SELCTL_OFFSET) 77 #define MC_CGM_MUXn_CSC_SELCTL(val) (MC_CGM_MUXn_CSC_SELCTL_MASK & ((val) \ 78 << MC_CGM_MUXn_CSC_SELCTL_OFFSET)) 79 #define MC_CGM_MUXn_CSC_CLK_SW BIT_32(2U) 80 #define MC_CGM_MUXn_CSC_SAFE_SW BIT_32(3U) 81 82 #define CGM_MUXn_CSS(CGM_ADDR, MUX) ((CGM_ADDR) + 0x304UL + ((MUX) * 0x40UL)) 83 #define MC_CGM_MUXn_CSS_SELSTAT_OFFSET 24U 84 #define MC_CGM_MUXn_CSS_SELSTAT_MASK GENMASK_32(29U, MC_CGM_MUXn_CSS_SELSTAT_OFFSET) 85 #define MC_CGM_MUXn_CSS_SELSTAT(css) ((MC_CGM_MUXn_CSS_SELSTAT_MASK & (css))\ 86 >> MC_CGM_MUXn_CSS_SELSTAT_OFFSET) 87 #define MC_CGM_MUXn_CSS_SWTRG(css) ((MC_CGM_MUXn_CSS_SWTRG_MASK & (css)) \ 88 >> MC_CGM_MUXn_CSS_SWTRG_OFFSET) 89 #define MC_CGM_MUXn_CSS_SWTRG_OFFSET 17U 90 #define MC_CGM_MUXn_CSS_SWTRG_MASK GENMASK_32(19U, MC_CGM_MUXn_CSS_SWTRG_OFFSET) 91 #define MC_CGM_MUXn_CSS_SWTRG_SUCCESS 0x1U 92 #define MC_CGM_MUXn_CSS_SWTRG_SAFE_CLK 0x4U 93 #define MC_CGM_MUXn_CSS_SWTRG_SAFE_CLK_INACTIVE 0x5U 94 #define MC_CGM_MUXn_CSS_SWIP BIT_32(16U) 95 #define MC_CGM_MUXn_CSS_SAFE_SW BIT_32(3U) 96 #define MC_CGM_MUXn_DCm(CGM_ADDR, MUX, DC) \ 97 (((CGM_ADDR) + 0x308UL) + \ 98 ((MUX) * 0x40UL) + ((DC) * 0x4UL)) 99 #define MC_CGM_MUXn_DCm_DIV_OFFSET (16U) 100 #define MC_CGM_MUXn_DCm_DIV_MASK GENMASK_32(23U, MC_CGM_MUXn_DCm_DIV_OFFSET) 101 #define MC_CGM_MUXn_DCm_DIV_SET(VAL) (MC_CGM_MUXn_DCm_DIV_MASK & ((VAL) \ 102 << MC_CGM_MUXn_DCm_DIV_OFFSET)) 103 #define MC_CGM_MUXn_DCm_DIV(VAL) ((MC_CGM_MUXn_DCm_DIV_MASK & (VAL)) \ 104 >> MC_CGM_MUXn_DCm_DIV_OFFSET) 105 #define MC_CGM_MUXn_DCm_DE BIT_32(31U) 106 #define MC_CGM_MUXn_DIV_UPD_STAT(CGM_ADDR, MUX) \ 107 (((CGM_ADDR) + 0x33CUL + ((MUX) * 0x40UL))) 108 #define MC_CGM_MUXn_DIV_UPD_STAT_DIVSTAT_OFFSET (0U) 109 #define MC_CGM_MUXn_DIV_UPD_STAT_DIVSTAT(CSS) \ 110 ((MC_CGM_MUXn_DIV_UPD_STAT_DIVSTAT_MASK \ 111 & (CSS)) \ 112 >> MC_CGM_MUXn_DIV_UPD_STAT_DIVSTAT_OFFSET) 113 #define MC_CGM_MUXn_DIV_UPD_STAT_DIVSTAT_MASK BIT_32(0U) 114 115 116 /* DFS */ 117 #define DFS_PORTSR(DFS_ADDR) ((DFS_ADDR) + 0xCUL) 118 #define DFS_PORTOLSR(DFS_ADDR) ((DFS_ADDR) + 0x10UL) 119 #define DFS_PORTOLSR_LOL(N) (BIT_32(N) & GENMASK_32(5U, 0U)) 120 #define DFS_PORTRESET(DFS_ADDR) ((DFS_ADDR) + 0x14UL) 121 #define DFS_PORTRESET_MASK GENMASK_32(5U, 0U) 122 #define DFS_PORTRESET_SET(VAL) (((VAL) & DFS_PORTRESET_MASK)) 123 124 #define DFS_CTL(DFS_ADDR) ((DFS_ADDR) + 0x18UL) 125 #define DFS_CTL_RESET BIT_32(1U) 126 127 #define DFS_DVPORTn(DFS_ADDR, PORT) ((DFS_ADDR) + 0x1CUL + ((PORT) * 0x4UL)) 128 #define DFS_DVPORTn_MFI_MASK GENMASK_32(15U, 8U) 129 #define DFS_DVPORTn_MFI_SHIFT 8U 130 #define DFS_DVPORTn_MFN_MASK GENMASK_32(7U, 0U) 131 #define DFS_DVPORTn_MFN_SHIFT 0U 132 #define DFS_DVPORTn_MFI(MFI) (((MFI) & DFS_DVPORTn_MFI_MASK) >> DFS_DVPORTn_MFI_SHIFT) 133 #define DFS_DVPORTn_MFN(MFN) (((MFN) & DFS_DVPORTn_MFN_MASK) >> DFS_DVPORTn_MFN_SHIFT) 134 #define DFS_DVPORTn_MFI_SET(VAL) (((VAL) << DFS_DVPORTn_MFI_SHIFT) & DFS_DVPORTn_MFI_MASK) 135 #define DFS_DVPORTn_MFN_SET(VAL) (((VAL) << DFS_DVPORTn_MFN_SHIFT) & DFS_DVPORTn_MFN_MASK) 136 137 #endif /* S32CC_CLK_REGS_H */ 138