1 /* 2 * Copyright (c) 2023-2025, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLAT_DEF_H__ 8 #define __PLAT_DEF_H__ 9 10 #define MAJOR_VERSION (1) 11 #define MINOR_VERSION (0) 12 13 #define SIZE_K(n) ((n) * 1024) 14 15 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 16 #define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 17 18 #define GIC600_BASE 0xfd400000 19 #define GIC600_SIZE SIZE_K(64) 20 21 #define PMUSGRF_BASE 0xfdc00000 22 #define SYSSGRF_BASE 0xfdc10000 23 #define PMUGRF_BASE 0xfdc20000 24 #define CPUGRF_BASE 0xfdc30000 25 #define DDRGRF_BASE 0xfdc40000 26 #define PIPEGRF_BASE 0xfdc50000 27 #define GRF_BASE 0xfdc60000 28 #define PIPEPHY_GRF0 0xfdc70000 29 #define PIPEPHY_GRF1 0xfdc80000 30 #define PIPEPHY_GRF2 0xfdc90000 31 #define USBPHY_U3_GRF 0xfdca0000 32 #define USB2PHY_U2_GRF 0xfdca8000 33 #define EDPPHY_GRF 0xfdcb0000 34 #define SYSSRAM_BASE 0xfdcc0000 35 #define PCIE30PHY_GRF 0xfdcb8000 36 #define USBGRF_BASE 0xfdcf0000 37 38 #define PMUCRU_BASE 0xfdd00000 39 #define SCRU_BASE 0xfdd10000 40 #define SGRF_BASE 0xfdd18000 41 #define STIME_BASE 0xfdd1c000 42 #define CRU_BASE 0xfdd20000 43 #define PMUSCRU_BASE 0xfdd30000 44 #define I2C0_BASE 0xfdd40000 45 46 #define UART0_BASE 0xfdd50000 47 #define GPIO0_BASE 0xfdd60000 48 #define PMUPVTM_BASE 0xfdd80000 49 #define PMU_BASE 0xfdd90000 50 #define PMUSRAM_BASE 0xfdcd0000 51 #define PMUSRAM_SIZE SIZE_K(128) 52 #define PMUSRAM_RSIZE SIZE_K(8) 53 54 #define DDRSGRF_BASE 0xfe200000 55 #define OTP_NS_BASE 0xfe38c000 56 #define OTP_S_BASE 0xfe3a0000 57 #define UART1_BASE 0xfe650000 58 #define UART2_BASE 0xfe660000 59 #define GPIO1_BASE 0xfe740000 60 #define GPIO2_BASE 0xfe750000 61 #define GPIO3_BASE 0xfe760000 62 #define GPIO4_BASE 0xfe770000 63 64 #define OTP_PHY_BASE 0xfe880000 65 66 #define REMAP_BASE 0xffff0000 67 #define REMAP_SIZE SIZE_K(64) 68 /************************************************************************** 69 * UART related constants 70 **************************************************************************/ 71 #define FPGA_UART_BASE UART2_BASE 72 #define FPGA_BAUDRATE 1500000 73 #define FPGA_UART_CLOCK 24000000 74 75 /****************************************************************************** 76 * System counter frequency related constants 77 ******************************************************************************/ 78 #define SYS_COUNTER_FREQ_IN_TICKS 24000000 79 #define SYS_COUNTER_FREQ_IN_MHZ 24 80 81 /****************************************************************************** 82 * GIC-600 & interrupt handling related constants 83 ******************************************************************************/ 84 85 /* Base rk_platform compatible GIC memory map */ 86 #define PLAT_GICD_BASE GIC600_BASE 87 #define PLAT_GICC_BASE 0 88 #define PLAT_GICR_BASE (GIC600_BASE + 0x60000) 89 90 /****************************************************************************** 91 * sgi, ppi 92 ******************************************************************************/ 93 #define RK_IRQ_SEC_PHY_TIMER 29 94 95 #define RK_IRQ_SEC_SGI_0 8 96 #define RK_IRQ_SEC_SGI_1 9 97 #define RK_IRQ_SEC_SGI_2 10 98 #define RK_IRQ_SEC_SGI_3 11 99 #define RK_IRQ_SEC_SGI_4 12 100 #define RK_IRQ_SEC_SGI_5 13 101 #define RK_IRQ_SEC_SGI_6 14 102 #define RK_IRQ_SEC_SGI_7 15 103 104 /************************************************************************** 105 * share mem region allocation: 1M~2M 106 **************************************************************************/ 107 #define DDR_SHARE_MEM SIZE_K(1024) 108 #define DDR_SHARE_SIZE SIZE_K(64) 109 110 #define SHARE_MEM_BASE 0x100000/* [1MB, 1MB+60K] */ 111 #define SHARE_MEM_PAGE_NUM 15 112 #define SHARE_MEM_SIZE SIZE_K(SHARE_MEM_PAGE_NUM * 4) 113 114 #define SCMI_SHARE_MEM_BASE (SHARE_MEM_BASE + SHARE_MEM_SIZE) 115 #define SCMI_SHARE_MEM_SIZE SIZE_K(4) 116 117 #define SMT_BUFFER_BASE SCMI_SHARE_MEM_BASE 118 #define SMT_BUFFER0_BASE SMT_BUFFER_BASE 119 120 #endif /* __PLAT_DEF_H__ */ 121