1 /* SPDX-License-Identifier: BSD-2-Clause */
2 /*
3 * Copyright (c) 2015, Linaro Limited
4 * Copyright (c) 2023, Arm Limited
5 */
6 #ifndef __ARM64_H
7 #define __ARM64_H
8
9 #include <compiler.h>
10 #include <sys/cdefs.h>
11 #include <stdint.h>
12 #include <util.h>
13
14 #define SCTLR_M BIT64(0)
15 #define SCTLR_A BIT64(1)
16 #define SCTLR_C BIT64(2)
17 #define SCTLR_SA BIT64(3)
18 #define SCTLR_I BIT64(12)
19 #define SCTLR_ENDB BIT64(13)
20 #define SCTLR_WXN BIT64(19)
21 #define SCTLR_SPAN BIT64(23)
22 #define SCTLR_ENDA BIT64(27)
23 #define SCTLR_ENIB BIT64(30)
24 #define SCTLR_ENIA BIT64(31)
25 #define SCTLR_BT0 BIT64(35)
26 #define SCTLR_BT1 BIT64(36)
27 #define SCTLR_ITFSB BIT64(37)
28
29 #define SCTLR_TCF_MASK SHIFT_U64(0x3, 40)
30 #define SCTLR_TCF_NONE SHIFT_U64(0x0, 40)
31 #define SCTLR_TCF_SYNC SHIFT_U64(0x1, 40)
32 #define SCTLR_TCF_ASYNC SHIFT_U64(0x2, 40)
33 #define SCTLR_TCF_ASYMM SHIFT_U64(0x3, 40)
34
35 #define SCTLR_TCF0_MASK SHIFT_U64(0x3, 38)
36 #define SCTLR_TCF0_NONE SHIFT_U64(0x0, 38)
37 #define SCTLR_TCF0_SYNC SHIFT_U64(0x1, 38)
38 #define SCTLR_TCF0_ASYNC SHIFT_U64(0x2, 38)
39 #define SCTLR_TCF0_ASYMM SHIFT_U64(0x3, 38)
40
41 #define SCTLR_ATA0 BIT64(42)
42 #define SCTLR_ATA BIT64(43)
43
44 #define TTBR_ASID_MASK U(0xff)
45 #define TTBR_ASID_SHIFT U(48)
46
47 #define CLIDR_LOUIS_SHIFT U(21)
48 #define CLIDR_LOC_SHIFT U(24)
49 #define CLIDR_FIELD_WIDTH U(3)
50
51 #define CSSELR_LEVEL_SHIFT U(1)
52
53 #define DAIFBIT_FIQ BIT32(0)
54 #define DAIFBIT_IRQ BIT32(1)
55 #define DAIFBIT_ABT BIT32(2)
56 #define DAIFBIT_DBG BIT32(3)
57 #define DAIFBIT_ALL (DAIFBIT_FIQ | DAIFBIT_IRQ | \
58 DAIFBIT_ABT | DAIFBIT_DBG)
59
60 #if defined(CFG_CORE_IRQ_IS_NATIVE_INTR)
61 #define DAIFBIT_NATIVE_INTR DAIFBIT_IRQ
62 #define DAIFBIT_FOREIGN_INTR DAIFBIT_FIQ
63 #else
64 #define DAIFBIT_NATIVE_INTR DAIFBIT_FIQ
65 #define DAIFBIT_FOREIGN_INTR DAIFBIT_IRQ
66 #endif
67
68 #define DAIF_F_SHIFT U(6)
69 #define DAIF_F BIT32(6)
70 #define DAIF_I BIT32(7)
71 #define DAIF_A BIT32(8)
72 #define DAIF_D BIT32(9)
73 #define DAIF_AIF (DAIF_A | DAIF_I | DAIF_F)
74
75 #define SPSR_MODE_RW_SHIFT U(4)
76 #define SPSR_MODE_RW_MASK U(0x1)
77 #define SPSR_MODE_RW_64 U(0x0)
78 #define SPSR_MODE_RW_32 U(0x1)
79
80 #define SPSR_64_MODE_SP_SHIFT U(0)
81 #define SPSR_64_MODE_SP_MASK U(0x1)
82 #define SPSR_64_MODE_SP_EL0 U(0x0)
83 #define SPSR_64_MODE_SP_ELX U(0x1)
84
85 #define SPSR_64_MODE_EL_SHIFT U(2)
86 #define SPSR_64_MODE_EL_MASK U(0x3)
87 #define SPSR_64_MODE_EL1 U(0x1)
88 #define SPSR_64_MODE_EL0 U(0x0)
89
90 #define SPSR_64_DAIF_SHIFT U(6)
91 #define SPSR_64_DAIF_MASK U(0xf)
92
93 #define SPSR_64_PAN BIT64(22)
94
95 #define SPSR_32_AIF_SHIFT U(6)
96 #define SPSR_32_AIF_MASK U(0x7)
97
98 #define SPSR_32_E_SHIFT U(9)
99 #define SPSR_32_E_MASK U(0x1)
100 #define SPSR_32_E_LITTLE U(0x0)
101 #define SPSR_32_E_BIG U(0x1)
102
103 #define SPSR_32_T_SHIFT U(5)
104 #define SPSR_32_T_MASK U(0x1)
105 #define SPSR_32_T_ARM U(0x0)
106 #define SPSR_32_T_THUMB U(0x1)
107
108 #define SPSR_32_MODE_SHIFT U(0)
109 #define SPSR_32_MODE_MASK U(0xf)
110 #define SPSR_32_MODE_USR U(0x0)
111
112
113 #define SPSR_64(el, sp, daif) \
114 (SPSR_MODE_RW_64 << SPSR_MODE_RW_SHIFT | \
115 ((el) & SPSR_64_MODE_EL_MASK) << SPSR_64_MODE_EL_SHIFT | \
116 ((sp) & SPSR_64_MODE_SP_MASK) << SPSR_64_MODE_SP_SHIFT | \
117 ((daif) & SPSR_64_DAIF_MASK) << SPSR_64_DAIF_SHIFT)
118
119 #define SPSR_32(mode, isa, aif) \
120 (SPSR_MODE_RW_32 << SPSR_MODE_RW_SHIFT | \
121 SPSR_32_E_LITTLE << SPSR_32_E_SHIFT | \
122 ((mode) & SPSR_32_MODE_MASK) << SPSR_32_MODE_SHIFT | \
123 ((isa) & SPSR_32_T_MASK) << SPSR_32_T_SHIFT | \
124 ((aif) & SPSR_32_AIF_MASK) << SPSR_32_AIF_SHIFT)
125
126
127 #define TCR_T0SZ_SHIFT U(0)
128 #define TCR_EPD0 BIT64(7)
129 #define TCR_IRGN0_SHIFT U(8)
130 #define TCR_ORGN0_SHIFT U(10)
131 #define TCR_SH0_SHIFT U(12)
132 #define TCR_T1SZ_SHIFT U(16)
133 #define TCR_A1 BIT64(22)
134 #define TCR_EPD1 BIT64(23)
135 #define TCR_IRGN1_SHIFT U(24)
136 #define TCR_ORGN1_SHIFT U(26)
137 #define TCR_SH1_SHIFT U(28)
138 #define TCR_EL1_IPS_SHIFT U(32)
139 #define TCR_EL1_IPS_MASK UINT64_C(0x7)
140 #define TCR_TG1_4KB SHIFT_U64(2, 30)
141 #define TCR_RES1 BIT64(31)
142 #define TCR_TBI0 BIT64(37)
143 #define TCR_TBI1 BIT64(38)
144 #define TCR_TCMA0 BIT64(57)
145 #define TCR_TCMA1 BIT64(58)
146
147
148 /* Normal memory, Inner/Outer Non-cacheable */
149 #define TCR_XRGNX_NC U(0x0)
150 /* Normal memory, Inner/Outer Write-Back Write-Allocate Cacheable */
151 #define TCR_XRGNX_WB U(0x1)
152 /* Normal memory, Inner/Outer Write-Through Cacheable */
153 #define TCR_XRGNX_WT U(0x2)
154 /* Normal memory, Inner/Outer Write-Back no Write-Allocate Cacheable */
155 #define TCR_XRGNX_WBWA U(0x3)
156
157 /* Non-shareable */
158 #define TCR_SHX_NSH U(0x0)
159 /* Outer Shareable */
160 #define TCR_SHX_OSH U(0x2)
161 /* Inner Shareable */
162 #define TCR_SHX_ISH U(0x3)
163
164 #define ESR_EC_SHIFT U(26)
165 #define ESR_EC_MASK U(0x3f)
166
167 #define ESR_EC_UNKNOWN U(0x00)
168 #define ESR_EC_WFI U(0x01)
169 #define ESR_EC_AARCH32_CP15_32 U(0x03)
170 #define ESR_EC_AARCH32_CP15_64 U(0x04)
171 #define ESR_EC_AARCH32_CP14_MR U(0x05)
172 #define ESR_EC_AARCH32_CP14_LS U(0x06)
173 #define ESR_EC_FP_ASIMD U(0x07)
174 #define ESR_EC_AARCH32_CP10_ID U(0x08)
175 #define ESR_EC_PAUTH U(0x09)
176 #define ESR_EC_AARCH32_CP14_64 U(0x0c)
177 #define ESR_EC_BTI U(0x0d)
178 #define ESR_EC_ILLEGAL U(0x0e)
179 #define ESR_EC_AARCH32_SVC U(0x11)
180 #define ESR_EC_AARCH64_SVC U(0x15)
181 #define ESR_EC_AARCH64_SYS U(0x18)
182 #define ESR_EC_ERET U(0x1a)
183 #define ESR_EC_FPAC U(0x1c)
184 #define ESR_EC_IABT_EL0 U(0x20)
185 #define ESR_EC_IABT_EL1 U(0x21)
186 #define ESR_EC_PC_ALIGN U(0x22)
187 #define ESR_EC_DABT_EL0 U(0x24)
188 #define ESR_EC_DABT_EL1 U(0x25)
189 #define ESR_EC_SP_ALIGN U(0x26)
190 #define ESR_EC_AARCH32_FP U(0x28)
191 #define ESR_EC_AARCH64_FP U(0x2c)
192 #define ESR_EC_SERROR U(0x2f)
193 #define ESR_EC_BREAKPT_EL0 U(0x30)
194 #define ESR_EC_BREAKPT_EL1 U(0x31)
195 #define ESR_EC_SOFTSTP_EL0 U(0x32)
196 #define ESR_EC_SOFTSTP_EL1 U(0x33)
197 #define ESR_EC_WATCHPT_EL0 U(0x34)
198 #define ESR_EC_WATCHPT_EL1 U(0x35)
199 #define ESR_EC_AARCH32_BKPT U(0x38)
200 #define ESR_EC_AARCH64_BRK U(0x3c)
201
202 /* Combined defines for DFSC and IFSC */
203 #define ESR_FSC_MASK U(0x3f)
204 #define ESR_FSC_SIZE_L0 U(0x00)
205 #define ESR_FSC_SIZE_L1 U(0x01)
206 #define ESR_FSC_SIZE_L2 U(0x02)
207 #define ESR_FSC_SIZE_L3 U(0x03)
208 #define ESR_FSC_TRANS_L0 U(0x04)
209 #define ESR_FSC_TRANS_L1 U(0x05)
210 #define ESR_FSC_TRANS_L2 U(0x06)
211 #define ESR_FSC_TRANS_L3 U(0x07)
212 #define ESR_FSC_ACCF_L1 U(0x09)
213 #define ESR_FSC_ACCF_L2 U(0x0a)
214 #define ESR_FSC_ACCF_L3 U(0x0b)
215 #define ESR_FSC_PERMF_L1 U(0x0d)
216 #define ESR_FSC_PERMF_L2 U(0x0e)
217 #define ESR_FSC_PERMF_L3 U(0x0f)
218 #define ESR_FSC_SEA_NTT U(0x10)
219 #define ESR_FSC_TAG_CHECK U(0x11)
220 #define ESR_FSC_SEA_TT_SUB_L2 U(0x12)
221 #define ESR_FSC_SEA_TT_SUB_L1 U(0x13)
222 #define ESR_FSC_SEA_TT_L0 U(0x14)
223 #define ESR_FSC_SEA_TT_L1 U(0x15)
224 #define ESR_FSC_SEA_TT_L2 U(0x16)
225 #define ESR_FSC_SEA_TT_L3 U(0x17)
226 #define ESR_FSC_ALIGN U(0x21)
227
228 /* WnR for DABT and RES0 for IABT */
229 #define ESR_ABT_WNR BIT32(6)
230
231 #define CPACR_EL1_FPEN_SHIFT U(20)
232 #define CPACR_EL1_FPEN_MASK U(0x3)
233 #define CPACR_EL1_FPEN_NONE U(0x0)
234 #define CPACR_EL1_FPEN_EL1 U(0x1)
235 #define CPACR_EL1_FPEN_EL0EL1 U(0x3)
236 #define CPACR_EL1_FPEN(x) ((x) >> CPACR_EL1_FPEN_SHIFT \
237 & CPACR_EL1_FPEN_MASK)
238
239
240 #define PAR_F BIT32(0)
241 #define PAR_PA_SHIFT U(12)
242 #define PAR_PA_MASK (BIT64(36) - 1)
243
244 #define TLBI_VA_SHIFT U(12)
245 #define TLBI_ASID_SHIFT U(48)
246 #define TLBI_ASID_MASK U(0xff)
247
248 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf)
249 #define FEAT_BTI_IMPLEMENTED ULL(0x1)
250
251 #define ID_AA64PFR1_EL1_MTE_MASK UL(0xf)
252 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8)
253 #define FEAT_MTE_NOT_IMPLEMENTED U(0x0)
254 #define FEAT_MTE_IMPLEMENTED U(0x1)
255 #define FEAT_MTE2_IMPLEMENTED U(0x2)
256 #define FEAT_MTE3_IMPLEMENTED U(0x3)
257
258 #define ID_AA64MMFR0_EL1_PARANGE_MASK UL(0xf)
259
260 #define ID_AA64MMFR1_EL1_PAN_MASK UL(0xf)
261 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20)
262 #define FEAT_PAN_NOT_IMPLEMENTED U(0x0)
263 #define FEAT_PAN_IMPLEMENTED U(0x1)
264 #define FEAT_PAN2_IMPLEMENTED U(0x2)
265 #define FEAT_PAN3_IMPLEMENTED U(0x3)
266
267 #define ID_AA64ISAR1_GPI_SHIFT U(28)
268 #define ID_AA64ISAR1_GPI_MASK U(0xf)
269 #define ID_AA64ISAR1_GPI_NI U(0x0)
270 #define ID_AA64ISAR1_GPI_IMP_DEF U(0x1)
271
272 #define ID_AA64ISAR1_GPA_SHIFT U(24)
273 #define ID_AA64ISAR1_GPA_MASK U(0xf)
274 #define ID_AA64ISAR1_GPA_NI U(0x0)
275 #define ID_AA64ISAR1_GPA_ARCHITECTED U(0x1)
276
277 #define ID_AA64ISAR1_API_SHIFT U(8)
278 #define ID_AA64ISAR1_API_MASK U(0xf)
279 #define ID_AA64ISAR1_API_NI U(0x0)
280 #define ID_AA64ISAR1_API_IMP_DEF U(0x1)
281 #define ID_AA64ISAR1_API_IMP_DEF_EPAC U(0x2)
282 #define ID_AA64ISAR1_API_IMP_DEF_EPAC2 U(0x3)
283 #define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC U(0x4)
284 #define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC_CMB U(0x5)
285
286 #define ID_AA64ISAR1_APA_SHIFT U(4)
287 #define ID_AA64ISAR1_APA_MASK U(0xf)
288 #define ID_AA64ISAR1_APA_NI U(0x0)
289 #define ID_AA64ISAR1_APA_ARCHITECTED U(0x1)
290 #define ID_AA64ISAR1_APA_ARCH_EPAC U(0x2)
291 #define ID_AA64ISAR1_APA_ARCH_EPAC2 U(0x3)
292 #define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC U(0x4)
293 #define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC_CMB U(0x5)
294
295 #define ID_AA64ISAR2_APA3_SHIFT U(12)
296 #define ID_AA64ISAR2_APA3_MASK U(0xf)
297 #define ID_AA64ISAR2_APA3_NI U(0x0)
298 #define ID_AA64ISAR2_APA3_PAUTH U(0x1)
299 #define ID_AA64ISAR2_APA3_EPAC U(0x2)
300 #define ID_AA64ISAR2_APA3_PAUTH2 U(0x3)
301 #define ID_AA64ISAR2_APA3_FPAC U(0x4)
302 #define ID_AA64ISAR2_APA3_FPAC_CMB U(0x5)
303 #define ID_AA64ISAR2_APA3_PAUTH_LR U(0x6)
304
305 #define ID_AA64ISAR2_GPA3_SHIFT U(8)
306 #define ID_AA64ISAR2_GPA3_MASK U(0xf)
307 #define ID_AA64ISAR2_GPA3_NI U(0x0)
308 #define ID_AA64ISAR2_GPA3_IMPLEMENTED U(0x1)
309
310 #define ID_MMFR3_EL1_PAN_SHIFT U(16)
311
312 #define GCR_EL1_RRND BIT64(16)
313
314 /* ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0 */
315 #define ID_AA64ISAR0_AES GENMASK_64(7, 4)
316 #define ID_AA64ISAR0_SHA1 GENMASK_64(11, 8)
317 #define ID_AA64ISAR0_SHA2 GENMASK_64(15, 12)
318 #define ID_AA64ISAR0_CRC32 GENMASK_64(19, 16)
319 #define ID_AA64ISAR0_ATOMIC GENMASK_64(23, 20)
320 #define ID_AA64ISAR0_TME GENMASK_64(27, 24)
321 #define ID_AA64ISAR0_RDM GENMASK_64(31, 28)
322 #define ID_AA64ISAR0_SHA3 GENMASK_64(35, 32)
323 #define ID_AA64ISAR0_SM3 GENMASK_64(39, 36)
324 #define ID_AA64ISAR0_SM4 GENMASK_64(43, 40)
325
326 #define ID_AA64ISAR0_SHA2_SHIFT U(12)
327 #define ID_AA64ISAR0_SHA2_FEAT_SHA256 U(1)
328 #define ID_AA64ISAR0_SHA2_FEAT_SHA512 U(2)
329
330 #ifndef __ASSEMBLER__
isb(void)331 static inline __noprof void isb(void)
332 {
333 asm volatile ("isb" : : : "memory");
334 }
335
dsb(void)336 static inline __noprof void dsb(void)
337 {
338 asm volatile ("dsb sy" : : : "memory");
339 }
340
dsb_ish(void)341 static inline __noprof void dsb_ish(void)
342 {
343 asm volatile ("dsb ish" : : : "memory");
344 }
345
dsb_ishst(void)346 static inline __noprof void dsb_ishst(void)
347 {
348 asm volatile ("dsb ishst" : : : "memory");
349 }
350
dsb_osh(void)351 static inline __noprof void dsb_osh(void)
352 {
353 asm volatile ("dsb osh" : : : "memory");
354 }
355
sev(void)356 static inline __noprof void sev(void)
357 {
358 asm volatile ("sev" : : : "memory");
359 }
360
wfe(void)361 static inline __noprof void wfe(void)
362 {
363 asm volatile ("wfe" : : : "memory");
364 }
365
wfi(void)366 static inline __noprof void wfi(void)
367 {
368 asm volatile ("wfi" : : : "memory");
369 }
370
write_at_s1e1r(uint64_t va)371 static inline __noprof void write_at_s1e1r(uint64_t va)
372 {
373 asm volatile ("at S1E1R, %0" : : "r" (va));
374 }
375
read_pc(void)376 static __always_inline __noprof uint64_t read_pc(void)
377 {
378 uint64_t val;
379
380 asm volatile ("adr %0, ." : "=r" (val));
381 return val;
382 }
383
read_fp(void)384 static __always_inline __noprof uint64_t read_fp(void)
385 {
386 uint64_t val;
387
388 asm volatile ("mov %0, x29" : "=r" (val));
389 return val;
390 }
391
read_pmu_ccnt(void)392 static inline __noprof uint64_t read_pmu_ccnt(void)
393 {
394 uint64_t val;
395
396 asm volatile("mrs %0, PMCCNTR_EL0" : "=r"(val));
397 return val;
398 }
399
tlbi_vaae1is(uint64_t va)400 static inline __noprof void tlbi_vaae1is(uint64_t va)
401 {
402 asm volatile ("tlbi vaae1is, %0" : : "r" (va));
403 }
404
tlbi_vale1is(uint64_t va)405 static inline __noprof void tlbi_vale1is(uint64_t va)
406 {
407 asm volatile ("tlbi vale1is, %0" : : "r" (va));
408 }
409
write_64bit_pair(uint64_t dst,uint64_t hi,uint64_t lo)410 static inline void write_64bit_pair(uint64_t dst, uint64_t hi, uint64_t lo)
411 {
412 /* 128bits should be written to hardware at one time */
413 asm volatile ("stp %1, %0, [%2]" : :
414 "r" (hi), "r" (lo), "r" (dst) : "memory");
415 }
416
read_64bit_pair(uint64_t src,uint64_t * hi,uint64_t * lo)417 static inline void read_64bit_pair(uint64_t src, uint64_t *hi, uint64_t *lo)
418 {
419 uint64_t tmp0 = 0;
420 uint64_t tmp1 = 0;
421
422 /* 128bits should be read from hardware at one time */
423 asm volatile ("ldp %0, %1, [%2]\n" : "=&r"(tmp0), "=&r"(tmp1) :
424 "r"(src) : "memory");
425
426 *lo = tmp0;
427 *hi = tmp1;
428 }
429
430 /*
431 * Templates for register read/write functions based on mrs/msr
432 */
433
434 #define DEFINE_REG_READ_FUNC_(reg, type, asmreg) \
435 static inline __noprof type read_##reg(void) \
436 { \
437 uint64_t val64 = 0; \
438 \
439 asm volatile("mrs %0, " #asmreg : "=r" (val64)); \
440 return val64; \
441 }
442
443 #define DEFINE_REG_WRITE_FUNC_(reg, type, asmreg) \
444 static inline __noprof void write_##reg(type val) \
445 { \
446 uint64_t val64 = val; \
447 \
448 asm volatile("msr " #asmreg ", %0" : : "r" (val64)); \
449 }
450
451 #define DEFINE_U32_REG_READ_FUNC(reg) \
452 DEFINE_REG_READ_FUNC_(reg, uint32_t, reg)
453
454 #define DEFINE_U32_REG_WRITE_FUNC(reg) \
455 DEFINE_REG_WRITE_FUNC_(reg, uint32_t, reg)
456
457 #define DEFINE_U32_REG_READWRITE_FUNCS(reg) \
458 DEFINE_U32_REG_READ_FUNC(reg) \
459 DEFINE_U32_REG_WRITE_FUNC(reg)
460
461 #define DEFINE_U64_REG_READ_FUNC(reg) \
462 DEFINE_REG_READ_FUNC_(reg, uint64_t, reg)
463
464 #define DEFINE_U64_REG_WRITE_FUNC(reg) \
465 DEFINE_REG_WRITE_FUNC_(reg, uint64_t, reg)
466
467 #define DEFINE_U64_REG_READWRITE_FUNCS(reg) \
468 DEFINE_U64_REG_READ_FUNC(reg) \
469 DEFINE_U64_REG_WRITE_FUNC(reg)
470
471 /*
472 * Define register access functions
473 */
474
475 DEFINE_U32_REG_READWRITE_FUNCS(cpacr_el1)
DEFINE_U32_REG_READWRITE_FUNCS(daif)476 DEFINE_U32_REG_READWRITE_FUNCS(daif)
477 #ifdef __clang__
478 DEFINE_REG_READ_FUNC_(fpcr, uint32_t, S3_3_c4_c4_0)
479 DEFINE_REG_WRITE_FUNC_(fpcr, uint32_t, S3_3_c4_c4_0)
480 DEFINE_REG_READ_FUNC_(fpsr, uint32_t, S3_3_c4_c4_1)
481 DEFINE_REG_WRITE_FUNC_(fpsr, uint32_t, S3_3_c4_c4_1)
482 #else
483 DEFINE_U32_REG_READWRITE_FUNCS(fpcr)
484 DEFINE_U32_REG_READWRITE_FUNCS(fpsr)
485 #endif
486
487 DEFINE_U32_REG_READ_FUNC(ctr_el0)
488 #define read_ctr() read_ctr_el0()
489 DEFINE_U32_REG_READ_FUNC(contextidr_el1)
490 DEFINE_U64_REG_READ_FUNC(sctlr_el1)
491
492 /* ARM Generic timer functions */
493 DEFINE_REG_READ_FUNC_(cntfrq, uint32_t, cntfrq_el0)
494 DEFINE_REG_READ_FUNC_(cntvct, uint64_t, cntvct_el0)
495 DEFINE_REG_READ_FUNC_(cntpct, uint64_t, cntpct_el0)
496 DEFINE_REG_READ_FUNC_(cntp_ctl, uint32_t, cntp_ctl_el0)
497 DEFINE_REG_WRITE_FUNC_(cntp_ctl, uint32_t, cntp_ctl_el0)
498 DEFINE_REG_READ_FUNC_(cntp_tval, uint32_t, cntp_tval_el0)
499 DEFINE_REG_WRITE_FUNC_(cntp_tval, uint32_t, cntp_tval_el0)
500 DEFINE_REG_READ_FUNC_(cntp_cval, uint64_t, cntp_cval_el0)
501 DEFINE_REG_WRITE_FUNC_(cntp_cval, uint64_t, cntp_cval_el0)
502 DEFINE_REG_READ_FUNC_(cntkctl, uint32_t, cntkctl_el1)
503 DEFINE_REG_WRITE_FUNC_(cntkctl, uint32_t, cntkctl_el1)
504 DEFINE_REG_READ_FUNC_(cntps_ctl, uint32_t, cntps_ctl_el1)
505 DEFINE_REG_WRITE_FUNC_(cntps_ctl, uint32_t, cntps_ctl_el1)
506 DEFINE_REG_READ_FUNC_(cntps_tval, uint32_t, cntps_tval_el1)
507 DEFINE_REG_WRITE_FUNC_(cntps_tval, uint32_t, cntps_tval_el1)
508 DEFINE_REG_READ_FUNC_(cntps_cval, uint64_t, cntps_cval_el1)
509 DEFINE_REG_WRITE_FUNC_(cntps_cval, uint64_t, cntps_cval_el1)
510
511 DEFINE_REG_READ_FUNC_(pmccntr, uint64_t, pmccntr_el0)
512
513 DEFINE_U64_REG_READWRITE_FUNCS(ttbr0_el1)
514 DEFINE_U64_REG_READWRITE_FUNCS(ttbr1_el1)
515 DEFINE_U64_REG_READWRITE_FUNCS(tcr_el1)
516
517 DEFINE_U64_REG_READ_FUNC(esr_el1)
518 DEFINE_U64_REG_READ_FUNC(far_el1)
519 DEFINE_U64_REG_READ_FUNC(mpidr_el1)
520 /* Alias for reading this register to avoid ifdefs in code */
521 #define read_mpidr() read_mpidr_el1()
522 DEFINE_U64_REG_READ_FUNC(midr_el1)
523 /* Alias for reading this register to avoid ifdefs in code */
524 #define read_midr() read_midr_el1()
525 DEFINE_U64_REG_READ_FUNC(par_el1)
526
527 DEFINE_U64_REG_WRITE_FUNC(mair_el1)
528
529 DEFINE_U64_REG_READ_FUNC(id_aa64mmfr0_el1)
530 DEFINE_U64_REG_READ_FUNC(id_aa64mmfr1_el1)
531 DEFINE_U64_REG_READ_FUNC(id_aa64pfr1_el1)
532 DEFINE_U64_REG_READ_FUNC(id_aa64isar0_el1)
533 DEFINE_U64_REG_READ_FUNC(id_aa64isar1_el1)
534 DEFINE_U64_REG_READ_FUNC(id_aa64isar2_el1)
535 DEFINE_REG_READ_FUNC_(apiakeylo, uint64_t, S3_0_c2_c1_0)
536 DEFINE_REG_READ_FUNC_(apiakeyhi, uint64_t, S3_0_c2_c1_1)
537
538 DEFINE_REG_WRITE_FUNC_(apibkeylo, uint64_t, S3_0_c2_c1_2)
539 DEFINE_REG_WRITE_FUNC_(apibkeyhi, uint64_t, S3_0_c2_c1_3)
540
541 DEFINE_REG_READ_FUNC_(apdakeylo, uint64_t, S3_0_c2_c2_0)
542 DEFINE_REG_READ_FUNC_(apdakeyhi, uint64_t, S3_0_c2_c2_1)
543
544 DEFINE_REG_WRITE_FUNC_(apdbkeylo, uint64_t, S3_0_c2_c2_2)
545 DEFINE_REG_WRITE_FUNC_(apdbkeyhi, uint64_t, S3_0_c2_c2_3)
546
547 DEFINE_REG_WRITE_FUNC_(apgakeylo, uint64_t, S3_0_c2_c3_0)
548 DEFINE_REG_WRITE_FUNC_(apgakeyhi, uint64_t, S3_0_c2_c3_1)
549
550 /* Register read/write functions for GICC registers by using system interface */
551 DEFINE_REG_READ_FUNC_(icc_ctlr, uint32_t, S3_0_C12_C12_4)
552 DEFINE_REG_WRITE_FUNC_(icc_ctlr, uint32_t, S3_0_C12_C12_4)
553 DEFINE_REG_WRITE_FUNC_(icc_pmr, uint32_t, S3_0_C4_C6_0)
554 DEFINE_REG_READ_FUNC_(icc_iar0, uint32_t, S3_0_c12_c8_0)
555 DEFINE_REG_READ_FUNC_(icc_iar1, uint32_t, S3_0_c12_c12_0)
556 DEFINE_REG_WRITE_FUNC_(icc_eoir0, uint32_t, S3_0_c12_c8_1)
557 DEFINE_REG_WRITE_FUNC_(icc_eoir1, uint32_t, S3_0_c12_c12_1)
558 DEFINE_REG_WRITE_FUNC_(icc_igrpen0, uint32_t, S3_0_C12_C12_6)
559 DEFINE_REG_WRITE_FUNC_(icc_igrpen1, uint32_t, S3_0_C12_C12_7)
560 DEFINE_REG_WRITE_FUNC_(icc_sgi1r, uint64_t, S3_0_C12_C11_5)
561 DEFINE_REG_WRITE_FUNC_(icc_asgi1r, uint64_t, S3_0_C12_C11_6)
562
563 DEFINE_REG_WRITE_FUNC_(pan, uint64_t, S3_0_c4_c2_3)
564 DEFINE_REG_READ_FUNC_(pan, uint64_t, S3_0_c4_c2_3)
565
566 static inline void write_pan_enable(void)
567 {
568 /* msr pan, #1 */
569 asm volatile("msr S0_0_c4_c1_4, xzr" ::: "memory" );
570 }
571
write_pan_disable(void)572 static inline void write_pan_disable(void)
573 {
574 /* msr pan, #0 */
575 asm volatile("msr S0_0_c4_c0_4, xzr" ::: "memory" );
576 }
577
578 #endif /*__ASSEMBLER__*/
579
580 #endif /*__ARM64_H*/
581
582