1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MT_SPM_VCOREFS_REG_6991_H 8 #define MT_SPM_VCOREFS_REG_6991_H 9 10 #include <platform_def.h> 11 12 /************************************************************************* 13 * DVFSRC related constants 14 *************************************************************************/ 15 #define DVFSRC_BASE (IO_PHYS + 0x0C013000) 16 #define EFUSEC_BASE (IO_PHYS + 0x03260000) 17 #define EFUSE_SIZE (0x1000) 18 #define DVFSRC_REG_SIZE (0x1000) 19 #define DVFSRC_BASIC_CONTROL (DVFSRC_BASE + 0x0) 20 #define DVFSRC_BASIC_CONTROL_4 (DVFSRC_BASE + 0xC) 21 #define DVFSRC_SW_REQ1 (DVFSRC_BASE + 0x10) 22 #define DVFSRC_SW_REQ2 (DVFSRC_BASE + 0x14) 23 #define DVFSRC_SW_REQ3 (DVFSRC_BASE + 0x18) 24 #define DVFSRC_SW_REQ4 (DVFSRC_BASE + 0x1C) 25 #define DVFSRC_SW_REQ5 (DVFSRC_BASE + 0x20) 26 #define DVFSRC_SW_REQ6 (DVFSRC_BASE + 0x24) 27 #define DVFSRC_SW_REQ7 (DVFSRC_BASE + 0x28) 28 #define DVFSRC_SW_REQ8 (DVFSRC_BASE + 0x2C) 29 #define DVFSRC_EMI_REQUEST (DVFSRC_BASE + 0x30) 30 #define DVFSRC_EMI_REQUEST3 (DVFSRC_BASE + 0x38) 31 #define DVFSRC_EMI_REQUEST5 (DVFSRC_BASE + 0x40) 32 #define DVFSRC_EMI_QOS0 (DVFSRC_BASE + 0x4C) 33 #define DVFSRC_EMI_QOS1 (DVFSRC_BASE + 0x50) 34 #define DVFSRC_EMI_QOS2 (DVFSRC_BASE + 0x54) 35 #define DVFSRC_EMI_QOS3 (DVFSRC_BASE + 0x58) 36 #define DVFSRC_EMI_QOS4 (DVFSRC_BASE + 0x5C) 37 #define DVFSRC_EMI_QOS5 (DVFSRC_BASE + 0x60) 38 #define DVFSRC_EMI_QOS6 (DVFSRC_BASE + 0x64) 39 #define DVFSRC_VCORE_REQUEST (DVFSRC_BASE + 0x80) 40 #define DVFSRC_VCORE_REQUEST3 (DVFSRC_BASE + 0x88) 41 #define DVFSRC_VCORE_QOS0 (DVFSRC_BASE + 0x94) 42 #define DVFSRC_VCORE_QOS1 (DVFSRC_BASE + 0x98) 43 #define DVFSRC_VCORE_QOS2 (DVFSRC_BASE + 0x9C) 44 #define DVFSRC_VCORE_QOS3 (DVFSRC_BASE + 0xA0) 45 #define DVFSRC_VCORE_QOS4 (DVFSRC_BASE + 0xA4) 46 #define DVFSRC_HALT_SW_CONTROL (DVFSRC_BASE + 0xC4) 47 #define DVFSRC_INT (DVFSRC_BASE + 0xC8) 48 #define DVFSRC_INT_EN (DVFSRC_BASE + 0xCC) 49 #define DVFSRC_INT_CLR (DVFSRC_BASE + 0xD0) 50 #define DVFSRC_BW_MON_WINDOW (DVFSRC_BASE + 0xD4) 51 #define DVFSRC_BW_MON_THRES_1 (DVFSRC_BASE + 0xD8) 52 #define DVFSRC_BW_MON_THRES_2 (DVFSRC_BASE + 0xDC) 53 #define DVFSRC_MD_TURBO (DVFSRC_BASE + 0xE0) 54 #define DVFSRC_PCIE_VCORE_REQ (DVFSRC_BASE + 0xE4) 55 #define DVFSRC_VCORE_USER_REQ (DVFSRC_BASE + 0xE8) 56 #define DVFSRC_BW_USER_REQ (DVFSRC_BASE + 0xEC) 57 #define DVFSRC_TIMEOUT_NEXTREQ (DVFSRC_BASE + 0xF8) 58 #define DVFSRC_LEVEL_LABEL_0_1 (DVFSRC_BASE + 0xFC) 59 #define DVFSRC_LEVEL_LABEL_2_3 (DVFSRC_BASE + 0x100) 60 #define DVFSRC_LEVEL_LABEL_4_5 (DVFSRC_BASE + 0x104) 61 #define DVFSRC_LEVEL_LABEL_6_7 (DVFSRC_BASE + 0x108) 62 #define DVFSRC_LEVEL_LABEL_8_9 (DVFSRC_BASE + 0x10C) 63 #define DVFSRC_LEVEL_LABEL_10_11 (DVFSRC_BASE + 0x110) 64 #define DVFSRC_LEVEL_LABEL_12_13 (DVFSRC_BASE + 0x114) 65 #define DVFSRC_LEVEL_LABEL_14_15 (DVFSRC_BASE + 0x118) 66 #define DVFSRC_LEVEL_LABEL_16_17 (DVFSRC_BASE + 0x11C) 67 #define DVFSRC_LEVEL_LABEL_18_19 (DVFSRC_BASE + 0x120) 68 #define DVFSRC_LEVEL_LABEL_20_21 (DVFSRC_BASE + 0x124) 69 #define DVFSRC_LEVEL_LABEL_22_23 (DVFSRC_BASE + 0x128) 70 #define DVFSRC_LEVEL_LABEL_24_25 (DVFSRC_BASE + 0x12C) 71 #define DVFSRC_LEVEL_LABEL_26_27 (DVFSRC_BASE + 0x130) 72 #define DVFSRC_LEVEL_LABEL_28_29 (DVFSRC_BASE + 0x134) 73 #define DVFSRC_LEVEL_LABEL_30_31 (DVFSRC_BASE + 0x138) 74 #define DVFSRC_LEVEL_LABEL_32_33 (DVFSRC_BASE + 0x13C) 75 #define DVFSRC_LEVEL_LABEL_34_35 (DVFSRC_BASE + 0x140) 76 #define DVFSRC_LEVEL_LABEL_36_37 (DVFSRC_BASE + 0x144) 77 #define DVFSRC_LEVEL_LABEL_38_39 (DVFSRC_BASE + 0x148) 78 #define DVFSRC_LEVEL_LABEL_40_41 (DVFSRC_BASE + 0x14C) 79 #define DVFSRC_LEVEL_LABEL_42_43 (DVFSRC_BASE + 0x150) 80 #define DVFSRC_LEVEL_LABEL_44_45 (DVFSRC_BASE + 0x154) 81 #define DVFSRC_LEVEL_LABEL_46_47 (DVFSRC_BASE + 0x158) 82 #define DVFSRC_LEVEL_LABEL_48_49 (DVFSRC_BASE + 0x15C) 83 #define DVFSRC_LEVEL_LABEL_50_51 (DVFSRC_BASE + 0x160) 84 #define DVFSRC_LEVEL_LABEL_52_53 (DVFSRC_BASE + 0x164) 85 #define DVFSRC_LEVEL_LABEL_54_55 (DVFSRC_BASE + 0x168) 86 #define DVFSRC_LEVEL_LABEL_56_57 (DVFSRC_BASE + 0x16C) 87 #define DVFSRC_LEVEL_LABEL_58_59 (DVFSRC_BASE + 0x170) 88 #define DVFSRC_LEVEL_LABEL_60_61 (DVFSRC_BASE + 0x174) 89 #define DVFSRC_LEVEL_LABEL_62_63 (DVFSRC_BASE + 0x178) 90 #define DVFSRC_SW_BW_0 (DVFSRC_BASE + 0x1DC) 91 #define DVFSRC_SW_BW_1 (DVFSRC_BASE + 0x1E0) 92 #define DVFSRC_SW_BW_2 (DVFSRC_BASE + 0x1E4) 93 #define DVFSRC_SW_BW_3 (DVFSRC_BASE + 0x1E8) 94 #define DVFSRC_SW_BW_4 (DVFSRC_BASE + 0x1EC) 95 #define DVFSRC_SW_BW_5 (DVFSRC_BASE + 0x1F0) 96 #define DVFSRC_SW_BW_6 (DVFSRC_BASE + 0x1F4) 97 #define DVFSRC_SW_BW_7 (DVFSRC_BASE + 0x1F8) 98 #define DVFSRC_SW_BW_8 (DVFSRC_BASE + 0x1FC) 99 #define DVFSRC_SW_BW_9 (DVFSRC_BASE + 0x200) 100 #define DVFSRC_QOS_EN (DVFSRC_BASE + 0x204) 101 #define DVFSRC_ISP_HRT (DVFSRC_BASE + 0x20C) 102 #define DVFSRC_HRT_BW_BASE (DVFSRC_BASE + 0x210) 103 #define DVFSRC_SEC_SW_REQ (DVFSRC_BASE + 0x214) 104 #define DVFSRC_EMI_MON_DEBOUNCE_TIME (DVFSRC_BASE + 0x218) 105 #define DVFSRC_MD_LATENCY_IMPROVE (DVFSRC_BASE + 0x21C) 106 #define DVFSRC_DEBOUNCE_TIME (DVFSRC_BASE + 0x220) 107 #define DVFSRC_LEVEL_MASK_MD_1 (DVFSRC_BASE + 0x224) 108 #define DVFSRC_LEVEL_MASK_MD_2 (DVFSRC_BASE + 0x228) 109 #define DVFSRC_DEFAULT_OPP_1 (DVFSRC_BASE + 0x22C) 110 #define DVFSRC_DEFAULT_OPP_2 (DVFSRC_BASE + 0x230) 111 #define DVFSRC_95MD_SCEN_EMI0 (DVFSRC_BASE + 0x234) 112 #define DVFSRC_95MD_SCEN_EMI1 (DVFSRC_BASE + 0x238) 113 #define DVFSRC_95MD_SCEN_EMI2 (DVFSRC_BASE + 0x23C) 114 #define DVFSRC_95MD_SCEN_EMI3 (DVFSRC_BASE + 0x240) 115 #define DVFSRC_95MD_SCEN_EMI0_T (DVFSRC_BASE + 0x244) 116 #define DVFSRC_95MD_SCEN_EMI1_T (DVFSRC_BASE + 0x248) 117 #define DVFSRC_95MD_SCEN_EMI2_T (DVFSRC_BASE + 0x24C) 118 #define DVFSRC_95MD_SCEN_EMI3_T (DVFSRC_BASE + 0x250) 119 #define DVFSRC_95MD_SCEN_EMIU (DVFSRC_BASE + 0x254) 120 #define DVFSRC_95MD_SCEN_BW0 (DVFSRC_BASE + 0x258) 121 #define DVFSRC_95MD_SCEN_BW1 (DVFSRC_BASE + 0x25C) 122 #define DVFSRC_95MD_SCEN_BW2 (DVFSRC_BASE + 0x260) 123 #define DVFSRC_95MD_SCEN_BW3 (DVFSRC_BASE + 0x264) 124 #define DVFSRC_95MD_SCEN_BW0_T (DVFSRC_BASE + 0x268) 125 #define DVFSRC_95MD_SCEN_BW1_T (DVFSRC_BASE + 0x26C) 126 #define DVFSRC_95MD_SCEN_BW2_T (DVFSRC_BASE + 0x270) 127 #define DVFSRC_95MD_SCEN_BW3_T (DVFSRC_BASE + 0x274) 128 #define DVFSRC_95MD_SCEN_BWU (DVFSRC_BASE + 0x278) 129 #define DVFSRC_MD_LEVEL_SW_REG (DVFSRC_BASE + 0x27C) 130 #define DVFSRC_RSRV_0 (DVFSRC_BASE + 0x280) 131 #define DVFSRC_RSRV_1 (DVFSRC_BASE + 0x284) 132 #define DVFSRC_RSRV_2 (DVFSRC_BASE + 0x288) 133 #define DVFSRC_RSRV_3 (DVFSRC_BASE + 0x28C) 134 #define DVFSRC_RSRV_4 (DVFSRC_BASE + 0x290) 135 #define DVFSRC_RSRV_5 (DVFSRC_BASE + 0x294) 136 #define DVFSRC_SPM_RESEND (DVFSRC_BASE + 0x298) 137 #define DVFSRC_DEBUG_STA_0 (DVFSRC_BASE + 0x29C) 138 #define DVFSRC_DEBUG_STA_1 (DVFSRC_BASE + 0x2A0) 139 #define DVFSRC_DEBUG_STA_2 (DVFSRC_BASE + 0x2A4) 140 #define DVFSRC_DEBUG_STA_3 (DVFSRC_BASE + 0x2A8) 141 #define DVFSRC_DEBUG_STA_4 (DVFSRC_BASE + 0x2AC) 142 #define DVFSRC_DEBUG_STA_5 (DVFSRC_BASE + 0x2B0) 143 #define DVFSRC_DEBUG_STA_6 (DVFSRC_BASE + 0x2B4) 144 #define DVFSRC_DEBUG_STA_8 (DVFSRC_BASE + 0x2BC) 145 #define DVFSRC_DEBUG_STA_9 (DVFSRC_BASE + 0x2C0) 146 #define DVFSRC_DEBUG_STA_10 (DVFSRC_BASE + 0x2C4) 147 #define DVFSRC_DDR_REQUEST (DVFSRC_BASE + 0x2C8) 148 #define DVFSRC_DDR_REQUEST3 (DVFSRC_BASE + 0x2D0) 149 #define DVFSRC_DDR_REQUEST5 (DVFSRC_BASE + 0x2D8) 150 #define DVFSRC_DDR_QOS0 (DVFSRC_BASE + 0x2E8) 151 #define DVFSRC_DDR_QOS1 (DVFSRC_BASE + 0x2EC) 152 #define DVFSRC_DDR_QOS2 (DVFSRC_BASE + 0x2F0) 153 #define DVFSRC_DDR_QOS3 (DVFSRC_BASE + 0x2F4) 154 #define DVFSRC_DDR_QOS4 (DVFSRC_BASE + 0x2F8) 155 #define DVFSRC_DDR_QOS5 (DVFSRC_BASE + 0x2FC) 156 #define DVFSRC_DDR_QOS6 (DVFSRC_BASE + 0x300) 157 #define DVFSRC_RSRV_6 (DVFSRC_BASE + 0x304) 158 #define DVFSRC_RSRV_7 (DVFSRC_BASE + 0x308) 159 #define DVFSRC_RSRV_8 (DVFSRC_BASE + 0x30C) 160 #define DVFSRC_RSRV_9 (DVFSRC_BASE + 0x310) 161 #define DVFSRC_RSRV_10 (DVFSRC_BASE + 0x314) 162 #define DVFSRC_RSRV_11 (DVFSRC_BASE + 0x318) 163 #define DVFSRC_HRT_REQ_MD_URG (DVFSRC_BASE + 0x320) 164 #define DVFSRC_HRT_REQ_MD_BW_0 (DVFSRC_BASE + 0x324) 165 #define DVFSRC_HRT_REQ_MD_BW_1 (DVFSRC_BASE + 0x328) 166 #define DVFSRC_HRT_REQ_MD_BW_2 (DVFSRC_BASE + 0x32C) 167 #define DVFSRC_HRT_REQ_MD_BW_3 (DVFSRC_BASE + 0x330) 168 #define DVFSRC_HRT_REQ_MD_BW_4 (DVFSRC_BASE + 0x334) 169 #define DVFSRC_HRT_REQ_MD_BW_5 (DVFSRC_BASE + 0x338) 170 #define DVFSRC_HRT_REQ_MD_BW_6 (DVFSRC_BASE + 0x33C) 171 #define DVFSRC_HRT_REQ_MD_BW_7 (DVFSRC_BASE + 0x340) 172 #define DVFSRC_HRT_REQ_MD_BW_8 (DVFSRC_BASE + 0x344) 173 #define DVFSRC_HRT_REQ_MD_BW_9 (DVFSRC_BASE + 0x348) 174 #define DVFSRC_HRT_REQ_MD_BW_10 (DVFSRC_BASE + 0x34C) 175 #define DVFSRC_HRT1_REQ_MD_BW_0 (DVFSRC_BASE + 0x350) 176 #define DVFSRC_HRT1_REQ_MD_BW_1 (DVFSRC_BASE + 0x354) 177 #define DVFSRC_HRT1_REQ_MD_BW_2 (DVFSRC_BASE + 0x358) 178 #define DVFSRC_HRT1_REQ_MD_BW_3 (DVFSRC_BASE + 0x35C) 179 #define DVFSRC_HRT1_REQ_MD_BW_4 (DVFSRC_BASE + 0x360) 180 #define DVFSRC_HRT1_REQ_MD_BW_5 (DVFSRC_BASE + 0x364) 181 #define DVFSRC_HRT1_REQ_MD_BW_6 (DVFSRC_BASE + 0x368) 182 #define DVFSRC_HRT1_REQ_MD_BW_7 (DVFSRC_BASE + 0x36C) 183 #define DVFSRC_HRT1_REQ_MD_BW_8 (DVFSRC_BASE + 0x370) 184 #define DVFSRC_HRT1_REQ_MD_BW_9 (DVFSRC_BASE + 0x374) 185 #define DVFSRC_HRT1_REQ_MD_BW_10 (DVFSRC_BASE + 0x378) 186 #define DVFSRC_HRT_REQUEST (DVFSRC_BASE + 0x380) 187 #define DVFSRC_HRT_HIGH_3 (DVFSRC_BASE + 0x384) 188 #define DVFSRC_HRT_HIGH_2 (DVFSRC_BASE + 0x388) 189 #define DVFSRC_HRT_HIGH_1 (DVFSRC_BASE + 0x38C) 190 #define DVFSRC_HRT_HIGH (DVFSRC_BASE + 0x390) 191 #define DVFSRC_HRT_LOW_3 (DVFSRC_BASE + 0x394) 192 #define DVFSRC_HRT_LOW_2 (DVFSRC_BASE + 0x398) 193 #define DVFSRC_HRT_LOW_1 (DVFSRC_BASE + 0x39C) 194 #define DVFSRC_HRT_LOW (DVFSRC_BASE + 0x3A0) 195 #define DVFSRC_DDR_ADD_REQUEST (DVFSRC_BASE + 0x3A4) 196 #define DVFSRC_EMI_ADD_REQUEST (DVFSRC_BASE + 0x3A8) 197 #define DVFSRC_LAST (DVFSRC_BASE + 0x3AC) 198 #define DVFSRC_LAST_L (DVFSRC_BASE + 0x3B0) 199 #define DVFSRC_MD_SCENARIO (DVFSRC_BASE + 0x3B4) 200 #define DVFSRC_RECORD_0_0 (DVFSRC_BASE + 0x3B8) 201 #define DVFSRC_RECORD_0_1 (DVFSRC_BASE + 0x3BC) 202 #define DVFSRC_RECORD_0_2 (DVFSRC_BASE + 0x3C0) 203 #define DVFSRC_RECORD_0_3 (DVFSRC_BASE + 0x3C4) 204 #define DVFSRC_RECORD_0_4 (DVFSRC_BASE + 0x3C8) 205 #define DVFSRC_RECORD_0_5 (DVFSRC_BASE + 0x3CC) 206 #define DVFSRC_RECORD_0_6 (DVFSRC_BASE + 0x3D0) 207 #define DVFSRC_RECORD_0_7 (DVFSRC_BASE + 0x3D4) 208 #define DVFSRC_RECORD_1_0 (DVFSRC_BASE + 0x3D8) 209 #define DVFSRC_RECORD_1_1 (DVFSRC_BASE + 0x3DC) 210 #define DVFSRC_RECORD_1_2 (DVFSRC_BASE + 0x3E0) 211 #define DVFSRC_RECORD_1_3 (DVFSRC_BASE + 0x3E4) 212 #define DVFSRC_RECORD_1_4 (DVFSRC_BASE + 0x3E8) 213 #define DVFSRC_RECORD_1_5 (DVFSRC_BASE + 0x3EC) 214 #define DVFSRC_RECORD_1_6 (DVFSRC_BASE + 0x3F0) 215 #define DVFSRC_RECORD_1_7 (DVFSRC_BASE + 0x3F4) 216 #define DVFSRC_RECORD_2_0 (DVFSRC_BASE + 0x3F8) 217 #define DVFSRC_RECORD_2_1 (DVFSRC_BASE + 0x3FC) 218 #define DVFSRC_RECORD_2_2 (DVFSRC_BASE + 0x400) 219 #define DVFSRC_RECORD_2_3 (DVFSRC_BASE + 0x404) 220 #define DVFSRC_RECORD_2_4 (DVFSRC_BASE + 0x408) 221 #define DVFSRC_RECORD_2_5 (DVFSRC_BASE + 0x40C) 222 #define DVFSRC_RECORD_2_6 (DVFSRC_BASE + 0x410) 223 #define DVFSRC_RECORD_2_7 (DVFSRC_BASE + 0x414) 224 #define DVFSRC_RECORD_3_0 (DVFSRC_BASE + 0x418) 225 #define DVFSRC_RECORD_3_1 (DVFSRC_BASE + 0x41C) 226 #define DVFSRC_RECORD_3_2 (DVFSRC_BASE + 0x420) 227 #define DVFSRC_RECORD_3_3 (DVFSRC_BASE + 0x424) 228 #define DVFSRC_RECORD_3_4 (DVFSRC_BASE + 0x428) 229 #define DVFSRC_RECORD_3_5 (DVFSRC_BASE + 0x42C) 230 #define DVFSRC_RECORD_3_6 (DVFSRC_BASE + 0x430) 231 #define DVFSRC_RECORD_3_7 (DVFSRC_BASE + 0x434) 232 #define DVFSRC_RECORD_4_0 (DVFSRC_BASE + 0x438) 233 #define DVFSRC_RECORD_4_1 (DVFSRC_BASE + 0x43C) 234 #define DVFSRC_RECORD_4_2 (DVFSRC_BASE + 0x440) 235 #define DVFSRC_RECORD_4_3 (DVFSRC_BASE + 0x444) 236 #define DVFSRC_RECORD_4_4 (DVFSRC_BASE + 0x448) 237 #define DVFSRC_RECORD_4_5 (DVFSRC_BASE + 0x44C) 238 #define DVFSRC_RECORD_4_6 (DVFSRC_BASE + 0x450) 239 #define DVFSRC_RECORD_4_7 (DVFSRC_BASE + 0x454) 240 #define DVFSRC_RECORD_5_0 (DVFSRC_BASE + 0x458) 241 #define DVFSRC_RECORD_5_1 (DVFSRC_BASE + 0x45C) 242 #define DVFSRC_RECORD_5_2 (DVFSRC_BASE + 0x460) 243 #define DVFSRC_RECORD_5_3 (DVFSRC_BASE + 0x464) 244 #define DVFSRC_RECORD_5_4 (DVFSRC_BASE + 0x468) 245 #define DVFSRC_RECORD_5_5 (DVFSRC_BASE + 0x46C) 246 #define DVFSRC_RECORD_5_6 (DVFSRC_BASE + 0x470) 247 #define DVFSRC_RECORD_5_7 (DVFSRC_BASE + 0x474) 248 #define DVFSRC_RECORD_6_0 (DVFSRC_BASE + 0x478) 249 #define DVFSRC_RECORD_6_1 (DVFSRC_BASE + 0x47C) 250 #define DVFSRC_RECORD_6_2 (DVFSRC_BASE + 0x480) 251 #define DVFSRC_RECORD_6_3 (DVFSRC_BASE + 0x484) 252 #define DVFSRC_RECORD_6_4 (DVFSRC_BASE + 0x488) 253 #define DVFSRC_RECORD_6_5 (DVFSRC_BASE + 0x48C) 254 #define DVFSRC_RECORD_6_6 (DVFSRC_BASE + 0x490) 255 #define DVFSRC_RECORD_6_7 (DVFSRC_BASE + 0x494) 256 #define DVFSRC_RECORD_7_0 (DVFSRC_BASE + 0x498) 257 #define DVFSRC_RECORD_7_1 (DVFSRC_BASE + 0x49C) 258 #define DVFSRC_RECORD_7_2 (DVFSRC_BASE + 0x4A0) 259 #define DVFSRC_RECORD_7_3 (DVFSRC_BASE + 0x4A4) 260 #define DVFSRC_RECORD_7_4 (DVFSRC_BASE + 0x4A8) 261 #define DVFSRC_RECORD_7_5 (DVFSRC_BASE + 0x4AC) 262 #define DVFSRC_RECORD_7_6 (DVFSRC_BASE + 0x4B0) 263 #define DVFSRC_RECORD_7_7 (DVFSRC_BASE + 0x4B4) 264 #define DVFSRC_RECORD_0_L_0 (DVFSRC_BASE + 0x4B8) 265 #define DVFSRC_RECORD_0_L_1 (DVFSRC_BASE + 0x4BC) 266 #define DVFSRC_RECORD_0_L_2 (DVFSRC_BASE + 0x4C0) 267 #define DVFSRC_RECORD_0_L_3 (DVFSRC_BASE + 0x4C4) 268 #define DVFSRC_RECORD_0_L_4 (DVFSRC_BASE + 0x4C8) 269 #define DVFSRC_RECORD_0_L_5 (DVFSRC_BASE + 0x4CC) 270 #define DVFSRC_RECORD_0_L_6 (DVFSRC_BASE + 0x4D0) 271 #define DVFSRC_RECORD_0_L_7 (DVFSRC_BASE + 0x4D4) 272 #define DVFSRC_RECORD_1_L_0 (DVFSRC_BASE + 0x4D8) 273 #define DVFSRC_RECORD_1_L_1 (DVFSRC_BASE + 0x4DC) 274 #define DVFSRC_RECORD_1_L_2 (DVFSRC_BASE + 0x4E0) 275 #define DVFSRC_RECORD_1_L_3 (DVFSRC_BASE + 0x4E4) 276 #define DVFSRC_RECORD_1_L_4 (DVFSRC_BASE + 0x4E8) 277 #define DVFSRC_RECORD_1_L_5 (DVFSRC_BASE + 0x4EC) 278 #define DVFSRC_RECORD_1_L_6 (DVFSRC_BASE + 0x4F0) 279 #define DVFSRC_RECORD_1_L_7 (DVFSRC_BASE + 0x4F4) 280 #define DVFSRC_RECORD_2_L_0 (DVFSRC_BASE + 0x4F8) 281 #define DVFSRC_RECORD_2_L_1 (DVFSRC_BASE + 0x4FC) 282 #define DVFSRC_RECORD_2_L_2 (DVFSRC_BASE + 0x500) 283 #define DVFSRC_RECORD_2_L_3 (DVFSRC_BASE + 0x504) 284 #define DVFSRC_RECORD_2_L_4 (DVFSRC_BASE + 0x508) 285 #define DVFSRC_RECORD_2_L_5 (DVFSRC_BASE + 0x50C) 286 #define DVFSRC_RECORD_2_L_6 (DVFSRC_BASE + 0x510) 287 #define DVFSRC_RECORD_2_L_7 (DVFSRC_BASE + 0x514) 288 #define DVFSRC_RECORD_3_L_0 (DVFSRC_BASE + 0x518) 289 #define DVFSRC_RECORD_3_L_1 (DVFSRC_BASE + 0x51C) 290 #define DVFSRC_RECORD_3_L_2 (DVFSRC_BASE + 0x520) 291 #define DVFSRC_RECORD_3_L_3 (DVFSRC_BASE + 0x524) 292 #define DVFSRC_RECORD_3_L_4 (DVFSRC_BASE + 0x528) 293 #define DVFSRC_RECORD_3_L_5 (DVFSRC_BASE + 0x52C) 294 #define DVFSRC_RECORD_3_L_6 (DVFSRC_BASE + 0x530) 295 #define DVFSRC_RECORD_3_L_7 (DVFSRC_BASE + 0x534) 296 #define DVFSRC_RECORD_4_L_0 (DVFSRC_BASE + 0x538) 297 #define DVFSRC_RECORD_4_L_1 (DVFSRC_BASE + 0x53C) 298 #define DVFSRC_RECORD_4_L_2 (DVFSRC_BASE + 0x540) 299 #define DVFSRC_RECORD_4_L_3 (DVFSRC_BASE + 0x544) 300 #define DVFSRC_RECORD_4_L_4 (DVFSRC_BASE + 0x548) 301 #define DVFSRC_RECORD_4_L_5 (DVFSRC_BASE + 0x54C) 302 #define DVFSRC_RECORD_4_L_6 (DVFSRC_BASE + 0x550) 303 #define DVFSRC_RECORD_4_L_7 (DVFSRC_BASE + 0x554) 304 #define DVFSRC_RECORD_5_L_0 (DVFSRC_BASE + 0x558) 305 #define DVFSRC_RECORD_5_L_1 (DVFSRC_BASE + 0x55C) 306 #define DVFSRC_RECORD_5_L_2 (DVFSRC_BASE + 0x560) 307 #define DVFSRC_RECORD_5_L_3 (DVFSRC_BASE + 0x564) 308 #define DVFSRC_RECORD_5_L_4 (DVFSRC_BASE + 0x568) 309 #define DVFSRC_RECORD_5_L_5 (DVFSRC_BASE + 0x56C) 310 #define DVFSRC_RECORD_5_L_6 (DVFSRC_BASE + 0x570) 311 #define DVFSRC_RECORD_5_L_7 (DVFSRC_BASE + 0x574) 312 #define DVFSRC_RECORD_6_L_0 (DVFSRC_BASE + 0x578) 313 #define DVFSRC_RECORD_6_L_1 (DVFSRC_BASE + 0x57C) 314 #define DVFSRC_RECORD_6_L_2 (DVFSRC_BASE + 0x580) 315 #define DVFSRC_RECORD_6_L_3 (DVFSRC_BASE + 0x584) 316 #define DVFSRC_RECORD_6_L_4 (DVFSRC_BASE + 0x588) 317 #define DVFSRC_RECORD_6_L_5 (DVFSRC_BASE + 0x58C) 318 #define DVFSRC_RECORD_6_L_6 (DVFSRC_BASE + 0x590) 319 #define DVFSRC_RECORD_6_L_7 (DVFSRC_BASE + 0x594) 320 #define DVFSRC_RECORD_7_L_0 (DVFSRC_BASE + 0x598) 321 #define DVFSRC_RECORD_7_L_1 (DVFSRC_BASE + 0x59C) 322 #define DVFSRC_RECORD_7_L_2 (DVFSRC_BASE + 0x5A0) 323 #define DVFSRC_RECORD_7_L_3 (DVFSRC_BASE + 0x5A4) 324 #define DVFSRC_RECORD_7_L_4 (DVFSRC_BASE + 0x5A8) 325 #define DVFSRC_RECORD_7_L_5 (DVFSRC_BASE + 0x5AC) 326 #define DVFSRC_RECORD_7_L_6 (DVFSRC_BASE + 0x5B0) 327 #define DVFSRC_RECORD_7_L_7 (DVFSRC_BASE + 0x5B4) 328 #define DVFSRC_CURRENT_LEVEL_1 (DVFSRC_BASE + 0x5C4) 329 #define DVFSRC_CURRENT_LEVEL_2 (DVFSRC_BASE + 0x5C8) 330 #define DVFSRC_TARGET_LEVEL_1 (DVFSRC_BASE + 0x5CC) 331 #define DVFSRC_TARGET_LEVEL_2 (DVFSRC_BASE + 0x5D0) 332 #define DVFSRC_CURRENT_FORCE_1 (DVFSRC_BASE + 0x5D4) 333 #define DVFSRC_CURRENT_FORCE_2 (DVFSRC_BASE + 0x5D8) 334 #define DVFSRC_TARGET_FORCE_1 (DVFSRC_BASE + 0x5DC) 335 #define DVFSRC_TARGET_FORCE_2 (DVFSRC_BASE + 0x5E0) 336 #define DVFSRC_MD_DDR_FLOOR_REQUEST (DVFSRC_BASE + 0x5E4) 337 #define DVFSRC_QOS_DDR_REQUEST (DVFSRC_BASE + 0x5E8) 338 #define DVFSRC_FORCE_MASK (DVFSRC_BASE + 0x5EC) 339 #define DVFSRC_LEVEL_HEX (DVFSRC_BASE + 0x5F0) 340 #define DVFSRC_AVS_RETRY (DVFSRC_BASE + 0x5F4) 341 #define DVFSRC_SW_REQ9 (DVFSRC_BASE + 0x5F8) 342 #define DVFSRC_SW_REQ10 (DVFSRC_BASE + 0x5FC) 343 #define DVFSRC_SW_REQ11 (DVFSRC_BASE + 0x600) 344 #define DVFSRC_SW_REQ12 (DVFSRC_BASE + 0x604) 345 #define DVFSRC_LEVEL_MASK_SW_1 (DVFSRC_BASE + 0x608) 346 #define DVFSRC_LEVEL_MASK_SW_2 (DVFSRC_BASE + 0x60C) 347 #define DVFSRC_ACCEPT_RETRY (DVFSRC_BASE + 0x610) 348 #define DVFSRC_TARGET_LEVEL_SPM_1 (DVFSRC_BASE + 0x614) 349 #define DVFSRC_TARGET_LEVEL_SPM_2 (DVFSRC_BASE + 0x618) 350 #define DVFSRC_EMI_REQUEST8 (DVFSRC_BASE + 0x620) 351 #define DVFSRC_DDR_REQUEST8 (DVFSRC_BASE + 0x62C) 352 #define DVFSRC_EMI_QOS7 (DVFSRC_BASE + 0x64C) 353 #define DVFSRC_EMI_QOS8 (DVFSRC_BASE + 0x650) 354 #define DVFSRC_EMI_QOS9 (DVFSRC_BASE + 0x654) 355 #define DVFSRC_EMI_QOS10 (DVFSRC_BASE + 0x658) 356 #define DVFSRC_DDR_QOS7 (DVFSRC_BASE + 0x65C) 357 #define DVFSRC_DDR_QOS8 (DVFSRC_BASE + 0x660) 358 #define DVFSRC_DDR_QOS9 (DVFSRC_BASE + 0x664) 359 #define DVFSRC_DDR_QOS10 (DVFSRC_BASE + 0x668) 360 #define DVFSRC_HRT_HIGH_7 (DVFSRC_BASE + 0x66C) 361 #define DVFSRC_HRT_HIGH_6 (DVFSRC_BASE + 0x670) 362 #define DVFSRC_HRT_HIGH_5 (DVFSRC_BASE + 0x674) 363 #define DVFSRC_HRT_HIGH_4 (DVFSRC_BASE + 0x678) 364 #define DVFSRC_HRT_LOW_7 (DVFSRC_BASE + 0x67C) 365 #define DVFSRC_HRT_LOW_6 (DVFSRC_BASE + 0x680) 366 #define DVFSRC_HRT_LOW_5 (DVFSRC_BASE + 0x684) 367 #define DVFSRC_HRT_LOW_4 (DVFSRC_BASE + 0x688) 368 #define DVFSRC_DDR_ADD_REQUEST_1 (DVFSRC_BASE + 0x68C) 369 #define DVFSRC_EMI_ADD_REQUEST_1 (DVFSRC_BASE + 0x690) 370 #define DVFSRC_HRT_REQUEST_1 (DVFSRC_BASE + 0x694) 371 #define DVFSRC_VCORE_QOS5 (DVFSRC_BASE + 0x69C) 372 #define DVFSRC_VCORE_QOS6 (DVFSRC_BASE + 0x6A0) 373 #define DVFSRC_VCORE_QOS7 (DVFSRC_BASE + 0x6A4) 374 #define DVFSRC_CEILING_SET (DVFSRC_BASE + 0x6A8) 375 #define DVFSRC_CUR_TARGET_GEAR (DVFSRC_BASE + 0x6AC) 376 #define DVFSRC_LEVEL_LABEL_64_65 (DVFSRC_BASE + 0x6B0) 377 #define DVFSRC_LEVEL_LABEL_66_67 (DVFSRC_BASE + 0x6B4) 378 #define DVFSRC_LEVEL_LABEL_68_69 (DVFSRC_BASE + 0x6B8) 379 #define DVFSRC_LEVEL_LABEL_70_71 (DVFSRC_BASE + 0x6BC) 380 #define DVFSRC_LEVEL_LABEL_72_73 (DVFSRC_BASE + 0x6C0) 381 #define DVFSRC_LEVEL_LABEL_74_75 (DVFSRC_BASE + 0x6C4) 382 #define DVFSRC_LEVEL_LABEL_76_77 (DVFSRC_BASE + 0x6C8) 383 #define DVFSRC_LEVEL_LABEL_78_79 (DVFSRC_BASE + 0x6CC) 384 #define DVFSRC_LEVEL_LABEL_80_81 (DVFSRC_BASE + 0x6D0) 385 #define DVFSRC_LEVEL_LABEL_82_83 (DVFSRC_BASE + 0x6D4) 386 #define DVFSRC_LEVEL_LABEL_84_85 (DVFSRC_BASE + 0x6D8) 387 #define DVFSRC_LEVEL_LABEL_86_87 (DVFSRC_BASE + 0x6DC) 388 #define DVFSRC_LEVEL_LABEL_88_89 (DVFSRC_BASE + 0x6E0) 389 #define DVFSRC_LEVEL_LABEL_90_91 (DVFSRC_BASE + 0x6E4) 390 #define DVFSRC_LEVEL_LABEL_92_93 (DVFSRC_BASE + 0x6E8) 391 #define DVFSRC_LEVEL_LABEL_94_95 (DVFSRC_BASE + 0x6EC) 392 #define DVFSRC_LEVEL_LABEL_96_97 (DVFSRC_BASE + 0x6F0) 393 #define DVFSRC_LEVEL_LABEL_98_99 (DVFSRC_BASE + 0x6F4) 394 #define DVFSRC_LEVEL_LABEL_100_101 (DVFSRC_BASE + 0x6F8) 395 #define DVFSRC_LEVEL_LABEL_102_103 (DVFSRC_BASE + 0x6FC) 396 #define DVFSRC_LEVEL_LABEL_104_105 (DVFSRC_BASE + 0x700) 397 #define DVFSRC_LEVEL_LABEL_106_107 (DVFSRC_BASE + 0x704) 398 #define DVFSRC_LEVEL_LABEL_108_109 (DVFSRC_BASE + 0x708) 399 #define DVFSRC_LEVEL_LABEL_110_111 (DVFSRC_BASE + 0x70C) 400 #define DVFSRC_LEVEL_LABEL_112_113 (DVFSRC_BASE + 0x710) 401 #define DVFSRC_LEVEL_LABEL_114_115 (DVFSRC_BASE + 0x714) 402 #define DVFSRC_LEVEL_LABEL_116_117 (DVFSRC_BASE + 0x718) 403 #define DVFSRC_LEVEL_LABEL_118_119 (DVFSRC_BASE + 0x71C) 404 #define DVFSRC_LEVEL_LABEL_120_121 (DVFSRC_BASE + 0x720) 405 #define DVFSRC_LEVEL_LABEL_122_123 (DVFSRC_BASE + 0x724) 406 #define DVFSRC_LEVEL_LABEL_124_125 (DVFSRC_BASE + 0x728) 407 #define DVFSRC_LEVEL_LABEL_126_127 (DVFSRC_BASE + 0x72C) 408 #define DVFSRC_LEVEL_MASK_MD_3 (DVFSRC_BASE + 0x738) 409 #define DVFSRC_LEVEL_MASK_MD_4 (DVFSRC_BASE + 0x73C) 410 #define DVFSRC_DEFAULT_OPP_3 (DVFSRC_BASE + 0x740) 411 #define DVFSRC_DEFAULT_OPP_4 (DVFSRC_BASE + 0x744) 412 #define DVFSRC_LEVEL_MASK_SW_3 (DVFSRC_BASE + 0x748) 413 #define DVFSRC_LEVEL_MASK_SW_4 (DVFSRC_BASE + 0x74C) 414 #define DVFSRC_TARGET_LEVEL_SPM_3 (DVFSRC_BASE + 0x750) 415 #define DVFSRC_TARGET_LEVEL_SPM_4 (DVFSRC_BASE + 0x754) 416 #define DVFSRC_CURRENT_LEVEL_3 (DVFSRC_BASE + 0x758) 417 #define DVFSRC_CURRENT_LEVEL_4 (DVFSRC_BASE + 0x75C) 418 #define DVFSRC_TARGET_LEVEL_3 (DVFSRC_BASE + 0x760) 419 #define DVFSRC_TARGET_LEVEL_4 (DVFSRC_BASE + 0x764) 420 #define DVFSRC_CURRENT_FORCE_3 (DVFSRC_BASE + 0x768) 421 #define DVFSRC_CURRENT_FORCE_4 (DVFSRC_BASE + 0x76C) 422 #define DVFSRC_TARGET_FORCE_3 (DVFSRC_BASE + 0x770) 423 #define DVFSRC_TARGET_FORCE_4 (DVFSRC_BASE + 0x774) 424 #define DVFSRC_DDR_REQUEST10 (DVFSRC_BASE + 0x778) 425 #define DVFSRC_EMI_REQUEST10 (DVFSRC_BASE + 0x77C) 426 #define DVFSRC_DDR_REQUEST11 (DVFSRC_BASE + 0x780) 427 #define DVFSRC_EMI_REQUEST11 (DVFSRC_BASE + 0x784) 428 #define DVFSRC_TARGET_FORCE_5 (DVFSRC_BASE + 0x788) 429 #define DVFSRC_TARGET_FORCE_6 (DVFSRC_BASE + 0x78C) 430 #define DVFSRC_TARGET_FORCE_7 (DVFSRC_BASE + 0x790) 431 #define DVFSRC_TARGET_FORCE_8 (DVFSRC_BASE + 0x794) 432 #define DVFSRC_PMQOS_HRT_UNIT_SW_BW (DVFSRC_BASE + 0x798) 433 #define DVFSRC_DISP_HRT_UNIT_SW_BW (DVFSRC_BASE + 0x79C) 434 #define DVFSRC_ISP_HRT_UNIT_SW_BW (DVFSRC_BASE + 0x7A0) 435 #define DVFSRC_MD_HRT_UNIT_SW_BW (DVFSRC_BASE + 0x7A4) 436 #define DVFSRC_HRT_BASE_HRT_UNIT_SW_BW (DVFSRC_BASE + 0x7A8) 437 #define DVFSRC_APU_HRT_UNIT_SW_BW (DVFSRC_BASE + 0x7AC) 438 #define DVFSRC_SMMU_HRT_UNIT_SW_BW (DVFSRC_BASE + 0x7B0) 439 #define DVFSRC_SMAP_CG_SET (DVFSRC_BASE + 0x814) 440 #define DVFSRC_LEVEL_MASK_MD_5 (DVFSRC_BASE + 0x818) 441 #define DVFSRC_LEVEL_MASK_MD_6 (DVFSRC_BASE + 0x81C) 442 #define DVFSRC_LEVEL_MASK_MD_7 (DVFSRC_BASE + 0x820) 443 #define DVFSRC_LEVEL_MASK_MD_8 (DVFSRC_BASE + 0x824) 444 #define DVFSRC_DEFAULT_OPP_5 (DVFSRC_BASE + 0x828) 445 #define DVFSRC_DEFAULT_OPP_6 (DVFSRC_BASE + 0x82C) 446 #define DVFSRC_DEFAULT_OPP_7 (DVFSRC_BASE + 0x830) 447 #define DVFSRC_DEFAULT_OPP_8 (DVFSRC_BASE + 0x834) 448 #define DVFSRC_LEVEL_MASK_SW_5 (DVFSRC_BASE + 0x838) 449 #define DVFSRC_LEVEL_MASK_SW_6 (DVFSRC_BASE + 0x83C) 450 #define DVFSRC_LEVEL_MASK_SW_7 (DVFSRC_BASE + 0x840) 451 #define DVFSRC_LEVEL_MASK_SW_8 (DVFSRC_BASE + 0x844) 452 #define DVFSRC_TARGET_LEVEL_SPM_5 (DVFSRC_BASE + 0x848) 453 #define DVFSRC_TARGET_LEVEL_SPM_6 (DVFSRC_BASE + 0x84C) 454 #define DVFSRC_TARGET_LEVEL_SPM_7 (DVFSRC_BASE + 0x850) 455 #define DVFSRC_TARGET_LEVEL_SPM_8 (DVFSRC_BASE + 0x854) 456 #define DVFSRC_CURRENT_LEVEL_5 (DVFSRC_BASE + 0x858) 457 #define DVFSRC_CURRENT_LEVEL_6 (DVFSRC_BASE + 0x85C) 458 #define DVFSRC_CURRENT_LEVEL_7 (DVFSRC_BASE + 0x860) 459 #define DVFSRC_CURRENT_LEVEL_8 (DVFSRC_BASE + 0x864) 460 #define DVFSRC_TARGET_LEVEL_5 (DVFSRC_BASE + 0x868) 461 #define DVFSRC_TARGET_LEVEL_6 (DVFSRC_BASE + 0x86C) 462 #define DVFSRC_TARGET_LEVEL_7 (DVFSRC_BASE + 0x870) 463 #define DVFSRC_TARGET_LEVEL_8 (DVFSRC_BASE + 0x874) 464 #define DVFSRC_CURRENT_FORCE_5 (DVFSRC_BASE + 0x878) 465 #define DVFSRC_CURRENT_FORCE_6 (DVFSRC_BASE + 0x87C) 466 #define DVFSRC_CURRENT_FORCE_7 (DVFSRC_BASE + 0x880) 467 #define DVFSRC_CURRENT_FORCE_8 (DVFSRC_BASE + 0x884) 468 #define DVFSRC_HRT_REQ_MD_BW_11 (DVFSRC_BASE + 0x88C) 469 #define DVFSRC_HRT_REQ_MD_BW_12 (DVFSRC_BASE + 0x890) 470 #define DVFSRC_HRT_REQ_MD_BW_13 (DVFSRC_BASE + 0x894) 471 #define DVFSRC_HRT_REQ_MD_BW_14 (DVFSRC_BASE + 0x898) 472 #define DVFSRC_HRT_REQ_MD_BW_15 (DVFSRC_BASE + 0x89C) 473 #define DVFSRC_HRT_REQ_MD_BW_16 (DVFSRC_BASE + 0x8A0) 474 #define DVFSRC_HRT_REQ_MD_BW_17 (DVFSRC_BASE + 0x8A4) 475 #define DVFSRC_HRT_REQ_MD_BW_18 (DVFSRC_BASE + 0x8A8) 476 #define DVFSRC_HRT_REQ_MD_BW_19 (DVFSRC_BASE + 0x8AC) 477 #define DVFSRC_HRT_REQ_MD_BW_20 (DVFSRC_BASE + 0x8B0) 478 #define DVFSRC_HRT_REQ_MD_BW_21 (DVFSRC_BASE + 0x8B4) 479 #define DVFSRC_HRT1_REQ_MD_BW_11 (DVFSRC_BASE + 0x8B8) 480 #define DVFSRC_HRT1_REQ_MD_BW_12 (DVFSRC_BASE + 0x8BC) 481 #define DVFSRC_HRT1_REQ_MD_BW_13 (DVFSRC_BASE + 0x8C0) 482 #define DVFSRC_HRT1_REQ_MD_BW_14 (DVFSRC_BASE + 0x8C4) 483 #define DVFSRC_HRT1_REQ_MD_BW_15 (DVFSRC_BASE + 0x8C8) 484 #define DVFSRC_HRT1_REQ_MD_BW_16 (DVFSRC_BASE + 0x8CC) 485 #define DVFSRC_HRT1_REQ_MD_BW_17 (DVFSRC_BASE + 0x8D0) 486 #define DVFSRC_HRT1_REQ_MD_BW_18 (DVFSRC_BASE + 0x8D4) 487 #define DVFSRC_HRT1_REQ_MD_BW_19 (DVFSRC_BASE + 0x8D8) 488 #define DVFSRC_HRT1_REQ_MD_BW_20 (DVFSRC_BASE + 0x8DC) 489 #define DVFSRC_HRT1_REQ_MD_BW_21 (DVFSRC_BASE + 0x8E0) 490 #define DVFSRC_95MD_SCEN_EMI4 (DVFSRC_BASE + 0x904) 491 #define DVFSRC_95MD_SCEN_EMI5 (DVFSRC_BASE + 0x908) 492 #define DVFSRC_95MD_SCEN_EMI6 (DVFSRC_BASE + 0x90C) 493 #define DVFSRC_95MD_SCEN_EMI7 (DVFSRC_BASE + 0x910) 494 #define DVFSRC_95MD_SCEN_EMI4_T (DVFSRC_BASE + 0x914) 495 #define DVFSRC_95MD_SCEN_EMI5_T (DVFSRC_BASE + 0x918) 496 #define DVFSRC_95MD_SCEN_EMI6_T (DVFSRC_BASE + 0x91C) 497 #define DVFSRC_95MD_SCEN_EMI7_T (DVFSRC_BASE + 0x920) 498 #define DVFSRC_95MD_SCEN_BW4 (DVFSRC_BASE + 0x924) 499 #define DVFSRC_95MD_SCEN_BW5 (DVFSRC_BASE + 0x928) 500 #define DVFSRC_95MD_SCEN_BW6 (DVFSRC_BASE + 0x92C) 501 #define DVFSRC_95MD_SCEN_BW7 (DVFSRC_BASE + 0x930) 502 #define DVFSRC_95MD_SCEN_BW4_T (DVFSRC_BASE + 0x934) 503 #define DVFSRC_95MD_SCEN_BW5_T (DVFSRC_BASE + 0x938) 504 #define DVFSRC_95MD_SCEN_BW6_T (DVFSRC_BASE + 0x93C) 505 #define DVFSRC_95MD_SCEN_BW7_T (DVFSRC_BASE + 0x940) 506 #define DVFSRC_LEVEL_LABEL_128_129 (DVFSRC_BASE + 0x944) 507 #define DVFSRC_LEVEL_LABEL_130_131 (DVFSRC_BASE + 0x948) 508 #define DVFSRC_LEVEL_LABEL_132_133 (DVFSRC_BASE + 0x94C) 509 #define DVFSRC_LEVEL_LABEL_134_135 (DVFSRC_BASE + 0x950) 510 #define DVFSRC_LEVEL_LABEL_136_137 (DVFSRC_BASE + 0x954) 511 #define DVFSRC_LEVEL_LABEL_138_139 (DVFSRC_BASE + 0x958) 512 #define DVFSRC_LEVEL_LABEL_140_141 (DVFSRC_BASE + 0x95C) 513 #define DVFSRC_LEVEL_LABEL_142_143 (DVFSRC_BASE + 0x960) 514 #define DVFSRC_LEVEL_LABEL_144_145 (DVFSRC_BASE + 0x964) 515 #define DVFSRC_LEVEL_LABEL_146_147 (DVFSRC_BASE + 0x968) 516 #define DVFSRC_LEVEL_LABEL_148_149 (DVFSRC_BASE + 0x96C) 517 #define DVFSRC_LEVEL_LABEL_150_151 (DVFSRC_BASE + 0x970) 518 #define DVFSRC_LEVEL_LABEL_152_153 (DVFSRC_BASE + 0x974) 519 #define DVFSRC_LEVEL_LABEL_154_155 (DVFSRC_BASE + 0x978) 520 #define DVFSRC_LEVEL_LABEL_156_157 (DVFSRC_BASE + 0x97C) 521 #define DVFSRC_LEVEL_LABEL_158_159 (DVFSRC_BASE + 0x980) 522 #define DVFSRC_LEVEL_LABEL_160_161 (DVFSRC_BASE + 0x984) 523 #define DVFSRC_LEVEL_LABEL_162_163 (DVFSRC_BASE + 0x988) 524 #define DVFSRC_LEVEL_LABEL_164_165 (DVFSRC_BASE + 0x98C) 525 #define DVFSRC_LEVEL_LABEL_166_167 (DVFSRC_BASE + 0x990) 526 #define DVFSRC_LEVEL_LABEL_168_169 (DVFSRC_BASE + 0x994) 527 #define DVFSRC_LEVEL_LABEL_170_171 (DVFSRC_BASE + 0x998) 528 #define DVFSRC_LEVEL_LABEL_172_173 (DVFSRC_BASE + 0x99C) 529 #define DVFSRC_LEVEL_LABEL_174_175 (DVFSRC_BASE + 0x9A0) 530 #define DVFSRC_LEVEL_LABEL_176_177 (DVFSRC_BASE + 0x9A4) 531 #define DVFSRC_LEVEL_LABEL_178_179 (DVFSRC_BASE + 0x9A8) 532 #define DVFSRC_LEVEL_LABEL_180_181 (DVFSRC_BASE + 0x9AC) 533 #define DVFSRC_LEVEL_LABEL_182_183 (DVFSRC_BASE + 0x9B0) 534 #define DVFSRC_LEVEL_LABEL_184_185 (DVFSRC_BASE + 0x9B4) 535 #define DVFSRC_LEVEL_LABEL_186_187 (DVFSRC_BASE + 0x9B8) 536 #define DVFSRC_LEVEL_LABEL_188_189 (DVFSRC_BASE + 0x9BC) 537 #define DVFSRC_LEVEL_LABEL_190_191 (DVFSRC_BASE + 0x9C0) 538 #define DVFSRC_LEVEL_LABEL_192_193 (DVFSRC_BASE + 0x9C4) 539 #define DVFSRC_LEVEL_LABEL_194_195 (DVFSRC_BASE + 0x9C8) 540 #define DVFSRC_LEVEL_LABEL_196_197 (DVFSRC_BASE + 0x9CC) 541 #define DVFSRC_LEVEL_LABEL_198_199 (DVFSRC_BASE + 0x9D0) 542 #define DVFSRC_LEVEL_LABEL_200_201 (DVFSRC_BASE + 0x9D4) 543 #define DVFSRC_LEVEL_LABEL_202_203 (DVFSRC_BASE + 0x9D8) 544 #define DVFSRC_LEVEL_LABEL_204_205 (DVFSRC_BASE + 0x9DC) 545 #define DVFSRC_LEVEL_LABEL_206_207 (DVFSRC_BASE + 0x9E0) 546 #define DVFSRC_LEVEL_LABEL_208_209 (DVFSRC_BASE + 0x9E4) 547 #define DVFSRC_LEVEL_LABEL_210_211 (DVFSRC_BASE + 0x9E8) 548 #define DVFSRC_LEVEL_LABEL_212_213 (DVFSRC_BASE + 0x9EC) 549 #define DVFSRC_LEVEL_LABEL_214_215 (DVFSRC_BASE + 0x9F0) 550 #define DVFSRC_LEVEL_LABEL_216_217 (DVFSRC_BASE + 0x9F4) 551 #define DVFSRC_LEVEL_LABEL_218_219 (DVFSRC_BASE + 0x9F8) 552 #define DVFSRC_LEVEL_LABEL_220_221 (DVFSRC_BASE + 0x9FC) 553 #define DVFSRC_LEVEL_LABEL_222_223 (DVFSRC_BASE + 0xA00) 554 #define DVFSRC_LEVEL_LABEL_224_225 (DVFSRC_BASE + 0xA04) 555 #define DVFSRC_LEVEL_LABEL_226_227 (DVFSRC_BASE + 0xA08) 556 #define DVFSRC_LEVEL_LABEL_228_229 (DVFSRC_BASE + 0xA0C) 557 #define DVFSRC_LEVEL_LABEL_230_231 (DVFSRC_BASE + 0xA10) 558 #define DVFSRC_LEVEL_LABEL_232_233 (DVFSRC_BASE + 0xA14) 559 #define DVFSRC_LEVEL_LABEL_234_235 (DVFSRC_BASE + 0xA18) 560 #define DVFSRC_LEVEL_LABEL_236_237 (DVFSRC_BASE + 0xA1C) 561 #define DVFSRC_LEVEL_LABEL_238_239 (DVFSRC_BASE + 0xA20) 562 #define DVFSRC_LEVEL_LABEL_240_241 (DVFSRC_BASE + 0xA24) 563 #define DVFSRC_LEVEL_LABEL_242_243 (DVFSRC_BASE + 0xA28) 564 #define DVFSRC_LEVEL_LABEL_244_245 (DVFSRC_BASE + 0xA2C) 565 #define DVFSRC_LEVEL_LABEL_246_247 (DVFSRC_BASE + 0xA30) 566 #define DVFSRC_LEVEL_LABEL_248_249 (DVFSRC_BASE + 0xA34) 567 #define DVFSRC_LEVEL_LABEL_250_251 (DVFSRC_BASE + 0xA38) 568 #define DVFSRC_LEVEL_LABEL_252_253 (DVFSRC_BASE + 0xA3C) 569 #define DVFSRC_LEVEL_LABEL_254_255 (DVFSRC_BASE + 0xA40) 570 #define DVFSRC_HRT_HIGH_15 (DVFSRC_BASE + 0xA44) 571 #define DVFSRC_HRT_HIGH_14 (DVFSRC_BASE + 0xA48) 572 #define DVFSRC_HRT_HIGH_13 (DVFSRC_BASE + 0xA4C) 573 #define DVFSRC_HRT_HIGH_12 (DVFSRC_BASE + 0xA50) 574 #define DVFSRC_HRT_HIGH_11 (DVFSRC_BASE + 0xA54) 575 #define DVFSRC_HRT_HIGH_10 (DVFSRC_BASE + 0xA58) 576 #define DVFSRC_HRT_HIGH_9 (DVFSRC_BASE + 0xA5C) 577 #define DVFSRC_HRT_HIGH_8 (DVFSRC_BASE + 0xA60) 578 #define DVFSRC_HRT_LOW_15 (DVFSRC_BASE + 0xA64) 579 #define DVFSRC_HRT_LOW_14 (DVFSRC_BASE + 0xA68) 580 #define DVFSRC_HRT_LOW_13 (DVFSRC_BASE + 0xA6C) 581 #define DVFSRC_HRT_LOW_12 (DVFSRC_BASE + 0xA70) 582 #define DVFSRC_HRT_LOW_11 (DVFSRC_BASE + 0xA74) 583 #define DVFSRC_HRT_LOW_10 (DVFSRC_BASE + 0xA78) 584 #define DVFSRC_HRT_LOW_9 (DVFSRC_BASE + 0xA7C) 585 #define DVFSRC_HRT_LOW_8 (DVFSRC_BASE + 0xA80) 586 #define DVFSRC_DDR_QOS11 (DVFSRC_BASE + 0xA84) 587 #define DVFSRC_DDR_QOS12 (DVFSRC_BASE + 0xA88) 588 #define DVFSRC_DDR_QOS13 (DVFSRC_BASE + 0xA8C) 589 #define DVFSRC_DDR_QOS14 (DVFSRC_BASE + 0xA90) 590 #define DVFSRC_DDR_QOS15 (DVFSRC_BASE + 0xA94) 591 #define DVFSRC_EMI_QOS11 (DVFSRC_BASE + 0xA98) 592 #define DVFSRC_EMI_QOS12 (DVFSRC_BASE + 0xA9C) 593 #define DVFSRC_EMI_QOS13 (DVFSRC_BASE + 0xAA0) 594 #define DVFSRC_EMI_QOS14 (DVFSRC_BASE + 0xAA4) 595 #define DVFSRC_EMI_QOS15 (DVFSRC_BASE + 0xAA8) 596 #define DVFSRC_TARGET_REQ_MASK BIT(16) 597 #define DVFSRC_EN_MASK 1 598 #endif /* MT_SPM_VCOREFS_REG_6991_H */ 599