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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 #ifndef MHAL_XC_CONFIG_H 95 #define MHAL_XC_CONFIG_H 96 97 //------------------------------------------------------------------------------------------------- 98 // Emerald 99 //------------------------------------------------------------------------------------------------- 100 //------------------------------------------------------------------------------------------------- 101 // Chip Configuration 102 //------------------------------------------------------------------------------------------------- 103 #define MAX_XC_DEVICE_NUM (1) 104 #define MAX_XC_DEVICE0_OFFSET (0UL) 105 106 #define MAX_WINDOW_NUM (2) 107 #define MAX_FRAME_NUM_IN_MEM (4) // Progressive 108 #define MAX_FIELD_NUM_IN_MEM (16) // Interlace 109 #define NUM_OF_DIGITAL_DDCRAM (1) 110 111 #define SCALER_LINE_BUFFER_MAX (1920UL) 112 #define MST_LINE_BFF_MAX MAX(1680, SCALER_LINE_BUFFER_MAX) 113 114 #define SUB_MAIN_LINEOFFSET_GUARD_BAND 0 115 #define SUB_SCALER_LINE_BUFFER_MAX 960UL - SUB_MAIN_LINEOFFSET_GUARD_BAND 116 #define SUB_MST_LINE_BFF_MAX SUB_SCALER_LINE_BUFFER_MAX 117 118 #define MS_3D_LINE_BFF_MAX (960UL)//(1440UL) 119 120 // MIU Word (Bytes) 121 #define BYTE_PER_WORD (16) 122 #define OFFSET_PIXEL_ALIGNMENT (32) 123 #define LPLL_LOOPGAIN (16) 124 #define LVDS_MPLL_CLOCK_MHZ (432) 125 126 #define MCDI_BYTE_PER_WORD 16 127 128 #define DEFAULT_STEP_P 4 //conservative step value 129 #define DEFAULT_STEP_I ((DEFAULT_STEP_P*DEFAULT_STEP_P)/2) 130 #define STEP_P 2 //recommended step value -> more faster fpll(T3) 131 #define STEP_I ((STEP_P*STEP_P)/2) 132 #define IPGAIN_REFACTOR 5 133 134 #define F2_WRITE_LIMIT_EN BIT(31) //BK12_1b[15] 135 #define F2_WRITE_LIMIT_MIN BIT(30) //BK12_1b[14] 136 137 #define F1_WRITE_LIMIT_EN BIT(31) //BK12_5b[15] 138 #define F1_WRITE_LIMIT_MIN BIT(30) //BK12_5b[14] 139 140 #define F2_FRCM_WRITE_LIMIT_EN BIT(31) //BK32_1b[15] 141 #define F1_FRCM_WRITE_LIMIT_EN BIT(31) //BK32_5b[15] 142 143 #define F2_V_WRITE_LIMIT_EN BIT(15) //BK12_18[12] 144 #define F1_V_WRITE_LIMIT_EN BIT(15) //BK12_58[12] 145 146 #define F2_OPW_WRITE_LIMIT_EN BIT(31) //for UC 147 #define F2_OPW_WRITE_LIMIT_MIN BIT(30) //for UC 148 149 #define F2_V_WRITE_LIMIT_EN BIT(15) 150 #define F1_V_WRITE_LIMIT_EN BIT(15) 151 152 #define ADC_MAX_CLK (3500) 153 154 #define SUPPORTED_XC_INT ((1UL << SC_INT_VSINT) | \ 155 (1UL << SC_INT_F2_VTT_CHG) | \ 156 (1UL << SC_INT_F1_VTT_CHG) | \ 157 (1UL << SC_INT_F2_VS_LOSE) | \ 158 (1UL << SC_INT_F1_VS_LOSE) | \ 159 (1UL << SC_INT_F2_JITTER) | \ 160 (1UL << SC_INT_F1_JITTER) | \ 161 (1UL << SC_INT_F2_IPVS_SB) | \ 162 (1UL << SC_INT_F1_IPVS_SB) | \ 163 (1UL << SC_INT_F2_IPHCS_DET) | \ 164 (1UL << SC_INT_F1_IPHCS_DET) | \ 165 (1UL << SC_INT_F2_HTT_CHG) | \ 166 (1UL << SC_INT_F1_HTT_CHG) | \ 167 (1UL << SC_INT_F2_HS_LOSE) | \ 168 (1UL << SC_INT_F1_HS_LOSE) | \ 169 (1UL << SC_INT_F2_CSOG) | \ 170 (1UL << SC_INT_F1_CSOG) | \ 171 (1UL << SC_INT_F2_ATP_READY) | \ 172 (1UL << SC_INT_F1_ATP_READY) | \ 173 (1UL << IRQ_INT_PWM_FP_L_INT)) 174 175 176 //These table definition is from SC_BK0 spec. 177 //Because some chip development is different, it need to check and remap when INT function is used 178 #define IRQ_INT_DIPW 1 179 #define IRQ_INT_START 4 180 #define IRQ_INT_RESERVED1 IRQ_INT_START 181 182 #define IRQ_INT_VSINT 5 183 #define IRQ_INT_F2_VTT_CHG 6 184 #define IRQ_INT_F1_VTT_CHG 7 185 #define IRQ_INT_F2_VS_LOSE 8 186 #define IRQ_INT_F1_VS_LOSE 9 187 #define IRQ_INT_F2_JITTER 10 188 #define IRQ_INT_F1_JITTER 11 189 #define IRQ_INT_F2_IPVS_SB 12 190 #define IRQ_INT_F1_IPVS_SB 13 191 #define IRQ_INT_F2_IPHCS_DET 14 192 #define IRQ_INT_F1_IPHCS_DET 15 193 194 #define IRQ_INT_PWM_RP_L_INT 16 195 #define IRQ_INT_PWM_FP_L_INT 17 196 #define IRQ_INT_F2_HTT_CHG 18 197 #define IRQ_INT_F1_HTT_CHG 19 198 #define IRQ_INT_F2_HS_LOSE 20 199 #define IRQ_INT_F1_HS_LOSE 21 200 #define IRQ_INT_PWM_RP_R_INT 22 201 #define IRQ_INT_PWM_FP_R_INT 23 202 #define IRQ_INT_F2_CSOG 24 203 #define IRQ_INT_F1_CSOG 25 204 #define IRQ_INT_F2_RESERVED2 26 205 #define IRQ_INT_F1_RESERVED2 27 206 #define IRQ_INT_F2_ATP_READY 28 207 #define IRQ_INT_F1_ATP_READY 29 208 #define IRQ_INT_F2_RESERVED3 30 209 #define IRQ_INT_F1_RESERVED3 31 210 211 //------------------------------------------------------------------------------------------------- 212 // Chip Feature 213 //------------------------------------------------------------------------------------------------- 214 215 /* 12 frame mode for progessive */ 216 #define _12FRAME_BUFFER_PMODE_SUPPORTED 0 217 /* 8 frame mode for progessive */ 218 #define _8FRAME_BUFFER_PMODE_SUPPORTED 1 219 /* 6 frame mode for progessive */ 220 #define _6FRAME_BUFFER_PMODE_SUPPORTED 0 221 /* 4 frame mode for progessive */ 222 #define _4FRAME_BUFFER_PMODE_SUPPORTED 1 223 /* 3 frame mode for progessive */ 224 #define _3FRAME_BUFFER_PMODE_SUPPORTED 1 225 226 /* 227 Field-packing ( Customized name ) 228 This is a feature in M10. M10 only needs one IPM buffer address. (Other chips need two or three 229 IPM buffer address). We show one of memory format for example at below. 230 231 Block : Y0 C0 L M Y1 C1 232 Each block contain 4 fields (F0 ~ F3) and each fields in one block is 64 bits 233 Y0 has 64 * 4 bits ( 8 pixel for each field ). 234 Y1 has 64 * 4 bits ( 8 pixel for each field ). 235 So, in this memory format, pixel alignment is 16 pixels (OFFSET_PIXEL_ALIGNMENT = 16). 236 For cropping, OPM address offset have to multiple 4. 237 */ 238 #define _FIELD_PACKING_MODE_SUPPORTED 1 239 240 #if (_FIELD_PACKING_MODE_SUPPORTED) 241 242 /* Linear mode */ 243 #define _LINEAR_ADDRESS_MODE_SUPPORTED 0 244 245 #else 246 /* Linear mode */ 247 #define _LINEAR_ADDRESS_MODE_SUPPORTED 1 248 249 #endif 250 251 #define SUPPORT_2_FRAME_MIRROR 0 252 253 /* Because fix loop_div, lpll initial set is different between singal port and dual port */ 254 #define _FIX_LOOP_DIV_SUPPORTED 0 255 256 // You can only enable ENABLE_8_FIELD_SUPPORTED or ENABLE_16_FIELD_SUPPORTED. (one of them) 257 // 16 field mode include 8 field configurion in it. ENABLE_8_FIELD_SUPPORTED is specital case in T7 258 #define ENABLE_8_FIELD_SUPPORTED 1 259 #define ENABLE_16_FIELD_SUPPORTED 1 260 #define ENABLE_OPM_WRITE_SUPPORTED 0 261 #define ENABLE_YPBPR_PRESCALING_TO_ORIGINAL 0 262 #define ENABLE_VD_PRESCALING_TO_DOT75 0 263 #define ENABLE_NONSTD_INPUT_MCNR 0 264 #define ENABLE_REGISTER_SPREAD 1 265 266 #define ENABLE_REQUEST_FBL 1 267 #define DELAY_LINE_SC_UP 7 268 #define DELAY_LINE_SC_DOWN 8 269 270 #define CHANGE_VTT_STEPS 15 271 #define CHANGE_VTT_DELAY 5 272 273 #define SUPPORT_IMMESWITCH 1 274 #define SUPPORT_DVI_AUTO_EQ 1 275 #define SUPPORT_HDMI_RX_NEW_FEATURE 1 276 #define SUPPORT_DEVICE1 0 277 #define SUPPORT_SEAMLESS_ZAPPING 0 278 279 #define SUPPORT_OP2_TEST_PATTERN 1 280 #define SUPPORT_FRCM_MODE 0 281 #define SUPPORT_4K2K_PIP 0 282 283 // if H/W support 4k2k_60p output timing 284 #define HW_SUPPORT_4K2K_60P_OUTPUT FALSE 285 286 // Special frame lock means that the frame rates of input and output are the same in HW design spec. 287 #define SUPPORT_SPECIAL_FRAMELOCK FALSE 288 289 #define LD_ENABLE 1 290 291 #define FRC_INSIDE FALSE 292 293 /// need to refine and test 294 #define Eagle_Bringup 1 295 296 // 480p and 576p have FPLL problem in HV mode. 297 // So only allow HV mode for 720P 298 #define ONLY_ALLOW_HV_MODE_FOR_720P 0 299 300 #define DS_BUFFER_NUM_EX 6 301 #define DS_MAX_INDEX 6 302 #define DS_INDEX_DEPTH 16 303 304 #define ENABLE_64BITS_COMMAND 0 305 #define ENABLE_64BITS_SPREAD_MODE 0 306 #define ENABLE_DS_4_BASEADDR_MODE 0 // need enable both ENABLE_64BITS_COMMAND and ENABLE_64BITS_SPREAD_MODE first 307 #define DS_CMD_LEN_64BITS 8 308 309 // T12, T13 cannot use IP_HDMI for HV mode 310 // We must use IP_HDMI for HV mode, otherwise 480i 576i will have color space proble,m 311 //Note: if use IP_HDMI, MApi_XC_GetDEWindow() cannot get value correctly 312 // and IP_HDMI is set in MApi_XC_SetInputSource(), so cannot change dynamically 313 // Thus, chip could use this flag to determine whether could do HV mode or not. 314 #define SUPPORT_IP_HDMI_FOR_HV_MODE 0 315 316 // version1: edison: 4k2k@mm :mvop->dip->gop->ursa; 4k2k@hdmi:hdmi->ursa 317 // version2: nike: 318 // version3: napoli: frc: double frc and width 319 // version4: monaco: frcm and 2p 320 // version5: clippers: 4k2k@60 MVOP directly output to HVSP 321 #define HW_DESIGN_4K2K_VER (1) 322 323 #define HW_DESIGN_3D_VER (3) 324 #define HW_2DTO3D_SUPPORT TRUE 325 #define HW_2DTO3D_VER (3) 326 #define HW_2DTO3D_BYTE_PER_WORD (16) 327 #define HW_2DTO3D_PATCH TRUE //a1 u01:2d to 3d hw bug 328 #define HW_2DTO3D_BLOCK_DR_BUF_SIZE (0x1000) 329 330 //hw support fbl 3d or not. if support,can do SBS to LBL and SBS to SBS 331 #define HW_3D_SUPPORT_FBL (PM_R1BYTE(REG_CHIP_REVISION, 7:0) > 1) 332 333 //M10, A2, J2 ,A5,A6,A3,Agate HW will automatic use IPM fetch's reg setting to alignment IPM fetch, so skip sw alignment 334 //and for mirror cbcr swap, need check IPM fetch to decide if need swap 335 #define HW_IPM_FETCH_ALIGNMENT TRUE 336 //hw support 2 line mode deinterlace for interlace or not 337 #define HW_2LINEMODE_DEINTERLACE_SUPPORT FALSE 338 339 #define OSD_LAYER_NUM (3) 340 #define VIDEO_OSD_SWITCH_VER (1) 341 342 343 #define SUPPORT_IMMESWITCH 1 344 #define SUPPORT_DVI_AUTO_EQ 1 345 #define SUPPORT_MHL 0 346 #define SUPPORT_SECURITY_MODE 0 347 #define SUPPORT_HDMI_RX_NEW_FEATURE 1 348 349 #define XC_SUPPORT_4K2K 0 350 351 // Special frame lock means that the frame rates of input and output are the same in HW design spec. 352 #define SUPPORT_SPECIAL_FRAMELOCK FALSE 353 354 //device 1 is interlace out 355 #define XC_DEVICE1_IS_INTERLACE_OUT 0 356 357 #define FRC_INSIDE FALSE 358 359 #define HW_SUPPORT_FORCE_VSP_IN_DS_MODE FALSE 360 361 #define SUPPORT_OSD_HSLVDS_PATH 0 362 363 #define ENABLE_LOCK_IVS_OVS_FOR_ATV 1 364 #define ENABLE_SRC_SPREADER_FOR_ATV 0 365 366 // if H/W support interlace output timing 367 #define HW_SUPPORT_LOCK_FREQ_ONLY_WITHOUT_LOCK_PHASE TRUE 368 #define HW_SUPPORT_INTERLACE_OUTPUT FALSE 369 #define SUPPORT_HDMI20 0 370 371 #define HW_4K2K_VIP_PEAKING_LIMITATION 0 372 373 //------------------------------------------------------------------------------------------------- 374 // Register base 375 //------------------------------------------------------------------------------------------------- 376 #define BK_REG_L( x, y ) ((x) | (((y) << 1))) 377 #define BK_REG_H( x, y ) (((x) | (((y) << 1))) + 1) 378 379 380 // PM 381 #define REG_DDC_BASE 0x000400 382 #define REG_PM_SLP_BASE 0x000E00 383 #define REG_PM_SLEEP_BASE REG_PM_SLP_BASE//0x0E00//alex_tung 384 385 // NONPM 386 #define REG_MIU0_BASE 0x101200 387 #define REG_MIU1_BASE 0x100600 388 #define REG_CLKGEN2_BASE 0x100A00 389 #define REG_CHIPTOP_BASE 0x100B00 390 #define REG_CLKGEN0_BASE 0x100B00 // 0x1E00 - 0x1EFF 391 #define REG_UHC0_BASE 0x102400 392 #define REG_UHC1_BASE 0x100D00 393 #define REG_ADC_ATOP_BASE 0x102500 // 0x2500 - 0x25FF 394 #define REG_ADC_DTOP_BASE 0x102600 // 0x2600 - 0x26EF 395 #define REG_ADC_CHIPTOP_BASE 0x101E00 // 0x1E00 - 0x1EFF 396 #define REG_HDMI_BASE 0x102700 // 0x2700 - 0x27FF 397 #define REG_ADC_ATOPB_BASE 0x103D00 // 0x3D00 - 0x3DFF 398 #define REG_MHL_TMDS_BASE 0x122700 399 400 #define REG_HDMI2_BASE 0x101A00 401 #define REG_IPMUX_BASE 0x102E00 402 #define REG_MVOP_BASE 0x101400 403 #if ENABLE_REGISTER_SPREAD 404 #define REG_SCALER_BASE 0x130000 405 #else 406 #define REG_SCALER_BASE 0x102F00 407 #endif 408 #define REG_LPLL_BASE 0x103100 409 #define REG_MOD_BASE 0x103200 410 #define REG_AFEC_BASE 0x103500 411 #define REG_COMB_BASE 0x103600 412 413 #define REG_HDCPKEY_BASE 0x123A00 414 #define REG_DVI_ATOP_BASE 0x110900 415 #define REG_DVI_DTOP_BASE 0x110A00 416 #define REG_DVI_EQ_BASE 0x110A80 // EQ started from 0x80 417 #define REG_HDCP_BASE 0x110AC0 // HDCP started from 0xC0 418 #define REG_ADC_DTOPB_BASE 0x111200 // ADC DTOPB 419 #define REG_DVI_ATOP1_BASE 0x113200 420 #define REG_DVI_DTOP1_BASE 0x113300 421 #define REG_DVI_EQ1_BASE 0x113380 // EQ started from 0x80 422 #define REG_HDCP1_BASE 0x1133C0 // HDCP started from 0xC0 423 #define REG_DVI_ATOP2_BASE 0x113400 424 #define REG_DVI_ATOP3_BASE 0x162F00 425 #define REG_DVI_DTOP2_BASE 0x113500 426 #define REG_DVI_EQ2_BASE 0x113580 // EQ started from 0x80 427 #define REG_HDCP2_BASE 0x1135C0 // HDCP started from 0xC0 428 #define REG_DVI_PS_BASE 0x113600 // DVI power saving 429 #define REG_DVI_PS1_BASE 0x113640 // DVI power saving1 430 #define REG_DVI_PS2_BASE 0x113680 // DVI power saving2 431 #define REG_DVI_PS3_BASE 0x1136C0 // DVI power saving3 432 #define REG_DVI_DTOP3_BASE 0x113700 433 #define REG_DVI_EQ3_BASE 0x113780 // EQ started from 0x80 434 #define REG_HDCP3_BASE 0x1137C0 // HDCP started from 0xC0 435 436 #define REG_HDCP22_P0_BASE 0x162A00 437 #define REG_HDCP22_P1_BASE 0x162B00 438 #define REG_HDCP22_P2_BASE 0x162C00 439 #define REG_HDCP22_P3_BASE 0x162D00 440 441 #define REG_CHIP_ID_MAJOR 0x1ECC 442 #define REG_CHIP_ID_MINOR 0x1ECD 443 #define REG_CHIP_VERSION 0x1ECE 444 #define REG_CHIP_REVISION 0x1ECF 445 446 #define REG_CLKGEN0_BASE 0x100B00 447 #define REG_CLKGEN1_BASE 0x103300 448 449 #define L_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x) 450 #define H_CLKGEN0(x) BK_REG_H(REG_CLKGEN0_BASE, x) 451 #define L_CLKGEN1(x) BK_REG_L(REG_CLKGEN1_BASE, x) 452 #define H_CLKGEN1(x) BK_REG_H(REG_CLKGEN1_BASE, x) 453 454 455 456 // store bank 457 #define LPLL_BK_STORE 458 459 // restore bank 460 #define LPLL_BK_RESTORE 461 462 // switch bank 463 #define LPLL_BK_SWITCH(_x_) MDrv_WriteByte(REG_LPLL_BASE, _x_) 464 465 //------------------------------------------------------------------------------ 466 // Register configure 467 //------------------------------------------------------------------------------ 468 #define REG_CKG_DACA2 (REG_CLKGEN0_BASE + 0x4C ) //DAC out 469 #define CKG_DACA2_GATED BIT(0) 470 #define CKG_DACA2_INVERT BIT(1) 471 #define CKG_DACA2_MASK BMASK(3:2) 472 #define CKG_DACA2_VIF_CLK (0 << 2) 473 #define CKG_DACA2_VD_CLK (1 << 2) 474 #define CKG_DACA2_EXT_TEST_CLK (2 << 2) 475 #define CKG_DACA2_XTAL (3 << 2) 476 477 #define REG_CKG_DACB2 (REG_CLKGEN0_BASE + 0x4D ) //DAC out 478 #define CKG_DACB2_GATED BIT(0) 479 #define CKG_DACB2_INVERT BIT(1) 480 #define CKG_DACB2_MASK BMASK(3:2) 481 #define CKG_DACB2_VIF_CLK (0 << 2) 482 #define CKG_DACB2_VD_CLK (1 << 2) 483 #define CKG_DACB2_EXT_TEST_CLK (2 << 2) 484 #define CKG_DACB2_XTAL (3 << 2) 485 486 #define REG_CKG_FICLK_F1 (REG_CLKGEN0_BASE + 0xA2 ) // scaling line buffer, set to fclk if post scaling, set to idclk is pre-scaling 487 #define CKG_FICLK_F1_GATED BIT(0) 488 #define CKG_FICLK_F1_INVERT BIT(1) 489 #define CKG_FICLK_F1_MASK BMASK(3:2) 490 #define CKG_FICLK_F1_IDCLK1 (0 << 2) 491 #define CKG_FICLK_F1_FLK (1 << 2) 492 //#define CKG_FICLK_F1_XTAL (3 << 2) 493 494 #define REG_CKG_FICLK_F2 (REG_CLKGEN0_BASE + 0xA3 ) // scaling line buffer, set to fclk if post scaling, set to idclk is pre-scaling 495 #define CKG_FICLK_F2_GATED BIT(0) 496 #define CKG_FICLK_F2_INVERT BIT(1) 497 #define CKG_FICLK_F2_MASK BMASK(3:2) 498 #define CKG_FICLK_F2_IDCLK2 (0 << 2) 499 #define CKG_FICLK_F2_FLK (1 << 2) 500 //#define CKG_FICLK_F2_XTAL (3 << 2) 501 502 #define REG_CKG_FICLK2_F2 (REG_CLKGEN0_BASE + 0xA3 ) // scaling line buffer, set to fclk if post scaling, set to idclk is pre-scaling 503 #define CKG_FICLK2_F2_GATED BIT(4) 504 #define CKG_FICLK2_F2_INVERT BIT(5) 505 #define CKG_FICLK2_F2_MASK BMASK(7:6) 506 #define CKG_FICLK2_F2_IDCLK2 (0 << 6) 507 #define CKG_FICLK2_F2_FCLK (1 << 6) 508 509 #define REG_CKG_FCLK (REG_CLKGEN0_BASE + 0xA5 ) // after memory, before fodclk 510 #define CKG_FCLK_GATED BIT(0) 511 #define CKG_FCLK_INVERT BIT(1) 512 #define CKG_FCLK_MASK BMASK(5:2) 513 #define CKG_FCLK_170MHZ (0 << 2) 514 #define CKG_FCLK_CLK_MIU (1 << 2) 515 #define CKG_FCLK_CLK_ODCLK (2 << 2) 516 #define CKG_FCLK_216MHZ (3 << 2) 517 #define CKG_FCLK_192MHZ (4 << 2) 518 #define CKG_FCLK_SCPLL (5 << 2) 519 #define CKG_FCLK_0 (6 << 2) 520 #define CKG_FCLK_XTAL (7 << 2) 521 #define CKG_FCLK_XTAL_ CKG_FCLK_XTAL//(8 << 2) for A5 no XTAL 522 #define CKG_FCLK_DEFAULT CKG_FCLK_216MHZ 523 524 #define REG_CKG_ODCLK (REG_CLKGEN0_BASE + 0xA6 ) // output dot clock, usually select LPLL, select XTAL when debug 525 #define CKG_ODCLK_GATED BIT(0) 526 #define CKG_ODCLK_INVERT BIT(1) 527 #define CKG_ODCLK_MASK BMASK(5:2) 528 #define CKG_ODCLK_SC_PLL (0 << 2) 529 #define CKG_ODCLK_LPLL_DIV2 (5 << 2) 530 #define CKG_ODCLK_27M (6 << 2) 531 #define CKG_ODCLK_CLK_LPLL (7 << 2) 532 #define CKG_ODCLK_XTAL (8 << 2) 533 534 #define REG_CKG_IDCLK0 (REG_CLKGEN0_BASE + 0xA8 ) // off-line detect idclk 535 #define CKG_IDCLK0_GATED BIT(0) 536 #define CKG_IDCLK0_INVERT BIT(1) 537 #define CKG_IDCLK0_MASK BMASK(5:2) 538 #define CKG_IDCLK0_CLK_ADC (0 << 2) 539 #define CKG_IDCLK0_CLK_DVI (1 << 2) 540 #define CKG_IDCLK0_CLK_VD (2 << 2) 541 #define CKG_IDCLK0_CLK_DC0 (3 << 2) 542 #define CKG_IDCLK0_ODCLK (4 << 2) 543 #define CKG_IDCLK0_0 (5 << 2) 544 #define CKG_IDCLK0_CLK_VD_ADC (6 << 2) 545 #define CKG_IDCLK0_00 (7 << 2) // same as 5 --> also is 0 546 #define CKG_IDCLK0_XTAL (8 << 2) 547 548 #define REG_CKG_IDCLK1 (REG_CLKGEN0_BASE + 0xA9 ) // sub main window idclk 549 #define CKG_IDCLK1_GATED BIT(0) 550 #define CKG_IDCLK1_INVERT BIT(1) 551 #define CKG_IDCLK1_MASK BMASK(5:2) 552 #define CKG_IDCLK1_CLK_ADC (0 << 2) 553 #define CKG_IDCLK1_CLK_DVI (1 << 2) 554 #define CKG_IDCLK1_CLK_VD (2 << 2) 555 #define CKG_IDCLK1_CLK_DC0 (3 << 2) 556 #define CKG_IDCLK1_ODCLK (4 << 2) 557 #define CKG_IDCLK1_0 (5 << 2) 558 #define CKG_IDCLK1_CLK_VD_ADC (6 << 2) 559 #define CKG_IDCLK1_00 (7 << 2) // same as 5 --> also is 0 560 #define CKG_IDCLK1_XTAL (8 << 2) 561 562 #define REG_CKG_PRE_IDCLK1 (REG_CLKGEN0_BASE + 0xBC ) // pre-main window idclk 563 #define CKG_PRE_IDCLK1_MASK BMASK(5:3) 564 #define CKG_PRE_IDCLK1_CLK_ADC (0 << 3) 565 #define CKG_PRE_IDCLK1_CLK_DVI (1 << 3) 566 #define CKG_PRE_IDCLK1_CLK_MHL (2 << 3) 567 568 #define REG_CKG_IDCLK2 (REG_CLKGEN0_BASE + 0xAA ) // main window idclk 569 #define CKG_IDCLK2_GATED BIT(0) 570 #define CKG_IDCLK2_INVERT BIT(1) 571 #define CKG_IDCLK2_SHIFT 2 572 #define CKG_IDCLK2_MASK BMASK(5:2) 573 #define CKG_IDCLK2_CLK_ADC (0 << 2) 574 #define CKG_IDCLK2_CLK_DVI (1 << 2) 575 #define CKG_IDCLK2_CLK_VD (2 << 2) 576 #define CKG_IDCLK2_CLK_DC0 (3 << 2) 577 #define CKG_IDCLK2_ODCLK (4 << 2) 578 #define CKG_IDCLK2_0 (5 << 2) 579 #define CKG_IDCLK2_CLK_VD_ADC (6 << 2) 580 #define CKG_IDCLK2_00 (7 << 2) // same as 5 --> also is 0 581 #define CKG_IDCLK2_XTAL (8 << 2) 582 583 #define REG_CKG_PRE_IDCLK2 (REG_CLKGEN0_BASE + 0xBC ) // pre-main window idclk 584 #define CKG_PRE_IDCLK2_MASK BMASK(8:6) 585 #define CKG_PRE_IDCLK2_CLK_ADC (0 << 6) 586 #define CKG_PRE_IDCLK2_CLK_DVI (1 << 6) 587 #define CKG_PRE_IDCLK2_CLK_MHL (2 << 6) 588 589 #define REG_CKG_IDCLK3 (REG_CLKGEN0_BASE + (0x59<<1) ) 590 #define CKG_IDCLK3_GATED BIT(4) 591 #define CKG_IDCLK3_INVERT BIT(5) 592 #define CKG_IDCLK3_MASK BMASK(8:6) 593 #define CKG_IDCLK3_SHIFT 6 594 #define CKG_IDCLK3_CLK_ADC (0 << 6) 595 #define CKG_IDCLK3_CLK_DVI (1 << 6) 596 #define CKG_IDCLK3_CLK_VD (2 << 6) 597 #define CKG_IDCLK3_CLK_DC0 (3 << 6) 598 #define CKG_IDCLK3_ODCLK (4 << 6) 599 #define CKG_IDCLK3_0 (5 << 6) 600 #define CKG_IDCLK3_CLK_VD_ADC (6 << 6) 601 #define CKG_IDCLK3_00 (7 << 6) // same as 5 --> also is 0 602 #define CKG_IDCLK3_XTAL (8 << 6) 603 604 #define REG_CKG_PDW0 (REG_CLKGEN0_BASE + (0x5F<<1) ) 605 #define CKG_PDW0_GATED BIT(0) 606 #define CKG_PDW0_INVERT BIT(1) 607 #define CKG_PDW0_SHIFT 2 608 #define CKG_PDW0_MASK BMASK(5:2) 609 #define CKG_PDW0_CLK_ADC (0 << 2) 610 #define CKG_PDW0_CLK_DVI (1 << 2) 611 #define CKG_PDW0_CLK_VD (2 << 2) 612 #define CKG_PDW0_CLK_DC0 (3 << 2) 613 #define CKG_PDW0_ODCLK (4 << 2) 614 #define CKG_PDW0_0 (5 << 2) 615 #define CKG_PDW0_CLK_VD_ADC (6 << 2) 616 #define CKG_PDW0_00 (7 << 2) // same as 5 --> also is 0 617 #define CKG_PDW0_XTAL (8 << 2) 618 619 #define REG_CKG_OSDC (REG_CLKGEN0_BASE + 0xAB ) 620 #define CKG_OSDC_GATED BIT(0) 621 #define CKG_OSDC_INVERT BIT(1) 622 #define CKG_OSDC_MASK BMASK(3:2) 623 #define CKG_OSDC_CLK_LPLL_OSD (0 << 2) 624 625 #define REG_DE_ONLY_F3 (REG_CLKGEN0_BASE + 0xA0 ) 626 #define DE_ONLY_F3_MASK BIT(3) 627 628 #define REG_DE_ONLY_F2 (REG_CLKGEN0_BASE + 0xA0 ) 629 #define DE_ONLY_F2_MASK BIT(2) 630 631 #define REG_DE_ONLY_F1 (REG_CLKGEN0_BASE + 0xA0 ) 632 #define DE_ONLY_F1_MASK BIT(1) 633 634 #define REG_DE_ONLY_F0 (REG_CLKGEN0_BASE + 0xA0 ) 635 #define DE_ONLY_F0_MASK BIT(0) 636 637 638 #define REG_PM_DVI_SRC_CLK (REG_PM_SLP_BASE + 0x96) 639 #define REG_PM_DDC_CLK (REG_PM_SLP_BASE + 0x42) 640 641 #define REG_CLKGEN0_50_L (REG_CLKGEN0_BASE + 0xA0) 642 #define REG_CLKGEN0_51_L (REG_CLKGEN0_BASE + 0xA2) 643 #define REG_CLKGEN0_57_L (REG_CLKGEN0_BASE + 0xAE) 644 645 #define REG_MVOP_MIRROR (REG_MVOP_BASE + 0x76) 646 647 #define CLK_SRC_IDCLK2 0 648 #define CLK_SRC_FCLK 1 649 #define CLK_SRC_XTAL 3 650 651 #define MIU0_G0_REQUEST_MASK (REG_MIU0_BASE + 0x46) 652 #define MIU0_G1_REQUEST_MASK (REG_MIU0_BASE + 0x66) 653 #define MIU0_G2_REQUEST_MASK (REG_MIU0_BASE + 0x86) 654 #define MIU0_G3_REQUEST_MASK (REG_MIU0_BASE + 0xA6) 655 656 #define MIU1_G0_REQUEST_MASK (REG_MIU1_BASE + 0x46) 657 #define MIU1_G1_REQUEST_MASK (REG_MIU1_BASE + 0x66) 658 #define MIU1_G2_REQUEST_MASK (REG_MIU1_BASE + 0x86) 659 #define MIU1_G3_REQUEST_MASK (REG_MIU1_BASE + 0xA6) 660 661 #define MIU_SC_G0REQUEST_MASK (0x0000) 662 #define MIU_SC_G1REQUEST_MASK (0x0E00) 663 #define MIU_SC_G2REQUEST_MASK (0x0030) 664 #define MIU_SC_G3REQUEST_MASK (0x0000) 665 666 #define IP_DE_HSTART_MASK (0x1FFF) //BK_01_13 BK_03_13 667 #define IP_DE_HEND_MASK (0x1FFF) //BK_01_15 BK_03_15 668 #define IP_DE_VSTART_MASK (0x1FFF) //BK_01_12 BK_03_12 669 #define IP_DE_VEND_MASK (0x1FFF) //BK_01_14 BK_03_14 670 671 #define VOP_DE_HSTART_MASK (0x1FFF) //BK_10_04 672 #define VOP_DE_HEND_MASK (0x1FFF) //BK_10_05 673 #define VOP_DE_VSTART_MASK (0x0FFF) //BK_10_06 674 #define VOP_DE_VEND_MASK (0x0FFF) //BK_10_07 675 676 #define VOP_VTT_MASK (0x0FFF) //BK_10_0D 677 #define VOP_HTT_MASK (0x1FFF) //BK_10_0C 678 679 #define VOP_VSYNC_END_MASK (0x0FFF) //BK_10_03 680 #define VOP_DISPLAY_HSTART_MASK (0x1FFF) //BK_10_08 681 #define VOP_DISPLAY_HEND_MASK (0x1FFF) //BK_10_09 682 #define VOP_DISPLAY_VSTART_MASK (0x0FFF) //BK_10_0A 683 #define VOP_DISPLAY_VEND_MASK (0x0FFF) //BK_10_0B 684 685 686 687 #define HW_DESIGN_LD_VER (1) 688 689 #define FPLL_THRESH_MODE_SUPPORT 0 690 691 #define ADC_CENTER_GAIN 0x1000 692 #define ADC_CENTER_OFFSET 0x0800 693 #define ADC_GAIN_BIT_CNT 14 694 #define ADC_OFFSET_BIT_CNT 13 695 696 #define ADC_VGA_DEFAULT_GAIN_R 0x1000 697 #define ADC_VGA_DEFAULT_GAIN_G 0x1000 698 #define ADC_VGA_DEFAULT_GAIN_B 0x1000 699 #define ADC_VGA_DEFAULT_OFFSET_R 0x0000 700 #define ADC_VGA_DEFAULT_OFFSET_G 0x0000 701 #define ADC_VGA_DEFAULT_OFFSET_B 0x0000 702 #define ADC_YPBPR_DEFAULT_GAIN_R 0x1212 703 #define ADC_YPBPR_DEFAULT_GAIN_G 0x11AA 704 #define ADC_YPBPR_DEFAULT_GAIN_B 0x1212 705 #define ADC_YPBPR_DEFAULT_OFFSET_R 0x0800 706 #define ADC_YPBPR_DEFAULT_OFFSET_G 0x0100 707 #define ADC_YPBPR_DEFAULT_OFFSET_B 0x0800 708 #define ADC_SCART_DEFAULT_GAIN_R 0x1000 709 #define ADC_SCART_DEFAULT_GAIN_G 0x1000 710 #define ADC_SCART_DEFAULT_GAIN_B 0x1000 711 #define ADC_SCART_DEFAULT_OFFSET_R 0x0100 712 #define ADC_SCART_DEFAULT_OFFSET_G 0x0100 713 #define ADC_SCART_DEFAULT_OFFSET_B 0x0100 714 715 /////////////////////////////////////////////// 716 // Enable Hardware auto gain/offset 717 #define ADC_HARDWARE_AUTOOFFSET_RGB ENABLE 718 #define ADC_HARDWARE_AUTOOFFSET_YPBPR ENABLE 719 #define ADC_HARDWARE_AUTOOFFSET_SCARTRGB ENABLE 720 #define ADC_HARDWARE_AUTOGAIN_SUPPORTED ENABLE 721 #define ADC_VGA_FIXED_GAIN_R 0x1796 722 #define ADC_VGA_FIXED_GAIN_G 0x1796 723 #define ADC_VGA_FIXED_GAIN_B 0x1796 724 #define ADC_VGA_FIXED_OFFSET_R 0x0000 725 #define ADC_VGA_FIXED_OFFSET_G 0x0000 726 #define ADC_VGA_FIXED_OFFSET_B 0x0000 727 #define ADC_YPBPR_FIXED_GAIN_R 0x14B7 728 #define ADC_YPBPR_FIXED_GAIN_G 0x1441 729 #define ADC_YPBPR_FIXED_GAIN_B 0x14B7 730 #define ADC_YPBPR_FIXED_OFFSET_R 0x0800 731 #define ADC_YPBPR_FIXED_OFFSET_G 0x0100 732 #define ADC_YPBPR_FIXED_OFFSET_B 0x0800 733 #define ADC_SCART_FIXED_GAIN_R 0x1796 734 #define ADC_SCART_FIXED_GAIN_G 0x1796 735 #define ADC_SCART_FIXED_GAIN_B 0x1796 736 #define ADC_SCART_FIXED_OFFSET_R 0x0000 737 #define ADC_SCART_FIXED_OFFSET_G 0x0000 738 #define ADC_SCART_FIXED_OFFSET_B 0x0000 739 740 #endif /* MHAL_XC_CONFIG_H */ 741 742