1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 #ifndef _AUDIO_COMM2_H_ 79 #define _AUDIO_COMM2_H_ 80 81 82 #include "audio_mbox2.h" 83 #include "ddr_config.h" 84 85 #ifdef _COMPILE_DSP_ 86 #include "Sys_def.h" 87 #endif 88 89 /************************************************ 90 * �ЫO�� Utopia �M DSP �̪��o���ɮפ@�P 91 * 92 * 1. ���Ѥ��n�� ! 93 * 2. �ŧi���n�� .const xxxx = ????; 94 ************************************************/ 95 96 97 /********************************************************* 98 * Version Control 99 *********************************************************/ 100 #define system_version_num 0x000B6E 101 #define dde_version_num 0xD20053 102 #define ms10_dde_version_num 0xD800CA 103 #define btscEnc_version_num 0xEF0127 104 #define fmTx_version_num 0xED010D 105 106 #define AUDIO_DSP2_VERSION (system_version_num + dde_version_num + ms10_dde_version_num + btscEnc_version_num + fmTx_version_num) 107 108 109 /********************************************************* 110 * system define 111 *********************************************************/ 112 #define DSP2_DDP_HDMI_BYPASS_EN 0 113 114 /* ASND System Channels */ 115 #define SE_PROCESS_FETCH_CHANNELS 2 // SE_Buffer input channels 116 #define SE_PROCESS_STORE_CHANNELS 4 // SE_Buffer output channels 117 #define SPDIF_DELAY_STORE_CHANNELS 2 // SPDIF Buffer channels 118 #define HDMI_DELAY_STORE_CHANNELS 8 // HDMI Buffer channels, 8:_deciFs4x_ 119 #define DELAY_FUNCTION_STORE_CHANNELS 2 // Delay function Buffer channels 120 #define MULTI_CH_INPUT_DELAY_STORE_CHANNELS 6 // multi-channel input delay function Buffer channels 121 122 /* DSP Audio Delay Setting */ 123 #define AUDIO_DELAY_FS 48 // fs = 48kHz 124 #define SPDIF_DELAY_FS 48 125 #define HDMI_DELAY_FS 48 126 #define DMA24BIT_BYTES_IN_WORDS 3 127 #define DMA16BIT_BYTES_IN_WORDS 2 128 129 #define AUDIO_DELAY_LOWER_BOUND 0x20 // min main audio delay , 0x20 = 32 ms 130 #define SPDIF_DELAY_LOWER_BOUND 0x05 // min spdif audio delay, 0x05 = 5 ms 131 #define HDMI_DELAY_LOWER_BOUND 0x05 // min hdmi audio delay , 0x05 = 5 ms 132 #define KTV_DELAY_LOWER_BOUND 0x14 // min ktv audio delay , 0x14 = 20 ms 133 #define AUDIO_DELAY_UPPER_BOUND ((SE_MAIN_IN_DRAM_SIZE/SE_PROCESS_FETCH_CHANNELS + SE_MAIN_OUT_DRAM_SIZE/SE_PROCESS_STORE_CHANNELS)/DMA24BIT_BYTES_IN_WORDS/AUDIO_DELAY_FS) //unit : ms 134 #define SPDIF_DELAY_UPPER_BOUND ((SPDIF_DLY_DRAM_SIZE/SPDIF_DELAY_STORE_CHANNELS)/DMA16BIT_BYTES_IN_WORDS/SPDIF_DELAY_FS) //unit : ms 135 #define HDMI_DELAY_UPPER_BOUND ((SE_HDMI_DLY_DRAM_SIZE/HDMI_DELAY_STORE_CHANNELS)/DMA16BIT_BYTES_IN_WORDS/HDMI_DELAY_FS) //unit : ms 136 137 #define CH5_INPUT_DLY_UPPER_BOUND ((CH5_INPUT_DLY_DRAM_SIZE/DELAY_FUNCTION_STORE_CHANNELS)/DMA24BIT_BYTES_IN_WORDS/AUDIO_DELAY_FS) //unit : ms 138 #define CH6_INPUT_DLY_UPPER_BOUND ((CH6_INPUT_DLY_DRAM_SIZE/DELAY_FUNCTION_STORE_CHANNELS)/DMA24BIT_BYTES_IN_WORDS/AUDIO_DELAY_FS) //unit : ms 139 #define MULTI_CH_INPUT_DLY_UPPER_BOUND ((MULTI_CH_INPUT_DLY_DRAM_SIZE/MULTI_CH_INPUT_DELAY_STORE_CHANNELS)/DMA24BIT_BYTES_IN_WORDS/AUDIO_DELAY_FS) //unit : ms 140 141 /* Audio Ease */ 142 #define AUDIO_EASE_TYPE_LINEAR 0 143 #define AUDIO_EASE_TYPE_INCUBIC 1 144 #define AUDIO_EASE_TYPE_OUTCUBIC 2 145 #define AUDIO_EASE_TYPE_INOUTCUBIC 3 146 147 #define AUDIO_EASE_CH_NONE 0 148 #define AUDIO_EASE_CH_A 1 149 #define AUDIO_EASE_CH_B 2 150 151 /************************************************ 152 * DSP sram address mapping 153 ************************************************/ 154 /* DSP SRAM Segment */ 155 /* CM */ 156 #define DSP2_CM_MAIN_ADDR 0x0 157 #define DSP2_CM_MAIN_SIZE 0x2000 158 #define DSP2_CM_CODE1_ADDR 0x2000 159 #define DSP2_CM_CODE1_SIZE 0x0100 160 #define DSP2_CM_CODE2_ADDR 0x2100 161 #define DSP2_CM_CODE2_SIZE 0x0000 162 163 /* PM */ 164 #define DSP2_PM_MAIN_ADDR 0x2100 165 #define DSP2_PM_MAIN_SIZE 0x02FF 166 #define DSP2_PM_SEG1_ADDR 0x23FF 167 #define DSP2_PM_SEG1_SIZE 0x2401 168 #define DSP2_PM_SEG2_ADDR 0x4800 169 #define DSP2_PM_SEG2_SIZE 0x0000 170 171 /* Prefetch */ 172 #define DSP2_PM_PREFETCH_DSPADDR 0x10000 // check "arch.sys" 173 #define DSP2_PM_PREFETCH_DDRADDR DSP2_PM_PREFETCH_DSPADDR*3/BYTES_IN_MIU_LINE 174 #define DSP2_PM_PREFETCH2_DSPADDR 0x12000 // check "arch.sys" 175 #define DSP2_PM_PREFETCH2_DDRADDR DSP2_PM_PREFETCH2_DSPADDR*3/BYTES_IN_MIU_LINE 176 177 /* DM */ 178 #define DSP2_DM_MAIN_ADDR 0x2F00 179 #define DSP2_DM_MAIN_SIZE 0x1100 180 #define DSP2_DM_SEG1A_ADDR 0x0 181 #define DSP2_DM_SEG1A_SIZE 0x2F00 182 #define DSP2_DM_SEG1B_ADDR 0x2F00 183 #define DSP2_DM_SEG1B_SIZE 0x0 184 #define DSP2_DM_SEG2_ADDR 0x2F00 185 #define DSP2_DM_SEG2_SIZE 0x0 186 187 /* XBox */ 188 #define DSP2_XBOX_MAIN_ADDR 0xB800 189 #define DSP2_XBOX_MAIN_SIZE 0x200 190 191 #define ENC_INIT_ADDR DSP2_CM_CODE1_ADDR 192 #define ENC_CM_SEG _cm_code1 193 #define ENC_PM_SEG _pm_ovly1 194 #define ENC_CACHE_SEG _ext_code05 195 #define ENC_FETCH_SEG _ext_fetch1 196 #define ENC_DM_SEG _dm_ovly1a 197 #define ENC_PM_SEG_ADDR DSP2_PM_SEG1_ADDR 198 #define ENC_DM_SEG_ADDR DSP2_DM_SEG1A_ADDR 199 200 /* SND DSP PM vars */ 201 /* common */ 202 #define DSP2PmAddr_mainVer (DSP2_PM_MAIN_ADDR) //0x1900 203 #define DSP2PmAddr_alg1Ver (DSP2_PM_SEG1_ADDR) //0x1BFF // decoder 2 version 204 #define DSP2PmAddr_alg2Ver (DSP2_PM_MAIN_ADDR-1) 205 206 #define DSP2PmAddr_peq48KCoeffAddr (DSP2PmAddr_mainVer + 1) 207 #define DSP2PmAddr_peq32KCoeffAddr (DSP2PmAddr_peq48KCoeffAddr) 208 #define DSP2PmAddr_peqscale48KAddr (DSP2PmAddr_peq48KCoeffAddr + 40 ) 209 #define DSP2PmAddr_peqbandEnAddr (DSP2PmAddr_peqscale48KAddr + 8 ) 210 #define DSP2PmAddr_peqbandDoubleAddr (DSP2PmAddr_peqbandEnAddr + 1 ) 211 #define DSP2PmAddr_hpf48KCoeffAddr (DSP2PmAddr_peqbandDoubleAddr + 1 ) 212 #define DSP2PmAddr_toneSelectAddr (DSP2PmAddr_hpf48KCoeffAddr + 5 ) 213 #define DSP2PmAddr_bass48KCoeffAddr (DSP2PmAddr_toneSelectAddr + 1 ) 214 #define DSP2PmAddr_bassscale48KAddr (DSP2PmAddr_bass48KCoeffAddr + 5 ) 215 #define DSP2PmAddr_treble48KCoeffAddr (DSP2PmAddr_bassscale48KAddr + 1 ) 216 #define DSP2PmAddr_treblescale48KAddr (DSP2PmAddr_treble48KCoeffAddr + 5 ) 217 #define DSP2PmAddr_VolEaseAddr (DSP2PmAddr_treblescale48KAddr + 1 ) 218 219 /* ATV_Enc */ 220 #define DSP2_PM_ATV_Enc_input_attenuation_ADDR (DSP2PmAddr_alg1Ver+1) 221 #define DSP2_PM_ATV_Enc_output_scaling_ADDR (DSP2PmAddr_alg1Ver+2) 222 #define DSP2_PM_BTSC_Enc_output_M_gain_ADDR (DSP2PmAddr_alg1Ver+3) 223 #define DSP2_PM_BTSC_Enc_output_D_gain_ADDR (DSP2PmAddr_alg1Ver+4) 224 #define DSP2_PM_BTSC_Enc_output_SAP_gain_ADDR (DSP2PmAddr_alg1Ver+5) 225 226 /* SND DSP DM vars */ 227 228 /* Extra Box Address */ 229 230 /* sys_param */ 231 #define DSP2XboxAddr_mainVer 0xB800 232 #define DSP2XboxAddr_mainAudioDelay (DSP2XboxAddr_mainVer + 0x01) 233 #define DSP2XboxAddr_spdifDelay (DSP2XboxAddr_mainVer + 0x02) 234 #define DSP2XboxAddr_hpDelay (DSP2XboxAddr_mainVer + 0x03) 235 #define DSP2XboxAddr_hdmiNonPcmSts (DSP2XboxAddr_mainVer + 0x04) 236 #define DSP2XboxAddr_btFrameSize (DSP2XboxAddr_mainVer + 0x05) 237 #define DSP2XboxAddr_ipSecurity (DSP2XboxAddr_mainVer + 0x06) 238 #define DSP2XboxAddr_hdmiDelay (DSP2XboxAddr_mainVer + 0x07) 239 #define DSP2XboxAddr_ch5InputDelay (DSP2XboxAddr_mainVer + 0x08) 240 #define DSP2XboxAddr_ch6InputDelay (DSP2XboxAddr_mainVer + 0x09) 241 #define DSP2XboxAddr_multiChInputDelay (DSP2XboxAddr_mainVer + 0x0A) 242 243 #define DSP2XboxAddr_peq48KCoeffAddr (DSP2XboxAddr_mainVer + 0x10) // len 40 244 #define DSP2XboxAddr_peq32KCoeffAddr (DSP2XboxAddr_peq48KCoeffAddr) 245 #define DSP2XboxAddr_peqscale48KAddr (DSP2XboxAddr_mainVer + 0x38) // len 8 246 #define DSP2XboxAddr_peqbandEnAddr (DSP2XboxAddr_mainVer + 0x40) // len 1 247 #define DSP2XboxAddr_peqbandDoubleAddr (DSP2XboxAddr_mainVer + 0x41) // len 1 248 #define DSP2XboxAddr_hpf48KCoeffAddr (DSP2XboxAddr_mainVer + 0x42) // len 5 249 #define DSP2XboxAddr_toneSelectAddr (DSP2XboxAddr_mainVer + 0x47) // len 1 250 #define DSP2XboxAddr_bass48KCoeffAddr (DSP2XboxAddr_mainVer + 0x48) // len 5 251 #define DSP2XboxAddr_bassscale48KAddr (DSP2XboxAddr_mainVer + 0x4D) // len 1 252 #define DSP2XboxAddr_treble48KCoeffAddr (DSP2XboxAddr_mainVer + 0x4E) // len 5 253 #define DSP2XboxAddr_treblescale48KAddr (DSP2XboxAddr_mainVer + 0x53) // len 1 254 #define DSP2XboxAddr_VolEaseAddr (DSP2XboxAddr_mainVer + 0x54) // len 9 255 256 #define DSP2XboxAddr_peqUpdateFlag (DSP2XboxAddr_mainVer + 0x5D) // len 1 257 #define DSP2XboxAddr_hpUpdateFlag (DSP2XboxAddr_mainVer + 0x5E) // len 1 258 #define DSP2XboxAddr_bassUpdateFlag (DSP2XboxAddr_mainVer + 0x5F) // len 1 259 #define DSP2XboxAddr_trebleUpdateFlag (DSP2XboxAddr_mainVer + 0x60) // len 1 260 #define DSP2XboxAddr_toneUpdateFlag (DSP2XboxAddr_mainVer + 0x61) // len 1 261 #define DSP2XboxAddr_easeAUpdateFlag (DSP2XboxAddr_mainVer + 0x62) // len 1 262 #define DSP2XboxAddr_easeBUpdateFlag (DSP2XboxAddr_mainVer + 0x63) // len 1 263 264 #define DSP2XboxAddr_ATVEnc_input_attenuation_ADDR (DSP2XboxAddr_mainVer + 0x64) // len 1 265 #define DSP2XboxAddr_ATVEnc_output_scaling_ADDR (DSP2XboxAddr_ATVEnc_input_attenuation_ADDR + 1) 266 #define DSP2XboxAddr_BTSCEnc_output_M_gain_ADDR (DSP2XboxAddr_ATVEnc_output_scaling_ADDR + 1) 267 #define DSP2XboxAddr_BTSCEnc_output_D_gain_ADDR (DSP2XboxAddr_BTSCEnc_output_M_gain_ADDR + 1) 268 #define DSP2XboxAddr_BTSCEnc_output_SAP_gain_ADDR (DSP2XboxAddr_BTSCEnc_output_D_gain_ADDR + 1) 269 270 /* sys_info */ 271 #define DSP2XboxAddr_IO_Info1 0xB900 272 #define IO_INFO1_DAC1_OUT 0x0000 273 #define IO_INFO1_DAC2_OUT 0x0002 274 #define IO_INFO1_DAC3_OUT 0x0004 275 #define IO_INFO1_DAC4_OUT 0x0006 276 #define IO_INFO1_IIS1_OUT 0x0008 277 #define IO_INFO1_SPDIF_OUT 0x000A 278 #define IO_INFO1_HDMI_OUT 0x000C 279 280 #define DSP2XboxAddr_IO_Info2 DSP2XboxAddr_IO_Info1 + 0x000E 281 #define IO_INFO2_MUL_CH1 0x0000 282 #define IO_INFO2_MUL_CH2 0x0002 283 #define IO_INFO2_MUL_CH3 0x0004 284 #define IO_INFO2_MUL_CH4 0x0006 285 #define IO_INFO2_RAW 0x0008 286 #define IO_INFO2_RAW_DELAY 0x000A 287 #define IO_INFO2_RAW_DELAY_SE 0x000C 288 #define IO_INFO2_SCART 0x000E 289 #define IO_INFO2_KTV 0x0010 290 #define IO_INFO2_MUL_CH6 0x0012 291 #define IO_INFO2_SPDIF_DATA 0x0014 292 #define IO_INFO2_RESERVED4 0x0016 293 #define IO_INFO2_SINTONE 0x0018 294 #define IO_INFO2_MUL_CH8 0x001A 295 #define IO_INFO2_GPA_FS 0x001C 296 #define IO_INFO2_GPB_FS 0x001D 297 #define IO_INFO2_GPC_FS 0x001E 298 #define IO_INFO2_ALSA_MODE 0x001F 299 300 301 /* common */ 302 #define DSP2XboxAddr_dec1_signal_energy (DSP2XboxAddr_IO_Info2 + 0x0020) // len 1 303 #define DSP2XboxAddr_pcmCapture_overflow (DSP2XboxAddr_IO_Info2 + 0x0021) // len 1 304 #define DSP2XboxAddr_pcmCapture_underflow (DSP2XboxAddr_IO_Info2 + 0x0022) // len 1 305 #define DSP2XboxAddr_pcmCapture_volume (DSP2XboxAddr_IO_Info2 + 0x0023) // len 1 306 #define DSP2XboxAddr_pcmCapture2_overflow (DSP2XboxAddr_IO_Info2 + 0x0024) // len 1 307 #define DSP2XboxAddr_pcmCapture2_underflow (DSP2XboxAddr_IO_Info2 + 0x0025) // len 1 308 #define DSP2XboxAddr_pcmCapture2_volume (DSP2XboxAddr_IO_Info2 + 0x0026) // len 1 309 #define DSP2XboxAddr_pcmCapture3_overflow (DSP2XboxAddr_IO_Info2 + 0x0027) // len 1 310 #define DSP2XboxAddr_pcmCapture3_underflow (DSP2XboxAddr_IO_Info2 + 0x0028) // len 1 311 #define DSP2XboxAddr_pcmCapture3_volume (DSP2XboxAddr_IO_Info2 + 0x0029) // len 1 312 #define DSP2XboxAddr_swDmaRdr_ctrlBase (DSP2XboxAddr_IO_Info2 + 0x002A) // len 11 313 314 #define DSP2XboxAddr_hdmi_npcm_lock (DSP2XboxAddr_IO_Info2 + 0x0035) // len 1 315 #define DSP2XboxAddr_hdmi_unstable_protect (DSP2XboxAddr_IO_Info2 + 0x0036) // len 1 316 #define DSP2XboxAddr_hdmi_unstable_threshold (DSP2XboxAddr_IO_Info2 + 0x0037) // len 1 317 #define DSP2XboxAddr_hdmi_decimation_mode_flag (DSP2XboxAddr_IO_Info2 + 0x0038) // len 2 318 319 #define DSP2XboxAddr_mips_crisis_flag (DSP2XboxAddr_IO_Info2 + 0x003A) // len 1 320 321 /* basic sound effect */ 322 #define DSP2XboxAddr_AvcSOffsetAddr (DSP2XboxAddr_IO_Info2 + 0x003B) // len 1 323 #define DSP2XboxAddr_KTV_XAGain (DSP2XboxAddr_IO_Info2 + 0x003C) // len 1 324 #define DSP2XboxAddr_KTV_XBGain (DSP2XboxAddr_IO_Info2 + 0x003D) // len 1 325 #define DSP2XboxAddr_Multi_Channel_VOL (DSP2XboxAddr_IO_Info2 + 0x003E) // len 1 326 327 328 /******************************************************************** 329 * Decoder default setting 330 ********************************************************************/ 331 /* SIF DSP PM vars */ 332 /* 333 #define ADDR_gain_base_2 0x2521 //B860 334 #define ADDR_thr_base_2 0x2620 335 #define ADDR_pfir_base_2 0x2690 336 // for SIF BTSC DSP PM vars // 337 #define BTSC_COMPILE_OPTION_Addr_2 0x25F1 // len 1 338 #define BTSC_OUTPUT_GAIN_Addr_2 0x2621 // len 2 339 #define BTSC_THRESHOLD_Addr_2 0x2623 // len 10 340 #define MTS_OUTPUT_GAIN_Addr_2 0x2634 //len 6 341 #define SIF_AGC_THRESHOLD_Addr_2 0x252D //len 3 342 343 /// PAL gain setting address 344 #define ADDR_fm_stdM_gain_2 ADDR_gain_base_2 // len = 4 345 #define ADDR_fm_stdX_gain_2 ADDR_fm_stdM_gain_2+4 // len = 4 346 #define ADDR_nicam_gain_2 ADDR_fm_stdX_gain_2+4 // len = 2 347 #define ADDR_am_gain_2 ADDR_nicam_gain_2+2 // len = 2 348 #define ADDR_agc_gain_2 ADDR_am_gain_2+2 // len = 24 349 350 // PAL threshold setting address 351 #define ADDR_a2_stdM_thr_2 ADDR_thr_base_2 // len = 15 352 #define ADDR_a2_stdBG_thr_2 ADDR_a2_stdM_thr_2+15 // len = 15 353 #define ADDR_a2_stdDK_thr_2 ADDR_a2_stdBG_thr_2+15 // len = 15 354 #define ADDR_a2_stdI_thr_2 ADDR_a2_stdDK_thr_2+15 // len = 4 355 #define ADDR_am_thr_2 ADDR_a2_stdI_thr_2+4 // len = 3 356 #define ADDR_hidev_stdM_thr_2 ADDR_am_thr_2+3 // len = 4 357 #define ADDR_hidev_stdBG_thr_2 ADDR_hidev_stdM_thr_2+4 // len = 4 358 #define ADDR_hidev_stdDK_thr_2 ADDR_hidev_stdBG_thr_2+4 // len = 4 359 #define ADDR_hidev_stdI_thr_2 ADDR_hidev_stdDK_thr_2+4 // len = 4 360 #define ADDR_nicam_stdBG_pherr_thr_2 ADDR_hidev_stdI_thr_2+4 //len = 3 361 #define ADDR_nicam_stdI_pherr_thr_2 ADDR_nicam_stdBG_pherr_thr_2+3 // len = 3 362 #define ADDR_a2_bg_nicam_fm_nsr_thr_2 0x246F // len = 1 363 #define ADDR_a2_dk_nicam_fm_nsr_thr_2 0x2470 // len = 1 364 365 // pfir setting address 366 #define ADDR_hidev_demfir_2 ADDR_pfir_base_2 // len = 15 367 #define ADDR_fm_ch1_pfir_2 ADDR_hidev_demfir_2+16 // len = 30 368 #define ADDR_fm_ch2_pfir_2 ADDR_fm_ch1_pfir_2+30 // len = 30 369 #define ADDR_hidev_lv1_pfir_2 ADDR_fm_ch2_pfir_2+30 // len = 20 370 #define ADDR_hidev_lv2_pfir_2 ADDR_hidev_lv1_pfir_2+20 // len = 20 371 #define ADDR_hidev_lv3_pfir_2 ADDR_hidev_lv2_pfir_2+20 // len = 20 372 373 // BTSC threshold setting address 374 #define HIDEV_NSR_THRESHOLD_Addr_2 BTSC_THRESHOLD_Addr_2+10 // len 2 375 #define BTSC_MONO_AMP_THRESHOLD_Addr_2 HIDEV_NSR_THRESHOLD_Addr_2+2 // len 2 376 #define HIDEV_AMP_THRESHOLD_Addr_2 BTSC_MONO_AMP_THRESHOLD_Addr_2+2 // len 2 377 378 #define BTSC_SAP_PHASE_DIFF_CLIP_THR_Addr_2 HIDEV_AMP_THRESHOLD_Addr_2+2 // len 1 379 #define BTSC_PILOT_DEBOUNCE_THRESHOLD_Addr_2 MTS_OUTPUT_GAIN_Addr_2+6 // len 3 380 #define BTSC_SAP_ON_DETECTION_DEBOUNCE_THRESHOLD_Addr_2 BTSC_PILOT_DEBOUNCE_THRESHOLD_Addr_2+3 // len 1 381 */ 382 383 /************************************************ 384 * Below is MailBox config 385 *************************************************/ 386 387 /************************************************ 388 * MCU to DSP mailbox 389 ************************************************/ 390 /* SIF */ 391 #define M2S_MBOX_SIF_CMD_STANDARD MB_2DC0 392 #define M2S_MBOX_SIF_CMD_PFIRBANDWIDTH MB_2DC2 393 #define M2S_MBOX_SIF_CMD_MODE1 MB_2DC4 394 #define M2S_MBOX_SIF_CMD_MODE2 MB_2DC6 395 396 /* ATV Encoder */ 397 #define M2S_MBOX_ATVEnc_MODE_CTRL MB_2DC0 398 399 /* SPDIF */ 400 #define M2S_MBOX_SPDIF_SETTING MB_2D8E 401 #define M2S_MBOX_HDMI_SETTING MB_2D8E 402 #define MBOX_SPDIF_SETTING_BIT_MUTE MBOX_BIT0 403 #define MBOX_SPDIF_SETTING_BIT_NPCMSEL MBOX_BIT1 404 #define MBOX_SPDIF_SETTING_R2_NPCM_SELBIT MBOX_BIT2 405 #define MBOX_SPDIF_SETTING_DVB2_NPCM_SELBIT MBOX_BIT3 406 #define MBOX_SPDIF_SETTING_MINUS_11DB_BIT MBOX_BIT5 407 #define MBOX_HDMI_SETTING_BIT_NPCMSEL MBOX_BIT13 408 #define MBOX_HDMI_SETTING_BIT_HDMI_OUTPATH MBOX_BIT14 409 #define MBOX_HDMI_SETTING_BIT_MUTE MBOX_BIT15 410 411 #define M2S_MBOX_DOLBY_LOUDNESS_INFO MB_2D98 412 #define MBOX_DOLBY_LOUDNESS_ENABLE_BIT MBOX_BIT15 413 #define MBOX_DOLBY_LOUDNESS_ATSC_MODE MBOX_BIT14 414 #define MBOX_DOLBY_LOUDNESS_OTHER_MODE MBOX_BIT13 415 416 /* Sound effect */ 417 #define M2S_MBOX_AUOUT0_VOL MB_2D00 418 #define M2S_MBOX_AUOUT1_VOL MB_2D02 419 #define M2S_MBOX_AUOUT2_VOL MB_2D04 420 #define M2S_MBOX_AUOUT3_VOL MB_2D06 421 #define M2S_MBOX_I2S_VOL MB_2D08 422 #define M2S_MBOX_SPDIF_VOL MB_2D0A 423 #define M2S_MBOX_SRC_VOL MB_2D0C 424 #define M2S_MBOX_HDMI_VOL MB_2D0E //STB only 425 #define M2S_MBOX_I2S2_VOL MB_2D0E 426 #define M2S_MBOX_PRESCALE MB_2D10 427 428 #define M2S_MBOX_EQ1_GAIN MB_2D14 //[15:8] 429 #define M2S_MBOX_BASS_CTRL MB_2D14 //[7:0] 430 #define M2S_MBOX_EQ2_GAIN MB_2D16 //[15:8] 431 #define M2S_MBOX_TREBLE_CTRL MB_2D16 //[7:0] 432 #define M2S_MBOX_EQ3_GAIN MB_2D18 //[15:8] 433 #define M2S_MBOX_SUPBASS_CTRL MB_2D18 //[7:0] 434 #define M2S_MBOX_EQ4_GAIN MB_2D1A //[15:8] 435 #define M2S_MBOX_EQ5_GAIN MB_2D1C //[15:8] 436 #define M2S_MBOX_BAL_CTRL MB_2D1E 437 438 #define M2S_MBOX_SNDEFF_EN MB_2D20 439 #define M2S_MBOX_STEREO_EN_BIT MBOX_BIT15 440 #define M2S_MBOX_DRC_EN_BIT MBOX_BIT13 441 #define M2S_MBOX_AVC_EN_BIT MBOX_BIT12 442 #define M2S_MBOX_TONE_EN_BIT MBOX_BIT11 443 #define M2S_MBOX_SPATIAL_EN_BIT MBOX_BIT10 444 #define M2S_MBOX_VOLBAL_EN_BIT MBOX_BIT9 445 #define M2S_MBOX_GEQ_EN_BIT MBOX_BIT7 446 #define M2S_MBOX_EASE_EN_BIT MBOX_BIT6 447 #define M2S_MBOX_BASSBOOST_EN_BIT MBOX_BIT5 448 #define M2S_MBOX_ECHO_EN_BIT MBOX_BIT4 449 #define M2S_MBOX_DC_REMOVE_EN_BIT MBOX_BIT3 450 #define M2S_MBOX_HPF_EN_BIT MBOX_BIT2 451 #define M2S_MBOX_COEFFUPDATE_EN_BIT MBOX_BIT1 452 #define M2S_MBOX_PEQ_EN_BIT MBOX_BIT0 453 454 #define M2S_MBOX_VOLUME_EN MB_2D22 455 #define M2S_MBOX_VOL_DAC0_EN_BIT MBOX_BIT0 456 #define M2S_MBOX_VOL_DAC1_EN_BIT MBOX_BIT1 457 #define M2S_MBOX_VOL_DAC2_EN_BIT MBOX_BIT2 458 #define M2S_MBOX_VOL_DAC3_EN_BIT MBOX_BIT3 459 #define M2S_MBOX_VOL_I2S0_EN_BIT MBOX_BIT4 460 #define M2S_MBOX_VOL_I2S1_EN_BIT MBOX_BIT5 461 #define M2S_MBOX_VOL_I2S2_EN_BIT MBOX_BIT6 462 #define M2S_MBOX_VOL_I2S3_EN_BIT MBOX_BIT7 463 #define M2S_MBOX_VOL_SPDIF_EN_BIT MBOX_BIT8 464 #define M2S_MBOX_VOL_SRC_EN_BIT MBOX_BIT9 465 466 #define M2S_MBOX_AVC_CTRL MB_2D24 467 #define M2S_MBOX_SURR_CTRL MB_2D26 468 #define M2S_MBOX_SINE_GEN MB_2D28 469 #define M2S_MBOX_SINE_GEN_CTRL_MASK 0x7F 470 #define M2S_MBOX_SINE_GEN_EN_BIT MBOX_BIT7 471 472 #define M2S_MBOX_BALANCE_EN MB_2D2A 473 #define M2S_MBOX_BAL_DAC0_EN_BIT MBOX_BIT0 474 #define M2S_MBOX_BAL_DAC1_EN_BIT MBOX_BIT1 475 #define M2S_MBOX_BAL_DAC2_EN_BIT MBOX_BIT2 476 #define M2S_MBOX_BAL_DAC3_EN_BIT MBOX_BIT3 477 #define M2S_MBOX_BAL_I2S0_EN_BIT MBOX_BIT4 478 #define M2S_MBOX_BAL_I2S1_EN_BIT MBOX_BIT5 479 #define M2S_MBOX_BAL_I2S2_EN_BIT MBOX_BIT6 480 #define M2S_MBOX_BAL_I2S3_EN_BIT MBOX_BIT7 481 #define M2S_MBOX_BAL_SPDIF_EN_BIT MBOX_BIT8 482 #define M2S_MBOX_BAL_SRC_EN_BIT MBOX_BIT9 483 #define M2S_MBOX_BAL_HDMI_EN_BIT MBOX_BIT10 484 485 #define M2S_MBOX_SOUND_MODE_SEL MB_2D30 //[1:0] : LR / LL / RR 486 #define M2S_MBOX_POWER_DOWN MB_2D30 //[8:9] 487 #define M2S_MBOX_NR_CTRL MB_2D32 488 489 #define M2S_MBOX_ADVSND_EN MB_2D40 490 #define M2S_MBOX_ADVSND_SUMMARY_EN_BIT MBOX_BIT15 491 492 #define M2S_MBOX_KTV_CTRL MB_2D46 493 #define M2S_MBOX_KTV_EN_BIT MBOX_BIT15 494 495 #define M2S_MBOX_INPUT_MUX_SEL1 MB_2D50 496 #define M2S_MBOX_INPUT_MUX_SEL2 MB_2D52 497 #define M2S_MBOX_INPUT_MUX_SEL3 MB_2D54 498 499 #define M2S_MBOX_KTV8_VOL MB_2D5A 500 #define M2S_MBOX_KTV5_VOL MB_2D5C 501 #define M2S_MBOX_KTV6_VOL MB_2D5E 502 #define M2S_MBOX_CH7_VOL MB_2D58 503 504 #define M2S_MBOX_AD_CONTROL MB_2DD8 505 #define M2S_MBOX_MIX_MODE_BSTART MBOX_BITS_SHIFT-11 506 #define M2S_MBOX_MIX_MODE_BMASK 0x7 507 508 /* M2S_MBOX_MIX_MODE */ 509 #define GPA_MIX_MODE_IS_FORWARD 0 510 #define GPA_MIX_MODE_IS_BACKWARD 1 511 #define GPA_MIX_MODE_IS_NULL 2 ! 2 & 3: NULL_Mixer_Mode 512 513 #define M2S_MBOX_DBG_CMD1 MB_2DDC 514 #define MBOX_DBGCMD_SET_ADDR 0x0200 515 #define MBOX_DBGCMD_WRITE_DM 0x0300 516 #define MBOX_DBGCMD_WRITE_PM 0x0400 517 #define MBOX_DBGCMD_READ_DM 0x0500 518 #define MBOX_DBGCMD_READ_PM 0x0600 519 #define MBOX_DBGCMD_READ_PMASK 0x0700 520 #define MBOX_DBGCMD_READ_IMASK 0x0800 521 522 #define MBOX_DBGCMD_READ_MAIN_VER 0x9000 523 #define MBOX_DBGCMD_READ_ALG1_VER 0x9100 524 #define MBOX_DBGCMD_READ_ALG2_VER 0x9200 525 526 //#define MBOX_DBGCMD_MIP_INT 0xE000 527 //#define MBOX_DBGCMD_ENC_INT 0xE100 528 //#define MBOX_DBGCMD_FILE_PTS_INT 0xEA00 529 530 #define MBOX_DBGCMD_RELOAD_SIF_BEG 0xF000 531 #define MBOX_DBGCMD_RELOAD_SIF_END 0xF100 532 #define MBOX_DBGCMD_WAIT_MCU_START 0xF300 533 #define MBOX_DBGCMD_RELOAD_ADVSND_BEG 0xF400 534 #define MBOX_DBGCMD_RELOAD_ADVSND_END 0xF500 535 536 #define M2S_MBOX_DBG_CMD2 MB_2DDE 537 538 /* MISC */ 539 #define M2S_MBOX_SW_DMA_READER_DDR_WtPtr MB_2D34 540 #define M2S_MBOX_SW_DMA_READER_DDR_Ctrl MB_2D36 541 #define M2S_MBOX_SW_DMA_READER_DDR_SynthFreq MB_2D56 542 #define M2S_MBOX_SW_DMA_READER_DDR_SynthFreq_L 0 //Reserved 543 544 #define M2S_MBOX_CAPTURE_CTRL MB_2D4A //[7:0] PCM_capture1 [15:8] PCM_capture2 545 //#define M2S_MBOX_CAPTURE3_CTRL //MB_2D4C //[7:0] PCM_capture3 //RESERVED 546 #define M2S_MBOX_GET_CH5 1 547 #define M2S_MBOX_GET_CH6 2 548 #define M2S_MBOX_GET_CH7 3 549 #define M2S_MBOX_GET_CH8 4 550 #define M2S_MBOX_GET_ADC1 5 551 #define M2S_MBOX_GET_ADC2 6 552 #define M2S_MBOX_GET_Raw_Delay_SE 7 553 #define M2S_MBOX_GET_MIXER 8 554 #define M2S_MBOX_GET_DEBUG 128 555 556 #define M2S_MBOX_PCM_CAPTURE_DDR_RdPtr MB_2DD4 557 #define M2S_MBOX_PCM_CAPTURE_DDR_Size MB_2DD6 558 559 #define M2S_MBOX_PCM_CAPTURE2_DDR_RdPtr MB_2D38 560 #define M2S_MBOX_PCM_CAPTURE2_DDR_Size MB_2D3A 561 562 //#define M2S_MBOX_PCM_CAPTURE3_DDR_RdPtr //MB_2D94 //RESERVED 563 //#define M2S_MBOX_PCM_CAPTURE3_DDR_Size //MB_2D96 //RESERVED 564 565 /************************************************ 566 * DSP to MCU mailbox 567 ************************************************/ 568 #define S2M_MBOX_ES_MEMCNT MB_2D70 569 #define S2M_MBOX_PCM_MEMCNT MB_2D72 570 #define S2M_MBOX_MM_BROWSE_TIME MB_2D74 571 #define S2M_MBOX_MM_PTS_IN_SEC MB_2D76 572 #define S2M_MBOX_MM_PTS_IN_MSEC MB_2D78 573 #define S2M_MBOX_MM_PTS_HI MB_2D7A 574 #define S2M_MBOX_MM_PTS_ME MB_2D7C 575 #define S2M_MBOX_MM_PTS_LO MB_2D7E 576 577 #define S2M_MBOX_DEC_STATUS MB_2DFA 578 579 #define S2M_MBOX_SIF_DETECTION_RESULT MB_2DE0 580 #define S2M_MBOX_SIF_STATUS_INFO MB_2DE2 581 #define S2M_MBOX_SIF_STATUS_MODE1 MB_2DE4 582 #define S2M_MBOX_SIF_STATUS_MODE2 MB_2DE6 583 #define S2M_MBOX_SIF_STATUS_NICAM_INFO MB_2DE8 584 #define S2M_MBOX_SIF_STATUS_NICAM_PARITY_ERR_CNT MB_2DEA 585 586 #define S2M_MBOX_NR_STATUS MB_2DEE 587 #define S2M_MBOX_BSND_STATUS MB_2DEE 588 #define MBOX_NR_WORKING_NOW MBOX_BIT0 // 1: NR working now , 0 NR not working 589 #define MBOX_TONE_FUNC_SELECT MBOX_BIT1 // 0: EQ_Bass_Treble , 1: Bass_Treble_old 590 #define MBOX_PEQ_FUNC_SELECT MBOX_BIT2 // 0: PEQ: single precision , 1: double precision 591 592 #define S2M_MBOX_MAIN_OVERFLOW_CNT MB_2DF2 //[15:8], full cnt of input SRAM buff2 593 #define S2M_MBOX_MAIN_UNDERFLOW_CNT MB_2DF2 //[ 7:0], empty cnt of output SRAM buff1 594 595 #define S2M_MBOX_ISR_CNTR MB_2DF6 //[15:8] 596 #define S2M_MBOX_INTR_CMDTYPE MB_2DF6 //[ 7:0] 597 #define SE_DSP_INTR_CMD_MMES_NEED_DATA 0x0300 598 #define SE_DSP_INTR_CMD_REPORT_PTS 0x0500 599 #define SE_DSP_INTR_CMD_MMUNI_NEED_DATA 0x0600 600 #define SE_DSP_INTR_CMD_VOIP 0x0900 601 #define DSP_INTR_CMD_PCM_UPLOAD 0x3300 602 #define DSP_INTR_CMD_PCM_DOWNLOAD 0xC000 603 604 #define S2M_MBOX_WHILE1_CNTR MB_2DF8 //[ 7:0] Always in Low Byte 605 #define S2M_MBOX_TIMER_CNTR MB_2DF8 //[15:8] Always in High Byte 606 607 #define S2M_MBOX_DBG_RESULT1 MB_2DFC // 608 #define S2M_MBOX_DSP_INIT_ACK 0x00E3 609 610 #define S2M_MBOX_DBG_RESULT2 MB_2DFE // 611 #define MBOX_DSP_RELOAD_ACK1 0x0033 612 #define MBOX_DSP_RELOAD_ACK2 0x0077 613 614 #define S2M_MBOX_SW_DMA_READER_DDR_Level MB_2DE0 615 616 #define S2M_MBOX_PCM_CAPTURE_DDR_WrPtr MB_2DF0 617 #define S2M_MBOX_PCM_CAPTURE2_DDR_WrPtr MB_2DF4 618 //#define S2M_MBOX_PCM_CAPTURE3_DDR_WrPtr //MB_2D7E //RESERVED 619 620 #ifdef _COMPILE_DSP_ 621 /************************************************ 622 * DSP ddr address mapping 623 *************************************************/ 624 /* DRAM Config */ 625 .const DSP2_TO_COMMON_DRAM_OFFSET = ASND_DSP_DDR_SIZE / BYTES_IN_MIU_LINE; 626 627 /* SPDIF delay (GP C Bffer) */ 628 .const DSP2_SPDIF_DLY_DRAM_BASE = (OFFSET_SPDIF_DLY_DRAM_BASE / BYTES_IN_MIU_LINE); 629 .const DSP2_SPDIF_DLY_DRAM_SIZE = ((SPDIF_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1); 630 631 /* HDMI delay (GP C Bffer) */ 632 .const HDMI_DLY_DRAM_BASE = SE_HDMI_DLY_DRAM_BASE / BYTES_IN_MIU_LINE; 633 .const HDMI_DLY_DRAM_SIZE = (SE_HDMI_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1; 634 635 /* sound system */ 636 .const DSP2_DMA_START_DRAM_BASE1 = OFFSET_SE_MAIN_IN_DRAM_ADDR / BYTES_IN_MIU_LINE; 637 .const DSP2_DMA_START_DRAM_SIZE1 = SE_MAIN_IN_DRAM_SIZE / BYTES_IN_MIU_LINE; 638 .const DSP2_DMA_START_DRAM_BASE2 = OFFSET_SE_MAIN_OUT_DRAM_ADDR / BYTES_IN_MIU_LINE; 639 .const DSP2_DMA_START_DRAM_SIZE2 = SE_MAIN_OUT_DRAM_SIZE / BYTES_IN_MIU_LINE; 640 641 /* Surround */ 642 #if(MSTAR_SURROUND_DRAM_SIZE>0) 643 #define SUR_DRAM_BASEADDR (OFFSET_MSTAR_SURROUND_DRAM_ADDR / BYTES_IN_MIU_LINE) // Line Address 644 #define SUR_DRAM_ENDADDR ((OFFSET_MSTAR_SURROUND_DRAM_ADDR + MSTAR_SURROUND_DRAM_SIZE) / BYTES_IN_MIU_LINE) // Line Address 645 #endif 646 647 /* HE-AAC Metadata Buffer on DEC */ 648 .const DSP2_HEAAC_METADATA_DRAM_BASE = (OFFSET_DDENC_METADATA_DRAM_ADDR / BYTES_IN_MIU_LINE); 649 .const DSP2_HEAAC_METADATA_DRAM_SIZE = (DDENC_METADATA_DRAM_SIZE / BYTES_IN_MIU_LINE); // 8KB 650 651 /* KTV */ 652 #if(KTV_SURROUND_DRAM_SIZE>0) 653 #define SUR_DRAM_KTV_BASEADDR (OFFSET_KTV_SURROUND_DRAM_ADDR / BYTES_IN_MIU_LINE) // Line address, Only in KTV mode, MS surround -> echo 654 #define SUR_DARM_KTV_ENDADDR ((OFFSET_KTV_SURROUND_DRAM_ADDR + KTV_SURROUND_DRAM_SIZE) / BYTES_IN_MIU_LINE) // Line address, Overlay with DM prefetch 655 #endif 656 657 /* DSP DM Prefetch */ 658 #define DSP2_DM_PREFETCH_DRAM_BASE (OFFSET_DM_PREFETCH_DRAM_ADDR / BYTES_IN_MIU_LINE) 659 #define DSP2_DM_PREFETCH_DRAM_SIZE (DM_PREFETCH_DRAM_SIZE / BYTES_IN_MIU_LINE) // 64KB 660 661 /* standalone DDCO PCM Buffer */ 662 //#define DSP2_DDE_PCM_DRAM_BASE DSP2_DM_PREFETCH_DRAM_BASE+0x400 // AC3 Encode base address 663 //#define DSP2_DDE_PCM_DRAM_SIZE 0xBFF // 48KB 664 .const DSP2_DDE_PCM_DRAM_BASE = (OFFSET_SER2_DDENC_MCHOUT_DRAM_ADDR / BYTES_IN_MIU_LINE); // AC3 Encode base address 665 .const DSP2_DDE_PCM_DRAM_SIZE = ((SER2_DDENC_MCHOUT_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1); // 54kB 666 667 /* HEAD PHONE delay */ 668 #if(HEAD_PHONE_DLY_DRAM_SIZE>0) 669 .const DSP2_HEAD_PHONE_DLY_DRAM_BASE = (OFFSET_HEAD_PHONE_DLY_DRAM_BASE / BYTES_IN_MIU_LINE); // Line address 670 .const DSP2_HEAD_PHONE_DLY_DRAM_SIZE = ((HEAD_PHONE_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1); 671 #endif 672 673 /* CH5 input delay */ 674 #if(CH5_INPUT_DLY_DRAM_SIZE>0) 675 .const DSP2_CH5_INPUT_DLY_DRAM_BASE = (OFFSET_CH5_INPUT_DLY_DRAM_BASE / BYTES_IN_MIU_LINE); // Line address 676 .const DSP2_CH5_INPUT_DLY_DRAM_SIZE = ((CH5_INPUT_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1); 677 #endif 678 679 /* CH6 input delay */ 680 #if(CH6_INPUT_DLY_DRAM_SIZE>0) 681 .const DSP2_CH6_INPUT_DLY_DRAM_BASE = (OFFSET_CH6_INPUT_DLY_DRAM_BASE / BYTES_IN_MIU_LINE); // Line address 682 .const DSP2_CH6_INPUT_DLY_DRAM_SIZE = ((CH6_INPUT_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1); 683 #endif 684 685 /* multiChInput audio delay */ 686 #if(MULTI_CH_INPUT_DLY_DRAM_SIZE>0) 687 .const DSP2_MULTI_CH_INPUT_DLY_DRAM_BASE = (OFFSET_MULTI_CH_INPUT_DLY_DRAM_BASE / BYTES_IN_MIU_LINE); // Line address 688 .const DSP2_MULTI_CH_INPUT_DLY_DRAM_SIZE = ((MULTI_CH_INPUT_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1); 689 #endif 690 691 /* SPDIF Non-PCM */ 692 .const DSP2_SPDIF_DRAM_BASE = OFFSET_SPDIF_NONPCM_DRAM_BASE / BYTES_IN_MIU_LINE; 693 .const DSP2_SPDIF_DRAM_SIZE = (SPDIF_NONPCM_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1; 694 695 /* HDMI Non-PCM */ 696 .const DSP2_HDMI_DRAM_BASE = OFFSET_HDMI_NONPCM_DRAM_BASE / BYTES_IN_MIU_LINE; 697 .const DSP2_HDMI_DRAM_SIZE = (HDMI_NONPCM_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1; 698 699 /* pcmR_dmxPcm from preAsndR2 */ 700 .const DSP2_PCMR_DMXPCM_DRAM_BASE = (OFFSET_SER2_OUTPCM_DMX_DRAM_ADDR / BYTES_IN_MIU_LINE); 701 .const DSP2_PCMR_DMXPCM_DRAM_SIZE = ((SER2_OUTPCM_DMX_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1); 702 703 /* COMMON DRAM */ 704 705 /* PCM 1 / 2 */ 706 .const DSP2_PCM1_DRAM_BASE = DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_PCM1_DRAM_ADDR / BYTES_IN_MIU_LINE); 707 .const DSP2_PCM1_DRAM_SIZE = (PCM1_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1; 708 709 .const DSP2_PCM2_DRAM_BASE = DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_PCM2_DRAM_ADDR / BYTES_IN_MIU_LINE); 710 .const DSP2_PCM2_DRAM_SIZE = (PCM2_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1; 711 712 /* Software DMA */ 713 #if(SW_DMA_READER_DRAM_SIZE>0) 714 .const DSP2_SW_DMA_READER_DRAM_BASE = DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_SW_DMA_READER_DRAM_BASE / BYTES_IN_MIU_LINE); 715 .const DSP2_SW_DMA_READER_DRAM_SIZE = (SW_DMA_READER_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1; 716 #endif 717 /* PCM capture buffer */ 718 .const DSP2_PCM_CAPTURE_BUFFER_DRAM_BASE = DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_PCM_CAPTURE1_BUFFER_DRAM_BASE / BYTES_IN_MIU_LINE); 719 .const DSP2_PCM_CAPTURE2_BUFFER_DRAM_BASE = DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_PCM_CAPTURE2_BUFFER_DRAM_BASE / BYTES_IN_MIU_LINE); 720 .const DSP2_PCM_CAPTURE3_BUFFER_DRAM_BASE = DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_PCM_CAPTURE3_BUFFER_DRAM_BASE / BYTES_IN_MIU_LINE); 721 .const DSP2_PCM_CAPTURE_BUFFER_DRAM_SIZE = (PCM_CAPTURE_BUFFER_DRAM_SIZE/ BYTES_IN_MIU_LINE); 722 .const DSP2_PCM_CAPTURE2_BUFFER_DRAM_SIZE = (PCM_CAPTURE2_BUFFER_DRAM_SIZE/ BYTES_IN_MIU_LINE); 723 #define DSP2_PCM_CAPTURE_COPY_WORDSIZE 32 724 #define DSP2_PCM_CAPTURE_COPY_LINESIZE 4 725 726 /************************************************ 727 * DSP TSCALE & TCOUNT setting 728 ************************************************/ 729 #define DSP_SYSTEM_FREQUENCY 432 730 #define TSCALE_CONSTANT 0xF9 731 #define DSP_TIME_CONSTANT (DSP_SYSTEM_FREQUENCY/2 -1) 732 #define DSP_TIMER_SETTING DSP_TIME_CONSTANT 733 734 /************************************************ 735 * Below is DMA config 736 *************************************************/ 737 #define DMAITF_DSPCMD_ALIGNMENT_BIT 7 // 1/0 : msb / lsb alignment 738 #define DMAITF_DSPCMD_BYTESWAP_BIT 6 // set 1 to byte swap 739 #define DMAITF_DSPCMD_READY_BIT 5 // set 1 to trigger, will be 0 when dma is finished 740 #define DMAITF_DSPCMD_CLRCNTR_BIT 4 // set 1 to clear 741 #define DMAITF_DSPCMD_PRIORITY_BIT 3 // 1/0 : high / low 742 #define DMAITF_DSPCMD_24BITS_BIT 2 // 1/0 : 24bits / 16bits 743 744 #define DMAITF_DSPCMD_ALIGNMENT_MASK 0x80 745 #define DMAITF_DSPCMD_BYTESWAP_MASK 0x40 746 #define DMAITF_DSPCMD_READY_MASK 0x20 747 #define DMAITF_DSPCMD_CLRCNTR_MASK 0x10 748 #define DMAITF_DSPCMD_PRIORITY_MASK 0x08 749 #define DMAITF_DSPCMD_24BITS_MASK 0x04 750 #define DMAITF_DSPCMD_BURST_6 0x03 751 #define DMAITF_DSPCMD_BURST_3 0x02 752 #define DMAITF_DSPCMD_BURST_2 0x01 753 #define DMAITF_DSPCMD_BURST_1 0x00 754 755 #if (MIU_128 == 1) 756 /* 1 MIU Line = 128bit (16 bytes) */ 757 #define DMAITF_DSPWORDS_IN_1_LINE 8 758 #define DMAITF_DSPWORDS_IN_1LINE_LOG2 3 759 #define DMAITF_DSPWORDS_IN_3LINE_LOG2 4 760 #define DMAITF_WR_BIT 16 761 #define DMAITF_DM_BIT 15 762 #define DMAITF_BYTES_IN_1MIU_LINE BYTES_IN_MIU_LINE 763 764 #define DMAITF_RD_PM_MASK 0x000000 765 #define DMAITF_WR_PM_MASK 0x010000 766 #define DMAITF_RD_DM_MASK 0x008000 767 #define DMAITF_WR_DM_MASK 0x018000 768 769 #define DMAITF_16BITS_B1_DMA_CMD 0xA8 // 16 Bits Burst 1, high alignment 770 #define DMAITF_16BITS_B2_DMA_CMD 0xA8 //no Burst 2 cmd, use B1 instead 771 #define DMAITF_16BITS_B1_SWAP_DMA_CMD 0xE8 // 16 Bits Burst 1, high alignment 772 #define DMAITF_16BITS_B2_SWAP_DMA_CMD 0xE8 //no Burst 2 cmd, use B1 instead 773 774 #define DMAITF_24BITS_B3_DMA_CMD 0x2E // 24 Bits Burst 3 775 #define DMAITF_24BITS_B6_DMA_CMD 0x2E //no Burst 6 cmd, use B3 instead 776 777 #define DMAITF_16BITS_LowAlign_B1_DMA_CMD 0x28 //16 Bits Burst 1, low alignment 778 #define DMAITF_16BITS_LowAlign_B1_SWAP_DMA_CMD 0x68 //16 Bits Burst 1, low alignment 779 #else 780 /* 1 MIU Line = 64bit (8 bytes) */ 781 #define DMAITF_DSPWORDS_IN_1_LINE 4 782 #define DMAITF_DSPWORDS_IN_1LINE_LOG2 2 783 #define DMAITF_DSPWORDS_IN_3LINE_LOG2 3 784 #define DMAITF_WR_BIT 15 785 #define DMAITF_DM_BIT 14 786 #define DMAITF_BYTES_IN_1MIU_LINE BYTES_IN_MIU_LINE 787 788 #define DMAITF_RD_PM_MASK 0x000000 789 #define DMAITF_WR_PM_MASK 0x008000 790 #define DMAITF_RD_DM_MASK 0x004000 791 #define DMAITF_WR_DM_MASK 0x00C000 792 793 #define DMAITF_16BITS_B1_DMA_CMD 0xA8 // 16 Bits Burst 1, high alignment 794 #define DMAITF_16BITS_B2_DMA_CMD 0xA9 795 #define DMAITF_16BITS_B1_SWAP_DMA_CMD 0xE8 // 16 Bits Burst 1, high alignment 796 #define DMAITF_16BITS_B2_SWAP_DMA_CMD 0xE9 797 798 #define DMAITF_24BITS_B3_DMA_CMD 0x2E // 24 Bits Burst 3 799 #define DMAITF_24BITS_B6_DMA_CMD 0x2F // 24 Bits Burst 6 800 801 #define DMAITF_16BITS_LowAlign_B1_DMA_CMD 0x28 //16 Bits Burst 1, low alignment 802 #define DMAITF_16BITS_LowAlign_B1_SWAP_DMA_CMD 0x68 //16 Bits Burst 1, low alignment 803 #endif 804 805 /* DMA Mapping */ 806 #define General_DSP_IDMA_CMD_Number 15 // just info this chip nubmer of DSP_IDMA can support, (no any purpose) need sync with HW spec 807 808 #define SNDISR1_DMA_CTRL DSPDMA7_DMA_CTRL 809 #define SNDISR2_DMA_CTRL DSPDMA2_DMA_CTRL 810 #define SPDIF_DMA_CTRL DSPDMA6_DMA_CTRL // SPDIF npcm 811 #define HDMI_DMA_CTRL DSPDMA6_DMA_CTRL // HDMI npcm 812 #define PCM_CAPTURE_DMA_CTRL DSPDMA15_DMA_CTRL 813 #define PCM_CAPTURE2_DMA_CTRL DSPDMA14_DMA_CTRL 814 #define PCM_CAPTURE3_DMA_CTRL DSPDMA13_DMA_CTRL 815 #define SW_DMARDR_DMA_CTRL DSPDMA12_DMA_CTRL 816 #define HP_DLY_DMA_CTRL DSPDMA11_DMA_CTRL 817 #define CH5_IN_DLY_DMA_CTRL DSPDMA10_DMA_CTRL 818 #define CH6_IN_DLY_DMA_CTRL DSPDMA9_DMA_CTRL 819 #define MULTI_CH_INPUT_DLY_DMA_CTRL DSPDMA8_DMA_CTRL 820 #define R2_DEC_PCM1R_DMA_CTRL PCM1R_DMA_CTRL 821 #define DDE_ISR_PCM_DMA_CTRL DSPDMA1_DMA_CTRL 822 #define SPDIF_DLY_IN_DMA_CTRL DSPDMA2_DMA_CTRL 823 #define HDMI_DLY_IN_DMA_CTRL DSPDMA2_DMA_CTRL 824 #define SPDIF_DLY_OUT_DMA_CTRL DSPDMA6_DMA_CTRL 825 #define HDMI_DLY_OUT_DMA_CTRL DSPDMA6_DMA_CTRL 826 #define PCMR_DMXPCM_DMA_CTRL PCM1R_DMA_CTRL 827 828 #define SNDBG_DMA_CTRL DSPDMA3_DMA_CTRL // Background sound effect 829 #define ADEC_DMA1_CTRL DSPDMA3_DMA_CTRL 830 #define ADEC_DMA2_CTRL DSPDMA4_DMA_CTRL 831 #define ADEC_DMA3_CTRL DSPDMA3_DMA_CTRL 832 #define ADEC_DMA4_CTRL DSPDMA4_DMA_CTRL 833 #define ADEC_DMA5_CTRL DSPDMA5_DMA_CTRL 834 835 /************************************************ 836 * Below is DSP FIFO/DDR unit Setting 837 *************************************************/ 838 .const SE_R2_FRAME_SIZE = 256; //256 samples for R2_SE 839 .const SE_PROCESS_FRAME_SMP_UNIT = 128; //128 samples per frame 840 841 .const SE_PROCESS_FETCH_FRAME_LINE_SIZE = SE_PROCESS_FRAME_SMP_UNIT*SE_PROCESS_FETCH_CHANNELS*3/BYTES_IN_MIU_LINE; 842 .const SE_PROCESS_STORE_FRAME_LINE_SIZE = SE_PROCESS_FRAME_SMP_UNIT*SE_PROCESS_STORE_CHANNELS*3/BYTES_IN_MIU_LINE; 843 844 /* sound effect buffer / share buffer setting */ 845 .const SE_PROCESS_FIFO_SIZE_UNIT = 64; //delay fifo size per channel 846 .const SE_PROCESS_DMA_WORD_SIZE_UNIT = 16; //DMA_WORD_SIZE per channel 847 848 /* ISR PCM samples -> DDR unit setting */ 849 .const SE_BUFF2_FIFO_SIZE = (SE_PROCESS_FIFO_SIZE_UNIT * SE_PROCESS_FETCH_CHANNELS); 850 .const SE_BUFF2_DMA_WORD_SIZE = (SE_PROCESS_DMA_WORD_SIZE_UNIT * SE_PROCESS_FETCH_CHANNELS); // (DMA_WORD_SIZE per channel) * channel number 0x80; 851 .const SE_BUFF2_DMA_24BIT_LINE_SIZE = SE_BUFF2_DMA_WORD_SIZE*3/BYTES_IN_MIU_LINE; 852 .const SE_BUFF2_DMA_16BIT_LINE_SIZE = SE_BUFF2_DMA_WORD_SIZE*2/BYTES_IN_MIU_LINE; 853 854 /* DDR2 --> output ISR PCM samples */ 855 .const SE_BUFF1_FIFO_SIZE = (SE_PROCESS_FIFO_SIZE_UNIT * SE_PROCESS_STORE_CHANNELS); 856 .const SE_BUFF1_DMA_WORD_SIZE = (SE_PROCESS_DMA_WORD_SIZE_UNIT * SE_PROCESS_STORE_CHANNELS); // (DMA_WORD_SIZE per channel) * channel number 0x80; 857 .const SE_BUFF1_DMA_24BIT_LINE_SIZE = SE_BUFF1_DMA_WORD_SIZE*3/BYTES_IN_MIU_LINE; 858 .const SE_BUFF1_DMA_16BIT_LINE_SIZE = SE_BUFF1_DMA_WORD_SIZE*2/BYTES_IN_MIU_LINE; 859 860 /* share buffer in dm mapping */ 861 .const SE_PROCESS_BUFFER_MAIN = 0x0; //share buffer in dm 862 .const SE_PROCESS_BUFFER_MAIN_RAW1_LR = SE_PROCESS_BUFFER_MAIN + SE_PROCESS_FRAME_SMP_UNIT*0; 863 .const SE_PROCESS_BUFFER_MAIN_RAW2_LR = SE_PROCESS_BUFFER_MAIN + SE_PROCESS_FRAME_SMP_UNIT*2; 864 .const SE_PROCESS_BUFFER_MAIN_SE_LR = SE_PROCESS_BUFFER_MAIN + SE_PROCESS_FRAME_SMP_UNIT*4; 865 .const SE_PROCESS_BUFFER_MAIN_SE_LmRm = SE_PROCESS_BUFFER_MAIN + SE_PROCESS_FRAME_SMP_UNIT*6; 866 .const SURR_DLY_BUFFER = SE_PROCESS_BUFFER_MAIN + SE_PROCESS_FRAME_SMP_UNIT*8; 867 .const NR_PARAMETER_BUFFER = SE_PROCESS_BUFFER_MAIN + SE_PROCESS_FRAME_SMP_UNIT*10; 868 .const SE_PROCESS_BUFFER_MAIN_TMP = SE_PROCESS_BUFFER_MAIN + SE_PROCESS_FRAME_SMP_UNIT*12; //0x600 869 870 #define DSP2DmAddr_system_shareBuff 0x0 //SE_PROCESS_BUFFER_MAIN 871 #define DSP2DmAddr_system_shareBuff_size (0x600) //(SE_PROCESS_BUFFER_MAIN_TMP - SE_PROCESS_BUFFER_MAIN) 872 #define DSP2DmAddr_advSnd_shareBuff_base SE_PROCESS_BUFFER_MAIN_TMP 873 #define DSP2DmAddr_advSnd_shareBuff_size (0x1500) // min size: (SE_PROCESS_FRAME_SMP_UNIT*SE_PROCESS_FETCH_CHANNELS) for system frame base SE 874 875 .const SndEff_Array_TMP1 = SE_PROCESS_BUFFER_MAIN_TMP; 876 .const SndEff_Array_TMP2 = SndEff_Array_TMP1 + SE_PROCESS_FRAME_SMP_UNIT*2; 877 .const SndEff_Array_TMP3 = SndEff_Array_TMP2 + SE_PROCESS_FRAME_SMP_UNIT*2; 878 .const SndEff_Array_TMP4 = SndEff_Array_TMP3 + SE_PROCESS_FRAME_SMP_UNIT*2; 879 880 .const Apply_NR_Status_BUFFER = NR_PARAMETER_BUFFER; 881 .const Apply_NR_Gain_BUFFER = Apply_NR_Status_BUFFER + SE_PROCESS_FRAME_SMP_UNIT; 882 883 /* General delay buffer template */ 884 .const HP_DLY_MAX_DELAY = 512; //unit : ms 885 .const DELAY_MAX_DELAY = 512; 886 .const DELAY_FIFO_SIZE = 128; 887 .const DELAY_DMA_WORDSIZE = 32; 888 .const DELAY_DMA_LINESIZE = DELAY_DMA_WORDSIZE*3/BYTES_IN_MIU_LINE; 889 890 .const MULTI_CH_INPUT_DELAY_FIFO_SIZE = (SE_PROCESS_FIFO_SIZE_UNIT * MULTI_CH_INPUT_DELAY_STORE_CHANNELS); // fifo len 891 .const MULTI_CH_INPUT_DELAY_DMA_WORDSIZE = (SE_PROCESS_DMA_WORD_SIZE_UNIT * MULTI_CH_INPUT_DELAY_STORE_CHANNELS); 892 .const MULTI_CH_INPUT_DELAY_DMA_LINESIZE = (MULTI_CH_INPUT_DELAY_DMA_WORDSIZE*3/BYTES_IN_MIU_LINE); 893 894 /* Dly_status */ 895 .const DELAY_INPUT_STOP = 0; 896 .const DELAY_OUTPUT_STOP = 1; 897 .const DELAY_DLYIN_DMA_ASSERT = 2; 898 .const DELAY_DLYOUT_DMA_ASSERT = 3; 899 900 /* Mstar Surround delay buffer */ 901 .const SUR_FIFO_UNIT = SE_PROCESS_FRAME_SMP_UNIT*2; 902 .const SUR_DRAM_BURSRT = (SUR_FIFO_UNIT*2)/BYTES_IN_MIU_LINE; 903 904 /* spdif delay unit setting */ 905 .const SPDIF_DLYBUF_DMA_WORDSIZE = 32; 906 .const SPDIF_DLYBUF_DMA_LINESIZE = SPDIF_DLYBUF_DMA_WORDSIZE*2/BYTES_IN_MIU_LINE; 907 .const SPDIF_DLYFIFO_LEN = 64; 908 909 /* spdif nonPcm unit setting */ 910 .const SPDIF_NPCM_DMA_WORDSIZE = 32; 911 .const SPDIF_NPCM_DMA_LINESIZE = SPDIF_NPCM_DMA_WORDSIZE*2/BYTES_IN_MIU_LINE; 912 .const SPDIF_NPCMFIFO_LEN = 64; 913 914 /* pcmR_dmxPcm unit setting */ 915 .const PCMR_DMXPCM_DMA_WORDSIZE = 32; 916 .const PCMR_DMXPCM_DMA_LINESIZE = PCMR_DMXPCM_DMA_WORDSIZE*2/BYTES_IN_MIU_LINE; 917 .const PCMR_DMXPCMFIFO_LEN = 64; 918 919 /* hdmi npcm fifo unit setting */ 920 .const HDMI_NPCM_DMA_WORDSIZE = 128; 921 .const HDMI_NPCM_DMA_LINESIZE = HDMI_NPCM_DMA_WORDSIZE*2/BYTES_IN_MIU_LINE; 922 .const HDMI_NFIFO_LEN = 128*2; 923 924 /* hdmi delay unit setting */ 925 .const HDMI_DLYBUF_DMA_WORDSIZE = 32; 926 .const HDMI_DLYBUF_DMA_LINESIZE = HDMI_DLYBUF_DMA_WORDSIZE*2/BYTES_IN_MIU_LINE; 927 .const HDMI_DLYFIFO_LEN = 64; 928 929 /* SW DMA */ 930 .const SW_DMA_CTRL_RESET_BIT = 0; 931 .const SW_DMA_CTRL_START_BIT = 1; 932 .const SW_DMA_CTRL_CIRCL_BIT = 2; 933 934 .const SW_DMA_WORDSIZE = 32; 935 .const SW_DMA_LINESIZE = SW_DMA_WORDSIZE*2/BYTES_IN_MIU_LINE; 936 937 /******************************************************************** 938 * DSP ISR mapping 939 ********************************************************************/ 940 /* default 0 (no use) */ 941 #define ISR_MASK_PCM IMASK_SP1T_IRQ1 942 #define ISR_MASK_PCM2 IMASK_SP1R_IRQ0 943 #define ISR_MASK_TIMER IMASK_TM 944 945 /* default -1 (no use) */ 946 #define ISR_PMASK_PCM -1 947 #define ISR_PMASK_PCM2 -1 948 #define ISR_PMASK_DEC_R2_CMD 20 //from R2_0 IO 0xB000_0860 949 #define ISR_PMASK_R2_LOAD_CODE_CMD 21 //from R2_0 IO 0xB000_0840 950 #define ISR_PMASK_SPDIF2_ISR IMASK_IRQE1 951 #define ISR_PMASK_HDMI_ISR IMASK_IRQL1 952 953 #define DEC_MAIN_FUNC_PTR g_DecFunPtr 954 #define PCMOUT_FUNC_PTR g_IRQ1_isr_funcPtr 955 #define SIF_PCMOUT_FUNC_PTR g_IRQ0_isr_funcPtr 956 #define SIF_ENC_FUNC_PTR g_SifEncFuncPtr 957 #define SIF_ENC_DATAOUT_FUNC_PTR g_SifEncDataOutFuncPtr 958 959 /******************************************************************** 960 * DSP internal mailbox mapping 961 ********************************************************************/ 962 963 /* SPDIF NonPCM */ 964 #define D2S_MBOX_SPDIF_CTRL ddco_spdifNpcmCtrl // [0:2]=Acmod for AC3/AC3+/HE-AAC, [3]=LFE flag, 965 // [ 8:11]: HDMI sample rate 966 // 0: 96K, 1: 88K, 2: 64K 967 // 3: 48K, 4: 44K, 5: 32K 968 // 6: 24K, 7: 22K, 8: 16K 969 // 9: 12K, a: 11K, b: 8K 970 // c:192K, d: 176K e: 128K 971 // [12:15]: SPDIF sample rate 972 // 0: 96K, 1: 88K, 2: 64K 973 // 3: 48K, 4: 44K, 5: 32K 974 // 6: 24K, 7: 22K, 8: 16K 975 // 9: 12K, a: 11K, b: 8K 976 // [18] info to DDCO: 1-> -4.75dB; 0-> do nothing 977 // [19] : 1->48KHz, 0->non-48KHz 978 // [20] MultiCH_EN, [21]=ADEC Stop/Play,[22]=Freeze,[23]=Start 979 #define D2S_MBOX_SPDIF_WRPTR ddco_spdifNpcmWrPtr 980 #define S2D_MBOX_SPDIF_RDPTR ddco_spdifNpcmRdPtr 981 982 .const MBOX_MULTI_CHANNEL_ENABLE_BIT = 20; 983 .const MBOX_SPDIF_NPCM_CTRL_BIT_PLAY = 17; 984 .const MBOX_SPDIF_NPCM_CTRL_BIT_FREEZE = 22; 985 .const MBOX_SPDIF_NPCM_CTRL_BIT_START = 19; 986 987 .const MBOX_HDMI_NPCM_CTRL_BIT_PLAY = 21; 988 .const MBOX_HDMI_NPCM_CTRL_BIT_START = 23; 989 //[23] HDMI nonPcm Start 990 //[22] 991 //[21] HDMI nonPcm PlayEnable 992 //[20] HDMI HBR mode 993 //[19] SPDIF nonPcm Start 994 //[18] inform DDEncode to attenuate 4.75dB 995 //[17] SPDIF nonPcm PlayEnable 996 //[16] 997 //[15:12] SPDIF nonPcm sampleRate index 998 // 0: 96K, 1: 88K, 2: 64K 999 // 3: 48K, 4: 44K, 5: 32K 1000 // 6: 24K, 7: 22K, 8: 16K 1001 // 9: 12K, a: 11K, b: 8K 1002 1003 //[11:8] HDMI nonPcm sampleRate index 1004 // 0: 96K, 1: 88K, 2: 64K 1005 // 3: 48K, 4: 44K, 5: 32K 1006 // 6: 24K, 7: 22K, 8: 16K 1007 // 9: 12K, a: 11K, b: 8K 1008 // c:192K, d: 176K e: 128K 1009 1010 //[7] HDMI is Pcm or nonPcm 1011 //[6] SPDIF is Pcm or nonPcm 1012 //[5:4] hdmi nonPcm owner 1013 //[3:2] spdif nonPcm owner 1014 //[0:1] spdif/hdmi PCM attenuator index 1015 1016 #define NULL_PAYLOAD_TEST 1 1017 1018 #if (NULL_PAYLOAD_TEST == 1) 1019 .const SPDIF_NPCM_MUTE_FRMCNT = 0x8; 1020 .const SPDIF_PCM_MUTE_SMPCNT = 0; 1021 .const SPDIF_NPCM_NULL_FRMCNT = 0x0 + SPDIF_NPCM_MUTE_FRMCNT; 1022 #else 1023 .const SPDIF_NPCM_MUTE_FRMCNT = 0x10; 1024 .const SPDIF_PCM_MUTE_SMPCNT = 0; 1025 #endif 1026 1027 /* Mailbox with DEC R2 */ 1028 #define D2S_MBOX_LOAD_CODE_CMD DECR2M_2_DSP_MAILBOX0 1029 1030 #define D2S_MBOX_PCMISR_CTRL DECR2M_2_DSP_MAILBOX1 1031 #define MBOX_R2_PCM1ISR_PLAY_START_BIT 0 //--> �o�U�� playSmpFlag / stop / pause �M�w 1032 #define MBOX_R2_PCM1ISR_PLAY_MUTE_BIT 1 //--> Mute 1033 #define MBOX_R2_PCM1ISR_USING_ASINK_ISR_BIT 2 1034 #define MBOX_R2_PCM2ISR_PLAY_START_BIT 8 1035 #define MBOX_R2_PCM2ISR_PLAY_MUTE_BIT 9 1036 #define MBOX_R2_PCM2ISR_USING_ASINK_ISR_BIT 10 1037 1038 #define D2S_MBOX_PCM1_DRAM_WRPTR DECR2M_2_DSP_MAILBOX2 1039 #define D2S_MBOX_PCM1_SYNTH_H DECR2M_2_DSP_MAILBOX3 1040 #define D2S_MBOX_PCM1_SYNTH_L DECR2M_2_DSP_MAILBOX4 1041 1042 #define D2S_MBOX_PCM2_DRAM_WRPTR DECR2M_2_DSP_MAILBOX5 1043 #define D2S_MBOX_PCM2_SYNTH_H DECR2M_2_DSP_MAILBOX6 1044 #define D2S_MBOX_PCM2_SYNTH_L DECR2M_2_DSP_MAILBOX7 1045 1046 #define D2S_MBOX_R2_TO_DSP_COMMAND DECR2M_2_DSP_MAILBOX8 1047 #define D2S_CMD_UPD_PCM1_MUTECNT 0x0001 // Bit0 1048 #define D2S_CMD_CLR_PCM1_PLAYCNT 0x0002 // Bit1 1049 #define D2S_CMD_UPD_PCM1_PLAYCNT 0x0004 // Bit2 1050 #define D2S_CMD_FLUSH_PCM1_SMPS 0x0008 // Bit3 1051 #define D2S_CMD_RESET_PCM1 0x0010 // Bit4 1052 #define D2S_CMD_UPD_PCM2_MUTECNT 0x0020 // Bit5 1053 #define D2S_CMD_CLR_PCM2_PLAYCNT 0x0040 // Bit6 1054 #define D2S_CMD_UPD_PCM2_PLAYCNT 0x0080 // Bit7 1055 #define D2S_CMD_FLUSH_PCM2_SMPS 0x0100 // Bit8 1056 #define D2S_CMD_RESET_PCM2 0x0200 // Bit9 1057 1058 #define D2S_MBOX_R2_TO_DSP_PARAM DECR2M_2_DSP_MAILBOX9 1059 #define D2S_R2_SPDIF_WR_PTR DECR2M_2_DSP_MAILBOXA 1060 #define D2S_MBOX_HDMI_NPCM_WRPTR DECR2M_2_DSP_MAILBOXB 1061 1062 #define D2S_MBOX_HDMI_NPCM_CMD DECR2M_2_DSP_MAILBOXC 1063 #define D2S_R2_SPDIF_CTRL DECR2M_2_DSP_MAILBOXC 1064 #define D2S_MBOX_NPCM_CTRL D2S_R2_SPDIF_CTRL 1065 //#define MBOX_HDMI_NPCM_CTRL_BIT_START MBOX_BIT23 1066 //#define MBOX_HDMI_NPCM_CTRL_BIT_PLAY MBOX_BIT21 1067 //#define MBOX_MULTI_CHANNEL_ENABLE_BIT MBOX_BIT20 1068 //#define MBOX_SPDIF_NPCM_CTRL_BIT_START MBOX_BIT19 1069 #define MBOX_SPDIF_NPCM_DDE_MINUS_4_75DB MBOX_BIT18 1070 //#define MBOX_SPDIF_NPCM_CTRL_BIT_PLAY MBOX_BIT17 1071 #define MBOX_HDMI_NONPCM_FROM_ASND_DSP_BIT MBOX_BIT5 1072 #define MBOX_HDMI_NONPCM_FROM_ASND_R2_BIT MBOX_BIT4 1073 #define MBOX_SPDIF_NONPCM_FROM_ASND_DSP_BIT MBOX_BIT3 1074 #define MBOX_SPDIF_NONPCM_FROM_ASND_R2_BIT MBOX_BIT2 1075 //[23] HDMI nonPcm Start 1076 //[22] 1077 //[21] HDMI nonPcm PlayEnable 1078 //[20] HDMI HBR mode 1079 //[19] SPDIF nonPcm Start 1080 //[18] inform DDEncode to attenuate 4.75dB 1081 //[17] SPDIF nonPcm PlayEnable 1082 //[16] 1083 //[15:12] SPDIF nonPcm sampleRate index 1084 // 0: 96K, 1: 88K, 2: 64K 1085 // 3: 48K, 4: 44K, 5: 32K 1086 // 6: 24K, 7: 22K, 8: 16K 1087 // 9: 12K, a: 11K, b: 8K 1088 1089 //[11:8] HDMI nonPcm sampleRate index 1090 // 0: 96K, 1: 88K, 2: 64K 1091 // 3: 48K, 4: 44K, 5: 32K 1092 // 6: 24K, 7: 22K, 8: 16K 1093 // 9: 12K, a: 11K, b: 8K 1094 // c:192K, d: 176K e: 128K 1095 1096 //[7] HDMI is Pcm or nonPcm 1097 //[6] SPDIF is Pcm or nonPcm 1098 //[5:4] hdmi nonPcm owner 1099 //[3:2] spdif nonPcm owner 1100 //[0:1] spdif/hdmi PCM attenuator index //Dolby Bulletin 11: PCM Level control, 0: 0dB, 1:-7dB(ATSC), 2:-8dB(DVB), 3:-11dB(ISDB) 1101 1102 #define D2S_R2_DOLBY_META_DATA DECR2M_2_DSP_MAILBOXD 1103 #define D2S_DSP_ENCODE_SETTING DECR2M_2_DSP_MAILBOXE 1104 #define MBOX_NONPCM_DDE_ENABLE_BIT MBOX_BIT6 1105 #define MBOX_NONPCM_DTSE_ENABLE_BIT MBOX_BIT5 1106 //[6] DSP DDENC ENABLE bit 1107 //[5] DSP DTS ENC ENABLE bit 1108 //[4] LFE 1109 //[3:0] AC mode 1110 1111 /************************************************************/ 1112 1113 #define S2D_MBOX_DSP_TO_R2_COMMAND DSP_2_DECR2M_MAILBOX0 1114 #define S2D_CMD_RESET_PCM1_AVSYNC 0x0001 1115 #define S2D_CMD_RESET_PCM2_AVSYNC 0x0002 1116 1117 #define S2D_MBOX_DSP_TO_R2_PARAM DSP_2_DECR2M_MAILBOX1 1118 #define S2D_MBOX_R2CMD_RECEIVE_CNT DSP_2_DECR2M_MAILBOX2 1119 1120 #define S2D_MBOX_PCM1_PLAYCNT DSP_2_DECR2M_MAILBOX3 1121 #define S2D_MBOX_PCM1_FIFOCNT DSP_2_DECR2M_MAILBOX4 1122 #define S2D_MBOX_PCM1_DRAM_RDPTR DSP_2_DECR2M_MAILBOX5 1123 1124 #define S2D_MBOX_PCM2_PLAYCNT DSP_2_DECR2M_MAILBOX6 1125 #define S2D_MBOX_PCM2_FIFOCNT DSP_2_DECR2M_MAILBOX7 1126 #define S2D_MBOX_PCM2_DRAM_RDPTR DSP_2_DECR2M_MAILBOX8 1127 1128 #define S2D_MBOX_ENCODE_SURPPORT DSP_2_DECR2M_MAILBOX9 1129 #define DDE_ENCODE_SURPPORT_BIT MBOX_BIT0 1130 #define DTSE_ENCODE_SURPPORT_BIT MBOX_BIT1 1131 #define DDPE_ENCODE_SURPPORT_BIT MBOX_BIT2 1132 1133 #define S2D_R2_SPDIF_RD_PTR DSP_2_DECR2M_MAILBOXA 1134 #define S2D_MBOX_HDMI_NPCM_RDPTR DSP_2_DECR2M_MAILBOXB 1135 1136 #define S2D_IP_SECURITY_KEY DSP_2_DECR2M_MAILBOXE 1137 #define S2D_OTP_BOUNDING DSP_2_DECR2M_MAILBOXF 1138 1139 #define S2A_IP_SECURITY_KEY DSP_2_SNDR2M_MAILBOXE 1140 #define S2A_OTP_BOUNDING DSP_2_SNDR2M_MAILBOXF 1141 1142 !#define S2A_R2_PCMIN_WRPTR DSP_2_DECR2M_MAILBOX7 1143 !#define S2A_R2_PCMIN2_WRPTR DSP_2_DECR2M_MAILBOX8 1144 !#define S2A_R2_SPDIF_RD_PTR DSP_2_DECR2M_MAILBOX9 1145 !#define S2A_IP_SECURITY_KEY DSP_2_DECR2M_MAILBOXE 1146 !#define S2A_OTP_BOUNDING DSP_2_DECR2M_MAILBOXF 1147 1148 !#define A2S_R2_PCMOUT_WRPTR DECR2M_2_DSP_MAILBOXD 1149 !#define A2S_R2_PCMOUT2_WRPTR DECR2M_2_DSP_MAILBOX0 1150 !#define A2S_R2_SPDIF_WR_PTR DECR2M_2_DSP_MAILBOXE 1151 !#define A2S_R2_SPDIF_CTRL DECR2M_2_DSP_MAILBOXF 1152 /* Mailbox with SND R2 */ 1153 #define S2A_R2_PCMIN_WRPTR DSP_2_SNDR2M_MAILBOX1 1154 #define S2A_R2_PCMIN2_WRPTR DSP_2_SNDR2M_MAILBOX2 1155 #define S2A_R2_SPDIF_RD_PTR DSP_2_SNDR2M_MAILBOX3 1156 #define S2A_IP_SECURITY_KEY DSP_2_SNDR2M_MAILBOXE 1157 #define S2A_OTP_BOUNDING DSP_2_SNDR2M_MAILBOXF 1158 #define S2A_MBOX_HDMI_NPCM_RDPTR DSP_2_SNDR2M_MAILBOX4 1159 #define S2A_MBOX_SPEAKER_CH_VOLUME DSP_2_SNDR2M_MAILBOXA 1160 1161 #define A2S_R2_PCMOUT_WRPTR SNDR2M_2_DSP_MAILBOX1 1162 #define A2S_R2_PCMOUT2_WRPTR SNDR2M_2_DSP_MAILBOX2 1163 #define A2S_R2_SPDIF_WR_PTR SNDR2M_2_DSP_MAILBOX3 1164 #define A2S_MBOX_HDMI_NPCM_WRPTR SNDR2M_2_DSP_MAILBOX4 1165 #define A2S_R2_SPDIF_CTRL SNDR2M_2_DSP_MAILBOX5 1166 #define A2S_MBOX_HDMI_NPCM_CMD SNDR2M_2_DSP_MAILBOX5 1167 #define A2S_R2_DOLBY_META_DATA SNDR2M_2_DSP_MAILBOX6 1168 #define A2S_MBOX_DDENC_OUTMCH_WRPTR SNDR2M_2_DSP_MAILBOX6 1169 1170 #define A2S_MBOX_R2_TO_DSP_CTRL SNDR2M_2_DSP_MAILBOX7 1171 #define A2S_DDENC_ENABLE MBOX_BIT0 1172 #define A2S_CMD_SOUND_MIXER_DISABLE_BIT MBOX_BIT1 //[1] SOUND_MIXER, 0:in DSP (MS11), 1:in SND_R2 (MS12) 1173 1174 #define A2S_MBOX_PCMR_DMXPCM_WRPTR SNDR2M_2_DSP_MAILBOX9 // pcmR_dmxPcm from preAsndR2 WRPTR 1175 1176 #define A2S_R2_SOUND_PROCESS_CTRL SNDR2M_2_DSP_MAILBOXF 1177 #define MBOX_PRE_SOUND_PROCESS_DISABLE_BIT MBOX_BIT0 1178 #define MBOX_POST_SOUND_PROCESS_DISABLE_BIT MBOX_BIT1 1179 1180 /******************************************************************** 1181 * DSP io mapping 1182 ********************************************************************/ 1183 #define NULL_IO 0 1184 1185 /* DSP common IO */ 1186 #define DSPIO_SPDIF_IN_FREQ STATUS_SPDIF_FREQ 1187 #define DSPIO_HDMI_IN_FREQ STATUS_HDMI_FREQ 1188 #define DSPIO_HDMI_IN_PC STATUS_HDMI_PC 1189 1190 /* DSP Bounding IO */ 1191 #define DSP_BOUND_OPTION 1 1192 #define DSPIO_BOUND_OPTION 0xA0FF 1193 .const BOUNDING_BIT_DD = 0; //DD 1194 .const BOUNDING_BIT_DDP = 1; //DD+ 1195 .const BOUNDING_BIT_DPULSE = 2; //Dolby Pulse (MS10 DDT) or DDCO 1196 .const BOUNDING_BIT_DVOL = 3; //Dolby Volume 1197 .const BOUNDING_BIT_DTRUEHD = 4; //Dolby TrueHD 1198 .const BOUNDING_BIT_DDDCO = 5; //Dolby DDCO 1199 .const BOUNDING_BIT_DTSENVELO = 6; //DTS Envelo / Symmetry 1200 .const BOUNDING_BIT_DTSDMP = 7; //DTS DMP 1201 .const BOUNDING_BIT_DTSLBR = 8; //DTS LBR 1202 .const BOUNDING_BIT_DTSTS = 9; //DTS Transcoder 1203 .const BOUNDING_BIT_DTSCORELESS = 10; //DTS Coreless 1204 .const BOUNDING_BIT_SRS = 11; //SRS / Adv Sound 1205 .const BOUNDING_BIT_DOLBY = 12; // when bit[12] = 0, all dolby ip's licenses open 1206 1207 //#define AUTH_OPTION 0x0FF2 1208 .const AUTH_BIT_DD = 0; 1209 .const AUTH_BIT_DDP = 1; 1210 .const AUTH_BIT_DDE = 2; 1211 .const AUTH_BIT_DTSDEC = 3; 1212 .const AUTH_BIT_MS10DDT = 4; 1213 .const AUTH_BIT_WMA = 5; 1214 .const AUTH_BIT_DRA = 6; 1215 .const AUTH_BIT_DTSLBR = 7; 1216 .const AUTH_BIT_GAAC = 8; 1217 .const AUTH_BIT_MS11DDT = 9; 1218 .const AUTH_BIT_DEMOMODE = 12; 1219 .const AUTH_BIT_COOK = 16; 1220 .const AUTH_BIT_MS12_D = 19; 1221 .const AUTH_BIT_MS12_B = 21; 1222 1223 /* IP AUTH */ 1224 #define D2S_MBOX_IP_AUTH DEC2SE_MAILBOX7 1225 1226 /* PCM output port */ 1227 #define DSP_SW_DMA_PCM_L_OUT DEC4_PCM1_OUT 1228 #define DSP_SW_DMA_PCM_R_OUT DEC4_PCM2_OUT 1229 #define SIF_DSP_MAIN_DMX_L_OUT DEC4_PCM1_OUT 1230 #define SIF_DSP_MAIN_DMX_R_OUT DEC4_PCM2_OUT 1231 1232 #define R2_PCM1_MCH__L_OUT DEC3_PCM3_OUT 1233 #define R2_PCM1_MCH__C_OUT DEC3_PCM4_OUT 1234 #define R2_PCM1_MCH__R_OUT DEC3_PCM5_OUT 1235 #define R2_PCM1_MCH_LS_OUT DEC3_PCM6_OUT 1236 #define R2_PCM1_MCH_RS_OUT DEC3_PCM7_OUT 1237 #define R2_PCM1_MCH_SW_OUT DEC3_PCM8_OUT 1238 #define R2_PCM1_DMX__L_OUT DEC3_PCM1_OUT 1239 #define R2_PCM1_DMX__R_OUT DEC3_PCM2_OUT 1240 1241 #define R2_PCM2_DMX__L_OUT DEC4_PCM1_OUT 1242 #define R2_PCM2_DMX__R_OUT DEC4_PCM2_OUT 1243 1244 #define R2_PCM1_SYNTH_L DVB3_FIX_SYNTH_NF_L 1245 #define R2_PCM1_SYNTH_H DVB3_FIX_SYNTH_NF_H 1246 #define R2_PCM2_SYNTH_L DVB4_FIX_SYNTH_NF_L 1247 #define R2_PCM2_SYNTH_H DVB4_FIX_SYNTH_NF_H 1248 1249 /************************************************ 1250 * Below is macro for DSP code only 1251 *************************************************/ 1252 #define DSP_DMA_CHECK 1253 1254 #define INC_WHILE_ONE_CNTR ar = dm (S2M_MBOX_WHILE1_CNTR); \ 1255 ay0 = 0x00FF00; \ 1256 af = ar and ay0; \ 1257 ar = ar + 0x000001; \ 1258 ay0 = 0x0000FF; \ 1259 ar = ar and ay0; \ 1260 ar = ar or af; \ 1261 dm (S2M_MBOX_WHILE1_CNTR) = ar 1262 1263 #define INC_DEBUG_CNT(x) ar = dm(kh_debugCnt+x); \ 1264 ar = ar + 1; \ 1265 dm(kh_debugCnt+x) = ar; 1266 1267 #define CONFIG_PCM_OUTPUT_PORT ar = 0; \ 1268 dm (DEC_OUT_SEL) = ar; 1269 1270 #define TRIGGER_INT_TO_MCU ar = 0x0000; IO(PDATA) = ar; \ 1271 nop; nop; nop; nop; \ 1272 nop; nop; nop; nop; \ 1273 ar = 0x8000; IO(PDATA) = ar; \ 1274 nop; nop; nop; nop; \ 1275 nop; nop; nop; nop; \ 1276 ar = 0x0000; IO(PDATA) = ar 1277 1278 /* Saft jump to i0 ~ i7 x:address, y:i0 ~ i7 */ 1279 #define I_REGISTER_JUMP(x,y) sr = lshift x by -16(lo); \ 1280 y = x; \ 1281 CPR = sr0; \ 1282 jump (y); 1283 1284 /* Saft call to i0 ~ i7 x:address, y:i0 ~ i7 */ 1285 #define I_REGISTER_CALL(x,y) sr = lshift x by -16(lo); \ 1286 y = x; \ 1287 CPR = sr0; \ 1288 call (y); 1289 1290 #define SEND_INT_TO_R2(cmd, param) ar = param; \ 1291 dm(S2D_MBOX_DSP_TO_R2_PARAM) = ar; \ 1292 ar = cmd; \ 1293 dm(S2D_MBOX_DSP_TO_R2_COMMAND) = ar 1294 1295 #else 1296 1297 #define DSP2_TO_COMMON_DRAM_OFFSET (ASND_DSP_DDR_SIZE / BYTES_IN_MIU_LINE) 1298 1299 /* DMA Reader Buffer */ 1300 #define DSP2_DMA_READER_DRAM_BASE (DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_DMA_READER_DRAM_BASE /BYTES_IN_MIU_LINE)) 1301 #define DSP2_DMA_READER_DRAM_SIZE ((DMA_READER_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1) 1302 1303 /* HW DMA Reader2 Buffer */ 1304 #define DSP2_HW_DMA_READER2_DRAM_BASE (DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_HW_DMA_READER2_DRAM_BASE /BYTES_IN_MIU_LINE)) 1305 #define DSP2_HW_DMA_READER2_DRAM_SIZE ((HW_DMA_READER2_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1) 1306 1307 /* Software DMA */ 1308 #define DSP2_SW_DMA_READER_DRAM_BASE (DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_SW_DMA_READER_DRAM_BASE / BYTES_IN_MIU_LINE)) 1309 #define DSP2_SW_DMA_READER_DRAM_SIZE ((SW_DMA_READER_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1) 1310 1311 /* PCM capture buffer */ 1312 #define DSP2_PCM_CAPTURE_BUFFER_DRAM_BASE (DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_PCM_CAPTURE1_BUFFER_DRAM_BASE / BYTES_IN_MIU_LINE)) 1313 #define DSP2_PCM_CAPTURE2_BUFFER_DRAM_BASE (DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_PCM_CAPTURE2_BUFFER_DRAM_BASE / BYTES_IN_MIU_LINE)) 1314 #define DSP2_PCM_CAPTURE3_BUFFER_DRAM_BASE (DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_PCM_CAPTURE3_BUFFER_DRAM_BASE / BYTES_IN_MIU_LINE)) 1315 #define DSP2_PCM_CAPTURE_BUFFER_DRAM_SIZE (PCM_CAPTURE_BUFFER_DRAM_SIZE/ BYTES_IN_MIU_LINE) 1316 #define DSP2_PCM_CAPTURE2_BUFFER_DRAM_SIZE (PCM_CAPTURE2_BUFFER_DRAM_SIZE/ BYTES_IN_MIU_LINE) 1317 #define DSP2_PCM_CAPTURE_COPY_WORDSIZE 32 1318 #define DSP2_PCM_CAPTURE_COPY_LINESIZE 4 1319 1320 #endif //_COMPILE_DSP_ 1321 1322 //Reseved XBox 1323 /* srs puresound */ 1324 //reserved XBox for SRS start from XBox 0xB960 1325 #define DSP2XboxAddr_SRS_PURESOUND_RESERVED1 0xB960 1326 1327 #define SRS_PURESOUND_AeqFir_NumOfTaps_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+1 1328 #define SRS_PURESOUND_AeqIir_NumOfSections_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+2 1329 #define SRS_PURESOUND_AeqIir1Coefs_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+3 1330 #define SRS_PURESOUND_AeqIir2Coefs_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+8 1331 #define SRS_PURESOUND_AeqIir3Coefs_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+13 1332 #define SRS_PURESOUND_AeqIir4Coefs_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+18 1333 #define SRS_PURESOUND_AeqIir5Coefs_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+23 1334 #define SRS_PURESOUND_AeqIir6Coefs_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+28 1335 #define SRS_PURESOUND_AeqIir7Coefs_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+33 1336 #define SRS_PURESOUND_AeqIir8Coefs_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+38 1337 #define SRS_PURESOUND_AeqIir1_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+43 1338 #define SRS_PURESOUND_AeqIir2_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+44 1339 #define SRS_PURESOUND_AeqIir3_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+45 1340 #define SRS_PURESOUND_AeqIir4_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+46 1341 #define SRS_PURESOUND_AeqIir5_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+47 1342 #define SRS_PURESOUND_AeqIir6_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+48 1343 #define SRS_PURESOUND_AeqIir7_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+49 1344 #define SRS_PURESOUND_AeqIir8_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+50 1345 #define SRS_PURESOUND_AeqIir_Gain_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+51 1346 #define SRS_PURESOUND_AeqIir_Gain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+52 1347 #define SRS_PURESOUND_AeqFir_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+53 1348 #define SRS_PURESOUND_AeqFir_Gain_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+54 1349 #define SRS_PURESOUND_AeqFir_Gain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+55 1350 #define SRS_PURESOUND_AeqFirCoefs_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+64 1351 1352 #define DSP2XboxAddr_SRS_PURESOUND_RESERVED2 SRS_PURESOUND_AeqFirCoefs_addr+1 1353 #define SRS_PURESOUND_mDummy_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2 1354 #define SRS_PURESOUND_SRS_EN_BITS_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+1 1355 #define SRS_PURESOUND_mInputGain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+2 1356 #define SRS_PURESOUND_mOutputGain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+3 1357 #define SRS_PURESOUND_mBypassGain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+4 1358 #define SRS_PURESOUND_mHPFfc_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+5 1359 #define SRS_PURESOUND_hlInputGain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+25 1360 #define SRS_PURESOUND_hlOutputGain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+26 1361 #define SRS_PURESOUND_hlBypassGain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+27 1362 #define SRS_PURESOUND_hlLimiterboost_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+28 1363 #define SRS_PURESOUND_hlHardLimit_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+29 1364 #define SRS_PURESOUND_hlDelaylen_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+30 1365 #define SRS_PURESOUND_AeqInputGain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+32 1366 #define SRS_PURESOUND_AeqOutputGain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+33 1367 #define SRS_PURESOUND_AeqBypassGain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+34 1368 1369 #define DSP2XboxAddr_SRS_PURESOUND_RESERVED_END SRS_PURESOUND_AeqBypassGain_addr 1370 1371 /* atv */ 1372 //reserved XBox for ATV 1373 #define DSP2XboxAddr_ATV_RESERVED1 DSP2XboxAddr_SRS_PURESOUND_RESERVED_END+1 1374 #define DSP2XboxAddr_AU_PAL_SYS_THRESHOLD DSP2XboxAddr_ATV_RESERVED1 1375 #define DSP2XboxAddr_SIF_PM_GAIN_TBL_PAL DSP2XboxAddr_AU_PAL_SYS_THRESHOLD+12 1376 #define DSP2XboxAddr_SIF_PM_GAIN_TBL_BTSC DSP2XboxAddr_AU_PAL_SYS_THRESHOLD+12 1377 #define DSP2XboxAddr_ATV_RESERVED_END DSP2XboxAddr_SIF_PM_GAIN_TBL_BTSC+8-1 1378 1379 /************************************************ 1380 * For Compile Pass mailbox (Need to remove later) 1381 ************************************************/ 1382 1383 #define D2M_MBOX_INTR_CMDTYPE MB_2DB2 1384 #define DSP1PmAddr_ipSecurity 0x0FF2 1385 #define D2M_MBOX_ENC_LINEADDR MB_2DAC //MPEG Encoder 1386 #define D2M_MBOX_ENC_LINESIZE MB_2DAE //MPEG Encoder 1387 #define M2D_MBOX_PIO_ID MB_2D8A 1388 #define DSP1PmAddr_smpRate 0x0FF7 1389 #define D2M_MBOX_HDMI_NPCM_LOCK MB_2DB4 //[ 3:0] Always in LSB Nibble 1390 #define MBOX_DBGCMD_RELOAD_DTV1_BEG 0xF000 1391 #define MBOX_DBGCMD_RELOAD_DTV1_END 0xF100 1392 #define MBOX_DBGCMD_RELOAD_DTV2_BEG 0xF600 1393 #define MBOX_DBGCMD_RELOAD_DTV2_END 0xF700 1394 #define DSP1DmAddr_sys_IoInfo NULL 1395 #define M2D_MBOX_MM_FILEIN_TAG MB_2D8C 1396 #define MBOX_DSP_INIT_ACK 0xE300 1397 #define D2M_MBOX_DBG_RESULT2 MB_2DBE 1398 #define D2M_MBOX_DBG_RESULT1 MB_2DBC 1399 #define M2D_MBOX_DEC_CTRL MB_2D86 1400 #define M2D_MBOX_DBG_CMD1 MB_2D9C 1401 1402 #define D2M_MBOX_DBG_RESULT1 MB_2DBC 1403 #define MBOX_DSP_INIT_ACK 0xE300 1404 #define D2M_MBOX_DBG_RESULT2 MB_2DBE 1405 #define MBOX_DSP_RELOAD_ACK1 0x0033 1406 #define MBOX_DSP_RELOAD_ACK2 0x0077 1407 #define M2D_MBOX_DEC_CTRL MB_2D86 1408 #define D2M_MBOX_SAMPLERATE MB_2DA6 1409 #define DSP1DmAddr_dec1_param 0x47A0 1410 #define DSP1DmAddr_dec1_info 0x47C0 1411 #define DSP1DmAddr_dec1_omx_param 0x42B4 1412 #define M2D_MBOX_UNI_PCM3_WRPTR MB_2D94 1413 #define DSP1PmAddr_video_TD 0x0FF1 1414 #define D2M_MBOX_UNI_PCM_BUFFEBT MB_2D6A 1415 1416 //// SIF /* SIF DSP PM vars */ // for SIF PAL DSP PM vars // 1417 #define ADDR_gain_base 0x1921 1418 #define ADDR_thr_base 0x1A20 1419 #define ADDR_pfir_base 0x1A90 // for SIF BTSC DSP PM vars // 1420 #define BTSC_COMPILE_OPTION_Addr 0x19F1 // len 1 1421 #define BTSC_OUTPUT_GAIN_Addr 0x1A21 // len 2 1422 #define BTSC_THRESHOLD_Addr 0x1A23 // len 10 1423 #define MTS_OUTPUT_GAIN_Addr 0x1A34 //len 6 1424 #define SIF_AGC_THRESHOLD_Addr 0x192D //len 3 /// PAL gain setting address 1425 #define ADDR_fm_stdM_gain ADDR_gain_base // len = 4 1426 #define ADDR_fm_stdX_gain ADDR_fm_stdM_gain+4 // len = 4 1427 #define ADDR_nicam_gain ADDR_fm_stdX_gain+4 // len = 2 1428 #define ADDR_am_gain ADDR_nicam_gain+2 // len = 2 1429 #define ADDR_agc_gain ADDR_am_gain+2 // len = 24 // PAL threshold setting address 1430 #define ADDR_a2_stdM_thr ADDR_thr_base // len = 15 1431 #define ADDR_a2_stdBG_thr ADDR_a2_stdM_thr+15 // len = 15 1432 #define ADDR_a2_stdDK_thr ADDR_a2_stdBG_thr+15 // len = 15 1433 #define ADDR_a2_stdI_thr ADDR_a2_stdDK_thr+15 // len = 4 1434 #define ADDR_am_thr ADDR_a2_stdI_thr+4 // len = 3 1435 #define ADDR_hidev_stdM_thr ADDR_am_thr+3 // len = 4 1436 #define ADDR_hidev_stdBG_thr ADDR_hidev_stdM_thr+4 // len = 4 1437 #define ADDR_hidev_stdDK_thr ADDR_hidev_stdBG_thr+4 // len = 4 1438 #define ADDR_hidev_stdI_thr ADDR_hidev_stdDK_thr+4 // len = 4 1439 #define ADDR_nicam_stdBG_pherr_thr ADDR_hidev_stdI_thr+4 //len = 3 1440 #define ADDR_nicam_stdI_pherr_thr ADDR_nicam_stdBG_pherr_thr+3 // len = 3 1441 #define ADDR_a2_bg_nicam_fm_nsr_thr 0x186F // len = 1 1442 #define ADDR_a2_dk_nicam_fm_nsr_thr 0x1870 // len = 1 // pfir setting address 1443 #define ADDR_hidev_demfir ADDR_pfir_base // len = 15 1444 #define ADDR_fm_ch1_pfir ADDR_hidev_demfir+16 // len = 30 1445 #define ADDR_fm_ch2_pfir ADDR_fm_ch1_pfir+30 // len = 30 1446 #define ADDR_hidev_lv1_pfir ADDR_fm_ch2_pfir+30 // len = 20 1447 #define ADDR_hidev_lv2_pfir ADDR_hidev_lv1_pfir+20 // len = 20 1448 #define ADDR_hidev_lv3_pfir ADDR_hidev_lv2_pfir+20 // len = 20 // BTSC threshold setting address 1449 #define HIDEV_NSR_THRESHOLD_Addr BTSC_THRESHOLD_Addr+10 // len 2 1450 #define BTSC_MONO_AMP_THRESHOLD_Addr HIDEV_NSR_THRESHOLD_Addr+2 // len 2 1451 #define HIDEV_AMP_THRESHOLD_Addr BTSC_MONO_AMP_THRESHOLD_Addr+2 // len 2 1452 #define BTSC_SAP_PHASE_DIFF_CLIP_THR_Addr HIDEV_AMP_THRESHOLD_Addr+2 // len 1 1453 #define BTSC_PILOT_DEBOUNCE_THRESHOLD_Addr MTS_OUTPUT_GAIN_Addr+6 // len 3 1454 #define BTSC_SAP_ON_DETECTION_DEBOUNCE_THRESHOLD_Addr BTSC_PILOT_DEBOUNCE_THRESHOLD_Addr+3 // len 1 1455 1456 #define M2S_MBOX_MM_FILEIN_TAG MB_2DCC //[7:0] 1457 #define DSP2PmAddr_smpRate 0x0D49 1458 #define DSP2PmAddr_soundMode 0x0D4A 1459 #define DSP2DmAddr_dec1_param 0x4390 1460 #define DSP2DmAddr_hdmi_debugInfo 0x396A 1461 #define DSP2DmAddr_spdif_debugInfo 0x3832 1462 #define M2S_MBOX_DRC_CTRL MB_2D2E 1463 1464 /* SIF DSP PM vars */ 1465 /* for SIF PAL DSP PM vars */ 1466 1467 #define ADDR_gain_base_2 NULL 1468 #define ADDR_thr_base_2 NULL 1469 #define ADDR_pfir_base_2 NULL 1470 // for SIF BTSC DSP PM vars // 1471 #define BTSC_COMPILE_OPTION_Addr_2 NULL // len 1 1472 #define BTSC_OUTPUT_GAIN_Addr_2 NULL // len 2 1473 #define BTSC_THRESHOLD_Addr_2 NULL // len 10 1474 #define MTS_OUTPUT_GAIN_Addr_2 NULL //len 6 1475 #define SIF_AGC_THRESHOLD_Addr_2 NULL //len 3 1476 1477 /// PAL gain setting address 1478 #define ADDR_fm_stdM_gain_2 NULL // len = 4 1479 #define ADDR_fm_stdX_gain_2 NULL // len = 4 1480 #define ADDR_nicam_gain_2 NULL // len = 2 1481 #define ADDR_am_gain_2 NULL // len = 2 1482 #define ADDR_agc_gain_2 NULL // len = 24 1483 1484 // PAL threshold setting address 1485 #define ADDR_a2_stdM_thr_2 NULL // len = 15 1486 #define ADDR_a2_stdBG_thr_2 NULL // len = 15 1487 #define ADDR_a2_stdDK_thr_2 NULL // len = 15 1488 #define ADDR_a2_stdI_thr_2 NULL // len = 4 1489 #define ADDR_am_thr_2 NULL // len = 3 1490 #define ADDR_hidev_stdM_thr_2 NULL // len = 4 1491 #define ADDR_hidev_stdBG_thr_2 NULL // len = 4 1492 #define ADDR_hidev_stdDK_thr_2 NULL // len = 4 1493 #define ADDR_hidev_stdI_thr_2 NULL // len = 4 1494 #define ADDR_nicam_stdBG_pherr_thr_2 NULL //len = 3 1495 #define ADDR_nicam_stdI_pherr_thr_2 NULL // len = 3 1496 #define ADDR_a2_bg_nicam_fm_nsr_thr_2 NULL // len = 1 1497 #define ADDR_a2_dk_nicam_fm_nsr_thr_2 NULL // len = 1 1498 1499 // pfir setting address 1500 #define ADDR_hidev_demfir_2 NULL // len = 15 1501 #define ADDR_fm_ch1_pfir_2 NULL // len = 30 1502 #define ADDR_fm_ch2_pfir_2 NULL // len = 30 1503 #define ADDR_hidev_lv1_pfir_2 NULL // len = 20 1504 #define ADDR_hidev_lv2_pfir_2 NULL // len = 20 1505 #define ADDR_hidev_lv3_pfir_2 NULL // len = 20 1506 1507 // BTSC threshold setting address 1508 #define HIDEV_NSR_THRESHOLD_Addr_2 NULL // len 2 1509 #define BTSC_MONO_AMP_THRESHOLD_Addr_2 NULL // len 2 1510 #define HIDEV_AMP_THRESHOLD_Addr_2 NULL // len 2 1511 1512 #define BTSC_SAP_PHASE_DIFF_CLIP_THR_Addr_2 NULL // len 1 1513 #define BTSC_PILOT_DEBOUNCE_THRESHOLD_Addr_2 NULL // len 3 1514 #define BTSC_SAP_ON_DETECTION_DEBOUNCE_THRESHOLD_Addr_2 NULL // len 1 1515 1516 /************************************************ 1517 * End for Compile Pass mailbox (Need to remove later) 1518 ************************************************/ 1519 1520 1521 #endif //_AUDIO_COMM2_H_ 1522