1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 #ifndef _AUDIO_COMM2_H_ 79 #define _AUDIO_COMM2_H_ 80 81 82 #include "audio_mbox2.h" 83 #include "ddr_config.h" 84 85 #ifdef _COMPILE_DSP_ 86 #include "Sys_def.h" 87 #endif 88 89 /************************************************ 90 * ½Ð«O«ù Utopia ©M DSP ¸Ìªº³oÓÀɮפ@P 91 * 92 * 1. µù¸Ñ¤£n¥Î ! 93 * 2. «Å§i¤£n¥Î .const xxxx = ????; 94 ************************************************/ 95 96 97 /********************************************************* 98 * Version Control 99 *********************************************************/ 100 #define system_version_num 0x000B6C 101 #define dde_version_num 0xD20051 102 #define ms10_dde_version_num 0xD800C1 103 #define btscEnc_version_num 0xEF0126 104 #define fmTx_version_num 0xED010C 105 #define ms12_ddpe_version_num 0xEC3017 106 107 #define AUDIO_DSP2_VERSION (system_version_num + dde_version_num + ms10_dde_version_num + btscEnc_version_num + fmTx_version_num + ms12_ddpe_version_num) 108 109 110 /********************************************************* 111 * system define 112 *********************************************************/ 113 #define DSP2_DDP_HDMI_BYPASS_EN 0 114 115 /* ASND System Channels */ 116 #define SE_PROCESS_FETCH_CHANNELS 12 // SE_Buffer input channels 117 #define SE_PROCESS_STORE_CHANNELS 8 // SE_Buffer output channels 118 #define SPDIF_DELAY_STORE_CHANNELS 2 // SPDIF Buffer channels 119 #define HDMI_DELAY_STORE_CHANNELS 2 // HDMI Buffer channels 120 121 /* DSP Audio Delay Setting */ 122 #define AUDIO_DELAY_FS 48 // fs = 48kHz 123 #define SPDIF_DELAY_FS 48 124 #define HDMI_DELAY_FS 48 125 #define DMA24BIT_BYTES_IN_WORDS 3 126 #define DMA16BIT_BYTES_IN_WORDS 2 127 128 #define AUDIO_DELAY_LOWER_BOUND 0x30 // min main audio delay , 0x30 = 48 ms 129 #define SPDIF_DELAY_LOWER_BOUND 0x05 // min spdif audio delay, 0x05 = 5 ms 130 #define HDMI_DELAY_LOWER_BOUND 0x05 // min hdmi audio delay , 0x05 = 5 ms 131 #define KTV_DELAY_LOWER_BOUND 0x10 // min ktv audio delay , 0x14 = 20 ms 132 #define AUDIO_DELAY_UPPER_BOUND ((SE_MAIN_IN_DRAM_SIZE/SE_PROCESS_FETCH_CHANNELS + SE_MAIN_OUT_DRAM_SIZE/SE_PROCESS_STORE_CHANNELS)/DMA24BIT_BYTES_IN_WORDS/AUDIO_DELAY_FS) 133 #define SPDIF_DELAY_UPPER_BOUND ((SPDIF_DLY_DRAM_SIZE/SPDIF_DELAY_STORE_CHANNELS)/DMA16BIT_BYTES_IN_WORDS/SPDIF_DELAY_FS) 134 #define HDMI_DELAY_UPPER_BOUND ((SE_HDMI_DLY_DRAM_SIZE/HDMI_DELAY_STORE_CHANNELS)/DMA16BIT_BYTES_IN_WORDS/HDMI_DELAY_FS) 135 136 /* Audio Ease */ 137 #define AUDIO_EASE_TYPE_LINEAR 0 138 #define AUDIO_EASE_TYPE_INCUBIC 1 139 #define AUDIO_EASE_TYPE_OUTCUBIC 2 140 #define AUDIO_EASE_TYPE_INOUTCUBIC 3 141 142 #define AUDIO_EASE_CH_NONE 0 143 #define AUDIO_EASE_CH_A 1 144 #define AUDIO_EASE_CH_B 2 145 146 /************************************************ 147 * DSP sram address mapping 148 ************************************************/ 149 /* DSP SRAM Segment */ 150 /* CM */ 151 #define DSP2_CM_MAIN_ADDR 0x0 152 #define DSP2_CM_MAIN_SIZE 0x1000 153 #define DSP2_CM_CODE1_ADDR 0x1000 154 #define DSP2_CM_CODE1_SIZE 0x0400 155 #define DSP2_CM_CODE2_ADDR 0x1400 156 #define DSP2_CM_CODE2_SIZE 0x0000 157 158 /* PM */ 159 #define DSP2_PM_MAIN_ADDR 0x1400 160 #define DSP2_PM_MAIN_SIZE 0x02FF 161 #define DSP2_PM_SEG1_ADDR 0x16FF 162 #define DSP2_PM_SEG1_SIZE 0x3101 163 #define DSP2_PM_SEG2_ADDR 0x4800 164 #define DSP2_PM_SEG2_SIZE 0x0000 165 166 /* Prefetch */ 167 #define DSP2_PM_PREFETCH_DSPADDR 0x10000 // check "arch.sys" 168 #define DSP2_PM_PREFETCH_DDRADDR DSP2_PM_PREFETCH_DSPADDR*3/BYTES_IN_MIU_LINE 169 #define DSP2_PM_PREFETCH2_DSPADDR 0x10000 // check "arch.sys" 170 #define DSP2_PM_PREFETCH2_DDRADDR DSP2_PM_PREFETCH2_DSPADDR*3/BYTES_IN_MIU_LINE 171 172 /* DM */ 173 #define DSP2_DM_MAIN_ADDR 0x3300 174 #define DSP2_DM_MAIN_SIZE 0x0D00 175 #define DSP2_DM_SEG1A_ADDR 0x0 176 #define DSP2_DM_SEG1A_SIZE 0x3300 177 #define DSP2_DM_SEG1B_ADDR 0x3300 178 #define DSP2_DM_SEG1B_SIZE 0x0 179 #define DSP2_DM_SEG2_ADDR 0x3300 180 #define DSP2_DM_SEG2_SIZE 0x0 181 182 /* XBox */ 183 #define DSP2_XBOX_MAIN_ADDR 0xB800 184 #define DSP2_XBOX_MAIN_SIZE 0x200 185 186 /* SND DSP PM vars */ 187 /* common */ 188 #define DSP2PmAddr_mainVer (DSP2_PM_MAIN_ADDR) //0x1900 189 #define DSP2PmAddr_alg1Ver (DSP2_PM_SEG1_ADDR) //0x1BFF // decoder 2 version 190 #define DSP2PmAddr_alg2Ver (DSP2_PM_MAIN_ADDR-1) 191 192 #define DSP2PmAddr_peq48KCoeffAddr (DSP2PmAddr_mainVer + 1) 193 #define DSP2PmAddr_peq32KCoeffAddr (DSP2PmAddr_peq48KCoeffAddr) 194 #define DSP2PmAddr_peqscale48KAddr (DSP2PmAddr_peq48KCoeffAddr + 40 ) 195 #define DSP2PmAddr_peqbandEnAddr (DSP2PmAddr_peqscale48KAddr + 8 ) 196 #define DSP2PmAddr_peqbandDoubleAddr (DSP2PmAddr_peqbandEnAddr + 1 ) 197 #define DSP2PmAddr_hpf48KCoeffAddr (DSP2PmAddr_peqbandDoubleAddr + 1 ) 198 #define DSP2PmAddr_toneSelectAddr (DSP2PmAddr_hpf48KCoeffAddr + 5 ) 199 #define DSP2PmAddr_bass48KCoeffAddr (DSP2PmAddr_toneSelectAddr + 1 ) 200 #define DSP2PmAddr_bassscale48KAddr (DSP2PmAddr_bass48KCoeffAddr + 5 ) 201 #define DSP2PmAddr_treble48KCoeffAddr (DSP2PmAddr_bassscale48KAddr + 1 ) 202 #define DSP2PmAddr_treblescale48KAddr (DSP2PmAddr_treble48KCoeffAddr + 5 ) 203 #define DSP2PmAddr_VolEaseAddr (DSP2PmAddr_treblescale48KAddr + 1 ) 204 205 /* ATV_Enc */ 206 #define DSP2_PM_ATV_Enc_input_attenuation_ADDR (DSP2PmAddr_alg1Ver+1) 207 #define DSP2_PM_ATV_Enc_output_scaling_ADDR (DSP2PmAddr_alg1Ver+2) 208 #define DSP2_PM_BTSC_Enc_output_M_gain_ADDR (DSP2PmAddr_alg1Ver+3) 209 #define DSP2_PM_BTSC_Enc_output_D_gain_ADDR (DSP2PmAddr_alg1Ver+4) 210 #define DSP2_PM_BTSC_Enc_output_SAP_gain_ADDR (DSP2PmAddr_alg1Ver+5) 211 212 /* SND DSP DM vars */ 213 214 /* Extra Box Address */ 215 216 /* sys_param */ 217 #define DSP2XboxAddr_mainVer 0xB800 218 #define DSP2XboxAddr_mainAudioDelay (DSP2XboxAddr_mainVer + 0x01) 219 #define DSP2XboxAddr_spdifDelay (DSP2XboxAddr_mainVer + 0x02) 220 #define DSP2XboxAddr_hpDelay (DSP2XboxAddr_mainVer + 0x03) 221 #define DSP2XboxAddr_hdmiNonPcmSts (DSP2XboxAddr_mainVer + 0x04) 222 #define DSP2XboxAddr_btFrameSize (DSP2XboxAddr_mainVer + 0x05) 223 #define DSP2XboxAddr_ipSecurity (DSP2XboxAddr_mainVer + 0x06) 224 #define DSP2XboxAddr_hdmiDelay (DSP2XboxAddr_mainVer + 0x07) 225 226 #define DSP2XboxAddr_peq48KCoeffAddr (DSP2XboxAddr_mainVer + 0x10) // len 40 227 #define DSP2XboxAddr_peq32KCoeffAddr (DSP2XboxAddr_peq48KCoeffAddr) 228 #define DSP2XboxAddr_peqscale48KAddr (DSP2XboxAddr_mainVer + 0x38) // len 8 229 #define DSP2XboxAddr_peqbandEnAddr (DSP2XboxAddr_mainVer + 0x40) // len 1 230 #define DSP2XboxAddr_peqbandDoubleAddr (DSP2XboxAddr_mainVer + 0x41) // len 1 231 #define DSP2XboxAddr_hpf48KCoeffAddr (DSP2XboxAddr_mainVer + 0x42) // len 5 232 #define DSP2XboxAddr_toneSelectAddr (DSP2XboxAddr_mainVer + 0x47) // len 1 233 #define DSP2XboxAddr_bass48KCoeffAddr (DSP2XboxAddr_mainVer + 0x48) // len 5 234 #define DSP2XboxAddr_bassscale48KAddr (DSP2XboxAddr_mainVer + 0x4D) // len 1 235 #define DSP2XboxAddr_treble48KCoeffAddr (DSP2XboxAddr_mainVer + 0x4E) // len 5 236 #define DSP2XboxAddr_treblescale48KAddr (DSP2XboxAddr_mainVer + 0x53) // len 1 237 #define DSP2XboxAddr_VolEaseAddr (DSP2XboxAddr_mainVer + 0x54) // len 9 238 #define DSP2XboxAddr_AVCRmodeP1 (DSP2XboxAddr_mainVer + 0x5D) // len 1 239 #define DSP2XboxAddr_AVCRmodeP2 (DSP2XboxAddr_mainVer + 0x5E) // len 1 240 #define DSP2XboxAddr_AVCRmodeType (DSP2XboxAddr_mainVer + 0x5F) // len 1 241 242 #define DSP2XboxAddr_peqUpdateFlag (DSP2XboxAddr_mainVer + 0x60) // len 1 243 #define DSP2XboxAddr_hpUpdateFlag (DSP2XboxAddr_mainVer + 0x61) // len 1 244 #define DSP2XboxAddr_bassUpdateFlag (DSP2XboxAddr_mainVer + 0x62) // len 1 245 #define DSP2XboxAddr_trebleUpdateFlag (DSP2XboxAddr_mainVer + 0x63) // len 1 246 #define DSP2XboxAddr_toneUpdateFlag (DSP2XboxAddr_mainVer + 0x64) // len 1 247 #define DSP2XboxAddr_easeAUpdateFlag (DSP2XboxAddr_mainVer + 0x65) // len 1 248 #define DSP2XboxAddr_easeBUpdateFlag (DSP2XboxAddr_mainVer + 0x66) // len 1 249 #define DSP2XboxAddr_mSurrUpdateFlag (DSP2XboxAddr_mainVer + 0x67) // len 1 250 #define DSP2XboxAddr_mSurrReverbLen (DSP2XboxAddr_mainVer + 0x68) // len 1 251 #define DSP2XboxAddr_avcUpdateFlag (DSP2XboxAddr_mainVer + 0x69) // len 1 252 253 #define DSP2XboxAddr_ATVEnc_input_attenuation_ADDR (DSP2XboxAddr_mainVer + 0x6A) // len 1 254 #define DSP2XboxAddr_ATVEnc_output_scaling_ADDR (DSP2XboxAddr_ATVEnc_input_attenuation_ADDR + 1) 255 #define DSP2XboxAddr_BTSCEnc_output_M_gain_ADDR (DSP2XboxAddr_ATVEnc_output_scaling_ADDR + 1) 256 #define DSP2XboxAddr_BTSCEnc_output_D_gain_ADDR (DSP2XboxAddr_BTSCEnc_output_M_gain_ADDR + 1) 257 #define DSP2XboxAddr_BTSCEnc_output_SAP_gain_ADDR (DSP2XboxAddr_BTSCEnc_output_D_gain_ADDR + 1) 258 259 /* sys_info */ 260 #define DSP2XboxAddr_IO_Info1 0xB900 261 #define IO_INFO1_DAC1_OUT 0x0000 262 #define IO_INFO1_DAC2_OUT 0x0002 263 #define IO_INFO1_DAC3_OUT 0x0004 264 #define IO_INFO1_DAC4_OUT 0x0006 265 #define IO_INFO1_IIS1_OUT 0x0008 266 #define IO_INFO1_SPDIF_OUT 0x000A 267 #define IO_INFO1_HDMI_OUT 0x000C 268 269 #define DSP2XboxAddr_IO_Info2 DSP2XboxAddr_IO_Info1 + 0x000E 270 #define IO_INFO2_MUL_CH1 0x0000 271 #define IO_INFO2_MUL_CH2 0x0002 272 #define IO_INFO2_MUL_CH3 0x0004 273 #define IO_INFO2_MUL_CH4 0x0006 274 #define IO_INFO2_RAW 0x0008 275 #define IO_INFO2_RAW_DELAY 0x000A 276 #define IO_INFO2_RAW_DELAY_SE 0x000C 277 #define IO_INFO2_SCART 0x000E 278 #define IO_INFO2_KTV 0x0010 279 #define IO_INFO2_MUL_CH6 0x0012 280 #define IO_INFO2_SPDIF_DATA 0x0014 281 #define IO_INFO2_RESERVED4 0x0016 282 #define IO_INFO2_SINTONE 0x0018 283 #define IO_INFO2_MUL_CH8 0x001A 284 #define IO_INFO2_GPA_FS 0x001C 285 #define IO_INFO2_GPB_FS 0x001D 286 #define IO_INFO2_GPC_FS 0x001E 287 #define IO_INFO2_ALSA_MODE 0x001F 288 289 290 /* common */ 291 #define DSP2XboxAddr_dec1_signal_energy (DSP2XboxAddr_IO_Info2 + 0x0020) // len 1 292 #define DSP2XboxAddr_pcmCapture_overflow (DSP2XboxAddr_IO_Info2 + 0x0021) // len 1 293 #define DSP2XboxAddr_pcmCapture_underflow (DSP2XboxAddr_IO_Info2 + 0x0022) // len 1 294 #define DSP2XboxAddr_pcmCapture_volume (DSP2XboxAddr_IO_Info2 + 0x0023) // len 1 295 #define DSP2XboxAddr_pcmCapture2_overflow (DSP2XboxAddr_IO_Info2 + 0x0024) // len 1 296 #define DSP2XboxAddr_pcmCapture2_underflow (DSP2XboxAddr_IO_Info2 + 0x0025) // len 1 297 #define DSP2XboxAddr_pcmCapture2_volume (DSP2XboxAddr_IO_Info2 + 0x0026) // len 1 298 #define DSP2XboxAddr_pcmCapture3_overflow (DSP2XboxAddr_IO_Info2 + 0x0027) // len 1 299 #define DSP2XboxAddr_pcmCapture3_underflow (DSP2XboxAddr_IO_Info2 + 0x0028) // len 1 300 #define DSP2XboxAddr_pcmCapture3_volume (DSP2XboxAddr_IO_Info2 + 0x0029) // len 1 301 #define DSP2XboxAddr_swDmaRdr_ctrlBase (DSP2XboxAddr_IO_Info2 + 0x002A) // len 11 302 303 #define DSP2XboxAddr_hdmi_npcm_lock (DSP2XboxAddr_IO_Info2 + 0x0035) // len 1 304 #define DSP2XboxAddr_hdmi_unstable_protect (DSP2XboxAddr_IO_Info2 + 0x0036) // len 1 305 #define DSP2XboxAddr_hdmi_unstable_threshold (DSP2XboxAddr_IO_Info2 + 0x0037) // len 1 306 #define DSP2XboxAddr_hdmi_decimation_mode_flag (DSP2XboxAddr_IO_Info2 + 0x0038) // len 2 307 308 #define DSP2XboxAddr_mips_crisis_flag (DSP2XboxAddr_IO_Info2 + 0x003A) // len 1 309 310 /* basic sound effect */ 311 #define DSP2XboxAddr_AvcSOffsetAddr (DSP2XboxAddr_IO_Info2 + 0x003B) // len 1 312 #define DSP2XboxAddr_KTV_XAGain (DSP2XboxAddr_IO_Info2 + 0x003C) // len 1 313 #define DSP2XboxAddr_KTV_XBGain (DSP2XboxAddr_IO_Info2 + 0x003D) // len 1 314 #define DSP2XboxAddr_Multi_Channel_VOL (DSP2XboxAddr_IO_Info2 + 0x003E) // len 1 315 316 317 /******************************************************************** 318 * Decoder default setting 319 ********************************************************************/ 320 /* SIF DSP PM vars */ 321 /* 322 #define ADDR_gain_base_2 0x2521 //B860 323 #define ADDR_thr_base_2 0x2620 324 #define ADDR_pfir_base_2 0x2690 325 // for SIF BTSC DSP PM vars // 326 #define BTSC_COMPILE_OPTION_Addr_2 0x25F1 // len 1 327 #define BTSC_OUTPUT_GAIN_Addr_2 0x2621 // len 2 328 #define BTSC_THRESHOLD_Addr_2 0x2623 // len 10 329 #define MTS_OUTPUT_GAIN_Addr_2 0x2634 //len 6 330 #define SIF_AGC_THRESHOLD_Addr_2 0x252D //len 3 331 332 /// PAL gain setting address 333 #define ADDR_fm_stdM_gain_2 ADDR_gain_base_2 // len = 4 334 #define ADDR_fm_stdX_gain_2 ADDR_fm_stdM_gain_2+4 // len = 4 335 #define ADDR_nicam_gain_2 ADDR_fm_stdX_gain_2+4 // len = 2 336 #define ADDR_am_gain_2 ADDR_nicam_gain_2+2 // len = 2 337 #define ADDR_agc_gain_2 ADDR_am_gain_2+2 // len = 24 338 339 // PAL threshold setting address 340 #define ADDR_a2_stdM_thr_2 ADDR_thr_base_2 // len = 15 341 #define ADDR_a2_stdBG_thr_2 ADDR_a2_stdM_thr_2+15 // len = 15 342 #define ADDR_a2_stdDK_thr_2 ADDR_a2_stdBG_thr_2+15 // len = 15 343 #define ADDR_a2_stdI_thr_2 ADDR_a2_stdDK_thr_2+15 // len = 4 344 #define ADDR_am_thr_2 ADDR_a2_stdI_thr_2+4 // len = 3 345 #define ADDR_hidev_stdM_thr_2 ADDR_am_thr_2+3 // len = 4 346 #define ADDR_hidev_stdBG_thr_2 ADDR_hidev_stdM_thr_2+4 // len = 4 347 #define ADDR_hidev_stdDK_thr_2 ADDR_hidev_stdBG_thr_2+4 // len = 4 348 #define ADDR_hidev_stdI_thr_2 ADDR_hidev_stdDK_thr_2+4 // len = 4 349 #define ADDR_nicam_stdBG_pherr_thr_2 ADDR_hidev_stdI_thr_2+4 //len = 3 350 #define ADDR_nicam_stdI_pherr_thr_2 ADDR_nicam_stdBG_pherr_thr_2+3 // len = 3 351 #define ADDR_a2_bg_nicam_fm_nsr_thr_2 0x246F // len = 1 352 #define ADDR_a2_dk_nicam_fm_nsr_thr_2 0x2470 // len = 1 353 354 // pfir setting address 355 #define ADDR_hidev_demfir_2 ADDR_pfir_base_2 // len = 15 356 #define ADDR_fm_ch1_pfir_2 ADDR_hidev_demfir_2+16 // len = 30 357 #define ADDR_fm_ch2_pfir_2 ADDR_fm_ch1_pfir_2+30 // len = 30 358 #define ADDR_hidev_lv1_pfir_2 ADDR_fm_ch2_pfir_2+30 // len = 20 359 #define ADDR_hidev_lv2_pfir_2 ADDR_hidev_lv1_pfir_2+20 // len = 20 360 #define ADDR_hidev_lv3_pfir_2 ADDR_hidev_lv2_pfir_2+20 // len = 20 361 362 // BTSC threshold setting address 363 #define HIDEV_NSR_THRESHOLD_Addr_2 BTSC_THRESHOLD_Addr_2+10 // len 2 364 #define BTSC_MONO_AMP_THRESHOLD_Addr_2 HIDEV_NSR_THRESHOLD_Addr_2+2 // len 2 365 #define HIDEV_AMP_THRESHOLD_Addr_2 BTSC_MONO_AMP_THRESHOLD_Addr_2+2 // len 2 366 367 #define BTSC_SAP_PHASE_DIFF_CLIP_THR_Addr_2 HIDEV_AMP_THRESHOLD_Addr_2+2 // len 1 368 #define BTSC_PILOT_DEBOUNCE_THRESHOLD_Addr_2 MTS_OUTPUT_GAIN_Addr_2+6 // len 3 369 #define BTSC_SAP_ON_DETECTION_DEBOUNCE_THRESHOLD_Addr_2 BTSC_PILOT_DEBOUNCE_THRESHOLD_Addr_2+3 // len 1 370 */ 371 372 /************************************************ 373 * Below is MailBox config 374 *************************************************/ 375 376 /************************************************ 377 * MCU to DSP mailbox 378 ************************************************/ 379 /* SIF */ 380 #define M2S_MBOX_SIF_CMD_STANDARD MB_2DC0 381 #define M2S_MBOX_SIF_CMD_PFIRBANDWIDTH MB_2DC2 382 #define M2S_MBOX_SIF_CMD_MODE1 MB_2DC4 383 #define M2S_MBOX_SIF_CMD_MODE2 MB_2DC6 384 385 /* ATV Encoder */ 386 #define M2S_MBOX_ATVEnc_MODE_CTRL MB_2DC0 387 388 /* SPDIF */ 389 #define M2S_MBOX_SPDIF_SETTING MB_2D8E 390 #define M2S_MBOX_HDMI_SETTING MB_2D8E 391 #define MBOX_SPDIF_SETTING_BIT_MUTE MBOX_BIT0 392 #define MBOX_SPDIF_SETTING_BIT_NPCMSEL MBOX_BIT1 393 #define MBOX_SPDIF_SETTING_R2_NPCM_SELBIT MBOX_BIT2 394 #define MBOX_SPDIF_SETTING_DVB2_NPCM_SELBIT MBOX_BIT3 395 #define MBOX_SPDIF_SETTING_MINUS_11DB_BIT MBOX_BIT5 396 #define MBOX_HDMI_SETTING_BIT_NPCMSEL MBOX_BIT13 397 #define MBOX_HDMI_SETTING_DDP_BYPASS_BIT MBOX_BIT14 398 #define MBOX_HDMI_SETTING_BIT_MUTE MBOX_BIT15 399 400 #define M2S_MBOX_DOLBY_LOUDNESS_INFO MB_2D98 401 #define MBOX_DOLBY_LOUDNESS_ENABLE_BIT MBOX_BIT15 402 #define MBOX_DOLBY_LOUDNESS_ATSC_MODE MBOX_BIT14 403 #define MBOX_DOLBY_LOUDNESS_OTHER_MODE MBOX_BIT13 404 405 /* Sound effect */ 406 #define M2S_MBOX_AUOUT0_VOL MB_2D00 407 #define M2S_MBOX_AUOUT1_VOL MB_2D02 408 #define M2S_MBOX_AUOUT2_VOL MB_2D04 409 #define M2S_MBOX_AUOUT3_VOL MB_2D06 410 #define M2S_MBOX_I2S_VOL MB_2D08 411 #define M2S_MBOX_SPDIF_VOL MB_2D0A 412 #define M2S_MBOX_SRC_VOL MB_2D0C 413 #define M2S_MBOX_HDMI_VOL MB_2D0E //STB only 414 #define M2S_MBOX_I2S2_VOL MB_2D0E 415 #define M2S_MBOX_PRESCALE MB_2D10 416 417 #define M2S_MBOX_EQ1_GAIN MB_2D14 //[15:8] 418 #define M2S_MBOX_BASS_CTRL MB_2D14 //[7:0] 419 #define M2S_MBOX_EQ2_GAIN MB_2D16 //[15:8] 420 #define M2S_MBOX_TREBLE_CTRL MB_2D16 //[7:0] 421 #define M2S_MBOX_EQ3_GAIN MB_2D18 //[15:8] 422 #define M2S_MBOX_SUPBASS_CTRL MB_2D18 //[7:0] 423 #define M2S_MBOX_EQ4_GAIN MB_2D1A //[15:8] 424 #define M2S_MBOX_EQ5_GAIN MB_2D1C //[15:8] 425 #define M2S_MBOX_BAL_CTRL MB_2D1E 426 427 #define M2S_MBOX_SNDEFF_EN MB_2D20 428 #define M2S_MBOX_STEREO_EN_BIT MBOX_BIT15 429 #define M2S_MBOX_DRC_EN_BIT MBOX_BIT13 430 #define M2S_MBOX_AVC_EN_BIT MBOX_BIT12 431 #define M2S_MBOX_TONE_EN_BIT MBOX_BIT11 432 #define M2S_MBOX_SPATIAL_EN_BIT MBOX_BIT10 433 #define M2S_MBOX_VOLBAL_EN_BIT MBOX_BIT9 434 #define M2S_MBOX_GEQ_EN_BIT MBOX_BIT7 435 #define M2S_MBOX_EASE_EN_BIT MBOX_BIT6 436 #define M2S_MBOX_BASSBOOST_EN_BIT MBOX_BIT5 437 #define M2S_MBOX_ECHO_EN_BIT MBOX_BIT4 438 #define M2S_MBOX_DC_REMOVE_EN_BIT MBOX_BIT3 439 #define M2S_MBOX_HPF_EN_BIT MBOX_BIT2 440 #define M2S_MBOX_COEFFUPDATE_EN_BIT MBOX_BIT1 441 #define M2S_MBOX_PEQ_EN_BIT MBOX_BIT0 442 443 #define M2S_MBOX_VOLUME_EN MB_2D22 444 #define M2S_MBOX_VOL_DAC0_EN_BIT MBOX_BIT0 445 #define M2S_MBOX_VOL_DAC1_EN_BIT MBOX_BIT1 446 #define M2S_MBOX_VOL_DAC2_EN_BIT MBOX_BIT2 447 #define M2S_MBOX_VOL_DAC3_EN_BIT MBOX_BIT3 448 #define M2S_MBOX_VOL_I2S0_EN_BIT MBOX_BIT4 449 #define M2S_MBOX_VOL_I2S1_EN_BIT MBOX_BIT5 450 #define M2S_MBOX_VOL_I2S2_EN_BIT MBOX_BIT6 451 #define M2S_MBOX_VOL_I2S3_EN_BIT MBOX_BIT7 452 #define M2S_MBOX_VOL_SPDIF_EN_BIT MBOX_BIT8 453 #define M2S_MBOX_VOL_SRC_EN_BIT MBOX_BIT9 454 455 #define M2S_MBOX_AVC_CTRL MB_2D24 456 #define M2S_MBOX_SURR_CTRL MB_2D26 457 #define M2S_MBOX_SINE_GEN MB_2D28 458 #define M2S_MBOX_SINE_GEN_CTRL_MASK 0x7F 459 #define M2S_MBOX_SINE_GEN_EN_BIT MBOX_BIT7 460 461 #define M2S_MBOX_BALANCE_EN MB_2D2A 462 #define M2S_MBOX_BAL_DAC0_EN_BIT MBOX_BIT0 463 #define M2S_MBOX_BAL_DAC1_EN_BIT MBOX_BIT1 464 #define M2S_MBOX_BAL_DAC2_EN_BIT MBOX_BIT2 465 #define M2S_MBOX_BAL_DAC3_EN_BIT MBOX_BIT3 466 #define M2S_MBOX_BAL_I2S0_EN_BIT MBOX_BIT4 467 #define M2S_MBOX_BAL_I2S1_EN_BIT MBOX_BIT5 468 #define M2S_MBOX_BAL_I2S2_EN_BIT MBOX_BIT6 469 #define M2S_MBOX_BAL_I2S3_EN_BIT MBOX_BIT7 470 #define M2S_MBOX_BAL_SPDIF_EN_BIT MBOX_BIT8 471 #define M2S_MBOX_BAL_SRC_EN_BIT MBOX_BIT9 472 #define M2S_MBOX_BAL_HDMI_EN_BIT MBOX_BIT10 473 474 #define M2S_MBOX_SOUND_MODE_SEL MB_2D30 //[1:0] : LR / LL / RR 475 #define M2S_MBOX_POWER_DOWN MB_2D30 //[8:9] 476 #define M2S_MBOX_NR_CTRL MB_2D32 477 478 #define M2S_MBOX_ADVSND_EN MB_2D40 479 #define M2S_MBOX_ADVSND_SUMMARY_EN_BIT MBOX_BIT15 480 481 #define M2S_MBOX_KTV_CTRL MB_2D46 482 #define M2S_MBOX_KTV_EN_BIT MBOX_BIT15 483 484 #define M2S_MBOX_INPUT_MUX_SEL1 MB_2D50 485 #define M2S_MBOX_INPUT_MUX_SEL2 MB_2D52 486 #define M2S_MBOX_INPUT_MUX_SEL3 MB_2D54 487 488 #define M2S_MBOX_KTV8_VOL MB_2D5A 489 #define M2S_MBOX_KTV5_VOL MB_2D5C 490 #define M2S_MBOX_KTV6_VOL MB_2D5E 491 #define M2S_MBOX_CH7_VOL MB_2D58 492 493 #define M2S_MBOX_AD_CONTROL MB_2DD8 494 #define M2S_MBOX_MIX_MODE_BSTART MBOX_BITS_SHIFT-11 495 #define M2S_MBOX_MIX_MODE_BMASK 0x7 496 497 /* M2S_MBOX_MIX_MODE */ 498 #define GPA_MIX_MODE_IS_FORWARD 0 499 #define GPA_MIX_MODE_IS_BACKWARD 1 500 #define GPA_MIX_MODE_IS_NULL 2 ! 2 & 3: NULL_Mixer_Mode 501 502 #define M2S_MBOX_DBG_CMD1 MB_2DDC 503 #define MBOX_DBGCMD_SET_ADDR 0x0200 504 #define MBOX_DBGCMD_WRITE_DM 0x0300 505 #define MBOX_DBGCMD_WRITE_PM 0x0400 506 #define MBOX_DBGCMD_READ_DM 0x0500 507 #define MBOX_DBGCMD_READ_PM 0x0600 508 #define MBOX_DBGCMD_READ_PMASK 0x0700 509 #define MBOX_DBGCMD_READ_IMASK 0x0800 510 511 #define MBOX_DBGCMD_READ_MAIN_VER 0x9000 512 #define MBOX_DBGCMD_READ_ALG1_VER 0x9100 513 #define MBOX_DBGCMD_READ_ALG2_VER 0x9200 514 515 //#define MBOX_DBGCMD_MIP_INT 0xE000 516 //#define MBOX_DBGCMD_ENC_INT 0xE100 517 //#define MBOX_DBGCMD_FILE_PTS_INT 0xEA00 518 519 #define MBOX_DBGCMD_RELOAD_SIF_BEG 0xF000 520 #define MBOX_DBGCMD_RELOAD_SIF_END 0xF100 521 #define MBOX_DBGCMD_WAIT_MCU_START 0xF300 522 #define MBOX_DBGCMD_RELOAD_ADVSND_BEG 0xF400 523 #define MBOX_DBGCMD_RELOAD_ADVSND_END 0xF500 524 525 #define M2S_MBOX_DBG_CMD2 MB_2DDE 526 527 /* MISC */ 528 #define M2S_MBOX_SW_DMA_READER_DDR_WtPtr MB_2D34 529 #define M2S_MBOX_SW_DMA_READER_DDR_Ctrl MB_2D36 530 #define M2S_MBOX_SW_DMA_READER_DDR_SynthFreq MB_2D56 531 #define M2S_MBOX_SW_DMA_READER_DDR_SynthFreq_L 0 //Reserved 532 533 #define M2S_MBOX_CAPTURE_CTRL MB_2D4A //[7:0] PCM_capture1 [15:8] PCM_capture2 534 //#define M2S_MBOX_CAPTURE3_CTRL //MB_2D4C //[7:0] PCM_capture3 //RESERVED 535 #define M2S_MBOX_GET_CH5 1 536 #define M2S_MBOX_GET_CH6 2 537 #define M2S_MBOX_GET_CH7 3 538 #define M2S_MBOX_GET_CH8 4 539 #define M2S_MBOX_GET_ADC1 5 540 #define M2S_MBOX_GET_ADC2 6 541 #define M2S_MBOX_GET_Raw_Delay_SE 7 542 #define M2S_MBOX_GET_MIXER 8 543 #define M2S_MBOX_GET_DEBUG 128 544 545 #define M2S_MBOX_PCM_CAPTURE_DDR_RdPtr MB_2DD4 546 #define M2S_MBOX_PCM_CAPTURE_DDR_Size MB_2DD6 547 548 #define M2S_MBOX_PCM_CAPTURE2_DDR_RdPtr MB_2D38 549 #define M2S_MBOX_PCM_CAPTURE2_DDR_Size MB_2D3A 550 551 //#define M2S_MBOX_PCM_CAPTURE3_DDR_RdPtr //MB_2D94 //RESERVED 552 //#define M2S_MBOX_PCM_CAPTURE3_DDR_Size //MB_2D96 //RESERVED 553 554 //************************************************************ 555 // MS12 DDPE control 556 //************************************************************ 557 //#define M2S_MBOX_DDP_ENC_SELECT MB_2DC0 558 #define MBOX_DDP_ENC_SELECT ddpe_enc_select 559 #define ENC_DDP_MODE_BIT 0 // 0:DD, 1:DDP 560 #define ENC_DDP_ENCODE_FLAG_BIT 1 // 0:Not Encode, 1:Encode. 561 #define ENC_LISTEN_MODE_BIT 4 // 0: 562 #define ENC_FORCE_MODE_BIT 8 563 564 #define D2S_MBOX_DDP_PCM_WRPTR DECR2M_2_DSP_MAILBOXD //³æ¦ì: miu line, range: 0 ~ 0x1200 (SEDSP_DDPENC_MCHOUT_DRAM_SIZE) 565 //#define D2S_MBOX_DDP_PCM_WRPTR ddpe_pcm_dram_wrPtr //³æ¦ì: miu line, range: 0 ~ 0x1200 (SEDSP_DDPENC_MCHOUT_DRAM_SIZE) 566 #define S2D_MBOX_DDP_PCM_RDPTR ddpe_pcm_dram_rdPtr //³æ¦ì: miu line, range: 0 ~ 0x1200 (SEDSP_DDPENC_MCHOUT_DRAM_SIZE) 567 568 569 #define S2D_MBOX_DDP_RAW_HDMI_WRPTR ddpe_hdmi_npcmWrAddr //³æ¦ì: miu line, range: 0 ~ 0xD800 (HDMI_NONPCM_DRAM_SIZE) 570 #define S2D_MBOX_DDP_RAW_SPDIF_WRPTR ddpe_spdif_npcmWrAddr //³æ¦ì: miu line, range: 0 ~ 0x3600 (SPDIF_NONPCM_DRAM_SIZE) 571 572 #define M2S_MBOX_DDPE_ENCODE_CTRL MB_2DC2 573 #define MBOX_DSP_DDPE_DISABLE_BIT MBOX_BIT0 574 575 #define M2S_MBOX_MCU_HDMI_NONPCM_CTRL MB_2DC4 576 #define HDMI_MCU_FORCE_CTRL_BIT MBOX_BIT0 577 #define HDMI_NONPCM_FROM_SER2 MBOX_HDMI_NONPCM_FROM_ASND_R2_BIT //MBOX_BIT4 578 #define HDMI_NONPCM_FROM_SEDSP MBOX_HDMI_NONPCM_FROM_ASND_DSP_BIT //MBOX_BIT5 579 580 //************************************************************ 581 // DSP clock control 582 //************************************************************ 583 #define M2S_MBOX_DSP_TIMER_CONSTANT MB_2DC0 584 585 /************************************************ 586 * DSP to MCU mailbox 587 ************************************************/ 588 #define S2M_MBOX_ES_MEMCNT MB_2D70 589 #define S2M_MBOX_PCM_MEMCNT MB_2D72 590 #define S2M_MBOX_MM_BROWSE_TIME MB_2D74 591 #define S2M_MBOX_MM_PTS_IN_SEC MB_2D76 592 #define S2M_MBOX_MM_PTS_IN_MSEC MB_2D78 593 #define S2M_MBOX_MM_PTS_HI MB_2D7A 594 #define S2M_MBOX_MM_PTS_ME MB_2D7C 595 #define S2M_MBOX_MM_PTS_LO MB_2D7E 596 597 #define S2M_MBOX_DEC_STATUS MB_2DFA 598 599 #define S2M_MBOX_SIF_DETECTION_RESULT MB_2DE0 600 #define S2M_MBOX_SIF_STATUS_INFO MB_2DE2 601 #define S2M_MBOX_SIF_STATUS_MODE1 MB_2DE4 602 #define S2M_MBOX_SIF_STATUS_MODE2 MB_2DE6 603 #define S2M_MBOX_SIF_STATUS_NICAM_INFO MB_2DE8 604 #define S2M_MBOX_SIF_STATUS_NICAM_PARITY_ERR_CNT MB_2DEA 605 606 #define S2M_MBOX_NR_STATUS MB_2DEE 607 #define S2M_MBOX_BSND_STATUS MB_2DEE 608 #define MBOX_NR_WORKING_NOW MBOX_BIT0 // 1: NR working now , 0 NR not working 609 #define MBOX_TONE_FUNC_SELECT MBOX_BIT1 // 0: EQ_Bass_Treble , 1: Bass_Treble_old 610 #define MBOX_PEQ_FUNC_SELECT MBOX_BIT2 // 0: PEQ: single precision , 1: double precision 611 612 #define S2M_MBOX_MAIN_OVERFLOW_CNT MB_2DF2 //[15:8], full cnt of input SRAM buff2 613 #define S2M_MBOX_MAIN_UNDERFLOW_CNT MB_2DF2 //[ 7:0], empty cnt of output SRAM buff1 614 615 #define S2M_MBOX_ISR_CNTR MB_2DF6 //[15:8] 616 #define S2M_MBOX_INTR_CMDTYPE MB_2DF6 //[ 7:0] 617 #define SE_DSP_INTR_CMD_MMES_NEED_DATA 0x0300 618 #define SE_DSP_INTR_CMD_REPORT_PTS 0x0500 619 #define SE_DSP_INTR_CMD_MMUNI_NEED_DATA 0x0600 620 #define SE_DSP_INTR_CMD_VOIP 0x0900 621 #define DSP_INTR_CMD_PCM_UPLOAD 0x3300 622 #define DSP_INTR_CMD_PCM_DOWNLOAD 0xC000 623 624 #define S2M_MBOX_WHILE1_CNTR MB_2DF8 //[ 7:0] Always in Low Byte 625 #define S2M_MBOX_TIMER_CNTR MB_2DF8 //[15:8] Always in High Byte 626 627 #define S2M_MBOX_DBG_RESULT1 MB_2DFC // 628 #define S2M_MBOX_DSP_INIT_ACK 0x00E3 629 630 #define S2M_MBOX_DBG_RESULT2 MB_2DFE // 631 #define MBOX_DSP_RELOAD_ACK1 0x0033 632 #define MBOX_DSP_RELOAD_ACK2 0x0077 633 634 #define S2M_MBOX_SW_DMA_READER_DDR_Level MB_2DE0 635 636 #define S2M_MBOX_PCM_CAPTURE_DDR_WrPtr MB_2DF0 637 #define S2M_MBOX_PCM_CAPTURE2_DDR_WrPtr MB_2DF4 638 //#define S2M_MBOX_PCM_CAPTURE3_DDR_WrPtr //MB_2D7E //RESERVED 639 640 #ifdef _COMPILE_DSP_ 641 /************************************************ 642 * DSP ddr address mapping 643 *************************************************/ 644 /* DRAM Config */ 645 .const DSP2_TO_COMMON_DRAM_OFFSET = ASND_DSP_DDR_SIZE / BYTES_IN_MIU_LINE; 646 647 /* SPDIF delay (GP C Bffer) */ 648 .const DSP2_SPDIF_DLY_DRAM_BASE = (OFFSET_SPDIF_DLY_DRAM_BASE / BYTES_IN_MIU_LINE); 649 .const DSP2_SPDIF_DLY_DRAM_SIZE = ((SPDIF_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1); 650 651 /* DSP SRAM DM/PM */ 652 653 654 /* sound system */ 655 .const DSP2_DMA_START_DRAM_BASE1 = OFFSET_SE_MAIN_IN_DRAM_ADDR / BYTES_IN_MIU_LINE; 656 .const DSP2_DMA_START_DRAM_SIZE1 = SE_MAIN_IN_DRAM_SIZE / BYTES_IN_MIU_LINE; 657 .const DSP2_DMA_START_DRAM_BASE2 = OFFSET_SE_MAIN_OUT_DRAM_ADDR / BYTES_IN_MIU_LINE; 658 .const DSP2_DMA_START_DRAM_SIZE2 = SE_MAIN_OUT_DRAM_SIZE / BYTES_IN_MIU_LINE; 659 660 /* DSP DM Prefetch */ 661 #define DSP2_DM_PREFETCH_DRAM_BASE 0x00A800 662 #define DSP2_DM_PREFETCH_DRAM_SIZE 0x3000 // 192KB 663 664 /* standalone DDCO PCM Buffer */ 665 #define DSP2_DDE_PCM_DRAM_BASE DSP2_DM_PREFETCH_DRAM_BASE+0x400 // AC3 Encode base address 666 #define DSP2_DDE_PCM_DRAM_SIZE 0xBFF // 48KB 667 668 /* HE-AAC Metadata Buffer on DEC */ 669 #define DSP2_HEAAC_METADATA_DRAM_BASE 0x00D800 670 #define DSP2_HEAAC_METADATA_DRAM_SIZE 0x00200 // 8KB 671 672 /* Surround */ 673 #define SUR_DRAM_BASEADDR 0x00DA00 // Line Address 674 #define SUR_DRAM_ENDADDR (SUR_DRAM_BASEADDR + 0x00800) //0x00800 // 32KB 675 676 /* KTV */ 677 #define SUR_DRAM_KTV_BASEADDR 0x00E200 // Line address, Only in KTV mode, MS surround -> echo 678 #define SUR_DARM_KTV_ENDADDR (SUR_DRAM_KTV_BASEADDR + 0x002000) //0x002000 // Line address, Overlay with DM prefetch 679 680 /* SPDIF Non-PCM */ 681 .const DSP2_SPDIF_DRAM_BASE = OFFSET_SPDIF_NONPCM_DRAM_BASE / BYTES_IN_MIU_LINE; 682 .const DSP2_SPDIF_DRAM_SIZE = (SPDIF_NONPCM_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1; 683 684 /* HDMI Non-PCM */ 685 .const DSP2_HDMI_DRAM_BASE = OFFSET_HDMI_NONPCM_DRAM_BASE / BYTES_IN_MIU_LINE; 686 .const DSP2_HDMI_DRAM_SIZE = (HDMI_NONPCM_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1; 687 688 /* ES1 */ 689 /* ES2 */ 690 /* ES3 */ 691 /* ES4 */ 692 693 /* Head phone delay */ 694 #define DSP2_HEAD_PHONE_DLY_DRAM_BASE 0x029000 695 #define DSP2_HEAD_PHONE_DLY_DRAM_SIZE 0x17FF 696 697 /* HDMI delay (GP C Bffer) */ 698 .const HDMI_DLY_DRAM_BASE = SE_HDMI_DLY_DRAM_BASE / BYTES_IN_MIU_LINE; 699 .const HDMI_DLY_DRAM_SIZE = (SE_HDMI_DLY_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1; 700 701 702 /* COMMON DRAM */ 703 704 /* PCM 1 / 2 */ 705 .const DSP2_PCM1_DRAM_BASE = DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_PCM1_DRAM_ADDR / BYTES_IN_MIU_LINE); 706 .const DSP2_PCM1_DRAM_SIZE = (PCM1_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1; 707 708 .const DSP2_PCM2_DRAM_BASE = DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_PCM2_DRAM_ADDR / BYTES_IN_MIU_LINE); 709 .const DSP2_PCM2_DRAM_SIZE = (PCM2_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1; 710 711 /* Software DMA */ 712 .const DSP2_SW_DMA_READER_DRAM_BASE = DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_SW_DMA_READER_DRAM_BASE / BYTES_IN_MIU_LINE); 713 .const DSP2_SW_DMA_READER_DRAM_SIZE = (SW_DMA_READER_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1; 714 715 /* PCM capture buffer */ 716 .const DSP2_PCM_CAPTURE_BUFFER_DRAM_BASE = DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_PCM_CAPTURE1_BUFFER_DRAM_BASE / BYTES_IN_MIU_LINE); 717 .const DSP2_PCM_CAPTURE2_BUFFER_DRAM_BASE = DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_PCM_CAPTURE2_BUFFER_DRAM_BASE / BYTES_IN_MIU_LINE); 718 .const DSP2_PCM_CAPTURE3_BUFFER_DRAM_BASE = DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_PCM_CAPTURE3_BUFFER_DRAM_BASE / BYTES_IN_MIU_LINE); 719 .const DSP2_PCM_CAPTURE_BUFFER_DRAM_SIZE = (PCM_CAPTURE_BUFFER_DRAM_SIZE/ BYTES_IN_MIU_LINE); 720 #define DSP2_PCM_CAPTURE_COPY_WORDSIZE 32 721 #define DSP2_PCM_CAPTURE_COPY_LINESIZE 4 722 723 /* DDPE */ 724 .const DSP2_DDPE_PCM_DRAM_BASE = DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_SEDSP_DDPENC_MCHOUT_DRAM_ADDR / BYTES_IN_MIU_LINE); 725 .const DSP2_DDPE_PCM_DRAM_SIZE = (SEDSP_DDPENC_MCHOUT_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1; 726 .const DSP2_DDPE_META_DRAM_BASE = DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_DDPENC_METADATA_DRAM_ADDR / BYTES_IN_MIU_LINE); 727 .const DSP2_DDPE_META_DRAM_SIZE = (DDPENC_METADATA_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1; 728 .const DSP2_DDPE_RAW_HDMI_DRAM_BASE = (OFFSET_HDMI_NONPCM_DRAM_BASE / BYTES_IN_MIU_LINE); 729 .const DSP2_DDPE_RAW_HDMI_DRAM_SIZE = (HDMI_NONPCM_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1; 730 .const DSP2_DDE_RAW_SPDIF_DRAM_BASE = (OFFSET_SPDIF_NONPCM_DRAM_BASE / BYTES_IN_MIU_LINE); 731 .const DSP2_DDE_RAW_SPDIF_DRAM_SIZE = (SPDIF_NONPCM_DRAM_SIZE/ BYTES_IN_MIU_LINE) - 1; 732 733 /************************************************ 734 * DSP TSCALE & TCOUNT setting 735 ************************************************/ 736 #define DSP_SYSTEM_FREQUENCY 368 737 #define TSCALE_CONSTANT 0xF9 738 #define DSP_TIME_CONSTANT (DSP_SYSTEM_FREQUENCY/2 -1) 739 #define DSP_TIMER_SETTING DSP_TIME_CONSTANT 740 741 /************************************************ 742 * Below is DMA config 743 *************************************************/ 744 #define DMAITF_DSPCMD_ALIGNMENT_BIT 7 // 1/0 : msb / lsb alignment 745 #define DMAITF_DSPCMD_BYTESWAP_BIT 6 // set 1 to byte swap 746 #define DMAITF_DSPCMD_READY_BIT 5 // set 1 to trigger, will be 0 when dma is finished 747 #define DMAITF_DSPCMD_CLRCNTR_BIT 4 // set 1 to clear 748 #define DMAITF_DSPCMD_PRIORITY_BIT 3 // 1/0 : high / low 749 #define DMAITF_DSPCMD_24BITS_BIT 2 // 1/0 : 24bits / 16bits 750 751 #define DMAITF_DSPCMD_ALIGNMENT_MASK 0x80 752 #define DMAITF_DSPCMD_BYTESWAP_MASK 0x40 753 #define DMAITF_DSPCMD_READY_MASK 0x20 754 #define DMAITF_DSPCMD_CLRCNTR_MASK 0x10 755 #define DMAITF_DSPCMD_PRIORITY_MASK 0x08 756 #define DMAITF_DSPCMD_24BITS_MASK 0x04 757 #define DMAITF_DSPCMD_BURST_6 0x03 758 #define DMAITF_DSPCMD_BURST_3 0x02 759 #define DMAITF_DSPCMD_BURST_2 0x01 760 #define DMAITF_DSPCMD_BURST_1 0x00 761 762 #if (MIU_128 == 1) 763 /* 1 MIU Line = 128bit (16 bytes) */ 764 #define DMAITF_DSPWORDS_IN_1_LINE 8 765 #define DMAITF_DSPWORDS_IN_1LINE_LOG2 3 766 #define DMAITF_DSPWORDS_IN_3LINE_LOG2 4 767 #define DMAITF_WR_BIT 16 768 #define DMAITF_DM_BIT 15 769 #define DMAITF_BYTES_IN_1MIU_LINE BYTES_IN_MIU_LINE 770 771 #define DMAITF_RD_PM_MASK 0x000000 772 #define DMAITF_WR_PM_MASK 0x010000 773 #define DMAITF_RD_DM_MASK 0x008000 774 #define DMAITF_WR_DM_MASK 0x018000 775 776 #define DMAITF_16BITS_B1_DMA_CMD 0xA8 // 16 Bits Burst 1, high alignment 777 #define DMAITF_16BITS_B2_DMA_CMD 0xA8 //no Burst 2 cmd, use B1 instead 778 #define DMAITF_16BITS_B1_SWAP_DMA_CMD 0xE8 // 16 Bits Burst 1, high alignment 779 #define DMAITF_16BITS_B2_SWAP_DMA_CMD 0xE8 //no Burst 2 cmd, use B1 instead 780 781 #define DMAITF_24BITS_B3_DMA_CMD 0x2E // 24 Bits Burst 3 782 #define DMAITF_24BITS_B6_DMA_CMD 0x2E //no Burst 6 cmd, use B3 instead 783 784 #define DMAITF_16BITS_LowAlign_B1_DMA_CMD 0x28 //16 Bits Burst 1, low alignment 785 #define DMAITF_16BITS_LowAlign_B1_SWAP_DMA_CMD 0x68 //16 Bits Burst 1, low alignment 786 #else 787 /* 1 MIU Line = 64bit (8 bytes) */ 788 #define DMAITF_DSPWORDS_IN_1_LINE 4 789 #define DMAITF_DSPWORDS_IN_1LINE_LOG2 2 790 #define DMAITF_DSPWORDS_IN_3LINE_LOG2 3 791 #define DMAITF_WR_BIT 15 792 #define DMAITF_DM_BIT 14 793 #define DMAITF_BYTES_IN_1MIU_LINE BYTES_IN_MIU_LINE 794 795 #define DMAITF_RD_PM_MASK 0x000000 796 #define DMAITF_WR_PM_MASK 0x008000 797 #define DMAITF_RD_DM_MASK 0x004000 798 #define DMAITF_WR_DM_MASK 0x00C000 799 800 #define DMAITF_16BITS_B1_DMA_CMD 0xA8 // 16 Bits Burst 1, high alignment 801 #define DMAITF_16BITS_B2_DMA_CMD 0xA9 802 #define DMAITF_16BITS_B1_SWAP_DMA_CMD 0xE8 // 16 Bits Burst 1, high alignment 803 #define DMAITF_16BITS_B2_SWAP_DMA_CMD 0xE9 804 805 #define DMAITF_24BITS_B3_DMA_CMD 0x2E // 24 Bits Burst 3 806 #define DMAITF_24BITS_B6_DMA_CMD 0x2F // 24 Bits Burst 6 807 808 #define DMAITF_16BITS_LowAlign_B1_DMA_CMD 0x28 //16 Bits Burst 1, low alignment 809 #define DMAITF_16BITS_LowAlign_B1_SWAP_DMA_CMD 0x68 //16 Bits Burst 1, low alignment 810 #endif 811 812 /* DMA Mapping */ 813 #define General_DSP_IDMA_CMD_Number 15 // just info this chip nubmer of DSP_IDMA can support, (no any purpose) need sync with HW spec 814 815 #define SNDISR1_DMA_CTRL DSPDMA7_DMA_CTRL 816 #define SNDISR2_DMA_CTRL DSPDMA2_DMA_CTRL 817 #define SPDIF_DMA_CTRL DSPDMA6_DMA_CTRL // SPDIF npcm 818 #define HDMI_DMA_CTRL DSPDMA6_DMA_CTRL // HDMI npcm 819 #define PCM_CAPTURE_DMA_CTRL DSPDMA1_DMA_CTRL 820 #define PCM_CAPTURE2_DMA_CTRL DSPDMA8_DMA_CTRL 821 #define PCM_CAPTURE3_DMA_CTRL DSPDMA9_DMA_CTRL 822 #define SW_DMARDR_DMA_CTRL DSPDMA7_DMA_CTRL 823 #define HP_DLY_DMA_CTRL DSPDMA2_DMA_CTRL 824 #define R2_DEC_PCM1R_DMA_CTRL PCM1R_DMA_CTRL 825 #define DDE_ISR_PCM_DMA_CTRL DSPDMA1_DMA_CTRL 826 #define SPDIF_DLY_IN_DMA_CTRL DSPDMA2_DMA_CTRL 827 #define HDMI_DLY_IN_DMA_CTRL DSPDMA2_DMA_CTRL 828 #define SPDIF_DLY_OUT_DMA_CTRL DSPDMA6_DMA_CTRL 829 #define HDMI_DLY_OUT_DMA_CTRL DSPDMA6_DMA_CTRL 830 831 #define SNDBG_DMA_CTRL DSPDMA3_DMA_CTRL // Background sound effect 832 #define ADEC_DMA1_CTRL DSPDMA3_DMA_CTRL 833 #define ADEC_DMA2_CTRL DSPDMA4_DMA_CTRL 834 #define ADEC_DMA3_CTRL DSPDMA3_DMA_CTRL 835 #define ADEC_DMA4_CTRL DSPDMA4_DMA_CTRL 836 #define ADEC_DMA5_CTRL DSPDMA5_DMA_CTRL 837 838 /************************************************ 839 * Below is DSP FIFO/DDR unit Setting 840 *************************************************/ 841 /* sound effect buffer / share buffer setting */ 842 .const SE_R2_FRAME_SIZE = 256; //256 samples for R2_SE 843 .const SE_PROCESS_FRAME_SMP_UNIT = 128; //128 samples per frame 844 845 .const SE_PROCESS_FETCH_FRAME_LINE_SIZE = SE_PROCESS_FRAME_SMP_UNIT*SE_PROCESS_FETCH_CHANNELS*3/BYTES_IN_MIU_LINE; 846 .const SE_PROCESS_STORE_FRAME_LINE_SIZE = SE_PROCESS_FRAME_SMP_UNIT*SE_PROCESS_STORE_CHANNELS*3/BYTES_IN_MIU_LINE; 847 848 .const SE_PROCESS_BUFFER_MAIN = 0x0; //share buffer in dm 849 .const SE_PROCESS_BUFFER_MAIN_RAW1_LR = SE_PROCESS_BUFFER_MAIN + SE_PROCESS_FRAME_SMP_UNIT*0; 850 .const SE_PROCESS_BUFFER_MAIN_RAW2_LR = SE_PROCESS_BUFFER_MAIN + SE_PROCESS_FRAME_SMP_UNIT*2; 851 .const SE_PROCESS_BUFFER_MAIN_SE_LR = SE_PROCESS_BUFFER_MAIN + SE_PROCESS_FRAME_SMP_UNIT*4; 852 .const SE_PROCESS_BUFFER_MAIN_SE_LmRm = SE_PROCESS_BUFFER_MAIN + SE_PROCESS_FRAME_SMP_UNIT*6; 853 .const SURR_DLY_BUFFER = SE_PROCESS_BUFFER_MAIN + SE_PROCESS_FRAME_SMP_UNIT*8; 854 .const NR_PARAMETER_BUFFER = SE_PROCESS_BUFFER_MAIN + SE_PROCESS_FRAME_SMP_UNIT*10; 855 .const SE_PROCESS_BUFFER_MAIN_TMP = SE_PROCESS_BUFFER_MAIN + SE_PROCESS_FRAME_SMP_UNIT*12; //0x600 856 857 #define DSP2DmAddr_system_shareBuff 0x0 //SE_PROCESS_BUFFER_MAIN 858 #define DSP2DmAddr_system_shareBuff_size (0x600) //(SE_PROCESS_BUFFER_MAIN_TMP - SE_PROCESS_BUFFER_MAIN) 859 #define DSP2DmAddr_advSnd_shareBuff_base SE_PROCESS_BUFFER_MAIN_TMP 860 #define DSP2DmAddr_advSnd_shareBuff_size (0x1500) // min size: (SE_PROCESS_FRAME_SMP_UNIT*SE_PROCESS_FETCH_CHANNELS) for system frame base SE 861 862 .const SndEff_Array_TMP1 = SE_PROCESS_BUFFER_MAIN_TMP; 863 .const SndEff_Array_TMP2 = SndEff_Array_TMP1 + SE_PROCESS_FRAME_SMP_UNIT*2; 864 .const SndEff_Array_TMP3 = SndEff_Array_TMP2 + SE_PROCESS_FRAME_SMP_UNIT*2; 865 .const SndEff_Array_TMP4 = SndEff_Array_TMP3 + SE_PROCESS_FRAME_SMP_UNIT*2; 866 867 .const Apply_NR_Status_BUFFER = NR_PARAMETER_BUFFER; 868 .const Apply_NR_Gain_BUFFER = Apply_NR_Status_BUFFER + SE_PROCESS_FRAME_SMP_UNIT; 869 870 /* General delay buffer template */ 871 .const HP_DLY_MAX_DELAY = 512; //unit : ms 872 .const DELAY_MAX_DELAY = 512; 873 .const DELAY_FIFO_SIZE = 128; 874 .const DELAY_DMA_WORDSIZE = 32; 875 .const DELAY_DMA_LINESIZE = DELAY_DMA_WORDSIZE*3/BYTES_IN_MIU_LINE; 876 877 /* Dly_status */ 878 .const DELAY_INPUT_STOP = 0; 879 .const DELAY_OUTPUT_STOP = 1; 880 .const DELAY_DLYIN_DMA_ASSERT = 2; 881 .const DELAY_DLYOUT_DMA_ASSERT = 3; 882 883 /* Mstar Surround delay buffer */ 884 .const SUR_FIFO_UNIT = SE_PROCESS_FRAME_SMP_UNIT*2; 885 .const SUR_DRAM_BURSRT = (SUR_FIFO_UNIT*2)/BYTES_IN_MIU_LINE; 886 887 /* sound effect buffer / share buffer setting */ 888 .const SE_PROCESS_FIFO_SIZE_UNIT = 64; //delay fifo size per channel 889 .const SE_PROCESS_DMA_WORD_SIZE_UNIT = 16; //DMA_WORD_SIZE per channel 890 891 /* ISR PCM samples -> DDR unit setting */ 892 .const SE_BUFF2_FIFO_SIZE = (SE_PROCESS_FIFO_SIZE_UNIT * SE_PROCESS_FETCH_CHANNELS); 893 .const SE_BUFF2_DMA_WORD_SIZE = (SE_PROCESS_DMA_WORD_SIZE_UNIT * SE_PROCESS_FETCH_CHANNELS); // (DMA_WORD_SIZE per channel) * channel number 0x80; 894 .const SE_BUFF2_DMA_24BIT_LINE_SIZE = SE_BUFF2_DMA_WORD_SIZE*3/BYTES_IN_MIU_LINE; 895 .const SE_BUFF2_DMA_16BIT_LINE_SIZE = SE_BUFF2_DMA_WORD_SIZE*2/BYTES_IN_MIU_LINE; 896 897 /* DDR2 --> output ISR PCM samples */ 898 .const SE_BUFF1_FIFO_SIZE = (SE_PROCESS_FIFO_SIZE_UNIT * SE_PROCESS_STORE_CHANNELS); 899 .const SE_BUFF1_DMA_WORD_SIZE = (SE_PROCESS_DMA_WORD_SIZE_UNIT * SE_PROCESS_STORE_CHANNELS); // (DMA_WORD_SIZE per channel) * channel number 0x80; 900 .const SE_BUFF1_DMA_24BIT_LINE_SIZE = SE_BUFF1_DMA_WORD_SIZE*3/BYTES_IN_MIU_LINE; 901 .const SE_BUFF1_DMA_16BIT_LINE_SIZE = SE_BUFF1_DMA_WORD_SIZE*2/BYTES_IN_MIU_LINE; 902 903 /* SE Background process DDR1 --> DDR2 */ 904 .const SE_BG_PROCESS_DMA_WORD_SIZE = 32; 905 .const SE_BG_PROCESS_DMA_24BIT_LINE_SIZE = SE_BG_PROCESS_DMA_WORD_SIZE*3/BYTES_IN_MIU_LINE; 906 .const SE_BG_PROCESS_DMA_16BIT_LINE_SIZE = SE_BG_PROCESS_DMA_WORD_SIZE*2/BYTES_IN_MIU_LINE; 907 908 /* spdif delay unit setting */ 909 .const SPDIF_DLYBUF_DMA_WORDSIZE = 32; 910 .const SPDIF_DLYBUF_DMA_LINESIZE = SPDIF_DLYBUF_DMA_WORDSIZE*2/BYTES_IN_MIU_LINE; 911 .const SPDIF_DLYFIFO_LEN = 64; 912 913 /* spdif nonPcm unit setting */ 914 .const SPDIF_NPCM_DMA_WORDSIZE = 32; 915 .const SPDIF_NPCM_DMA_LINESIZE = SPDIF_NPCM_DMA_WORDSIZE*2/BYTES_IN_MIU_LINE; 916 .const SPDIF_NPCMFIFO_LEN = 64; 917 918 /* hdmi npcm fifo unit setting */ 919 .const HDMI_NPCM_DMA_WORDSIZE = 128; 920 .const HDMI_NPCM_DMA_LINESIZE = HDMI_NPCM_DMA_WORDSIZE*2/BYTES_IN_MIU_LINE; 921 .const HDMI_NFIFO_LEN = 128*2; 922 923 /* hdmi delay unit setting */ 924 .const HDMI_DLYBUF_DMA_WORDSIZE = 32; 925 .const HDMI_DLYBUF_DMA_LINESIZE = HDMI_DLYBUF_DMA_WORDSIZE*2/BYTES_IN_MIU_LINE; 926 .const HDMI_DLYFIFO_LEN = 64; 927 928 /* SW DMA */ 929 .const SW_DMA_CTRL_RESET_BIT = 0; 930 .const SW_DMA_CTRL_START_BIT = 1; 931 .const SW_DMA_CTRL_CIRCL_BIT = 2; 932 933 .const SW_DMA_WORDSIZE = 32; 934 .const SW_DMA_LINESIZE = SW_DMA_WORDSIZE*2/BYTES_IN_MIU_LINE; 935 936 /******************************************************************** 937 * DSP ISR mapping 938 ********************************************************************/ 939 /* default 0 (no use) */ 940 #define ISR_MASK_PCM IMASK_SP1T_IRQ1 941 #define ISR_MASK_PCM2 IMASK_SP1R_IRQ0 942 #define ISR_MASK_TIMER IMASK_TM 943 944 /* default -1 (no use) */ 945 #define ISR_PMASK_PCM -1 946 #define ISR_PMASK_PCM2 -1 947 #define ISR_PMASK_DEC_R2_CMD 20 //from R2 IO 0xB000_0860 948 #define ISR_PMASK_R2_LOAD_CODE_CMD 21 //from R2 IO 0xB000_0840 949 950 #define DEC_MAIN_FUNC_PTR g_DecFunPtr 951 #define PCMOUT_FUNC_PTR g_IRQ1_isr_funcPtr 952 #define SIF_PCMOUT_FUNC_PTR g_IRQ0_isr_funcPtr 953 #define SIF_ENC_FUNC_PTR g_SifEncFuncPtr 954 #define SIF_ENC_DATAOUT_FUNC_PTR g_SifEncDataOutFuncPtr 955 956 /******************************************************************** 957 * DSP internal mailbox mapping 958 ********************************************************************/ 959 960 /* SPDIF NonPCM */ 961 #define D2S_MBOX_SPDIF_CTRL ddco_spdifNpcmCtrl // [0:2]=Acmod for AC3/AC3+/HE-AAC, [3]=LFE flag, 962 // [ 8:11]: HDMI sample rate 963 // 0: 96K, 1: 88K, 2: 64K 964 // 3: 48K, 4: 44K, 5: 32K 965 // 6: 24K, 7: 22K, 8: 16K 966 // 9: 12K, a: 11K, b: 8K 967 // c:192K, d: 176K e: 128K 968 // [12:15]: SPDIF sample rate 969 // 0: 96K, 1: 88K, 2: 64K 970 // 3: 48K, 4: 44K, 5: 32K 971 // 6: 24K, 7: 22K, 8: 16K 972 // 9: 12K, a: 11K, b: 8K 973 // [18] info to DDCO: 1-> -4.75dB; 0-> do nothing 974 // [19] : 1->48KHz, 0->non-48KHz 975 // [20] MultiCH_EN, [21]=ADEC Stop/Play,[22]=Freeze,[23]=Start 976 #define D2S_MBOX_SPDIF_WRPTR ddco_spdifNpcmWrPtr 977 #define S2D_MBOX_SPDIF_RDPTR ddco_spdifNpcmRdPtr 978 979 .const MBOX_MULTI_CHANNEL_ENABLE_BIT = 20; 980 .const MBOX_SPDIF_NPCM_CTRL_BIT_PLAY = 17; 981 .const MBOX_SPDIF_NPCM_CTRL_BIT_FREEZE = 22; 982 .const MBOX_SPDIF_NPCM_CTRL_BIT_START = 19; 983 .const MBOX_HDMI_NPCM_CTRL_BIT_PLAY = 21; 984 .const MBOX_HDMI_NPCM_CTRL_BIT_START = 23; 985 986 //#define MBOX_HDMI_NPCM_CTRL_BIT_START MBOX_BIT23 987 //#define MBOX_HDMI_NPCM_CTRL_BIT_PLAY MBOX_BIT21 988 //#define MBOX_MULTI_CHANNEL_ENABLE_BIT MBOX_BIT20 989 //#define MBOX_SPDIF_NPCM_CTRL_BIT_START MBOX_BIT19 990 #define MBOX_SPDIF_NPCM_DDE_MINUS_4_75DB MBOX_BIT18 991 //#define MBOX_SPDIF_NPCM_CTRL_BIT_PLAY MBOX_BIT17 992 #define MBOX_HDMI_NONPCM_FROM_ASND_DSP_BIT MBOX_BIT5 993 #define MBOX_HDMI_NONPCM_FROM_ASND_R2_BIT MBOX_BIT4 994 #define MBOX_SPDIF_NONPCM_FROM_ASND_DSP_BIT MBOX_BIT3 995 #define MBOX_SPDIF_NONPCM_FROM_ASND_R2_BIT MBOX_BIT2 996 //[23] HDMI nonPcm Start 997 //[22] 998 //[21] HDMI nonPcm PlayEnable 999 //[20] HDMI HBR mode 1000 //[19] SPDIF nonPcm Start 1001 //[18] inform DDEncode to attenuate 4.75dB 1002 //[17] SPDIF nonPcm PlayEnable 1003 //[16] 1004 //[15:12] SPDIF nonPcm sampleRate index 1005 // 0: 96K, 1: 88K, 2: 64K 1006 // 3: 48K, 4: 44K, 5: 32K 1007 // 6: 24K, 7: 22K, 8: 16K 1008 // 9: 12K, a: 11K, b: 8K 1009 1010 //[11:8] HDMI nonPcm sampleRate index 1011 // 0: 96K, 1: 88K, 2: 64K 1012 // 3: 48K, 4: 44K, 5: 32K 1013 // 6: 24K, 7: 22K, 8: 16K 1014 // 9: 12K, a: 11K, b: 8K 1015 // c:192K, d: 176K e: 128K 1016 1017 //[7] HDMI is Pcm or nonPcm 1018 //[6] SPDIF is Pcm or nonPcm 1019 //[5:4] hdmi nonPcm owner 1020 //[3:2] spdif nonPcm owner 1021 //[0:1] spdif/hdmi PCM attenuator index 1022 1023 1024 #define NULL_PAYLOAD_TEST 1 1025 1026 #if (NULL_PAYLOAD_TEST == 1) 1027 .const SPDIF_NPCM_MUTE_FRMCNT = 0x8; 1028 .const SPDIF_PCM_MUTE_SMPCNT = 0; 1029 .const SPDIF_NPCM_NULL_FRMCNT = 0xC + SPDIF_NPCM_MUTE_FRMCNT; 1030 #else 1031 .const SPDIF_NPCM_MUTE_FRMCNT = 0x10; 1032 .const SPDIF_PCM_MUTE_SMPCNT = 0; 1033 #endif 1034 1035 /* Mailbox with DEC R2 */ 1036 #define D2S_MBOX_PCMISR_CTRL DECR2M_2_DSP_MAILBOX1 1037 #define MBOX_R2_PCM1ISR_PLAY_START_BIT 0 //--> ³o¦U¥Ñ playSmpFlag / stop / pause ¨M©w 1038 #define MBOX_R2_PCM1ISR_PLAY_MUTE_BIT 1 //--> Mute 1039 #define MBOX_R2_PCM1ISR_USING_ASINK_ISR_BIT 2 1040 #define MBOX_R2_PCM2ISR_PLAY_START_BIT 8 1041 #define MBOX_R2_PCM2ISR_PLAY_MUTE_BIT 9 1042 #define MBOX_R2_PCM2ISR_USING_ASINK_ISR_BIT 10 1043 1044 #define D2S_MBOX_PCM1_DRAM_WRPTR DECR2M_2_DSP_MAILBOX2 1045 #define D2S_MBOX_PCM1_SYNTH_H DECR2M_2_DSP_MAILBOX3 1046 #define D2S_MBOX_PCM1_SYNTH_L DECR2M_2_DSP_MAILBOX4 1047 1048 #define D2S_MBOX_PCM2_DRAM_WRPTR DECR2M_2_DSP_MAILBOX5 1049 #define D2S_MBOX_PCM2_SYNTH_H DECR2M_2_DSP_MAILBOX6 1050 #define D2S_MBOX_PCM2_SYNTH_L DECR2M_2_DSP_MAILBOX7 1051 1052 #define D2S_MBOX_R2_TO_DSP_COMMAND DECR2M_2_DSP_MAILBOX8 1053 #define D2S_CMD_UPD_PCM1_MUTECNT 0x0001 // Bit0 1054 #define D2S_CMD_CLR_PCM1_PLAYCNT 0x0002 // Bit1 1055 #define D2S_CMD_UPD_PCM1_PLAYCNT 0x0004 // Bit2 1056 #define D2S_CMD_FLUSH_PCM1_SMPS 0x0008 // Bit3 1057 #define D2S_CMD_RESET_PCM1 0x0010 // Bit4 1058 #define D2S_CMD_UPD_PCM2_MUTECNT 0x0020 // Bit5 1059 #define D2S_CMD_CLR_PCM2_PLAYCNT 0x0040 // Bit6 1060 #define D2S_CMD_UPD_PCM2_PLAYCNT 0x0080 // Bit7 1061 #define D2S_CMD_FLUSH_PCM2_SMPS 0x0100 // Bit8 1062 #define D2S_CMD_RESET_PCM2 0x0200 // Bit9 1063 1064 #define D2S_MBOX_R2_TO_DSP_PARAM DECR2M_2_DSP_MAILBOX9 1065 #define D2S_R2_SPDIF_WR_PTR DECR2M_2_DSP_MAILBOXA 1066 #define D2S_MBOX_HDMI_NPCM_WRPTR DECR2M_2_DSP_MAILBOXB 1067 //#define D2S_MBOX_HDMI_NPCM_WRPTR hdmi_npcmWrAddr 1068 1069 #define D2S_MBOX_HDMI_NPCM_CMD DECR2M_2_DSP_MAILBOXC 1070 #define D2S_R2_SPDIF_CTRL DECR2M_2_DSP_MAILBOXC 1071 #define D2S_MBOX_NPCM_CTRL DECR2M_2_DSP_MAILBOXC 1072 1073 #define D2S_R2_DOLBY_META_DATA DECR2M_2_DSP_MAILBOXD 1074 1075 // PRE-SE PCM Read/Write pointer 1076 // DEC-R2 --> SE-DSP 1077 #define D2S_R2_PCMOUT_WRPTR DECR2M_2_DSP_MAILBOXF // 0xB000087C 1078 1079 // SE-DSP --> DEC-R2 1080 #define S2D_R2_PCMIN_WRPTR DSP_2_DECR2M_MAILBOXC // 0xB0000830 1081 1082 #define D2S_DSP_ENCODE_SETTING DECR2M_2_DSP_MAILBOXE 1083 #define D2S_CMD_SOUND_MIXER_DISABLE_BIT MBOX_BIT11 // Bit11 //[1] SOUND_MIXER, 0:in DSP (MS11), 1:in DEC_R2 (MS12) 1084 #define D2S_CMD_DDENC_ENABLE MBOX_BIT10 // Bit10 1085 //#define MBOX_NONPCM_DDPE_ENABLE_BIT MBOX_BIT7 //Roger Add 1086 #define MBOX_NONPCM_DDE_ENABLE_BIT MBOX_BIT6 1087 #define MBOX_NONPCM_DTSE_ENABLE_BIT MBOX_BIT5 1088 //[6] DSP DDENC ENABLE bit 1089 //[5] DSP DTS ENC ENABLE bit 1090 //[4] LFE 1091 //[3:0] AC mode 1092 1093 /************************************************************/ 1094 1095 #define S2D_MBOX_DSP_TO_R2_COMMAND DSP_2_DECR2M_MAILBOX0 1096 #define S2D_CMD_RESET_PCM1_AVSYNC 0x0001 1097 #define S2D_CMD_RESET_PCM2_AVSYNC 0x0002 1098 1099 #define S2D_MBOX_DSP_TO_R2_PARAM DSP_2_DECR2M_MAILBOX1 1100 #define S2D_MBOX_R2CMD_RECEIVE_CNT DSP_2_DECR2M_MAILBOX2 1101 1102 #define S2D_MBOX_PCM1_PLAYCNT DSP_2_DECR2M_MAILBOX3 1103 #define S2D_MBOX_PCM1_FIFOCNT DSP_2_DECR2M_MAILBOX4 1104 //#define S2D_MBOX_PCM1_DRAM_RDPTR DSP_2_DECR2M_MAILBOX5 1105 1106 #define S2D_MBOX_PCM2_PLAYCNT DSP_2_DECR2M_MAILBOX6 1107 #define S2D_MBOX_PCM2_FIFOCNT DSP_2_DECR2M_MAILBOX7 1108 #define S2D_MBOX_PCM2_DRAM_RDPTR DSP_2_DECR2M_MAILBOX5 1109 1110 #define S2D_R2_SPDIF_RD_PTR DSP_2_DECR2M_MAILBOXA 1111 #define S2D_MBOX_HDMI_NPCM_RDPTR DSP_2_DECR2M_MAILBOXB 1112 1113 #define S2D_IP_SECURITY_KEY DSP_2_DECR2M_MAILBOXE 1114 #define S2D_OTP_BOUNDING DSP_2_DECR2M_MAILBOXF 1115 1116 #define S2D_MBOX_ENCODE_SURPPORT DSP_2_DECR2M_MAILBOX9 1117 #define DDE_ENCODE_SURPPORT_BIT MBOX_BIT0 1118 #define DTSE_ENCODE_SURPPORT_BIT MBOX_BIT1 1119 #define DDPE_ENCODE_SURPPORT_BIT MBOX_BIT2 1120 1121 1122 1123 !#define S2A_R2_PCMIN_WRPTR DSP_2_DECR2M_MAILBOX7 1124 !#define S2A_R2_PCMIN2_WRPTR DSP_2_DECR2M_MAILBOX8 1125 !#define S2A_R2_SPDIF_RD_PTR DSP_2_DECR2M_MAILBOX9 1126 !#define S2A_IP_SECURITY_KEY DSP_2_DECR2M_MAILBOXE 1127 !#define S2A_OTP_BOUNDING DSP_2_DECR2M_MAILBOXF 1128 1129 !#define A2S_R2_PCMOUT_WRPTR DECR2M_2_DSP_MAILBOXD 1130 !#define A2S_R2_PCMOUT2_WRPTR DECR2M_2_DSP_MAILBOX0 1131 !#define A2S_R2_SPDIF_WR_PTR DECR2M_2_DSP_MAILBOXE 1132 !#define A2S_R2_SPDIF_CTRL DECR2M_2_DSP_MAILBOXF 1133 1134 /******************************************************************** 1135 * DSP io mapping 1136 ********************************************************************/ 1137 #define NULL_IO 0 1138 1139 /* DSP common IO */ 1140 #define DSPIO_SPDIF_IN_FREQ STATUS_SPDIF_FREQ 1141 #define DSPIO_HDMI_IN_FREQ STATUS_HDMI_FREQ 1142 #define DSPIO_HDMI_IN_PC STATUS_HDMI_PC 1143 1144 /* DSP Bounding IO */ 1145 #define DSP_BOUND_OPTION 1 1146 #define DSPIO_BOUND_OPTION 0xA0FF 1147 .const BOUNDING_BIT_DD = 0; //DD 1148 .const BOUNDING_BIT_DDP = 1; //DD+ 1149 .const BOUNDING_BIT_DPULSE = 2; //Dolby Pulse (MS10 DDT) or DDCO 1150 .const BOUNDING_BIT_DVOL = 3; //Dolby Volume 1151 .const BOUNDING_BIT_DTRUEHD = 4; //Dolby TrueHD 1152 .const BOUNDING_BIT_DDDCO = 5; //Dolby DDCO 1153 .const BOUNDING_BIT_DTSENVELO = 6; //DTS Envelo / Symmetry 1154 .const BOUNDING_BIT_DTSDMP = 7; //DTS DMP 1155 .const BOUNDING_BIT_DTSLBR = 8; //DTS LBR 1156 .const BOUNDING_BIT_DTSTS = 9; //DTS Transcoder 1157 .const BOUNDING_BIT_DTSCORELESS = 10; //DTS Coreless 1158 .const BOUNDING_BIT_SRS = 11; //SRS / Adv Sound 1159 .const BOUNDING_BIT_DOLBY = 12; // when bit[12] = 0, all dolby ip's licenses open 1160 1161 //#define AUTH_OPTION 0x0FF2 1162 .const AUTH_BIT_DD = 0; 1163 .const AUTH_BIT_DDP = 1; 1164 .const AUTH_BIT_DDE = 2; 1165 .const AUTH_BIT_DTSDEC = 3; 1166 .const AUTH_BIT_MS10DDT = 4; 1167 .const AUTH_BIT_WMA = 5; 1168 .const AUTH_BIT_DRA = 6; 1169 .const AUTH_BIT_DTSLBR = 7; 1170 .const AUTH_BIT_GAAC = 8; 1171 .const AUTH_BIT_DEMOMODE = 12; 1172 .const AUTH_BIT_COOK = 16; 1173 .const AUTH_BIT_DTS_HD = 17; 1174 .const AUTH_BIT_MS12_LC = 18; 1175 .const AUTH_BIT_MS12_D = 19; 1176 .const AUTH_BIT_SONICMOTION_ABS3D = 20; 1177 .const AUTH_BIT_MS12_B = 21; 1178 .const AUTH_BIT_DV258 = 22; 1179 1180 /* IP AUTH */ 1181 #define D2S_MBOX_IP_AUTH DEC2SE_MAILBOX7 1182 1183 /* PCM output port */ 1184 #define DSP_SW_DMA_PCM_L_OUT DEC4_PCM1_OUT 1185 #define DSP_SW_DMA_PCM_R_OUT DEC4_PCM2_OUT 1186 #define SIF_DSP_MAIN_DMX_L_OUT DEC4_PCM1_OUT 1187 #define SIF_DSP_MAIN_DMX_R_OUT DEC4_PCM2_OUT 1188 1189 #define R2_PCM1_MCH__L_OUT DEC3_PCM3_OUT 1190 #define R2_PCM1_MCH__C_OUT DEC3_PCM4_OUT 1191 #define R2_PCM1_MCH__R_OUT DEC3_PCM5_OUT 1192 #define R2_PCM1_MCH_LS_OUT DEC3_PCM6_OUT 1193 #define R2_PCM1_MCH_RS_OUT DEC3_PCM7_OUT 1194 #define R2_PCM1_MCH_SW_OUT DEC3_PCM8_OUT 1195 #define R2_PCM1_DMX__L_OUT DEC3_PCM1_OUT 1196 #define R2_PCM1_DMX__R_OUT DEC3_PCM2_OUT 1197 1198 #define R2_PCM2_DMX__L_OUT DEC4_PCM1_OUT 1199 #define R2_PCM2_DMX__R_OUT DEC4_PCM2_OUT 1200 1201 #define R2_PCM1_SYNTH_L DVB3_FIX_SYNTH_NF_L 1202 #define R2_PCM1_SYNTH_H DVB3_FIX_SYNTH_NF_H 1203 #define R2_PCM2_SYNTH_L DVB4_FIX_SYNTH_NF_L 1204 #define R2_PCM2_SYNTH_H DVB4_FIX_SYNTH_NF_H 1205 1206 /************************************************ 1207 * Below is macro for DSP code only 1208 *************************************************/ 1209 #define DSP_DMA_CHECK 1210 1211 #define INC_WHILE_ONE_CNTR ar = dm (S2M_MBOX_WHILE1_CNTR); \ 1212 ay0 = 0x00FF00; \ 1213 af = ar and ay0; \ 1214 ar = ar + 0x000001; \ 1215 ay0 = 0x0000FF; \ 1216 ar = ar and ay0; \ 1217 ar = ar or af; \ 1218 dm (S2M_MBOX_WHILE1_CNTR) = ar 1219 1220 #define INC_DEBUG_CNT(x) ar = dm(kh_debugCnt+x); \ 1221 ar = ar + 1; \ 1222 dm(kh_debugCnt+x) = ar; 1223 1224 #define CONFIG_PCM_OUTPUT_PORT ar = 0; \ 1225 dm (DEC_OUT_SEL) = ar; 1226 1227 #define TRIGGER_INT_TO_MCU ar = 0x0000; IO(PDATA) = ar; \ 1228 nop; nop; nop; nop; \ 1229 nop; nop; nop; nop; \ 1230 ar = 0x8000; IO(PDATA) = ar; \ 1231 nop; nop; nop; nop; \ 1232 nop; nop; nop; nop; \ 1233 ar = 0x0000; IO(PDATA) = ar 1234 1235 /* Saft jump to i0 ~ i7 x:address, y:i0 ~ i7 */ 1236 #define I_REGISTER_JUMP(x,y) sr = lshift x by -16(lo); \ 1237 y = x; \ 1238 CPR = sr0; \ 1239 jump (y); 1240 1241 /* Saft call to i0 ~ i7 x:address, y:i0 ~ i7 */ 1242 #define I_REGISTER_CALL(x,y) sr = lshift x by -16(lo); \ 1243 y = x; \ 1244 CPR = sr0; \ 1245 call (y); 1246 1247 #define SEND_INT_TO_R2(cmd, param) ar = param; \ 1248 dm(S2D_MBOX_DSP_TO_R2_PARAM) = ar; \ 1249 ar = cmd; \ 1250 dm(S2D_MBOX_DSP_TO_R2_COMMAND) = ar 1251 1252 #else 1253 1254 #define DSP2_TO_COMMON_DRAM_OFFSET (ASND_DSP_DDR_SIZE / BYTES_IN_MIU_LINE) 1255 1256 /* DMA Reader Buffer */ 1257 #define DSP2_DMA_READER_DRAM_BASE (DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_DMA_READER_DRAM_BASE /BYTES_IN_MIU_LINE)) 1258 #define DSP2_DMA_READER_DRAM_SIZE ((DMA_READER_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1) 1259 1260 /* HW DMA Reader2 Buffer */ 1261 #define DSP2_HW_DMA_READER2_DRAM_BASE (DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_HW_DMA_READER2_DRAM_BASE /BYTES_IN_MIU_LINE)) 1262 #define DSP2_HW_DMA_READER2_DRAM_SIZE ((HW_DMA_READER2_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1) 1263 1264 /* Software DMA */ 1265 #define DSP2_SW_DMA_READER_DRAM_BASE (DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_SW_DMA_READER_DRAM_BASE / BYTES_IN_MIU_LINE)) 1266 #define DSP2_SW_DMA_READER_DRAM_SIZE ((SW_DMA_READER_DRAM_SIZE / BYTES_IN_MIU_LINE) - 1) 1267 1268 /* PCM capture buffer */ 1269 #define DSP2_PCM_CAPTURE_BUFFER_DRAM_BASE (DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_PCM_CAPTURE1_BUFFER_DRAM_BASE / BYTES_IN_MIU_LINE)) 1270 #define DSP2_PCM_CAPTURE2_BUFFER_DRAM_BASE (DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_PCM_CAPTURE2_BUFFER_DRAM_BASE / BYTES_IN_MIU_LINE)) 1271 #define DSP2_PCM_CAPTURE3_BUFFER_DRAM_BASE (DSP2_TO_COMMON_DRAM_OFFSET + (OFFSET_PCM_CAPTURE3_BUFFER_DRAM_BASE / BYTES_IN_MIU_LINE)) 1272 #define DSP2_PCM_CAPTURE_BUFFER_DRAM_SIZE (PCM_CAPTURE_BUFFER_DRAM_SIZE/ BYTES_IN_MIU_LINE) 1273 #define DSP2_PCM_CAPTURE_COPY_WORDSIZE 32 1274 #define DSP2_PCM_CAPTURE_COPY_LINESIZE 4 1275 1276 #endif //_COMPILE_DSP_ 1277 1278 //Reseved XBox 1279 /* srs puresound */ 1280 //reserved XBox for SRS start from XBox 0xB960 1281 #define DSP2XboxAddr_SRS_PURESOUND_RESERVED1 0xB960 1282 1283 #define SRS_PURESOUND_AeqFir_NumOfTaps_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+1 1284 #define SRS_PURESOUND_AeqIir_NumOfSections_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+2 1285 #define SRS_PURESOUND_AeqIir1Coefs_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+3 1286 #define SRS_PURESOUND_AeqIir2Coefs_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+8 1287 #define SRS_PURESOUND_AeqIir3Coefs_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+13 1288 #define SRS_PURESOUND_AeqIir4Coefs_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+18 1289 #define SRS_PURESOUND_AeqIir5Coefs_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+23 1290 #define SRS_PURESOUND_AeqIir6Coefs_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+28 1291 #define SRS_PURESOUND_AeqIir7Coefs_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+33 1292 #define SRS_PURESOUND_AeqIir8Coefs_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+38 1293 #define SRS_PURESOUND_AeqIir1_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+43 1294 #define SRS_PURESOUND_AeqIir2_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+44 1295 #define SRS_PURESOUND_AeqIir3_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+45 1296 #define SRS_PURESOUND_AeqIir4_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+46 1297 #define SRS_PURESOUND_AeqIir5_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+47 1298 #define SRS_PURESOUND_AeqIir6_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+48 1299 #define SRS_PURESOUND_AeqIir7_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+49 1300 #define SRS_PURESOUND_AeqIir8_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+50 1301 #define SRS_PURESOUND_AeqIir_Gain_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+51 1302 #define SRS_PURESOUND_AeqIir_Gain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+52 1303 #define SRS_PURESOUND_AeqFir_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+53 1304 #define SRS_PURESOUND_AeqFir_Gain_iwl_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+54 1305 #define SRS_PURESOUND_AeqFir_Gain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+55 1306 #define SRS_PURESOUND_AeqFirCoefs_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED1+64 1307 1308 #define DSP2XboxAddr_SRS_PURESOUND_RESERVED2 SRS_PURESOUND_AeqFirCoefs_addr+1 1309 #define SRS_PURESOUND_mDummy_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2 1310 #define SRS_PURESOUND_SRS_EN_BITS_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+1 1311 #define SRS_PURESOUND_mInputGain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+2 1312 #define SRS_PURESOUND_mOutputGain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+3 1313 #define SRS_PURESOUND_mBypassGain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+4 1314 #define SRS_PURESOUND_mHPFfc_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+5 1315 #define SRS_PURESOUND_hlInputGain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+25 1316 #define SRS_PURESOUND_hlOutputGain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+26 1317 #define SRS_PURESOUND_hlBypassGain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+27 1318 #define SRS_PURESOUND_hlLimiterboost_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+28 1319 #define SRS_PURESOUND_hlHardLimit_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+29 1320 #define SRS_PURESOUND_hlDelaylen_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+30 1321 #define SRS_PURESOUND_AeqInputGain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+32 1322 #define SRS_PURESOUND_AeqOutputGain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+33 1323 #define SRS_PURESOUND_AeqBypassGain_addr DSP2XboxAddr_SRS_PURESOUND_RESERVED2+34 1324 1325 #define DSP2XboxAddr_SRS_PURESOUND_RESERVED_END SRS_PURESOUND_AeqBypassGain_addr 1326 1327 /* atv */ 1328 //reserved XBox for ATV 1329 #define DSP2XboxAddr_ATV_RESERVED1 DSP2XboxAddr_SRS_PURESOUND_RESERVED_END+1 1330 #define DSP2XboxAddr_AU_PAL_SYS_THRESHOLD DSP2XboxAddr_ATV_RESERVED1 1331 #define DSP2XboxAddr_SIF_PM_GAIN_TBL_PAL DSP2XboxAddr_AU_PAL_SYS_THRESHOLD+12 1332 #define DSP2XboxAddr_SIF_PM_GAIN_TBL_BTSC DSP2XboxAddr_AU_PAL_SYS_THRESHOLD+12 1333 #define DSP2XboxAddr_ATV_RESERVED_END DSP2XboxAddr_SIF_PM_GAIN_TBL_BTSC+8-1 1334 1335 /************************************************ 1336 * For Compile Pass mailbox (Need to remove later) 1337 ************************************************/ 1338 1339 #define D2M_MBOX_INTR_CMDTYPE MB_2DB2 1340 #define DSP1PmAddr_ipSecurity 0x0FF2 1341 #define D2M_MBOX_ENC_LINEADDR MB_2DAC //MPEG Encoder 1342 #define D2M_MBOX_ENC_LINESIZE MB_2DAE //MPEG Encoder 1343 #define M2D_MBOX_PIO_ID MB_2D8A 1344 #define DSP1PmAddr_smpRate 0x0FF7 1345 #define D2M_MBOX_HDMI_NPCM_LOCK MB_2DB4 //[ 3:0] Always in LSB Nibble 1346 #define MBOX_DBGCMD_RELOAD_DTV1_BEG 0xF000 1347 #define MBOX_DBGCMD_RELOAD_DTV1_END 0xF100 1348 #define MBOX_DBGCMD_RELOAD_DTV2_BEG 0xF600 1349 #define MBOX_DBGCMD_RELOAD_DTV2_END 0xF700 1350 #define DSP1DmAddr_sys_IoInfo NULL 1351 #define M2D_MBOX_MM_FILEIN_TAG MB_2D8C 1352 #define MBOX_DSP_INIT_ACK 0xE300 1353 #define D2M_MBOX_DBG_RESULT2 MB_2DBE 1354 #define D2M_MBOX_DBG_RESULT1 MB_2DBC 1355 #define M2D_MBOX_DEC_CTRL MB_2D86 1356 #define M2D_MBOX_DBG_CMD1 MB_2D9C 1357 1358 #define D2M_MBOX_DBG_RESULT1 MB_2DBC 1359 #define MBOX_DSP_INIT_ACK 0xE300 1360 #define D2M_MBOX_DBG_RESULT2 MB_2DBE 1361 #define MBOX_DSP_RELOAD_ACK1 0x0033 1362 #define MBOX_DSP_RELOAD_ACK2 0x0077 1363 #define M2D_MBOX_DEC_CTRL MB_2D86 1364 #define D2M_MBOX_SAMPLERATE MB_2DA6 1365 #define DSP1DmAddr_dec1_param 0x47A0 1366 #define DSP1DmAddr_dec1_info 0x47C0 1367 #define DSP1DmAddr_dec1_omx_param 0x42B4 1368 #define M2D_MBOX_UNI_PCM3_WRPTR MB_2D94 1369 #define DSP1PmAddr_video_TD 0x0FF1 1370 #define D2M_MBOX_UNI_PCM_BUFFEBT MB_2D6A 1371 1372 //// SIF /* SIF DSP PM vars */ // for SIF PAL DSP PM vars // 1373 #define ADDR_gain_base 0x1921 1374 #define ADDR_thr_base 0x1A20 1375 #define ADDR_pfir_base 0x1A90 // for SIF BTSC DSP PM vars // 1376 #define BTSC_COMPILE_OPTION_Addr 0x19F1 // len 1 1377 #define BTSC_OUTPUT_GAIN_Addr 0x1A21 // len 2 1378 #define BTSC_THRESHOLD_Addr 0x1A23 // len 10 1379 #define MTS_OUTPUT_GAIN_Addr 0x1A34 //len 6 1380 #define SIF_AGC_THRESHOLD_Addr 0x192D //len 3 /// PAL gain setting address 1381 #define ADDR_fm_stdM_gain ADDR_gain_base // len = 4 1382 #define ADDR_fm_stdX_gain ADDR_fm_stdM_gain+4 // len = 4 1383 #define ADDR_nicam_gain ADDR_fm_stdX_gain+4 // len = 2 1384 #define ADDR_am_gain ADDR_nicam_gain+2 // len = 2 1385 #define ADDR_agc_gain ADDR_am_gain+2 // len = 24 // PAL threshold setting address 1386 #define ADDR_a2_stdM_thr ADDR_thr_base // len = 15 1387 #define ADDR_a2_stdBG_thr ADDR_a2_stdM_thr+15 // len = 15 1388 #define ADDR_a2_stdDK_thr ADDR_a2_stdBG_thr+15 // len = 15 1389 #define ADDR_a2_stdI_thr ADDR_a2_stdDK_thr+15 // len = 4 1390 #define ADDR_am_thr ADDR_a2_stdI_thr+4 // len = 3 1391 #define ADDR_hidev_stdM_thr ADDR_am_thr+3 // len = 4 1392 #define ADDR_hidev_stdBG_thr ADDR_hidev_stdM_thr+4 // len = 4 1393 #define ADDR_hidev_stdDK_thr ADDR_hidev_stdBG_thr+4 // len = 4 1394 #define ADDR_hidev_stdI_thr ADDR_hidev_stdDK_thr+4 // len = 4 1395 #define ADDR_nicam_stdBG_pherr_thr ADDR_hidev_stdI_thr+4 //len = 3 1396 #define ADDR_nicam_stdI_pherr_thr ADDR_nicam_stdBG_pherr_thr+3 // len = 3 1397 #define ADDR_a2_bg_nicam_fm_nsr_thr 0x186F // len = 1 1398 #define ADDR_a2_dk_nicam_fm_nsr_thr 0x1870 // len = 1 // pfir setting address 1399 #define ADDR_hidev_demfir ADDR_pfir_base // len = 15 1400 #define ADDR_fm_ch1_pfir ADDR_hidev_demfir+16 // len = 30 1401 #define ADDR_fm_ch2_pfir ADDR_fm_ch1_pfir+30 // len = 30 1402 #define ADDR_hidev_lv1_pfir ADDR_fm_ch2_pfir+30 // len = 20 1403 #define ADDR_hidev_lv2_pfir ADDR_hidev_lv1_pfir+20 // len = 20 1404 #define ADDR_hidev_lv3_pfir ADDR_hidev_lv2_pfir+20 // len = 20 // BTSC threshold setting address 1405 #define HIDEV_NSR_THRESHOLD_Addr BTSC_THRESHOLD_Addr+10 // len 2 1406 #define BTSC_MONO_AMP_THRESHOLD_Addr HIDEV_NSR_THRESHOLD_Addr+2 // len 2 1407 #define HIDEV_AMP_THRESHOLD_Addr BTSC_MONO_AMP_THRESHOLD_Addr+2 // len 2 1408 #define BTSC_SAP_PHASE_DIFF_CLIP_THR_Addr HIDEV_AMP_THRESHOLD_Addr+2 // len 1 1409 #define BTSC_PILOT_DEBOUNCE_THRESHOLD_Addr MTS_OUTPUT_GAIN_Addr+6 // len 3 1410 #define BTSC_SAP_ON_DETECTION_DEBOUNCE_THRESHOLD_Addr BTSC_PILOT_DEBOUNCE_THRESHOLD_Addr+3 // len 1 1411 1412 #define M2S_MBOX_MM_FILEIN_TAG MB_2DCC //[7:0] 1413 #define DSP2PmAddr_smpRate 0x0D49 1414 #define DSP2PmAddr_soundMode 0x0D4A 1415 #define DSP2DmAddr_dec1_param 0x4390 1416 #define M2S_MBOX_DRC_CTRL MB_2D2E 1417 1418 /* SIF DSP PM vars */ 1419 /* for SIF PAL DSP PM vars */ 1420 1421 #define ADDR_gain_base_2 NULL 1422 #define ADDR_thr_base_2 NULL 1423 #define ADDR_pfir_base_2 NULL 1424 // for SIF BTSC DSP PM vars // 1425 #define BTSC_COMPILE_OPTION_Addr_2 NULL // len 1 1426 #define BTSC_OUTPUT_GAIN_Addr_2 NULL // len 2 1427 #define BTSC_THRESHOLD_Addr_2 NULL // len 10 1428 #define MTS_OUTPUT_GAIN_Addr_2 NULL //len 6 1429 #define SIF_AGC_THRESHOLD_Addr_2 NULL //len 3 1430 1431 /// PAL gain setting address 1432 #define ADDR_fm_stdM_gain_2 NULL // len = 4 1433 #define ADDR_fm_stdX_gain_2 NULL // len = 4 1434 #define ADDR_nicam_gain_2 NULL // len = 2 1435 #define ADDR_am_gain_2 NULL // len = 2 1436 #define ADDR_agc_gain_2 NULL // len = 24 1437 1438 // PAL threshold setting address 1439 #define ADDR_a2_stdM_thr_2 NULL // len = 15 1440 #define ADDR_a2_stdBG_thr_2 NULL // len = 15 1441 #define ADDR_a2_stdDK_thr_2 NULL // len = 15 1442 #define ADDR_a2_stdI_thr_2 NULL // len = 4 1443 #define ADDR_am_thr_2 NULL // len = 3 1444 #define ADDR_hidev_stdM_thr_2 NULL // len = 4 1445 #define ADDR_hidev_stdBG_thr_2 NULL // len = 4 1446 #define ADDR_hidev_stdDK_thr_2 NULL // len = 4 1447 #define ADDR_hidev_stdI_thr_2 NULL // len = 4 1448 #define ADDR_nicam_stdBG_pherr_thr_2 NULL //len = 3 1449 #define ADDR_nicam_stdI_pherr_thr_2 NULL // len = 3 1450 #define ADDR_a2_bg_nicam_fm_nsr_thr_2 NULL // len = 1 1451 #define ADDR_a2_dk_nicam_fm_nsr_thr_2 NULL // len = 1 1452 1453 // pfir setting address 1454 #define ADDR_hidev_demfir_2 NULL // len = 15 1455 #define ADDR_fm_ch1_pfir_2 NULL // len = 30 1456 #define ADDR_fm_ch2_pfir_2 NULL // len = 30 1457 #define ADDR_hidev_lv1_pfir_2 NULL // len = 20 1458 #define ADDR_hidev_lv2_pfir_2 NULL // len = 20 1459 #define ADDR_hidev_lv3_pfir_2 NULL // len = 20 1460 1461 // BTSC threshold setting address 1462 #define HIDEV_NSR_THRESHOLD_Addr_2 NULL // len 2 1463 #define BTSC_MONO_AMP_THRESHOLD_Addr_2 NULL // len 2 1464 #define HIDEV_AMP_THRESHOLD_Addr_2 NULL // len 2 1465 1466 #define BTSC_SAP_PHASE_DIFF_CLIP_THR_Addr_2 NULL // len 1 1467 #define BTSC_PILOT_DEBOUNCE_THRESHOLD_Addr_2 NULL // len 3 1468 #define BTSC_SAP_ON_DETECTION_DEBOUNCE_THRESHOLD_Addr_2 NULL // len 1 1469 1470 /************************************************ 1471 * End for Compile Pass mailbox (Need to remove later) 1472 ************************************************/ 1473 1474 1475 #endif //_AUDIO_COMM2_H_ 1476 1477