xref: /rk3399_rockchip-uboot/include/drm_modes.h (revision 298cc5970d24f4573ffb30717f481df2581d59b4)
1 /*
2  * (C) Copyright 2008-2016 Fuzhou Rockchip Electronics Co., Ltd
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef _DRM_MODES_H
8 #define _DRM_MODES_H
9 
10 #include "fdtdec.h"
11 
12 #define DRM_DISPLAY_INFO_LEN	32
13 #define DRM_CONNECTOR_NAME_LEN	32
14 #define DRM_DISPLAY_MODE_LEN	32
15 #define DRM_PROP_NAME_LEN	32
16 
17 #define DRM_MODE_TYPE_BUILTIN	(1<<0)
18 #define DRM_MODE_TYPE_CLOCK_C	((1<<1) | DRM_MODE_TYPE_BUILTIN)
19 #define DRM_MODE_TYPE_CRTC_C	((1<<2) | DRM_MODE_TYPE_BUILTIN)
20 #define DRM_MODE_TYPE_PREFERRED	(1<<3)
21 #define DRM_MODE_TYPE_DEFAULT	(1<<4)
22 #define DRM_MODE_TYPE_USERDEF	(1<<5)
23 #define DRM_MODE_TYPE_DRIVER	(1<<6)
24 
25 /* Video mode flags */
26 /* bit compatible with the xorg definitions. */
27 #define DRM_MODE_FLAG_PHSYNC			(1 << 0)
28 #define DRM_MODE_FLAG_NHSYNC			(1 << 1)
29 #define DRM_MODE_FLAG_PVSYNC			(1 << 2)
30 #define DRM_MODE_FLAG_NVSYNC			(1 << 3)
31 #define DRM_MODE_FLAG_INTERLACE			(1 << 4)
32 #define DRM_MODE_FLAG_DBLSCAN			(1 << 5)
33 #define DRM_MODE_FLAG_CSYNC			(1 << 6)
34 #define DRM_MODE_FLAG_PCSYNC			(1 << 7)
35 #define DRM_MODE_FLAG_NCSYNC			(1 << 8)
36 #define DRM_MODE_FLAG_HSKEW			(1 << 9) /* hskew provided */
37 #define DRM_MODE_FLAG_BCAST			(1 << 10)
38 #define DRM_MODE_FLAG_PIXMUX			(1 << 11)
39 #define DRM_MODE_FLAG_DBLCLK			(1 << 12)
40 #define DRM_MODE_FLAG_CLKDIV2			(1 << 13)
41 /*
42  * When adding a new stereo mode don't forget to adjust DRM_MODE_FLAGS_3D_MAX
43  * (define not exposed to user space).
44  */
45 #define DRM_MODE_FLAG_3D_MASK			(0x1f << 14)
46 #define  DRM_MODE_FLAG_3D_NONE			(0 << 14)
47 #define  DRM_MODE_FLAG_3D_FRAME_PACKING		(1 << 14)
48 #define  DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE	(2 << 14)
49 #define  DRM_MODE_FLAG_3D_LINE_ALTERNATIVE	(3 << 14)
50 #define  DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL	(4 << 14)
51 #define  DRM_MODE_FLAG_3D_L_DEPTH		(5 << 14)
52 #define  DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH	(6 << 14)
53 #define  DRM_MODE_FLAG_3D_TOP_AND_BOTTOM	(7 << 14)
54 #define  DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF	(8 << 14)
55 
56 /* Panel Mirror control */
57 #define DRM_MODE_FLAG_XMIRROR			(1<<28)
58 #define DRM_MODE_FLAG_YMIRROR			(1<<29)
59 #define DRM_MODE_FLAG_XYMIRROR			(DRM_MODE_FLAG_XMIRROR | DRM_MODE_FLAG_YMIRROR)
60 
61 /* Picture aspect ratio options */
62 #define DRM_MODE_PICTURE_ASPECT_NONE		0
63 #define DRM_MODE_PICTURE_ASPECT_4_3		1
64 #define DRM_MODE_PICTURE_ASPECT_16_9		2
65 #define DRM_MODE_PICTURE_ASPECT_64_27		3
66 #define DRM_MODE_PICTURE_ASPECT_256_135		4
67 
68 /* Aspect ratio flag bitmask (4 bits 22:19) */
69 #define DRM_MODE_FLAG_PIC_AR_MASK		(0x0F << 19)
70 #define  DRM_MODE_FLAG_PIC_AR_NONE \
71 			(DRM_MODE_PICTURE_ASPECT_NONE << 19)
72 #define  DRM_MODE_FLAG_PIC_AR_4_3 \
73 			(DRM_MODE_PICTURE_ASPECT_4_3 << 19)
74 #define  DRM_MODE_FLAG_PIC_AR_16_9 \
75 			(DRM_MODE_PICTURE_ASPECT_16_9 << 19)
76 #define  DRM_MODE_FLAG_PIC_AR_64_27 \
77 			(DRM_MODE_PICTURE_ASPECT_64_27 << 19)
78 #define  DRM_MODE_FLAG_PIC_AR_256_135 \
79 			(DRM_MODE_PICTURE_ASPECT_256_135 << 19)
80 
81 /*
82  * DRM_MODE_ROTATE_<degrees>
83  *
84  * Signals that a drm plane is been rotated <degrees> degrees in counter
85  * clockwise direction.
86  *
87  * This define is provided as a convenience, looking up the property id
88  * using the name->prop id lookup is the preferred method.
89  */
90 #define DRM_MODE_ROTATE_0       (1<<0)
91 #define DRM_MODE_ROTATE_90      (1<<1)
92 #define DRM_MODE_ROTATE_180     (1<<2)
93 #define DRM_MODE_ROTATE_270     (1<<3)
94 
95 /*
96  * DRM_MODE_ROTATE_MASK
97  *
98  * Bitmask used to look for drm plane rotations.
99  */
100 #define DRM_MODE_ROTATE_MASK (\
101 		DRM_MODE_ROTATE_0  | \
102 		DRM_MODE_ROTATE_90  | \
103 		DRM_MODE_ROTATE_180 | \
104 		DRM_MODE_ROTATE_270)
105 
106 /*
107  * DRM_MODE_REFLECT_<axis>
108  *
109  * Signals that the contents of a drm plane is reflected along the <axis> axis,
110  * in the same way as mirroring.
111  * See kerneldoc chapter "Plane Composition Properties" for more details.
112  *
113  * This define is provided as a convenience, looking up the property id
114  * using the name->prop id lookup is the preferred method.
115  */
116 #define DRM_MODE_REFLECT_X      (1<<4)
117 #define DRM_MODE_REFLECT_Y      (1<<5)
118 
119 /*
120  * DRM_MODE_REFLECT_MASK
121  *
122  * Bitmask used to look for drm plane reflections.
123  */
124 #define DRM_MODE_REFLECT_MASK (\
125 		DRM_MODE_REFLECT_X | \
126 		DRM_MODE_REFLECT_Y)
127 
128 #define DRM_MODE_CONNECTOR_Unknown	0
129 #define DRM_MODE_CONNECTOR_VGA		1
130 #define DRM_MODE_CONNECTOR_DVII		2
131 #define DRM_MODE_CONNECTOR_DVID		3
132 #define DRM_MODE_CONNECTOR_DVIA		4
133 #define DRM_MODE_CONNECTOR_Composite	5
134 #define DRM_MODE_CONNECTOR_SVIDEO	6
135 #define DRM_MODE_CONNECTOR_LVDS		7
136 #define DRM_MODE_CONNECTOR_Component	8
137 #define DRM_MODE_CONNECTOR_9PinDIN	9
138 #define DRM_MODE_CONNECTOR_DisplayPort	10
139 #define DRM_MODE_CONNECTOR_HDMIA	11
140 #define DRM_MODE_CONNECTOR_HDMIB	12
141 #define DRM_MODE_CONNECTOR_TV		13
142 #define DRM_MODE_CONNECTOR_eDP		14
143 #define DRM_MODE_CONNECTOR_VIRTUAL      15
144 #define DRM_MODE_CONNECTOR_DSI		16
145 #define DRM_MODE_CONNECTOR_DPI		17
146 
147 #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
148 #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
149 #define DRM_EDID_PT_SEPARATE_SYNC  (3 << 3)
150 #define DRM_EDID_PT_STEREO         (1 << 5)
151 #define DRM_EDID_PT_INTERLACED     (1 << 7)
152 
153 /* see also http://vektor.theorem.ca/graphics/ycbcr/ */
154 enum v4l2_colorspace {
155 	/*
156 	 * Default colorspace, i.e. let the driver figure it out.
157 	 * Can only be used with video capture.
158 	 */
159 	V4L2_COLORSPACE_DEFAULT       = 0,
160 
161 	/* SMPTE 170M: used for broadcast NTSC/PAL SDTV */
162 	V4L2_COLORSPACE_SMPTE170M     = 1,
163 
164 	/* Obsolete pre-1998 SMPTE 240M HDTV standard, superseded by Rec 709 */
165 	V4L2_COLORSPACE_SMPTE240M     = 2,
166 
167 	/* Rec.709: used for HDTV */
168 	V4L2_COLORSPACE_REC709        = 3,
169 
170 	/*
171 	 * Deprecated, do not use. No driver will ever return this. This was
172 	 * based on a misunderstanding of the bt878 datasheet.
173 	 */
174 	V4L2_COLORSPACE_BT878         = 4,
175 
176 	/*
177 	 * NTSC 1953 colorspace. This only makes sense when dealing with
178 	 * really, really old NTSC recordings. Superseded by SMPTE 170M.
179 	 */
180 	V4L2_COLORSPACE_470_SYSTEM_M  = 5,
181 
182 	/*
183 	 * EBU Tech 3213 PAL/SECAM colorspace. This only makes sense when
184 	 * dealing with really old PAL/SECAM recordings. Superseded by
185 	 * SMPTE 170M.
186 	 */
187 	V4L2_COLORSPACE_470_SYSTEM_BG = 6,
188 
189 	/*
190 	 * Effectively shorthand for V4L2_COLORSPACE_SRGB, V4L2_YCBCR_ENC_601
191 	 * and V4L2_QUANTIZATION_FULL_RANGE. To be used for (Motion-)JPEG.
192 	 */
193 	V4L2_COLORSPACE_JPEG          = 7,
194 
195 	/* For RGB colorspaces such as produces by most webcams. */
196 	V4L2_COLORSPACE_SRGB          = 8,
197 
198 	/* AdobeRGB colorspace */
199 	V4L2_COLORSPACE_ADOBERGB      = 9,
200 
201 	/* BT.2020 colorspace, used for UHDTV. */
202 	V4L2_COLORSPACE_BT2020        = 10,
203 
204 	/* Raw colorspace: for RAW unprocessed images */
205 	V4L2_COLORSPACE_RAW           = 11,
206 
207 	/* DCI-P3 colorspace, used by cinema projectors */
208 	V4L2_COLORSPACE_DCI_P3        = 12,
209 };
210 
211 #define CRTC_INTERLACE_HALVE_V	(1 << 0) /* halve V values for interlacing */
212 #define CRTC_STEREO_DOUBLE	(1 << 1) /* adjust timings for stereo modes */
213 #define CRTC_NO_DBLSCAN		(1 << 2) /* don't adjust doublescan */
214 #define CRTC_NO_VSCAN		(1 << 3) /* don't adjust doublescan */
215 #define CRTC_STEREO_DOUBLE_ONLY	(CRTC_STEREO_DOUBLE | CRTC_NO_DBLSCAN | \
216 				 CRTC_NO_VSCAN)
217 
218 #define DRM_MODE_FLAG_3D_MAX	DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF
219 
220 #define DRM_MODE_MATCH_TIMINGS		(1 << 0)
221 #define DRM_MODE_MATCH_CLOCK		(1 << 1)
222 #define DRM_MODE_MATCH_FLAGS		(1 << 2)
223 #define DRM_MODE_MATCH_3D_FLAGS		(1 << 3)
224 #define DRM_MODE_MATCH_ASPECT_RATIO	(1 << 4)
225 
226 struct drm_display_mode {
227 	/* Proposed mode values */
228 	int clock;		/* in kHz */
229 	int hdisplay;
230 	int hsync_start;
231 	int hsync_end;
232 	int htotal;
233 	int vdisplay;
234 	int vsync_start;
235 	int vsync_end;
236 	int vtotal;
237 	int vrefresh;
238 	int vscan;
239 	unsigned int flags;
240 	int picture_aspect_ratio;
241 	int hskew;
242 	unsigned int type;
243 	/* Actual mode we give to hw */
244 	int crtc_clock;         /* in KHz */
245 	int crtc_hdisplay;
246 	int crtc_hblank_start;
247 	int crtc_hblank_end;
248 	int crtc_hsync_start;
249 	int crtc_hsync_end;
250 	int crtc_htotal;
251 	int crtc_hskew;
252 	int crtc_vdisplay;
253 	int crtc_vblank_start;
254 	int crtc_vblank_end;
255 	int crtc_vsync_start;
256 	int crtc_vsync_end;
257 	int crtc_vtotal;
258 	bool invalid;
259 };
260 
261 /**
262  * enum drm_mode_status - hardware support status of a mode
263  * @MODE_OK: Mode OK
264  * @MODE_HSYNC: hsync out of range
265  * @MODE_VSYNC: vsync out of range
266  * @MODE_H_ILLEGAL: mode has illegal horizontal timings
267  * @MODE_V_ILLEGAL: mode has illegal vertical timings
268  * @MODE_BAD_WIDTH: requires an unsupported linepitch
269  * @MODE_NOMODE: no mode with a matching name
270  * @MODE_NO_INTERLACE: interlaced mode not supported
271  * @MODE_NO_DBLESCAN: doublescan mode not supported
272  * @MODE_NO_VSCAN: multiscan mode not supported
273  * @MODE_MEM: insufficient video memory
274  * @MODE_VIRTUAL_X: mode width too large for specified virtual size
275  * @MODE_VIRTUAL_Y: mode height too large for specified virtual size
276  * @MODE_MEM_VIRT: insufficient video memory given virtual size
277  * @MODE_NOCLOCK: no fixed clock available
278  * @MODE_CLOCK_HIGH: clock required is too high
279  * @MODE_CLOCK_LOW: clock required is too low
280  * @MODE_CLOCK_RANGE: clock/mode isn't in a ClockRange
281  * @MODE_BAD_HVALUE: horizontal timing was out of range
282  * @MODE_BAD_VVALUE: vertical timing was out of range
283  * @MODE_BAD_VSCAN: VScan value out of range
284  * @MODE_HSYNC_NARROW: horizontal sync too narrow
285  * @MODE_HSYNC_WIDE: horizontal sync too wide
286  * @MODE_HBLANK_NARROW: horizontal blanking too narrow
287  * @MODE_HBLANK_WIDE: horizontal blanking too wide
288  * @MODE_VSYNC_NARROW: vertical sync too narrow
289  * @MODE_VSYNC_WIDE: vertical sync too wide
290  * @MODE_VBLANK_NARROW: vertical blanking too narrow
291  * @MODE_VBLANK_WIDE: vertical blanking too wide
292  * @MODE_PANEL: exceeds panel dimensions
293  * @MODE_INTERLACE_WIDTH: width too large for interlaced mode
294  * @MODE_ONE_WIDTH: only one width is supported
295  * @MODE_ONE_HEIGHT: only one height is supported
296  * @MODE_ONE_SIZE: only one resolution is supported
297  * @MODE_NO_REDUCED: monitor doesn't accept reduced blanking
298  * @MODE_NO_STEREO: stereo modes not supported
299  * @MODE_NO_420: ycbcr 420 modes not supported
300  * @MODE_STALE: mode has become stale
301  * @MODE_BAD: unspecified reason
302  * @MODE_ERROR: error condition
303  *
304  * This enum is used to filter out modes not supported by the driver/hardware
305  * combination.
306  */
307 enum drm_mode_status {
308 	MODE_OK = 0,
309 	MODE_HSYNC,
310 	MODE_VSYNC,
311 	MODE_H_ILLEGAL,
312 	MODE_V_ILLEGAL,
313 	MODE_BAD_WIDTH,
314 	MODE_NOMODE,
315 	MODE_NO_INTERLACE,
316 	MODE_NO_DBLESCAN,
317 	MODE_NO_VSCAN,
318 	MODE_MEM,
319 	MODE_VIRTUAL_X,
320 	MODE_VIRTUAL_Y,
321 	MODE_MEM_VIRT,
322 	MODE_NOCLOCK,
323 	MODE_CLOCK_HIGH,
324 	MODE_CLOCK_LOW,
325 	MODE_CLOCK_RANGE,
326 	MODE_BAD_HVALUE,
327 	MODE_BAD_VVALUE,
328 	MODE_BAD_VSCAN,
329 	MODE_HSYNC_NARROW,
330 	MODE_HSYNC_WIDE,
331 	MODE_HBLANK_NARROW,
332 	MODE_HBLANK_WIDE,
333 	MODE_VSYNC_NARROW,
334 	MODE_VSYNC_WIDE,
335 	MODE_VBLANK_NARROW,
336 	MODE_VBLANK_WIDE,
337 	MODE_PANEL,
338 	MODE_INTERLACE_WIDTH,
339 	MODE_ONE_WIDTH,
340 	MODE_ONE_HEIGHT,
341 	MODE_ONE_SIZE,
342 	MODE_NO_REDUCED,
343 	MODE_NO_STEREO,
344 	MODE_NO_420,
345 	MODE_STALE = -3,
346 	MODE_BAD = -2,
347 	MODE_ERROR = -1
348 };
349 
350 /*
351  * Subsystem independent description of a videomode.
352  * Can be generated from struct display_timing.
353  */
354 struct videomode {
355 	unsigned long pixelclock;	/* pixelclock in Hz */
356 
357 	u32 hactive;
358 	u32 hfront_porch;
359 	u32 hback_porch;
360 	u32 hsync_len;
361 
362 	u32 vactive;
363 	u32 vfront_porch;
364 	u32 vback_porch;
365 	u32 vsync_len;
366 
367 	enum display_flags flags; /* display flags */
368 };
369 
370 struct drm_display_mode *drm_mode_create(void);
371 void drm_mode_copy(struct drm_display_mode *dst,
372 		   const struct drm_display_mode *src);
373 void drm_mode_destroy(struct drm_display_mode *mode);
374 bool drm_mode_match(const struct drm_display_mode *mode1,
375 		    const struct drm_display_mode *mode2,
376 		    unsigned int match_flags);
377 bool drm_mode_equal(const struct drm_display_mode *mode1,
378 		    const struct drm_display_mode *mode2);
379 void drm_display_mode_from_videomode(const struct videomode *vm,
380 				     struct drm_display_mode *dmode);
381 void drm_display_mode_to_videomode(const struct drm_display_mode *dmode,
382 				   struct videomode *vm);
383 
384 #endif
385