1 /* 2 * Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef XPU3_H 8 #define XPU3_H 9 10 #include <stdbool.h> 11 #include <stddef.h> 12 #include <stdint.h> 13 14 #define MSA_DOMAIN QAD0_NS_DOMAIN 15 #define SPU_DOMAIN QAD1_NS_DOMAIN 16 17 #define XPU_ERR_SEC_CTX 0 18 #define XPU_ERR_NON_SEC_CTX 1 19 #define XPU3_RGn_GCR0_RG_SEC_SHIFT 0x8 20 21 #define XPU_RG_ALL 0x00ffffff 22 #define XPU_UMR_RG (XPU_RG_ALL - 1) 23 24 #define XPU_PROTECTION_STATIC 0x1 25 26 enum xpu { 27 XPU_TYPE_NONE, 28 XPU_TYPE_IPA_0_GSI_TOP, 29 XPU_TYPE_SEC_CTRL_APU, 30 XPU_TYPE_ANOC1_MPU, 31 XPU_TYPE_ANOC2_MPU, 32 XPU_TYPE_BIMC_MPU0, 33 XPU_TYPE_MSS_NAV_MPU, 34 XPU_TYPE_LLCC_BROADCAST_MPU, 35 XPU_TYPE_AOSS_MPU, 36 XPU_TYPE_GEMNOC_MS_MPU, 37 XPU_TYPE_BOOT_ROM, 38 XPU_TYPE_IMEM_MPU, 39 XPU_TYPE_CNOC_SNOC_MPU, 40 XPU_TYPE_MSS_Q6_MPU, 41 XPU_TYPE_MSS_MPU, 42 XPU_TYPE_BIMC_MPU1, 43 XPU_TYPE_DC_NOC_NON_BROADCAST_MPU, 44 XPU_TYPE_DC_NOC_SHRM_MPU, 45 XPU_TYPE_PKA_APU, 46 XPU_TYPE_IPC_MPU, 47 XPU_TYPE_CNOC_GEMNOC_MPU, 48 XPU_TYPE_CNOC2_SS_MPU, 49 XPU_TYPE_WPSS_MPU, 50 XPU_TYPE_AOSS_CNOC_MPU, 51 XPU_TYPE_CNOC_SS_MPU, 52 XPU_TYPE_COUNT, 53 }; 54 55 enum domain_type { 56 NO_DOMAIN = 0, 57 APPS_NS_DOMAIN = BIT(0), 58 APPS_S_DOMAIN = BIT(0) | BIT(XPU3_RGn_GCR0_RG_SEC_SHIFT), 59 QAD0_NS_DOMAIN = BIT(1), 60 QAD1_NS_DOMAIN = BIT(2), 61 }; 62 63 enum device_type { 64 DEVICE_MODEM = 30, 65 DEVICE_MSS_NAV = 35, 66 }; 67 68 struct rg_domain_ownership { 69 uint32_t rg_num; 70 enum domain_type owner_domain; 71 uint32_t perm_r; 72 uint32_t perm_w; 73 }; 74 75 struct rg_partition_range { 76 uint32_t rg_num; 77 uintptr_t start_addr; 78 uintptr_t end_addr; 79 }; 80 81 struct xpu_instance { 82 uintptr_t xpu_base_addr; 83 uint64_t owner_arr_size; 84 struct rg_domain_ownership *rg_owner; 85 uint64_t part_range_arr_size; 86 struct rg_partition_range *partition_range; 87 enum xpu xpu_id; 88 uint32_t flag; 89 }; 90 91 struct mpu_ranges { 92 const enum device_type device; 93 uint8_t mpus_count; 94 uint16_t device_prtn_cnt; 95 struct xpu_instance *mpus; 96 }; 97 98 struct xpu_err_pos_to_hal_map { 99 uint32_t bit_mask; 100 uint8_t xpu; 101 }; 102 103 struct xpu_intr_reg_dtls { 104 uintptr_t xpu_intr_reg_addr; 105 uintptr_t xpu_intr_reg_mask; 106 }; 107 108 struct xpu_base_addr_info { 109 enum xpu e_xpu; 110 uintptr_t base_addr; 111 char *name; 112 }; 113 114 void xpu_lock_down_assets(struct xpu_instance *xpus, uint8_t xpu_count); 115 int xpu_lock_down_assets_dynamic(struct xpu_instance *xpus, uint8_t xpu_count, 116 uint32_t xpu_id, uint32_t rg_num, 117 uint32_t perm_r, uint32_t perm_w); 118 void xpu_master_mpu_init(struct mpu_ranges *msm_mpu_ranges, 119 const uint32_t msm_mpu_ranges_count); 120 121 void xpu_print_log(void *ctx); 122 123 #endif /* XPU3_H */ 124