1 /*
2 * Copyright 2020-2022,2025-2026 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef DDR_INIT_H
8 #define DDR_INIT_H
9
10 #include <stdlib.h>
11 #include <string.h>
12 #include "ddr_utils.h"
13
14 #define APBONLY_MICRORESET 0x40380420U
15 #define MASTER_PLLCTRL1 0x403816F0U
16 #define MASTER_PLLTESTMODE 0x40381708U
17 #define MASTER_PLLCTRL4 0x4038171CU
18 #define MASTER_PLLCTRL2 0x403816DCU
19
20 #define MASTER_CALOFFSET 0x40381514U
21 #define MASTER_CALMISC2 0x40381660U
22
23 #define CALDRV 0x9U
24 #define CALDRV_OFFSET 0x6U
25 #define CALDRV2_OFFSET 0xAU
26 #define CALDRV_MASK 0x3FC0U
27
28 #define CALMISC2 0x1U
29 #define CALMISC2_OFFSET 0xDU
30
31 #define MICROCONT_MUX_SEL 0x40380400U
32 #define LOCK_CSR_ACCESS 0x00000001U
33 #define UNLOCK_CSR_ACCESS 0x00000000U
34
35 #define APBONLY_RESET_TO_MICRO_MASK 0x00000008U
36 #define APBONLY_STALL_TO_MICRO_MASK 0x00000001U
37 #define APBONLY_RESET_STALL_MASK APBONLY_RESET_TO_MICRO_MASK | \
38 APBONLY_STALL_TO_MICRO_MASK
39 #define APBONLY_MICRORESET_CLR_MASK 0x00000000U
40
41 #define PLLCTRL1_VALUE 0x00000021U
42 #define PLLTESTMODE_VALUE 0x00000024U
43 #define PLLCTRL4_VALUE 0x0000017FU
44
pllctrl2_value(uint16_t freq)45 static inline uint32_t pllctrl2_value(uint16_t freq)
46 {
47 if (freq < 469U) {
48 return 0x7U;
49 } else if (freq < 625U) {
50 return 0x6U;
51 } else if (freq <= 937U) {
52 return 0xbU;
53 } else if (freq < 1250U) {
54 return 0xaU;
55 } else {
56 return 0x19U;
57 }
58 }
59
60 /* Enum for DRAM Type */
61 enum dram_type {
62 DDR3L = 1,
63 LPDDR4
64 };
65
66 struct regconf {
67 uint32_t addr;
68 uint32_t data;
69 };
70
71 struct regconf_16 {
72 uint32_t addr;
73 uint16_t data;
74 } __packed;
75
76 struct dqconf {
77 uint32_t addr;
78 uint8_t data;
79 } __packed;
80
81 struct ddrss_config {
82 uint8_t memory_type;
83 uint16_t frequency;
84 struct regconf *ddrc;
85 size_t ddrc_size;
86 struct dqconf *dq_swap;
87 size_t dq_swap_size;
88 struct regconf_16 *phy;
89 size_t phy_size;
90 struct regconf_16 *pie;
91 size_t pie_size;
92 uint16_t *imem_1d;
93 size_t imem_1d_size;
94 uint16_t *dmem_1d;
95 size_t dmem_1d_size;
96 uint16_t *imem_2d;
97 size_t imem_2d_size;
98 uint16_t *dmem_2d;
99 size_t dmem_2d_size;
100 uint32_t *phy_csr;
101 size_t phy_csr_size;
102 uint32_t *ddrc_csr;
103 size_t ddrc_csr_size;
104 };
105
106 struct ddr_fw_header {
107 uint8_t header_version;
108 char ddrt_version[8];
109 char soc_name[16];
110 char fw_version[16];
111 char reserved[23];
112 };
113
114 struct ddr_fw_layout {
115 uint8_t memory_type;
116 uint16_t frequency;
117 uint16_t ddrc_size;
118 uint16_t dq_swap_size;
119 uint16_t phy_size;
120 uint16_t pie_size;
121 uint16_t imem_1d_size;
122 uint16_t dmem_1d_size;
123 uint16_t imem_2d_size;
124 uint16_t dmem_2d_size;
125 uint16_t phy_csr_size;
126 uint16_t ddrc_csr_size;
127 uint32_t ddrc_offset;
128 uint32_t dq_swap_offset;
129 uint32_t phy_offset;
130 uint32_t pie_offset;
131 uint32_t imem_1d_offset;
132 uint32_t dmem_1d_offset;
133 uint32_t imem_2d_offset;
134 uint32_t dmem_2d_offset;
135 uint32_t phy_csr_offset;
136 uint32_t ddrc_csr_offset;
137 };
138
139 uint32_t ddr_init_cfg(const struct ddrss_config *config);
140
141 /*
142 * Full initialization of DDR SubSystem.
143 * @param load_from - memory address from where imem/dmem binary will be loaded.
144 * @return - error code, 0 if init succeeds, non-zero on error.
145 */
146 uint32_t ddr_init(uintptr_t load_from);
147
148 /*
149 * Map DDR-related memory regions before DDR initialization.
150 *
151 * @return - error code, 0 if succeeds, non-zero on error.
152 */
153 int plat_ddr_mmap_setup(void);
154
155 /*
156 * Writes the data associated for each address.
157 *
158 * @param size - size of the array, number of elements
159 * @param cfg - array of configuration elements
160 * @return - error code, 0 if init succeeds, non-zero on error.
161 */
162 uint32_t load_register_cfg(size_t size, const struct regconf cfg[]);
163
164 /*
165 * Writes the data associated for each address. Similar to
166 * @load_register_cfg but uses 16bit data elements for memory
167 * usage optimization.
168 *
169 * @param size - size of the array, number of elements
170 * @param cfg - array of configuration elements
171 * @return - error code, 0 if init succeeds, non-zero on error.
172 */
173 uint32_t load_register_cfg_16(size_t size, const struct regconf_16 cfg[]);
174
175 /*
176 * Writes the data associated for each address. Similar to
177 * @load_register_cfg but uses 8bit data elements for memory
178 * usage optimization.
179 *
180 * @param size - size of the array, number of elements
181 * @param cfg - array of configuration elements
182 * @return - error code, 0 if init succeeds, non-zero on error.
183 */
184 uint32_t load_dq_cfg(size_t size, const struct dqconf cfg[]);
185
186 /*
187 * Updates PHY internal PLL settings.
188 * @param frequency - selected DDR frequency
189 */
190 void set_optimal_pll(uint16_t frequency);
191
192 #endif /* DDR_INIT_H */
193