1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 *
19 ******************************************************************************/
20 #define _HAL_INIT_C_
21
22 #include <drv_types.h>
23 #include <rtl8188e_hal.h>
24
25
26 #if defined(CONFIG_IOL)
iol_mode_enable(PADAPTER padapter,u8 enable)27 static void iol_mode_enable(PADAPTER padapter, u8 enable)
28 {
29 u8 reg_0xf0 = 0;
30
31 if(enable)
32 {
33 //Enable initial offload
34 reg_0xf0 = rtw_read8(padapter, REG_SYS_CFG);
35 //DBG_871X("%s reg_0xf0:0x%02x, write 0x%02x\n", __FUNCTION__, reg_0xf0, reg_0xf0|SW_OFFLOAD_EN);
36 rtw_write8(padapter, REG_SYS_CFG, reg_0xf0|SW_OFFLOAD_EN);
37
38 if(padapter->bFWReady == _FALSE)
39 {
40 printk("bFWReady == _FALSE call reset 8051...\n");
41 _8051Reset88E(padapter);
42 }
43
44 }
45 else
46 {
47 //disable initial offload
48 reg_0xf0 = rtw_read8(padapter, REG_SYS_CFG);
49 //DBG_871X("%s reg_0xf0:0x%02x, write 0x%02x\n", __FUNCTION__, reg_0xf0, reg_0xf0& ~SW_OFFLOAD_EN);
50 rtw_write8(padapter, REG_SYS_CFG, reg_0xf0 & ~SW_OFFLOAD_EN);
51 }
52 }
53
iol_execute(PADAPTER padapter,u8 control)54 static s32 iol_execute(PADAPTER padapter, u8 control)
55 {
56 s32 status = _FAIL;
57 u8 reg_0x88 = 0,reg_1c7=0;
58 u32 start = 0, passing_time = 0;
59
60 u32 t1,t2;
61 control = control&0x0f;
62 reg_0x88 = rtw_read8(padapter, REG_HMEBOX_E0);
63 //DBG_871X("%s reg_0x88:0x%02x, write 0x%02x\n", __FUNCTION__, reg_0x88, reg_0x88|control);
64 rtw_write8(padapter, REG_HMEBOX_E0, reg_0x88|control);
65
66 t1 = start = rtw_get_current_time();
67 while(
68 //(reg_1c7 = rtw_read8(padapter, 0x1c7) >1) &&
69 (reg_0x88=rtw_read8(padapter, REG_HMEBOX_E0)) & control
70 && (passing_time=rtw_get_passing_time_ms(start))<1000
71 ) {
72 //DBG_871X("%s polling reg_0x88:0x%02x,reg_0x1c7:0x%02x\n", __FUNCTION__, reg_0x88,rtw_read8(padapter, 0x1c7) );
73 //rtw_udelay_os(100);
74 }
75
76 reg_0x88 = rtw_read8(padapter, REG_HMEBOX_E0);
77 status = (reg_0x88 & control)?_FAIL:_SUCCESS;
78 if(reg_0x88 & control<<4)
79 status = _FAIL;
80 t2= rtw_get_current_time();
81 //printk("==> step iol_execute : %5u reg-0x1c0= 0x%02x\n",rtw_get_time_interval_ms(t1,t2),rtw_read8(padapter, 0x1c0));
82 //DBG_871X("%s in %u ms, reg_0x88:0x%02x\n", __FUNCTION__, passing_time, reg_0x88);
83
84 return status;
85 }
86
iol_InitLLTTable(PADAPTER padapter,u8 txpktbuf_bndy)87 static s32 iol_InitLLTTable(
88 PADAPTER padapter,
89 u8 txpktbuf_bndy
90 )
91 {
92 s32 rst = _SUCCESS;
93 iol_mode_enable(padapter, 1);
94 //DBG_871X("%s txpktbuf_bndy:%u\n", __FUNCTION__, txpktbuf_bndy);
95 rtw_write8(padapter, REG_TDECTRL+1, txpktbuf_bndy);
96 rst = iol_execute(padapter, CMD_INIT_LLT);
97 iol_mode_enable(padapter, 0);
98 return rst;
99 }
100
101 static VOID
efuse_phymap_to_logical(u8 * phymap,u16 _offset,u16 _size_byte,u8 * pbuf)102 efuse_phymap_to_logical(u8 * phymap, u16 _offset, u16 _size_byte, u8 *pbuf)
103 {
104 u8 *efuseTbl = NULL;
105 u8 rtemp8;
106 u16 eFuse_Addr = 0;
107 u8 offset, wren;
108 u16 i, j;
109 u16 **eFuseWord = NULL;
110 u16 efuse_utilized = 0;
111 u8 efuse_usage = 0;
112 u8 u1temp = 0;
113
114
115 efuseTbl = (u8*)rtw_zmalloc(EFUSE_MAP_LEN_88E);
116 if(efuseTbl == NULL)
117 {
118 DBG_871X("%s: alloc efuseTbl fail!\n", __FUNCTION__);
119 goto exit;
120 }
121
122 eFuseWord= (u16 **)rtw_malloc2d(EFUSE_MAX_SECTION_88E, EFUSE_MAX_WORD_UNIT, 2);
123 if(eFuseWord == NULL)
124 {
125 DBG_871X("%s: alloc eFuseWord fail!\n", __FUNCTION__);
126 goto exit;
127 }
128
129 // 0. Refresh efuse init map as all oxFF.
130 for (i = 0; i < EFUSE_MAX_SECTION_88E; i++)
131 for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++)
132 eFuseWord[i][j] = 0xFFFF;
133
134 //
135 // 1. Read the first byte to check if efuse is empty!!!
136 //
137 //
138 rtemp8 = *(phymap+eFuse_Addr);
139 if(rtemp8 != 0xFF)
140 {
141 efuse_utilized++;
142 //printk("efuse_Addr-%d efuse_data=%x\n", eFuse_Addr, *rtemp8);
143 eFuse_Addr++;
144 }
145 else
146 {
147 DBG_871X("EFUSE is empty efuse_Addr-%d efuse_data=%x\n", eFuse_Addr, rtemp8);
148 goto exit;
149 }
150
151
152 //
153 // 2. Read real efuse content. Filter PG header and every section data.
154 //
155 while((rtemp8 != 0xFF) && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E))
156 {
157 //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("efuse_Addr-%d efuse_data=%x\n", eFuse_Addr-1, *rtemp8));
158
159 // Check PG header for section num.
160 if((rtemp8 & 0x1F ) == 0x0F) //extended header
161 {
162 u1temp =( (rtemp8 & 0xE0) >> 5);
163 //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header u1temp=%x *rtemp&0xE0 0x%x\n", u1temp, *rtemp8 & 0xE0));
164
165 //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header u1temp=%x \n", u1temp));
166
167 rtemp8 = *(phymap+eFuse_Addr);
168
169 //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header efuse_Addr-%d efuse_data=%x\n", eFuse_Addr, *rtemp8));
170
171 if((rtemp8 & 0x0F) == 0x0F)
172 {
173 eFuse_Addr++;
174 rtemp8 = *(phymap+eFuse_Addr);
175
176 if(rtemp8 != 0xFF && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E))
177 {
178 eFuse_Addr++;
179 }
180 continue;
181 }
182 else
183 {
184 offset = ((rtemp8 & 0xF0) >> 1) | u1temp;
185 wren = (rtemp8 & 0x0F);
186 eFuse_Addr++;
187 }
188 }
189 else
190 {
191 offset = ((rtemp8 >> 4) & 0x0f);
192 wren = (rtemp8 & 0x0f);
193 }
194
195 if(offset < EFUSE_MAX_SECTION_88E)
196 {
197 // Get word enable value from PG header
198 //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Offset-%d Worden=%x\n", offset, wren));
199
200 for(i=0; i<EFUSE_MAX_WORD_UNIT; i++)
201 {
202 // Check word enable condition in the section
203 if(!(wren & 0x01))
204 {
205 //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d \n", eFuse_Addr));
206 rtemp8 = *(phymap+eFuse_Addr);
207 eFuse_Addr++;
208 //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Data=0x%x\n", *rtemp8));
209 efuse_utilized++;
210 eFuseWord[offset][i] = (rtemp8 & 0xff);
211
212
213 if(eFuse_Addr >= EFUSE_REAL_CONTENT_LEN_88E)
214 break;
215
216 //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d", eFuse_Addr));
217 rtemp8 = *(phymap+eFuse_Addr);
218 eFuse_Addr++;
219 //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Data=0x%x\n", *rtemp8));
220
221 efuse_utilized++;
222 eFuseWord[offset][i] |= (((u2Byte)rtemp8 << 8) & 0xff00);
223
224 if(eFuse_Addr >= EFUSE_REAL_CONTENT_LEN_88E)
225 break;
226 }
227
228 wren >>= 1;
229
230 }
231 }
232
233 // Read next PG header
234 rtemp8 = *(phymap+eFuse_Addr);
235 //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d rtemp 0x%x\n", eFuse_Addr, *rtemp8));
236
237 if(rtemp8 != 0xFF && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E))
238 {
239 efuse_utilized++;
240 eFuse_Addr++;
241 }
242 }
243
244 //
245 // 3. Collect 16 sections and 4 word unit into Efuse map.
246 //
247 for(i=0; i<EFUSE_MAX_SECTION_88E; i++)
248 {
249 for(j=0; j<EFUSE_MAX_WORD_UNIT; j++)
250 {
251 efuseTbl[(i*8)+(j*2)]=(eFuseWord[i][j] & 0xff);
252 efuseTbl[(i*8)+((j*2)+1)]=((eFuseWord[i][j] >> 8) & 0xff);
253 }
254 }
255
256
257 //
258 // 4. Copy from Efuse map to output pointer memory!!!
259 //
260 for(i=0; i<_size_byte; i++)
261 {
262 pbuf[i] = efuseTbl[_offset+i];
263 }
264
265 //
266 // 5. Calculate Efuse utilization.
267 //
268 efuse_usage = (u1Byte)((efuse_utilized*100)/EFUSE_REAL_CONTENT_LEN_88E);
269 //rtw_hal_set_hwreg(Adapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_utilized);
270
271 exit:
272 if(efuseTbl)
273 rtw_mfree(efuseTbl, EFUSE_MAP_LEN_88E);
274
275 if(eFuseWord)
276 rtw_mfree2d((void *)eFuseWord, EFUSE_MAX_SECTION_88E, EFUSE_MAX_WORD_UNIT, sizeof(u16));
277 }
278
efuse_read_phymap_from_txpktbuf(ADAPTER * adapter,int bcnhead,u8 * content,u16 * size)279 void efuse_read_phymap_from_txpktbuf(
280 ADAPTER *adapter,
281 int bcnhead, //beacon head, where FW store len(2-byte) and efuse physical map.
282 u8 *content, //buffer to store efuse physical map
283 u16 *size //for efuse content: the max byte to read. will update to byte read
284 )
285 {
286 u16 dbg_addr = 0;
287 u32 start = 0, passing_time = 0;
288 u8 reg_0x143 = 0;
289 u8 reg_0x106 = 0;
290 u32 lo32 = 0, hi32 = 0;
291 u16 len = 0, count = 0;
292 int i = 0;
293 u16 limit = *size;
294
295 u8 *pos = content;
296
297 if(bcnhead<0) //if not valid
298 bcnhead = rtw_read8(adapter, REG_TDECTRL+1);
299
300 DBG_871X("%s bcnhead:%d\n", __FUNCTION__, bcnhead);
301
302 //reg_0x106 = rtw_read8(adapter, REG_PKT_BUFF_ACCESS_CTRL);
303 //DBG_871X("%s reg_0x106:0x%02x, write 0x%02x\n", __FUNCTION__, reg_0x106, 0x69);
304 rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, TXPKT_BUF_SELECT);
305 //DBG_871X("%s reg_0x106:0x%02x\n", __FUNCTION__, rtw_read8(adapter, 0x106));
306
307 dbg_addr = bcnhead*128/8; //8-bytes addressing
308
309 while(1)
310 {
311 //DBG_871X("%s dbg_addr:0x%x\n", __FUNCTION__, dbg_addr+i);
312 rtw_write16(adapter, REG_PKTBUF_DBG_ADDR, dbg_addr+i);
313
314 //DBG_871X("%s write reg_0x143:0x00\n", __FUNCTION__);
315 rtw_write8(adapter, REG_TXPKTBUF_DBG, 0);
316 start = rtw_get_current_time();
317 while(!(reg_0x143=rtw_read8(adapter, REG_TXPKTBUF_DBG))//dbg
318 //while(rtw_read8(adapter, REG_TXPKTBUF_DBG) & BIT0
319 && (passing_time=rtw_get_passing_time_ms(start))<1000
320 ) {
321 DBG_871X("%s polling reg_0x143:0x%02x, reg_0x106:0x%02x\n", __FUNCTION__, reg_0x143, rtw_read8(adapter, 0x106));
322 rtw_usleep_os(100);
323 }
324
325
326 lo32 = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_L);
327 hi32 = rtw_read32(adapter, REG_PKTBUF_DBG_DATA_H);
328
329 #if 0
330 DBG_871X("%s lo32:0x%08x, %02x %02x %02x %02x\n", __FUNCTION__, lo32
331 , rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L)
332 , rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L+1)
333 , rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L+2)
334 , rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L+3)
335 );
336 DBG_871X("%s hi32:0x%08x, %02x %02x %02x %02x\n", __FUNCTION__, hi32
337 , rtw_read8(adapter, REG_PKTBUF_DBG_DATA_H)
338 , rtw_read8(adapter, REG_PKTBUF_DBG_DATA_H+1)
339 , rtw_read8(adapter, REG_PKTBUF_DBG_DATA_H+2)
340 , rtw_read8(adapter, REG_PKTBUF_DBG_DATA_H+3)
341 );
342 #endif
343
344 if(i==0)
345 {
346 #if 1 //for debug
347 u8 lenc[2];
348 u16 lenbak, aaabak;
349 u16 aaa;
350 lenc[0] = rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L);
351 lenc[1] = rtw_read8(adapter, REG_PKTBUF_DBG_DATA_L+1);
352
353 aaabak = le16_to_cpup((u16*)lenc);
354 lenbak = le16_to_cpu(*((u16*)lenc));
355 aaa = le16_to_cpup((u16*)&lo32);
356 #endif
357 len = le16_to_cpu(*((u16*)&lo32));
358
359 limit = (len-2<limit)?len-2:limit;
360
361 DBG_871X("%s len:%u, lenbak:%u, aaa:%u, aaabak:%u\n", __FUNCTION__, len, lenbak, aaa, aaabak);
362
363 _rtw_memcpy(pos, ((u8*)&lo32)+2, (limit>=count+2)?2:limit-count);
364 count+= (limit>=count+2)?2:limit-count;
365 pos=content+count;
366
367 }
368 else
369 {
370 _rtw_memcpy(pos, ((u8*)&lo32), (limit>=count+4)?4:limit-count);
371 count+=(limit>=count+4)?4:limit-count;
372 pos=content+count;
373
374
375 }
376
377 if(limit>count && len-2>count) {
378 _rtw_memcpy(pos, (u8*)&hi32, (limit>=count+4)?4:limit-count);
379 count+=(limit>=count+4)?4:limit-count;
380 pos=content+count;
381 }
382
383 if(limit<=count || len-2<=count)
384 break;
385
386 i++;
387 }
388
389 rtw_write8(adapter, REG_PKT_BUFF_ACCESS_CTRL, DISABLE_TRXPKT_BUF_ACCESS);
390
391 DBG_871X("%s read count:%u\n", __FUNCTION__, count);
392 *size = count;
393
394 }
395
396
iol_read_efuse(PADAPTER padapter,u8 txpktbuf_bndy,u16 offset,u16 size_byte,u8 * logical_map)397 static s32 iol_read_efuse(
398 PADAPTER padapter,
399 u8 txpktbuf_bndy,
400 u16 offset,
401 u16 size_byte,
402 u8 *logical_map
403 )
404 {
405 s32 status = _FAIL;
406 u8 reg_0x106 = 0;
407 u8 physical_map[512];
408 u16 size = 512;
409 int i;
410
411
412 rtw_write8(padapter, REG_TDECTRL+1, txpktbuf_bndy);
413 _rtw_memset(physical_map, 0xFF, 512);
414
415 ///reg_0x106 = rtw_read8(padapter, REG_PKT_BUFF_ACCESS_CTRL);
416 //DBG_871X("%s reg_0x106:0x%02x, write 0x%02x\n", __FUNCTION__, reg_0x106, 0x69);
417 rtw_write8(padapter, REG_PKT_BUFF_ACCESS_CTRL, TXPKT_BUF_SELECT);
418 //DBG_871X("%s reg_0x106:0x%02x\n", __FUNCTION__, rtw_read8(padapter, 0x106));
419
420 status = iol_execute(padapter, CMD_READ_EFUSE_MAP);
421
422 if(status == _SUCCESS)
423 efuse_read_phymap_from_txpktbuf(padapter, txpktbuf_bndy, physical_map, &size);
424
425 #if 0
426 DBG_871X_LEVEL(_drv_always_, "%s physical map\n", __FUNCTION__);
427 for(i=0;i<size;i++)
428 {
429 if (i%16==0)
430 DBG_871X_LEVEL(_drv_always_, "%02x", physical_map[i]);
431 else
432 _DBG_871X_LEVEL(_drv_always_, "%02x", physical_map[i]);
433
434 if (i%16==7)
435 _DBG_871X_LEVEL(_drv_always_, " ");
436 else if (i%16==15)
437 _DBG_871X_LEVEL(_drv_always_, "\n");
438 else
439 _DBG_871X_LEVEL(_drv_always_, " ");
440 }
441 _DBG_871X_LEVEL(_drv_always_, "\n");
442 #endif
443
444 efuse_phymap_to_logical(physical_map, offset, size_byte, logical_map);
445
446 return status;
447 }
448
rtl8188e_iol_efuse_patch(PADAPTER padapter)449 s32 rtl8188e_iol_efuse_patch(PADAPTER padapter)
450 {
451 s32 result = _SUCCESS;
452 printk("==> %s \n",__FUNCTION__);
453
454 if(rtw_IOL_applied(padapter)){
455 iol_mode_enable(padapter, 1);
456 result = iol_execute(padapter, CMD_READ_EFUSE_MAP);
457 if(result == _SUCCESS)
458 result = iol_execute(padapter, CMD_EFUSE_PATCH);
459
460 iol_mode_enable(padapter, 0);
461 }
462 return result;
463 }
464
iol_ioconfig(PADAPTER padapter,u8 iocfg_bndy)465 static s32 iol_ioconfig(
466 PADAPTER padapter,
467 u8 iocfg_bndy
468 )
469 {
470 s32 rst = _SUCCESS;
471
472 //DBG_871X("%s iocfg_bndy:%u\n", __FUNCTION__, iocfg_bndy);
473 rtw_write8(padapter, REG_TDECTRL+1, iocfg_bndy);
474 rst = iol_execute(padapter, CMD_IOCONFIG);
475
476 return rst;
477 }
478
rtl8188e_IOL_exec_cmds_sync(ADAPTER * adapter,struct xmit_frame * xmit_frame,u32 max_wating_ms,u32 bndy_cnt)479 int rtl8188e_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms,u32 bndy_cnt)
480 {
481
482 u32 start_time = rtw_get_current_time();
483 u32 passing_time_ms;
484 u8 polling_ret,i;
485 int ret = _FAIL;
486 u32 t1,t2;
487
488 //printk("===> %s ,bndy_cnt = %d \n",__FUNCTION__,bndy_cnt);
489 if (rtw_IOL_append_END_cmd(xmit_frame) != _SUCCESS)
490 goto exit;
491 #ifdef CONFIG_USB_HCI
492 {
493 struct pkt_attrib *pattrib = &xmit_frame->attrib;
494 if(rtw_usb_bulk_size_boundary(adapter,TXDESC_SIZE+pattrib->last_txcmdsz))
495 {
496 if (rtw_IOL_append_END_cmd(xmit_frame) != _SUCCESS)
497 goto exit;
498 }
499 }
500 #endif //CONFIG_USB_HCI
501
502 //rtw_IOL_cmd_buf_dump(adapter,xmit_frame->attrib.pktlen+TXDESC_OFFSET,xmit_frame->buf_addr);
503 //rtw_hal_mgnt_xmit(adapter, xmit_frame);
504 //rtw_dump_xframe_sync(adapter, xmit_frame);
505
506 dump_mgntframe_and_wait(adapter, xmit_frame, max_wating_ms);
507
508 t1= rtw_get_current_time();
509 iol_mode_enable(adapter, 1);
510 for(i=0;i<bndy_cnt;i++){
511 u8 page_no = 0;
512 page_no = i*2 ;
513 //printk(" i = %d, page_no = %d \n",i,page_no);
514 if( (ret = iol_ioconfig(adapter, page_no)) != _SUCCESS)
515 {
516 break;
517 }
518 }
519 iol_mode_enable(adapter, 0);
520 t2 = rtw_get_current_time();
521 //printk("==> %s : %5u\n",__FUNCTION__,rtw_get_time_interval_ms(t1,t2));
522 exit:
523 //restore BCN_HEAD
524 rtw_write8(adapter, REG_TDECTRL+1, 0);
525 return ret;
526 }
527
rtw_IOL_cmd_tx_pkt_buf_dump(ADAPTER * Adapter,int data_len)528 void rtw_IOL_cmd_tx_pkt_buf_dump(ADAPTER *Adapter,int data_len)
529 {
530 u32 fifo_data,reg_140;
531 u32 addr,rstatus,loop=0;
532
533 u16 data_cnts = (data_len/8)+1;
534 u8 *pbuf =rtw_zvmalloc(data_len+10);
535 printk("###### %s ######\n",__FUNCTION__);
536
537 rtw_write8(Adapter, REG_PKT_BUFF_ACCESS_CTRL, TXPKT_BUF_SELECT);
538 if(pbuf){
539 for(addr=0;addr< data_cnts;addr++){
540 //printk("==> addr:0x%02x\n",addr);
541 rtw_write32(Adapter,0x140,addr);
542 rtw_usleep_os(2);
543 loop=0;
544 do{
545 rstatus=(reg_140=rtw_read32(Adapter,REG_PKTBUF_DBG_CTRL)&BIT24);
546 //printk("rstatus = %02x, reg_140:0x%08x\n",rstatus,reg_140);
547 if(rstatus){
548 fifo_data = rtw_read32(Adapter,REG_PKTBUF_DBG_DATA_L);
549 //printk("fifo_data_144:0x%08x\n",fifo_data);
550 _rtw_memcpy(pbuf+(addr*8),&fifo_data , 4);
551
552 fifo_data = rtw_read32(Adapter,REG_PKTBUF_DBG_DATA_H);
553 //printk("fifo_data_148:0x%08x\n",fifo_data);
554 _rtw_memcpy(pbuf+(addr*8+4), &fifo_data, 4);
555
556 }
557 rtw_usleep_os(2);
558 }while( !rstatus && (loop++ <10));
559 }
560 rtw_IOL_cmd_buf_dump(Adapter,data_len,pbuf);
561 rtw_vmfree(pbuf, data_len+10);
562
563 }
564 printk("###### %s ######\n",__FUNCTION__);
565 }
566
567 #endif /* defined(CONFIG_IOL) */
568
569
570 static VOID
_FWDownloadEnable_8188E(IN PADAPTER padapter,IN BOOLEAN enable)571 _FWDownloadEnable_8188E(
572 IN PADAPTER padapter,
573 IN BOOLEAN enable
574 )
575 {
576 u8 tmp;
577
578 if(enable)
579 {
580 // MCU firmware download enable.
581 tmp = rtw_read8(padapter, REG_MCUFWDL);
582 rtw_write8(padapter, REG_MCUFWDL, tmp|0x01);
583
584 // 8051 reset
585 tmp = rtw_read8(padapter, REG_MCUFWDL+2);
586 rtw_write8(padapter, REG_MCUFWDL+2, tmp&0xf7);
587 }
588 else
589 {
590
591 // MCU firmware download disable.
592 tmp = rtw_read8(padapter, REG_MCUFWDL);
593 rtw_write8(padapter, REG_MCUFWDL, tmp&0xfe);
594
595 // Reserved for fw extension.
596 rtw_write8(padapter, REG_MCUFWDL+1, 0x00);
597 }
598 }
599 #define MAX_REG_BOLCK_SIZE 196
600 static int
_BlockWrite(IN PADAPTER padapter,IN PVOID buffer,IN u32 buffSize)601 _BlockWrite(
602 IN PADAPTER padapter,
603 IN PVOID buffer,
604 IN u32 buffSize
605 )
606 {
607 int ret = _SUCCESS;
608
609 u32 blockSize_p1 = 4; // (Default) Phase #1 : PCI muse use 4-byte write to download FW
610 u32 blockSize_p2 = 8; // Phase #2 : Use 8-byte, if Phase#1 use big size to write FW.
611 u32 blockSize_p3 = 1; // Phase #3 : Use 1-byte, the remnant of FW image.
612 u32 blockCount_p1 = 0, blockCount_p2 = 0, blockCount_p3 = 0;
613 u32 remainSize_p1 = 0, remainSize_p2 = 0;
614 u8 *bufferPtr = (u8*)buffer;
615 u32 i=0, offset=0;
616 #ifdef CONFIG_PCI_HCI
617 u8 remainFW[4] = {0, 0, 0, 0};
618 u8 *p = NULL;
619 #endif
620
621 #ifdef CONFIG_USB_HCI
622 blockSize_p1 = MAX_REG_BOLCK_SIZE;
623 #endif
624
625 //3 Phase #1
626 blockCount_p1 = buffSize / blockSize_p1;
627 remainSize_p1 = buffSize % blockSize_p1;
628
629 if (blockCount_p1) {
630 RT_TRACE(_module_hal_init_c_, _drv_notice_,
631 ("_BlockWrite: [P1] buffSize(%d) blockSize_p1(%d) blockCount_p1(%d) remainSize_p1(%d)\n",
632 buffSize, blockSize_p1, blockCount_p1, remainSize_p1));
633 }
634
635 for (i = 0; i < blockCount_p1; i++)
636 {
637 #ifdef CONFIG_USB_HCI
638 ret = rtw_writeN(padapter, (FW_8188E_START_ADDRESS + i * blockSize_p1), blockSize_p1, (bufferPtr + i * blockSize_p1));
639 #else
640 ret = rtw_write32(padapter, (FW_8188E_START_ADDRESS + i * blockSize_p1), le32_to_cpu(*((u32*)(bufferPtr + i * blockSize_p1))));
641 #endif
642
643 if(ret == _FAIL)
644 goto exit;
645 }
646
647 #ifdef CONFIG_PCI_HCI
648 p = (u8*)((u32*)(bufferPtr + blockCount_p1 * blockSize_p1));
649 if (remainSize_p1) {
650 switch (remainSize_p1) {
651 case 0:
652 break;
653 case 3:
654 remainFW[2]=*(p+2);
655 case 2:
656 remainFW[1]=*(p+1);
657 case 1:
658 remainFW[0]=*(p);
659 ret = rtw_write32(padapter, (FW_8188E_START_ADDRESS + blockCount_p1 * blockSize_p1),
660 le32_to_cpu(*(u32*)remainFW));
661 }
662 return ret;
663 }
664 #endif
665
666 //3 Phase #2
667 if (remainSize_p1)
668 {
669 offset = blockCount_p1 * blockSize_p1;
670
671 blockCount_p2 = remainSize_p1/blockSize_p2;
672 remainSize_p2 = remainSize_p1%blockSize_p2;
673
674 if (blockCount_p2) {
675 RT_TRACE(_module_hal_init_c_, _drv_notice_,
676 ("_BlockWrite: [P2] buffSize_p2(%d) blockSize_p2(%d) blockCount_p2(%d) remainSize_p2(%d)\n",
677 (buffSize-offset), blockSize_p2 ,blockCount_p2, remainSize_p2));
678 }
679
680 #ifdef CONFIG_USB_HCI
681 for (i = 0; i < blockCount_p2; i++) {
682 ret = rtw_writeN(padapter, (FW_8188E_START_ADDRESS + offset + i*blockSize_p2), blockSize_p2, (bufferPtr + offset + i*blockSize_p2));
683
684 if(ret == _FAIL)
685 goto exit;
686 }
687 #endif
688 }
689
690 //3 Phase #3
691 if (remainSize_p2)
692 {
693 offset = (blockCount_p1 * blockSize_p1) + (blockCount_p2 * blockSize_p2);
694
695 blockCount_p3 = remainSize_p2 / blockSize_p3;
696
697 RT_TRACE(_module_hal_init_c_, _drv_notice_,
698 ("_BlockWrite: [P3] buffSize_p3(%d) blockSize_p3(%d) blockCount_p3(%d)\n",
699 (buffSize-offset), blockSize_p3, blockCount_p3));
700
701 for(i = 0 ; i < blockCount_p3 ; i++){
702 ret =rtw_write8(padapter, (FW_8188E_START_ADDRESS + offset + i), *(bufferPtr + offset + i));
703
704 if(ret == _FAIL)
705 goto exit;
706 }
707 }
708
709 exit:
710 return ret;
711 }
712
713 static int
_PageWrite(IN PADAPTER padapter,IN u32 page,IN PVOID buffer,IN u32 size)714 _PageWrite(
715 IN PADAPTER padapter,
716 IN u32 page,
717 IN PVOID buffer,
718 IN u32 size
719 )
720 {
721 u8 value8;
722 u8 u8Page = (u8) (page & 0x07) ;
723
724 value8 = (rtw_read8(padapter, REG_MCUFWDL+2) & 0xF8) | u8Page ;
725 rtw_write8(padapter, REG_MCUFWDL+2,value8);
726
727 return _BlockWrite(padapter,buffer,size);
728 }
729
730 static VOID
_FillDummy(u8 * pFwBuf,u32 * pFwLen)731 _FillDummy(
732 u8* pFwBuf,
733 u32* pFwLen
734 )
735 {
736 u32 FwLen = *pFwLen;
737 u8 remain = (u8)(FwLen%4);
738 remain = (remain==0)?0:(4-remain);
739
740 while(remain>0)
741 {
742 pFwBuf[FwLen] = 0;
743 FwLen++;
744 remain--;
745 }
746
747 *pFwLen = FwLen;
748 }
749
750 static int
_WriteFW(IN PADAPTER padapter,IN PVOID buffer,IN u32 size)751 _WriteFW(
752 IN PADAPTER padapter,
753 IN PVOID buffer,
754 IN u32 size
755 )
756 {
757 // Since we need dynamic decide method of dwonload fw, so we call this function to get chip version.
758 int ret = _SUCCESS;
759 u32 pageNums,remainSize ;
760 u32 page, offset;
761 u8 *bufferPtr = (u8*)buffer;
762
763 #ifdef CONFIG_PCI_HCI
764 // 20100120 Joseph: Add for 88CE normal chip.
765 // Fill in zero to make firmware image to dword alignment.
766 // _FillDummy(bufferPtr, &size);
767 #endif
768
769 pageNums = size / MAX_DLFW_PAGE_SIZE ;
770 //RT_ASSERT((pageNums <= 4), ("Page numbers should not greater then 4 \n"));
771 remainSize = size % MAX_DLFW_PAGE_SIZE;
772
773 for (page = 0; page < pageNums; page++) {
774 offset = page * MAX_DLFW_PAGE_SIZE;
775 ret = _PageWrite(padapter, page, bufferPtr+offset, MAX_DLFW_PAGE_SIZE);
776
777 if(ret == _FAIL)
778 goto exit;
779 }
780 if (remainSize) {
781 offset = pageNums * MAX_DLFW_PAGE_SIZE;
782 page = pageNums;
783 ret = _PageWrite(padapter, page, bufferPtr+offset, remainSize);
784
785 if(ret == _FAIL)
786 goto exit;
787
788 }
789 RT_TRACE(_module_hal_init_c_, _drv_info_, ("_WriteFW Done- for Normal chip.\n"));
790
791 exit:
792 return ret;
793 }
794
_MCUIO_Reset88E(PADAPTER padapter,u8 bReset)795 void _MCUIO_Reset88E(PADAPTER padapter,u8 bReset)
796 {
797 u8 u1bTmp;
798
799 if(bReset==_TRUE){
800 u1bTmp = rtw_read8(padapter, REG_RSV_CTRL);
801 rtw_write8(padapter,REG_RSV_CTRL, (u1bTmp&(~BIT1)));
802 // Reset MCU IO Wrapper- sugggest by SD1-Gimmy
803 u1bTmp = rtw_read8(padapter, REG_RSV_CTRL+1);
804 rtw_write8(padapter,REG_RSV_CTRL+1, (u1bTmp&(~BIT3)));
805 }else{
806 u1bTmp = rtw_read8(padapter, REG_RSV_CTRL);
807 rtw_write8(padapter,REG_RSV_CTRL, (u1bTmp&(~BIT1)));
808 // Enable MCU IO Wrapper
809 u1bTmp = rtw_read8(padapter, REG_RSV_CTRL+1);
810 rtw_write8(padapter, REG_RSV_CTRL+1, u1bTmp|BIT3);
811 }
812
813 }
814
_8051Reset88E(PADAPTER padapter)815 void _8051Reset88E(PADAPTER padapter)
816 {
817 u8 u1bTmp;
818
819 _MCUIO_Reset88E(padapter,_TRUE);
820 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
821 rtw_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp&(~BIT2));
822 _MCUIO_Reset88E(padapter,_FALSE);
823 rtw_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp|(BIT2));
824
825 DBG_871X("=====> _8051Reset88E(): 8051 reset success .\n");
826 }
827
polling_fwdl_chksum(_adapter * adapter,u32 min_cnt,u32 timeout_ms)828 static s32 polling_fwdl_chksum(_adapter *adapter, u32 min_cnt, u32 timeout_ms)
829 {
830 s32 ret = _FAIL;
831 u32 value32;
832 u32 start = rtw_get_current_time();
833 u32 cnt = 0;
834
835 /* polling CheckSum report */
836 do {
837 cnt++;
838 value32 = rtw_read32(adapter, REG_MCUFWDL);
839 if (value32 & FWDL_ChkSum_rpt || RTW_CANNOT_RUN(adapter))
840 break;
841 rtw_yield_os();
842 } while (rtw_get_passing_time_ms(start) < timeout_ms || cnt < min_cnt);
843
844 if (!(value32 & FWDL_ChkSum_rpt)) {
845 goto exit;
846 }
847
848 if (rtw_fwdl_test_trigger_chksum_fail())
849 goto exit;
850
851 ret = _SUCCESS;
852
853 exit:
854 DBG_871X("%s: Checksum report %s! (%u, %dms), REG_MCUFWDL:0x%08x\n", __FUNCTION__
855 , (ret==_SUCCESS)?"OK":"Fail", cnt, rtw_get_passing_time_ms(start), value32);
856
857 return ret;
858 }
859
_FWFreeToGo(_adapter * adapter,u32 min_cnt,u32 timeout_ms)860 static s32 _FWFreeToGo(_adapter *adapter, u32 min_cnt, u32 timeout_ms)
861 {
862 s32 ret = _FAIL;
863 u32 value32;
864 u32 start = rtw_get_current_time();
865 u32 cnt = 0;
866
867 value32 = rtw_read32(adapter, REG_MCUFWDL);
868 value32 |= MCUFWDL_RDY;
869 value32 &= ~WINTINI_RDY;
870 rtw_write32(adapter, REG_MCUFWDL, value32);
871
872 _8051Reset88E(adapter);
873
874 /* polling for FW ready */
875 do {
876 cnt++;
877 value32 = rtw_read32(adapter, REG_MCUFWDL);
878 if (value32 & WINTINI_RDY || RTW_CANNOT_RUN(adapter))
879 break;
880 rtw_yield_os();
881 } while (rtw_get_passing_time_ms(start) < timeout_ms || cnt < min_cnt);
882
883 if (!(value32 & WINTINI_RDY)) {
884 goto exit;
885 }
886
887 if (rtw_fwdl_test_trigger_wintint_rdy_fail())
888 goto exit;
889
890 ret = _SUCCESS;
891
892 exit:
893 DBG_871X("%s: Polling FW ready %s! (%u, %dms), REG_MCUFWDL:0x%08x\n", __FUNCTION__
894 , (ret==_SUCCESS)?"OK":"Fail", cnt, rtw_get_passing_time_ms(start), value32);
895 return ret;
896 }
897
898 #define IS_FW_81xxC(padapter) (((GET_HAL_DATA(padapter))->FirmwareSignature & 0xFFF0) == 0x88C0)
899
900
901 #ifdef CONFIG_FILE_FWIMG
902 extern char *rtw_fw_file_path;
903 extern char *rtw_fw_wow_file_path;
904 u8 FwBuffer8188E[FW_8188E_SIZE];
905 #endif //CONFIG_FILE_FWIMG
906
907 //
908 // Description:
909 // Download 8192C firmware code.
910 //
911 //
rtl8188e_FirmwareDownload(PADAPTER padapter,BOOLEAN bUsedWoWLANFw)912 s32 rtl8188e_FirmwareDownload(PADAPTER padapter, BOOLEAN bUsedWoWLANFw)
913 {
914 s32 rtStatus = _SUCCESS;
915 u8 write_fw = 0;
916 u32 fwdl_start_time;
917 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
918
919 PRT_FIRMWARE_8188E pFirmware = NULL;
920 PRT_8188E_FIRMWARE_HDR pFwHdr = NULL;
921
922 u8 *pFirmwareBuf;
923 u32 FirmwareLen,tmp_fw_len=0;
924 #ifdef CONFIG_FILE_FWIMG
925 u8 *fwfilepath;
926 #endif // CONFIG_FILE_FWIMG
927
928 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
929 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
930 #endif
931
932 RT_TRACE(_module_hal_init_c_, _drv_info_, ("+%s\n", __FUNCTION__));
933 pFirmware = (PRT_FIRMWARE_8188E)rtw_zmalloc(sizeof(RT_FIRMWARE_8188E));
934 if(!pFirmware)
935 {
936 rtStatus = _FAIL;
937 goto exit;
938 }
939
940
941 // RT_TRACE(_module_hal_init_c_, _drv_err_, ("%s: %s\n",__FUNCTION__, pFwImageFileName));
942
943 #ifdef CONFIG_FILE_FWIMG
944 #ifdef CONFIG_WOWLAN
945 if (bUsedWoWLANFw)
946 {
947 fwfilepath = rtw_fw_wow_file_path;
948 }
949 else
950 #endif // CONFIG_WOWLAN
951 {
952 fwfilepath = rtw_fw_file_path;
953 }
954 #endif // CONFIG_FILE_FWIMG
955
956 #ifdef CONFIG_FILE_FWIMG
957 if(rtw_is_file_readable(fwfilepath) == _TRUE)
958 {
959 DBG_871X("%s accquire FW from file:%s\n", __FUNCTION__, fwfilepath);
960 pFirmware->eFWSource = FW_SOURCE_IMG_FILE;
961 }
962 else
963 #endif //CONFIG_FILE_FWIMG
964 {
965 pFirmware->eFWSource = FW_SOURCE_HEADER_FILE;
966 }
967
968 switch(pFirmware->eFWSource)
969 {
970 case FW_SOURCE_IMG_FILE:
971 #ifdef CONFIG_FILE_FWIMG
972 rtStatus = rtw_retrieve_from_file(fwfilepath, FwBuffer8188E, FW_8188E_SIZE);
973 pFirmware->ulFwLength = rtStatus>=0?rtStatus:0;
974 pFirmware->szFwBuffer = FwBuffer8188E;
975 #endif //CONFIG_FILE_FWIMG
976 break;
977 case FW_SOURCE_HEADER_FILE:
978 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
979 if(bUsedWoWLANFw) {
980 #ifdef CONFIG_SFW_SUPPORTED
981 if (IS_VENDOR_8188E_I_CUT_SERIES(padapter)) {
982 ODM_ConfigFWWithHeaderFile(&pHalData->odmpriv, CONFIG_FW_WoWLAN_2,
983 (u8 *)&(pFirmware->szFwBuffer), &(pFirmware->ulFwLength));
984 } else
985 #endif
986 {
987 if (!pwrpriv->wowlan_ap_mode) {
988 ODM_ConfigFWWithHeaderFile(
989 &pHalData->odmpriv,
990 CONFIG_FW_WoWLAN,
991 (u8 *)&(pFirmware->szFwBuffer),
992 &(pFirmware->ulFwLength));
993 DBG_871X("%s fw:%s, size: %d\n", __func__,
994 "WoWLAN", pFirmware->ulFwLength);
995 } else {
996 ODM_ConfigFWWithHeaderFile(
997 &pHalData->odmpriv,
998 CONFIG_FW_AP,
999 (u8 *)&(pFirmware->szFwBuffer),
1000 &(pFirmware->ulFwLength));
1001 DBG_871X("%s fw: %s, size: %d\n", __func__,
1002 "AP_WoWLAN", pFirmware->ulFwLength);
1003 }
1004 }
1005
1006 }else
1007 #endif //CONFIG_WOWLAN
1008 {
1009 #ifdef CONFIG_SFW_SUPPORTED
1010 if(IS_VENDOR_8188E_I_CUT_SERIES(padapter))
1011 ODM_ConfigFWWithHeaderFile(&pHalData->odmpriv, CONFIG_FW_NIC_2,
1012 (u8 *)&(pFirmware->szFwBuffer), &(pFirmware->ulFwLength));
1013 else
1014 #endif
1015 ODM_ConfigFWWithHeaderFile(&pHalData->odmpriv, CONFIG_FW_NIC,
1016 (u8 *)&(pFirmware->szFwBuffer), &(pFirmware->ulFwLength));
1017 DBG_871X("%s fw:%s, size: %d\n", __FUNCTION__, "NIC", pFirmware->ulFwLength);
1018 }
1019 break;
1020 }
1021
1022 tmp_fw_len = IS_VENDOR_8188E_I_CUT_SERIES(padapter)?FW_8188E_SIZE_2:FW_8188E_SIZE;
1023
1024 if (pFirmware->ulFwLength > tmp_fw_len) {
1025 rtStatus = _FAIL;
1026 DBG_871X_LEVEL(_drv_emerg_, "Firmware size:%u exceed %u\n", pFirmware->ulFwLength, tmp_fw_len);
1027 goto exit;
1028 }
1029
1030 pFirmwareBuf = pFirmware->szFwBuffer;
1031 FirmwareLen = pFirmware->ulFwLength;
1032
1033 // To Check Fw header. Added by tynli. 2009.12.04.
1034 pFwHdr = (PRT_8188E_FIRMWARE_HDR)pFirmwareBuf;
1035
1036 pHalData->FirmwareVersion = le16_to_cpu(pFwHdr->Version);
1037 pHalData->FirmwareSubVersion = pFwHdr->Subversion;
1038 pHalData->FirmwareSignature = le16_to_cpu(pFwHdr->Signature);
1039
1040 DBG_871X("%s: fw_ver=%x fw_subver=%04x sig=0x%x, Month=%02x, Date=%02x, Hour=%02x, Minute=%02x\n",
1041 __FUNCTION__, pHalData->FirmwareVersion, pHalData->FirmwareSubVersion, pHalData->FirmwareSignature
1042 ,pFwHdr->Month,pFwHdr->Date,pFwHdr->Hour,pFwHdr->Minute);
1043
1044 if (IS_FW_HEADER_EXIST_88E(pFwHdr))
1045 {
1046 // Shift 32 bytes for FW header
1047 pFirmwareBuf = pFirmwareBuf + 32;
1048 FirmwareLen = FirmwareLen - 32;
1049 }
1050
1051 // Suggested by Filen. If 8051 is running in RAM code, driver should inform Fw to reset by itself,
1052 // or it will cause download Fw fail. 2010.02.01. by tynli.
1053 if (rtw_read8(padapter, REG_MCUFWDL) & RAM_DL_SEL) //8051 RAM code
1054 {
1055 rtw_write8(padapter, REG_MCUFWDL, 0x00);
1056 _8051Reset88E(padapter);
1057 }
1058
1059 _FWDownloadEnable_8188E(padapter, _TRUE);
1060 fwdl_start_time = rtw_get_current_time();
1061 while (!RTW_CANNOT_RUN(padapter)
1062 && (write_fw++ < 3 || rtw_get_passing_time_ms(fwdl_start_time) < 500))
1063 {
1064 /* reset FWDL chksum */
1065 rtw_write8(padapter, REG_MCUFWDL, rtw_read8(padapter, REG_MCUFWDL)|FWDL_ChkSum_rpt);
1066
1067 rtStatus = _WriteFW(padapter, pFirmwareBuf, FirmwareLen);
1068 if (rtStatus != _SUCCESS)
1069 continue;
1070
1071 rtStatus = polling_fwdl_chksum(padapter, 5, 50);
1072 if (rtStatus == _SUCCESS)
1073 break;
1074 }
1075 _FWDownloadEnable_8188E(padapter, _FALSE);
1076 if(_SUCCESS != rtStatus)
1077 goto fwdl_stat;
1078
1079 rtStatus = _FWFreeToGo(padapter, 10, 200);
1080 if (_SUCCESS != rtStatus)
1081 goto fwdl_stat;
1082
1083 fwdl_stat:
1084 DBG_871X("FWDL %s. write_fw:%u, %dms\n"
1085 , (rtStatus == _SUCCESS)?"success":"fail"
1086 , write_fw
1087 , rtw_get_passing_time_ms(fwdl_start_time)
1088 );
1089
1090 exit:
1091 if (pFirmware)
1092 rtw_mfree((u8*)pFirmware, sizeof(RT_FIRMWARE_8188E));
1093
1094 return rtStatus;
1095 }
1096
rtl8188e_InitializeFirmwareVars(PADAPTER padapter)1097 void rtl8188e_InitializeFirmwareVars(PADAPTER padapter)
1098 {
1099 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
1100 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
1101
1102 // Init Fw LPS related.
1103 pwrpriv->bFwCurrentInPSMode = _FALSE;
1104
1105 //Init H2C cmd.
1106 rtw_write8(padapter, REG_HMETFR, 0x0f);
1107
1108 // Init H2C counter. by tynli. 2009.12.09.
1109 pHalData->LastHMEBoxNum = 0;
1110 }
1111
1112 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
1113 //===========================================
1114
1115 //
1116 // Description: Prepare some information to Fw for WoWLAN.
1117 // (1) Download wowlan Fw.
1118 // (2) Download RSVD page packets.
1119 // (3) Enable AP offload if needed.
1120 //
1121 // 2011.04.12 by tynli.
1122 //
1123 VOID
SetFwRelatedForWoWLAN8188ES(IN PADAPTER padapter,IN u8 bHostIsGoingtoSleep)1124 SetFwRelatedForWoWLAN8188ES(
1125 IN PADAPTER padapter,
1126 IN u8 bHostIsGoingtoSleep
1127 )
1128 {
1129 int status=_FAIL;
1130 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
1131 u8 bRecover = _FALSE;
1132 //
1133 // 1. Before WoWLAN we need to re-download WoWLAN Fw.
1134 //
1135 status = rtl8188e_FirmwareDownload(padapter, bHostIsGoingtoSleep);
1136 if(status != _SUCCESS) {
1137 DBG_871X("ConfigFwRelatedForWoWLAN8188ES(): Re-Download Firmware failed!!\n");
1138 return;
1139 } else {
1140 DBG_871X("ConfigFwRelatedForWoWLAN8188ES(): Re-Download Firmware Success !!\n");
1141 }
1142 //
1143 // 2. Re-Init the variables about Fw related setting.
1144 //
1145 rtl8188e_InitializeFirmwareVars(padapter);
1146 }
1147 #endif /*CONFIG_WOWLAN || CONFIG_AP_WOWLAN*/
1148
1149 //===========================================================
1150 // Efuse related code
1151 //===========================================================
1152 enum{
1153 VOLTAGE_V25 = 0x03,
1154 LDOE25_SHIFT = 28 ,
1155 };
1156
1157 static BOOLEAN
1158 hal_EfusePgPacketWrite2ByteHeader(
1159 IN PADAPTER pAdapter,
1160 IN u8 efuseType,
1161 IN u16 *pAddr,
1162 IN PPGPKT_STRUCT pTargetPkt,
1163 IN BOOLEAN bPseudoTest);
1164 static BOOLEAN
1165 hal_EfusePgPacketWrite1ByteHeader(
1166 IN PADAPTER pAdapter,
1167 IN u8 efuseType,
1168 IN u16 *pAddr,
1169 IN PPGPKT_STRUCT pTargetPkt,
1170 IN BOOLEAN bPseudoTest);
1171 static BOOLEAN
1172 hal_EfusePgPacketWriteData(
1173 IN PADAPTER pAdapter,
1174 IN u8 efuseType,
1175 IN u16 *pAddr,
1176 IN PPGPKT_STRUCT pTargetPkt,
1177 IN BOOLEAN bPseudoTest);
1178
1179 static VOID
hal_EfusePowerSwitch_RTL8188E(IN PADAPTER pAdapter,IN u8 bWrite,IN u8 PwrState)1180 hal_EfusePowerSwitch_RTL8188E(
1181 IN PADAPTER pAdapter,
1182 IN u8 bWrite,
1183 IN u8 PwrState)
1184 {
1185 u8 tempval;
1186 u16 tmpV16;
1187
1188 if (PwrState == _TRUE)
1189 {
1190 rtw_write8(pAdapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON);
1191 #if 0
1192 // 1.2V Power: From VDDON with Power Cut(0x0000h[15]), defualt valid
1193 tmpV16 = rtw_read16(pAdapter,REG_SYS_ISO_CTRL);
1194 if( ! (tmpV16 & PWC_EV12V ) ){
1195 tmpV16 |= PWC_EV12V ;
1196 rtw_write16(pAdapter,REG_SYS_ISO_CTRL,tmpV16);
1197 }
1198 #endif
1199 // Reset: 0x0000h[28], default valid
1200 tmpV16 = rtw_read16(pAdapter,REG_SYS_FUNC_EN);
1201 if( !(tmpV16 & FEN_ELDR) ){
1202 tmpV16 |= FEN_ELDR ;
1203 rtw_write16(pAdapter,REG_SYS_FUNC_EN,tmpV16);
1204 }
1205
1206 // Clock: Gated(0x0008h[5]) 8M(0x0008h[1]) clock from ANA, default valid
1207 tmpV16 = rtw_read16(pAdapter,REG_SYS_CLKR);
1208 if( (!(tmpV16 & LOADER_CLK_EN) ) ||(!(tmpV16 & ANA8M) ) ){
1209 tmpV16 |= (LOADER_CLK_EN |ANA8M ) ;
1210 rtw_write16(pAdapter,REG_SYS_CLKR,tmpV16);
1211 }
1212
1213 if(bWrite == _TRUE)
1214 {
1215 // Enable LDO 2.5V before read/write action
1216 tempval = rtw_read8(pAdapter, EFUSE_TEST+3);
1217 if(IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)){
1218 tempval &= 0x87;
1219 tempval |= 0x38; // 0x34[30:27] = 0b'0111, Use LDO 2.25V, Suggested by SD1 Pisa
1220 }
1221 else{
1222 tempval &= 0x0F;
1223 tempval |= (VOLTAGE_V25 << 4);
1224 }
1225 rtw_write8(pAdapter, EFUSE_TEST+3, (tempval | 0x80));
1226 }
1227 }
1228 else
1229 {
1230 rtw_write8(pAdapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF);
1231
1232 if(bWrite == _TRUE){
1233 // Disable LDO 2.5V after read/write action
1234 tempval = rtw_read8(pAdapter, EFUSE_TEST+3);
1235 rtw_write8(pAdapter, EFUSE_TEST+3, (tempval & 0x7F));
1236 }
1237 }
1238 }
1239
1240 static VOID
rtl8188e_EfusePowerSwitch(IN PADAPTER pAdapter,IN u8 bWrite,IN u8 PwrState)1241 rtl8188e_EfusePowerSwitch(
1242 IN PADAPTER pAdapter,
1243 IN u8 bWrite,
1244 IN u8 PwrState)
1245 {
1246 hal_EfusePowerSwitch_RTL8188E(pAdapter, bWrite, PwrState);
1247 }
1248
1249
1250
efuse_read_phymap(PADAPTER Adapter,u8 * pbuf,u16 * size)1251 static bool efuse_read_phymap(
1252 PADAPTER Adapter,
1253 u8 *pbuf, //buffer to store efuse physical map
1254 u16 *size //the max byte to read. will update to byte read
1255 )
1256 {
1257 u8 *pos = pbuf;
1258 u16 limit = *size;
1259 u16 addr = 0;
1260 bool reach_end = _FALSE;
1261
1262 //
1263 // Refresh efuse init map as all 0xFF.
1264 //
1265 _rtw_memset(pbuf, 0xFF, limit);
1266
1267
1268 //
1269 // Read physical efuse content.
1270 //
1271 while(addr < limit)
1272 {
1273 ReadEFuseByte(Adapter, addr, pos, _FALSE);
1274 if(*pos != 0xFF)
1275 {
1276 pos++;
1277 addr++;
1278 }
1279 else
1280 {
1281 reach_end = _TRUE;
1282 break;
1283 }
1284 }
1285
1286 *size = addr;
1287
1288 return reach_end;
1289
1290 }
1291
1292 static VOID
Hal_EfuseReadEFuse88E(PADAPTER Adapter,u16 _offset,u16 _size_byte,u8 * pbuf,IN BOOLEAN bPseudoTest)1293 Hal_EfuseReadEFuse88E(
1294 PADAPTER Adapter,
1295 u16 _offset,
1296 u16 _size_byte,
1297 u8 *pbuf,
1298 IN BOOLEAN bPseudoTest
1299 )
1300 {
1301 //u8 efuseTbl[EFUSE_MAP_LEN_88E];
1302 u8 *efuseTbl = NULL;
1303 u8 rtemp8[1];
1304 u16 eFuse_Addr = 0;
1305 u8 offset, wren;
1306 u16 i, j;
1307 //u16 eFuseWord[EFUSE_MAX_SECTION_88E][EFUSE_MAX_WORD_UNIT];
1308 u16 **eFuseWord = NULL;
1309 u16 efuse_utilized = 0;
1310 u8 efuse_usage = 0;
1311 u8 u1temp = 0;
1312
1313 //
1314 // Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10.
1315 //
1316 if((_offset + _size_byte)>EFUSE_MAP_LEN_88E)
1317 {// total E-Fuse table is 512bytes
1318 DBG_8192C("Hal_EfuseReadEFuse88E(): Invalid offset(%#x) with read bytes(%#x)!!\n",_offset, _size_byte);
1319 goto exit;
1320 }
1321
1322 efuseTbl = (u8*)rtw_zmalloc(EFUSE_MAP_LEN_88E);
1323 if(efuseTbl == NULL)
1324 {
1325 DBG_871X("%s: alloc efuseTbl fail!\n", __FUNCTION__);
1326 goto exit;
1327 }
1328
1329 eFuseWord= (u16 **)rtw_malloc2d(EFUSE_MAX_SECTION_88E, EFUSE_MAX_WORD_UNIT, 2);
1330 if(eFuseWord == NULL)
1331 {
1332 DBG_871X("%s: alloc eFuseWord fail!\n", __FUNCTION__);
1333 goto exit;
1334 }
1335
1336 // 0. Refresh efuse init map as all oxFF.
1337 for (i = 0; i < EFUSE_MAX_SECTION_88E; i++)
1338 for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++)
1339 eFuseWord[i][j] = 0xFFFF;
1340
1341 //
1342 // 1. Read the first byte to check if efuse is empty!!!
1343 //
1344 //
1345 ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest);
1346 if(*rtemp8 != 0xFF)
1347 {
1348 efuse_utilized++;
1349 //DBG_8192C("efuse_Addr-%d efuse_data=%x\n", eFuse_Addr, *rtemp8);
1350 eFuse_Addr++;
1351 }
1352 else
1353 {
1354 DBG_871X("EFUSE is empty efuse_Addr-%d efuse_data=%x\n", eFuse_Addr, *rtemp8);
1355 goto exit;
1356 }
1357
1358
1359 //
1360 // 2. Read real efuse content. Filter PG header and every section data.
1361 //
1362 while((*rtemp8 != 0xFF) && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E))
1363 {
1364 //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("efuse_Addr-%d efuse_data=%x\n", eFuse_Addr-1, *rtemp8));
1365
1366 // Check PG header for section num.
1367 if((*rtemp8 & 0x1F ) == 0x0F) //extended header
1368 {
1369 u1temp =( (*rtemp8 & 0xE0) >> 5);
1370 //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header u1temp=%x *rtemp&0xE0 0x%x\n", u1temp, *rtemp8 & 0xE0));
1371
1372 //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header u1temp=%x \n", u1temp));
1373
1374 ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest);
1375
1376 //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header efuse_Addr-%d efuse_data=%x\n", eFuse_Addr, *rtemp8));
1377
1378 if((*rtemp8 & 0x0F) == 0x0F)
1379 {
1380 eFuse_Addr++;
1381 ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest);
1382
1383 if(*rtemp8 != 0xFF && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E))
1384 {
1385 eFuse_Addr++;
1386 }
1387 continue;
1388 }
1389 else
1390 {
1391 offset = ((*rtemp8 & 0xF0) >> 1) | u1temp;
1392 wren = (*rtemp8 & 0x0F);
1393 eFuse_Addr++;
1394 }
1395 }
1396 else
1397 {
1398 offset = ((*rtemp8 >> 4) & 0x0f);
1399 wren = (*rtemp8 & 0x0f);
1400 }
1401
1402 if(offset < EFUSE_MAX_SECTION_88E)
1403 {
1404 // Get word enable value from PG header
1405 //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Offset-%d Worden=%x\n", offset, wren));
1406
1407 for(i=0; i<EFUSE_MAX_WORD_UNIT; i++)
1408 {
1409 // Check word enable condition in the section
1410 if(!(wren & 0x01))
1411 {
1412 //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d \n", eFuse_Addr));
1413 ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest);
1414 eFuse_Addr++;
1415 //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Data=0x%x\n", *rtemp8));
1416 efuse_utilized++;
1417 eFuseWord[offset][i] = (*rtemp8 & 0xff);
1418
1419
1420 if(eFuse_Addr >= EFUSE_REAL_CONTENT_LEN_88E)
1421 break;
1422
1423 //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d", eFuse_Addr));
1424 ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest);
1425 eFuse_Addr++;
1426 //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Data=0x%x\n", *rtemp8));
1427
1428 efuse_utilized++;
1429 eFuseWord[offset][i] |= (((u2Byte)*rtemp8 << 8) & 0xff00);
1430
1431 if(eFuse_Addr >= EFUSE_REAL_CONTENT_LEN_88E)
1432 break;
1433 }
1434
1435 wren >>= 1;
1436
1437 }
1438 }
1439 else{//deal with error offset,skip error data
1440 DBG_871X_LEVEL(_drv_always_, "invalid offset:0x%02x \n",offset);
1441 for(i=0; i<EFUSE_MAX_WORD_UNIT; i++){
1442 // Check word enable condition in the section
1443 if(!(wren & 0x01)){
1444 eFuse_Addr++;
1445 efuse_utilized++;
1446 if(eFuse_Addr >= EFUSE_REAL_CONTENT_LEN_88E)
1447 break;
1448 eFuse_Addr++;
1449 efuse_utilized++;
1450 if(eFuse_Addr >= EFUSE_REAL_CONTENT_LEN_88E)
1451 break;
1452 }
1453 }
1454 }
1455 // Read next PG header
1456 ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest);
1457 //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d rtemp 0x%x\n", eFuse_Addr, *rtemp8));
1458
1459 if(*rtemp8 != 0xFF && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN_88E))
1460 {
1461 efuse_utilized++;
1462 eFuse_Addr++;
1463 }
1464 }
1465
1466 //
1467 // 3. Collect 16 sections and 4 word unit into Efuse map.
1468 //
1469 for(i=0; i<EFUSE_MAX_SECTION_88E; i++)
1470 {
1471 for(j=0; j<EFUSE_MAX_WORD_UNIT; j++)
1472 {
1473 efuseTbl[(i*8)+(j*2)]=(eFuseWord[i][j] & 0xff);
1474 efuseTbl[(i*8)+((j*2)+1)]=((eFuseWord[i][j] >> 8) & 0xff);
1475 }
1476 }
1477
1478
1479 //
1480 // 4. Copy from Efuse map to output pointer memory!!!
1481 //
1482 for(i=0; i<_size_byte; i++)
1483 {
1484 pbuf[i] = efuseTbl[_offset+i];
1485 }
1486
1487 //
1488 // 5. Calculate Efuse utilization.
1489 //
1490 efuse_usage = (u1Byte)((eFuse_Addr*100)/EFUSE_REAL_CONTENT_LEN_88E);
1491 rtw_hal_set_hwreg(Adapter, HW_VAR_EFUSE_BYTES, (u8 *)&eFuse_Addr);
1492
1493 exit:
1494 if(efuseTbl)
1495 rtw_mfree(efuseTbl, EFUSE_MAP_LEN_88E);
1496
1497 if(eFuseWord)
1498 rtw_mfree2d((void *)eFuseWord, EFUSE_MAX_SECTION_88E, EFUSE_MAX_WORD_UNIT, sizeof(u16));
1499 }
1500
1501
1502 static BOOLEAN
Hal_EfuseSwitchToBank(IN PADAPTER pAdapter,IN u8 bank,IN BOOLEAN bPseudoTest)1503 Hal_EfuseSwitchToBank(
1504 IN PADAPTER pAdapter,
1505 IN u8 bank,
1506 IN BOOLEAN bPseudoTest
1507 )
1508 {
1509 BOOLEAN bRet = _FALSE;
1510 u32 value32=0;
1511
1512 //RTPRINT(FEEPROM, EFUSE_PG, ("Efuse switch bank to %d\n", bank));
1513 if(bPseudoTest)
1514 {
1515 fakeEfuseBank = bank;
1516 bRet = _TRUE;
1517 }
1518 else
1519 {
1520 bRet = _TRUE;
1521 }
1522 return bRet;
1523 }
1524
1525
1526
1527 static VOID
ReadEFuseByIC(PADAPTER Adapter,u8 efuseType,u16 _offset,u16 _size_byte,u8 * pbuf,IN BOOLEAN bPseudoTest)1528 ReadEFuseByIC(
1529 PADAPTER Adapter,
1530 u8 efuseType,
1531 u16 _offset,
1532 u16 _size_byte,
1533 u8 *pbuf,
1534 IN BOOLEAN bPseudoTest
1535 )
1536 {
1537 PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
1538 #ifdef DBG_IOL_READ_EFUSE_MAP
1539 u8 logical_map[512];
1540 #endif
1541
1542 #ifdef CONFIG_IOL_READ_EFUSE_MAP
1543 if(!bPseudoTest )//&& rtw_IOL_applied(Adapter))
1544 {
1545 int ret = _FAIL;
1546 if(rtw_IOL_applied(Adapter))
1547 {
1548 rtw_hal_power_on(Adapter);
1549
1550 iol_mode_enable(Adapter, 1);
1551 #ifdef DBG_IOL_READ_EFUSE_MAP
1552 iol_read_efuse(Adapter, 0, _offset, _size_byte, logical_map);
1553 #else
1554 ret = iol_read_efuse(Adapter, 0, _offset, _size_byte, pbuf);
1555 #endif
1556 iol_mode_enable(Adapter, 0);
1557
1558 if(_SUCCESS == ret)
1559 goto exit;
1560 }
1561 }
1562 #endif
1563 Hal_EfuseReadEFuse88E(Adapter, _offset, _size_byte, pbuf, bPseudoTest);
1564
1565 exit:
1566
1567 #ifdef DBG_IOL_READ_EFUSE_MAP
1568 if(_rtw_memcmp(logical_map, pHalData->efuse_eeprom_data, 0x130) == _FALSE)
1569 {
1570 int i;
1571 DBG_871X("%s compare first 0x130 byte fail\n", __FUNCTION__);
1572 for(i=0;i<512;i++)
1573 {
1574 if(i%16==0)
1575 DBG_871X("0x%03x: ", i);
1576 DBG_871X("%02x ", logical_map[i]);
1577 if(i%16==15)
1578 DBG_871X("\n");
1579 }
1580 DBG_871X("\n");
1581 }
1582 #endif
1583
1584 return;
1585 }
1586
1587 static VOID
ReadEFuse_Pseudo(PADAPTER Adapter,u8 efuseType,u16 _offset,u16 _size_byte,u8 * pbuf,IN BOOLEAN bPseudoTest)1588 ReadEFuse_Pseudo(
1589 PADAPTER Adapter,
1590 u8 efuseType,
1591 u16 _offset,
1592 u16 _size_byte,
1593 u8 *pbuf,
1594 IN BOOLEAN bPseudoTest
1595 )
1596 {
1597 Hal_EfuseReadEFuse88E(Adapter, _offset, _size_byte, pbuf, bPseudoTest);
1598 }
1599
1600 static VOID
rtl8188e_ReadEFuse(PADAPTER Adapter,u8 efuseType,u16 _offset,u16 _size_byte,u8 * pbuf,IN BOOLEAN bPseudoTest)1601 rtl8188e_ReadEFuse(
1602 PADAPTER Adapter,
1603 u8 efuseType,
1604 u16 _offset,
1605 u16 _size_byte,
1606 u8 *pbuf,
1607 IN BOOLEAN bPseudoTest
1608 )
1609 {
1610 if(bPseudoTest)
1611 {
1612 ReadEFuse_Pseudo(Adapter, efuseType, _offset, _size_byte, pbuf, bPseudoTest);
1613 }
1614 else
1615 {
1616 ReadEFuseByIC(Adapter, efuseType, _offset, _size_byte, pbuf, bPseudoTest);
1617 }
1618 }
1619
1620 //Do not support BT
1621 VOID
Hal_EFUSEGetEfuseDefinition88E(IN PADAPTER pAdapter,IN u1Byte efuseType,IN u1Byte type,OUT PVOID pOut)1622 Hal_EFUSEGetEfuseDefinition88E(
1623 IN PADAPTER pAdapter,
1624 IN u1Byte efuseType,
1625 IN u1Byte type,
1626 OUT PVOID pOut
1627 )
1628 {
1629 switch(type)
1630 {
1631 case TYPE_EFUSE_MAX_SECTION:
1632 {
1633 u8* pMax_section;
1634 pMax_section = (u8*)pOut;
1635 *pMax_section = EFUSE_MAX_SECTION_88E;
1636 }
1637 break;
1638 case TYPE_EFUSE_REAL_CONTENT_LEN:
1639 {
1640 u16* pu2Tmp;
1641 pu2Tmp = (u16*)pOut;
1642 *pu2Tmp = EFUSE_REAL_CONTENT_LEN_88E;
1643 }
1644 break;
1645 case TYPE_EFUSE_CONTENT_LEN_BANK:
1646 {
1647 u16* pu2Tmp;
1648 pu2Tmp = (u16*)pOut;
1649 *pu2Tmp = EFUSE_REAL_CONTENT_LEN_88E;
1650 }
1651 break;
1652 case TYPE_AVAILABLE_EFUSE_BYTES_BANK:
1653 {
1654 u16* pu2Tmp;
1655 pu2Tmp = (u16*)pOut;
1656 *pu2Tmp = (u16)(EFUSE_REAL_CONTENT_LEN_88E-EFUSE_OOB_PROTECT_BYTES_88E);
1657 }
1658 break;
1659 case TYPE_AVAILABLE_EFUSE_BYTES_TOTAL:
1660 {
1661 u16* pu2Tmp;
1662 pu2Tmp = (u16*)pOut;
1663 *pu2Tmp = (u16)(EFUSE_REAL_CONTENT_LEN_88E-EFUSE_OOB_PROTECT_BYTES_88E);
1664 }
1665 break;
1666 case TYPE_EFUSE_MAP_LEN:
1667 {
1668 u16* pu2Tmp;
1669 pu2Tmp = (u16*)pOut;
1670 *pu2Tmp = (u16)EFUSE_MAP_LEN_88E;
1671 }
1672 break;
1673 case TYPE_EFUSE_PROTECT_BYTES_BANK:
1674 {
1675 u8* pu1Tmp;
1676 pu1Tmp = (u8*)pOut;
1677 *pu1Tmp = (u8)(EFUSE_OOB_PROTECT_BYTES_88E);
1678 }
1679 break;
1680 default:
1681 {
1682 u8* pu1Tmp;
1683 pu1Tmp = (u8*)pOut;
1684 *pu1Tmp = 0;
1685 }
1686 break;
1687 }
1688 }
1689 VOID
Hal_EFUSEGetEfuseDefinition_Pseudo88E(IN PADAPTER pAdapter,IN u8 efuseType,IN u8 type,OUT PVOID pOut)1690 Hal_EFUSEGetEfuseDefinition_Pseudo88E(
1691 IN PADAPTER pAdapter,
1692 IN u8 efuseType,
1693 IN u8 type,
1694 OUT PVOID pOut
1695 )
1696 {
1697 switch(type)
1698 {
1699 case TYPE_EFUSE_MAX_SECTION:
1700 {
1701 u8* pMax_section;
1702 pMax_section = (pu1Byte)pOut;
1703 *pMax_section = EFUSE_MAX_SECTION_88E;
1704 }
1705 break;
1706 case TYPE_EFUSE_REAL_CONTENT_LEN:
1707 {
1708 u16* pu2Tmp;
1709 pu2Tmp = (pu2Byte)pOut;
1710 *pu2Tmp = EFUSE_REAL_CONTENT_LEN_88E;
1711 }
1712 break;
1713 case TYPE_EFUSE_CONTENT_LEN_BANK:
1714 {
1715 u16* pu2Tmp;
1716 pu2Tmp = (pu2Byte)pOut;
1717 *pu2Tmp = EFUSE_REAL_CONTENT_LEN_88E;
1718 }
1719 break;
1720 case TYPE_AVAILABLE_EFUSE_BYTES_BANK:
1721 {
1722 u16* pu2Tmp;
1723 pu2Tmp = (pu2Byte)pOut;
1724 *pu2Tmp = (u2Byte)(EFUSE_REAL_CONTENT_LEN_88E-EFUSE_OOB_PROTECT_BYTES_88E);
1725 }
1726 break;
1727 case TYPE_AVAILABLE_EFUSE_BYTES_TOTAL:
1728 {
1729 u16* pu2Tmp;
1730 pu2Tmp = (pu2Byte)pOut;
1731 *pu2Tmp = (u2Byte)(EFUSE_REAL_CONTENT_LEN_88E-EFUSE_OOB_PROTECT_BYTES_88E);
1732 }
1733 break;
1734 case TYPE_EFUSE_MAP_LEN:
1735 {
1736 u16* pu2Tmp;
1737 pu2Tmp = (pu2Byte)pOut;
1738 *pu2Tmp = (u2Byte)EFUSE_MAP_LEN_88E;
1739 }
1740 break;
1741 case TYPE_EFUSE_PROTECT_BYTES_BANK:
1742 {
1743 u8* pu1Tmp;
1744 pu1Tmp = (u8*)pOut;
1745 *pu1Tmp = (u8)(EFUSE_OOB_PROTECT_BYTES_88E);
1746 }
1747 break;
1748 default:
1749 {
1750 u8* pu1Tmp;
1751 pu1Tmp = (u8*)pOut;
1752 *pu1Tmp = 0;
1753 }
1754 break;
1755 }
1756 }
1757
1758
1759 static VOID
rtl8188e_EFUSE_GetEfuseDefinition(IN PADAPTER pAdapter,IN u8 efuseType,IN u8 type,OUT void * pOut,IN BOOLEAN bPseudoTest)1760 rtl8188e_EFUSE_GetEfuseDefinition(
1761 IN PADAPTER pAdapter,
1762 IN u8 efuseType,
1763 IN u8 type,
1764 OUT void *pOut,
1765 IN BOOLEAN bPseudoTest
1766 )
1767 {
1768 if(bPseudoTest)
1769 {
1770 Hal_EFUSEGetEfuseDefinition_Pseudo88E(pAdapter, efuseType, type, pOut);
1771 }
1772 else
1773 {
1774 Hal_EFUSEGetEfuseDefinition88E(pAdapter, efuseType, type, pOut);
1775 }
1776 }
1777
1778 static u8
Hal_EfuseWordEnableDataWrite(IN PADAPTER pAdapter,IN u16 efuse_addr,IN u8 word_en,IN u8 * data,IN BOOLEAN bPseudoTest)1779 Hal_EfuseWordEnableDataWrite( IN PADAPTER pAdapter,
1780 IN u16 efuse_addr,
1781 IN u8 word_en,
1782 IN u8 *data,
1783 IN BOOLEAN bPseudoTest)
1784 {
1785 u16 tmpaddr = 0;
1786 u16 start_addr = efuse_addr;
1787 u8 badworden = 0x0F;
1788 u8 tmpdata[8];
1789
1790 _rtw_memset((PVOID)tmpdata, 0xff, PGPKT_DATA_SIZE);
1791 //RT_TRACE(COMP_EFUSE, DBG_LOUD, ("word_en = %x efuse_addr=%x\n", word_en, efuse_addr));
1792
1793 if(!(word_en&BIT0))
1794 {
1795 tmpaddr = start_addr;
1796 efuse_OneByteWrite(pAdapter,start_addr++, data[0], bPseudoTest);
1797 efuse_OneByteWrite(pAdapter,start_addr++, data[1], bPseudoTest);
1798 PHY_SetMacReg(pAdapter, EFUSE_TEST, BIT26, 0);
1799
1800 efuse_OneByteRead(pAdapter,tmpaddr, &tmpdata[0], bPseudoTest);
1801 efuse_OneByteRead(pAdapter,tmpaddr+1, &tmpdata[1], bPseudoTest);
1802 PHY_SetMacReg(pAdapter, EFUSE_TEST, BIT26, 1);
1803
1804 if((data[0]!=tmpdata[0])||(data[1]!=tmpdata[1])){
1805 badworden &= (~BIT0);
1806 }
1807 }
1808 if(!(word_en&BIT1))
1809 {
1810 tmpaddr = start_addr;
1811 efuse_OneByteWrite(pAdapter,start_addr++, data[2], bPseudoTest);
1812 efuse_OneByteWrite(pAdapter,start_addr++, data[3], bPseudoTest);
1813 PHY_SetMacReg(pAdapter, EFUSE_TEST, BIT26, 0);
1814
1815 efuse_OneByteRead(pAdapter,tmpaddr , &tmpdata[2], bPseudoTest);
1816 efuse_OneByteRead(pAdapter,tmpaddr+1, &tmpdata[3], bPseudoTest);
1817 PHY_SetMacReg(pAdapter, EFUSE_TEST, BIT26, 1);
1818
1819 if((data[2]!=tmpdata[2])||(data[3]!=tmpdata[3])){
1820 badworden &=( ~BIT1);
1821 }
1822 }
1823 if(!(word_en&BIT2))
1824 {
1825 tmpaddr = start_addr;
1826 efuse_OneByteWrite(pAdapter,start_addr++, data[4], bPseudoTest);
1827 efuse_OneByteWrite(pAdapter,start_addr++, data[5], bPseudoTest);
1828 PHY_SetMacReg(pAdapter, EFUSE_TEST, BIT26, 0);
1829
1830 efuse_OneByteRead(pAdapter,tmpaddr, &tmpdata[4], bPseudoTest);
1831 efuse_OneByteRead(pAdapter,tmpaddr+1, &tmpdata[5], bPseudoTest);
1832 PHY_SetMacReg(pAdapter, EFUSE_TEST, BIT26, 1);
1833
1834 if((data[4]!=tmpdata[4])||(data[5]!=tmpdata[5])){
1835 badworden &=( ~BIT2);
1836 }
1837 }
1838 if(!(word_en&BIT3))
1839 {
1840 tmpaddr = start_addr;
1841 efuse_OneByteWrite(pAdapter,start_addr++, data[6], bPseudoTest);
1842 efuse_OneByteWrite(pAdapter,start_addr++, data[7], bPseudoTest);
1843 PHY_SetMacReg(pAdapter, EFUSE_TEST, BIT26, 0);
1844
1845 efuse_OneByteRead(pAdapter,tmpaddr, &tmpdata[6], bPseudoTest);
1846 efuse_OneByteRead(pAdapter,tmpaddr+1, &tmpdata[7], bPseudoTest);
1847 PHY_SetMacReg(pAdapter, EFUSE_TEST, BIT26, 1);
1848
1849 if((data[6]!=tmpdata[6])||(data[7]!=tmpdata[7])){
1850 badworden &=( ~BIT3);
1851 }
1852 }
1853 return badworden;
1854 }
1855
1856 static u8
Hal_EfuseWordEnableDataWrite_Pseudo(IN PADAPTER pAdapter,IN u16 efuse_addr,IN u8 word_en,IN u8 * data,IN BOOLEAN bPseudoTest)1857 Hal_EfuseWordEnableDataWrite_Pseudo( IN PADAPTER pAdapter,
1858 IN u16 efuse_addr,
1859 IN u8 word_en,
1860 IN u8 *data,
1861 IN BOOLEAN bPseudoTest)
1862 {
1863 u8 ret=0;
1864
1865 ret = Hal_EfuseWordEnableDataWrite(pAdapter, efuse_addr, word_en, data, bPseudoTest);
1866
1867 return ret;
1868 }
1869
1870 static u8
rtl8188e_Efuse_WordEnableDataWrite(IN PADAPTER pAdapter,IN u16 efuse_addr,IN u8 word_en,IN u8 * data,IN BOOLEAN bPseudoTest)1871 rtl8188e_Efuse_WordEnableDataWrite( IN PADAPTER pAdapter,
1872 IN u16 efuse_addr,
1873 IN u8 word_en,
1874 IN u8 *data,
1875 IN BOOLEAN bPseudoTest)
1876 {
1877 u8 ret=0;
1878
1879 if(bPseudoTest)
1880 {
1881 ret = Hal_EfuseWordEnableDataWrite_Pseudo(pAdapter, efuse_addr, word_en, data, bPseudoTest);
1882 }
1883 else
1884 {
1885 ret = Hal_EfuseWordEnableDataWrite(pAdapter, efuse_addr, word_en, data, bPseudoTest);
1886 }
1887
1888 return ret;
1889 }
1890
1891
1892 static u16
hal_EfuseGetCurrentSize_8188e(IN PADAPTER pAdapter,IN BOOLEAN bPseudoTest)1893 hal_EfuseGetCurrentSize_8188e(IN PADAPTER pAdapter,
1894 IN BOOLEAN bPseudoTest)
1895 {
1896 int bContinual = _TRUE;
1897
1898 u16 efuse_addr = 0;
1899 u8 hoffset=0,hworden=0;
1900 u8 efuse_data,word_cnts=0;
1901
1902 if(bPseudoTest)
1903 {
1904 efuse_addr = (u16)(fakeEfuseUsedBytes);
1905 }
1906 else
1907 {
1908 rtw_hal_get_hwreg(pAdapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr);
1909 }
1910 //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfuseGetCurrentSize_8723A(), start_efuse_addr = %d\n", efuse_addr));
1911
1912 while ( bContinual &&
1913 efuse_OneByteRead(pAdapter, efuse_addr ,&efuse_data, bPseudoTest) &&
1914 AVAILABLE_EFUSE_ADDR(efuse_addr))
1915 {
1916 if(efuse_data!=0xFF)
1917 {
1918 if((efuse_data&0x1F) == 0x0F) //extended header
1919 {
1920 hoffset = efuse_data;
1921 efuse_addr++;
1922 efuse_OneByteRead(pAdapter, efuse_addr ,&efuse_data, bPseudoTest);
1923 if((efuse_data & 0x0F) == 0x0F)
1924 {
1925 efuse_addr++;
1926 continue;
1927 }
1928 else
1929 {
1930 hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
1931 hworden = efuse_data & 0x0F;
1932 }
1933 }
1934 else
1935 {
1936 hoffset = (efuse_data>>4) & 0x0F;
1937 hworden = efuse_data & 0x0F;
1938 }
1939 word_cnts = Efuse_CalculateWordCnts(hworden);
1940 //read next header
1941 efuse_addr = efuse_addr + (word_cnts*2)+1;
1942 }
1943 else
1944 {
1945 bContinual = _FALSE ;
1946 }
1947 }
1948
1949 if(bPseudoTest)
1950 {
1951 fakeEfuseUsedBytes = efuse_addr;
1952 //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfuseGetCurrentSize_8723A(), return %d\n", fakeEfuseUsedBytes));
1953 }
1954 else
1955 {
1956 rtw_hal_set_hwreg(pAdapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr);
1957 //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfuseGetCurrentSize_8723A(), return %d\n", efuse_addr));
1958 }
1959
1960 return efuse_addr;
1961 }
1962
1963 static u16
Hal_EfuseGetCurrentSize_Pseudo(IN PADAPTER pAdapter,IN BOOLEAN bPseudoTest)1964 Hal_EfuseGetCurrentSize_Pseudo(IN PADAPTER pAdapter,
1965 IN BOOLEAN bPseudoTest)
1966 {
1967 u16 ret=0;
1968
1969 ret = hal_EfuseGetCurrentSize_8188e(pAdapter, bPseudoTest);
1970
1971 return ret;
1972 }
1973
1974
1975 static u16
rtl8188e_EfuseGetCurrentSize(IN PADAPTER pAdapter,IN u8 efuseType,IN BOOLEAN bPseudoTest)1976 rtl8188e_EfuseGetCurrentSize(
1977 IN PADAPTER pAdapter,
1978 IN u8 efuseType,
1979 IN BOOLEAN bPseudoTest)
1980 {
1981 u16 ret=0;
1982
1983 if(bPseudoTest)
1984 {
1985 ret = Hal_EfuseGetCurrentSize_Pseudo(pAdapter, bPseudoTest);
1986 }
1987 else
1988 {
1989 ret = hal_EfuseGetCurrentSize_8188e(pAdapter, bPseudoTest);
1990
1991 }
1992
1993 return ret;
1994 }
1995
1996
1997 static int
hal_EfusePgPacketRead_8188e(IN PADAPTER pAdapter,IN u8 offset,IN u8 * data,IN BOOLEAN bPseudoTest)1998 hal_EfusePgPacketRead_8188e(
1999 IN PADAPTER pAdapter,
2000 IN u8 offset,
2001 IN u8 *data,
2002 IN BOOLEAN bPseudoTest)
2003 {
2004 u8 ReadState = PG_STATE_HEADER;
2005
2006 int bContinual = _TRUE;
2007 int bDataEmpty = _TRUE ;
2008
2009 u8 efuse_data,word_cnts = 0;
2010 u16 efuse_addr = 0;
2011 u8 hoffset = 0,hworden = 0;
2012 u8 tmpidx = 0;
2013 u8 tmpdata[8];
2014 u8 max_section = 0;
2015 u8 tmp_header = 0;
2016
2017 EFUSE_GetEfuseDefinition(pAdapter, EFUSE_WIFI, TYPE_EFUSE_MAX_SECTION, (PVOID)&max_section, bPseudoTest);
2018
2019 if(data==NULL)
2020 return _FALSE;
2021 if(offset>max_section)
2022 return _FALSE;
2023
2024 _rtw_memset((PVOID)data, 0xff, sizeof(u8)*PGPKT_DATA_SIZE);
2025 _rtw_memset((PVOID)tmpdata, 0xff, sizeof(u8)*PGPKT_DATA_SIZE);
2026
2027
2028 //
2029 // <Roger_TODO> Efuse has been pre-programmed dummy 5Bytes at the end of Efuse by CP.
2030 // Skip dummy parts to prevent unexpected data read from Efuse.
2031 // By pass right now. 2009.02.19.
2032 //
2033 while(bContinual && AVAILABLE_EFUSE_ADDR(efuse_addr) )
2034 {
2035 //------- Header Read -------------
2036 if(ReadState & PG_STATE_HEADER)
2037 {
2038 if(efuse_OneByteRead(pAdapter, efuse_addr ,&efuse_data, bPseudoTest)&&(efuse_data!=0xFF))
2039 {
2040 if(EXT_HEADER(efuse_data))
2041 {
2042 tmp_header = efuse_data;
2043 efuse_addr++;
2044 efuse_OneByteRead(pAdapter, efuse_addr ,&efuse_data, bPseudoTest);
2045 if(!ALL_WORDS_DISABLED(efuse_data))
2046 {
2047 hoffset = ((tmp_header & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
2048 hworden = efuse_data & 0x0F;
2049 }
2050 else
2051 {
2052 DBG_8192C("Error, All words disabled\n");
2053 efuse_addr++;
2054 continue;
2055 }
2056 }
2057 else
2058 {
2059 hoffset = (efuse_data>>4) & 0x0F;
2060 hworden = efuse_data & 0x0F;
2061 }
2062 word_cnts = Efuse_CalculateWordCnts(hworden);
2063 bDataEmpty = _TRUE ;
2064
2065 if(hoffset==offset)
2066 {
2067 for(tmpidx = 0;tmpidx< word_cnts*2 ;tmpidx++)
2068 {
2069 if(efuse_OneByteRead(pAdapter, efuse_addr+1+tmpidx ,&efuse_data, bPseudoTest) )
2070 {
2071 tmpdata[tmpidx] = efuse_data;
2072 if(efuse_data!=0xff)
2073 {
2074 bDataEmpty = _FALSE;
2075 }
2076 }
2077 }
2078 if(bDataEmpty==_FALSE){
2079 ReadState = PG_STATE_DATA;
2080 }else{//read next header
2081 efuse_addr = efuse_addr + (word_cnts*2)+1;
2082 ReadState = PG_STATE_HEADER;
2083 }
2084 }
2085 else{//read next header
2086 efuse_addr = efuse_addr + (word_cnts*2)+1;
2087 ReadState = PG_STATE_HEADER;
2088 }
2089
2090 }
2091 else{
2092 bContinual = _FALSE ;
2093 }
2094 }
2095 //------- Data section Read -------------
2096 else if(ReadState & PG_STATE_DATA)
2097 {
2098 efuse_WordEnableDataRead(hworden,tmpdata,data);
2099 efuse_addr = efuse_addr + (word_cnts*2)+1;
2100 ReadState = PG_STATE_HEADER;
2101 }
2102
2103 }
2104
2105 if( (data[0]==0xff) &&(data[1]==0xff) && (data[2]==0xff) && (data[3]==0xff) &&
2106 (data[4]==0xff) &&(data[5]==0xff) && (data[6]==0xff) && (data[7]==0xff))
2107 return _FALSE;
2108 else
2109 return _TRUE;
2110
2111 }
2112
2113 static int
Hal_EfusePgPacketRead(IN PADAPTER pAdapter,IN u8 offset,IN u8 * data,IN BOOLEAN bPseudoTest)2114 Hal_EfusePgPacketRead( IN PADAPTER pAdapter,
2115 IN u8 offset,
2116 IN u8 *data,
2117 IN BOOLEAN bPseudoTest)
2118 {
2119 int ret=0;
2120
2121 ret = hal_EfusePgPacketRead_8188e(pAdapter, offset, data, bPseudoTest);
2122
2123
2124 return ret;
2125 }
2126
2127 static int
Hal_EfusePgPacketRead_Pseudo(IN PADAPTER pAdapter,IN u8 offset,IN u8 * data,IN BOOLEAN bPseudoTest)2128 Hal_EfusePgPacketRead_Pseudo( IN PADAPTER pAdapter,
2129 IN u8 offset,
2130 IN u8 *data,
2131 IN BOOLEAN bPseudoTest)
2132 {
2133 int ret=0;
2134
2135 ret = hal_EfusePgPacketRead_8188e(pAdapter, offset, data, bPseudoTest);
2136
2137 return ret;
2138 }
2139
2140 static int
rtl8188e_Efuse_PgPacketRead(IN PADAPTER pAdapter,IN u8 offset,IN u8 * data,IN BOOLEAN bPseudoTest)2141 rtl8188e_Efuse_PgPacketRead( IN PADAPTER pAdapter,
2142 IN u8 offset,
2143 IN u8 *data,
2144 IN BOOLEAN bPseudoTest)
2145 {
2146 int ret=0;
2147
2148 if(bPseudoTest)
2149 {
2150 ret = Hal_EfusePgPacketRead_Pseudo(pAdapter, offset, data, bPseudoTest);
2151 }
2152 else
2153 {
2154 ret = Hal_EfusePgPacketRead(pAdapter, offset, data, bPseudoTest);
2155 }
2156
2157 return ret;
2158 }
2159
2160 static BOOLEAN
hal_EfuseFixHeaderProcess(IN PADAPTER pAdapter,IN u8 efuseType,IN PPGPKT_STRUCT pFixPkt,IN u16 * pAddr,IN BOOLEAN bPseudoTest)2161 hal_EfuseFixHeaderProcess(
2162 IN PADAPTER pAdapter,
2163 IN u8 efuseType,
2164 IN PPGPKT_STRUCT pFixPkt,
2165 IN u16 *pAddr,
2166 IN BOOLEAN bPseudoTest
2167 )
2168 {
2169 u8 originaldata[8], badworden=0;
2170 u16 efuse_addr=*pAddr;
2171 u32 PgWriteSuccess=0;
2172
2173 _rtw_memset((PVOID)originaldata, 0xff, 8);
2174
2175 if(Efuse_PgPacketRead(pAdapter, pFixPkt->offset, originaldata, bPseudoTest))
2176 { //check if data exist
2177 badworden = Efuse_WordEnableDataWrite(pAdapter, efuse_addr+1, pFixPkt->word_en, originaldata, bPseudoTest);
2178
2179 if(badworden != 0xf) // write fail
2180 {
2181 PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pFixPkt->offset, badworden, originaldata, bPseudoTest);
2182
2183 if(!PgWriteSuccess)
2184 return _FALSE;
2185 else
2186 efuse_addr = Efuse_GetCurrentSize(pAdapter, efuseType, bPseudoTest);
2187 }
2188 else
2189 {
2190 efuse_addr = efuse_addr + (pFixPkt->word_cnts*2) +1;
2191 }
2192 }
2193 else
2194 {
2195 efuse_addr = efuse_addr + (pFixPkt->word_cnts*2) +1;
2196 }
2197 *pAddr = efuse_addr;
2198 return _TRUE;
2199 }
2200
2201 static BOOLEAN
hal_EfusePgPacketWrite2ByteHeader(IN PADAPTER pAdapter,IN u8 efuseType,IN u16 * pAddr,IN PPGPKT_STRUCT pTargetPkt,IN BOOLEAN bPseudoTest)2202 hal_EfusePgPacketWrite2ByteHeader(
2203 IN PADAPTER pAdapter,
2204 IN u8 efuseType,
2205 IN u16 *pAddr,
2206 IN PPGPKT_STRUCT pTargetPkt,
2207 IN BOOLEAN bPseudoTest)
2208 {
2209 BOOLEAN bRet=_FALSE, bContinual=_TRUE;
2210 u16 efuse_addr=*pAddr, efuse_max_available_len=0;
2211 u8 pg_header=0, tmp_header=0, pg_header_temp=0;
2212 u8 repeatcnt=0;
2213
2214 //RTPRINT(FEEPROM, EFUSE_PG, ("Wirte 2byte header\n"));
2215 EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_BANK, (PVOID)&efuse_max_available_len, bPseudoTest);
2216
2217 while(efuse_addr < efuse_max_available_len)
2218 {
2219 pg_header = ((pTargetPkt->offset & 0x07) << 5) | 0x0F;
2220 //RTPRINT(FEEPROM, EFUSE_PG, ("pg_header = 0x%x\n", pg_header));
2221 efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
2222 PHY_SetMacReg(pAdapter, EFUSE_TEST, BIT26, 0);
2223 efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
2224 PHY_SetMacReg(pAdapter, EFUSE_TEST, BIT26, 1);
2225
2226 while(tmp_header == 0xFF || pg_header != tmp_header)
2227 {
2228 if(repeatcnt++ > EFUSE_REPEAT_THRESHOLD_)
2229 {
2230 //RTPRINT(FEEPROM, EFUSE_PG, ("Repeat over limit for pg_header!!\n"));
2231 return _FALSE;
2232 }
2233
2234 efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
2235 efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
2236 }
2237
2238 //to write ext_header
2239 if(tmp_header == pg_header)
2240 {
2241 efuse_addr++;
2242 pg_header_temp = pg_header;
2243 pg_header = ((pTargetPkt->offset & 0x78) << 1) | pTargetPkt->word_en;
2244
2245 efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
2246 PHY_SetMacReg(pAdapter, EFUSE_TEST, BIT26, 0);
2247 efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
2248 PHY_SetMacReg(pAdapter, EFUSE_TEST, BIT26, 1);
2249
2250 while(tmp_header == 0xFF || pg_header != tmp_header)
2251 {
2252 if(repeatcnt++ > EFUSE_REPEAT_THRESHOLD_)
2253 {
2254 //RTPRINT(FEEPROM, EFUSE_PG, ("Repeat over limit for ext_header!!\n"));
2255 return _FALSE;
2256 }
2257
2258 efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
2259 efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
2260 }
2261
2262 if((tmp_header & 0x0F) == 0x0F) //word_en PG fail
2263 {
2264 if(repeatcnt++ > EFUSE_REPEAT_THRESHOLD_)
2265 {
2266 //RTPRINT(FEEPROM, EFUSE_PG, ("Repeat over limit for word_en!!\n"));
2267 return _FALSE;
2268 }
2269 else
2270 {
2271 efuse_addr++;
2272 continue;
2273 }
2274 }
2275 else if(pg_header != tmp_header) //offset PG fail
2276 {
2277 PGPKT_STRUCT fixPkt;
2278 //RTPRINT(FEEPROM, EFUSE_PG, ("Error condition for offset PG fail, need to cover the existed data\n"));
2279 fixPkt.offset = ((pg_header_temp & 0xE0) >> 5) | ((tmp_header & 0xF0) >> 1);
2280 fixPkt.word_en = tmp_header & 0x0F;
2281 fixPkt.word_cnts = Efuse_CalculateWordCnts(fixPkt.word_en);
2282 if(!hal_EfuseFixHeaderProcess(pAdapter, efuseType, &fixPkt, &efuse_addr, bPseudoTest))
2283 return _FALSE;
2284 }
2285 else
2286 {
2287 bRet = _TRUE;
2288 break;
2289 }
2290 }
2291 else if ((tmp_header & 0x1F) == 0x0F) //wrong extended header
2292 {
2293 efuse_addr+=2;
2294 continue;
2295 }
2296 }
2297
2298 *pAddr = efuse_addr;
2299 return bRet;
2300 }
2301
2302 static BOOLEAN
hal_EfusePgPacketWrite1ByteHeader(IN PADAPTER pAdapter,IN u8 efuseType,IN u16 * pAddr,IN PPGPKT_STRUCT pTargetPkt,IN BOOLEAN bPseudoTest)2303 hal_EfusePgPacketWrite1ByteHeader(
2304 IN PADAPTER pAdapter,
2305 IN u8 efuseType,
2306 IN u16 *pAddr,
2307 IN PPGPKT_STRUCT pTargetPkt,
2308 IN BOOLEAN bPseudoTest)
2309 {
2310 BOOLEAN bRet=_FALSE;
2311 u8 pg_header=0, tmp_header=0;
2312 u16 efuse_addr=*pAddr;
2313 u8 repeatcnt=0;
2314
2315 //RTPRINT(FEEPROM, EFUSE_PG, ("Wirte 1byte header\n"));
2316 pg_header = ((pTargetPkt->offset << 4) & 0xf0) |pTargetPkt->word_en;
2317
2318 efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest);
2319 PHY_SetMacReg(pAdapter, EFUSE_TEST, BIT26, 0);
2320
2321 efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest);
2322 PHY_SetMacReg(pAdapter, EFUSE_TEST, BIT26, 1);
2323
2324 while(tmp_header == 0xFF || pg_header != tmp_header)
2325 {
2326 if(repeatcnt++ > EFUSE_REPEAT_THRESHOLD_)
2327 {
2328 return _FALSE;
2329 }
2330 efuse_OneByteWrite(pAdapter,efuse_addr, pg_header, bPseudoTest);
2331 efuse_OneByteRead(pAdapter,efuse_addr, &tmp_header, bPseudoTest);
2332 }
2333
2334 if(pg_header == tmp_header)
2335 {
2336 bRet = _TRUE;
2337 }
2338 else
2339 {
2340 PGPKT_STRUCT fixPkt;
2341 //RTPRINT(FEEPROM, EFUSE_PG, ("Error condition for fixed PG packet, need to cover the existed data\n"));
2342 fixPkt.offset = (tmp_header>>4) & 0x0F;
2343 fixPkt.word_en = tmp_header & 0x0F;
2344 fixPkt.word_cnts = Efuse_CalculateWordCnts(fixPkt.word_en);
2345 if(!hal_EfuseFixHeaderProcess(pAdapter, efuseType, &fixPkt, &efuse_addr, bPseudoTest))
2346 return _FALSE;
2347 }
2348
2349 *pAddr = efuse_addr;
2350 return bRet;
2351 }
2352
2353 static BOOLEAN
hal_EfusePgPacketWriteData(IN PADAPTER pAdapter,IN u8 efuseType,IN u16 * pAddr,IN PPGPKT_STRUCT pTargetPkt,IN BOOLEAN bPseudoTest)2354 hal_EfusePgPacketWriteData(
2355 IN PADAPTER pAdapter,
2356 IN u8 efuseType,
2357 IN u16 *pAddr,
2358 IN PPGPKT_STRUCT pTargetPkt,
2359 IN BOOLEAN bPseudoTest)
2360 {
2361 BOOLEAN bRet=_FALSE;
2362 u16 efuse_addr=*pAddr;
2363 u8 badworden=0;
2364 u32 PgWriteSuccess=0;
2365
2366 badworden = 0x0f;
2367 badworden = Efuse_WordEnableDataWrite(pAdapter, efuse_addr+1, pTargetPkt->word_en, pTargetPkt->data, bPseudoTest);
2368 if(badworden == 0x0F)
2369 {
2370 // write ok
2371 //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfusePgPacketWriteData ok!!\n"));
2372 return _TRUE;
2373 }
2374 else
2375 {
2376 //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfusePgPacketWriteData Fail!!\n"));
2377 //reorganize other pg packet
2378
2379 PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest);
2380
2381 if(!PgWriteSuccess)
2382 return _FALSE;
2383 else
2384 return _TRUE;
2385 }
2386
2387 return bRet;
2388 }
2389
2390 static BOOLEAN
hal_EfusePgPacketWriteHeader(IN PADAPTER pAdapter,IN u8 efuseType,IN u16 * pAddr,IN PPGPKT_STRUCT pTargetPkt,IN BOOLEAN bPseudoTest)2391 hal_EfusePgPacketWriteHeader(
2392 IN PADAPTER pAdapter,
2393 IN u8 efuseType,
2394 IN u16 *pAddr,
2395 IN PPGPKT_STRUCT pTargetPkt,
2396 IN BOOLEAN bPseudoTest)
2397 {
2398 BOOLEAN bRet=_FALSE;
2399
2400 if(pTargetPkt->offset >= EFUSE_MAX_SECTION_BASE)
2401 {
2402 bRet = hal_EfusePgPacketWrite2ByteHeader(pAdapter, efuseType, pAddr, pTargetPkt, bPseudoTest);
2403 }
2404 else
2405 {
2406 bRet = hal_EfusePgPacketWrite1ByteHeader(pAdapter, efuseType, pAddr, pTargetPkt, bPseudoTest);
2407 }
2408
2409 return bRet;
2410 }
2411
2412 static BOOLEAN
wordEnMatched(IN PPGPKT_STRUCT pTargetPkt,IN PPGPKT_STRUCT pCurPkt,IN u8 * pWden)2413 wordEnMatched(
2414 IN PPGPKT_STRUCT pTargetPkt,
2415 IN PPGPKT_STRUCT pCurPkt,
2416 IN u8 *pWden
2417 )
2418 {
2419 u8 match_word_en = 0x0F; // default all words are disabled
2420 u8 i;
2421
2422 // check if the same words are enabled both target and current PG packet
2423 if( ((pTargetPkt->word_en & BIT0) == 0) &&
2424 ((pCurPkt->word_en & BIT0) == 0) )
2425 {
2426 match_word_en &= ~BIT0; // enable word 0
2427 }
2428 if( ((pTargetPkt->word_en & BIT1) == 0) &&
2429 ((pCurPkt->word_en & BIT1) == 0) )
2430 {
2431 match_word_en &= ~BIT1; // enable word 1
2432 }
2433 if( ((pTargetPkt->word_en & BIT2) == 0) &&
2434 ((pCurPkt->word_en & BIT2) == 0) )
2435 {
2436 match_word_en &= ~BIT2; // enable word 2
2437 }
2438 if( ((pTargetPkt->word_en & BIT3) == 0) &&
2439 ((pCurPkt->word_en & BIT3) == 0) )
2440 {
2441 match_word_en &= ~BIT3; // enable word 3
2442 }
2443
2444 *pWden = match_word_en;
2445
2446 if(match_word_en != 0xf)
2447 return _TRUE;
2448 else
2449 return _FALSE;
2450 }
2451
2452 static BOOLEAN
hal_EfuseCheckIfDatafollowed(IN PADAPTER pAdapter,IN u8 word_cnts,IN u16 startAddr,IN BOOLEAN bPseudoTest)2453 hal_EfuseCheckIfDatafollowed(
2454 IN PADAPTER pAdapter,
2455 IN u8 word_cnts,
2456 IN u16 startAddr,
2457 IN BOOLEAN bPseudoTest
2458 )
2459 {
2460 BOOLEAN bRet=_FALSE;
2461 u8 i, efuse_data;
2462
2463 for(i=0; i<(word_cnts*2) ; i++)
2464 {
2465 if(efuse_OneByteRead(pAdapter, (startAddr+i) ,&efuse_data, bPseudoTest)&&(efuse_data != 0xFF))
2466 bRet = _TRUE;
2467 }
2468
2469 return bRet;
2470 }
2471
2472 static BOOLEAN
hal_EfusePartialWriteCheck(IN PADAPTER pAdapter,IN u8 efuseType,IN u16 * pAddr,IN PPGPKT_STRUCT pTargetPkt,IN BOOLEAN bPseudoTest)2473 hal_EfusePartialWriteCheck(
2474 IN PADAPTER pAdapter,
2475 IN u8 efuseType,
2476 IN u16 *pAddr,
2477 IN PPGPKT_STRUCT pTargetPkt,
2478 IN BOOLEAN bPseudoTest
2479 )
2480 {
2481 BOOLEAN bRet=_FALSE;
2482 u8 i, efuse_data=0, cur_header=0;
2483 u8 new_wden=0, matched_wden=0, badworden=0;
2484 u16 startAddr=0, efuse_max_available_len=0, efuse_max=0;
2485 PGPKT_STRUCT curPkt;
2486
2487 EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_BANK, (PVOID)&efuse_max_available_len, bPseudoTest);
2488 EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&efuse_max, bPseudoTest);
2489
2490 if(efuseType == EFUSE_WIFI)
2491 {
2492 if(bPseudoTest)
2493 {
2494 startAddr = (u16)(fakeEfuseUsedBytes%EFUSE_REAL_CONTENT_LEN);
2495 }
2496 else
2497 {
2498 rtw_hal_get_hwreg(pAdapter, HW_VAR_EFUSE_BYTES, (u8 *)&startAddr);
2499 startAddr%=EFUSE_REAL_CONTENT_LEN;
2500 }
2501 }
2502 else
2503 {
2504 if(bPseudoTest)
2505 {
2506 startAddr = (u16)(fakeBTEfuseUsedBytes%EFUSE_REAL_CONTENT_LEN);
2507 }
2508 else
2509 {
2510 startAddr = (u16)(BTEfuseUsedBytes%EFUSE_REAL_CONTENT_LEN);
2511 }
2512 }
2513 //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfusePartialWriteCheck(), startAddr=%d\n", startAddr));
2514
2515 while(1)
2516 {
2517 if(startAddr >= efuse_max_available_len)
2518 {
2519 bRet = _FALSE;
2520 break;
2521 }
2522
2523 if(efuse_OneByteRead(pAdapter, startAddr, &efuse_data, bPseudoTest) && (efuse_data!=0xFF))
2524 {
2525 if(EXT_HEADER(efuse_data))
2526 {
2527 cur_header = efuse_data;
2528 startAddr++;
2529 efuse_OneByteRead(pAdapter, startAddr, &efuse_data, bPseudoTest);
2530 if(ALL_WORDS_DISABLED(efuse_data))
2531 {
2532 //RTPRINT(FEEPROM, EFUSE_PG, ("Error condition, all words disabled"));
2533 bRet = _FALSE;
2534 break;
2535 }
2536 else
2537 {
2538 curPkt.offset = ((cur_header & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1);
2539 curPkt.word_en = efuse_data & 0x0F;
2540 }
2541 }
2542 else
2543 {
2544 cur_header = efuse_data;
2545 curPkt.offset = (cur_header>>4) & 0x0F;
2546 curPkt.word_en = cur_header & 0x0F;
2547 }
2548
2549 curPkt.word_cnts = Efuse_CalculateWordCnts(curPkt.word_en);
2550 // if same header is found but no data followed
2551 // write some part of data followed by the header.
2552 if( (curPkt.offset == pTargetPkt->offset) &&
2553 (!hal_EfuseCheckIfDatafollowed(pAdapter, curPkt.word_cnts, startAddr+1, bPseudoTest)) &&
2554 wordEnMatched(pTargetPkt, &curPkt, &matched_wden) )
2555 {
2556 //RTPRINT(FEEPROM, EFUSE_PG, ("Need to partial write data by the previous wrote header\n"));
2557 // Here to write partial data
2558 badworden = Efuse_WordEnableDataWrite(pAdapter, startAddr+1, matched_wden, pTargetPkt->data, bPseudoTest);
2559 if(badworden != 0x0F)
2560 {
2561 u32 PgWriteSuccess=0;
2562 // if write fail on some words, write these bad words again
2563
2564 PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest);
2565
2566 if(!PgWriteSuccess)
2567 {
2568 bRet = _FALSE; // write fail, return
2569 break;
2570 }
2571 }
2572 // partial write ok, update the target packet for later use
2573 for(i=0; i<4; i++)
2574 {
2575 if((matched_wden & (0x1<<i)) == 0) // this word has been written
2576 {
2577 pTargetPkt->word_en |= (0x1<<i); // disable the word
2578 }
2579 }
2580 pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en);
2581 }
2582 // read from next header
2583 startAddr = startAddr + (curPkt.word_cnts*2) +1;
2584 }
2585 else
2586 {
2587 // not used header, 0xff
2588 *pAddr = startAddr;
2589 //RTPRINT(FEEPROM, EFUSE_PG, ("Started from unused header offset=%d\n", startAddr));
2590 bRet = _TRUE;
2591 break;
2592 }
2593 }
2594 return bRet;
2595 }
2596
2597 static BOOLEAN
hal_EfusePgCheckAvailableAddr(IN PADAPTER pAdapter,IN u8 efuseType,IN BOOLEAN bPseudoTest)2598 hal_EfusePgCheckAvailableAddr(
2599 IN PADAPTER pAdapter,
2600 IN u8 efuseType,
2601 IN BOOLEAN bPseudoTest
2602 )
2603 {
2604 u16 efuse_max_available_len=0;
2605
2606 //Change to check TYPE_EFUSE_MAP_LEN ,beacuse 8188E raw 256,logic map over 256.
2607 EFUSE_GetEfuseDefinition(pAdapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&efuse_max_available_len, _FALSE);
2608
2609 //EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&efuse_max_available_len, bPseudoTest);
2610 //RTPRINT(FEEPROM, EFUSE_PG, ("efuse_max_available_len = %d\n", efuse_max_available_len));
2611
2612 if(Efuse_GetCurrentSize(pAdapter, efuseType, bPseudoTest) >= efuse_max_available_len)
2613 {
2614 //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfusePgCheckAvailableAddr error!!\n"));
2615 return _FALSE;
2616 }
2617 return _TRUE;
2618 }
2619
2620 static VOID
hal_EfuseConstructPGPkt(IN u8 offset,IN u8 word_en,IN u8 * pData,IN PPGPKT_STRUCT pTargetPkt)2621 hal_EfuseConstructPGPkt(
2622 IN u8 offset,
2623 IN u8 word_en,
2624 IN u8 *pData,
2625 IN PPGPKT_STRUCT pTargetPkt
2626
2627 )
2628 {
2629 _rtw_memset((PVOID)pTargetPkt->data, 0xFF, sizeof(u8)*8);
2630 pTargetPkt->offset = offset;
2631 pTargetPkt->word_en= word_en;
2632 efuse_WordEnableDataRead(word_en, pData, pTargetPkt->data);
2633 pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en);
2634
2635 //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfuseConstructPGPkt(), targetPkt, offset=%d, word_en=0x%x, word_cnts=%d\n", pTargetPkt->offset, pTargetPkt->word_en, pTargetPkt->word_cnts));
2636 }
2637
2638 static BOOLEAN
hal_EfusePgPacketWrite_BT(IN PADAPTER pAdapter,IN u8 offset,IN u8 word_en,IN u8 * pData,IN BOOLEAN bPseudoTest)2639 hal_EfusePgPacketWrite_BT(
2640 IN PADAPTER pAdapter,
2641 IN u8 offset,
2642 IN u8 word_en,
2643 IN u8 *pData,
2644 IN BOOLEAN bPseudoTest
2645 )
2646 {
2647 PGPKT_STRUCT targetPkt;
2648 u16 startAddr=0;
2649 u8 efuseType=EFUSE_BT;
2650
2651 if(!hal_EfusePgCheckAvailableAddr(pAdapter, efuseType, bPseudoTest))
2652 return _FALSE;
2653
2654 hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt);
2655
2656 if(!hal_EfusePartialWriteCheck(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
2657 return _FALSE;
2658
2659 if(!hal_EfusePgPacketWriteHeader(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
2660 return _FALSE;
2661
2662 if(!hal_EfusePgPacketWriteData(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
2663 return _FALSE;
2664
2665 return _TRUE;
2666 }
2667
2668 static BOOLEAN
hal_EfusePgPacketWrite_8188e(IN PADAPTER pAdapter,IN u8 offset,IN u8 word_en,IN u8 * pData,IN BOOLEAN bPseudoTest)2669 hal_EfusePgPacketWrite_8188e(
2670 IN PADAPTER pAdapter,
2671 IN u8 offset,
2672 IN u8 word_en,
2673 IN u8 *pData,
2674 IN BOOLEAN bPseudoTest
2675 )
2676 {
2677 PGPKT_STRUCT targetPkt;
2678 u16 startAddr=0;
2679 u8 efuseType=EFUSE_WIFI;
2680
2681 if(!hal_EfusePgCheckAvailableAddr(pAdapter, efuseType, bPseudoTest))
2682 return _FALSE;
2683
2684 hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt);
2685
2686 if(!hal_EfusePartialWriteCheck(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
2687 return _FALSE;
2688
2689 if(!hal_EfusePgPacketWriteHeader(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
2690 return _FALSE;
2691
2692 if(!hal_EfusePgPacketWriteData(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest))
2693 return _FALSE;
2694
2695 return _TRUE;
2696 }
2697
2698
2699 static int
Hal_EfusePgPacketWrite_Pseudo(IN PADAPTER pAdapter,IN u8 offset,IN u8 word_en,IN u8 * data,IN BOOLEAN bPseudoTest)2700 Hal_EfusePgPacketWrite_Pseudo(IN PADAPTER pAdapter,
2701 IN u8 offset,
2702 IN u8 word_en,
2703 IN u8 *data,
2704 IN BOOLEAN bPseudoTest)
2705 {
2706 int ret;
2707
2708 ret = hal_EfusePgPacketWrite_8188e(pAdapter, offset, word_en, data, bPseudoTest);
2709
2710 return ret;
2711 }
2712
2713 static int
Hal_EfusePgPacketWrite(IN PADAPTER pAdapter,IN u8 offset,IN u8 word_en,IN u8 * data,IN BOOLEAN bPseudoTest)2714 Hal_EfusePgPacketWrite(IN PADAPTER pAdapter,
2715 IN u8 offset,
2716 IN u8 word_en,
2717 IN u8 *data,
2718 IN BOOLEAN bPseudoTest)
2719 {
2720 int ret=0;
2721 ret = hal_EfusePgPacketWrite_8188e(pAdapter, offset, word_en, data, bPseudoTest);
2722
2723
2724 return ret;
2725 }
2726
2727 static int
rtl8188e_Efuse_PgPacketWrite(IN PADAPTER pAdapter,IN u8 offset,IN u8 word_en,IN u8 * data,IN BOOLEAN bPseudoTest)2728 rtl8188e_Efuse_PgPacketWrite(IN PADAPTER pAdapter,
2729 IN u8 offset,
2730 IN u8 word_en,
2731 IN u8 *data,
2732 IN BOOLEAN bPseudoTest)
2733 {
2734 int ret;
2735
2736 if(bPseudoTest)
2737 {
2738 ret = Hal_EfusePgPacketWrite_Pseudo(pAdapter, offset, word_en, data, bPseudoTest);
2739 }
2740 else
2741 {
2742 ret = Hal_EfusePgPacketWrite(pAdapter, offset, word_en, data, bPseudoTest);
2743 }
2744 return ret;
2745 }
2746
read_chip_version_8188e(PADAPTER padapter)2747 static void read_chip_version_8188e(PADAPTER padapter)
2748 {
2749 u32 value32;
2750 HAL_DATA_TYPE *pHalData;
2751
2752 pHalData = GET_HAL_DATA(padapter);
2753
2754 value32 = rtw_read32(padapter, REG_SYS_CFG);
2755 pHalData->VersionID.ICType = CHIP_8188E ;
2756 pHalData->VersionID.ChipType = ((value32 & RTL_ID) ? TEST_CHIP : NORMAL_CHIP);
2757
2758 pHalData->VersionID.RFType = RF_TYPE_1T1R;
2759 pHalData->VersionID.VendorType = ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : CHIP_VENDOR_TSMC);
2760 pHalData->VersionID.CUTVersion = (value32 & CHIP_VER_RTL_MASK)>>CHIP_VER_RTL_SHIFT; // IC version (CUT)
2761
2762 // For regulator mode. by tynli. 2011.01.14
2763 pHalData->RegulatorMode = ((value32 & TRP_BT_EN) ? RT_LDO_REGULATOR : RT_SWITCHING_REGULATOR);
2764
2765 pHalData->VersionID.ROMVer = 0; // ROM code version.
2766 pHalData->MultiFunc = RT_MULTI_FUNC_NONE;
2767
2768 rtw_hal_config_rftype(padapter);
2769
2770 #if 1
2771 dump_chip_info(pHalData->VersionID);
2772 #endif
2773
2774 }
2775
rtl8188e_start_thread(_adapter * padapter)2776 void rtl8188e_start_thread(_adapter *padapter)
2777 {
2778 #if defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)
2779 #ifndef CONFIG_SDIO_TX_TASKLET
2780 struct xmit_priv *xmitpriv = &padapter->xmitpriv;
2781
2782 xmitpriv->SdioXmitThread = kthread_run(rtl8188es_xmit_thread, padapter, "RTWHALXT");
2783 if (IS_ERR(xmitpriv->SdioXmitThread))
2784 {
2785 RT_TRACE(_module_hal_xmit_c_, _drv_err_, ("%s: start rtl8188es_xmit_thread FAIL!!\n", __FUNCTION__));
2786 }
2787 #endif
2788 #endif
2789 }
2790
rtl8188e_stop_thread(_adapter * padapter)2791 void rtl8188e_stop_thread(_adapter *padapter)
2792 {
2793 #if defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI)
2794 #ifndef CONFIG_SDIO_TX_TASKLET
2795 struct xmit_priv *xmitpriv = &padapter->xmitpriv;
2796
2797 // stop xmit_buf_thread
2798 if (xmitpriv->SdioXmitThread ) {
2799 _rtw_up_sema(&xmitpriv->SdioXmitSema);
2800 /*_rtw_down_sema(&xmitpriv->SdioXmitTerminateSema);*/
2801 rtw_wait_for_thread_stop(&xmitpriv->sdio_xmit_thread_comp);
2802 xmitpriv->SdioXmitThread = 0;
2803 }
2804 #endif
2805 #endif
2806 }
hal_notch_filter_8188e(_adapter * adapter,bool enable)2807 void hal_notch_filter_8188e(_adapter *adapter, bool enable)
2808 {
2809 if (enable) {
2810 DBG_871X("Enable notch filter\n");
2811 rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) | BIT1);
2812 } else {
2813 DBG_871X("Disable notch filter\n");
2814 rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) & ~BIT1);
2815 }
2816 }
2817
UpdateHalRAMask8188E(PADAPTER padapter,u32 mac_id,u8 rssi_level)2818 void UpdateHalRAMask8188E(PADAPTER padapter, u32 mac_id, u8 rssi_level)
2819 {
2820 u32 mask,rate_bitmap;
2821 u8 shortGIrate = _FALSE;
2822 struct sta_info *psta;
2823 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
2824 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
2825 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
2826
2827 if (mac_id >= NUM_STA) //CAM_SIZE
2828 {
2829 return;
2830 }
2831
2832 psta = pmlmeinfo->FW_sta_info[mac_id].psta;
2833 if(psta == NULL)
2834 {
2835 return;
2836 }
2837
2838 shortGIrate = query_ra_short_GI(psta);
2839
2840 mask = psta->ra_mask;
2841
2842 rate_bitmap = 0xffffffff;
2843 rate_bitmap = ODM_Get_Rate_Bitmap(&pHalData->odmpriv,mac_id,mask,rssi_level);
2844
2845
2846 DBG_871X("%s => mac_id:%d, rate_id:%d, networkType:0x%02x, mask:0x%08x\n\t ==> rssi_level:%d, rate_bitmap:0x%08x\n",
2847 __FUNCTION__,mac_id,psta->raid,psta->wireless_mode,mask,rssi_level,rate_bitmap);
2848
2849 mask &= rate_bitmap;
2850
2851 if(pHalData->fw_ractrl == _TRUE)
2852 {
2853 u8 arg[4] ={0};
2854
2855 arg[0] = mac_id;//MACID
2856 arg[1] = psta->raid;
2857 arg[2] = shortGIrate;
2858 arg[3] = psta->init_rate;
2859 rtl8188e_set_raid_cmd(padapter, mask,arg);
2860 }
2861 else
2862 {
2863
2864 #if(RATE_ADAPTIVE_SUPPORT == 1)
2865
2866 ODM_RA_UpdateRateInfo_8188E(
2867 &(pHalData->odmpriv),
2868 mac_id,
2869 psta->raid,
2870 mask,
2871 shortGIrate
2872 );
2873
2874 #endif
2875 }
2876 }
2877
rtl8188e_init_default_value(_adapter * adapter)2878 void rtl8188e_init_default_value(_adapter *adapter)
2879 {
2880 HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
2881
2882 /* hal capability values */
2883 hal_data->macid_num = MACID_NUM_88E;
2884 hal_data->cam_entry_num = CAM_ENTRY_NUM_88E;
2885 adapter->registrypriv.wireless_mode = WIRELESS_11BG_24N;
2886 }
2887
rtl8188e_set_hal_ops(struct hal_ops * pHalFunc)2888 void rtl8188e_set_hal_ops(struct hal_ops *pHalFunc)
2889 {
2890 pHalFunc->dm_init = &rtl8188e_init_dm_priv;
2891 pHalFunc->dm_deinit = &rtl8188e_deinit_dm_priv;
2892
2893 pHalFunc->read_chip_version = read_chip_version_8188e;
2894
2895 pHalFunc->UpdateRAMaskHandler = &UpdateHalRAMask8188E;
2896
2897 pHalFunc->set_bwmode_handler = &PHY_SetBWMode8188E;
2898 pHalFunc->set_channel_handler = &PHY_SwChnl8188E;
2899 pHalFunc->set_chnl_bw_handler = &PHY_SetSwChnlBWMode8188E;
2900
2901 pHalFunc->set_tx_power_level_handler = &PHY_SetTxPowerLevel8188E;
2902 pHalFunc->get_tx_power_level_handler = &PHY_GetTxPowerLevel8188E;
2903
2904 pHalFunc->hal_dm_watchdog = &rtl8188e_HalDmWatchDog;
2905
2906 pHalFunc->Add_RateATid = &rtl8188e_Add_RateATid;
2907
2908 pHalFunc->run_thread= &rtl8188e_start_thread;
2909 pHalFunc->cancel_thread= &rtl8188e_stop_thread;
2910
2911 #ifdef CONFIG_ANTENNA_DIVERSITY
2912 pHalFunc->AntDivBeforeLinkHandler = &AntDivBeforeLink8188E;
2913 pHalFunc->AntDivCompareHandler = &AntDivCompare8188E;
2914 #endif
2915
2916 pHalFunc->read_bbreg = &PHY_QueryBBReg8188E;
2917 pHalFunc->write_bbreg = &PHY_SetBBReg8188E;
2918 pHalFunc->read_rfreg = &PHY_QueryRFReg8188E;
2919 pHalFunc->write_rfreg = &PHY_SetRFReg8188E;
2920
2921
2922 // Efuse related function
2923 pHalFunc->EfusePowerSwitch = &rtl8188e_EfusePowerSwitch;
2924 pHalFunc->ReadEFuse = &rtl8188e_ReadEFuse;
2925 pHalFunc->EFUSEGetEfuseDefinition = &rtl8188e_EFUSE_GetEfuseDefinition;
2926 pHalFunc->EfuseGetCurrentSize = &rtl8188e_EfuseGetCurrentSize;
2927 pHalFunc->Efuse_PgPacketRead = &rtl8188e_Efuse_PgPacketRead;
2928 pHalFunc->Efuse_PgPacketWrite = &rtl8188e_Efuse_PgPacketWrite;
2929 pHalFunc->Efuse_WordEnableDataWrite = &rtl8188e_Efuse_WordEnableDataWrite;
2930
2931 #ifdef DBG_CONFIG_ERROR_DETECT
2932 pHalFunc->sreset_init_value = &sreset_init_value;
2933 pHalFunc->sreset_reset_value = &sreset_reset_value;
2934 pHalFunc->silentreset = &sreset_reset;
2935 pHalFunc->sreset_xmit_status_check = &rtl8188e_sreset_xmit_status_check;
2936 pHalFunc->sreset_linked_status_check = &rtl8188e_sreset_linked_status_check;
2937 pHalFunc->sreset_get_wifi_status = &sreset_get_wifi_status;
2938 pHalFunc->sreset_inprogress= &sreset_inprogress;
2939 #endif //DBG_CONFIG_ERROR_DETECT
2940
2941 pHalFunc->GetHalODMVarHandler = GetHalODMVar;
2942 pHalFunc->SetHalODMVarHandler = SetHalODMVar;
2943
2944 #ifdef CONFIG_IOL
2945 pHalFunc->IOL_exec_cmds_sync = &rtl8188e_IOL_exec_cmds_sync;
2946 #endif
2947
2948 pHalFunc->hal_notch_filter = &hal_notch_filter_8188e;
2949 pHalFunc->fill_h2c_cmd = &FillH2CCmd_88E;
2950 pHalFunc->fill_fake_txdesc = &rtl8188e_fill_fake_txdesc;
2951 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
2952 pHalFunc->hal_set_wowlan_fw = &SetFwRelatedForWoWLAN8188ES;
2953 #endif
2954 pHalFunc->hal_get_tx_buff_rsvd_page_num = &GetTxBufferRsvdPageNum8188E;
2955 }
2956
GetEEPROMSize8188E(PADAPTER padapter)2957 u8 GetEEPROMSize8188E(PADAPTER padapter)
2958 {
2959 u8 size = 0;
2960 u32 cr;
2961
2962 cr = rtw_read16(padapter, REG_9346CR);
2963 // 6: EEPROM used is 93C46, 4: boot from E-Fuse.
2964 size = (cr & BOOT_FROM_EEPROM) ? 6 : 4;
2965
2966 MSG_8192C("EEPROM type is %s\n", size==4 ? "E-FUSE" : "93C46");
2967
2968 return size;
2969 }
2970
2971 #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_PCI_HCI) || defined(CONFIG_GSPI_HCI)
2972 //-------------------------------------------------------------------------
2973 //
2974 // LLT R/W/Init function
2975 //
2976 //-------------------------------------------------------------------------
_LLTWrite(PADAPTER padapter,u32 address,u32 data)2977 s32 _LLTWrite(PADAPTER padapter, u32 address, u32 data)
2978 {
2979 s32 status = _SUCCESS;
2980 s8 count = POLLING_LLT_THRESHOLD;
2981 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
2982
2983 rtw_write32(padapter, REG_LLT_INIT, value);
2984
2985 //polling
2986 do {
2987 value = rtw_read32(padapter, REG_LLT_INIT);
2988 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) {
2989 break;
2990 }
2991 } while (--count);
2992
2993 if(count<=0){
2994 DBG_871X("Failed to polling write LLT done at address %d!\n", address);
2995 status = _FAIL;
2996 }
2997
2998 return status;
2999 }
3000
_LLTRead(PADAPTER padapter,u32 address)3001 u8 _LLTRead(PADAPTER padapter, u32 address)
3002 {
3003 s32 count = POLLING_LLT_THRESHOLD;
3004 u32 value = _LLT_INIT_ADDR(address) | _LLT_OP(_LLT_READ_ACCESS);
3005 u16 LLTReg = REG_LLT_INIT;
3006
3007
3008 rtw_write32(padapter, LLTReg, value);
3009
3010 //polling and get value
3011 do {
3012 value = rtw_read32(padapter, LLTReg);
3013 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) {
3014 return (u8)value;
3015 }
3016 } while (--count);
3017
3018 if (count <=0 ) {
3019 RT_TRACE(_module_hal_init_c_, _drv_err_, ("Failed to polling read LLT done at address %d!\n", address));
3020 }
3021
3022
3023 return 0xFF;
3024 }
3025
InitLLTTable(PADAPTER padapter,u8 txpktbuf_bndy)3026 s32 InitLLTTable(PADAPTER padapter, u8 txpktbuf_bndy)
3027 {
3028 s32 status = _FAIL;
3029 u32 i;
3030 u32 Last_Entry_Of_TxPktBuf = LAST_ENTRY_OF_TX_PKT_BUFFER_8188E(padapter);// 176, 22k
3031 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
3032
3033 #if defined(CONFIG_IOL_LLT)
3034 if(rtw_IOL_applied(padapter))
3035 {
3036 status = iol_InitLLTTable(padapter, txpktbuf_bndy);
3037 }
3038 else
3039 #endif
3040 {
3041 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
3042 status = _LLTWrite(padapter, i, i + 1);
3043 if (_SUCCESS != status) {
3044 return status;
3045 }
3046 }
3047
3048 // end of list
3049 status = _LLTWrite(padapter, (txpktbuf_bndy - 1), 0xFF);
3050 if (_SUCCESS != status) {
3051 return status;
3052 }
3053
3054 // Make the other pages as ring buffer
3055 // This ring buffer is used as beacon buffer if we config this MAC as two MAC transfer.
3056 // Otherwise used as local loopback buffer.
3057 for (i = txpktbuf_bndy; i < Last_Entry_Of_TxPktBuf; i++) {
3058 status = _LLTWrite(padapter, i, (i + 1));
3059 if (_SUCCESS != status) {
3060 return status;
3061 }
3062 }
3063
3064 // Let last entry point to the start entry of ring buffer
3065 status = _LLTWrite(padapter, Last_Entry_Of_TxPktBuf, txpktbuf_bndy);
3066 if (_SUCCESS != status) {
3067 return status;
3068 }
3069 }
3070
3071 return status;
3072 }
3073 #endif
3074
3075
3076 void
Hal_InitPGData88E(PADAPTER padapter)3077 Hal_InitPGData88E(PADAPTER padapter)
3078 {
3079
3080 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
3081 u32 i;
3082 u16 value16;
3083
3084 if(_FALSE == pHalData->bautoload_fail_flag)
3085 { // autoload OK.
3086 if (is_boot_from_eeprom(padapter))
3087 {
3088 // Read all Content from EEPROM or EFUSE.
3089 for(i = 0; i < HWSET_MAX_SIZE; i += 2)
3090 {
3091 // value16 = EF2Byte(ReadEEprom(pAdapter, (u2Byte) (i>>1)));
3092 // *((u16*)(&PROMContent[i])) = value16;
3093 }
3094 }
3095 else
3096 {
3097 // Read EFUSE real map to shadow.
3098 EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, _FALSE);
3099 }
3100 }
3101 else
3102 {//autoload fail
3103 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("AutoLoad Fail reported from CR9346!!\n"));
3104 // pHalData->AutoloadFailFlag = _TRUE;
3105 //update to default value 0xFF
3106 if (!is_boot_from_eeprom(padapter))
3107 EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, _FALSE);
3108 }
3109
3110 #ifdef CONFIG_EFUSE_CONFIG_FILE
3111 if (check_phy_efuse_tx_power_info_valid(padapter) == _FALSE) {
3112 if (Hal_readPGDataFromConfigFile(padapter) != _SUCCESS)
3113 DBG_871X_LEVEL(_drv_err_, "invalid phy efuse and read from file fail, will use driver default!!\n");
3114 }
3115 #endif
3116 }
3117
3118 void
Hal_EfuseParseIDCode88E(IN PADAPTER padapter,IN u8 * hwinfo)3119 Hal_EfuseParseIDCode88E(
3120 IN PADAPTER padapter,
3121 IN u8 *hwinfo
3122 )
3123 {
3124 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
3125 u16 EEPROMId;
3126
3127
3128 // Checl 0x8129 again for making sure autoload status!!
3129 EEPROMId = le16_to_cpu(*((u16*)hwinfo));
3130 if (EEPROMId != RTL_EEPROM_ID)
3131 {
3132 DBG_8192C("EEPROM ID(%#x) is invalid!!\n", EEPROMId);
3133 pHalData->bautoload_fail_flag = _TRUE;
3134 }
3135 else
3136 {
3137 pHalData->bautoload_fail_flag = _FALSE;
3138 }
3139
3140 DBG_871X("EEPROM ID=0x%04x\n", EEPROMId);
3141 }
3142
3143 static void
Hal_ReadPowerValueFromPROM_8188E(IN PADAPTER padapter,IN PTxPowerInfo24G pwrInfo24G,IN u8 * PROMContent,IN BOOLEAN AutoLoadFail)3144 Hal_ReadPowerValueFromPROM_8188E(
3145 IN PADAPTER padapter,
3146 IN PTxPowerInfo24G pwrInfo24G,
3147 IN u8* PROMContent,
3148 IN BOOLEAN AutoLoadFail
3149 )
3150 {
3151 u32 rfPath, eeAddr=EEPROM_TX_PWR_INX_88E, group,TxCount=0;
3152 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
3153
3154 _rtw_memset(pwrInfo24G, 0, sizeof(TxPowerInfo24G));
3155
3156 if(AutoLoadFail)
3157 {
3158 for(rfPath = 0 ; rfPath < pHalData->NumTotalRFPath ; rfPath++)
3159 {
3160 //2.4G default value
3161 for(group = 0 ; group < MAX_CHNL_GROUP_24G; group++)
3162 {
3163 pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
3164 pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
3165 }
3166 for(TxCount=0;TxCount<MAX_TX_COUNT;TxCount++)
3167 {
3168 if(TxCount==0)
3169 {
3170 pwrInfo24G->BW20_Diff[rfPath][0] = EEPROM_DEFAULT_24G_HT20_DIFF;
3171 pwrInfo24G->OFDM_Diff[rfPath][0] = EEPROM_DEFAULT_24G_OFDM_DIFF;
3172 }
3173 else
3174 {
3175 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
3176 pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
3177 pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
3178 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
3179 }
3180 }
3181
3182
3183 }
3184
3185 //pHalData->bNOPG = TRUE;
3186 return;
3187 }
3188
3189 for(rfPath = 0 ; rfPath < pHalData->NumTotalRFPath ; rfPath++)
3190 {
3191 //2.4G default value
3192 for(group = 0 ; group < MAX_CHNL_GROUP_24G; group++)
3193 {
3194 //printk(" IndexCCK_Base rfPath:%d group:%d,eeAddr:0x%02x ",rfPath,group,eeAddr);
3195 pwrInfo24G->IndexCCK_Base[rfPath][group] = PROMContent[eeAddr++];
3196 //printk(" IndexCCK_Base:%02x \n",pwrInfo24G->IndexCCK_Base[rfPath][group] );
3197 if(pwrInfo24G->IndexCCK_Base[rfPath][group] == 0xFF)
3198 {
3199 pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
3200 // pHalData->bNOPG = TRUE;
3201 }
3202 }
3203 for(group = 0 ; group < MAX_CHNL_GROUP_24G-1; group++)
3204 {
3205 //printk(" IndexBW40_Base rfPath:%d group:%d,eeAddr:0x%02x ",rfPath,group,eeAddr);
3206 pwrInfo24G->IndexBW40_Base[rfPath][group] = PROMContent[eeAddr++];
3207 //printk(" IndexBW40_Base: %02x \n",pwrInfo24G->IndexBW40_Base[rfPath][group] );
3208 if(pwrInfo24G->IndexBW40_Base[rfPath][group] == 0xFF)
3209 pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX;
3210 }
3211 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++)
3212 {
3213 if(TxCount==0)
3214 {
3215 pwrInfo24G->BW40_Diff[rfPath][TxCount] = 0;
3216 pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
3217 if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) /*4bit sign number to 8 bit sign number*/
3218 pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0;
3219
3220 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
3221 if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3) /*4bit sign number to 8 bit sign number*/
3222 pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0;
3223
3224 pwrInfo24G->CCK_Diff[rfPath][TxCount] = 0;
3225 eeAddr++;
3226 } else{
3227 pwrInfo24G->BW40_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
3228 if (pwrInfo24G->BW40_Diff[rfPath][TxCount] & BIT3) /*4bit sign number to 8 bit sign number*/
3229 pwrInfo24G->BW40_Diff[rfPath][TxCount] |= 0xF0;
3230
3231
3232 pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
3233 if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) /*4bit sign number to 8 bit sign number*/
3234 pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0;
3235 eeAddr++;
3236
3237 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
3238 if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3) /*4bit sign number to 8 bit sign number*/
3239 pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0;
3240
3241 pwrInfo24G->CCK_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
3242 if (pwrInfo24G->CCK_Diff[rfPath][TxCount] & BIT3) /*4bit sign number to 8 bit sign number*/
3243 pwrInfo24G->CCK_Diff[rfPath][TxCount] |= 0xF0;
3244
3245 eeAddr++;
3246 }
3247 }
3248
3249 }
3250
3251
3252 }
3253
3254 static u8
Hal_GetChnlGroup(IN u8 chnl)3255 Hal_GetChnlGroup(
3256 IN u8 chnl
3257 )
3258 {
3259 u8 group=0;
3260
3261 if (chnl < 3) // Cjanel 1-3
3262 group = 0;
3263 else if (chnl < 9) // Channel 4-9
3264 group = 1;
3265 else // Channel 10-14
3266 group = 2;
3267
3268 return group;
3269 }
3270 static u8
Hal_GetChnlGroup88E(IN u8 chnl,OUT u8 * pGroup)3271 Hal_GetChnlGroup88E(
3272 IN u8 chnl,
3273 OUT u8* pGroup
3274 )
3275 {
3276 u8 bIn24G=_TRUE;
3277
3278 if(chnl<=14)
3279 {
3280 bIn24G=_TRUE;
3281
3282 if (chnl < 3) // Chanel 1-2
3283 *pGroup = 0;
3284 else if (chnl < 6) // Channel 3-5
3285 *pGroup = 1;
3286 else if(chnl <9) // Channel 6-8
3287 *pGroup = 2;
3288 else if(chnl <12) // Channel 9-11
3289 *pGroup = 3;
3290 else if(chnl <14) // Channel 12-13
3291 *pGroup = 4;
3292 else if(chnl ==14) // Channel 14
3293 *pGroup = 5;
3294 else
3295 {
3296 //RT_TRACE(COMP_EFUSE,DBG_LOUD,("==>Hal_GetChnlGroup88E in 2.4 G, but Channel %d in Group not found \n",chnl));
3297 }
3298 }
3299 else
3300 {
3301 bIn24G=_FALSE;
3302
3303 if (chnl <=40)
3304 *pGroup = 0;
3305 else if (chnl <=48)
3306 *pGroup = 1;
3307 else if(chnl <=56)
3308 *pGroup = 2;
3309 else if(chnl <=64)
3310 *pGroup = 3;
3311 else if(chnl <=104)
3312 *pGroup = 4;
3313 else if(chnl <=112)
3314 *pGroup = 5;
3315 else if(chnl <=120)
3316 *pGroup = 5;
3317 else if(chnl <=128)
3318 *pGroup = 6;
3319 else if(chnl <=136)
3320 *pGroup = 7;
3321 else if(chnl <=144)
3322 *pGroup = 8;
3323 else if(chnl <=153)
3324 *pGroup = 9;
3325 else if(chnl <=161)
3326 *pGroup = 10;
3327 else if(chnl <=177)
3328 *pGroup = 11;
3329 else
3330 {
3331 //RT_TRACE(COMP_EFUSE,DBG_LOUD,("==>Hal_GetChnlGroup88E in 5G, but Channel %d in Group not found \n",chnl));
3332 }
3333
3334 }
3335 //RT_TRACE(COMP_EFUSE,DBG_LOUD,("<==Hal_GetChnlGroup88E, Channel = %d, bIn24G =%d,\n",chnl,bIn24G));
3336 return bIn24G;
3337 }
3338
Hal_ReadPowerSavingMode88E(PADAPTER padapter,IN u8 * hwinfo,IN BOOLEAN AutoLoadFail)3339 void Hal_ReadPowerSavingMode88E(
3340 PADAPTER padapter,
3341 IN u8* hwinfo,
3342 IN BOOLEAN AutoLoadFail
3343 )
3344 {
3345 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
3346 struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
3347 u8 tmpvalue;
3348
3349 if(AutoLoadFail){
3350 pwrctl->bHWPowerdown = _FALSE;
3351 pwrctl->bSupportRemoteWakeup = _FALSE;
3352 }
3353 else {
3354
3355 //hw power down mode selection , 0:rf-off / 1:power down
3356
3357 if(padapter->registrypriv.hwpdn_mode==2)
3358 pwrctl->bHWPowerdown = (hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & BIT4);
3359 else
3360 pwrctl->bHWPowerdown = padapter->registrypriv.hwpdn_mode;
3361
3362 // decide hw if support remote wakeup function
3363 // if hw supported, 8051 (SIE) will generate WeakUP signal( D+/D- toggle) when autoresume
3364 #ifdef CONFIG_USB_HCI
3365 pwrctl->bSupportRemoteWakeup = (hwinfo[EEPROM_USB_OPTIONAL_FUNCTION0] & BIT1)?_TRUE :_FALSE;
3366 #endif //CONFIG_USB_HCI
3367
3368 DBG_8192C("%s...bHWPwrPindetect(%x)-bHWPowerdown(%x) ,bSupportRemoteWakeup(%x)\n",__FUNCTION__,
3369 pwrctl->bHWPwrPindetect, pwrctl->bHWPowerdown, pwrctl->bSupportRemoteWakeup);
3370
3371 DBG_8192C("### PS params=> power_mgnt(%x),usbss_enable(%x) ###\n",padapter->registrypriv.power_mgnt,padapter->registrypriv.usbss_enable);
3372
3373 }
3374
3375 }
3376
3377 void
Hal_ReadTxPowerInfo88E(IN PADAPTER padapter,IN u8 * PROMContent,IN BOOLEAN AutoLoadFail)3378 Hal_ReadTxPowerInfo88E(
3379 IN PADAPTER padapter,
3380 IN u8* PROMContent,
3381 IN BOOLEAN AutoLoadFail
3382 )
3383 {
3384 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
3385 TxPowerInfo24G pwrInfo24G;
3386 u8 rfPath, ch, group=0, rfPathMax=1;
3387 u8 pwr, diff,bIn24G,TxCount;
3388
3389
3390 Hal_ReadPowerValueFromPROM_8188E(padapter, &pwrInfo24G, PROMContent, AutoLoadFail);
3391
3392 if(!AutoLoadFail)
3393 pHalData->bTXPowerDataReadFromEEPORM = TRUE;
3394
3395 //for(rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++)
3396 for(rfPath = 0 ; rfPath < pHalData->NumTotalRFPath ; rfPath++)
3397 {
3398 for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++)
3399 {
3400 bIn24G = Hal_GetChnlGroup88E(ch+1,&group);
3401 if(bIn24G)
3402 {
3403
3404 pHalData->Index24G_CCK_Base[rfPath][ch]=pwrInfo24G.IndexCCK_Base[rfPath][group];
3405
3406 if(ch==(14-1))
3407 pHalData->Index24G_BW40_Base[rfPath][ch]=pwrInfo24G.IndexBW40_Base[rfPath][4];
3408 else
3409 pHalData->Index24G_BW40_Base[rfPath][ch]=pwrInfo24G.IndexBW40_Base[rfPath][group];
3410 }
3411
3412 if(bIn24G)
3413 {
3414 DBG_871X("======= Path %d, Channel %d =======\n",rfPath,ch+1 );
3415 DBG_871X("Index24G_CCK_Base[%d][%d] = 0x%x\n",rfPath,ch+1 ,pHalData->Index24G_CCK_Base[rfPath][ch]);
3416 DBG_871X("Index24G_BW40_Base[%d][%d] = 0x%x\n",rfPath,ch+1 ,pHalData->Index24G_BW40_Base[rfPath][ch]);
3417 }
3418 }
3419
3420 for(TxCount=0;TxCount<MAX_TX_COUNT_8188E;TxCount++)
3421 {
3422 pHalData->CCK_24G_Diff[rfPath][TxCount]=pwrInfo24G.CCK_Diff[rfPath][TxCount];
3423 pHalData->OFDM_24G_Diff[rfPath][TxCount]=pwrInfo24G.OFDM_Diff[rfPath][TxCount];
3424 pHalData->BW20_24G_Diff[rfPath][TxCount]=pwrInfo24G.BW20_Diff[rfPath][TxCount];
3425 pHalData->BW40_24G_Diff[rfPath][TxCount]=pwrInfo24G.BW40_Diff[rfPath][TxCount];
3426 #if DBG
3427 DBG_871X("======= TxCount %d =======\n",TxCount );
3428 DBG_871X("CCK_24G_Diff[%d][%d]= %d\n",rfPath,TxCount,pHalData->CCK_24G_Diff[rfPath][TxCount]);
3429 DBG_871X("OFDM_24G_Diff[%d][%d]= %d\n",rfPath,TxCount,pHalData->OFDM_24G_Diff[rfPath][TxCount]);
3430 DBG_871X("BW20_24G_Diff[%d][%d]= %d\n",rfPath,TxCount,pHalData->BW20_24G_Diff[rfPath][TxCount]);
3431 DBG_871X("BW40_24G_Diff[%d][%d]= %d\n",rfPath,TxCount,pHalData->BW40_24G_Diff[rfPath][TxCount]);
3432 #endif
3433 }
3434 }
3435
3436
3437 // 2010/10/19 MH Add Regulator recognize for EU.
3438 if(!AutoLoadFail)
3439 {
3440 struct registry_priv *registry_par = &padapter->registrypriv;
3441
3442 if(PROMContent[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
3443 pHalData->EEPROMRegulatory = (EEPROM_DEFAULT_BOARD_OPTION&0x7); //bit0~2
3444 else
3445 pHalData->EEPROMRegulatory = (PROMContent[EEPROM_RF_BOARD_OPTION_88E]&0x7); //bit0~2
3446
3447 }
3448 else
3449 {
3450 pHalData->EEPROMRegulatory = 0;
3451 }
3452 DBG_871X("EEPROMRegulatory = 0x%x\n", pHalData->EEPROMRegulatory);
3453
3454 }
3455
3456
3457 VOID
Hal_EfuseParseXtal_8188E(IN PADAPTER pAdapter,IN u8 * hwinfo,IN BOOLEAN AutoLoadFail)3458 Hal_EfuseParseXtal_8188E(
3459 IN PADAPTER pAdapter,
3460 IN u8* hwinfo,
3461 IN BOOLEAN AutoLoadFail
3462 )
3463 {
3464 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
3465
3466 if(!AutoLoadFail)
3467 {
3468 pHalData->CrystalCap = hwinfo[EEPROM_XTAL_88E];
3469 if(pHalData->CrystalCap == 0xFF)
3470 pHalData->CrystalCap = EEPROM_Default_CrystalCap_88E;
3471 }
3472 else
3473 {
3474 pHalData->CrystalCap = EEPROM_Default_CrystalCap_88E;
3475 }
3476 DBG_871X("CrystalCap: 0x%2x\n", pHalData->CrystalCap);
3477 }
3478
3479 void
Hal_EfuseParseBoardType88E(IN PADAPTER pAdapter,IN u8 * hwinfo,IN BOOLEAN AutoLoadFail)3480 Hal_EfuseParseBoardType88E(
3481 IN PADAPTER pAdapter,
3482 IN u8* hwinfo,
3483 IN BOOLEAN AutoLoadFail
3484 )
3485 {
3486 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
3487
3488 if (!AutoLoadFail) {
3489 pHalData->InterfaceSel = ((hwinfo[EEPROM_RF_BOARD_OPTION_88E]&0xE0)>>5);
3490 if(hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
3491 pHalData->InterfaceSel = (EEPROM_DEFAULT_BOARD_OPTION&0xE0)>>5;
3492 }
3493 else {
3494 pHalData->InterfaceSel = 0;
3495 }
3496 DBG_871X("Board Type: 0x%2x\n", pHalData->InterfaceSel);
3497 }
3498
3499 void
Hal_EfuseParseEEPROMVer88E(IN PADAPTER padapter,IN u8 * hwinfo,IN BOOLEAN AutoLoadFail)3500 Hal_EfuseParseEEPROMVer88E(
3501 IN PADAPTER padapter,
3502 IN u8* hwinfo,
3503 IN BOOLEAN AutoLoadFail
3504 )
3505 {
3506 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
3507
3508 if(!AutoLoadFail){
3509 pHalData->EEPROMVersion = hwinfo[EEPROM_VERSION_88E];
3510 if(pHalData->EEPROMVersion == 0xFF)
3511 pHalData->EEPROMVersion = EEPROM_Default_Version;
3512 }
3513 else{
3514 pHalData->EEPROMVersion = 1;
3515 }
3516 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Hal_EfuseParseEEPROMVer(), EEVer = %d\n",
3517 pHalData->EEPROMVersion));
3518 }
3519
3520 void
rtl8188e_EfuseParseChnlPlan(IN PADAPTER padapter,IN u8 * hwinfo,IN BOOLEAN AutoLoadFail)3521 rtl8188e_EfuseParseChnlPlan(
3522 IN PADAPTER padapter,
3523 IN u8* hwinfo,
3524 IN BOOLEAN AutoLoadFail
3525 )
3526 {
3527 padapter->mlmepriv.ChannelPlan = hal_com_config_channel_plan(
3528 padapter
3529 , hwinfo?hwinfo[EEPROM_ChannelPlan_88E]:0xFF
3530 , padapter->registrypriv.channel_plan
3531 , RT_CHANNEL_DOMAIN_WORLD_NULL
3532 , AutoLoadFail
3533 );
3534
3535 DBG_871X("mlmepriv.ChannelPlan = 0x%02x\n", padapter->mlmepriv.ChannelPlan);
3536 }
3537
3538 void
Hal_EfuseParseCustomerID88E(IN PADAPTER padapter,IN u8 * hwinfo,IN BOOLEAN AutoLoadFail)3539 Hal_EfuseParseCustomerID88E(
3540 IN PADAPTER padapter,
3541 IN u8* hwinfo,
3542 IN BOOLEAN AutoLoadFail
3543 )
3544 {
3545 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
3546
3547 if (!AutoLoadFail)
3548 {
3549 pHalData->EEPROMCustomerID = hwinfo[EEPROM_CustomID_88E];
3550 //pHalData->EEPROMSubCustomerID = hwinfo[EEPROM_CustomID_88E];
3551 }
3552 else
3553 {
3554 pHalData->EEPROMCustomerID = 0;
3555 pHalData->EEPROMSubCustomerID = 0;
3556 }
3557 DBG_871X("EEPROM Customer ID: 0x%2x\n", pHalData->EEPROMCustomerID);
3558 //DBG_871X("EEPROM SubCustomer ID: 0x%02x\n", pHalData->EEPROMSubCustomerID);
3559 }
3560
3561
3562 void
Hal_ReadAntennaDiversity88E(IN PADAPTER pAdapter,IN u8 * PROMContent,IN BOOLEAN AutoLoadFail)3563 Hal_ReadAntennaDiversity88E(
3564 IN PADAPTER pAdapter,
3565 IN u8* PROMContent,
3566 IN BOOLEAN AutoLoadFail
3567 )
3568 {
3569 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
3570 struct registry_priv *registry_par = &pAdapter->registrypriv;
3571
3572 if(!AutoLoadFail)
3573 {
3574 // Antenna Diversity setting.
3575 if(registry_par->antdiv_cfg == 2)// 2:By EFUSE
3576 {
3577 pHalData->AntDivCfg = (PROMContent[EEPROM_RF_BOARD_OPTION_88E]&0x18)>>3;
3578 if(PROMContent[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
3579 pHalData->AntDivCfg = (EEPROM_DEFAULT_BOARD_OPTION&0x18)>>3;;
3580 }
3581 else
3582 {
3583 pHalData->AntDivCfg = registry_par->antdiv_cfg ; // 0:OFF , 1:ON, 2:By EFUSE
3584 }
3585
3586 if(registry_par->antdiv_type == 0)// If TRxAntDivType is AUTO in advanced setting, use EFUSE value instead.
3587 {
3588 pHalData->TRxAntDivType = PROMContent[EEPROM_RF_ANTENNA_OPT_88E];
3589 if (pHalData->TRxAntDivType == 0xFF)
3590 pHalData->TRxAntDivType = CG_TRX_HW_ANTDIV; // For 88EE, 1Tx and 1RxCG are fixed.(1Ant, Tx and RxCG are both on aux port)
3591 }
3592 else{
3593 pHalData->TRxAntDivType = registry_par->antdiv_type ;
3594 }
3595
3596 if (pHalData->TRxAntDivType == CG_TRX_HW_ANTDIV || pHalData->TRxAntDivType == CGCS_RX_HW_ANTDIV)
3597 pHalData->AntDivCfg = 1; // 0xC1[3] is ignored.
3598 }
3599 else
3600 {
3601 pHalData->AntDivCfg = 0;
3602 }
3603
3604 DBG_871X("EEPROM : AntDivCfg = %x, TRxAntDivType = %x\n",pHalData->AntDivCfg, pHalData->TRxAntDivType);
3605
3606
3607 }
3608
3609 void
Hal_ReadThermalMeter_88E(IN PADAPTER Adapter,IN u8 * PROMContent,IN BOOLEAN AutoloadFail)3610 Hal_ReadThermalMeter_88E(
3611 IN PADAPTER Adapter,
3612 IN u8* PROMContent,
3613 IN BOOLEAN AutoloadFail
3614 )
3615 {
3616 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
3617 u1Byte tempval;
3618
3619 //
3620 // ThermalMeter from EEPROM
3621 //
3622 if(!AutoloadFail)
3623 pHalData->EEPROMThermalMeter = PROMContent[EEPROM_THERMAL_METER_88E];
3624 else
3625 pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_88E;
3626 // pHalData->EEPROMThermalMeter = (tempval&0x1f); //[4:0]
3627
3628 if(pHalData->EEPROMThermalMeter == 0xff || AutoloadFail)
3629 {
3630 pHalData->odmpriv.RFCalibrateInfo.bAPKThermalMeterIgnore = _TRUE;
3631 pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_88E;
3632 }
3633
3634 //pHalData->ThermalMeter[0] = pHalData->EEPROMThermalMeter;
3635 DBG_871X("ThermalMeter = 0x%x\n", pHalData->EEPROMThermalMeter);
3636
3637 }
3638
3639 #ifdef CONFIG_RF_GAIN_OFFSET
Hal_ReadRFGainOffset(IN PADAPTER Adapter,IN u8 * PROMContent,IN BOOLEAN AutoloadFail)3640 void Hal_ReadRFGainOffset(
3641 IN PADAPTER Adapter,
3642 IN u8* PROMContent,
3643 IN BOOLEAN AutoloadFail)
3644 {
3645 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
3646 u8 thermal_offset=0;
3647 //
3648 // BB_RF Gain Offset from EEPROM
3649 //
3650
3651 if (!AutoloadFail) {
3652 pHalData->EEPROMRFGainOffset =PROMContent[EEPROM_RF_GAIN_OFFSET];
3653
3654 if((pHalData->EEPROMRFGainOffset != 0xFF) &&
3655 (pHalData->EEPROMRFGainOffset & BIT4)){
3656 pHalData->EEPROMRFGainVal = EFUSE_Read1Byte(Adapter, EEPROM_RF_GAIN_VAL);
3657 }else{
3658 pHalData->EEPROMRFGainOffset = 0;
3659 pHalData->EEPROMRFGainVal = 0;
3660 }
3661
3662 DBG_871X("pHalData->EEPROMRFGainVal=%x\n", pHalData->EEPROMRFGainVal);
3663 } else {
3664 pHalData->EEPROMRFGainVal=EFUSE_Read1Byte(Adapter,EEPROM_RF_GAIN_VAL);
3665
3666 if(pHalData->EEPROMRFGainVal != 0xFF)
3667 pHalData->EEPROMRFGainOffset = BIT4;
3668 else
3669 pHalData->EEPROMRFGainOffset = 0;
3670 DBG_871X("else AutoloadFail =%x,\n", AutoloadFail);
3671 }
3672 //
3673 // BB_RF Thermal Offset from EEPROM
3674 //
3675 if( (pHalData->EEPROMRFGainOffset!= 0xFF) &&
3676 (pHalData->EEPROMRFGainOffset & BIT4))
3677 {
3678
3679 thermal_offset = EFUSE_Read1Byte(Adapter, EEPROM_THERMAL_OFFSET);
3680 if( thermal_offset != 0xFF){
3681 if(thermal_offset & BIT0)
3682 pHalData->EEPROMThermalMeter += ((thermal_offset>>1) & 0x0F);
3683 else
3684 pHalData->EEPROMThermalMeter -= ((thermal_offset>>1) & 0x0F);
3685
3686 DBG_871X("%s =>thermal_offset:0x%02x pHalData->EEPROMThermalMeter=0x%02x\n",__FUNCTION__ ,thermal_offset,pHalData->EEPROMThermalMeter);
3687 }
3688 }
3689
3690 DBG_871X("%s => EEPRORFGainOffset = 0x%02x,EEPROMRFGainVal=0x%02x,thermal_offset:0x%02x \n",
3691 __FUNCTION__, pHalData->EEPROMRFGainOffset,pHalData->EEPROMRFGainVal,thermal_offset);
3692
3693 }
3694
3695 #endif //CONFIG_RF_GAIN_OFFSET
3696
HalDetectPwrDownMode88E(PADAPTER Adapter)3697 BOOLEAN HalDetectPwrDownMode88E(PADAPTER Adapter)
3698 {
3699 u8 tmpvalue = 0;
3700 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
3701 struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter);
3702
3703 EFUSE_ShadowRead(Adapter, 1, EEPROM_RF_FEATURE_OPTION_88E, (u32 *)&tmpvalue);
3704
3705 // 2010/08/25 MH INF priority > PDN Efuse value.
3706 if(tmpvalue & BIT(4) && pwrctrlpriv->reg_pdnmode)
3707 {
3708 pHalData->pwrdown = _TRUE;
3709 }
3710 else
3711 {
3712 pHalData->pwrdown = _FALSE;
3713 }
3714
3715 DBG_8192C("HalDetectPwrDownMode(): PDN=%d\n", pHalData->pwrdown);
3716
3717 return pHalData->pwrdown;
3718 } // HalDetectPwrDownMode
3719
3720 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
Hal_DetectWoWMode(PADAPTER pAdapter)3721 void Hal_DetectWoWMode(PADAPTER pAdapter)
3722 {
3723 adapter_to_pwrctl(pAdapter)->bSupportRemoteWakeup = _TRUE;
3724 }
3725 #endif
3726
3727 //====================================================================================
3728 //
3729 // 20100209 Joseph:
3730 // This function is used only for 92C to set REG_BCN_CTRL(0x550) register.
3731 // We just reserve the value of the register in variable pHalData->RegBcnCtrlVal and then operate
3732 // the value of the register via atomic operation.
3733 // This prevents from race condition when setting this register.
3734 // The value of pHalData->RegBcnCtrlVal is initialized in HwConfigureRTL8192CE() function.
3735 //
SetBcnCtrlReg(PADAPTER padapter,u8 SetBits,u8 ClearBits)3736 void SetBcnCtrlReg(
3737 PADAPTER padapter,
3738 u8 SetBits,
3739 u8 ClearBits)
3740 {
3741 PHAL_DATA_TYPE pHalData;
3742
3743
3744 pHalData = GET_HAL_DATA(padapter);
3745
3746 pHalData->RegBcnCtrlVal |= SetBits;
3747 pHalData->RegBcnCtrlVal &= ~ClearBits;
3748
3749 #if 0
3750 //#ifdef CONFIG_SDIO_HCI
3751 if (pHalData->sdio_himr & (SDIO_HIMR_TXBCNOK_MSK | SDIO_HIMR_TXBCNERR_MSK))
3752 pHalData->RegBcnCtrlVal |= EN_TXBCN_RPT;
3753 #endif
3754
3755 rtw_write8(padapter, REG_BCN_CTRL, (u8)pHalData->RegBcnCtrlVal);
3756 }
3757
_InitTransferPageSize(PADAPTER padapter)3758 void _InitTransferPageSize(PADAPTER padapter)
3759 {
3760 // Tx page size is always 128.
3761
3762 u8 value8;
3763 value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
3764 rtw_write8(padapter, REG_PBP, value8);
3765 }
3766
ResumeTxBeacon(PADAPTER padapter)3767 void ResumeTxBeacon(PADAPTER padapter)
3768 {
3769 HAL_DATA_TYPE* pHalData = GET_HAL_DATA(padapter);
3770
3771 // 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value
3772 // which should be read from register to a global variable.
3773
3774 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+ResumeTxBeacon\n"));
3775
3776 rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl) | BIT6);
3777 /*TBTT hold time :4ms */
3778 rtw_write16(padapter, REG_TBTT_PROHIBIT + 1,
3779 (rtw_read16(padapter, REG_TBTT_PROHIBIT + 1) & (~0xFFF)) | (TBTT_PROBIHIT_HOLD_TIME));
3780
3781 }
3782
StopTxBeacon(PADAPTER padapter)3783 void StopTxBeacon(PADAPTER padapter)
3784 {
3785 HAL_DATA_TYPE* pHalData = GET_HAL_DATA(padapter);
3786
3787 // 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value
3788 // which should be read from register to a global variable.
3789
3790 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+StopTxBeacon\n"));
3791
3792 rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl) & (~BIT6));
3793 pHalData->RegFwHwTxQCtrl &= (~BIT6);
3794 rtw_write8(padapter, REG_TBTT_PROHIBIT+1, 0x64);
3795
3796 /*CheckFwRsvdPageContent(padapter); // 2010.06.23. Added by tynli.*/
3797 }
3798
hw_var_set_monitor(PADAPTER Adapter,u8 variable,u8 * val)3799 static void hw_var_set_monitor(PADAPTER Adapter, u8 variable, u8 *val)
3800 {
3801 u32 value_rcr, rcr_bits;
3802 u16 value_rxfltmap2;
3803 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
3804 struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
3805
3806 if (*((u8 *)val) == _HW_STATE_MONITOR_) {
3807
3808 /* Leave IPS */
3809 rtw_pm_set_ips(Adapter, IPS_NONE);
3810 LeaveAllPowerSaveMode(Adapter);
3811
3812 /* Receive all type */
3813 rcr_bits = RCR_AAP | RCR_APM | RCR_AM | RCR_AB | RCR_APWRMGT | RCR_ADF | RCR_ACF | RCR_AMF | RCR_APP_PHYST_RXFF;
3814
3815 /* Append FCS */
3816 rcr_bits |= RCR_APPFCS;
3817
3818 #if 0
3819 /*
3820 CRC and ICV packet will drop in recvbuf2recvframe()
3821 We no turn on it.
3822 */
3823 rcr_bits |= (RCR_ACRC32 | RCR_AICV);
3824 #endif
3825
3826 /* Receive all data frames */
3827 value_rxfltmap2 = 0xFFFF;
3828
3829 value_rcr = rcr_bits;
3830 rtw_write32(Adapter, REG_RCR, value_rcr);
3831
3832 rtw_write16(Adapter, REG_RXFLTMAP2, value_rxfltmap2);
3833
3834 #if 0
3835 /* tx pause */
3836 rtw_write8(padapter, REG_TXPAUSE, 0xFF);
3837 #endif
3838 } else {
3839 /* do nothing */
3840 }
3841
3842 }
3843
hw_var_set_opmode(PADAPTER Adapter,u8 variable,u8 * val)3844 static void hw_var_set_opmode(PADAPTER Adapter, u8 variable, u8* val)
3845 {
3846 u8 val8;
3847 u8 mode = *((u8 *)val);
3848 static u8 isMonitor = _FALSE;
3849
3850 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
3851
3852 if (isMonitor == _TRUE) {
3853 /* reset RCR */
3854 rtw_write32(Adapter, REG_RCR, pHalData->ReceiveConfig);
3855 isMonitor = _FALSE;
3856 }
3857
3858 DBG_871X( ADPT_FMT "Port-%d set opmode = %d\n",ADPT_ARG(Adapter),
3859 get_iface_type(Adapter), mode);
3860
3861 if (mode == _HW_STATE_MONITOR_) {
3862 isMonitor = _TRUE;
3863 /* set net_type */
3864 Set_MSR(Adapter, _HW_STATE_NOLINK_);
3865
3866 hw_var_set_monitor(Adapter, variable, val);
3867 return;
3868 }
3869
3870 #ifdef CONFIG_CONCURRENT_MODE
3871 if(Adapter->iface_type == IFACE_PORT1)
3872 {
3873 // disable Port1 TSF update
3874 rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(4));
3875
3876 // set net_type
3877 Set_MSR(Adapter, mode);
3878
3879 if((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_))
3880 {
3881 if(!check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE))
3882 {
3883 #ifdef CONFIG_INTERRUPT_BASED_TXBCN
3884 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
3885 rtw_write8(Adapter, REG_DRVERLYINT, 0x05);//restore early int time to 5ms
3886
3887 #if defined(CONFIG_USB_HCI)
3888 UpdateInterruptMask8188EU(Adapter,_TRUE, 0, IMR_BCNDMAINT0_88E);
3889 #elif defined(CONFIG_SDIO_HCI)
3890 UpdateInterruptMask8188ESdio(Adapter, 0, SDIO_HIMR_BCNERLY_INT_MSK);
3891 #endif
3892
3893 #endif // CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
3894
3895 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
3896 #if defined(CONFIG_USB_HCI)
3897 UpdateInterruptMask8188EU(Adapter,_TRUE ,0, (IMR_TBDER_88E|IMR_TBDOK_88E));
3898 #elif defined(CONFIG_SDIO_HCI)
3899 UpdateInterruptMask8188ESdio(Adapter, 0, (SDIO_HIMR_TXBCNOK_MSK|SDIO_HIMR_TXBCNERR_MSK));
3900 #endif
3901
3902 #endif// CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
3903 #endif //CONFIG_INTERRUPT_BASED_TXBCN
3904
3905 StopTxBeacon(Adapter);
3906 #if defined(CONFIG_PCI_HCI)
3907 UpdateInterruptMask8188EE( Adapter, 0, 0, RT_BCN_INT_MASKS, 0);
3908 #endif
3909 }
3910
3911 rtw_write8(Adapter,REG_BCN_CTRL_1, 0x11);//disable atim wnd and disable beacon function
3912 //rtw_write8(Adapter,REG_BCN_CTRL_1, 0x18);
3913 }
3914 else if((mode == _HW_STATE_ADHOC_) /*|| (mode == _HW_STATE_AP_)*/)
3915 {
3916 //Beacon is polled to TXBUF
3917 rtw_write32(Adapter, REG_CR, rtw_read32(Adapter, REG_CR)|BIT(8));
3918
3919 ResumeTxBeacon(Adapter);
3920 rtw_write8(Adapter,REG_BCN_CTRL_1, 0x1a);
3921 //BIT4 - If set 0, hw will clr bcnq when tx becon ok/fail or port 1
3922 rtw_write8(Adapter, REG_MBID_NUM, rtw_read8(Adapter, REG_MBID_NUM)|BIT(3)|BIT(4));
3923 }
3924 else if(mode == _HW_STATE_AP_)
3925 {
3926 #ifdef CONFIG_INTERRUPT_BASED_TXBCN
3927 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
3928 #if defined(CONFIG_USB_HCI)
3929 UpdateInterruptMask8188EU(Adapter,_TRUE ,IMR_BCNDMAINT0_88E, 0);
3930 #elif defined(CONFIG_SDIO_HCI)
3931 UpdateInterruptMask8188ESdio(Adapter, SDIO_HIMR_BCNERLY_INT_MSK, 0);
3932 #endif
3933 #endif//CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
3934
3935 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
3936 #if defined(CONFIG_USB_HCI)
3937 UpdateInterruptMask8188EU(Adapter,_TRUE ,(IMR_TBDER_88E|IMR_TBDOK_88E), 0);
3938 #elif defined(CONFIG_SDIO_HCI)
3939 UpdateInterruptMask8188ESdio(Adapter, (SDIO_HIMR_TXBCNOK_MSK|SDIO_HIMR_TXBCNERR_MSK), 0);
3940 #endif
3941 #endif//CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
3942
3943 #endif //CONFIG_INTERRUPT_BASED_TXBCN
3944
3945 ResumeTxBeacon(Adapter);
3946
3947 rtw_write8(Adapter, REG_BCN_CTRL_1, 0x12);
3948
3949 //Beacon is polled to TXBUF
3950 rtw_write32(Adapter, REG_CR, rtw_read32(Adapter, REG_CR)|BIT(8));
3951
3952 //Set RCR
3953 //rtw_write32(padapter, REG_RCR, 0x70002a8e);//CBSSID_DATA must set to 0
3954 rtw_write32(Adapter, REG_RCR, 0x7000208e);//CBSSID_DATA must set to 0,Reject ICV_ERROR packets
3955
3956 //enable to rx data frame
3957 rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
3958 //enable to rx ps-poll
3959 rtw_write16(Adapter, REG_RXFLTMAP1, 0x0400);
3960
3961 //Beacon Control related register for first time
3962 rtw_write8(Adapter, REG_BCNDMATIM, 0x02); // 2ms
3963 rtw_write8(Adapter, REG_DRVERLYINT, 0x05);// 5ms
3964 //rtw_write8(Adapter, REG_BCN_MAX_ERR, 0xFF);
3965 rtw_write8(Adapter, REG_ATIMWND_1, 0x0c); // 13 ms for port1
3966 rtw_write16(Adapter, REG_BCNTCFG, 0x00);
3967 rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0x8004);
3968 rtw_write16(Adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);// +32767 (~32ms)
3969
3970 //reset TSF2
3971 rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(1));
3972
3973
3974 //BIT4 - If set 0, hw will clr bcnq when tx becon ok/fail or port 1
3975 rtw_write8(Adapter, REG_MBID_NUM, rtw_read8(Adapter, REG_MBID_NUM)|BIT(3)|BIT(4));
3976 //enable BCN1 Function for if2
3977 //don't enable update TSF1 for if2 (due to TSF update when beacon/probe rsp are received)
3978 rtw_write8(Adapter, REG_BCN_CTRL_1, (DIS_TSF_UDT0_NORMAL_CHIP|EN_BCN_FUNCTION | EN_TXBCN_RPT|BIT(1)));
3979
3980 #ifdef CONFIG_CONCURRENT_MODE
3981 if(check_buddy_fwstate(Adapter, WIFI_FW_NULL_STATE))
3982 rtw_write8(Adapter, REG_BCN_CTRL,
3983 rtw_read8(Adapter, REG_BCN_CTRL) & ~EN_BCN_FUNCTION);
3984 #endif
3985 //BCN1 TSF will sync to BCN0 TSF with offset(0x518) if if1_sta linked
3986 //rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(5));
3987 //rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(3));
3988
3989 //dis BCN0 ATIM WND if if1 is station
3990 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(0));
3991
3992 #ifdef CONFIG_TSF_RESET_OFFLOAD
3993 // Reset TSF for STA+AP concurrent mode
3994 if ( check_buddy_fwstate(Adapter, (WIFI_STATION_STATE|WIFI_ASOC_STATE)) ) {
3995 if (reset_tsf(Adapter, IFACE_PORT1) == _FALSE)
3996 DBG_871X("ERROR! %s()-%d: Reset port1 TSF fail\n",
3997 __FUNCTION__, __LINE__);
3998 }
3999 #endif // CONFIG_TSF_RESET_OFFLOAD
4000 #if defined(CONFIG_PCI_HCI)
4001 UpdateInterruptMask8188EE( Adapter, RT_BCN_INT_MASKS, 0, 0, 0);
4002 #endif
4003 }
4004 }
4005 else // (Adapter->iface_type == IFACE_PORT1)
4006 #endif //CONFIG_CONCURRENT_MODE
4007 {
4008 // disable Port0 TSF update
4009 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
4010
4011 // set net_type
4012 Set_MSR(Adapter, mode);
4013
4014 if((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_))
4015 {
4016 #ifdef CONFIG_CONCURRENT_MODE
4017 if(!check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE))
4018 #endif //CONFIG_CONCURRENT_MODE
4019 {
4020 #ifdef CONFIG_INTERRUPT_BASED_TXBCN
4021 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
4022 rtw_write8(Adapter, REG_DRVERLYINT, 0x05);//restore early int time to 5ms
4023 #if defined(CONFIG_USB_HCI)
4024 UpdateInterruptMask8188EU(Adapter,_TRUE, 0, IMR_BCNDMAINT0_88E);
4025 #elif defined(CONFIG_SDIO_HCI)
4026 UpdateInterruptMask8188ESdio(Adapter, 0, SDIO_HIMR_BCNERLY_INT_MSK);
4027 #endif
4028 #endif//CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
4029
4030 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
4031 #if defined(CONFIG_USB_HCI)
4032 UpdateInterruptMask8188EU(Adapter,_TRUE ,0, (IMR_TBDER_88E|IMR_TBDOK_88E));
4033 #elif defined(CONFIG_SDIO_HCI)
4034 UpdateInterruptMask8188ESdio(Adapter, 0, (SDIO_HIMR_TXBCNOK_MSK|SDIO_HIMR_TXBCNERR_MSK));
4035 #endif
4036 #endif //CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
4037
4038 #endif //CONFIG_INTERRUPT_BASED_TXBCN
4039 StopTxBeacon(Adapter);
4040 #if defined(CONFIG_PCI_HCI)
4041 UpdateInterruptMask8188EE(Adapter, 0, 0, RT_BCN_INT_MASKS, 0);
4042 #endif
4043 }
4044
4045 rtw_write8(Adapter,REG_BCN_CTRL, 0x19);//disable atim wnd
4046 //rtw_write8(Adapter,REG_BCN_CTRL, 0x18);
4047 }
4048 else if((mode == _HW_STATE_ADHOC_) /*|| (mode == _HW_STATE_AP_)*/)
4049 {
4050 //Beacon is polled to TXBUF
4051 rtw_write16(Adapter, REG_CR, rtw_read16(Adapter, REG_CR)|BIT(8));
4052
4053 ResumeTxBeacon(Adapter);
4054 rtw_write8(Adapter,REG_BCN_CTRL, 0x1a);
4055 //BIT3 - If set 0, hw will clr bcnq when tx becon ok/fail or port 0
4056 rtw_write8(Adapter, REG_MBID_NUM, rtw_read8(Adapter, REG_MBID_NUM)|BIT(3)|BIT(4));
4057 }
4058 else if(mode == _HW_STATE_AP_)
4059 {
4060 #ifdef CONFIG_INTERRUPT_BASED_TXBCN
4061 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
4062 #if defined(CONFIG_USB_HCI)
4063 UpdateInterruptMask8188EU(Adapter,_TRUE ,IMR_BCNDMAINT0_88E, 0);
4064 #elif defined(CONFIG_SDIO_HCI)
4065 UpdateInterruptMask8188ESdio(Adapter, SDIO_HIMR_BCNERLY_INT_MSK, 0);
4066 #endif
4067 #endif//CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
4068
4069 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
4070 #if defined(CONFIG_USB_HCI)
4071 UpdateInterruptMask8188EU(Adapter,_TRUE ,(IMR_TBDER_88E|IMR_TBDOK_88E), 0);
4072 #elif defined(CONFIG_SDIO_HCI)
4073 UpdateInterruptMask8188ESdio(Adapter, (SDIO_HIMR_TXBCNOK_MSK|SDIO_HIMR_TXBCNERR_MSK), 0);
4074 #endif
4075 #endif//CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
4076
4077 #endif //CONFIG_INTERRUPT_BASED_TXBCN
4078
4079 ResumeTxBeacon(Adapter);
4080
4081 rtw_write8(Adapter, REG_BCN_CTRL, 0x12);
4082
4083 //Beacon is polled to TXBUF
4084 rtw_write32(Adapter, REG_CR, rtw_read32(Adapter, REG_CR)|BIT(8));
4085
4086 //Set RCR
4087 //rtw_write32(padapter, REG_RCR, 0x70002a8e);//CBSSID_DATA must set to 0
4088 rtw_write32(Adapter, REG_RCR, 0x7000208e);//CBSSID_DATA must set to 0,reject ICV_ERR packet
4089 //enable to rx data frame
4090 rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
4091 //enable to rx ps-poll
4092 rtw_write16(Adapter, REG_RXFLTMAP1, 0x0400);
4093
4094 //Beacon Control related register for first time
4095 rtw_write8(Adapter, REG_BCNDMATIM, 0x02); // 2ms
4096 rtw_write8(Adapter, REG_DRVERLYINT, 0x05);// 5ms
4097 //rtw_write8(Adapter, REG_BCN_MAX_ERR, 0xFF);
4098 rtw_write8(Adapter, REG_ATIMWND, 0x0c); // 13ms
4099 rtw_write16(Adapter, REG_BCNTCFG, 0x00);
4100 rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0x8004);
4101 rtw_write16(Adapter, REG_TSFTR_SYN_OFFSET, 0x7fff);// +32767 (~32ms)
4102
4103 //reset TSF
4104 rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(0));
4105
4106 //BIT3 - If set 0, hw will clr bcnq when tx becon ok/fail or port 0
4107 rtw_write8(Adapter, REG_MBID_NUM, rtw_read8(Adapter, REG_MBID_NUM)|BIT(3)|BIT(4));
4108
4109 //enable BCN0 Function for if1
4110 //don't enable update TSF0 for if1 (due to TSF update when beacon/probe rsp are received)
4111 #if defined(CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR)
4112 rtw_write8(Adapter, REG_BCN_CTRL, (DIS_TSF_UDT0_NORMAL_CHIP|EN_BCN_FUNCTION | EN_TXBCN_RPT|BIT(1)));
4113 #else
4114 rtw_write8(Adapter, REG_BCN_CTRL, (DIS_TSF_UDT0_NORMAL_CHIP|EN_BCN_FUNCTION |BIT(1)));
4115 #endif
4116
4117 #ifdef CONFIG_CONCURRENT_MODE
4118 if(check_buddy_fwstate(Adapter, WIFI_FW_NULL_STATE))
4119 rtw_write8(Adapter, REG_BCN_CTRL_1,
4120 rtw_read8(Adapter, REG_BCN_CTRL_1) & ~EN_BCN_FUNCTION);
4121 #endif
4122
4123 //dis BCN1 ATIM WND if if2 is station
4124 rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(0));
4125 #ifdef CONFIG_TSF_RESET_OFFLOAD
4126 // Reset TSF for STA+AP concurrent mode
4127 if ( check_buddy_fwstate(Adapter, (WIFI_STATION_STATE|WIFI_ASOC_STATE)) ) {
4128 if (reset_tsf(Adapter, IFACE_PORT0) == _FALSE)
4129 DBG_871X("ERROR! %s()-%d: Reset port0 TSF fail\n",
4130 __FUNCTION__, __LINE__);
4131 }
4132 #endif // CONFIG_TSF_RESET_OFFLOAD
4133 #if defined(CONFIG_PCI_HCI)
4134 UpdateInterruptMask8188EE( Adapter, RT_BCN_INT_MASKS, 0, 0, 0);
4135 #endif
4136 }
4137 }
4138 }
hw_var_set_macaddr(PADAPTER Adapter,u8 variable,u8 * val)4139 static void hw_var_set_macaddr(PADAPTER Adapter, u8 variable, u8* val)
4140 {
4141 u8 idx = 0;
4142 u32 reg_macid;
4143
4144 #ifdef CONFIG_CONCURRENT_MODE
4145 if(Adapter->iface_type == IFACE_PORT1)
4146 {
4147 reg_macid = REG_MACID1;
4148 }
4149 else
4150 #endif
4151 {
4152 reg_macid = REG_MACID;
4153 }
4154
4155 for(idx = 0 ; idx < 6; idx++)
4156 {
4157 rtw_write8(GET_PRIMARY_ADAPTER(Adapter), (reg_macid+idx), val[idx]);
4158 }
4159
4160 }
4161
hw_var_set_bssid(PADAPTER Adapter,u8 variable,u8 * val)4162 static void hw_var_set_bssid(PADAPTER Adapter, u8 variable, u8* val)
4163 {
4164 u8 idx = 0;
4165 u32 reg_bssid;
4166
4167 #ifdef CONFIG_CONCURRENT_MODE
4168 if(Adapter->iface_type == IFACE_PORT1)
4169 {
4170 reg_bssid = REG_BSSID1;
4171 }
4172 else
4173 #endif
4174 {
4175 reg_bssid = REG_BSSID;
4176 }
4177
4178 for(idx = 0 ; idx < 6; idx++)
4179 {
4180 rtw_write8(Adapter, (reg_bssid+idx), val[idx]);
4181 }
4182
4183 }
4184
hw_var_set_bcn_func(PADAPTER Adapter,u8 variable,u8 * val)4185 static void hw_var_set_bcn_func(PADAPTER Adapter, u8 variable, u8* val)
4186 {
4187 u32 bcn_ctrl_reg;
4188
4189 #ifdef CONFIG_CONCURRENT_MODE
4190 if(Adapter->iface_type == IFACE_PORT1)
4191 {
4192 bcn_ctrl_reg = REG_BCN_CTRL_1;
4193 }
4194 else
4195 #endif
4196 {
4197 bcn_ctrl_reg = REG_BCN_CTRL;
4198 }
4199
4200 if(*((u8 *)val))
4201 {
4202 rtw_write8(Adapter, bcn_ctrl_reg, (EN_BCN_FUNCTION | EN_TXBCN_RPT));
4203 }
4204 else
4205 {
4206 rtw_write8(Adapter, bcn_ctrl_reg, rtw_read8(Adapter, bcn_ctrl_reg)&(~(EN_BCN_FUNCTION | EN_TXBCN_RPT)));
4207 }
4208
4209
4210 }
4211
hw_var_set_correct_tsf(PADAPTER Adapter,u8 variable,u8 * val)4212 static void hw_var_set_correct_tsf(PADAPTER Adapter, u8 variable, u8* val)
4213 {
4214 #ifdef CONFIG_CONCURRENT_MODE
4215 u64 tsf;
4216 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
4217 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
4218 PADAPTER pbuddy_adapter = Adapter->pbuddy_adapter;
4219
4220 //tsf = pmlmeext->TSFValue - ((u32)pmlmeext->TSFValue % (pmlmeinfo->bcn_interval*1024)) -1024; //us
4221 tsf = pmlmeext->TSFValue - rtw_modular64(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval*1024)) -1024; //us
4222
4223 if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
4224 {
4225 //pHalData->RegTxPause |= STOP_BCNQ;BIT(6)
4226 //rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)|BIT(6)));
4227 StopTxBeacon(Adapter);
4228 }
4229
4230 if(Adapter->iface_type == IFACE_PORT1)
4231 {
4232 //disable related TSF function
4233 rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(3)));
4234
4235 rtw_write32(Adapter, REG_TSFTR1, tsf);
4236 rtw_write32(Adapter, REG_TSFTR1+4, tsf>>32);
4237
4238
4239 //enable related TSF function
4240 rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(3));
4241
4242 // Update buddy port's TSF if it is SoftAP for beacon TX issue!
4243 if ( (pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE
4244 && check_buddy_fwstate(Adapter, WIFI_AP_STATE)
4245 ) {
4246 //disable related TSF function
4247 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(3)));
4248
4249 rtw_write32(Adapter, REG_TSFTR, tsf);
4250 rtw_write32(Adapter, REG_TSFTR+4, tsf>>32);
4251
4252 //enable related TSF function
4253 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(3));
4254 #ifdef CONFIG_TSF_RESET_OFFLOAD
4255 // Update buddy port's TSF(TBTT) if it is SoftAP for beacon TX issue!
4256 if (reset_tsf(Adapter, IFACE_PORT0) == _FALSE)
4257 DBG_871X("ERROR! %s()-%d: Reset port0 TSF fail\n",
4258 __FUNCTION__, __LINE__);
4259
4260 #endif // CONFIG_TSF_RESET_OFFLOAD
4261 }
4262
4263 }
4264 else
4265 {
4266 //disable related TSF function
4267 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(3)));
4268
4269 rtw_write32(Adapter, REG_TSFTR, tsf);
4270 rtw_write32(Adapter, REG_TSFTR+4, tsf>>32);
4271
4272 //enable related TSF function
4273 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(3));
4274
4275 // Update buddy port's TSF if it is SoftAP for beacon TX issue!
4276 if ( (pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE
4277 && check_buddy_fwstate(Adapter, WIFI_AP_STATE)
4278 ) {
4279 //disable related TSF function
4280 rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(3)));
4281
4282 rtw_write32(Adapter, REG_TSFTR1, tsf);
4283 rtw_write32(Adapter, REG_TSFTR1+4, tsf>>32);
4284
4285 //enable related TSF function
4286 rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(3));
4287 #ifdef CONFIG_TSF_RESET_OFFLOAD
4288 // Update buddy port's TSF if it is SoftAP for beacon TX issue!
4289 if (reset_tsf(Adapter, IFACE_PORT1) == _FALSE)
4290 DBG_871X("ERROR! %s()-%d: Reset port1 TSF fail\n",
4291 __FUNCTION__, __LINE__);
4292 #endif // CONFIG_TSF_RESET_OFFLOAD
4293 }
4294
4295 }
4296
4297
4298 if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
4299 {
4300 //pHalData->RegTxPause &= (~STOP_BCNQ);
4301 //rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)&(~BIT(6))));
4302 ResumeTxBeacon(Adapter);
4303 }
4304 #endif
4305 }
4306
hw_var_set_mlme_disconnect(PADAPTER Adapter,u8 variable,u8 * val)4307 static void hw_var_set_mlme_disconnect(PADAPTER Adapter, u8 variable, u8* val)
4308 {
4309 #ifdef CONFIG_CONCURRENT_MODE
4310 //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
4311 PADAPTER pbuddy_adapter = Adapter->pbuddy_adapter;
4312
4313
4314 if(check_buddy_mlmeinfo_state(Adapter, _HW_STATE_NOLINK_))
4315 rtw_write16(Adapter, REG_RXFLTMAP2, 0x00);
4316
4317
4318 if(Adapter->iface_type == IFACE_PORT1)
4319 {
4320 //reset TSF1
4321 rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(1));
4322
4323 //disable update TSF1
4324 rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(4));
4325
4326 // disable Port1's beacon function
4327 rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(3)));
4328 }
4329 else
4330 {
4331 //reset TSF
4332 rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(0));
4333
4334 //disable update TSF
4335 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
4336 }
4337 #endif
4338 }
4339
hw_var_set_mlme_sitesurvey(PADAPTER Adapter,u8 variable,u8 * val)4340 static void hw_var_set_mlme_sitesurvey(PADAPTER Adapter, u8 variable, u8* val)
4341 {
4342 #ifdef CONFIG_CONCURRENT_MODE
4343 struct dvobj_priv *dvobj = adapter_to_dvobj(Adapter);
4344 struct mlme_priv *pmlmepriv=&(Adapter->mlmepriv);
4345 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
4346 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
4347 u32 value_rcr, rcr_clear_bit, value_rxfltmap2;
4348 u8 ap_num;
4349
4350 rtw_dev_iface_status(Adapter, NULL, NULL, NULL, &ap_num, NULL);
4351
4352 #ifdef CONFIG_FIND_BEST_CHANNEL
4353
4354 rcr_clear_bit = (RCR_CBSSID_BCN | RCR_CBSSID_DATA);
4355
4356 /* Receive all data frames */
4357 value_rxfltmap2 = 0xFFFF;
4358
4359 #else /* CONFIG_FIND_BEST_CHANNEL */
4360
4361 rcr_clear_bit = RCR_CBSSID_BCN;
4362
4363 //config RCR to receive different BSSID & not to receive data frame
4364 value_rxfltmap2 = 0;
4365
4366 #endif /* CONFIG_FIND_BEST_CHANNEL */
4367
4368 if( (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
4369 #ifdef CONFIG_CONCURRENT_MODE
4370 || (check_buddy_fwstate(Adapter, WIFI_AP_STATE) == _TRUE)
4371 #endif
4372 ){
4373 rcr_clear_bit = RCR_CBSSID_BCN;
4374 }
4375 #ifdef CONFIG_TDLS
4376 // TDLS will clear RCR_CBSSID_DATA bit for connection.
4377 else if (Adapter->tdlsinfo.link_established == _TRUE)
4378 {
4379 rcr_clear_bit = RCR_CBSSID_BCN;
4380 }
4381 #endif // CONFIG_TDLS
4382
4383 value_rcr = rtw_read32(Adapter, REG_RCR);
4384 if(*((u8 *)val))//under sitesurvey
4385 {
4386 //config RCR to receive different BSSID & not to receive data frame
4387 value_rcr &= ~(rcr_clear_bit);
4388 rtw_write32(Adapter, REG_RCR, value_rcr);
4389 rtw_write16(Adapter, REG_RXFLTMAP2, value_rxfltmap2);
4390
4391 //disable update TSF
4392 if((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE)
4393 {
4394 if(Adapter->iface_type == IFACE_PORT1)
4395 {
4396 rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)|BIT(4));
4397 }
4398 else
4399 {
4400 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4));
4401 }
4402 }
4403
4404 if (ap_num)
4405 StopTxBeacon(Adapter);
4406
4407 }
4408 else//sitesurvey done
4409 {
4410 //enable to rx data frame
4411 //write32(Adapter, REG_RCR, read32(padapter, REG_RCR)|RCR_ADF);
4412 if(check_fwstate(pmlmepriv, (_FW_LINKED|WIFI_AP_STATE))
4413 || check_buddy_fwstate(Adapter, (_FW_LINKED|WIFI_AP_STATE)))
4414 rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF);
4415
4416 //enable update TSF
4417 if(Adapter->iface_type == IFACE_PORT1)
4418 rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(4)));
4419 else
4420 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
4421
4422 value_rcr |= rcr_clear_bit;
4423 rtw_write32(Adapter, REG_RCR, value_rcr);
4424
4425 if (ap_num) {
4426 int i;
4427 _adapter *iface;
4428
4429 ResumeTxBeacon(Adapter);
4430 for (i = 0; i < dvobj->iface_nums; i++) {
4431 iface = dvobj->padapters[i];
4432 if (!iface)
4433 continue;
4434
4435 if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE
4436 && check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE
4437 ) {
4438 iface->mlmepriv.update_bcn = _TRUE;
4439 #ifndef CONFIG_INTERRUPT_BASED_TXBCN
4440 #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
4441 tx_beacon_hdl(iface, NULL);
4442 #endif
4443 #endif
4444 }
4445 }
4446 }
4447 }
4448 #endif
4449 }
4450
hw_var_set_mlme_join(PADAPTER Adapter,u8 variable,u8 * val)4451 static void hw_var_set_mlme_join(PADAPTER Adapter, u8 variable, u8* val)
4452 {
4453 #ifdef CONFIG_CONCURRENT_MODE
4454 u8 RetryLimit = 0x30;
4455 u8 type = *((u8 *)val);
4456 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
4457 struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
4458
4459 if(type == 0) // prepare to join
4460 {
4461 if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) &&
4462 check_buddy_fwstate(Adapter, _FW_LINKED))
4463 {
4464 StopTxBeacon(Adapter);
4465 }
4466
4467 //enable to rx data frame.Accept all data frame
4468 //rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF);
4469 rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF);
4470
4471 if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE))
4472 rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN);
4473 else
4474 rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN);
4475
4476 if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
4477 {
4478 RetryLimit = (pHalData->CustomerID == RT_CID_CCX) ? 7 : 48;
4479 }
4480 else // Ad-hoc Mode
4481 {
4482 RetryLimit = 0x7;
4483 }
4484 }
4485 else if(type == 1) //joinbss_event call back when join res < 0
4486 {
4487 if(check_buddy_mlmeinfo_state(Adapter, _HW_STATE_NOLINK_))
4488 rtw_write16(Adapter, REG_RXFLTMAP2,0x00);
4489
4490 if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) &&
4491 check_buddy_fwstate(Adapter, _FW_LINKED))
4492 {
4493 ResumeTxBeacon(Adapter);
4494
4495 //reset TSF 1/2 after ResumeTxBeacon
4496 rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(1)|BIT(0));
4497
4498 }
4499 }
4500 else if(type == 2) //sta add event call back
4501 {
4502
4503 //enable update TSF
4504 if(Adapter->iface_type == IFACE_PORT1)
4505 rtw_write8(Adapter, REG_BCN_CTRL_1, rtw_read8(Adapter, REG_BCN_CTRL_1)&(~BIT(4)));
4506 else
4507 rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4)));
4508
4509
4510 if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE))
4511 {
4512 //fixed beacon issue for 8191su...........
4513 rtw_write8(Adapter,0x542 ,0x02);
4514 RetryLimit = 0x7;
4515 }
4516
4517
4518 if(check_buddy_mlmeinfo_state(Adapter, WIFI_FW_AP_STATE) &&
4519 check_buddy_fwstate(Adapter, _FW_LINKED))
4520 {
4521 ResumeTxBeacon(Adapter);
4522
4523 //reset TSF 1/2 after ResumeTxBeacon
4524 rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(1)|BIT(0));
4525 }
4526
4527 }
4528
4529 rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT);
4530
4531 #endif
4532 }
4533
4534
4535
SetHwReg8188E(_adapter * adapter,u8 variable,u8 * val)4536 void SetHwReg8188E(_adapter *adapter, u8 variable, u8 *val)
4537 {
4538 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
4539 DM_ODM_T *podmpriv = &pHalData->odmpriv;
4540 _func_enter_;
4541
4542 switch (variable) {
4543 case HW_VAR_MEDIA_STATUS:
4544 {
4545 u8 val8;
4546
4547 val8 = rtw_read8(adapter, MSR)&0x0c;
4548 val8 |= *((u8 *)val);
4549 rtw_write8(adapter, MSR, val8);
4550 }
4551 break;
4552 case HW_VAR_MEDIA_STATUS1:
4553 {
4554 u8 val8;
4555
4556 val8 = rtw_read8(adapter, MSR)&0x03;
4557 val8 |= *((u8 *)val) <<2;
4558 rtw_write8(adapter, MSR, val8);
4559 }
4560 break;
4561 case HW_VAR_SET_OPMODE:
4562 hw_var_set_opmode(adapter, variable, val);
4563 break;
4564 case HW_VAR_MAC_ADDR:
4565 hw_var_set_macaddr(adapter, variable, val);
4566 break;
4567 case HW_VAR_BSSID:
4568 hw_var_set_bssid(adapter, variable, val);
4569 break;
4570 case HW_VAR_BASIC_RATE:
4571 {
4572 struct mlme_ext_info *mlmext_info = &adapter->mlmeextpriv.mlmext_info;
4573 u16 input_b = 0, masked = 0, ioted = 0, BrateCfg = 0;
4574 u16 rrsr_2g_force_mask = RRSR_CCK_RATES;
4575 u16 rrsr_2g_allow_mask = (RRSR_24M|RRSR_12M|RRSR_6M|RRSR_CCK_RATES);
4576
4577 HalSetBrateCfg(adapter, val, &BrateCfg);
4578 input_b = BrateCfg;
4579
4580 /* apply force and allow mask */
4581 BrateCfg |= rrsr_2g_force_mask;
4582 BrateCfg &= rrsr_2g_allow_mask;
4583 masked = BrateCfg;
4584
4585 /* IOT consideration */
4586 if (mlmext_info->assoc_AP_vendor == HT_IOT_PEER_CISCO) {
4587 /* if peer is cisco and didn't use ofdm rate, we enable 6M ack */
4588 if((BrateCfg & (RRSR_24M|RRSR_12M|RRSR_6M)) == 0)
4589 BrateCfg |= RRSR_6M;
4590 }
4591 ioted = BrateCfg;
4592
4593 pHalData->BasicRateSet = BrateCfg;
4594
4595 DBG_8192C("HW_VAR_BASIC_RATE: %#x -> %#x -> %#x\n", input_b, masked, ioted);
4596
4597 // Set RRSR rate table.
4598 rtw_write16(adapter, REG_RRSR, BrateCfg);
4599 rtw_write8(adapter, REG_RRSR+2, rtw_read8(adapter, REG_RRSR+2)&0xf0);
4600
4601 rtw_hal_set_hwreg(adapter, HW_VAR_INIT_RTS_RATE, (u8*)&BrateCfg);
4602 }
4603 break;
4604 case HW_VAR_TXPAUSE:
4605 rtw_write8(adapter, REG_TXPAUSE, *((u8 *)val));
4606 break;
4607 case HW_VAR_BCN_FUNC:
4608 hw_var_set_bcn_func(adapter, variable, val);
4609 break;
4610
4611 case HW_VAR_CORRECT_TSF:
4612 #ifdef CONFIG_CONCURRENT_MODE
4613 hw_var_set_correct_tsf(adapter, variable, val);
4614 #else
4615 {
4616 u64 tsf;
4617 struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
4618 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
4619
4620 //tsf = pmlmeext->TSFValue - ((u32)pmlmeext->TSFValue % (pmlmeinfo->bcn_interval*1024)) -1024; //us
4621 tsf = pmlmeext->TSFValue - rtw_modular64(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval*1024)) -1024; //us
4622
4623 if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
4624 {
4625 //pHalData->RegTxPause |= STOP_BCNQ;BIT(6)
4626 //rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)|BIT(6)));
4627 StopTxBeacon(adapter);
4628 }
4629
4630 //disable related TSF function
4631 rtw_write8(adapter, REG_BCN_CTRL, rtw_read8(adapter, REG_BCN_CTRL)&(~BIT(3)));
4632
4633 rtw_write32(adapter, REG_TSFTR, tsf);
4634 rtw_write32(adapter, REG_TSFTR+4, tsf>>32);
4635
4636 //enable related TSF function
4637 rtw_write8(adapter, REG_BCN_CTRL, rtw_read8(adapter, REG_BCN_CTRL)|BIT(3));
4638
4639
4640 if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
4641 {
4642 //pHalData->RegTxPause &= (~STOP_BCNQ);
4643 //rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)&(~BIT(6))));
4644 ResumeTxBeacon(adapter);
4645 }
4646 }
4647 #endif
4648 break;
4649
4650 case HW_VAR_CHECK_BSSID:
4651 if(*((u8 *)val))
4652 {
4653 rtw_write32(adapter, REG_RCR, rtw_read32(adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN);
4654 }
4655 else
4656 {
4657 u32 val32;
4658
4659 val32 = rtw_read32(adapter, REG_RCR);
4660
4661 val32 &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
4662
4663 rtw_write32(adapter, REG_RCR, val32);
4664 }
4665 break;
4666
4667 case HW_VAR_MLME_DISCONNECT:
4668 #ifdef CONFIG_CONCURRENT_MODE
4669 hw_var_set_mlme_disconnect(adapter, variable, val);
4670 #else
4671 {
4672 //Set RCR to not to receive data frame when NO LINK state
4673 //rtw_write32(Adapter, REG_RCR, rtw_read32(padapter, REG_RCR) & ~RCR_ADF);
4674 //reject all data frames
4675 rtw_write16(adapter, REG_RXFLTMAP2,0x00);
4676
4677 //reset TSF
4678 rtw_write8(adapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1)));
4679
4680 //disable update TSF
4681 rtw_write8(adapter, REG_BCN_CTRL, rtw_read8(adapter, REG_BCN_CTRL)|BIT(4));
4682 }
4683 #endif
4684 break;
4685
4686 case HW_VAR_MLME_SITESURVEY:
4687 #ifdef CONFIG_CONCURRENT_MODE
4688 hw_var_set_mlme_sitesurvey(adapter, variable, val);
4689 #else
4690 {
4691 u32 value_rcr, rcr_clear_bit, value_rxfltmap2;
4692 #ifdef CONFIG_FIND_BEST_CHANNEL
4693
4694 rcr_clear_bit = (RCR_CBSSID_BCN | RCR_CBSSID_DATA);
4695
4696 /* Receive all data frames */
4697 value_rxfltmap2 = 0xFFFF;
4698
4699 #else /* CONFIG_FIND_BEST_CHANNEL */
4700
4701 rcr_clear_bit = RCR_CBSSID_BCN;
4702
4703 //config RCR to receive different BSSID & not to receive data frame
4704 value_rxfltmap2 = 0;
4705
4706 #endif /* CONFIG_FIND_BEST_CHANNEL */
4707
4708 if (check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _TRUE) {
4709 rcr_clear_bit = RCR_CBSSID_BCN;
4710 }
4711 #ifdef CONFIG_TDLS
4712 // TDLS will clear RCR_CBSSID_DATA bit for connection.
4713 else if (adapter->tdlsinfo.link_established == _TRUE) {
4714 rcr_clear_bit = RCR_CBSSID_BCN;
4715 }
4716 #endif // CONFIG_TDLS
4717
4718 value_rcr = rtw_read32(adapter, REG_RCR);
4719 if(*((u8 *)val))//under sitesurvey
4720 {
4721 //config RCR to receive different BSSID & not to receive data frame
4722 value_rcr &= ~(rcr_clear_bit);
4723 rtw_write32(adapter, REG_RCR, value_rcr);
4724 rtw_write16(adapter, REG_RXFLTMAP2, value_rxfltmap2);
4725
4726 //disable update TSF
4727 rtw_write8(adapter, REG_BCN_CTRL, rtw_read8(adapter, REG_BCN_CTRL)|BIT(4));
4728 }
4729 else//sitesurvey done
4730 {
4731 struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
4732 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
4733
4734 if ((is_client_associated_to_ap(adapter) == _TRUE) ||
4735 ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) )
4736 {
4737 //enable to rx data frame
4738 //rtw_write32(Adapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF);
4739 rtw_write16(adapter, REG_RXFLTMAP2,0xFFFF);
4740
4741 //enable update TSF
4742 rtw_write8(adapter, REG_BCN_CTRL, rtw_read8(adapter, REG_BCN_CTRL)&(~BIT(4)));
4743 }
4744 else if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)
4745 {
4746 //rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_ADF);
4747 rtw_write16(adapter, REG_RXFLTMAP2,0xFFFF);
4748
4749 //enable update TSF
4750 rtw_write8(adapter, REG_BCN_CTRL, rtw_read8(adapter, REG_BCN_CTRL)&(~BIT(4)));
4751 }
4752
4753 value_rcr |= rcr_clear_bit;
4754 if(((pmlmeinfo->state&0x03) != WIFI_FW_AP_STATE) && (adapter->in_cta_test)) {
4755 u32 v = rtw_read32(adapter, REG_RCR);
4756 v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN );//| RCR_ADF
4757 rtw_write32(adapter, REG_RCR, v);
4758 } else {
4759 rtw_write32(adapter, REG_RCR, value_rcr);
4760 }
4761 }
4762 }
4763 #endif
4764 break;
4765
4766 case HW_VAR_MLME_JOIN:
4767 #ifdef CONFIG_CONCURRENT_MODE
4768 hw_var_set_mlme_join(adapter, variable, val);
4769 #else
4770 {
4771 u8 RetryLimit = 0x30;
4772 u8 type = *((u8 *)val);
4773 struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
4774
4775 if(type == 0) // prepare to join
4776 {
4777 //enable to rx data frame.Accept all data frame
4778 //rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF);
4779 rtw_write16(adapter, REG_RXFLTMAP2,0xFFFF);
4780
4781 if(adapter->in_cta_test)
4782 {
4783 u32 v = rtw_read32(adapter, REG_RCR);
4784 v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN );//| RCR_ADF
4785 rtw_write32(adapter, REG_RCR, v);
4786 }
4787 else
4788 {
4789 rtw_write32(adapter, REG_RCR, rtw_read32(adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN);
4790 }
4791
4792 if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
4793 {
4794 RetryLimit = (pHalData->CustomerID == RT_CID_CCX) ? 7 : 48;
4795 }
4796 else // Ad-hoc Mode
4797 {
4798 RetryLimit = 0x7;
4799 }
4800 }
4801 else if(type == 1) //joinbss_event call back when join res < 0
4802 {
4803 rtw_write16(adapter, REG_RXFLTMAP2,0x00);
4804 }
4805 else if(type == 2) //sta add event call back
4806 {
4807 //enable update TSF
4808 rtw_write8(adapter, REG_BCN_CTRL, rtw_read8(adapter, REG_BCN_CTRL)&(~BIT(4)));
4809
4810 if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE))
4811 {
4812 RetryLimit = 0x7;
4813 }
4814 }
4815
4816 rtw_write16(adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT);
4817 }
4818 #endif
4819 break;
4820
4821 case HW_VAR_ON_RCR_AM:
4822 rtw_write32(adapter, REG_RCR, rtw_read32(adapter, REG_RCR)|RCR_AM);
4823 DBG_871X("%s, %d, RCR= %x \n", __FUNCTION__,__LINE__, rtw_read32(adapter, REG_RCR));
4824 break;
4825 case HW_VAR_OFF_RCR_AM:
4826 rtw_write32(adapter, REG_RCR, rtw_read32(adapter, REG_RCR)& (~RCR_AM));
4827 DBG_871X("%s, %d, RCR= %x \n", __FUNCTION__,__LINE__, rtw_read32(adapter, REG_RCR));
4828 break;
4829 case HW_VAR_BEACON_INTERVAL:
4830 rtw_write16(adapter, REG_BCN_INTERVAL, *((u16 *)val));
4831 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
4832 {
4833 struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
4834 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
4835 u16 bcn_interval = *((u16 *)val);
4836 if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE){
4837 DBG_8192C("%s==> bcn_interval:%d, eraly_int:%d \n",__FUNCTION__,bcn_interval,bcn_interval>>1);
4838 rtw_write8(adapter, REG_DRVERLYINT, bcn_interval>>1);// 50ms for sdio
4839 }
4840 }
4841 #endif//CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
4842
4843 break;
4844 case HW_VAR_SLOT_TIME:
4845 {
4846 rtw_write8(adapter, REG_SLOT, val[0]);
4847 }
4848 break;
4849 case HW_VAR_ACK_PREAMBLE:
4850 {
4851 u8 regTmp;
4852 u8 bShortPreamble = *( (PBOOLEAN)val );
4853 // Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily)
4854 regTmp = (pHalData->nCur40MhzPrimeSC)<<5;
4855 rtw_write8(adapter, REG_RRSR+2, regTmp);
4856
4857 regTmp = rtw_read8(adapter,REG_WMAC_TRXPTCL_CTL+2);
4858 if(bShortPreamble)
4859 regTmp |= BIT1;
4860 else
4861 regTmp &= (~BIT1);
4862 rtw_write8(adapter,REG_WMAC_TRXPTCL_CTL+2,regTmp);
4863 }
4864 break;
4865 case HW_VAR_CAM_EMPTY_ENTRY:
4866 {
4867 u8 ucIndex = *((u8 *)val);
4868 u8 i;
4869 u32 ulCommand=0;
4870 u32 ulContent=0;
4871 u32 ulEncAlgo=CAM_AES;
4872
4873 for(i=0;i<CAM_CONTENT_COUNT;i++)
4874 {
4875 // filled id in CAM config 2 byte
4876 if( i == 0)
4877 {
4878 ulContent |=(ucIndex & 0x03) | ((u16)(ulEncAlgo)<<2);
4879 //ulContent |= CAM_VALID;
4880 }
4881 else
4882 {
4883 ulContent = 0;
4884 }
4885 // polling bit, and No Write enable, and address
4886 ulCommand= CAM_CONTENT_COUNT*ucIndex+i;
4887 ulCommand= ulCommand | CAM_POLLINIG|CAM_WRITE;
4888 // write content 0 is equall to mark invalid
4889 rtw_write32(adapter, WCAMI, ulContent); //delay_ms(40);
4890 //RT_TRACE(COMP_SEC, DBG_LOUD, ("CAM_empty_entry(): WRITE A4: %lx \n",ulContent));
4891 rtw_write32(adapter, RWCAM, ulCommand); //delay_ms(40);
4892 //RT_TRACE(COMP_SEC, DBG_LOUD, ("CAM_empty_entry(): WRITE A0: %lx \n",ulCommand));
4893 }
4894 }
4895 break;
4896 case HW_VAR_CAM_INVALID_ALL:
4897 rtw_write32(adapter, RWCAM, BIT(31)|BIT(30));
4898 break;
4899 case HW_VAR_CAM_WRITE:
4900 {
4901 u32 cmd;
4902 u32 *cam_val = (u32 *)val;
4903 rtw_write32(adapter, WCAMI, cam_val[0]);
4904
4905 cmd = CAM_POLLINIG | CAM_WRITE | cam_val[1];
4906 rtw_write32(adapter, RWCAM, cmd);
4907 }
4908 break;
4909 case HW_VAR_AC_PARAM_VO:
4910 rtw_write32(adapter, REG_EDCA_VO_PARAM, ((u32 *)(val))[0]);
4911 break;
4912 case HW_VAR_AC_PARAM_VI:
4913 rtw_write32(adapter, REG_EDCA_VI_PARAM, ((u32 *)(val))[0]);
4914 break;
4915 case HW_VAR_AC_PARAM_BE:
4916 pHalData->AcParam_BE = ((u32 *)(val))[0];
4917 rtw_write32(adapter, REG_EDCA_BE_PARAM, ((u32 *)(val))[0]);
4918 break;
4919 case HW_VAR_AC_PARAM_BK:
4920 rtw_write32(adapter, REG_EDCA_BK_PARAM, ((u32 *)(val))[0]);
4921 break;
4922 case HW_VAR_ACM_CTRL:
4923 {
4924 u8 acm_ctrl = *((u8 *)val);
4925 u8 AcmCtrl = rtw_read8( adapter, REG_ACMHWCTRL);
4926
4927 if(acm_ctrl > 1)
4928 AcmCtrl = AcmCtrl | 0x1;
4929
4930 if(acm_ctrl & BIT(3))
4931 AcmCtrl |= AcmHw_VoqEn;
4932 else
4933 AcmCtrl &= (~AcmHw_VoqEn);
4934
4935 if(acm_ctrl & BIT(2))
4936 AcmCtrl |= AcmHw_ViqEn;
4937 else
4938 AcmCtrl &= (~AcmHw_ViqEn);
4939
4940 if(acm_ctrl & BIT(1))
4941 AcmCtrl |= AcmHw_BeqEn;
4942 else
4943 AcmCtrl &= (~AcmHw_BeqEn);
4944
4945 DBG_871X("[HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl );
4946 rtw_write8(adapter, REG_ACMHWCTRL, AcmCtrl );
4947 }
4948 break;
4949 case HW_VAR_AMPDU_FACTOR:
4950 {
4951 u8 RegToSet_Normal[4]={0x41,0xa8,0x72, 0xb9};
4952 u8 RegToSet_BT[4]={0x31,0x74,0x42, 0x97};
4953 u8 FactorToSet;
4954 u8 *pRegToSet;
4955 u8 index = 0;
4956
4957 #ifdef CONFIG_BT_COEXIST
4958 if( (pHalData->bt_coexist.BT_Coexist) &&
4959 (pHalData->bt_coexist.BT_CoexistType == BT_CSR_BC4) )
4960 pRegToSet = RegToSet_BT; // 0x97427431;
4961 else
4962 #endif
4963 pRegToSet = RegToSet_Normal; // 0xb972a841;
4964
4965 FactorToSet = *((u8 *)val);
4966 if(FactorToSet <= 3)
4967 {
4968 FactorToSet = (1<<(FactorToSet + 2));
4969 if(FactorToSet>0xf)
4970 FactorToSet = 0xf;
4971
4972 for(index=0; index<4; index++)
4973 {
4974 if((pRegToSet[index] & 0xf0) > (FactorToSet<<4))
4975 pRegToSet[index] = (pRegToSet[index] & 0x0f) | (FactorToSet<<4);
4976
4977 if((pRegToSet[index] & 0x0f) > FactorToSet)
4978 pRegToSet[index] = (pRegToSet[index] & 0xf0) | (FactorToSet);
4979
4980 rtw_write8(adapter, (REG_AGGLEN_LMT+index), pRegToSet[index]);
4981 }
4982
4983 //RT_TRACE(COMP_MLME, DBG_LOUD, ("Set HW_VAR_AMPDU_FACTOR: %#x\n", FactorToSet));
4984 }
4985 }
4986 break;
4987 case HW_VAR_H2C_FW_PWRMODE:
4988 {
4989 u8 psmode = (*(u8 *)val);
4990
4991 // Forece leave RF low power mode for 1T1R to prevent conficting setting in Fw power
4992 // saving sequence. 2010.06.07. Added by tynli. Suggested by SD3 yschang.
4993 if (psmode != PS_MODE_ACTIVE)
4994 {
4995 ODM_RF_Saving(podmpriv, _TRUE);
4996 }
4997 rtl8188e_set_FwPwrMode_cmd(adapter, psmode);
4998 }
4999 break;
5000 case HW_VAR_H2C_FW_JOINBSSRPT:
5001 {
5002 u8 mstatus = (*(u8 *)val);
5003 rtl8188e_set_FwJoinBssReport_cmd(adapter, mstatus);
5004 }
5005 break;
5006 #ifdef CONFIG_P2P_PS
5007 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
5008 {
5009 u8 p2p_ps_state = (*(u8 *)val);
5010 rtl8188e_set_p2p_ps_offload_cmd(adapter, p2p_ps_state);
5011 }
5012 break;
5013 #endif //CONFIG_P2P_PS
5014 #ifdef CONFIG_TDLS
5015 case HW_VAR_TDLS_WRCR:
5016 rtw_write32(adapter, REG_RCR, rtw_read32(adapter, REG_RCR)&(~RCR_CBSSID_DATA ));
5017 break;
5018 case HW_VAR_TDLS_RS_RCR:
5019 rtw_write32(adapter, REG_RCR, rtw_read32(adapter, REG_RCR)|(RCR_CBSSID_DATA));
5020 break;
5021 #endif //CONFIG_TDLS
5022 #ifdef CONFIG_BT_COEXIST
5023 case HW_VAR_BT_SET_COEXIST:
5024 {
5025 u8 bStart = (*(u8 *)val);
5026 rtl8192c_set_dm_bt_coexist(adapter, bStart);
5027 }
5028 break;
5029 case HW_VAR_BT_ISSUE_DELBA:
5030 {
5031 u8 dir = (*(u8 *)val);
5032 rtl8192c_issue_delete_ba(adapter, dir);
5033 }
5034 break;
5035 #endif
5036 #if (RATE_ADAPTIVE_SUPPORT==1)
5037 case HW_VAR_RPT_TIMER_SETTING:
5038 {
5039 u16 min_rpt_time = (*(u16 *)val);
5040
5041 //DBG_8192C("==> HW_VAR_ANTENNA_DIVERSITY_SELECT , Ant_(%s)\n",(Optimum_antenna==2)?"A":"B");
5042
5043 ODM_RA_Set_TxRPT_Time(podmpriv,min_rpt_time);
5044 }
5045 break;
5046 #endif
5047
5048 #ifdef CONFIG_SW_ANTENNA_DIVERSITY
5049 case HW_VAR_ANTENNA_DIVERSITY_LINK:
5050 //odm_SwAntDivRestAfterLink8192C(Adapter);
5051 ODM_SwAntDivRestAfterLink(podmpriv);
5052 break;
5053 #endif
5054 #ifdef CONFIG_ANTENNA_DIVERSITY
5055 case HW_VAR_ANTENNA_DIVERSITY_SELECT:
5056 {
5057 u8 Optimum_antenna = (*(u8 *)val);
5058 u8 Ant ;
5059 //switch antenna to Optimum_antenna
5060 //DBG_8192C("==> HW_VAR_ANTENNA_DIVERSITY_SELECT , Ant_(%s)\n",(Optimum_antenna==2)?"A":"B");
5061 if(pHalData->CurAntenna != Optimum_antenna)
5062 {
5063 Ant = (Optimum_antenna==2)?MAIN_ANT:AUX_ANT;
5064 ODM_UpdateRxIdleAnt(&pHalData->odmpriv, Ant);
5065
5066 pHalData->CurAntenna = Optimum_antenna ;
5067 //DBG_8192C("==> HW_VAR_ANTENNA_DIVERSITY_SELECT , Ant_(%s)\n",(Optimum_antenna==2)?"A":"B");
5068 }
5069 }
5070 break;
5071 #endif
5072 case HW_VAR_EFUSE_BYTES: // To set EFUE total used bytes, added by Roger, 2008.12.22.
5073 pHalData->EfuseUsedBytes = *((u16 *)val);
5074 break;
5075 case HW_VAR_FIFO_CLEARN_UP:
5076 {
5077 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
5078 u8 trycnt = 100;
5079
5080 //pause tx
5081 rtw_write8(adapter,REG_TXPAUSE,0xff);
5082
5083 //keep sn
5084 adapter->xmitpriv.nqos_ssn = rtw_read16(adapter,REG_NQOS_SEQ);
5085
5086 if(pwrpriv->bkeepfwalive != _TRUE)
5087 {
5088 //RX DMA stop
5089 rtw_write32(adapter,REG_RXPKT_NUM,(rtw_read32(adapter,REG_RXPKT_NUM)|RW_RELEASE_EN));
5090 do{
5091 if(!(rtw_read32(adapter,REG_RXPKT_NUM)&RXDMA_IDLE))
5092 break;
5093 }while(trycnt--);
5094 if(trycnt ==0)
5095 DBG_8192C("Stop RX DMA failed...... \n");
5096
5097 //RQPN Load 0
5098 rtw_write16(adapter,REG_RQPN_NPQ,0x0);
5099 rtw_write32(adapter,REG_RQPN,0x80000000);
5100 rtw_mdelay_os(10);
5101 }
5102 }
5103 break;
5104
5105 case HW_VAR_RESTORE_HW_SEQ:
5106 /* restore Sequence No. */
5107 rtw_write8(adapter, 0x4dc, adapter->xmitpriv.nqos_ssn);
5108 break;
5109
5110 case HW_VAR_APFM_ON_MAC:
5111 pHalData->bMacPwrCtrlOn = *val;
5112 DBG_871X("%s: bMacPwrCtrlOn=%d\n", __func__, pHalData->bMacPwrCtrlOn);
5113 break;
5114 #if (RATE_ADAPTIVE_SUPPORT == 1)
5115 case HW_VAR_TX_RPT_MAX_MACID:
5116 {
5117 if(pHalData->fw_ractrl == _FALSE){
5118 u8 maxMacid = *val;
5119 DBG_8192C("### MacID(%d),Set Max Tx RPT MID(%d)\n",maxMacid,maxMacid+1);
5120 rtw_write8(adapter, REG_TX_RPT_CTRL+1, maxMacid+1);
5121 }
5122 }
5123 break;
5124 #endif // (RATE_ADAPTIVE_SUPPORT == 1)
5125 case HW_VAR_H2C_MEDIA_STATUS_RPT:
5126 {
5127 rtl8188e_set_FwMediaStatus_cmd(adapter , (*(u16 *)val));
5128 }
5129 break;
5130 case HW_VAR_BCN_VALID:
5131 //BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2, write 1 to clear, Clear by sw
5132 rtw_write8(adapter, REG_TDECTRL+2, rtw_read8(adapter, REG_TDECTRL+2) | BIT0);
5133 break;
5134
5135
5136 case HW_VAR_CHECK_TXBUF:
5137 {
5138 u8 retry_limit;
5139 u16 val16;
5140 u32 reg_200 = 0, reg_204 = 0;
5141 u32 init_reg_200 = 0, init_reg_204 = 0;
5142 u32 start = rtw_get_current_time();
5143 u32 pass_ms;
5144 int i = 0;
5145
5146 retry_limit = 0x01;
5147
5148 val16 = retry_limit << RETRY_LIMIT_SHORT_SHIFT | retry_limit << RETRY_LIMIT_LONG_SHIFT;
5149 rtw_write16(adapter, REG_RL, val16);
5150
5151 while (rtw_get_passing_time_ms(start) < 2000
5152 && !RTW_CANNOT_RUN(adapter)
5153 ) {
5154 reg_200 = rtw_read32(adapter, 0x200);
5155 reg_204 = rtw_read32(adapter, 0x204);
5156
5157 if (i == 0) {
5158 init_reg_200 = reg_200;
5159 init_reg_204 = reg_204;
5160 }
5161
5162 i++;
5163 if ((reg_200 & 0x00ffffff) != (reg_204 & 0x00ffffff)) {
5164 //DBG_871X("%s: (HW_VAR_CHECK_TXBUF)TXBUF NOT empty - 0x204=0x%x, 0x200=0x%x (%d)\n", __FUNCTION__, reg_204, reg_200, i);
5165 rtw_msleep_os(10);
5166 } else {
5167 break;
5168 }
5169 }
5170
5171 pass_ms = rtw_get_passing_time_ms(start);
5172
5173 if (RTW_CANNOT_RUN(adapter))
5174 ;
5175 else if (pass_ms >= 2000 || (reg_200 & 0x00ffffff) != (reg_204 & 0x00ffffff)) {
5176 DBG_871X_LEVEL(_drv_always_, "%s:(HW_VAR_CHECK_TXBUF)NOT empty(%d) in %d ms\n", __FUNCTION__, i, pass_ms);
5177 DBG_871X_LEVEL(_drv_always_, "%s:(HW_VAR_CHECK_TXBUF)0x200=0x%08x, 0x204=0x%08x (0x%08x, 0x%08x)\n",
5178 __FUNCTION__, reg_200, reg_204, init_reg_200, init_reg_204);
5179 //rtw_warn_on(1);
5180 } else {
5181 DBG_871X("%s:(HW_VAR_CHECK_TXBUF)TXBUF Empty(%d) in %d ms\n", __FUNCTION__, i, pass_ms);
5182 }
5183
5184 retry_limit = 0x30;
5185 val16 = retry_limit << RETRY_LIMIT_SHORT_SHIFT | retry_limit << RETRY_LIMIT_LONG_SHIFT;
5186 rtw_write16(adapter, REG_RL, val16);
5187 }
5188 break;
5189 case HW_VAR_RESP_SIFS:
5190 {
5191 struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
5192
5193 if((pmlmeext->cur_wireless_mode==WIRELESS_11G) ||
5194 (pmlmeext->cur_wireless_mode==WIRELESS_11BG))//WIRELESS_MODE_G){
5195 {
5196 val[0] = 0x0a;
5197 val[1] = 0x0a;
5198 } else {
5199 val[0] = 0x0e;
5200 val[1] = 0x0e;
5201 }
5202
5203 // SIFS for OFDM Data ACK
5204 rtw_write8(adapter, REG_SIFS_CTX+1, val[0]);
5205 // SIFS for OFDM consecutive tx like CTS data!
5206 rtw_write8(adapter, REG_SIFS_TRX+1, val[1]);
5207
5208 rtw_write8(adapter, REG_SPEC_SIFS+1, val[0]);
5209 rtw_write8(adapter, REG_MAC_SPEC_SIFS+1, val[0]);
5210
5211 //RESP_SIFS for OFDM
5212 rtw_write8(adapter, REG_RESP_SIFS_OFDM, val[0]);
5213 rtw_write8(adapter, REG_RESP_SIFS_OFDM+1, val[0]);
5214 }
5215 break;
5216
5217 case HW_VAR_MACID_SLEEP:
5218 {
5219 u32 reg_macid_sleep;
5220 u8 bit_shift;
5221 u8 id = *(u8*)val;
5222 u32 val32;
5223
5224 if (id < 32){
5225 reg_macid_sleep = REG_MACID_PAUSE_0;
5226 bit_shift = id;
5227 } else if (id < 64) {
5228 reg_macid_sleep = REG_MACID_PAUSE_1;
5229 bit_shift = id-32;
5230 } else {
5231 rtw_warn_on(1);
5232 break;
5233 }
5234
5235 val32 = rtw_read32(adapter, reg_macid_sleep);
5236 DBG_8192C(FUNC_ADPT_FMT ": [HW_VAR_MACID_SLEEP] macid=%d, org reg_0x%03x=0x%08X\n",
5237 FUNC_ADPT_ARG(adapter), id, reg_macid_sleep, val32);
5238
5239 if (val32 & BIT(bit_shift))
5240 break;
5241
5242 val32 |= BIT(bit_shift);
5243 rtw_write32(adapter, reg_macid_sleep, val32);
5244 }
5245 break;
5246
5247 case HW_VAR_MACID_WAKEUP:
5248 {
5249 u32 reg_macid_sleep;
5250 u8 bit_shift;
5251 u8 id = *(u8*)val;
5252 u32 val32;
5253
5254 if (id < 32){
5255 reg_macid_sleep = REG_MACID_PAUSE_0;
5256 bit_shift = id;
5257 } else if (id < 64) {
5258 reg_macid_sleep = REG_MACID_PAUSE_1;
5259 bit_shift = id-32;
5260 } else {
5261 rtw_warn_on(1);
5262 break;
5263 }
5264
5265 val32 = rtw_read32(adapter, reg_macid_sleep);
5266 DBG_8192C(FUNC_ADPT_FMT ": [HW_VAR_MACID_WAKEUP] macid=%d, org reg_0x%03x=0x%08X\n",
5267 FUNC_ADPT_ARG(adapter), id, reg_macid_sleep, val32);
5268
5269 if (!(val32 & BIT(bit_shift)))
5270 break;
5271
5272 val32 &= ~BIT(bit_shift);
5273 rtw_write32(adapter, reg_macid_sleep, val32);
5274 }
5275 break;
5276
5277 default:
5278 SetHwReg(adapter, variable, val);
5279 break;
5280 }
5281
5282 _func_exit_;
5283 }
5284
5285 struct qinfo_88e {
5286 u32 head:8;
5287 u32 pkt_num:8;
5288 u32 tail:8;
5289 u32 ac:2;
5290 u32 macid:6;
5291 };
5292
5293 struct bcn_qinfo_88e {
5294 u16 head:8;
5295 u16 pkt_num:8;
5296 };
5297
dump_qinfo_88e(void * sel,struct qinfo_88e * info,const char * tag)5298 void dump_qinfo_88e(void *sel, struct qinfo_88e *info, const char *tag)
5299 {
5300 //if (info->pkt_num)
5301 DBG_871X_SEL_NL(sel, "%shead:0x%02x, tail:0x%02x, pkt_num:%u, macid:%u, ac:%u\n"
5302 , tag ? tag : "", info->head, info->tail, info->pkt_num, info->macid, info->ac
5303 );
5304 }
5305
dump_bcn_qinfo_88e(void * sel,struct bcn_qinfo_88e * info,const char * tag)5306 void dump_bcn_qinfo_88e(void *sel, struct bcn_qinfo_88e *info, const char *tag)
5307 {
5308 //if (info->pkt_num)
5309 DBG_871X_SEL_NL(sel, "%shead:0x%02x, pkt_num:%u\n"
5310 , tag ? tag : "", info->head, info->pkt_num
5311 );
5312 }
5313
dump_mac_qinfo_88e(void * sel,_adapter * adapter)5314 void dump_mac_qinfo_88e(void *sel, _adapter *adapter)
5315 {
5316 u32 q0_info;
5317 u32 q1_info;
5318 u32 q2_info;
5319 u32 q3_info;
5320 /*
5321 u32 q4_info;
5322 u32 q5_info;
5323 u32 q6_info;
5324 u32 q7_info;
5325 */
5326 u32 mg_q_info;
5327 u32 hi_q_info;
5328 u16 bcn_q_info;
5329
5330 q0_info = rtw_read32(adapter, REG_Q0_INFO);
5331 q1_info = rtw_read32(adapter, REG_Q1_INFO);
5332 q2_info = rtw_read32(adapter, REG_Q2_INFO);
5333 q3_info = rtw_read32(adapter, REG_Q3_INFO);
5334 /*
5335 q4_info = rtw_read32(adapter, REG_Q4_INFO);
5336 q5_info = rtw_read32(adapter, REG_Q5_INFO);
5337 q6_info = rtw_read32(adapter, REG_Q6_INFO);
5338 q7_info = rtw_read32(adapter, REG_Q7_INFO);
5339 */
5340 mg_q_info = rtw_read32(adapter, REG_MGQ_INFO);
5341 hi_q_info = rtw_read32(adapter, REG_HGQ_INFO);
5342 bcn_q_info = rtw_read16(adapter, REG_BCNQ_INFO);
5343
5344 dump_qinfo_88e(sel, (struct qinfo_88e *)&q0_info, "Q0 ");
5345 dump_qinfo_88e(sel, (struct qinfo_88e *)&q1_info, "Q1 ");
5346 dump_qinfo_88e(sel, (struct qinfo_88e *)&q2_info, "Q2 ");
5347 dump_qinfo_88e(sel, (struct qinfo_88e *)&q3_info, "Q3 ");
5348 /*
5349 dump_qinfo_88e(sel, (struct qinfo_88e *)&q4_info, "Q4 ");
5350 dump_qinfo_88e(sel, (struct qinfo_88e *)&q5_info, "Q5 ");
5351 dump_qinfo_88e(sel, (struct qinfo_88e *)&q6_info, "Q6 ");
5352 dump_qinfo_88e(sel, (struct qinfo_88e *)&q7_info, "Q7 ");
5353 */
5354 dump_qinfo_88e(sel, (struct qinfo_88e *)&mg_q_info, "MG ");
5355 dump_qinfo_88e(sel, (struct qinfo_88e *)&hi_q_info, "HI ");
5356 dump_bcn_qinfo_88e(sel, (struct bcn_qinfo_88e *)&bcn_q_info, "BCN ");
5357 }
5358
GetHwReg8188E(_adapter * adapter,u8 variable,u8 * val)5359 void GetHwReg8188E(_adapter *adapter, u8 variable, u8 *val)
5360 {
5361 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
5362
5363 _func_enter_;
5364
5365 switch (variable) {
5366 case HW_VAR_SYS_CLKR:
5367 *val = rtw_read8(adapter, REG_SYS_CLKR);
5368 break;
5369
5370 case HW_VAR_TXPAUSE:
5371 val[0] = rtw_read8(adapter, REG_TXPAUSE);
5372 break;
5373 case HW_VAR_BCN_VALID:
5374 //BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2
5375 val[0] = (BIT0 & rtw_read8(adapter, REG_TDECTRL+2))?_TRUE:_FALSE;
5376 break;
5377 case HW_VAR_FWLPS_RF_ON:
5378 {
5379 //When we halt NIC, we should check if FW LPS is leave.
5380 if(adapter_to_pwrctl(adapter)->rf_pwrstate == rf_off)
5381 {
5382 // If it is in HW/SW Radio OFF or IPS state, we do not check Fw LPS Leave,
5383 // because Fw is unload.
5384 val[0] = _TRUE;
5385 }
5386 else
5387 {
5388 u32 valRCR;
5389 valRCR = rtw_read32(adapter, REG_RCR);
5390 valRCR &= 0x00070000;
5391 if(valRCR)
5392 val[0] = _FALSE;
5393 else
5394 val[0] = _TRUE;
5395 }
5396 }
5397 break;
5398 #ifdef CONFIG_ANTENNA_DIVERSITY
5399 case HW_VAR_CURRENT_ANTENNA:
5400 val[0] = pHalData->CurAntenna;
5401 break;
5402 #endif
5403 case HW_VAR_EFUSE_BYTES: // To get EFUE total used bytes, added by Roger, 2008.12.22.
5404 *((u16 *)(val)) = pHalData->EfuseUsedBytes;
5405 break;
5406 case HW_VAR_APFM_ON_MAC:
5407 *val = pHalData->bMacPwrCtrlOn;
5408 break;
5409 case HW_VAR_CHK_HI_QUEUE_EMPTY:
5410 *val = ((rtw_read32(adapter, REG_HGQ_INFO)&0x0000ff00)==0) ? _TRUE:_FALSE;
5411 break;
5412 case HW_VAR_DUMP_MAC_QUEUE_INFO:
5413 dump_mac_qinfo_88e(val, adapter);
5414 break;
5415 default:
5416 GetHwReg(adapter, variable, val);
5417 break;
5418 }
5419
5420 _func_exit_;
5421 }
5422
5423 u8
GetHalDefVar8188E(IN PADAPTER Adapter,IN HAL_DEF_VARIABLE eVariable,IN PVOID pValue)5424 GetHalDefVar8188E(
5425 IN PADAPTER Adapter,
5426 IN HAL_DEF_VARIABLE eVariable,
5427 IN PVOID pValue
5428 )
5429 {
5430 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
5431 u8 bResult = _SUCCESS;
5432
5433 switch(eVariable)
5434 {
5435 case HAL_DEF_IS_SUPPORT_ANT_DIV:
5436 #ifdef CONFIG_ANTENNA_DIVERSITY
5437 *((u8 *)pValue) = (pHalData->AntDivCfg==0)?_FALSE:_TRUE;
5438 #endif
5439 break;
5440 case HAL_DEF_CURRENT_ANTENNA:
5441 #ifdef CONFIG_ANTENNA_DIVERSITY
5442 *(( u8*)pValue) = pHalData->CurAntenna;
5443 #endif
5444 break;
5445 case HAL_DEF_DRVINFO_SZ:
5446 *(( u32*)pValue) = DRVINFO_SZ;
5447 break;
5448 case HAL_DEF_MAX_RECVBUF_SZ:
5449 #ifdef CONFIG_SDIO_HCI
5450 *((u32 *)pValue) = MAX_RX_DMA_BUFFER_SIZE_88E(Adapter);
5451 #else
5452 *((u32 *)pValue) = MAX_RECVBUF_SZ;
5453 #endif
5454 break;
5455 case HAL_DEF_RX_PACKET_OFFSET:
5456 *(( u32*)pValue) = RXDESC_SIZE + DRVINFO_SZ*8;
5457 break;
5458 #if (RATE_ADAPTIVE_SUPPORT == 1)
5459 case HAL_DEF_RA_DECISION_RATE:
5460 {
5461 u8 MacID = *((u8*)pValue);
5462 *((u8*)pValue) = ODM_RA_GetDecisionRate_8188E(&(pHalData->odmpriv), MacID);
5463 }
5464 break;
5465
5466 case HAL_DEF_RA_SGI:
5467 {
5468 u8 MacID = *((u8*)pValue);
5469 *((u8*)pValue) = ODM_RA_GetShortGI_8188E(&(pHalData->odmpriv), MacID);
5470 }
5471 break;
5472 #endif
5473
5474
5475 case HAL_DEF_PT_PWR_STATUS:
5476 #if(POWER_TRAINING_ACTIVE==1)
5477 {
5478 u8 MacID = *((u8*)pValue);
5479 *((u8*)pValue) = ODM_RA_GetHwPwrStatus_8188E(&(pHalData->odmpriv), MacID);
5480 }
5481 #endif //(POWER_TRAINING_ACTIVE==1)
5482 break;
5483 case HAL_DEF_EXPLICIT_BEAMFORMEE:
5484 case HAL_DEF_EXPLICIT_BEAMFORMER:
5485 *((u8 *)pValue) = _FALSE;
5486 break;
5487
5488 case HW_DEF_RA_INFO_DUMP:
5489
5490 {
5491 u8 mac_id = *((u8*)pValue);
5492 u8 bLinked = _FALSE;
5493 #ifdef CONFIG_CONCURRENT_MODE
5494 PADAPTER pbuddy_adapter = Adapter->pbuddy_adapter;
5495 #endif //CONFIG_CONCURRENT_MODE
5496
5497 if(rtw_linked_check(Adapter))
5498 bLinked = _TRUE;
5499
5500 #ifdef CONFIG_CONCURRENT_MODE
5501 if(pbuddy_adapter && rtw_linked_check(pbuddy_adapter))
5502 bLinked = _TRUE;
5503 #endif
5504
5505 if(bLinked){
5506 DBG_871X("============ RA status - Mac_id:%d ===================\n",mac_id);
5507 if(pHalData->fw_ractrl == _FALSE){
5508 #if (RATE_ADAPTIVE_SUPPORT == 1)
5509 DBG_8192C("Mac_id:%d ,RSSI:%d(%%) ,PTStage = %d\n",
5510 mac_id,pHalData->odmpriv.RAInfo[mac_id].RssiStaRA,pHalData->odmpriv.RAInfo[mac_id].PTStage);
5511
5512 DBG_8192C("RateID = %d,RAUseRate = 0x%08x,RateSGI = %d, DecisionRate = %s\n",
5513 pHalData->odmpriv.RAInfo[mac_id].RateID,
5514 pHalData->odmpriv.RAInfo[mac_id].RAUseRate,
5515 pHalData->odmpriv.RAInfo[mac_id].RateSGI,
5516 HDATA_RATE(pHalData->odmpriv.RAInfo[mac_id].DecisionRate));
5517 #endif // (RATE_ADAPTIVE_SUPPORT == 1)
5518 }else{
5519 u8 cur_rate = rtw_read8(Adapter,REG_ADAPTIVE_DATA_RATE_0+mac_id);
5520 u8 sgi = (cur_rate & BIT7)?_TRUE:_FALSE;
5521 cur_rate &= 0x7f;
5522 DBG_8192C("Mac_id:%d ,SGI:%d ,Rate:%s \n",mac_id,sgi,HDATA_RATE(cur_rate));
5523 }
5524 }
5525 }
5526
5527 break;
5528 case HAL_DEF_TX_PAGE_SIZE:
5529 *(( u32*)pValue) = PAGE_SIZE_128;
5530 break;
5531 case HAL_DEF_TX_PAGE_BOUNDARY:
5532 if (!Adapter->registrypriv.wifi_spec)
5533 *(u8*)pValue = TX_PAGE_BOUNDARY_88E(Adapter);
5534 else
5535 *(u8*)pValue = WMM_NORMAL_TX_PAGE_BOUNDARY_88E(Adapter);
5536 break;
5537 case HAL_DEF_MACID_SLEEP:
5538 *(u8*)pValue = _TRUE; // support macid sleep
5539 break;
5540 case HAL_DEF_RX_DMA_SZ_WOW:
5541 *(u32 *)pValue = RX_DMA_SIZE_88E(Adapter) - RESV_FMWF;
5542 break;
5543 case HAL_DEF_RX_DMA_SZ:
5544 *(u32 *)pValue = MAX_RX_DMA_BUFFER_SIZE_88E(Adapter);
5545 break;
5546 case HAL_DEF_RX_PAGE_SIZE:
5547 *(u32 *)pValue = PAGE_SIZE_128;
5548 break;
5549 default:
5550 bResult = GetHalDefVar(Adapter, eVariable, pValue);
5551 break;
5552 }
5553
5554 return bResult;
5555 }
5556
5557