1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /******************************************************************************** 3 * 4 * Copyright (C) 2017 NEXTCHIP Inc. All rights reserved. 5 * Module : video_eq.h 6 * Description : 7 * Author : 8 * Date : 9 * Version : Version 1.0 10 * 11 ******************************************************************************** 12 * History : 13 * 14 * 15 ********************************************************************************/ 16 #ifndef _JAGUAR1_VIDEO_EQ_H_ 17 #define _JAGUAR1_VIDEO_EQ_H_ 18 19 #include "jaguar1_common.h" 20 21 typedef struct _video_equalizer_hsync_stage_s{ 22 unsigned int hsync_stage[6]; 23 }video_equalizer_hsync_stage_s; 24 25 typedef struct _video_equalizer_agc_stage_s{ 26 unsigned int agc_stage[6]; 27 }video_equalizer_agc_stage_s; 28 29 typedef struct _video_equalizer_distance_table_s{ 30 video_equalizer_hsync_stage_s hsync_stage; 31 video_equalizer_agc_stage_s agc_stage; 32 } video_equalizer_distance_table_s; 33 34 35 typedef struct _video_equalizer_base_s{ 36 unsigned char eq_bypass[11]; // B5x01 37 unsigned char eq_band_sel[11]; // B5x58 38 unsigned char eq_gain_sel[11]; // B5x5C 39 40 unsigned char deq_a_on[11]; // BAx3d 41 unsigned char deq_a_sel[11]; // BAx3C 42 43 } video_equalizer_base_s; 44 45 typedef struct _video_equalizer_coeff_s{ 46 47 unsigned char deqA_01[11]; // BankA 0x30 48 unsigned char deqA_02[11]; // BankA 0x31 49 unsigned char deqA_03[11]; // BankA 0x32 50 unsigned char deqA_04[11]; // BankA 0x33 51 unsigned char deqA_05[11]; // BankA 0x34 52 unsigned char deqA_06[11]; // BankA 0x35 53 unsigned char deqA_07[11]; // BankA 0x36 54 unsigned char deqA_08[11]; // BankA 0x37 55 unsigned char deqA_09[11]; // BankA 0x38 56 unsigned char deqA_10[11]; // BankA 0x39 57 unsigned char deqA_11[11]; // BankA 0x3A 58 unsigned char deqA_12[11]; // BankA 0x3B 59 60 } video_equalizer_coeff_s; 61 62 typedef struct _video_equalizer_color_s{ 63 unsigned char contrast[11]; // Bank0 0x10 64 unsigned char y_peaking_mode[11]; // Bank0 0x18 65 unsigned char y_fir_mode [11]; 66 unsigned char c_filter[11]; // Bank0 0x21 67 unsigned char pal_cm_off[11]; // Bank0 0x21 68 unsigned char hue[11]; // Bank0 0x40 69 unsigned char u_gain[11]; // Bank0 0x44 70 unsigned char v_gain[11]; // Bank0 0x48 71 unsigned char u_offset[11]; // Bank0 0x4c 72 unsigned char v_offset[11]; // Bank0 0x50 73 74 unsigned char black_level[11]; // Bank5 0x20 75 unsigned char acc_ref[11]; // Bank5 0x27 76 77 unsigned char cti_delay[11]; // Bank5 0x28 78 unsigned char saturation_b[11]; // Bank5 0x2B 79 unsigned char burst_dec_a[11]; // Bank5 0x24 80 unsigned char burst_dec_b[11]; // Bank5 0x5F 81 unsigned char burst_dec_c[11]; // Bank5 0xD1 82 unsigned char c_option[11]; // Bank5 0xD5 83 84 unsigned char y_filter_b[11]; // BankA 0x25 85 unsigned char y_filter_b_sel[11]; // BankA 0x27 86 87 } video_equalizer_color_s; 88 89 typedef struct _video_equalizer_timing_a_s{ 90 unsigned char h_delay_a[11]; // Bank0 0x58 91 unsigned char h_delay_b[11]; // Bank0 0x89 92 unsigned char h_delay_c[11]; // Bank0 0x8E 93 unsigned char y_delay[11]; // Bank0 0xA0 94 95 } video_equalizer_timing_a_s; 96 97 typedef struct _video_equalizer_clk_s{ 98 unsigned char clk_adc_pre[11]; // Bank1 0x84 99 unsigned char clk_adc_post[11]; // Bank1 0x8C 100 unsigned char clk_adc[11]; // Bank1 0x8C 101 102 } video_equalizer_clk_s; 103 104 typedef struct _video_equalizer_timing_b_s{ 105 unsigned char h_scaler1[11]; // B9x96 + ch*0x20 106 unsigned char h_scaler2[11]; // B9x97 + ch*0x20 107 unsigned char h_scaler3[11]; // B9x98 + ch*0x20 108 unsigned char h_scaler4[11]; // B9x99 + ch*0x20 109 unsigned char h_scaler5[11]; // B9x9a + ch*0x20 110 unsigned char h_scaler6[11]; // B9x9b + ch*0x20 111 unsigned char h_scaler7[11]; // B9x9c + ch*0x20 112 unsigned char h_scaler8[11]; // B9x9d + ch*0x20 113 unsigned char h_scaler9[11]; // B9x9e + ch*0x20 114 115 unsigned char pn_auto[11]; // B9x40 + ch 116 117 unsigned char comb_mode[11]; // B5x90 118 unsigned char h_pll_op_a[11]; // B5xB9 119 unsigned char mem_path[11]; // B5x57 120 unsigned char fsc_lock_speed[11]; //B5x25 121 122 unsigned char ahd_mode[11]; 123 unsigned char sd_mode[11]; 124 unsigned char spl_mode[11]; 125 unsigned char vblk_end[11]; 126 unsigned char afe_g_sel[11]; 127 unsigned char afe_ctr_clp[11]; 128 unsigned char d_agc_option[11]; 129 } video_equalizer_timing_b_s; 130 131 132 typedef struct _video_equalizer_value_table_s{ 133 video_equalizer_base_s eq_base; 134 video_equalizer_coeff_s eq_coeff; 135 video_equalizer_color_s eq_color; 136 137 video_equalizer_timing_a_s eq_timing_a; 138 video_equalizer_clk_s eq_clk; 139 video_equalizer_timing_b_s eq_timing_b; 140 141 } video_equalizer_value_table_s; 142 143 typedef struct _jaguar1_video_eq_value_table_s{ 144 char *name; 145 NC_VIVO_CH_FORMATDEF video_fmt; 146 NC_ANALOG_INPUT analog_input; 147 video_equalizer_base_s eq_base; 148 video_equalizer_coeff_s eq_coeff; 149 video_equalizer_color_s eq_color; 150 151 video_equalizer_timing_a_s eq_timing_a; 152 video_equalizer_clk_s eq_clk; 153 video_equalizer_timing_b_s eq_timing_b; 154 155 } _jaguar1_video_eq_value_table_s; 156 157 typedef struct _video_equalizer_info{ 158 unsigned char Ch; 159 unsigned char devnum; 160 unsigned char stage; 161 unsigned char FmtDef; 162 unsigned char Cable; 163 unsigned char Input; 164 } video_equalizer_info_s; 165 166 void video_input_eq_val_set(video_equalizer_info_s *pvin_eq_set); 167 void video_input_eq_cable_set(video_equalizer_info_s *pvin_eq_set); 168 void video_input_eq_analog_input_set(video_equalizer_info_s *pvin_eq_set); 169 170 #endif /* _JAGUAR1_VIDEO_EQ_H_ */ 171