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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: apiAUDIO_v2_customer_config.h 98 // Description: apiAUDIO_v2_customer_config.h 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 #ifdef ROLLS_ROYCE 102 103 #ifndef _AUDIO_V2_CUSTOMER_CONFIG_H_ 104 #define _AUDIO_V2_CUSTOMER_CONFIG_H_ 105 106 #ifdef __cplusplus 107 extern "C" 108 { 109 #endif 110 111 //-------------------------------------------------------------------------------------- 112 //config for different Linux Kernel Version 113 //-------------------------------------------------------------------------------------- 114 #define LINUX_KERNEL_VERSION_4_4_3 0 115 116 //-------------------------------------------------------------------------------------- 117 //config for different UTPA. 118 //-------------------------------------------------------------------------------------- 119 #define UTPA_SUPPORT_AAC_ENCODE 0 120 #define UTPA_SUPPORT_COMMON_DECODER_API 0 121 #define UTPA_SUPPORT_HDMI_TX_OUT_BYPASS 0 122 #define UTPA_SUPPORT_DOLBY_DAP 1 123 #define UTPA_SUPPORT_COMMON_CMD_API 0 124 #define UTPA_SUPPORT_XPCM_PARAM_CHANNEL_MASK 0 125 #define UTPA_SUPPORT_HDMI_TX_STATUS 0 126 #define UTPA_SUPPORT_SET_POWER_ON 1 127 #define UTPA_SUPPORT_AVC_R_MODE 0 128 #define UTPA_SUPPORT_SND_INTERNAL_DELAY 1 129 #define UTPA_SUPPORT_IS_ATMOS_STREAM 0 130 #define UTPA_SUPPORT_AAC_TYPE 0 131 132 //---DDPE Control by MCU--- 133 #define UTPA_SUPPORT_M2S_MBOX_DDPE_ENCODE_CTRL 0 134 #define M2S_MBOX_DDPE_ENCODE_CTRL 0x112DC2 135 136 //---HDMI NPCM Control by MCU--- 137 #define UTPA_SUPPORT_M2S_MBOX_MCU_HDMI_NONPCM_CTRL 0 138 #define M2S_MBOX_MCU_HDMI_NONPCM_CTRL 0x112DC8 139 /* 140 #define HDMI_MCU_FORCE_CTRL_BIT MBOX_BIT0 141 #define HDMI_NONPCM_FROM_SER2 MBOX_HDMI_NONPCM_FROM_ASND_R2_BIT //MBOX_BIT4 142 #define HDMI_NONPCM_FROM_SEDSP MBOX_HDMI_NONPCM_FROM_ASND_DSP_BIT //MBOX_BIT5 143 */ 144 145 //---[R2] MBOX_BYTE_STATUS_SELECT in decR2_proj.h--- 146 #define MBOX_BYTE_STATUS_SELECT 0x16039E 147 148 //---g_DDPBypassenable_1, g_DDPBypassenable_2 in halMAD.c--- 149 #define UTPA_SUPPORT_AC3P_INFOTYPE_HDMITX_BYPASS_ENABLE 1 150 #define DDPBYPASSENABLE_1_DEFAULT 0 151 #define DDPBYPASSENABLE_2_DEFAULT 0 152 153 //---check ASND_DSP_DDR_SIZE in ddr_config.h MUST to be sync with _MAD_DSP2_DRAM_SIZE in mhal_audio.c (ALSA kernel)--- 154 // _MAD_DMA_READER_BASE_OFFSET 155 // _MAD_PCM_PLAYBACK2_BASE_OFFSET 156 // _MAD_DMA_READER2_BASE_OFFSET 157 // _MAD_PCM_CAPTURE1_BASE_OFFSET 158 // _MAD_PCM_CAPTURE2_BASE_OFFSET 159 // _MAD_PCM_SWMIXER_CLIENT_INFO_BASE_OFFSET 160 #define UTPA_ASND_DSP_DDR_SIZE_SYNC_WITH_ALSA 0 161 162 //-------------------------------------------------------------------------------------- 163 //config for different R2. 164 //-------------------------------------------------------------------------------------- 165 #define R2_SUPPORT_MS12_PCM_RENDER_ALWAYS_ENABLE 1 166 #define R2_SUPPORT_R2DMA_READER2 1 167 #define R2_SUPPORT_R2_DEC_ISR2_EN 0 168 169 //-------------------------------------------------------------------------------------- 170 //config for different Chip. 171 //-------------------------------------------------------------------------------------- 172 #define UTPA_AUDIO_CHIP_TYPE_2R1D 1 173 #define UTPA_AUDIO_CHIP_TYPE_1R1D 0 174 #define UTPA_AUDIO_CHIP_TYPE_2D1R 0 175 #define UTPA_AUDIO_CHIP_TYPE_2D 0 176 #define UTPA_AUDIO_CHIP_TYPE_1D 0 177 178 //-------------------------------------------------------------------------------------- 179 //config for different audio common info 180 //-------------------------------------------------------------------------------------- 181 #define AUDIO_COMMON_INFO_SEDSP_MS12_DDE_DELAY 60 //ms 182 #define AUDIO_COMMON_INFO_SNDR2_MS12_DDPE_DELAY 110 //ms 183 #define AUDIO_COMMON_INFO_SNDR2_MS12_DAP_DELAY 50 //ms 184 185 //-------------------------------------------------------------------------------------- 186 //config for different customized behavior 187 //-------------------------------------------------------------------------------------- 188 //---ES Passthrough--- 189 #define CUSTOMIZED_PATCH_PARAM_ES_PASSTHROUGH 1 190 191 //---PCM Capture param rptr--- 192 #define CUSTOMIZED_PATCH_PARAM_PCM_CAPTURE1_RPTR 0 193 #define M2S_MBOX_PCM_CAPTURE_DDR_RdPtr 0x112DD4 194 195 #define CUSTOMIZED_PATCH_PARAM_PCM_CAPTURE2_RPTR 0 196 #define M2S_MBOX_PCM_CAPTURE2_DDR_RdPtr 0x112D38 197 198 //---SPDIF info NPCM wptr--- 199 #define CUSTOMIZED_PATCH_INFO_SPDIF_NPCM_WPTR 0 200 #define DSP2DmAddr_nonpcm_capture_wptr 0x3FAF 201 202 //---PCM Capture info wptr--- 203 #define CUSTOMIZED_PATCH_INFO_PCM_CAPTURE1_WPTR 0 204 #define S2M_MBOX_PCM_CAPTURE_DDR_WrPtr 0x112DF0 205 206 #define CUSTOMIZED_PATCH_INFO_PCM_CAPTURE2_WPTR 0 207 #define S2M_MBOX_PCM_CAPTURE2_DDR_WrPtr 0x112DF4 208 209 //---HDMI RX BYPASS--- 210 #define CUSTOMIZED_PATCH_PARAM_HDMI_RX_BYPASS 1 211 #define REG_AUDIO_SPDIF_OUT_CFG 0x112C8A 212 #define REG_AUDIO_SPDIF2_OUT_CFG 0x112C5E 213 214 //---Low Latency Limiter--- 215 #define CUSTOMIZED_PATCH_PARAM_LOW_LATENCY 0 216 217 //---DNSE--- 218 #define CUSTOMIZED_PATCH_PARAM_DNSE 0 219 220 //---DOLBY_ATMOS_CONTROL--- 221 #define CUSTOMIZED_PATCH_PARAM_DOLBY_ATMOS_CTRL 0 222 223 //---MCU dump R2 log--- 224 #define CUSTOMIZED_PATCH_PARAM_MCU_DUMP_R2_LOG 0 225 #define CUSTOMIZED_PATCH_INFO_MCU_DUMP_R2_LOG 0 226 227 //---ES Repeat Play--- 228 #define CUSTOMIZED_PATCH_PARAM_ES_REPEAT_PLAY 0 229 230 //---ASND DSP DDR size--- 231 #define ASND_DSP_DDR_SIZE 0x310000 232 233 //---DEC PCM1 buffer info--- 234 #define CUSTOMIZED_PATCH_INFO_DEC_PCM1_BUFFER 0 235 #define OFFSET_PCM1_DRAM_ADDR 0x0048000 236 #define PCM1_DRAM_SIZE 0xFF000 237 238 //---HDMI NPCM buffer info--- 239 #define CUSTOMIZED_PATCH_INFO_HDMI_NPCM_BUFFER 1 240 #define OFFSET_HDMI_NONPCM_DRAM_BASE 0x02A0000 241 #define HDMI_NONPCM_DRAM_SIZE 0xD8000 242 #define S2M_MBOX_HDMI_NPCM_RPTR 0x112DE8 243 #define S2M_MBOX_HDMI_NPCM_WPTR 0x112DEA 244 245 //---MS12 META DATA buffer info--- 246 #define CUSTOMIZED_PATCH_INFO_MS12_DDPE_METADATA_BUFFER 0 247 #define OFFSET_DDPENC_METADATA_DRAM_ADDR 0x030C000 248 #define DDPENC_METADATA_DRAM_SIZE 0x03100 249 #define S2M_MBOX_DDPE_METADATA_WPTR 0x112DEC 250 251 //---DEC ES1 buffer info--- 252 #define CUSTOMIZED_PATCH_INFO_DEC_ES1_BUFFER 1 253 #define ES1_DRAM_SIZE 0x20000 254 255 //---SE-DSP Force MS12 DD/DDP Encode without main sound--- 256 #define CUSTOMIZED_PATCH_PARAM_SEDSP_MS12_ENC_WO_MAIN_SND 0 257 258 //---SND-R2 Force MS12 DD/DDP Encode without main sound--- 259 #define CUSTOMIZED_PATCH_PARAM_SNDR2_MS12_ENC_WO_MAIN_SND 1 260 261 #define MBOX_BYTE_DEC_SPDIF_SEL 0x160396 262 /* 263 1R1D: 264 [7:5] SPDIF / HDMI owner (MCU inform R2 to decide who is encode owner) 265 000: DEC-R2 266 001: SND-R2 267 010: SE-DSP-DD / SE-DSP-DD 268 011: SE-DSP-PCM / SE-DSP-DDP 269 270 [4:0] raw decoder selct 271 272 2R1D: 273 [7:5] SPDIF / HDMI owner (MCU inform R2 to decide who is encode owner) 274 000: DEC-R2 275 001: SND-R2 276 010: SE-DSP-DD / SE-DSP-DD 277 011: SE-DSP-DD / SND-R2-DDP 278 279 [4:0] raw decoder selct 280 */ 281 282 //---HDMI RX swtich to PCM Debounce--- 283 #define CUSTOMIZED_PATCH_PARAM_HDMI_RX_SWITCH_TO_PCM_DEBOUNCE 1 284 285 //---HDMI RX Monitor Event CallBack--- 286 #define CUSTOMIZED_PATCH_PARAM_HDMI_RX_MONITOR_EVENT_CALLBACK 1 287 288 //-------------------------------------------------------------------------------------- 289 //config for different customized internal patch 290 //-------------------------------------------------------------------------------------- 291 //---ADEC set gain, mute--- 292 #define CUSTOMIZED_INTERNAL_PATCH_PARAM_ADEC_SET_GAIN 1 293 #define CUSTOMIZED_INTERNAL_PATCH_PARAM_ADEC_SET_MUTE 1 294 295 //---MS12 HDMI TX PCM ouput Auto Delay (for sync with NPCM)--- 296 #define CUSTOMIZED_INTERNAL_PATCH_PARAM_MS12_HDMI_TX_PCM_AUTO_AUDIO_DELAY_ENABLE 0 297 298 //input: MS12 DD/DDP/DP, HDMI output type: DD 299 #define CUSTOMIZED_INTERNAL_PATCH_MS12_HDMI_TX_PCM_DD_IN_AUTO_AUDIO_DELAY 100 //ms 300 #define CUSTOMIZED_INTERNAL_PATCH_MS12_HDMI_TX_PCM_DDP_IN_AUTO_AUDIO_DELAY 100 //ms 301 #define CUSTOMIZED_INTERNAL_PATCH_MS12_HDMI_TX_PCM_DP_IN_AUTO_AUDIO_DELAY 100 //ms 302 303 //---General Buffer Dump--- 304 #define CUSTOMIZED_INTERNAL_PATCH_PARAM_GENERAL_BUFFER_DUMP 1 305 306 //---SNDR2_MS12_PCMR_METADATA_SELECT--- 307 #define CUSTOMIZED_INTERNAL_PATCH_PARAM_SNDR2_MS12_PCMR_METADATA_SELECT 1 308 #define SNDR2_MS12_MBOX_PCMR_METADATA_SELECT 0x112E92 309 310 //---HW SRC Output Gain Compensate--- 311 #define CUSTOMIZED_INTERNAL_PATCH_HW_SRC_GAIN_COMPENSATE_I2S_OUT 13 312 #define CUSTOMIZED_INTERNAL_PATCH_HW_SRC_GAIN_COMPENSATE_SPDIF_OUT 13 313 #define CUSTOMIZED_INTERNAL_PATCH_HW_SRC_GAIN_COMPENSATE_LINE_0_OUT 13 314 #define CUSTOMIZED_INTERNAL_PATCH_HW_SRC_GAIN_COMPENSATE_LINE_1_OUT 13 315 #define CUSTOMIZED_INTERNAL_PATCH_HW_SRC_GAIN_COMPENSATE_LINE_2_OUT 13 316 #define CUSTOMIZED_INTERNAL_PATCH_HW_SRC_GAIN_COMPENSATE_LINE_3_OUT 13 317 #define CUSTOMIZED_INTERNAL_PATCH_HW_SRC_GAIN_COMPENSATE_HDMI_OUT 13 318 319 //---DDP_71 Auto Bypass--- 320 #define CUSTOMIZED_INTERNAL_PATCH_DDP_71_AUTO_BYPASS_ENABLE 1 321 #define CUSTOMIZED_INTERNAL_PATCH_DDP_71_AUTO_BYPASS_STB_HDMI_TX 0 322 #define CUSTOMIZED_INTERNAL_PATCH_DDP_71_AUTO_BYPASS_TV_HDMI_ARC 1 323 324 //---Avoid ADEC Pop Noise--- 325 #define CUSTOMIZED_INTERNAL_PATCH_AVOID_ADEC_STOP_POP_NOISE 1 326 #define CUSTOMIZED_INTERNAL_PATCH_AVOID_ADEC_PAUSE_POP_NOISE 1 327 328 //---Play/pause Cmd Delay--- 329 #define CUSTOMIZED_INTERNAL_PATCH_SET_PLAY_CMD_BY_ADEC_SOURCE_DELAY 1 330 #define CUSTOMIZED_INTERNAL_PATCH_PAUSE_DECODING_DELAY 1 331 332 //---DDPE SRS/DAP Auto Bypass--- 333 #define CUSTOMIZED_INTERNAL_PATCH_DDPE_SRS_AUTO_BYPASS_ENABLE 0 334 #define CUSTOMIZED_INTERNAL_PATCH_DDPE_DAP_AUTO_BYPASS_ENABLE 0 335 336 //---LIMITED AUDIO_DELAY for DDPE--- [SE-DSP] AUDIO_DELAY_LOWER_BOUND in audio_comm2.h 337 #define CUSTOMIZED_INTERNAL_PATCH_LIMITED_AUDIO_DELAY_ENABLE 1 338 #define AUDIO_DELAY_LOWER_BOUND 0x30 339 340 //---R2_Active_Monitor--- 341 #define CUSTOMIZED_INTERNAL_PATCH_R2_ACTIVE_MONITOR_ENABLE 0 342 #define REG_DECR2_ACK1 0xFFFFFF 343 #define REG_DECR2_ACK1_RESPONSE 0xFF 344 345 //---Initial Codec to AC3--- 346 #define CUSTOMIZED_INTERNAL_PATCH_ADEC0_INITIAL_CODEC_TYPE_AC3_ENABLE 1 347 348 //---Initial Dolby DRC mode--- 349 #define CUSTOMIZED_INTERNAL_PATCH_ADEC0_INITIAL_DOLBY_DRC_LINE_MODE 1 350 351 //---ADC Fast charge--- 352 #define CUSTOMIZED_INTERNAL_PATCH_STR_RESUME_ADC_FAST_CHARGE_ENABLE 0 353 #define REG_ADC_FAST_CHARGE 0x112CEE 354 355 #ifdef __cplusplus 356 } 357 #endif 358 359 #endif //_AUDIO_V2_CUSTOMER_CONFIG_H_ 360 361 #endif // #ifdef ROLLS_ROYCE 362