1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * 4 * (C) COPYRIGHT 2018-2023 ARM Limited. All rights reserved. 5 * 6 * This program is free software and is provided to you under the terms of the 7 * GNU General Public License version 2 as published by the Free Software 8 * Foundation, and any use by you of this program is subject to the terms 9 * of such GNU license. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, you can access it online at 18 * http://www.gnu.org/licenses/gpl-2.0.html. 19 * 20 */ 21 22 /* 23 * This header was originally autogenerated, but it is now ok (and 24 * expected) to have to add to it. 25 */ 26 27 #ifndef _KBASE_CSF_REGISTERS_H_ 28 #define _KBASE_CSF_REGISTERS_H_ 29 30 /* 31 * Begin register sets 32 */ 33 34 /* CS_KERNEL_INPUT_BLOCK base address */ 35 #define CS_KERNEL_INPUT_BLOCK_BASE 0x0000 36 #define CS_KERNEL_INPUT_BLOCK_REG(r) (CS_KERNEL_INPUT_BLOCK_BASE + (r)) 37 38 /* CS_KERNEL_OUTPUT_BLOCK base address */ 39 #define CS_KERNEL_OUTPUT_BLOCK_BASE 0x0000 40 #define CS_KERNEL_OUTPUT_BLOCK_REG(r) (CS_KERNEL_OUTPUT_BLOCK_BASE + (r)) 41 42 /* CS_USER_INPUT_BLOCK base address */ 43 #define CS_USER_INPUT_BLOCK_BASE 0x0000 44 #define CS_USER_INPUT_BLOCK_REG(r) (CS_USER_INPUT_BLOCK_BASE + (r)) 45 46 /* CS_USER_OUTPUT_BLOCK base address */ 47 #define CS_USER_OUTPUT_BLOCK_BASE 0x0000 48 #define CS_USER_OUTPUT_BLOCK_REG(r) (CS_USER_OUTPUT_BLOCK_BASE + (r)) 49 50 /* CSG_INPUT_BLOCK base address */ 51 #define CSG_INPUT_BLOCK_BASE 0x0000 52 #define CSG_INPUT_BLOCK_REG(r) (CSG_INPUT_BLOCK_BASE + (r)) 53 54 /* CSG_OUTPUT_BLOCK base address */ 55 #define CSG_OUTPUT_BLOCK_BASE 0x0000 56 #define CSG_OUTPUT_BLOCK_REG(r) (CSG_OUTPUT_BLOCK_BASE + (r)) 57 58 /* GLB_CONTROL_BLOCK base address */ 59 #define GLB_CONTROL_BLOCK_BASE 0x04000000 60 #define GLB_CONTROL_BLOCK_REG(r) (GLB_CONTROL_BLOCK_BASE + (r)) 61 62 /* GLB_INPUT_BLOCK base address */ 63 #define GLB_INPUT_BLOCK_BASE 0x0000 64 #define GLB_INPUT_BLOCK_REG(r) (GLB_INPUT_BLOCK_BASE + (r)) 65 66 /* GLB_OUTPUT_BLOCK base address */ 67 #define GLB_OUTPUT_BLOCK_BASE 0x0000 68 #define GLB_OUTPUT_BLOCK_REG(r) (GLB_OUTPUT_BLOCK_BASE + (r)) 69 70 /* End register sets */ 71 72 /* 73 * Begin register offsets 74 */ 75 76 /* DOORBELLS register offsets */ 77 #define DOORBELL_0 0x0000 /* () Doorbell 0 register */ 78 #define DOORBELL(n) (DOORBELL_0 + (n)*65536) 79 #define DOORBELL_REG(n, r) (DOORBELL(n) + DOORBELL_BLOCK_REG(r)) 80 #define DOORBELL_COUNT 1024 81 82 /* DOORBELL_BLOCK register offsets */ 83 #define DB_BLK_DOORBELL 0x0000 /* (WO) Doorbell request */ 84 85 /* CS_KERNEL_INPUT_BLOCK register offsets */ 86 #define CS_REQ 0x0000 /* () CS request flags */ 87 #define CS_CONFIG 0x0004 /* () CS configuration */ 88 #define CS_ACK_IRQ_MASK 0x000C /* () Command steam interrupt mask */ 89 #define CS_BASE_LO 0x0010 /* () Base pointer for the ring buffer, low word */ 90 #define CS_BASE_HI 0x0014 /* () Base pointer for the ring buffer, high word */ 91 #define CS_SIZE 0x0018 /* () Size of the ring buffer */ 92 #define CS_TILER_HEAP_START_LO 0x0020 /* () Pointer to heap start, low word */ 93 #define CS_TILER_HEAP_START_HI 0x0024 /* () Pointer to heap start, high word */ 94 #define CS_TILER_HEAP_END_LO 0x0028 /* () Tiler heap descriptor address, low word */ 95 #define CS_TILER_HEAP_END_HI 0x002C /* () Tiler heap descriptor address, high word */ 96 #define CS_USER_INPUT_LO 0x0030 /* () CS user mode input page address, low word */ 97 #define CS_USER_INPUT_HI 0x0034 /* () CS user mode input page address, high word */ 98 #define CS_USER_OUTPUT_LO 0x0038 /* () CS user mode input page address, low word */ 99 #define CS_USER_OUTPUT_HI 0x003C /* () CS user mode input page address, high word */ 100 #define CS_INSTR_CONFIG 0x0040 /* () Instrumentation buffer configuration */ 101 #define CS_INSTR_BUFFER_SIZE 0x0044 /* () Instrumentation buffer size */ 102 #define CS_INSTR_BUFFER_BASE_LO 0x0048 /* () Instrumentation buffer base pointer, low word */ 103 #define CS_INSTR_BUFFER_BASE_HI 0x004C /* () Instrumentation buffer base pointer, high word */ 104 #define CS_INSTR_BUFFER_OFFSET_POINTER_LO 0x0050 /* () Instrumentation buffer pointer to insert offset, low word */ 105 #define CS_INSTR_BUFFER_OFFSET_POINTER_HI 0x0054 /* () Instrumentation buffer pointer to insert offset, high word */ 106 107 /* CS_KERNEL_OUTPUT_BLOCK register offsets */ 108 #define CS_ACK 0x0000 /* () CS acknowledge flags */ 109 #define CS_STATUS_CMD_PTR_LO 0x0040 /* () Program pointer current value, low word */ 110 #define CS_STATUS_CMD_PTR_HI 0x0044 /* () Program pointer current value, high word */ 111 #define CS_STATUS_WAIT 0x0048 /* () Wait condition status register */ 112 #define CS_STATUS_REQ_RESOURCE 0x004C /* () Indicates the resources requested by the CS */ 113 #define CS_STATUS_WAIT_SYNC_POINTER_LO 0x0050 /* () Sync object pointer, low word */ 114 #define CS_STATUS_WAIT_SYNC_POINTER_HI 0x0054 /* () Sync object pointer, high word */ 115 #define CS_STATUS_WAIT_SYNC_VALUE 0x0058 /* () Sync object test value */ 116 #define CS_STATUS_SCOREBOARDS 0x005C /* () Scoreboard status */ 117 #define CS_STATUS_BLOCKED_REASON 0x0060 /* () Blocked reason */ 118 #define CS_FAULT 0x0080 /* () Recoverable fault information */ 119 #define CS_FATAL 0x0084 /* () Unrecoverable fault information */ 120 #define CS_FAULT_INFO_LO 0x0088 /* () Additional information about a recoverable fault, low word */ 121 #define CS_FAULT_INFO_HI 0x008C /* () Additional information about a recoverable fault, high word */ 122 #define CS_FATAL_INFO_LO 0x0090 /* () Additional information about a non-recoverable fault, low word */ 123 #define CS_FATAL_INFO_HI 0x0094 /* () Additional information about a non-recoverable fault, high word */ 124 #define CS_HEAP_VT_START 0x00C0 /* () Number of vertex/tiling operations started */ 125 #define CS_HEAP_VT_END 0x00C4 /* () Number of vertex/tiling operations completed */ 126 #define CS_HEAP_FRAG_END 0x00CC /* () Number of fragment completed */ 127 #define CS_HEAP_ADDRESS_LO 0x00D0 /* () Heap address, low word */ 128 #define CS_HEAP_ADDRESS_HI 0x00D4 /* () Heap address, high word */ 129 130 /* CS_USER_INPUT_BLOCK register offsets */ 131 #define CS_INSERT_LO 0x0000 /* () Current insert offset for ring buffer, low word */ 132 #define CS_INSERT_HI 0x0004 /* () Current insert offset for ring buffer, high word */ 133 #define CS_EXTRACT_INIT_LO 0x0008 /* () Initial extract offset for ring buffer, low word */ 134 #define CS_EXTRACT_INIT_HI 0x000C /* () Initial extract offset for ring buffer, high word */ 135 136 /* CS_USER_OUTPUT_BLOCK register offsets */ 137 #define CS_EXTRACT_LO 0x0000 /* () Current extract offset for ring buffer, low word */ 138 #define CS_EXTRACT_HI 0x0004 /* () Current extract offset for ring buffer, high word */ 139 #define CS_ACTIVE 0x0008 /* () Initial extract offset when the CS is started */ 140 141 /* CSG_INPUT_BLOCK register offsets */ 142 #define CSG_REQ 0x0000 /* () CSG request */ 143 #define CSG_ACK_IRQ_MASK 0x0004 /* () Global acknowledge interrupt mask */ 144 #define CSG_DB_REQ 0x0008 /* () Global doorbell request */ 145 #define CSG_IRQ_ACK 0x000C /* () CS IRQ acknowledge */ 146 #define CSG_ALLOW_COMPUTE_LO 0x0020 /* () Allowed compute endpoints, low word */ 147 #define CSG_ALLOW_COMPUTE_HI 0x0024 /* () Allowed compute endpoints, high word */ 148 #define CSG_ALLOW_FRAGMENT_LO 0x0028 /* () Allowed fragment endpoints, low word */ 149 #define CSG_ALLOW_FRAGMENT_HI 0x002C /* () Allowed fragment endpoints, high word */ 150 #define CSG_ALLOW_OTHER 0x0030 /* () Allowed other endpoints */ 151 #define CSG_EP_REQ 0x0034 /* () Maximum number of endpoints allowed */ 152 #define CSG_SUSPEND_BUF_LO 0x0040 /* () Normal mode suspend buffer, low word */ 153 #define CSG_SUSPEND_BUF_HI 0x0044 /* () Normal mode suspend buffer, high word */ 154 #define CSG_PROTM_SUSPEND_BUF_LO 0x0048 /* () Protected mode suspend buffer, low word */ 155 #define CSG_PROTM_SUSPEND_BUF_HI 0x004C /* () Protected mode suspend buffer, high word */ 156 #define CSG_CONFIG 0x0050 /* () CSG configuration options */ 157 #define CSG_ITER_TRACE_CONFIG 0x0054 /* () CSG trace configuration */ 158 #define CSG_DVS_BUF_LO 0x0060 /* () Normal mode deferred vertex shading work buffer, low word */ 159 #define CSG_DVS_BUF_HI 0x0064 /* () Normal mode deferred vertex shading work buffer, high word */ 160 161 /* CSG_OUTPUT_BLOCK register offsets */ 162 #define CSG_ACK 0x0000 /* () CSG acknowledge flags */ 163 #define CSG_DB_ACK 0x0008 /* () CS kernel doorbell acknowledge flags */ 164 #define CSG_IRQ_REQ 0x000C /* () CS interrupt request flags */ 165 #define CSG_STATUS_EP_CURRENT 0x0010 /* () Endpoint allocation status register */ 166 #define CSG_STATUS_EP_REQ 0x0014 /* () Endpoint request status register */ 167 #define CSG_RESOURCE_DEP 0x001C /* () Current resource dependencies */ 168 169 /* GLB_CONTROL_BLOCK register offsets */ 170 #define GLB_VERSION 0x0000 /* () Global interface version */ 171 #define GLB_FEATURES 0x0004 /* () Global interface features */ 172 #define GLB_INPUT_VA 0x0008 /* () Address of GLB_INPUT_BLOCK */ 173 #define GLB_OUTPUT_VA 0x000C /* () Address of GLB_OUTPUT_BLOCK */ 174 #define GLB_GROUP_NUM 0x0010 /* () Number of CSG interfaces */ 175 #define GLB_GROUP_STRIDE 0x0014 /* () Stride between CSG interfaces */ 176 #define GLB_PRFCNT_SIZE 0x0018 /* () Size of CSF performance counters */ 177 #define GLB_INSTR_FEATURES \ 178 0x001C /* () TRACE_POINT instrumentation. (csf >= 1.1.0) */ 179 #define GROUP_CONTROL_0 0x1000 /* () CSG control and capabilities */ 180 #define GROUP_CONTROL(n) (GROUP_CONTROL_0 + (n)*256) 181 #define GROUP_CONTROL_REG(n, r) (GROUP_CONTROL(n) + GROUP_CONTROL_BLOCK_REG(r)) 182 #define GROUP_CONTROL_COUNT 16 183 184 /* STREAM_CONTROL_BLOCK register offsets */ 185 #define STREAM_FEATURES 0x0000 /* () CSI features */ 186 #define STREAM_INPUT_VA 0x0004 /* () Address of CS_KERNEL_INPUT_BLOCK */ 187 #define STREAM_OUTPUT_VA 0x0008 /* () Address of CS_KERNEL_OUTPUT_BLOCK */ 188 189 /* GROUP_CONTROL_BLOCK register offsets */ 190 #define GROUP_FEATURES 0x0000 /* () CSG interface features */ 191 #define GROUP_INPUT_VA 0x0004 /* () Address of CSG_INPUT_BLOCK */ 192 #define GROUP_OUTPUT_VA 0x0008 /* () Address of CSG_OUTPUT_BLOCK */ 193 #define GROUP_SUSPEND_SIZE 0x000C /* () Size of CSG suspend buffer */ 194 #define GROUP_PROTM_SUSPEND_SIZE 0x0010 /* () Size of CSG protected-mode suspend buffer */ 195 #define GROUP_STREAM_NUM 0x0014 /* () Number of CS interfaces */ 196 #define GROUP_STREAM_STRIDE 0x0018 /* () Stride between CS interfaces */ 197 #define STREAM_CONTROL_0 0x0040 /* () CS control and capabilities */ 198 #define STREAM_CONTROL(n) (STREAM_CONTROL_0 + (n)*12) 199 #define STREAM_CONTROL_REG(n, r) (STREAM_CONTROL(n) + STREAM_CONTROL_BLOCK_REG(r)) 200 #define STREAM_CONTROL_COUNT 16 201 202 /* GLB_INPUT_BLOCK register offsets */ 203 #define GLB_REQ 0x0000 /* () Global request */ 204 #define GLB_ACK_IRQ_MASK 0x0004 /* () Global acknowledge interrupt mask */ 205 #define GLB_DB_REQ 0x0008 /* () Global doorbell request */ 206 #define GLB_PROGRESS_TIMER 0x0010 /* () Global progress timeout */ 207 #define GLB_PWROFF_TIMER 0x0014 /* () Global shader core power off timer */ 208 #define GLB_ALLOC_EN_LO 0x0018 /* () Global shader core allocation enable mask, low word */ 209 #define GLB_ALLOC_EN_HI 0x001C /* () Global shader core allocation enable mask, high word */ 210 211 #define GLB_PRFCNT_JASID 0x0024 /* () Performance counter address space */ 212 #define GLB_PRFCNT_BASE_LO 0x0028 /* () Performance counter buffer address, low word */ 213 #define GLB_PRFCNT_BASE_HI 0x002C /* () Performance counter buffer address, high word */ 214 #define GLB_PRFCNT_EXTRACT 0x0030 /* () Performance counter buffer extract index */ 215 #define GLB_PRFCNT_CONFIG 0x0040 /* () Performance counter configuration */ 216 #define GLB_PRFCNT_CSG_SELECT 0x0044 /* () CSG performance counting enable */ 217 #define GLB_PRFCNT_FW_EN 0x0048 /* () Performance counter enable for firmware */ 218 #define GLB_PRFCNT_CSG_EN 0x004C /* () Performance counter enable for CSG */ 219 #define GLB_PRFCNT_CSF_EN 0x0050 /* () Performance counter enable for CSF */ 220 #define GLB_PRFCNT_SHADER_EN 0x0054 /* () Performance counter enable for shader cores */ 221 #define GLB_PRFCNT_TILER_EN 0x0058 /* () Performance counter enable for tiler */ 222 #define GLB_PRFCNT_MMU_L2_EN 0x005C /* () Performance counter enable for MMU/L2 cache */ 223 224 #define GLB_DEBUG_ARG_IN0 0x0FE0 /* Firmware Debug argument array element 0 */ 225 #define GLB_DEBUG_ARG_IN1 0x0FE4 /* Firmware Debug argument array element 1 */ 226 #define GLB_DEBUG_ARG_IN2 0x0FE8 /* Firmware Debug argument array element 2 */ 227 #define GLB_DEBUG_ARG_IN3 0x0FEC /* Firmware Debug argument array element 3 */ 228 229 /* Mappings based on GLB_DEBUG_REQ.FWUTF_RUN bit being different from GLB_DEBUG_ACK.FWUTF_RUN */ 230 #define GLB_DEBUG_FWUTF_DESTROY GLB_DEBUG_ARG_IN0 /* () Test fixture destroy function address */ 231 #define GLB_DEBUG_FWUTF_TEST GLB_DEBUG_ARG_IN1 /* () Test index */ 232 #define GLB_DEBUG_FWUTF_FIXTURE GLB_DEBUG_ARG_IN2 /* () Test fixture index */ 233 #define GLB_DEBUG_FWUTF_CREATE GLB_DEBUG_ARG_IN3 /* () Test fixture create function address */ 234 235 #define GLB_DEBUG_ACK_IRQ_MASK 0x0FF8 /* () Global debug acknowledge interrupt mask */ 236 #define GLB_DEBUG_REQ 0x0FFC /* () Global debug request */ 237 238 /* GLB_OUTPUT_BLOCK register offsets */ 239 #define GLB_DEBUG_ARG_OUT0 0x0FE0 /* Firmware debug result element 0 */ 240 #define GLB_DEBUG_ARG_OUT1 0x0FE4 /* Firmware debug result element 1 */ 241 #define GLB_DEBUG_ARG_OUT2 0x0FE8 /* Firmware debug result element 2 */ 242 #define GLB_DEBUG_ARG_OUT3 0x0FEC /* Firmware debug result element 3 */ 243 244 #define GLB_ACK 0x0000 /* () Global acknowledge */ 245 #define GLB_DB_ACK 0x0008 /* () Global doorbell acknowledge */ 246 #define GLB_HALT_STATUS 0x0010 /* () Global halt status */ 247 #define GLB_PRFCNT_STATUS 0x0014 /* () Performance counter status */ 248 #define GLB_PRFCNT_INSERT 0x0018 /* () Performance counter buffer insert index */ 249 #define GLB_DEBUG_FWUTF_RESULT GLB_DEBUG_ARG_OUT0 /* () Firmware debug test result */ 250 #define GLB_DEBUG_ACK 0x0FFC /* () Global debug acknowledge */ 251 252 #ifdef CONFIG_MALI_CORESIGHT 253 #define GLB_DEBUG_REQ_FW_AS_WRITE_SHIFT 4 254 #define GLB_DEBUG_REQ_FW_AS_WRITE_MASK (0x1 << GLB_DEBUG_REQ_FW_AS_WRITE_SHIFT) 255 #define GLB_DEBUG_REQ_FW_AS_READ_SHIFT 5 256 #define GLB_DEBUG_REQ_FW_AS_READ_MASK (0x1 << GLB_DEBUG_REQ_FW_AS_READ_SHIFT) 257 #define GLB_DEBUG_ARG_IN0 0x0FE0 258 #define GLB_DEBUG_ARG_IN1 0x0FE4 259 #define GLB_DEBUG_ARG_OUT0 0x0FE0 260 #endif /* CONFIG_MALI_CORESIGHT */ 261 262 /* End register offsets */ 263 264 /* CS_KERNEL_INPUT_BLOCK register set definitions */ 265 /* GLB_VERSION register */ 266 #define GLB_VERSION_PATCH_SHIFT (0) 267 #define GLB_VERSION_PATCH_MASK ((0xFFFF) << GLB_VERSION_PATCH_SHIFT) 268 #define GLB_VERSION_PATCH_GET(reg_val) (((reg_val)&GLB_VERSION_PATCH_MASK) >> GLB_VERSION_PATCH_SHIFT) 269 #define GLB_VERSION_PATCH_SET(reg_val, value) \ 270 (((reg_val) & ~GLB_VERSION_PATCH_MASK) | (((value) << GLB_VERSION_PATCH_SHIFT) & GLB_VERSION_PATCH_MASK)) 271 #define GLB_VERSION_MINOR_SHIFT (16) 272 #define GLB_VERSION_MINOR_MASK ((0xFF) << GLB_VERSION_MINOR_SHIFT) 273 #define GLB_VERSION_MINOR_GET(reg_val) (((reg_val)&GLB_VERSION_MINOR_MASK) >> GLB_VERSION_MINOR_SHIFT) 274 #define GLB_VERSION_MINOR_SET(reg_val, value) \ 275 (((reg_val) & ~GLB_VERSION_MINOR_MASK) | (((value) << GLB_VERSION_MINOR_SHIFT) & GLB_VERSION_MINOR_MASK)) 276 #define GLB_VERSION_MAJOR_SHIFT (24) 277 #define GLB_VERSION_MAJOR_MASK ((0xFF) << GLB_VERSION_MAJOR_SHIFT) 278 #define GLB_VERSION_MAJOR_GET(reg_val) (((reg_val)&GLB_VERSION_MAJOR_MASK) >> GLB_VERSION_MAJOR_SHIFT) 279 #define GLB_VERSION_MAJOR_SET(reg_val, value) \ 280 (((reg_val) & ~GLB_VERSION_MAJOR_MASK) | (((value) << GLB_VERSION_MAJOR_SHIFT) & GLB_VERSION_MAJOR_MASK)) 281 282 /* CS_REQ register */ 283 #define CS_REQ_STATE_SHIFT 0 284 #define CS_REQ_STATE_MASK (0x7 << CS_REQ_STATE_SHIFT) 285 #define CS_REQ_STATE_GET(reg_val) (((reg_val)&CS_REQ_STATE_MASK) >> CS_REQ_STATE_SHIFT) 286 #define CS_REQ_STATE_SET(reg_val, value) \ 287 (((reg_val) & ~CS_REQ_STATE_MASK) | (((value) << CS_REQ_STATE_SHIFT) & CS_REQ_STATE_MASK)) 288 /* CS_REQ_STATE values */ 289 #define CS_REQ_STATE_STOP 0x0 290 #define CS_REQ_STATE_START 0x1 291 /* End of CS_REQ_STATE values */ 292 #define CS_REQ_EXTRACT_EVENT_SHIFT 4 293 #define CS_REQ_EXTRACT_EVENT_MASK (0x1 << CS_REQ_EXTRACT_EVENT_SHIFT) 294 #define CS_REQ_EXTRACT_EVENT_GET(reg_val) (((reg_val)&CS_REQ_EXTRACT_EVENT_MASK) >> CS_REQ_EXTRACT_EVENT_SHIFT) 295 #define CS_REQ_EXTRACT_EVENT_SET(reg_val, value) \ 296 (((reg_val) & ~CS_REQ_EXTRACT_EVENT_MASK) | (((value) << CS_REQ_EXTRACT_EVENT_SHIFT) & CS_REQ_EXTRACT_EVENT_MASK)) 297 298 #define CS_REQ_IDLE_SYNC_WAIT_SHIFT 8 299 #define CS_REQ_IDLE_SYNC_WAIT_MASK (0x1 << CS_REQ_IDLE_SYNC_WAIT_SHIFT) 300 #define CS_REQ_IDLE_SYNC_WAIT_GET(reg_val) (((reg_val)&CS_REQ_IDLE_SYNC_WAIT_MASK) >> CS_REQ_IDLE_SYNC_WAIT_SHIFT) 301 #define CS_REQ_IDLE_SYNC_WAIT_SET(reg_val, value) \ 302 (((reg_val) & ~CS_REQ_IDLE_SYNC_WAIT_MASK) | \ 303 (((value) << CS_REQ_IDLE_SYNC_WAIT_SHIFT) & CS_REQ_IDLE_SYNC_WAIT_MASK)) 304 #define CS_REQ_IDLE_PROTM_PEND_SHIFT 9 305 #define CS_REQ_IDLE_PROTM_PEND_MASK (0x1 << CS_REQ_IDLE_PROTM_PEND_SHIFT) 306 #define CS_REQ_IDLE_PROTM_PEND_GET(reg_val) (((reg_val)&CS_REQ_IDLE_PROTM_PEND_MASK) >> CS_REQ_IDLE_PROTM_PEND_SHIFT) 307 #define CS_REQ_IDLE_PROTM_PEND_SET(reg_val, value) \ 308 (((reg_val) & ~CS_REQ_IDLE_PROTM_PEND_MASK) | \ 309 (((value) << CS_REQ_IDLE_PROTM_PEND_SHIFT) & CS_REQ_IDLE_PROTM_PEND_MASK)) 310 #define CS_REQ_IDLE_EMPTY_SHIFT 10 311 #define CS_REQ_IDLE_EMPTY_MASK (0x1 << CS_REQ_IDLE_EMPTY_SHIFT) 312 #define CS_REQ_IDLE_EMPTY_GET(reg_val) (((reg_val)&CS_REQ_IDLE_EMPTY_MASK) >> CS_REQ_IDLE_EMPTY_SHIFT) 313 #define CS_REQ_IDLE_EMPTY_SET(reg_val, value) \ 314 (((reg_val) & ~CS_REQ_IDLE_EMPTY_MASK) | (((value) << CS_REQ_IDLE_EMPTY_SHIFT) & CS_REQ_IDLE_EMPTY_MASK)) 315 #define CS_REQ_IDLE_RESOURCE_REQ_SHIFT 11 316 #define CS_REQ_IDLE_RESOURCE_REQ_MASK (0x1 << CS_REQ_IDLE_RESOURCE_REQ_SHIFT) 317 #define CS_REQ_IDLE_RESOURCE_REQ_GET(reg_val) \ 318 (((reg_val) & CS_REQ_IDLE_RESOURCE_REQ_MASK) >> CS_REQ_IDLE_RESOURCE_REQ_SHIFT) 319 #define CS_REQ_IDLE_RESOURCE_REQ_SET(reg_val, value) \ 320 (((reg_val) & ~CS_REQ_IDLE_RESOURCE_REQ_MASK) | \ 321 (((value) << CS_REQ_IDLE_RESOURCE_REQ_SHIFT) & CS_REQ_IDLE_RESOURCE_REQ_MASK)) 322 #define CS_REQ_IDLE_SHARED_SB_DEC_SHIFT 12 323 #define CS_REQ_IDLE_SHARED_SB_DEC_MASK (0x1 << CS_REQ_IDLE_SHARED_SB_DEC_SHIFT) 324 #define CS_REQ_IDLE_SHARED_SB_DEC_GET(reg_val) \ 325 (((reg_val) & CS_REQ_IDLE_SHARED_SB_DEC_MASK) >> CS_REQ_IDLE_SHARED_SB_DEC_SHIFT) 326 #define CS_REQ_IDLE_SHARED_SB_DEC_REQ_SET(reg_val, value) \ 327 (((reg_val) & ~CS_REQ_IDLE_SHARED_SB_DEC_MASK) | \ 328 (((value) << CS_REQ_IDLE_SHARED_SB_DEC_SHIFT) & CS_REQ_IDLE_SHARED_SB_DEC_MASK)) 329 #define CS_REQ_TILER_OOM_SHIFT 26 330 #define CS_REQ_TILER_OOM_MASK (0x1 << CS_REQ_TILER_OOM_SHIFT) 331 #define CS_REQ_TILER_OOM_GET(reg_val) (((reg_val)&CS_REQ_TILER_OOM_MASK) >> CS_REQ_TILER_OOM_SHIFT) 332 #define CS_REQ_TILER_OOM_SET(reg_val, value) \ 333 (((reg_val) & ~CS_REQ_TILER_OOM_MASK) | (((value) << CS_REQ_TILER_OOM_SHIFT) & CS_REQ_TILER_OOM_MASK)) 334 #define CS_REQ_PROTM_PEND_SHIFT 27 335 #define CS_REQ_PROTM_PEND_MASK (0x1 << CS_REQ_PROTM_PEND_SHIFT) 336 #define CS_REQ_PROTM_PEND_GET(reg_val) (((reg_val)&CS_REQ_PROTM_PEND_MASK) >> CS_REQ_PROTM_PEND_SHIFT) 337 #define CS_REQ_PROTM_PEND_SET(reg_val, value) \ 338 (((reg_val) & ~CS_REQ_PROTM_PEND_MASK) | (((value) << CS_REQ_PROTM_PEND_SHIFT) & CS_REQ_PROTM_PEND_MASK)) 339 #define CS_REQ_FATAL_SHIFT 30 340 #define CS_REQ_FATAL_MASK (0x1 << CS_REQ_FATAL_SHIFT) 341 #define CS_REQ_FATAL_GET(reg_val) (((reg_val)&CS_REQ_FATAL_MASK) >> CS_REQ_FATAL_SHIFT) 342 #define CS_REQ_FATAL_SET(reg_val, value) \ 343 (((reg_val) & ~CS_REQ_FATAL_MASK) | (((value) << CS_REQ_FATAL_SHIFT) & CS_REQ_FATAL_MASK)) 344 #define CS_REQ_FAULT_SHIFT 31 345 #define CS_REQ_FAULT_MASK (0x1 << CS_REQ_FAULT_SHIFT) 346 #define CS_REQ_FAULT_GET(reg_val) (((reg_val)&CS_REQ_FAULT_MASK) >> CS_REQ_FAULT_SHIFT) 347 #define CS_REQ_FAULT_SET(reg_val, value) \ 348 (((reg_val) & ~CS_REQ_FAULT_MASK) | (((value) << CS_REQ_FAULT_SHIFT) & CS_REQ_FAULT_MASK)) 349 350 /* CS_CONFIG register */ 351 #define CS_CONFIG_PRIORITY_SHIFT 0 352 #define CS_CONFIG_PRIORITY_MASK (0xF << CS_CONFIG_PRIORITY_SHIFT) 353 #define CS_CONFIG_PRIORITY_GET(reg_val) (((reg_val)&CS_CONFIG_PRIORITY_MASK) >> CS_CONFIG_PRIORITY_SHIFT) 354 #define CS_CONFIG_PRIORITY_SET(reg_val, value) \ 355 (((reg_val) & ~CS_CONFIG_PRIORITY_MASK) | (((value) << CS_CONFIG_PRIORITY_SHIFT) & CS_CONFIG_PRIORITY_MASK)) 356 #define CS_CONFIG_USER_DOORBELL_SHIFT 8 357 #define CS_CONFIG_USER_DOORBELL_MASK (0xFF << CS_CONFIG_USER_DOORBELL_SHIFT) 358 #define CS_CONFIG_USER_DOORBELL_GET(reg_val) (((reg_val)&CS_CONFIG_USER_DOORBELL_MASK) >> CS_CONFIG_USER_DOORBELL_SHIFT) 359 #define CS_CONFIG_USER_DOORBELL_SET(reg_val, value) \ 360 (((reg_val) & ~CS_CONFIG_USER_DOORBELL_MASK) | \ 361 (((value) << CS_CONFIG_USER_DOORBELL_SHIFT) & CS_CONFIG_USER_DOORBELL_MASK)) 362 363 /* CS_ACK_IRQ_MASK register */ 364 #define CS_ACK_IRQ_MASK_STATE_SHIFT 0 365 #define CS_ACK_IRQ_MASK_STATE_MASK (0x7 << CS_ACK_IRQ_MASK_STATE_SHIFT) 366 #define CS_ACK_IRQ_MASK_STATE_GET(reg_val) (((reg_val)&CS_ACK_IRQ_MASK_STATE_MASK) >> CS_ACK_IRQ_MASK_STATE_SHIFT) 367 #define CS_ACK_IRQ_MASK_STATE_SET(reg_val, value) \ 368 (((reg_val) & ~CS_ACK_IRQ_MASK_STATE_MASK) | \ 369 (((value) << CS_ACK_IRQ_MASK_STATE_SHIFT) & CS_ACK_IRQ_MASK_STATE_MASK)) 370 /* CS_ACK_IRQ_MASK_STATE values */ 371 #define CS_ACK_IRQ_MASK_STATE_DISABLED 0x0 372 #define CS_ACK_IRQ_MASK_STATE_ENABLED 0x7 373 /* End of CS_ACK_IRQ_MASK_STATE values */ 374 #define CS_ACK_IRQ_MASK_EXTRACT_EVENT_SHIFT 4 375 #define CS_ACK_IRQ_MASK_EXTRACT_EVENT_MASK (0x1 << CS_ACK_IRQ_MASK_EXTRACT_EVENT_SHIFT) 376 #define CS_ACK_IRQ_MASK_EXTRACT_EVENT_GET(reg_val) \ 377 (((reg_val)&CS_ACK_IRQ_MASK_EXTRACT_EVENT_MASK) >> CS_ACK_IRQ_MASK_EXTRACT_EVENT_SHIFT) 378 #define CS_ACK_IRQ_MASK_EXTRACT_EVENT_SET(reg_val, value) \ 379 (((reg_val) & ~CS_ACK_IRQ_MASK_EXTRACT_EVENT_MASK) | \ 380 (((value) << CS_ACK_IRQ_MASK_EXTRACT_EVENT_SHIFT) & CS_ACK_IRQ_MASK_EXTRACT_EVENT_MASK)) 381 #define CS_ACK_IRQ_MASK_TILER_OOM_SHIFT 26 382 #define CS_ACK_IRQ_MASK_TILER_OOM_MASK (0x1 << CS_ACK_IRQ_MASK_TILER_OOM_SHIFT) 383 #define CS_ACK_IRQ_MASK_TILER_OOM_GET(reg_val) \ 384 (((reg_val)&CS_ACK_IRQ_MASK_TILER_OOM_MASK) >> CS_ACK_IRQ_MASK_TILER_OOM_SHIFT) 385 #define CS_ACK_IRQ_MASK_TILER_OOM_SET(reg_val, value) \ 386 (((reg_val) & ~CS_ACK_IRQ_MASK_TILER_OOM_MASK) | \ 387 (((value) << CS_ACK_IRQ_MASK_TILER_OOM_SHIFT) & CS_ACK_IRQ_MASK_TILER_OOM_MASK)) 388 #define CS_ACK_IRQ_MASK_PROTM_PEND_SHIFT 27 389 #define CS_ACK_IRQ_MASK_PROTM_PEND_MASK (0x1 << CS_ACK_IRQ_MASK_PROTM_PEND_SHIFT) 390 #define CS_ACK_IRQ_MASK_PROTM_PEND_GET(reg_val) \ 391 (((reg_val)&CS_ACK_IRQ_MASK_PROTM_PEND_MASK) >> CS_ACK_IRQ_MASK_PROTM_PEND_SHIFT) 392 #define CS_ACK_IRQ_MASK_PROTM_PEND_SET(reg_val, value) \ 393 (((reg_val) & ~CS_ACK_IRQ_MASK_PROTM_PEND_MASK) | \ 394 (((value) << CS_ACK_IRQ_MASK_PROTM_PEND_SHIFT) & CS_ACK_IRQ_MASK_PROTM_PEND_MASK)) 395 #define CS_ACK_IRQ_MASK_FATAL_SHIFT 30 396 #define CS_ACK_IRQ_MASK_FATAL_MASK (0x1 << CS_ACK_IRQ_MASK_FATAL_SHIFT) 397 #define CS_ACK_IRQ_MASK_FATAL_GET(reg_val) (((reg_val)&CS_ACK_IRQ_MASK_FATAL_MASK) >> CS_ACK_IRQ_MASK_FATAL_SHIFT) 398 #define CS_ACK_IRQ_MASK_FATAL_SET(reg_val, value) \ 399 (((reg_val) & ~CS_ACK_IRQ_MASK_FATAL_MASK) | \ 400 (((value) << CS_ACK_IRQ_MASK_FATAL_SHIFT) & CS_ACK_IRQ_MASK_FATAL_MASK)) 401 #define CS_ACK_IRQ_MASK_FAULT_SHIFT 31 402 #define CS_ACK_IRQ_MASK_FAULT_MASK (0x1 << CS_ACK_IRQ_MASK_FAULT_SHIFT) 403 #define CS_ACK_IRQ_MASK_FAULT_GET(reg_val) (((reg_val)&CS_ACK_IRQ_MASK_FAULT_MASK) >> CS_ACK_IRQ_MASK_FAULT_SHIFT) 404 #define CS_ACK_IRQ_MASK_FAULT_SET(reg_val, value) \ 405 (((reg_val) & ~CS_ACK_IRQ_MASK_FAULT_MASK) | \ 406 (((value) << CS_ACK_IRQ_MASK_FAULT_SHIFT) & CS_ACK_IRQ_MASK_FAULT_MASK)) 407 408 /* CS_BASE register */ 409 #define CS_BASE_POINTER_SHIFT 0 410 #define CS_BASE_POINTER_MASK (GPU_ULL(0xFFFFFFFFFFFFFFFF) << CS_BASE_POINTER_SHIFT) 411 #define CS_BASE_POINTER_GET(reg_val) (((reg_val)&CS_BASE_POINTER_MASK) >> CS_BASE_POINTER_SHIFT) 412 #define CS_BASE_POINTER_SET(reg_val, value) \ 413 (((reg_val) & ~CS_BASE_POINTER_MASK) | (((value) << CS_BASE_POINTER_SHIFT) & CS_BASE_POINTER_MASK)) 414 415 /* CS_SIZE register */ 416 #define CS_SIZE_SIZE_SHIFT 0 417 #define CS_SIZE_SIZE_MASK (0xFFFFFFFF << CS_SIZE_SIZE_SHIFT) 418 #define CS_SIZE_SIZE_GET(reg_val) (((reg_val)&CS_SIZE_SIZE_MASK) >> CS_SIZE_SIZE_SHIFT) 419 #define CS_SIZE_SIZE_SET(reg_val, value) \ 420 (((reg_val) & ~CS_SIZE_SIZE_MASK) | (((value) << CS_SIZE_SIZE_SHIFT) & CS_SIZE_SIZE_MASK)) 421 422 /* CS_TILER_HEAP_START register */ 423 #define CS_TILER_HEAP_START_POINTER_SHIFT 0 424 #define CS_TILER_HEAP_START_POINTER_MASK \ 425 (GPU_ULL(0xFFFFFFFFFFFFFFFF) << CS_TILER_HEAP_START_POINTER_SHIFT) 426 #define CS_TILER_HEAP_START_POINTER_GET(reg_val) \ 427 (((reg_val)&CS_TILER_HEAP_START_POINTER_MASK) >> CS_TILER_HEAP_START_POINTER_SHIFT) 428 #define CS_TILER_HEAP_START_POINTER_SET(reg_val, value) \ 429 (((reg_val) & ~CS_TILER_HEAP_START_POINTER_MASK) | \ 430 (((value) << CS_TILER_HEAP_START_POINTER_SHIFT) & CS_TILER_HEAP_START_POINTER_MASK)) 431 /* HeapChunkPointer nested in CS_TILER_HEAP_START_POINTER */ 432 /* End of HeapChunkPointer nested in CS_TILER_HEAP_START_POINTER */ 433 434 /* CS_TILER_HEAP_END register */ 435 #define CS_TILER_HEAP_END_POINTER_SHIFT 0 436 #define CS_TILER_HEAP_END_POINTER_MASK \ 437 (GPU_ULL(0xFFFFFFFFFFFFFFFF) << CS_TILER_HEAP_END_POINTER_SHIFT) 438 #define CS_TILER_HEAP_END_POINTER_GET(reg_val) \ 439 (((reg_val)&CS_TILER_HEAP_END_POINTER_MASK) >> CS_TILER_HEAP_END_POINTER_SHIFT) 440 #define CS_TILER_HEAP_END_POINTER_SET(reg_val, value) \ 441 (((reg_val) & ~CS_TILER_HEAP_END_POINTER_MASK) | \ 442 (((value) << CS_TILER_HEAP_END_POINTER_SHIFT) & CS_TILER_HEAP_END_POINTER_MASK)) 443 /* HeapChunkPointer nested in CS_TILER_HEAP_END_POINTER */ 444 /* End of HeapChunkPointer nested in CS_TILER_HEAP_END_POINTER */ 445 446 /* CS_USER_INPUT register */ 447 #define CS_USER_INPUT_POINTER_SHIFT 0 448 #define CS_USER_INPUT_POINTER_MASK (GPU_ULL(0xFFFFFFFFFFFFFFFF) << CS_USER_INPUT_POINTER_SHIFT) 449 #define CS_USER_INPUT_POINTER_GET(reg_val) (((reg_val)&CS_USER_INPUT_POINTER_MASK) >> CS_USER_INPUT_POINTER_SHIFT) 450 #define CS_USER_INPUT_POINTER_SET(reg_val, value) \ 451 (((reg_val) & ~CS_USER_INPUT_POINTER_MASK) | \ 452 (((value) << CS_USER_INPUT_POINTER_SHIFT) & CS_USER_INPUT_POINTER_MASK)) 453 454 /* CS_USER_OUTPUT register */ 455 #define CS_USER_OUTPUT_POINTER_SHIFT 0 456 #define CS_USER_OUTPUT_POINTER_MASK (GPU_ULL(0xFFFFFFFFFFFFFFFF) << CS_USER_OUTPUT_POINTER_SHIFT) 457 #define CS_USER_OUTPUT_POINTER_GET(reg_val) (((reg_val)&CS_USER_OUTPUT_POINTER_MASK) >> CS_USER_OUTPUT_POINTER_SHIFT) 458 #define CS_USER_OUTPUT_POINTER_SET(reg_val, value) \ 459 (((reg_val) & ~CS_USER_OUTPUT_POINTER_MASK) | \ 460 (((value) << CS_USER_OUTPUT_POINTER_SHIFT) & CS_USER_OUTPUT_POINTER_MASK)) 461 462 /* CS_INSTR_CONFIG register */ 463 #define CS_INSTR_CONFIG_JASID_SHIFT (0) 464 #define CS_INSTR_CONFIG_JASID_MASK ((u32)0xF << CS_INSTR_CONFIG_JASID_SHIFT) 465 #define CS_INSTR_CONFIG_JASID_GET(reg_val) (((reg_val)&CS_INSTR_CONFIG_JASID_MASK) >> CS_INSTR_CONFIG_JASID_SHIFT) 466 #define CS_INSTR_CONFIG_JASID_SET(reg_val, value) \ 467 (((reg_val) & ~CS_INSTR_CONFIG_JASID_MASK) | \ 468 (((value) << CS_INSTR_CONFIG_JASID_SHIFT) & CS_INSTR_CONFIG_JASID_MASK)) 469 #define CS_INSTR_CONFIG_EVENT_SIZE_SHIFT (4) 470 #define CS_INSTR_CONFIG_EVENT_SIZE_MASK ((u32)0xF << CS_INSTR_CONFIG_EVENT_SIZE_SHIFT) 471 #define CS_INSTR_CONFIG_EVENT_SIZE_GET(reg_val) \ 472 (((reg_val)&CS_INSTR_CONFIG_EVENT_SIZE_MASK) >> CS_INSTR_CONFIG_EVENT_SIZE_SHIFT) 473 #define CS_INSTR_CONFIG_EVENT_SIZE_SET(reg_val, value) \ 474 (((reg_val) & ~CS_INSTR_CONFIG_EVENT_SIZE_MASK) | \ 475 (((value) << CS_INSTR_CONFIG_EVENT_SIZE_SHIFT) & CS_INSTR_CONFIG_EVENT_SIZE_MASK)) 476 #define CS_INSTR_CONFIG_EVENT_STATE_SHIFT (16) 477 #define CS_INSTR_CONFIG_EVENT_STATE_MASK ((u32)0xFF << CS_INSTR_CONFIG_EVENT_STATE_SHIFT) 478 #define CS_INSTR_CONFIG_EVENT_STATE_GET(reg_val) \ 479 (((reg_val)&CS_INSTR_CONFIG_EVENT_STATE_MASK) >> CS_INSTR_CONFIG_EVENT_STATE_SHIFT) 480 #define CS_INSTR_CONFIG_EVENT_STATE_SET(reg_val, value) \ 481 (((reg_val) & ~CS_INSTR_CONFIG_EVENT_STATE_MASK) | \ 482 (((value) << CS_INSTR_CONFIG_EVENT_STATE_SHIFT) & CS_INSTR_CONFIG_EVENT_STATE_MASK)) 483 484 /* CS_INSTR_BUFFER_SIZE register */ 485 #define CS_INSTR_BUFFER_SIZE_SIZE_SHIFT (0) 486 #define CS_INSTR_BUFFER_SIZE_SIZE_MASK ((u32)0xFFFFFFFF << CS_INSTR_BUFFER_SIZE_SIZE_SHIFT) 487 #define CS_INSTR_BUFFER_SIZE_SIZE_GET(reg_val) \ 488 (((reg_val)&CS_INSTR_BUFFER_SIZE_SIZE_MASK) >> CS_INSTR_BUFFER_SIZE_SIZE_SHIFT) 489 #define CS_INSTR_BUFFER_SIZE_SIZE_SET(reg_val, value) \ 490 (((reg_val) & ~CS_INSTR_BUFFER_SIZE_SIZE_MASK) | \ 491 (((value) << CS_INSTR_BUFFER_SIZE_SIZE_SHIFT) & CS_INSTR_BUFFER_SIZE_SIZE_MASK)) 492 493 /* CS_INSTR_BUFFER_BASE register */ 494 #define CS_INSTR_BUFFER_BASE_POINTER_SHIFT (0) 495 #define CS_INSTR_BUFFER_BASE_POINTER_MASK \ 496 (GPU_ULL(0xFFFFFFFFFFFFFFFF) << CS_INSTR_BUFFER_BASE_POINTER_SHIFT) 497 #define CS_INSTR_BUFFER_BASE_POINTER_GET(reg_val) \ 498 (((reg_val)&CS_INSTR_BUFFER_BASE_POINTER_MASK) >> CS_INSTR_BUFFER_BASE_POINTER_SHIFT) 499 #define CS_INSTR_BUFFER_BASE_POINTER_SET(reg_val, value) \ 500 (((reg_val) & ~CS_INSTR_BUFFER_BASE_POINTER_MASK) | \ 501 (((value) << CS_INSTR_BUFFER_BASE_POINTER_SHIFT) & CS_INSTR_BUFFER_BASE_POINTER_MASK)) 502 503 /* CS_INSTR_BUFFER_OFFSET_POINTER register */ 504 #define CS_INSTR_BUFFER_OFFSET_POINTER_POINTER_SHIFT (0) 505 #define CS_INSTR_BUFFER_OFFSET_POINTER_POINTER_MASK \ 506 ((GPU_ULL(0xFFFFFFFFFFFFFFFF)) << CS_INSTR_BUFFER_OFFSET_POINTER_POINTER_SHIFT) 507 #define CS_INSTR_BUFFER_OFFSET_POINTER_POINTER_GET(reg_val) \ 508 (((reg_val)&CS_INSTR_BUFFER_OFFSET_POINTER_POINTER_MASK) >> CS_INSTR_BUFFER_OFFSET_POINTER_POINTER_SHIFT) 509 #define CS_INSTR_BUFFER_OFFSET_POINTER_POINTER_SET(reg_val, value) \ 510 (((reg_val) & ~CS_INSTR_BUFFER_OFFSET_POINTER_POINTER_MASK) | \ 511 (((value) << CS_INSTR_BUFFER_OFFSET_POINTER_POINTER_SHIFT) & CS_INSTR_BUFFER_OFFSET_POINTER_POINTER_MASK)) 512 513 /* End of CS_KERNEL_INPUT_BLOCK register set definitions */ 514 515 /* CS_KERNEL_OUTPUT_BLOCK register set definitions */ 516 517 /* CS_ACK register */ 518 #define CS_ACK_STATE_SHIFT 0 519 #define CS_ACK_STATE_MASK (0x7 << CS_ACK_STATE_SHIFT) 520 #define CS_ACK_STATE_GET(reg_val) (((reg_val)&CS_ACK_STATE_MASK) >> CS_ACK_STATE_SHIFT) 521 #define CS_ACK_STATE_SET(reg_val, value) \ 522 (((reg_val) & ~CS_ACK_STATE_MASK) | (((value) << CS_ACK_STATE_SHIFT) & CS_ACK_STATE_MASK)) 523 /* CS_ACK_STATE values */ 524 #define CS_ACK_STATE_STOP 0x0 525 #define CS_ACK_STATE_START 0x1 526 /* End of CS_ACK_STATE values */ 527 #define CS_ACK_EXTRACT_EVENT_SHIFT 4 528 #define CS_ACK_EXTRACT_EVENT_MASK (0x1 << CS_ACK_EXTRACT_EVENT_SHIFT) 529 #define CS_ACK_EXTRACT_EVENT_GET(reg_val) (((reg_val)&CS_ACK_EXTRACT_EVENT_MASK) >> CS_ACK_EXTRACT_EVENT_SHIFT) 530 #define CS_ACK_EXTRACT_EVENT_SET(reg_val, value) \ 531 (((reg_val) & ~CS_ACK_EXTRACT_EVENT_MASK) | (((value) << CS_ACK_EXTRACT_EVENT_SHIFT) & CS_ACK_EXTRACT_EVENT_MASK)) 532 #define CS_ACK_TILER_OOM_SHIFT 26 533 #define CS_ACK_TILER_OOM_MASK (0x1 << CS_ACK_TILER_OOM_SHIFT) 534 #define CS_ACK_TILER_OOM_GET(reg_val) (((reg_val)&CS_ACK_TILER_OOM_MASK) >> CS_ACK_TILER_OOM_SHIFT) 535 #define CS_ACK_TILER_OOM_SET(reg_val, value) \ 536 (((reg_val) & ~CS_ACK_TILER_OOM_MASK) | (((value) << CS_ACK_TILER_OOM_SHIFT) & CS_ACK_TILER_OOM_MASK)) 537 #define CS_ACK_PROTM_PEND_SHIFT 27 538 #define CS_ACK_PROTM_PEND_MASK (0x1 << CS_ACK_PROTM_PEND_SHIFT) 539 #define CS_ACK_PROTM_PEND_GET(reg_val) (((reg_val)&CS_ACK_PROTM_PEND_MASK) >> CS_ACK_PROTM_PEND_SHIFT) 540 #define CS_ACK_PROTM_PEND_SET(reg_val, value) \ 541 (((reg_val) & ~CS_ACK_PROTM_PEND_MASK) | (((value) << CS_ACK_PROTM_PEND_SHIFT) & CS_ACK_PROTM_PEND_MASK)) 542 #define CS_ACK_FATAL_SHIFT 30 543 #define CS_ACK_FATAL_MASK (0x1 << CS_ACK_FATAL_SHIFT) 544 #define CS_ACK_FATAL_GET(reg_val) (((reg_val)&CS_ACK_FATAL_MASK) >> CS_ACK_FATAL_SHIFT) 545 #define CS_ACK_FATAL_SET(reg_val, value) \ 546 (((reg_val) & ~CS_ACK_FATAL_MASK) | (((value) << CS_ACK_FATAL_SHIFT) & CS_ACK_FATAL_MASK)) 547 #define CS_ACK_FAULT_SHIFT 31 548 #define CS_ACK_FAULT_MASK (0x1 << CS_ACK_FAULT_SHIFT) 549 #define CS_ACK_FAULT_GET(reg_val) (((reg_val)&CS_ACK_FAULT_MASK) >> CS_ACK_FAULT_SHIFT) 550 #define CS_ACK_FAULT_SET(reg_val, value) \ 551 (((reg_val) & ~CS_ACK_FAULT_MASK) | (((value) << CS_ACK_FAULT_SHIFT) & CS_ACK_FAULT_MASK)) 552 553 /* CS_STATUS_CMD_PTR register */ 554 #define CS_STATUS_CMD_PTR_POINTER_SHIFT 0 555 #define CS_STATUS_CMD_PTR_POINTER_MASK \ 556 (GPU_ULL(0xFFFFFFFFFFFFFFFF) << CS_STATUS_CMD_PTR_POINTER_SHIFT) 557 #define CS_STATUS_CMD_PTR_POINTER_GET(reg_val) \ 558 (((reg_val)&CS_STATUS_CMD_PTR_POINTER_MASK) >> CS_STATUS_CMD_PTR_POINTER_SHIFT) 559 #define CS_STATUS_CMD_PTR_POINTER_SET(reg_val, value) \ 560 (((reg_val) & ~CS_STATUS_CMD_PTR_POINTER_MASK) | \ 561 (((value) << CS_STATUS_CMD_PTR_POINTER_SHIFT) & CS_STATUS_CMD_PTR_POINTER_MASK)) 562 563 /* CS_STATUS_WAIT register */ 564 #define CS_STATUS_WAIT_SB_MASK_SHIFT 0 565 #define CS_STATUS_WAIT_SB_MASK_MASK (0xFFFF << CS_STATUS_WAIT_SB_MASK_SHIFT) 566 #define CS_STATUS_WAIT_SB_MASK_GET(reg_val) (((reg_val)&CS_STATUS_WAIT_SB_MASK_MASK) >> CS_STATUS_WAIT_SB_MASK_SHIFT) 567 #define CS_STATUS_WAIT_SB_MASK_SET(reg_val, value) \ 568 (((reg_val) & ~CS_STATUS_WAIT_SB_MASK_MASK) | \ 569 (((value) << CS_STATUS_WAIT_SB_MASK_SHIFT) & CS_STATUS_WAIT_SB_MASK_MASK)) 570 #define CS_STATUS_WAIT_SB_SOURCE_SHIFT 16 571 #define CS_STATUS_WAIT_SB_SOURCE_MASK (0xF << CS_STATUS_WAIT_SB_SOURCE_SHIFT) 572 #define CS_STATUS_WAIT_SB_SOURCE_GET(reg_val) \ 573 (((reg_val)&CS_STATUS_WAIT_SB_SOURCE_MASK) >> CS_STATUS_WAIT_SB_SOURCE_SHIFT) 574 #define CS_STATUS_WAIT_SB_SOURCE_SET(reg_val, value) \ 575 (((reg_val) & ~CS_STATUS_WAIT_SB_SOURCE_MASK) | \ 576 (((value) << CS_STATUS_WAIT_SB_SOURCE_SHIFT) & CS_STATUS_WAIT_SB_SOURCE_MASK)) 577 #define CS_STATUS_WAIT_SYNC_WAIT_CONDITION_SHIFT 24 578 #define CS_STATUS_WAIT_SYNC_WAIT_CONDITION_MASK (0xF << CS_STATUS_WAIT_SYNC_WAIT_CONDITION_SHIFT) 579 #define CS_STATUS_WAIT_SYNC_WAIT_CONDITION_GET(reg_val) \ 580 (((reg_val)&CS_STATUS_WAIT_SYNC_WAIT_CONDITION_MASK) >> CS_STATUS_WAIT_SYNC_WAIT_CONDITION_SHIFT) 581 #define CS_STATUS_WAIT_SYNC_WAIT_CONDITION_SET(reg_val, value) \ 582 (((reg_val) & ~CS_STATUS_WAIT_SYNC_WAIT_CONDITION_MASK) | \ 583 (((value) << CS_STATUS_WAIT_SYNC_WAIT_CONDITION_SHIFT) & CS_STATUS_WAIT_SYNC_WAIT_CONDITION_MASK)) 584 /* CS_STATUS_WAIT_SYNC_WAIT_CONDITION values */ 585 #define CS_STATUS_WAIT_SYNC_WAIT_CONDITION_LE 0x0 586 #define CS_STATUS_WAIT_SYNC_WAIT_CONDITION_GT 0x1 587 #define CS_STATUS_WAIT_SYNC_WAIT_CONDITION_GE 0x5 588 /* End of CS_STATUS_WAIT_SYNC_WAIT_CONDITION values */ 589 #define CS_STATUS_WAIT_PROGRESS_WAIT_SHIFT 28 590 #define CS_STATUS_WAIT_PROGRESS_WAIT_MASK (0x1 << CS_STATUS_WAIT_PROGRESS_WAIT_SHIFT) 591 #define CS_STATUS_WAIT_PROGRESS_WAIT_GET(reg_val) \ 592 (((reg_val)&CS_STATUS_WAIT_PROGRESS_WAIT_MASK) >> CS_STATUS_WAIT_PROGRESS_WAIT_SHIFT) 593 #define CS_STATUS_WAIT_PROGRESS_WAIT_SET(reg_val, value) \ 594 (((reg_val) & ~CS_STATUS_WAIT_PROGRESS_WAIT_MASK) | \ 595 (((value) << CS_STATUS_WAIT_PROGRESS_WAIT_SHIFT) & CS_STATUS_WAIT_PROGRESS_WAIT_MASK)) 596 #define CS_STATUS_WAIT_PROTM_PEND_SHIFT 29 597 #define CS_STATUS_WAIT_PROTM_PEND_MASK (0x1 << CS_STATUS_WAIT_PROTM_PEND_SHIFT) 598 #define CS_STATUS_WAIT_PROTM_PEND_GET(reg_val) \ 599 (((reg_val)&CS_STATUS_WAIT_PROTM_PEND_MASK) >> CS_STATUS_WAIT_PROTM_PEND_SHIFT) 600 #define CS_STATUS_WAIT_PROTM_PEND_SET(reg_val, value) \ 601 (((reg_val) & ~CS_STATUS_WAIT_PROTM_PEND_MASK) | \ 602 (((value) << CS_STATUS_WAIT_PROTM_PEND_SHIFT) & CS_STATUS_WAIT_PROTM_PEND_MASK)) 603 #define CS_STATUS_WAIT_SYNC_WAIT_SIZE_SHIFT 30 604 #define CS_STATUS_WAIT_SYNC_WAIT_SIZE_MASK (0x1 << CS_STATUS_WAIT_SYNC_WAIT_SIZE_SHIFT) 605 #define CS_STATUS_WAIT_SYNC_WAIT_SIZE_GET(reg_val) \ 606 (((reg_val)&CS_STATUS_WAIT_SYNC_WAIT_SIZE_MASK) >> CS_STATUS_WAIT_SYNC_WAIT_SIZE_SHIFT) 607 #define CS_STATUS_WAIT_SYNC_WAIT_SIZE_SET(reg_val, value) \ 608 (((reg_val) & ~CS_STATUS_WAIT_SYNC_WAIT_SIZE_MASK) | \ 609 (((value) << CS_STATUS_WAIT_SYNC_WAIT_SIZE_SHIFT) & CS_STATUS_WAIT_SYNC_WAIT_SIZE_MASK)) 610 #define CS_STATUS_WAIT_SYNC_WAIT_SHIFT 31 611 #define CS_STATUS_WAIT_SYNC_WAIT_MASK (0x1 << CS_STATUS_WAIT_SYNC_WAIT_SHIFT) 612 #define CS_STATUS_WAIT_SYNC_WAIT_GET(reg_val) \ 613 (((reg_val)&CS_STATUS_WAIT_SYNC_WAIT_MASK) >> CS_STATUS_WAIT_SYNC_WAIT_SHIFT) 614 #define CS_STATUS_WAIT_SYNC_WAIT_SET(reg_val, value) \ 615 (((reg_val) & ~CS_STATUS_WAIT_SYNC_WAIT_MASK) | \ 616 (((value) << CS_STATUS_WAIT_SYNC_WAIT_SHIFT) & CS_STATUS_WAIT_SYNC_WAIT_MASK)) 617 618 /* CS_STATUS_REQ_RESOURCE register */ 619 #define CS_STATUS_REQ_RESOURCE_COMPUTE_RESOURCES_SHIFT 0 620 #define CS_STATUS_REQ_RESOURCE_COMPUTE_RESOURCES_MASK (0x1 << CS_STATUS_REQ_RESOURCE_COMPUTE_RESOURCES_SHIFT) 621 #define CS_STATUS_REQ_RESOURCE_COMPUTE_RESOURCES_GET(reg_val) \ 622 (((reg_val)&CS_STATUS_REQ_RESOURCE_COMPUTE_RESOURCES_MASK) >> CS_STATUS_REQ_RESOURCE_COMPUTE_RESOURCES_SHIFT) 623 #define CS_STATUS_REQ_RESOURCE_COMPUTE_RESOURCES_SET(reg_val, value) \ 624 (((reg_val) & ~CS_STATUS_REQ_RESOURCE_COMPUTE_RESOURCES_MASK) | \ 625 (((value) << CS_STATUS_REQ_RESOURCE_COMPUTE_RESOURCES_SHIFT) & CS_STATUS_REQ_RESOURCE_COMPUTE_RESOURCES_MASK)) 626 #define CS_STATUS_REQ_RESOURCE_FRAGMENT_RESOURCES_SHIFT 1 627 #define CS_STATUS_REQ_RESOURCE_FRAGMENT_RESOURCES_MASK (0x1 << CS_STATUS_REQ_RESOURCE_FRAGMENT_RESOURCES_SHIFT) 628 #define CS_STATUS_REQ_RESOURCE_FRAGMENT_RESOURCES_GET(reg_val) \ 629 (((reg_val)&CS_STATUS_REQ_RESOURCE_FRAGMENT_RESOURCES_MASK) >> CS_STATUS_REQ_RESOURCE_FRAGMENT_RESOURCES_SHIFT) 630 #define CS_STATUS_REQ_RESOURCE_FRAGMENT_RESOURCES_SET(reg_val, value) \ 631 (((reg_val) & ~CS_STATUS_REQ_RESOURCE_FRAGMENT_RESOURCES_MASK) | \ 632 (((value) << CS_STATUS_REQ_RESOURCE_FRAGMENT_RESOURCES_SHIFT) & CS_STATUS_REQ_RESOURCE_FRAGMENT_RESOURCES_MASK)) 633 #define CS_STATUS_REQ_RESOURCE_TILER_RESOURCES_SHIFT 2 634 #define CS_STATUS_REQ_RESOURCE_TILER_RESOURCES_MASK (0x1 << CS_STATUS_REQ_RESOURCE_TILER_RESOURCES_SHIFT) 635 #define CS_STATUS_REQ_RESOURCE_TILER_RESOURCES_GET(reg_val) \ 636 (((reg_val)&CS_STATUS_REQ_RESOURCE_TILER_RESOURCES_MASK) >> CS_STATUS_REQ_RESOURCE_TILER_RESOURCES_SHIFT) 637 #define CS_STATUS_REQ_RESOURCE_TILER_RESOURCES_SET(reg_val, value) \ 638 (((reg_val) & ~CS_STATUS_REQ_RESOURCE_TILER_RESOURCES_MASK) | \ 639 (((value) << CS_STATUS_REQ_RESOURCE_TILER_RESOURCES_SHIFT) & CS_STATUS_REQ_RESOURCE_TILER_RESOURCES_MASK)) 640 #define CS_STATUS_REQ_RESOURCE_IDVS_RESOURCES_SHIFT 3 641 #define CS_STATUS_REQ_RESOURCE_IDVS_RESOURCES_MASK (0x1 << CS_STATUS_REQ_RESOURCE_IDVS_RESOURCES_SHIFT) 642 #define CS_STATUS_REQ_RESOURCE_IDVS_RESOURCES_GET(reg_val) \ 643 (((reg_val)&CS_STATUS_REQ_RESOURCE_IDVS_RESOURCES_MASK) >> CS_STATUS_REQ_RESOURCE_IDVS_RESOURCES_SHIFT) 644 #define CS_STATUS_REQ_RESOURCE_IDVS_RESOURCES_SET(reg_val, value) \ 645 (((reg_val) & ~CS_STATUS_REQ_RESOURCE_IDVS_RESOURCES_MASK) | \ 646 (((value) << CS_STATUS_REQ_RESOURCE_IDVS_RESOURCES_SHIFT) & CS_STATUS_REQ_RESOURCE_IDVS_RESOURCES_MASK)) 647 648 /* CS_STATUS_WAIT_SYNC_POINTER register */ 649 #define CS_STATUS_WAIT_SYNC_POINTER_POINTER_SHIFT 0 650 #define CS_STATUS_WAIT_SYNC_POINTER_POINTER_MASK \ 651 (GPU_ULL(0xFFFFFFFFFFFFFFFF) << CS_STATUS_WAIT_SYNC_POINTER_POINTER_SHIFT) 652 #define CS_STATUS_WAIT_SYNC_POINTER_POINTER_GET(reg_val) \ 653 (((reg_val)&CS_STATUS_WAIT_SYNC_POINTER_POINTER_MASK) >> CS_STATUS_WAIT_SYNC_POINTER_POINTER_SHIFT) 654 #define CS_STATUS_WAIT_SYNC_POINTER_POINTER_SET(reg_val, value) \ 655 (((reg_val) & ~CS_STATUS_WAIT_SYNC_POINTER_POINTER_MASK) | \ 656 (((value) << CS_STATUS_WAIT_SYNC_POINTER_POINTER_SHIFT) & CS_STATUS_WAIT_SYNC_POINTER_POINTER_MASK)) 657 658 /* CS_STATUS_WAIT_SYNC_VALUE register */ 659 #define CS_STATUS_WAIT_SYNC_VALUE_VALUE_SHIFT 0 660 #define CS_STATUS_WAIT_SYNC_VALUE_VALUE_MASK (0xFFFFFFFF << CS_STATUS_WAIT_SYNC_VALUE_VALUE_SHIFT) 661 #define CS_STATUS_WAIT_SYNC_VALUE_VALUE_GET(reg_val) \ 662 (((reg_val)&CS_STATUS_WAIT_SYNC_VALUE_VALUE_MASK) >> CS_STATUS_WAIT_SYNC_VALUE_VALUE_SHIFT) 663 #define CS_STATUS_WAIT_SYNC_VALUE_VALUE_SET(reg_val, value) \ 664 (((reg_val) & ~CS_STATUS_WAIT_SYNC_VALUE_VALUE_MASK) | \ 665 (((value) << CS_STATUS_WAIT_SYNC_VALUE_VALUE_SHIFT) & CS_STATUS_WAIT_SYNC_VALUE_VALUE_MASK)) 666 667 /* CS_STATUS_SCOREBOARDS register */ 668 #define CS_STATUS_SCOREBOARDS_NONZERO_SHIFT (0) 669 #define CS_STATUS_SCOREBOARDS_NONZERO_MASK \ 670 ((0xFFFF) << CS_STATUS_SCOREBOARDS_NONZERO_SHIFT) 671 #define CS_STATUS_SCOREBOARDS_NONZERO_GET(reg_val) \ 672 (((reg_val)&CS_STATUS_SCOREBOARDS_NONZERO_MASK) >> \ 673 CS_STATUS_SCOREBOARDS_NONZERO_SHIFT) 674 #define CS_STATUS_SCOREBOARDS_NONZERO_SET(reg_val, value) \ 675 (((reg_val) & ~CS_STATUS_SCOREBOARDS_NONZERO_MASK) | \ 676 (((value) << CS_STATUS_SCOREBOARDS_NONZERO_SHIFT) & \ 677 CS_STATUS_SCOREBOARDS_NONZERO_MASK)) 678 679 /* CS_STATUS_BLOCKED_REASON register */ 680 #define CS_STATUS_BLOCKED_REASON_REASON_SHIFT (0) 681 #define CS_STATUS_BLOCKED_REASON_REASON_MASK \ 682 ((0xF) << CS_STATUS_BLOCKED_REASON_REASON_SHIFT) 683 #define CS_STATUS_BLOCKED_REASON_REASON_GET(reg_val) \ 684 (((reg_val)&CS_STATUS_BLOCKED_REASON_REASON_MASK) >> \ 685 CS_STATUS_BLOCKED_REASON_REASON_SHIFT) 686 #define CS_STATUS_BLOCKED_REASON_REASON_SET(reg_val, value) \ 687 (((reg_val) & ~CS_STATUS_BLOCKED_REASON_REASON_MASK) | \ 688 (((value) << CS_STATUS_BLOCKED_REASON_REASON_SHIFT) & \ 689 CS_STATUS_BLOCKED_REASON_REASON_MASK)) 690 /* CS_STATUS_BLOCKED_REASON_reason values */ 691 #define CS_STATUS_BLOCKED_REASON_REASON_UNBLOCKED 0x0 692 #define CS_STATUS_BLOCKED_REASON_REASON_WAIT 0x1 693 #define CS_STATUS_BLOCKED_REASON_REASON_PROGRESS_WAIT 0x2 694 #define CS_STATUS_BLOCKED_REASON_REASON_SYNC_WAIT 0x3 695 #define CS_STATUS_BLOCKED_REASON_REASON_DEFERRED 0x4 696 #define CS_STATUS_BLOCKED_REASON_REASON_RESOURCE 0x5 697 #define CS_STATUS_BLOCKED_REASON_REASON_FLUSH 0x6 698 /* End of CS_STATUS_BLOCKED_REASON_reason values */ 699 700 /* CS_FAULT register */ 701 #define CS_FAULT_EXCEPTION_TYPE_SHIFT 0 702 #define CS_FAULT_EXCEPTION_TYPE_MASK (0xFF << CS_FAULT_EXCEPTION_TYPE_SHIFT) 703 #define CS_FAULT_EXCEPTION_TYPE_GET(reg_val) (((reg_val)&CS_FAULT_EXCEPTION_TYPE_MASK) >> CS_FAULT_EXCEPTION_TYPE_SHIFT) 704 #define CS_FAULT_EXCEPTION_TYPE_SET(reg_val, value) \ 705 (((reg_val) & ~CS_FAULT_EXCEPTION_TYPE_MASK) | \ 706 (((value) << CS_FAULT_EXCEPTION_TYPE_SHIFT) & CS_FAULT_EXCEPTION_TYPE_MASK)) 707 /* CS_FAULT_EXCEPTION_TYPE values */ 708 #define CS_FAULT_EXCEPTION_TYPE_KABOOM 0x05 709 #define CS_FAULT_EXCEPTION_TYPE_CS_RESOURCE_TERMINATED 0x0F 710 #define CS_FAULT_EXCEPTION_TYPE_CS_BUS_FAULT 0x48 711 #define CS_FAULT_EXCEPTION_TYPE_CS_INHERIT_FAULT 0x4B 712 #define CS_FAULT_EXCEPTION_TYPE_INSTR_INVALID_PC 0x50 713 #define CS_FAULT_EXCEPTION_TYPE_INSTR_INVALID_ENC 0x51 714 #define CS_FAULT_EXCEPTION_TYPE_INSTR_BARRIER_FAULT 0x55 715 #define CS_FAULT_EXCEPTION_TYPE_DATA_INVALID_FAULT 0x58 716 #define CS_FAULT_EXCEPTION_TYPE_TILE_RANGE_FAULT 0x59 717 #define CS_FAULT_EXCEPTION_TYPE_ADDR_RANGE_FAULT 0x5A 718 #define CS_FAULT_EXCEPTION_TYPE_IMPRECISE_FAULT 0x5B 719 #define CS_FAULT_EXCEPTION_TYPE_RESOURCE_EVICTION_TIMEOUT 0x69 720 #define CS_FAULT_EXCEPTION_TYPE_TRANSLATION_FAULT_L0 0xC0 721 #define CS_FAULT_EXCEPTION_TYPE_TRANSLATION_FAULT_L1 0xC1 722 #define CS_FAULT_EXCEPTION_TYPE_TRANSLATION_FAULT_L2 0xC2 723 #define CS_FAULT_EXCEPTION_TYPE_TRANSLATION_FAULT_L3 0xC3 724 #define CS_FAULT_EXCEPTION_TYPE_TRANSLATION_FAULT_L4 0xC4 725 #define CS_FAULT_EXCEPTION_TYPE_PERMISSION_FAULT_0 0xC8 726 #define CS_FAULT_EXCEPTION_TYPE_PERMISSION_FAULT_1 0xC9 727 #define CS_FAULT_EXCEPTION_TYPE_PERMISSION_FAULT_2 0xCA 728 #define CS_FAULT_EXCEPTION_TYPE_PERMISSION_FAULT_3 0xCB 729 #define CS_FAULT_EXCEPTION_TYPE_ACCESS_FLAG_1 0xD9 730 #define CS_FAULT_EXCEPTION_TYPE_ACCESS_FLAG_2 0xDA 731 #define CS_FAULT_EXCEPTION_TYPE_ACCESS_FLAG_3 0xDB 732 #define CS_FAULT_EXCEPTION_TYPE_ADDRESS_SIZE_FAULT_IN 0xE0 733 #define CS_FAULT_EXCEPTION_TYPE_ADDRESS_SIZE_FAULT_OUT_0 0xE4 734 #define CS_FAULT_EXCEPTION_TYPE_ADDRESS_SIZE_FAULT_OUT_1 0xE5 735 #define CS_FAULT_EXCEPTION_TYPE_ADDRESS_SIZE_FAULT_OUT_2 0xE6 736 #define CS_FAULT_EXCEPTION_TYPE_ADDRESS_SIZE_FAULT_OUT_3 0xE7 737 #define CS_FAULT_EXCEPTION_TYPE_MEMORY_ATTRIBUTE_FAULT_0 0xE8 738 #define CS_FAULT_EXCEPTION_TYPE_MEMORY_ATTRIBUTE_FAULT_1 0xE9 739 #define CS_FAULT_EXCEPTION_TYPE_MEMORY_ATTRIBUTE_FAULT_2 0xEA 740 #define CS_FAULT_EXCEPTION_TYPE_MEMORY_ATTRIBUTE_FAULT_3 0xEB 741 /* End of CS_FAULT_EXCEPTION_TYPE values */ 742 #define CS_FAULT_EXCEPTION_DATA_SHIFT 8 743 #define CS_FAULT_EXCEPTION_DATA_MASK (0xFFFFFF << CS_FAULT_EXCEPTION_DATA_SHIFT) 744 #define CS_FAULT_EXCEPTION_DATA_GET(reg_val) (((reg_val)&CS_FAULT_EXCEPTION_DATA_MASK) >> CS_FAULT_EXCEPTION_DATA_SHIFT) 745 #define CS_FAULT_EXCEPTION_DATA_SET(reg_val, value) \ 746 (((reg_val) & ~CS_FAULT_EXCEPTION_DATA_MASK) | \ 747 (((value) << CS_FAULT_EXCEPTION_DATA_SHIFT) & CS_FAULT_EXCEPTION_DATA_MASK)) 748 749 /* CS_FATAL register */ 750 #define CS_FATAL_EXCEPTION_TYPE_SHIFT 0 751 #define CS_FATAL_EXCEPTION_TYPE_MASK (0xFF << CS_FATAL_EXCEPTION_TYPE_SHIFT) 752 #define CS_FATAL_EXCEPTION_TYPE_GET(reg_val) (((reg_val)&CS_FATAL_EXCEPTION_TYPE_MASK) >> CS_FATAL_EXCEPTION_TYPE_SHIFT) 753 #define CS_FATAL_EXCEPTION_TYPE_SET(reg_val, value) \ 754 (((reg_val) & ~CS_FATAL_EXCEPTION_TYPE_MASK) | \ 755 (((value) << CS_FATAL_EXCEPTION_TYPE_SHIFT) & CS_FATAL_EXCEPTION_TYPE_MASK)) 756 /* CS_FATAL_EXCEPTION_TYPE values */ 757 #define CS_FATAL_EXCEPTION_TYPE_CS_CONFIG_FAULT 0x40 758 #define CS_FATAL_EXCEPTION_TYPE_CS_UNRECOVERABLE 0x41 759 #define CS_FATAL_EXCEPTION_TYPE_CS_ENDPOINT_FAULT 0x44 760 #define CS_FATAL_EXCEPTION_TYPE_CS_BUS_FAULT 0x48 761 #define CS_FATAL_EXCEPTION_TYPE_CS_INVALID_INSTRUCTION 0x49 762 #define CS_FATAL_EXCEPTION_TYPE_CS_CALL_STACK_OVERFLOW 0x4A 763 #define CS_FATAL_EXCEPTION_TYPE_FIRMWARE_INTERNAL_ERROR 0x68 764 /* End of CS_FATAL_EXCEPTION_TYPE values */ 765 #define CS_FATAL_EXCEPTION_DATA_SHIFT 8 766 #define CS_FATAL_EXCEPTION_DATA_MASK (0xFFFFFF << CS_FATAL_EXCEPTION_DATA_SHIFT) 767 #define CS_FATAL_EXCEPTION_DATA_GET(reg_val) (((reg_val)&CS_FATAL_EXCEPTION_DATA_MASK) >> CS_FATAL_EXCEPTION_DATA_SHIFT) 768 #define CS_FATAL_EXCEPTION_DATA_SET(reg_val, value) \ 769 (((reg_val) & ~CS_FATAL_EXCEPTION_DATA_MASK) | \ 770 (((value) << CS_FATAL_EXCEPTION_DATA_SHIFT) & CS_FATAL_EXCEPTION_DATA_MASK)) 771 772 /* CS_FAULT_INFO register */ 773 #define CS_FAULT_INFO_EXCEPTION_DATA_SHIFT 0 774 #define CS_FAULT_INFO_EXCEPTION_DATA_MASK \ 775 (GPU_ULL(0xFFFFFFFFFFFFFFFF) << CS_FAULT_INFO_EXCEPTION_DATA_SHIFT) 776 #define CS_FAULT_INFO_EXCEPTION_DATA_GET(reg_val) \ 777 (((reg_val)&CS_FAULT_INFO_EXCEPTION_DATA_MASK) >> CS_FAULT_INFO_EXCEPTION_DATA_SHIFT) 778 #define CS_FAULT_INFO_EXCEPTION_DATA_SET(reg_val, value) \ 779 (((reg_val) & ~CS_FAULT_INFO_EXCEPTION_DATA_MASK) | \ 780 (((value) << CS_FAULT_INFO_EXCEPTION_DATA_SHIFT) & CS_FAULT_INFO_EXCEPTION_DATA_MASK)) 781 782 /* CS_FATAL_INFO register */ 783 #define CS_FATAL_INFO_EXCEPTION_DATA_SHIFT 0 784 #define CS_FATAL_INFO_EXCEPTION_DATA_MASK \ 785 (GPU_ULL(0xFFFFFFFFFFFFFFFF) << CS_FATAL_INFO_EXCEPTION_DATA_SHIFT) 786 #define CS_FATAL_INFO_EXCEPTION_DATA_GET(reg_val) \ 787 (((reg_val)&CS_FATAL_INFO_EXCEPTION_DATA_MASK) >> CS_FATAL_INFO_EXCEPTION_DATA_SHIFT) 788 #define CS_FATAL_INFO_EXCEPTION_DATA_SET(reg_val, value) \ 789 (((reg_val) & ~CS_FATAL_INFO_EXCEPTION_DATA_MASK) | \ 790 (((value) << CS_FATAL_INFO_EXCEPTION_DATA_SHIFT) & CS_FATAL_INFO_EXCEPTION_DATA_MASK)) 791 792 /* CS_HEAP_VT_START register */ 793 #define CS_HEAP_VT_START_VALUE_SHIFT 0 794 #define CS_HEAP_VT_START_VALUE_MASK (0xFFFFFFFF << CS_HEAP_VT_START_VALUE_SHIFT) 795 #define CS_HEAP_VT_START_VALUE_GET(reg_val) (((reg_val)&CS_HEAP_VT_START_VALUE_MASK) >> CS_HEAP_VT_START_VALUE_SHIFT) 796 #define CS_HEAP_VT_START_VALUE_SET(reg_val, value) \ 797 (((reg_val) & ~CS_HEAP_VT_START_VALUE_MASK) | \ 798 (((value) << CS_HEAP_VT_START_VALUE_SHIFT) & CS_HEAP_VT_START_VALUE_MASK)) 799 800 /* CS_HEAP_VT_END register */ 801 #define CS_HEAP_VT_END_VALUE_SHIFT 0 802 #define CS_HEAP_VT_END_VALUE_MASK (0xFFFFFFFF << CS_HEAP_VT_END_VALUE_SHIFT) 803 #define CS_HEAP_VT_END_VALUE_GET(reg_val) (((reg_val)&CS_HEAP_VT_END_VALUE_MASK) >> CS_HEAP_VT_END_VALUE_SHIFT) 804 #define CS_HEAP_VT_END_VALUE_SET(reg_val, value) \ 805 (((reg_val) & ~CS_HEAP_VT_END_VALUE_MASK) | (((value) << CS_HEAP_VT_END_VALUE_SHIFT) & CS_HEAP_VT_END_VALUE_MASK)) 806 807 /* CS_HEAP_FRAG_END register */ 808 #define CS_HEAP_FRAG_END_VALUE_SHIFT 0 809 #define CS_HEAP_FRAG_END_VALUE_MASK (0xFFFFFFFF << CS_HEAP_FRAG_END_VALUE_SHIFT) 810 #define CS_HEAP_FRAG_END_VALUE_GET(reg_val) (((reg_val)&CS_HEAP_FRAG_END_VALUE_MASK) >> CS_HEAP_FRAG_END_VALUE_SHIFT) 811 #define CS_HEAP_FRAG_END_VALUE_SET(reg_val, value) \ 812 (((reg_val) & ~CS_HEAP_FRAG_END_VALUE_MASK) | \ 813 (((value) << CS_HEAP_FRAG_END_VALUE_SHIFT) & CS_HEAP_FRAG_END_VALUE_MASK)) 814 815 /* CS_HEAP_ADDRESS register */ 816 #define CS_HEAP_ADDRESS_POINTER_SHIFT 0 817 #define CS_HEAP_ADDRESS_POINTER_MASK (GPU_ULL(0xFFFFFFFFFFFFFFFF) << CS_HEAP_ADDRESS_POINTER_SHIFT) 818 #define CS_HEAP_ADDRESS_POINTER_GET(reg_val) (((reg_val)&CS_HEAP_ADDRESS_POINTER_MASK) >> CS_HEAP_ADDRESS_POINTER_SHIFT) 819 #define CS_HEAP_ADDRESS_POINTER_SET(reg_val, value) \ 820 (((reg_val) & ~CS_HEAP_ADDRESS_POINTER_MASK) | \ 821 (((value) << CS_HEAP_ADDRESS_POINTER_SHIFT) & CS_HEAP_ADDRESS_POINTER_MASK)) 822 /* End of CS_KERNEL_OUTPUT_BLOCK register set definitions */ 823 824 /* CS_USER_INPUT_BLOCK register set definitions */ 825 826 /* CS_INSERT register */ 827 #define CS_INSERT_VALUE_SHIFT 0 828 #define CS_INSERT_VALUE_MASK (GPU_ULL(0xFFFFFFFFFFFFFFFF) << CS_INSERT_VALUE_SHIFT) 829 #define CS_INSERT_VALUE_GET(reg_val) (((reg_val)&CS_INSERT_VALUE_MASK) >> CS_INSERT_VALUE_SHIFT) 830 #define CS_INSERT_VALUE_SET(reg_val, value) \ 831 (((reg_val) & ~CS_INSERT_VALUE_MASK) | (((value) << CS_INSERT_VALUE_SHIFT) & CS_INSERT_VALUE_MASK)) 832 833 /* CS_EXTRACT_INIT register */ 834 #define CS_EXTRACT_INIT_VALUE_SHIFT 0 835 #define CS_EXTRACT_INIT_VALUE_MASK (GPU_ULL(0xFFFFFFFFFFFFFFFF) << CS_EXTRACT_INIT_VALUE_SHIFT) 836 #define CS_EXTRACT_INIT_VALUE_GET(reg_val) (((reg_val)&CS_EXTRACT_INIT_VALUE_MASK) >> CS_EXTRACT_INIT_VALUE_SHIFT) 837 #define CS_EXTRACT_INIT_VALUE_SET(reg_val, value) \ 838 (((reg_val) & ~CS_EXTRACT_INIT_VALUE_MASK) | \ 839 (((value) << CS_EXTRACT_INIT_VALUE_SHIFT) & CS_EXTRACT_INIT_VALUE_MASK)) 840 /* End of CS_USER_INPUT_BLOCK register set definitions */ 841 842 /* CS_USER_OUTPUT_BLOCK register set definitions */ 843 844 /* CS_EXTRACT register */ 845 #define CS_EXTRACT_VALUE_SHIFT 0 846 #define CS_EXTRACT_VALUE_MASK (GPU_ULL(0xFFFFFFFFFFFFFFFF) << CS_EXTRACT_VALUE_SHIFT) 847 #define CS_EXTRACT_VALUE_GET(reg_val) (((reg_val)&CS_EXTRACT_VALUE_MASK) >> CS_EXTRACT_VALUE_SHIFT) 848 #define CS_EXTRACT_VALUE_SET(reg_val, value) \ 849 (((reg_val) & ~CS_EXTRACT_VALUE_MASK) | (((value) << CS_EXTRACT_VALUE_SHIFT) & CS_EXTRACT_VALUE_MASK)) 850 851 /* CS_ACTIVE register */ 852 #define CS_ACTIVE_HW_ACTIVE_SHIFT 0 853 #define CS_ACTIVE_HW_ACTIVE_MASK (0x1 << CS_ACTIVE_HW_ACTIVE_SHIFT) 854 #define CS_ACTIVE_HW_ACTIVE_GET(reg_val) (((reg_val)&CS_ACTIVE_HW_ACTIVE_MASK) >> CS_ACTIVE_HW_ACTIVE_SHIFT) 855 #define CS_ACTIVE_HW_ACTIVE_SET(reg_val, value) \ 856 (((reg_val) & ~CS_ACTIVE_HW_ACTIVE_MASK) | (((value) << CS_ACTIVE_HW_ACTIVE_SHIFT) & CS_ACTIVE_HW_ACTIVE_MASK)) 857 /* End of CS_USER_OUTPUT_BLOCK register set definitions */ 858 859 /* CSG_INPUT_BLOCK register set definitions */ 860 861 /* CSG_REQ register */ 862 #define CSG_REQ_STATE_SHIFT 0 863 #define CSG_REQ_STATE_MASK (0x7 << CSG_REQ_STATE_SHIFT) 864 #define CSG_REQ_STATE_GET(reg_val) (((reg_val)&CSG_REQ_STATE_MASK) >> CSG_REQ_STATE_SHIFT) 865 #define CSG_REQ_STATE_SET(reg_val, value) \ 866 (((reg_val) & ~CSG_REQ_STATE_MASK) | (((value) << CSG_REQ_STATE_SHIFT) & CSG_REQ_STATE_MASK)) 867 /* CSG_REQ_STATE values */ 868 #define CSG_REQ_STATE_TERMINATE 0x0 869 #define CSG_REQ_STATE_START 0x1 870 #define CSG_REQ_STATE_SUSPEND 0x2 871 #define CSG_REQ_STATE_RESUME 0x3 872 /* End of CSG_REQ_STATE values */ 873 #define CSG_REQ_EP_CFG_SHIFT 4 874 #define CSG_REQ_EP_CFG_MASK (0x1 << CSG_REQ_EP_CFG_SHIFT) 875 #define CSG_REQ_EP_CFG_GET(reg_val) (((reg_val)&CSG_REQ_EP_CFG_MASK) >> CSG_REQ_EP_CFG_SHIFT) 876 #define CSG_REQ_EP_CFG_SET(reg_val, value) \ 877 (((reg_val) & ~CSG_REQ_EP_CFG_MASK) | (((value) << CSG_REQ_EP_CFG_SHIFT) & CSG_REQ_EP_CFG_MASK)) 878 #define CSG_REQ_STATUS_UPDATE_SHIFT 5 879 #define CSG_REQ_STATUS_UPDATE_MASK (0x1 << CSG_REQ_STATUS_UPDATE_SHIFT) 880 #define CSG_REQ_STATUS_UPDATE_GET(reg_val) (((reg_val)&CSG_REQ_STATUS_UPDATE_MASK) >> CSG_REQ_STATUS_UPDATE_SHIFT) 881 #define CSG_REQ_STATUS_UPDATE_SET(reg_val, value) \ 882 (((reg_val) & ~CSG_REQ_STATUS_UPDATE_MASK) | \ 883 (((value) << CSG_REQ_STATUS_UPDATE_SHIFT) & CSG_REQ_STATUS_UPDATE_MASK)) 884 #define CSG_REQ_SYNC_UPDATE_SHIFT 28 885 #define CSG_REQ_SYNC_UPDATE_MASK (0x1 << CSG_REQ_SYNC_UPDATE_SHIFT) 886 #define CSG_REQ_SYNC_UPDATE_GET(reg_val) (((reg_val)&CSG_REQ_SYNC_UPDATE_MASK) >> CSG_REQ_SYNC_UPDATE_SHIFT) 887 #define CSG_REQ_SYNC_UPDATE_SET(reg_val, value) \ 888 (((reg_val) & ~CSG_REQ_SYNC_UPDATE_MASK) | (((value) << CSG_REQ_SYNC_UPDATE_SHIFT) & CSG_REQ_SYNC_UPDATE_MASK)) 889 #define CSG_REQ_IDLE_SHIFT 29 890 #define CSG_REQ_IDLE_MASK (0x1 << CSG_REQ_IDLE_SHIFT) 891 #define CSG_REQ_IDLE_GET(reg_val) (((reg_val)&CSG_REQ_IDLE_MASK) >> CSG_REQ_IDLE_SHIFT) 892 #define CSG_REQ_IDLE_SET(reg_val, value) \ 893 (((reg_val) & ~CSG_REQ_IDLE_MASK) | (((value) << CSG_REQ_IDLE_SHIFT) & CSG_REQ_IDLE_MASK)) 894 #define CSG_REQ_PROGRESS_TIMER_EVENT_SHIFT 31 895 #define CSG_REQ_PROGRESS_TIMER_EVENT_MASK (0x1 << CSG_REQ_PROGRESS_TIMER_EVENT_SHIFT) 896 #define CSG_REQ_PROGRESS_TIMER_EVENT_GET(reg_val) \ 897 (((reg_val)&CSG_REQ_PROGRESS_TIMER_EVENT_MASK) >> CSG_REQ_PROGRESS_TIMER_EVENT_SHIFT) 898 #define CSG_REQ_PROGRESS_TIMER_EVENT_SET(reg_val, value) \ 899 (((reg_val) & ~CSG_REQ_PROGRESS_TIMER_EVENT_MASK) | \ 900 (((value) << CSG_REQ_PROGRESS_TIMER_EVENT_SHIFT) & CSG_REQ_PROGRESS_TIMER_EVENT_MASK)) 901 902 /* CSG_ACK_IRQ_MASK register */ 903 #define CSG_ACK_IRQ_MASK_STATE_SHIFT 0 904 #define CSG_ACK_IRQ_MASK_STATE_MASK (0x7 << CSG_ACK_IRQ_MASK_STATE_SHIFT) 905 #define CSG_ACK_IRQ_MASK_STATE_GET(reg_val) (((reg_val)&CSG_ACK_IRQ_MASK_STATE_MASK) >> CSG_ACK_IRQ_MASK_STATE_SHIFT) 906 #define CSG_ACK_IRQ_MASK_STATE_SET(reg_val, value) \ 907 (((reg_val) & ~CSG_ACK_IRQ_MASK_STATE_MASK) | \ 908 (((value) << CSG_ACK_IRQ_MASK_STATE_SHIFT) & CSG_ACK_IRQ_MASK_STATE_MASK)) 909 /* CSG_ACK_IRQ_MASK_STATE values */ 910 #define CSG_ACK_IRQ_MASK_STATE_DISABLED 0x0 911 #define CSG_ACK_IRQ_MASK_STATE_ENABLED 0x7 912 /* End of CSG_ACK_IRQ_MASK_STATE values */ 913 #define CSG_ACK_IRQ_MASK_EP_CFG_SHIFT 4 914 #define CSG_ACK_IRQ_MASK_EP_CFG_MASK (0x1 << CSG_ACK_IRQ_MASK_EP_CFG_SHIFT) 915 #define CSG_ACK_IRQ_MASK_EP_CFG_GET(reg_val) (((reg_val)&CSG_ACK_IRQ_MASK_EP_CFG_MASK) >> CSG_ACK_IRQ_MASK_EP_CFG_SHIFT) 916 #define CSG_ACK_IRQ_MASK_EP_CFG_SET(reg_val, value) \ 917 (((reg_val) & ~CSG_ACK_IRQ_MASK_EP_CFG_MASK) | \ 918 (((value) << CSG_ACK_IRQ_MASK_EP_CFG_SHIFT) & CSG_ACK_IRQ_MASK_EP_CFG_MASK)) 919 #define CSG_ACK_IRQ_MASK_STATUS_UPDATE_SHIFT 5 920 #define CSG_ACK_IRQ_MASK_STATUS_UPDATE_MASK (0x1 << CSG_ACK_IRQ_MASK_STATUS_UPDATE_SHIFT) 921 #define CSG_ACK_IRQ_MASK_STATUS_UPDATE_GET(reg_val) \ 922 (((reg_val)&CSG_ACK_IRQ_MASK_STATUS_UPDATE_MASK) >> CSG_ACK_IRQ_MASK_STATUS_UPDATE_SHIFT) 923 #define CSG_ACK_IRQ_MASK_STATUS_UPDATE_SET(reg_val, value) \ 924 (((reg_val) & ~CSG_ACK_IRQ_MASK_STATUS_UPDATE_MASK) | \ 925 (((value) << CSG_ACK_IRQ_MASK_STATUS_UPDATE_SHIFT) & CSG_ACK_IRQ_MASK_STATUS_UPDATE_MASK)) 926 #define CSG_ACK_IRQ_MASK_SYNC_UPDATE_SHIFT 28 927 #define CSG_ACK_IRQ_MASK_SYNC_UPDATE_MASK (0x1 << CSG_ACK_IRQ_MASK_SYNC_UPDATE_SHIFT) 928 #define CSG_ACK_IRQ_MASK_SYNC_UPDATE_GET(reg_val) \ 929 (((reg_val)&CSG_ACK_IRQ_MASK_SYNC_UPDATE_MASK) >> CSG_ACK_IRQ_MASK_SYNC_UPDATE_SHIFT) 930 #define CSG_ACK_IRQ_MASK_SYNC_UPDATE_SET(reg_val, value) \ 931 (((reg_val) & ~CSG_ACK_IRQ_MASK_SYNC_UPDATE_MASK) | \ 932 (((value) << CSG_ACK_IRQ_MASK_SYNC_UPDATE_SHIFT) & CSG_ACK_IRQ_MASK_SYNC_UPDATE_MASK)) 933 #define CSG_ACK_IRQ_MASK_IDLE_SHIFT 29 934 #define CSG_ACK_IRQ_MASK_IDLE_MASK (0x1 << CSG_ACK_IRQ_MASK_IDLE_SHIFT) 935 #define CSG_ACK_IRQ_MASK_IDLE_GET(reg_val) (((reg_val)&CSG_ACK_IRQ_MASK_IDLE_MASK) >> CSG_ACK_IRQ_MASK_IDLE_SHIFT) 936 #define CSG_ACK_IRQ_MASK_IDLE_SET(reg_val, value) \ 937 (((reg_val) & ~CSG_ACK_IRQ_MASK_IDLE_MASK) | \ 938 (((value) << CSG_ACK_IRQ_MASK_IDLE_SHIFT) & CSG_ACK_IRQ_MASK_IDLE_MASK)) 939 #define CSG_ACK_IRQ_MASK_DOORBELL_SHIFT 30 940 #define CSG_ACK_IRQ_MASK_DOORBELL_MASK (0x1 << CSG_ACK_IRQ_MASK_DOORBELL_SHIFT) 941 #define CSG_ACK_IRQ_MASK_DOORBELL_GET(reg_val) \ 942 (((reg_val)&CSG_ACK_IRQ_MASK_DOORBELL_MASK) >> CSG_ACK_IRQ_MASK_DOORBELL_SHIFT) 943 #define CSG_ACK_IRQ_MASK_DOORBELL_SET(reg_val, value) \ 944 (((reg_val) & ~CSG_ACK_IRQ_MASK_DOORBELL_MASK) | \ 945 (((value) << CSG_ACK_IRQ_MASK_DOORBELL_SHIFT) & CSG_ACK_IRQ_MASK_DOORBELL_MASK)) 946 #define CSG_ACK_IRQ_MASK_PROGRESS_TIMER_EVENT_SHIFT 31 947 #define CSG_ACK_IRQ_MASK_PROGRESS_TIMER_EVENT_MASK (0x1 << CSG_ACK_IRQ_MASK_PROGRESS_TIMER_EVENT_SHIFT) 948 #define CSG_ACK_IRQ_MASK_PROGRESS_TIMER_EVENT_GET(reg_val) \ 949 (((reg_val)&CSG_ACK_IRQ_MASK_PROGRESS_TIMER_EVENT_MASK) >> CSG_ACK_IRQ_MASK_PROGRESS_TIMER_EVENT_SHIFT) 950 #define CSG_ACK_IRQ_MASK_PROGRESS_TIMER_EVENT_SET(reg_val, value) \ 951 (((reg_val) & ~CSG_ACK_IRQ_MASK_PROGRESS_TIMER_EVENT_MASK) | \ 952 (((value) << CSG_ACK_IRQ_MASK_PROGRESS_TIMER_EVENT_SHIFT) & CSG_ACK_IRQ_MASK_PROGRESS_TIMER_EVENT_MASK)) 953 954 /* CSG_EP_REQ register */ 955 #define CSG_EP_REQ_COMPUTE_EP_SHIFT 0 956 #define CSG_EP_REQ_COMPUTE_EP_MASK (0xFF << CSG_EP_REQ_COMPUTE_EP_SHIFT) 957 #define CSG_EP_REQ_COMPUTE_EP_GET(reg_val) (((reg_val)&CSG_EP_REQ_COMPUTE_EP_MASK) >> CSG_EP_REQ_COMPUTE_EP_SHIFT) 958 #define CSG_EP_REQ_COMPUTE_EP_SET(reg_val, value) \ 959 (((reg_val) & ~CSG_EP_REQ_COMPUTE_EP_MASK) | \ 960 (((value) << CSG_EP_REQ_COMPUTE_EP_SHIFT) & CSG_EP_REQ_COMPUTE_EP_MASK)) 961 #define CSG_EP_REQ_FRAGMENT_EP_SHIFT 8 962 #define CSG_EP_REQ_FRAGMENT_EP_MASK (0xFF << CSG_EP_REQ_FRAGMENT_EP_SHIFT) 963 #define CSG_EP_REQ_FRAGMENT_EP_GET(reg_val) (((reg_val)&CSG_EP_REQ_FRAGMENT_EP_MASK) >> CSG_EP_REQ_FRAGMENT_EP_SHIFT) 964 #define CSG_EP_REQ_FRAGMENT_EP_SET(reg_val, value) \ 965 (((reg_val) & ~CSG_EP_REQ_FRAGMENT_EP_MASK) | \ 966 (((value) << CSG_EP_REQ_FRAGMENT_EP_SHIFT) & CSG_EP_REQ_FRAGMENT_EP_MASK)) 967 #define CSG_EP_REQ_TILER_EP_SHIFT 16 968 #define CSG_EP_REQ_TILER_EP_MASK (0xF << CSG_EP_REQ_TILER_EP_SHIFT) 969 #define CSG_EP_REQ_TILER_EP_GET(reg_val) (((reg_val)&CSG_EP_REQ_TILER_EP_MASK) >> CSG_EP_REQ_TILER_EP_SHIFT) 970 #define CSG_EP_REQ_TILER_EP_SET(reg_val, value) \ 971 (((reg_val) & ~CSG_EP_REQ_TILER_EP_MASK) | (((value) << CSG_EP_REQ_TILER_EP_SHIFT) & CSG_EP_REQ_TILER_EP_MASK)) 972 #define CSG_EP_REQ_EXCLUSIVE_COMPUTE_SHIFT 20 973 #define CSG_EP_REQ_EXCLUSIVE_COMPUTE_MASK (0x1 << CSG_EP_REQ_EXCLUSIVE_COMPUTE_SHIFT) 974 #define CSG_EP_REQ_EXCLUSIVE_COMPUTE_GET(reg_val) \ 975 (((reg_val)&CSG_EP_REQ_EXCLUSIVE_COMPUTE_MASK) >> CSG_EP_REQ_EXCLUSIVE_COMPUTE_SHIFT) 976 #define CSG_EP_REQ_EXCLUSIVE_COMPUTE_SET(reg_val, value) \ 977 (((reg_val) & ~CSG_EP_REQ_EXCLUSIVE_COMPUTE_MASK) | \ 978 (((value) << CSG_EP_REQ_EXCLUSIVE_COMPUTE_SHIFT) & CSG_EP_REQ_EXCLUSIVE_COMPUTE_MASK)) 979 #define CSG_EP_REQ_EXCLUSIVE_FRAGMENT_SHIFT 21 980 #define CSG_EP_REQ_EXCLUSIVE_FRAGMENT_MASK (0x1 << CSG_EP_REQ_EXCLUSIVE_FRAGMENT_SHIFT) 981 #define CSG_EP_REQ_EXCLUSIVE_FRAGMENT_GET(reg_val) \ 982 (((reg_val)&CSG_EP_REQ_EXCLUSIVE_FRAGMENT_MASK) >> CSG_EP_REQ_EXCLUSIVE_FRAGMENT_SHIFT) 983 #define CSG_EP_REQ_EXCLUSIVE_FRAGMENT_SET(reg_val, value) \ 984 (((reg_val) & ~CSG_EP_REQ_EXCLUSIVE_FRAGMENT_MASK) | \ 985 (((value) << CSG_EP_REQ_EXCLUSIVE_FRAGMENT_SHIFT) & CSG_EP_REQ_EXCLUSIVE_FRAGMENT_MASK)) 986 #define CSG_EP_REQ_PRIORITY_SHIFT 28 987 #define CSG_EP_REQ_PRIORITY_MASK (0xF << CSG_EP_REQ_PRIORITY_SHIFT) 988 #define CSG_EP_REQ_PRIORITY_GET(reg_val) (((reg_val)&CSG_EP_REQ_PRIORITY_MASK) >> CSG_EP_REQ_PRIORITY_SHIFT) 989 #define CSG_EP_REQ_PRIORITY_SET(reg_val, value) \ 990 (((reg_val) & ~CSG_EP_REQ_PRIORITY_MASK) | (((value) << CSG_EP_REQ_PRIORITY_SHIFT) & CSG_EP_REQ_PRIORITY_MASK)) 991 992 /* CSG_SUSPEND_BUF register */ 993 #define CSG_SUSPEND_BUF_POINTER_SHIFT 0 994 #define CSG_SUSPEND_BUF_POINTER_MASK (GPU_ULL(0xFFFFFFFFFFFFFFFF) << CSG_SUSPEND_BUF_POINTER_SHIFT) 995 #define CSG_SUSPEND_BUF_POINTER_GET(reg_val) (((reg_val)&CSG_SUSPEND_BUF_POINTER_MASK) >> CSG_SUSPEND_BUF_POINTER_SHIFT) 996 #define CSG_SUSPEND_BUF_POINTER_SET(reg_val, value) \ 997 (((reg_val) & ~CSG_SUSPEND_BUF_POINTER_MASK) | \ 998 (((value) << CSG_SUSPEND_BUF_POINTER_SHIFT) & CSG_SUSPEND_BUF_POINTER_MASK)) 999 1000 /* CSG_PROTM_SUSPEND_BUF register */ 1001 #define CSG_PROTM_SUSPEND_BUF_POINTER_SHIFT 0 1002 #define CSG_PROTM_SUSPEND_BUF_POINTER_MASK \ 1003 (GPU_ULL(0xFFFFFFFFFFFFFFFF) << CSG_PROTM_SUSPEND_BUF_POINTER_SHIFT) 1004 #define CSG_PROTM_SUSPEND_BUF_POINTER_GET(reg_val) \ 1005 (((reg_val)&CSG_PROTM_SUSPEND_BUF_POINTER_MASK) >> CSG_PROTM_SUSPEND_BUF_POINTER_SHIFT) 1006 #define CSG_PROTM_SUSPEND_BUF_POINTER_SET(reg_val, value) \ 1007 (((reg_val) & ~CSG_PROTM_SUSPEND_BUF_POINTER_MASK) | \ 1008 (((value) << CSG_PROTM_SUSPEND_BUF_POINTER_SHIFT) & CSG_PROTM_SUSPEND_BUF_POINTER_MASK)) 1009 1010 /* CSG_DVS_BUF_BUFFER register */ 1011 #define CSG_DVS_BUF_BUFFER_SIZE_SHIFT GPU_U(0) 1012 #define CSG_DVS_BUF_BUFFER_SIZE_MASK (GPU_U(0xFFF) << CSG_DVS_BUF_BUFFER_SIZE_SHIFT) 1013 #define CSG_DVS_BUF_BUFFER_SIZE_GET(reg_val) (((reg_val)&CSG_DVS_BUF_BUFFER_SIZE_MASK) >> CSG_DVS_BUF_BUFFER_SIZE_SHIFT) 1014 #define CSG_DVS_BUF_BUFFER_SIZE_SET(reg_val, value) \ 1015 (((reg_val) & ~CSG_DVS_BUF_BUFFER_SIZE_MASK) | \ 1016 (((value) << CSG_DVS_BUF_BUFFER_SIZE_SHIFT) & CSG_DVS_BUF_BUFFER_SIZE_MASK)) 1017 #define CSG_DVS_BUF_BUFFER_POINTER_SHIFT GPU_U(12) 1018 #define CSG_DVS_BUF_BUFFER_POINTER_MASK \ 1019 (GPU_ULL(0xFFFFFFFFFFFFF) << CSG_DVS_BUF_BUFFER_POINTER_SHIFT) 1020 #define CSG_DVS_BUF_BUFFER_POINTER_GET(reg_val) \ 1021 (((reg_val)&CSG_DVS_BUF_BUFFER_POINTER_MASK) >> CSG_DVS_BUF_BUFFER_POINTER_SHIFT) 1022 #define CSG_DVS_BUF_BUFFER_POINTER_SET(reg_val, value) \ 1023 (((reg_val) & ~CSG_DVS_BUF_BUFFER_POINTER_MASK) | \ 1024 (((value) << CSG_DVS_BUF_BUFFER_POINTER_SHIFT) & CSG_DVS_BUF_BUFFER_POINTER_MASK)) 1025 1026 /* End of CSG_INPUT_BLOCK register set definitions */ 1027 1028 /* CSG_OUTPUT_BLOCK register set definitions */ 1029 1030 /* CSG_ACK register */ 1031 #define CSG_ACK_STATE_SHIFT 0 1032 #define CSG_ACK_STATE_MASK (0x7 << CSG_ACK_STATE_SHIFT) 1033 #define CSG_ACK_STATE_GET(reg_val) (((reg_val)&CSG_ACK_STATE_MASK) >> CSG_ACK_STATE_SHIFT) 1034 #define CSG_ACK_STATE_SET(reg_val, value) \ 1035 (((reg_val) & ~CSG_ACK_STATE_MASK) | (((value) << CSG_ACK_STATE_SHIFT) & CSG_ACK_STATE_MASK)) 1036 /* CSG_ACK_STATE values */ 1037 #define CSG_ACK_STATE_TERMINATE 0x0 1038 #define CSG_ACK_STATE_START 0x1 1039 #define CSG_ACK_STATE_SUSPEND 0x2 1040 #define CSG_ACK_STATE_RESUME 0x3 1041 /* End of CSG_ACK_STATE values */ 1042 #define CSG_ACK_EP_CFG_SHIFT 4 1043 #define CSG_ACK_EP_CFG_MASK (0x1 << CSG_ACK_EP_CFG_SHIFT) 1044 #define CSG_ACK_EP_CFG_GET(reg_val) (((reg_val)&CSG_ACK_EP_CFG_MASK) >> CSG_ACK_EP_CFG_SHIFT) 1045 #define CSG_ACK_EP_CFG_SET(reg_val, value) \ 1046 (((reg_val) & ~CSG_ACK_EP_CFG_MASK) | (((value) << CSG_ACK_EP_CFG_SHIFT) & CSG_ACK_EP_CFG_MASK)) 1047 #define CSG_ACK_STATUS_UPDATE_SHIFT 5 1048 #define CSG_ACK_STATUS_UPDATE_MASK (0x1 << CSG_ACK_STATUS_UPDATE_SHIFT) 1049 #define CSG_ACK_STATUS_UPDATE_GET(reg_val) (((reg_val)&CSG_ACK_STATUS_UPDATE_MASK) >> CSG_ACK_STATUS_UPDATE_SHIFT) 1050 #define CSG_ACK_STATUS_UPDATE_SET(reg_val, value) \ 1051 (((reg_val) & ~CSG_ACK_STATUS_UPDATE_MASK) | \ 1052 (((value) << CSG_ACK_STATUS_UPDATE_SHIFT) & CSG_ACK_STATUS_UPDATE_MASK)) 1053 #define CSG_ACK_SYNC_UPDATE_SHIFT 28 1054 #define CSG_ACK_SYNC_UPDATE_MASK (0x1 << CSG_ACK_SYNC_UPDATE_SHIFT) 1055 #define CSG_ACK_SYNC_UPDATE_GET(reg_val) (((reg_val)&CSG_ACK_SYNC_UPDATE_MASK) >> CSG_ACK_SYNC_UPDATE_SHIFT) 1056 #define CSG_ACK_SYNC_UPDATE_SET(reg_val, value) \ 1057 (((reg_val) & ~CSG_ACK_SYNC_UPDATE_MASK) | (((value) << CSG_ACK_SYNC_UPDATE_SHIFT) & CSG_ACK_SYNC_UPDATE_MASK)) 1058 #define CSG_ACK_IDLE_SHIFT 29 1059 #define CSG_ACK_IDLE_MASK (0x1 << CSG_ACK_IDLE_SHIFT) 1060 #define CSG_ACK_IDLE_GET(reg_val) (((reg_val)&CSG_ACK_IDLE_MASK) >> CSG_ACK_IDLE_SHIFT) 1061 #define CSG_ACK_IDLE_SET(reg_val, value) \ 1062 (((reg_val) & ~CSG_ACK_IDLE_MASK) | (((value) << CSG_ACK_IDLE_SHIFT) & CSG_ACK_IDLE_MASK)) 1063 #define CSG_ACK_DOORBELL_SHIFT 30 1064 #define CSG_ACK_DOORBELL_MASK (0x1 << CSG_ACK_DOORBELL_SHIFT) 1065 #define CSG_ACK_DOORBELL_GET(reg_val) (((reg_val)&CSG_ACK_DOORBELL_MASK) >> CSG_ACK_DOORBELL_SHIFT) 1066 #define CSG_ACK_DOORBELL_SET(reg_val, value) \ 1067 (((reg_val) & ~CSG_ACK_DOORBELL_MASK) | (((value) << CSG_ACK_DOORBELL_SHIFT) & CSG_ACK_DOORBELL_MASK)) 1068 #define CSG_ACK_PROGRESS_TIMER_EVENT_SHIFT 31 1069 #define CSG_ACK_PROGRESS_TIMER_EVENT_MASK (0x1 << CSG_ACK_PROGRESS_TIMER_EVENT_SHIFT) 1070 #define CSG_ACK_PROGRESS_TIMER_EVENT_GET(reg_val) \ 1071 (((reg_val)&CSG_ACK_PROGRESS_TIMER_EVENT_MASK) >> CSG_ACK_PROGRESS_TIMER_EVENT_SHIFT) 1072 #define CSG_ACK_PROGRESS_TIMER_EVENT_SET(reg_val, value) \ 1073 (((reg_val) & ~CSG_ACK_PROGRESS_TIMER_EVENT_MASK) | \ 1074 (((value) << CSG_ACK_PROGRESS_TIMER_EVENT_SHIFT) & CSG_ACK_PROGRESS_TIMER_EVENT_MASK)) 1075 1076 /* CSG_STATUS_EP_CURRENT register */ 1077 #define CSG_STATUS_EP_CURRENT_COMPUTE_EP_SHIFT 0 1078 #define CSG_STATUS_EP_CURRENT_COMPUTE_EP_MASK (0xFF << CSG_STATUS_EP_CURRENT_COMPUTE_EP_SHIFT) 1079 #define CSG_STATUS_EP_CURRENT_COMPUTE_EP_GET(reg_val) \ 1080 (((reg_val)&CSG_STATUS_EP_CURRENT_COMPUTE_EP_MASK) >> CSG_STATUS_EP_CURRENT_COMPUTE_EP_SHIFT) 1081 #define CSG_STATUS_EP_CURRENT_COMPUTE_EP_SET(reg_val, value) \ 1082 (((reg_val) & ~CSG_STATUS_EP_CURRENT_COMPUTE_EP_MASK) | \ 1083 (((value) << CSG_STATUS_EP_CURRENT_COMPUTE_EP_SHIFT) & CSG_STATUS_EP_CURRENT_COMPUTE_EP_MASK)) 1084 #define CSG_STATUS_EP_CURRENT_FRAGMENT_EP_SHIFT 8 1085 #define CSG_STATUS_EP_CURRENT_FRAGMENT_EP_MASK (0xFF << CSG_STATUS_EP_CURRENT_FRAGMENT_EP_SHIFT) 1086 #define CSG_STATUS_EP_CURRENT_FRAGMENT_EP_GET(reg_val) \ 1087 (((reg_val)&CSG_STATUS_EP_CURRENT_FRAGMENT_EP_MASK) >> CSG_STATUS_EP_CURRENT_FRAGMENT_EP_SHIFT) 1088 #define CSG_STATUS_EP_CURRENT_FRAGMENT_EP_SET(reg_val, value) \ 1089 (((reg_val) & ~CSG_STATUS_EP_CURRENT_FRAGMENT_EP_MASK) | \ 1090 (((value) << CSG_STATUS_EP_CURRENT_FRAGMENT_EP_SHIFT) & CSG_STATUS_EP_CURRENT_FRAGMENT_EP_MASK)) 1091 #define CSG_STATUS_EP_CURRENT_TILER_EP_SHIFT 16 1092 #define CSG_STATUS_EP_CURRENT_TILER_EP_MASK (0xF << CSG_STATUS_EP_CURRENT_TILER_EP_SHIFT) 1093 #define CSG_STATUS_EP_CURRENT_TILER_EP_GET(reg_val) \ 1094 (((reg_val)&CSG_STATUS_EP_CURRENT_TILER_EP_MASK) >> CSG_STATUS_EP_CURRENT_TILER_EP_SHIFT) 1095 #define CSG_STATUS_EP_CURRENT_TILER_EP_SET(reg_val, value) \ 1096 (((reg_val) & ~CSG_STATUS_EP_CURRENT_TILER_EP_MASK) | \ 1097 (((value) << CSG_STATUS_EP_CURRENT_TILER_EP_SHIFT) & CSG_STATUS_EP_CURRENT_TILER_EP_MASK)) 1098 1099 /* CSG_STATUS_EP_REQ register */ 1100 #define CSG_STATUS_EP_REQ_COMPUTE_EP_SHIFT 0 1101 #define CSG_STATUS_EP_REQ_COMPUTE_EP_MASK (0xFF << CSG_STATUS_EP_REQ_COMPUTE_EP_SHIFT) 1102 #define CSG_STATUS_EP_REQ_COMPUTE_EP_GET(reg_val) \ 1103 (((reg_val)&CSG_STATUS_EP_REQ_COMPUTE_EP_MASK) >> CSG_STATUS_EP_REQ_COMPUTE_EP_SHIFT) 1104 #define CSG_STATUS_EP_REQ_COMPUTE_EP_SET(reg_val, value) \ 1105 (((reg_val) & ~CSG_STATUS_EP_REQ_COMPUTE_EP_MASK) | \ 1106 (((value) << CSG_STATUS_EP_REQ_COMPUTE_EP_SHIFT) & CSG_STATUS_EP_REQ_COMPUTE_EP_MASK)) 1107 #define CSG_STATUS_EP_REQ_FRAGMENT_EP_SHIFT 8 1108 #define CSG_STATUS_EP_REQ_FRAGMENT_EP_MASK (0xFF << CSG_STATUS_EP_REQ_FRAGMENT_EP_SHIFT) 1109 #define CSG_STATUS_EP_REQ_FRAGMENT_EP_GET(reg_val) \ 1110 (((reg_val)&CSG_STATUS_EP_REQ_FRAGMENT_EP_MASK) >> CSG_STATUS_EP_REQ_FRAGMENT_EP_SHIFT) 1111 #define CSG_STATUS_EP_REQ_FRAGMENT_EP_SET(reg_val, value) \ 1112 (((reg_val) & ~CSG_STATUS_EP_REQ_FRAGMENT_EP_MASK) | \ 1113 (((value) << CSG_STATUS_EP_REQ_FRAGMENT_EP_SHIFT) & CSG_STATUS_EP_REQ_FRAGMENT_EP_MASK)) 1114 #define CSG_STATUS_EP_REQ_TILER_EP_SHIFT 16 1115 #define CSG_STATUS_EP_REQ_TILER_EP_MASK (0xF << CSG_STATUS_EP_REQ_TILER_EP_SHIFT) 1116 #define CSG_STATUS_EP_REQ_TILER_EP_GET(reg_val) \ 1117 (((reg_val)&CSG_STATUS_EP_REQ_TILER_EP_MASK) >> CSG_STATUS_EP_REQ_TILER_EP_SHIFT) 1118 #define CSG_STATUS_EP_REQ_TILER_EP_SET(reg_val, value) \ 1119 (((reg_val) & ~CSG_STATUS_EP_REQ_TILER_EP_MASK) | \ 1120 (((value) << CSG_STATUS_EP_REQ_TILER_EP_SHIFT) & CSG_STATUS_EP_REQ_TILER_EP_MASK)) 1121 #define CSG_STATUS_EP_REQ_EXCLUSIVE_COMPUTE_SHIFT 20 1122 #define CSG_STATUS_EP_REQ_EXCLUSIVE_COMPUTE_MASK (0x1 << CSG_STATUS_EP_REQ_EXCLUSIVE_COMPUTE_SHIFT) 1123 #define CSG_STATUS_EP_REQ_EXCLUSIVE_COMPUTE_GET(reg_val) \ 1124 (((reg_val)&CSG_STATUS_EP_REQ_EXCLUSIVE_COMPUTE_MASK) >> CSG_STATUS_EP_REQ_EXCLUSIVE_COMPUTE_SHIFT) 1125 #define CSG_STATUS_EP_REQ_EXCLUSIVE_COMPUTE_SET(reg_val, value) \ 1126 (((reg_val) & ~CSG_STATUS_EP_REQ_EXCLUSIVE_COMPUTE_MASK) | \ 1127 (((value) << CSG_STATUS_EP_REQ_EXCLUSIVE_COMPUTE_SHIFT) & CSG_STATUS_EP_REQ_EXCLUSIVE_COMPUTE_MASK)) 1128 #define CSG_STATUS_EP_REQ_EXCLUSIVE_FRAGMENT_SHIFT 21 1129 #define CSG_STATUS_EP_REQ_EXCLUSIVE_FRAGMENT_MASK (0x1 << CSG_STATUS_EP_REQ_EXCLUSIVE_FRAGMENT_SHIFT) 1130 #define CSG_STATUS_EP_REQ_EXCLUSIVE_FRAGMENT_GET(reg_val) \ 1131 (((reg_val)&CSG_STATUS_EP_REQ_EXCLUSIVE_FRAGMENT_MASK) >> CSG_STATUS_EP_REQ_EXCLUSIVE_FRAGMENT_SHIFT) 1132 #define CSG_STATUS_EP_REQ_EXCLUSIVE_FRAGMENT_SET(reg_val, value) \ 1133 (((reg_val) & ~CSG_STATUS_EP_REQ_EXCLUSIVE_FRAGMENT_MASK) | \ 1134 (((value) << CSG_STATUS_EP_REQ_EXCLUSIVE_FRAGMENT_SHIFT) & CSG_STATUS_EP_REQ_EXCLUSIVE_FRAGMENT_MASK)) 1135 1136 /* End of CSG_OUTPUT_BLOCK register set definitions */ 1137 1138 /* STREAM_CONTROL_BLOCK register set definitions */ 1139 1140 /* STREAM_FEATURES register */ 1141 #define STREAM_FEATURES_WORK_REGISTERS_SHIFT 0 1142 #define STREAM_FEATURES_WORK_REGISTERS_MASK (0xFF << STREAM_FEATURES_WORK_REGISTERS_SHIFT) 1143 #define STREAM_FEATURES_WORK_REGISTERS_GET(reg_val) \ 1144 (((reg_val)&STREAM_FEATURES_WORK_REGISTERS_MASK) >> STREAM_FEATURES_WORK_REGISTERS_SHIFT) 1145 #define STREAM_FEATURES_WORK_REGISTERS_SET(reg_val, value) \ 1146 (((reg_val) & ~STREAM_FEATURES_WORK_REGISTERS_MASK) | \ 1147 (((value) << STREAM_FEATURES_WORK_REGISTERS_SHIFT) & STREAM_FEATURES_WORK_REGISTERS_MASK)) 1148 #define STREAM_FEATURES_SCOREBOARDS_SHIFT 8 1149 #define STREAM_FEATURES_SCOREBOARDS_MASK (0xFF << STREAM_FEATURES_SCOREBOARDS_SHIFT) 1150 #define STREAM_FEATURES_SCOREBOARDS_GET(reg_val) \ 1151 (((reg_val)&STREAM_FEATURES_SCOREBOARDS_MASK) >> STREAM_FEATURES_SCOREBOARDS_SHIFT) 1152 #define STREAM_FEATURES_SCOREBOARDS_SET(reg_val, value) \ 1153 (((reg_val) & ~STREAM_FEATURES_SCOREBOARDS_MASK) | \ 1154 (((value) << STREAM_FEATURES_SCOREBOARDS_SHIFT) & STREAM_FEATURES_SCOREBOARDS_MASK)) 1155 #define STREAM_FEATURES_COMPUTE_SHIFT 16 1156 #define STREAM_FEATURES_COMPUTE_MASK (0x1 << STREAM_FEATURES_COMPUTE_SHIFT) 1157 #define STREAM_FEATURES_COMPUTE_GET(reg_val) (((reg_val)&STREAM_FEATURES_COMPUTE_MASK) >> STREAM_FEATURES_COMPUTE_SHIFT) 1158 #define STREAM_FEATURES_COMPUTE_SET(reg_val, value) \ 1159 (((reg_val) & ~STREAM_FEATURES_COMPUTE_MASK) | \ 1160 (((value) << STREAM_FEATURES_COMPUTE_SHIFT) & STREAM_FEATURES_COMPUTE_MASK)) 1161 #define STREAM_FEATURES_FRAGMENT_SHIFT 17 1162 #define STREAM_FEATURES_FRAGMENT_MASK (0x1 << STREAM_FEATURES_FRAGMENT_SHIFT) 1163 #define STREAM_FEATURES_FRAGMENT_GET(reg_val) \ 1164 (((reg_val)&STREAM_FEATURES_FRAGMENT_MASK) >> STREAM_FEATURES_FRAGMENT_SHIFT) 1165 #define STREAM_FEATURES_FRAGMENT_SET(reg_val, value) \ 1166 (((reg_val) & ~STREAM_FEATURES_FRAGMENT_MASK) | \ 1167 (((value) << STREAM_FEATURES_FRAGMENT_SHIFT) & STREAM_FEATURES_FRAGMENT_MASK)) 1168 #define STREAM_FEATURES_TILER_SHIFT 18 1169 #define STREAM_FEATURES_TILER_MASK (0x1 << STREAM_FEATURES_TILER_SHIFT) 1170 #define STREAM_FEATURES_TILER_GET(reg_val) (((reg_val)&STREAM_FEATURES_TILER_MASK) >> STREAM_FEATURES_TILER_SHIFT) 1171 #define STREAM_FEATURES_TILER_SET(reg_val, value) \ 1172 (((reg_val) & ~STREAM_FEATURES_TILER_MASK) | \ 1173 (((value) << STREAM_FEATURES_TILER_SHIFT) & STREAM_FEATURES_TILER_MASK)) 1174 1175 /* STREAM_INPUT_VA register */ 1176 #define STREAM_INPUT_VA_VALUE_SHIFT 0 1177 #define STREAM_INPUT_VA_VALUE_MASK (0xFFFFFFFF << STREAM_INPUT_VA_VALUE_SHIFT) 1178 #define STREAM_INPUT_VA_VALUE_GET(reg_val) (((reg_val)&STREAM_INPUT_VA_VALUE_MASK) >> STREAM_INPUT_VA_VALUE_SHIFT) 1179 #define STREAM_INPUT_VA_VALUE_SET(reg_val, value) \ 1180 (((reg_val) & ~STREAM_INPUT_VA_VALUE_MASK) | \ 1181 (((value) << STREAM_INPUT_VA_VALUE_SHIFT) & STREAM_INPUT_VA_VALUE_MASK)) 1182 1183 /* STREAM_OUTPUT_VA register */ 1184 #define STREAM_OUTPUT_VA_VALUE_SHIFT 0 1185 #define STREAM_OUTPUT_VA_VALUE_MASK (0xFFFFFFFF << STREAM_OUTPUT_VA_VALUE_SHIFT) 1186 #define STREAM_OUTPUT_VA_VALUE_GET(reg_val) (((reg_val)&STREAM_OUTPUT_VA_VALUE_MASK) >> STREAM_OUTPUT_VA_VALUE_SHIFT) 1187 #define STREAM_OUTPUT_VA_VALUE_SET(reg_val, value) \ 1188 (((reg_val) & ~STREAM_OUTPUT_VA_VALUE_MASK) | \ 1189 (((value) << STREAM_OUTPUT_VA_VALUE_SHIFT) & STREAM_OUTPUT_VA_VALUE_MASK)) 1190 /* End of STREAM_CONTROL_BLOCK register set definitions */ 1191 1192 /* GLB_INPUT_BLOCK register set definitions */ 1193 1194 /* GLB_REQ register */ 1195 #define GLB_REQ_HALT_SHIFT 0 1196 #define GLB_REQ_HALT_MASK (0x1 << GLB_REQ_HALT_SHIFT) 1197 #define GLB_REQ_HALT_GET(reg_val) (((reg_val)&GLB_REQ_HALT_MASK) >> GLB_REQ_HALT_SHIFT) 1198 #define GLB_REQ_HALT_SET(reg_val, value) \ 1199 (((reg_val) & ~GLB_REQ_HALT_MASK) | (((value) << GLB_REQ_HALT_SHIFT) & GLB_REQ_HALT_MASK)) 1200 #define GLB_REQ_CFG_PROGRESS_TIMER_SHIFT 1 1201 #define GLB_REQ_CFG_PROGRESS_TIMER_MASK (0x1 << GLB_REQ_CFG_PROGRESS_TIMER_SHIFT) 1202 #define GLB_REQ_CFG_PROGRESS_TIMER_GET(reg_val) \ 1203 (((reg_val)&GLB_REQ_CFG_PROGRESS_TIMER_MASK) >> GLB_REQ_CFG_PROGRESS_TIMER_SHIFT) 1204 #define GLB_REQ_CFG_PROGRESS_TIMER_SET(reg_val, value) \ 1205 (((reg_val) & ~GLB_REQ_CFG_PROGRESS_TIMER_MASK) | \ 1206 (((value) << GLB_REQ_CFG_PROGRESS_TIMER_SHIFT) & GLB_REQ_CFG_PROGRESS_TIMER_MASK)) 1207 #define GLB_REQ_CFG_ALLOC_EN_SHIFT 2 1208 #define GLB_REQ_CFG_ALLOC_EN_MASK (0x1 << GLB_REQ_CFG_ALLOC_EN_SHIFT) 1209 #define GLB_REQ_CFG_ALLOC_EN_GET(reg_val) (((reg_val)&GLB_REQ_CFG_ALLOC_EN_MASK) >> GLB_REQ_CFG_ALLOC_EN_SHIFT) 1210 #define GLB_REQ_CFG_ALLOC_EN_SET(reg_val, value) \ 1211 (((reg_val) & ~GLB_REQ_CFG_ALLOC_EN_MASK) | (((value) << GLB_REQ_CFG_ALLOC_EN_SHIFT) & GLB_REQ_CFG_ALLOC_EN_MASK)) 1212 #define GLB_REQ_CFG_PWROFF_TIMER_SHIFT 3 1213 #define GLB_REQ_CFG_PWROFF_TIMER_MASK (0x1 << GLB_REQ_CFG_PWROFF_TIMER_SHIFT) 1214 #define GLB_REQ_CFG_PWROFF_TIMER_GET(reg_val) \ 1215 (((reg_val)&GLB_REQ_CFG_PWROFF_TIMER_MASK) >> GLB_REQ_CFG_PWROFF_TIMER_SHIFT) 1216 #define GLB_REQ_CFG_PWROFF_TIMER_SET(reg_val, value) \ 1217 (((reg_val) & ~GLB_REQ_CFG_PWROFF_TIMER_MASK) | \ 1218 (((value) << GLB_REQ_CFG_PWROFF_TIMER_SHIFT) & GLB_REQ_CFG_PWROFF_TIMER_MASK)) 1219 #define GLB_REQ_PROTM_ENTER_SHIFT 4 1220 #define GLB_REQ_PROTM_ENTER_MASK (0x1 << GLB_REQ_PROTM_ENTER_SHIFT) 1221 #define GLB_REQ_PROTM_ENTER_GET(reg_val) (((reg_val)&GLB_REQ_PROTM_ENTER_MASK) >> GLB_REQ_PROTM_ENTER_SHIFT) 1222 #define GLB_REQ_PROTM_ENTER_SET(reg_val, value) \ 1223 (((reg_val) & ~GLB_REQ_PROTM_ENTER_MASK) | (((value) << GLB_REQ_PROTM_ENTER_SHIFT) & GLB_REQ_PROTM_ENTER_MASK)) 1224 #define GLB_REQ_PRFCNT_ENABLE_SHIFT 5 1225 #define GLB_REQ_PRFCNT_ENABLE_MASK (0x1 << GLB_REQ_PRFCNT_ENABLE_SHIFT) 1226 #define GLB_REQ_PRFCNT_ENABLE_GET(reg_val) (((reg_val)&GLB_REQ_PRFCNT_ENABLE_MASK) >> GLB_REQ_PRFCNT_ENABLE_SHIFT) 1227 #define GLB_REQ_PRFCNT_ENABLE_SET(reg_val, value) \ 1228 (((reg_val) & ~GLB_REQ_PRFCNT_ENABLE_MASK) | \ 1229 (((value) << GLB_REQ_PRFCNT_ENABLE_SHIFT) & GLB_REQ_PRFCNT_ENABLE_MASK)) 1230 #define GLB_REQ_PRFCNT_SAMPLE_SHIFT 6 1231 #define GLB_REQ_PRFCNT_SAMPLE_MASK (0x1 << GLB_REQ_PRFCNT_SAMPLE_SHIFT) 1232 #define GLB_REQ_PRFCNT_SAMPLE_GET(reg_val) (((reg_val)&GLB_REQ_PRFCNT_SAMPLE_MASK) >> GLB_REQ_PRFCNT_SAMPLE_SHIFT) 1233 #define GLB_REQ_PRFCNT_SAMPLE_SET(reg_val, value) \ 1234 (((reg_val) & ~GLB_REQ_PRFCNT_SAMPLE_MASK) | \ 1235 (((value) << GLB_REQ_PRFCNT_SAMPLE_SHIFT) & GLB_REQ_PRFCNT_SAMPLE_MASK)) 1236 #define GLB_REQ_COUNTER_ENABLE_SHIFT 7 1237 #define GLB_REQ_COUNTER_ENABLE_MASK (0x1 << GLB_REQ_COUNTER_ENABLE_SHIFT) 1238 #define GLB_REQ_COUNTER_ENABLE_GET(reg_val) (((reg_val)&GLB_REQ_COUNTER_ENABLE_MASK) >> GLB_REQ_COUNTER_ENABLE_SHIFT) 1239 #define GLB_REQ_COUNTER_ENABLE_SET(reg_val, value) \ 1240 (((reg_val) & ~GLB_REQ_COUNTER_ENABLE_MASK) | \ 1241 (((value) << GLB_REQ_COUNTER_ENABLE_SHIFT) & GLB_REQ_COUNTER_ENABLE_MASK)) 1242 #define GLB_REQ_PING_SHIFT 8 1243 #define GLB_REQ_PING_MASK (0x1 << GLB_REQ_PING_SHIFT) 1244 #define GLB_REQ_PING_GET(reg_val) (((reg_val)&GLB_REQ_PING_MASK) >> GLB_REQ_PING_SHIFT) 1245 #define GLB_REQ_PING_SET(reg_val, value) \ 1246 (((reg_val) & ~GLB_REQ_PING_MASK) | (((value) << GLB_REQ_PING_SHIFT) & GLB_REQ_PING_MASK)) 1247 #define GLB_REQ_FIRMWARE_CONFIG_UPDATE_SHIFT 9 1248 #define GLB_REQ_FIRMWARE_CONFIG_UPDATE_MASK \ 1249 (0x1 << GLB_REQ_FIRMWARE_CONFIG_UPDATE_SHIFT) 1250 #define GLB_REQ_FIRMWARE_CONFIG_UPDATE_GET(reg_val) \ 1251 (((reg_val)&GLB_REQ_FIRMWARE_CONFIG_UPDATE_MASK) >> \ 1252 GLB_REQ_FIRMWARE_CONFIG_UPDATE_SHIFT) 1253 #define GLB_REQ_FIRMWARE_CONFIG_UPDATE_SET(reg_val, value) \ 1254 (((reg_val) & ~GLB_REQ_FIRMWARE_CONFIG_UPDATE_MASK) | \ 1255 (((value) << GLB_REQ_FIRMWARE_CONFIG_UPDATE_SHIFT) & \ 1256 GLB_REQ_FIRMWARE_CONFIG_UPDATE_MASK)) 1257 #define GLB_REQ_SLEEP_SHIFT 12 1258 #define GLB_REQ_SLEEP_MASK (0x1 << GLB_REQ_SLEEP_SHIFT) 1259 #define GLB_REQ_SLEEP_GET(reg_val) \ 1260 (((reg_val) & GLB_REQ_SLEEP_MASK) >> GLB_REQ_SLEEP_SHIFT) 1261 #define GLB_REQ_SLEEP_SET(reg_val, value) \ 1262 (((reg_val) & ~GLB_REQ_SLEEP_MASK) | \ 1263 (((value) << GLB_REQ_SLEEP_SHIFT) & GLB_REQ_SLEEP_MASK)) 1264 #define GLB_REQ_INACTIVE_COMPUTE_SHIFT 20 1265 #define GLB_REQ_INACTIVE_COMPUTE_MASK (0x1 << GLB_REQ_INACTIVE_COMPUTE_SHIFT) 1266 #define GLB_REQ_INACTIVE_COMPUTE_GET(reg_val) \ 1267 (((reg_val)&GLB_REQ_INACTIVE_COMPUTE_MASK) >> GLB_REQ_INACTIVE_COMPUTE_SHIFT) 1268 #define GLB_REQ_INACTIVE_COMPUTE_SET(reg_val, value) \ 1269 (((reg_val) & ~GLB_REQ_INACTIVE_COMPUTE_MASK) | \ 1270 (((value) << GLB_REQ_INACTIVE_COMPUTE_SHIFT) & GLB_REQ_INACTIVE_COMPUTE_MASK)) 1271 #define GLB_REQ_INACTIVE_FRAGMENT_SHIFT 21 1272 #define GLB_REQ_INACTIVE_FRAGMENT_MASK (0x1 << GLB_REQ_INACTIVE_FRAGMENT_SHIFT) 1273 #define GLB_REQ_INACTIVE_FRAGMENT_GET(reg_val) \ 1274 (((reg_val)&GLB_REQ_INACTIVE_FRAGMENT_MASK) >> GLB_REQ_INACTIVE_FRAGMENT_SHIFT) 1275 #define GLB_REQ_INACTIVE_FRAGMENT_SET(reg_val, value) \ 1276 (((reg_val) & ~GLB_REQ_INACTIVE_FRAGMENT_MASK) | \ 1277 (((value) << GLB_REQ_INACTIVE_FRAGMENT_SHIFT) & GLB_REQ_INACTIVE_FRAGMENT_MASK)) 1278 #define GLB_REQ_INACTIVE_TILER_SHIFT 22 1279 #define GLB_REQ_INACTIVE_TILER_MASK (0x1 << GLB_REQ_INACTIVE_TILER_SHIFT) 1280 #define GLB_REQ_INACTIVE_TILER_GET(reg_val) (((reg_val)&GLB_REQ_INACTIVE_TILER_MASK) >> GLB_REQ_INACTIVE_TILER_SHIFT) 1281 #define GLB_REQ_INACTIVE_TILER_SET(reg_val, value) \ 1282 (((reg_val) & ~GLB_REQ_INACTIVE_TILER_MASK) | \ 1283 (((value) << GLB_REQ_INACTIVE_TILER_SHIFT) & GLB_REQ_INACTIVE_TILER_MASK)) 1284 #define GLB_REQ_PROTM_EXIT_SHIFT 23 1285 #define GLB_REQ_PROTM_EXIT_MASK (0x1 << GLB_REQ_PROTM_EXIT_SHIFT) 1286 #define GLB_REQ_PROTM_EXIT_GET(reg_val) (((reg_val)&GLB_REQ_PROTM_EXIT_MASK) >> GLB_REQ_PROTM_EXIT_SHIFT) 1287 #define GLB_REQ_PROTM_EXIT_SET(reg_val, value) \ 1288 (((reg_val) & ~GLB_REQ_PROTM_EXIT_MASK) | (((value) << GLB_REQ_PROTM_EXIT_SHIFT) & GLB_REQ_PROTM_EXIT_MASK)) 1289 #define GLB_REQ_PRFCNT_THRESHOLD_SHIFT 24 1290 #define GLB_REQ_PRFCNT_THRESHOLD_MASK (0x1 << GLB_REQ_PRFCNT_THRESHOLD_SHIFT) 1291 #define GLB_REQ_PRFCNT_THRESHOLD_GET(reg_val) \ 1292 (((reg_val)&GLB_REQ_PRFCNT_THRESHOLD_MASK) >> \ 1293 GLB_REQ_PRFCNT_THRESHOLD_SHIFT) 1294 #define GLB_REQ_PRFCNT_THRESHOLD_SET(reg_val, value) \ 1295 (((reg_val) & ~GLB_REQ_PRFCNT_THRESHOLD_MASK) | \ 1296 (((value) << GLB_REQ_PRFCNT_THRESHOLD_SHIFT) & \ 1297 GLB_REQ_PRFCNT_THRESHOLD_MASK)) 1298 #define GLB_REQ_PRFCNT_OVERFLOW_SHIFT 25 1299 #define GLB_REQ_PRFCNT_OVERFLOW_MASK (0x1 << GLB_REQ_PRFCNT_OVERFLOW_SHIFT) 1300 #define GLB_REQ_PRFCNT_OVERFLOW_GET(reg_val) \ 1301 (((reg_val)&GLB_REQ_PRFCNT_OVERFLOW_MASK) >> \ 1302 GLB_REQ_PRFCNT_OVERFLOW_SHIFT) 1303 #define GLB_REQ_PRFCNT_OVERFLOW_SET(reg_val, value) \ 1304 (((reg_val) & ~GLB_REQ_PRFCNT_OVERFLOW_MASK) | \ 1305 (((value) << GLB_REQ_PRFCNT_OVERFLOW_SHIFT) & \ 1306 GLB_REQ_PRFCNT_OVERFLOW_MASK)) 1307 #define GLB_REQ_DEBUG_CSF_REQ_SHIFT 30 1308 #define GLB_REQ_DEBUG_CSF_REQ_MASK (0x1 << GLB_REQ_DEBUG_CSF_REQ_SHIFT) 1309 #define GLB_REQ_DEBUG_CSF_REQ_GET(reg_val) (((reg_val)&GLB_REQ_DEBUG_CSF_REQ_MASK) >> GLB_REQ_DEBUG_CSF_REQ_SHIFT) 1310 #define GLB_REQ_DEBUG_CSF_REQ_SET(reg_val, value) \ 1311 (((reg_val) & ~GLB_REQ_DEBUG_CSF_REQ_MASK) | \ 1312 (((value) << GLB_REQ_DEBUG_CSF_REQ_SHIFT) & GLB_REQ_DEBUG_CSF_REQ_MASK)) 1313 #define GLB_REQ_DEBUG_HOST_REQ_SHIFT 31 1314 #define GLB_REQ_DEBUG_HOST_REQ_MASK (0x1 << GLB_REQ_DEBUG_HOST_REQ_SHIFT) 1315 #define GLB_REQ_DEBUG_HOST_REQ_GET(reg_val) (((reg_val)&GLB_REQ_DEBUG_HOST_REQ_MASK) >> GLB_REQ_DEBUG_HOST_REQ_SHIFT) 1316 #define GLB_REQ_DEBUG_HOST_REQ_SET(reg_val, value) \ 1317 (((reg_val) & ~GLB_REQ_DEBUG_HOST_REQ_MASK) | \ 1318 (((value) << GLB_REQ_DEBUG_HOST_REQ_SHIFT) & GLB_REQ_DEBUG_HOST_REQ_MASK)) 1319 1320 /* GLB_ACK_IRQ_MASK register */ 1321 #define GLB_ACK_IRQ_MASK_HALT_SHIFT 0 1322 #define GLB_ACK_IRQ_MASK_HALT_MASK (0x1 << GLB_ACK_IRQ_MASK_HALT_SHIFT) 1323 #define GLB_ACK_IRQ_MASK_HALT_GET(reg_val) (((reg_val)&GLB_ACK_IRQ_MASK_HALT_MASK) >> GLB_ACK_IRQ_MASK_HALT_SHIFT) 1324 #define GLB_ACK_IRQ_MASK_HALT_SET(reg_val, value) \ 1325 (((reg_val) & ~GLB_ACK_IRQ_MASK_HALT_MASK) | \ 1326 (((value) << GLB_ACK_IRQ_MASK_HALT_SHIFT) & GLB_ACK_IRQ_MASK_HALT_MASK)) 1327 #define GLB_ACK_IRQ_MASK_CFG_PROGRESS_TIMER_SHIFT 1 1328 #define GLB_ACK_IRQ_MASK_CFG_PROGRESS_TIMER_MASK (0x1 << GLB_ACK_IRQ_MASK_CFG_PROGRESS_TIMER_SHIFT) 1329 #define GLB_ACK_IRQ_MASK_CFG_PROGRESS_TIMER_GET(reg_val) \ 1330 (((reg_val)&GLB_ACK_IRQ_MASK_CFG_PROGRESS_TIMER_MASK) >> GLB_ACK_IRQ_MASK_CFG_PROGRESS_TIMER_SHIFT) 1331 #define GLB_ACK_IRQ_MASK_CFG_PROGRESS_TIMER_SET(reg_val, value) \ 1332 (((reg_val) & ~GLB_ACK_IRQ_MASK_CFG_PROGRESS_TIMER_MASK) | \ 1333 (((value) << GLB_ACK_IRQ_MASK_CFG_PROGRESS_TIMER_SHIFT) & GLB_ACK_IRQ_MASK_CFG_PROGRESS_TIMER_MASK)) 1334 #define GLB_ACK_IRQ_MASK_CFG_ALLOC_EN_SHIFT 2 1335 #define GLB_ACK_IRQ_MASK_CFG_ALLOC_EN_MASK (0x1 << GLB_ACK_IRQ_MASK_CFG_ALLOC_EN_SHIFT) 1336 #define GLB_ACK_IRQ_MASK_CFG_ALLOC_EN_GET(reg_val) \ 1337 (((reg_val)&GLB_ACK_IRQ_MASK_CFG_ALLOC_EN_MASK) >> GLB_ACK_IRQ_MASK_CFG_ALLOC_EN_SHIFT) 1338 #define GLB_ACK_IRQ_MASK_CFG_ALLOC_EN_SET(reg_val, value) \ 1339 (((reg_val) & ~GLB_ACK_IRQ_MASK_CFG_ALLOC_EN_MASK) | \ 1340 (((value) << GLB_ACK_IRQ_MASK_CFG_ALLOC_EN_SHIFT) & GLB_ACK_IRQ_MASK_CFG_ALLOC_EN_MASK)) 1341 #define GLB_ACK_IRQ_MASK_CFG_PWROFF_TIMER_SHIFT 3 1342 #define GLB_ACK_IRQ_MASK_CFG_PWROFF_TIMER_MASK (0x1 << GLB_ACK_IRQ_MASK_CFG_PWROFF_TIMER_SHIFT) 1343 #define GLB_ACK_IRQ_MASK_CFG_PWROFF_TIMER_GET(reg_val) \ 1344 (((reg_val)&GLB_ACK_IRQ_MASK_CFG_PWROFF_TIMER_MASK) >> GLB_ACK_IRQ_MASK_CFG_PWROFF_TIMER_SHIFT) 1345 #define GLB_ACK_IRQ_MASK_CFG_PWROFF_TIMER_SET(reg_val, value) \ 1346 (((reg_val) & ~GLB_ACK_IRQ_MASK_CFG_PWROFF_TIMER_MASK) | \ 1347 (((value) << GLB_ACK_IRQ_MASK_CFG_PWROFF_TIMER_SHIFT) & GLB_ACK_IRQ_MASK_CFG_PWROFF_TIMER_MASK)) 1348 #define GLB_ACK_IRQ_MASK_PROTM_ENTER_SHIFT 4 1349 #define GLB_ACK_IRQ_MASK_PROTM_ENTER_MASK (0x1 << GLB_ACK_IRQ_MASK_PROTM_ENTER_SHIFT) 1350 #define GLB_ACK_IRQ_MASK_PROTM_ENTER_GET(reg_val) \ 1351 (((reg_val)&GLB_ACK_IRQ_MASK_PROTM_ENTER_MASK) >> GLB_ACK_IRQ_MASK_PROTM_ENTER_SHIFT) 1352 #define GLB_ACK_IRQ_MASK_PROTM_ENTER_SET(reg_val, value) \ 1353 (((reg_val) & ~GLB_ACK_IRQ_MASK_PROTM_ENTER_MASK) | \ 1354 (((value) << GLB_ACK_IRQ_MASK_PROTM_ENTER_SHIFT) & GLB_ACK_IRQ_MASK_PROTM_ENTER_MASK)) 1355 #define GLB_ACK_IRQ_MASK_PRFCNT_ENABLE_SHIFT 5 1356 #define GLB_ACK_IRQ_MASK_PRFCNT_ENABLE_MASK (0x1 << GLB_ACK_IRQ_MASK_PRFCNT_ENABLE_SHIFT) 1357 #define GLB_ACK_IRQ_MASK_PRFCNT_ENABLE_GET(reg_val) \ 1358 (((reg_val)&GLB_ACK_IRQ_MASK_PRFCNT_ENABLE_MASK) >> GLB_ACK_IRQ_MASK_PRFCNT_ENABLE_SHIFT) 1359 #define GLB_ACK_IRQ_MASK_PRFCNT_ENABLE_SET(reg_val, value) \ 1360 (((reg_val) & ~GLB_ACK_IRQ_MASK_PRFCNT_ENABLE_MASK) | \ 1361 (((value) << GLB_ACK_IRQ_MASK_PRFCNT_ENABLE_SHIFT) & GLB_ACK_IRQ_MASK_PRFCNT_ENABLE_MASK)) 1362 #define GLB_ACK_IRQ_MASK_PRFCNT_SAMPLE_SHIFT 6 1363 #define GLB_ACK_IRQ_MASK_PRFCNT_SAMPLE_MASK (0x1 << GLB_ACK_IRQ_MASK_PRFCNT_SAMPLE_SHIFT) 1364 #define GLB_ACK_IRQ_MASK_PRFCNT_SAMPLE_GET(reg_val) \ 1365 (((reg_val)&GLB_ACK_IRQ_MASK_PRFCNT_SAMPLE_MASK) >> GLB_ACK_IRQ_MASK_PRFCNT_SAMPLE_SHIFT) 1366 #define GLB_ACK_IRQ_MASK_PRFCNT_SAMPLE_SET(reg_val, value) \ 1367 (((reg_val) & ~GLB_ACK_IRQ_MASK_PRFCNT_SAMPLE_MASK) | \ 1368 (((value) << GLB_ACK_IRQ_MASK_PRFCNT_SAMPLE_SHIFT) & GLB_ACK_IRQ_MASK_PRFCNT_SAMPLE_MASK)) 1369 #define GLB_ACK_IRQ_MASK_COUNTER_ENABLE_SHIFT 7 1370 #define GLB_ACK_IRQ_MASK_COUNTER_ENABLE_MASK (0x1 << GLB_ACK_IRQ_MASK_COUNTER_ENABLE_SHIFT) 1371 #define GLB_ACK_IRQ_MASK_COUNTER_ENABLE_GET(reg_val) \ 1372 (((reg_val)&GLB_ACK_IRQ_MASK_COUNTER_ENABLE_MASK) >> GLB_ACK_IRQ_MASK_COUNTER_ENABLE_SHIFT) 1373 #define GLB_ACK_IRQ_MASK_COUNTER_ENABLE_SET(reg_val, value) \ 1374 (((reg_val) & ~GLB_ACK_IRQ_MASK_COUNTER_ENABLE_MASK) | \ 1375 (((value) << GLB_ACK_IRQ_MASK_COUNTER_ENABLE_SHIFT) & GLB_ACK_IRQ_MASK_COUNTER_ENABLE_MASK)) 1376 #define GLB_ACK_IRQ_MASK_PING_SHIFT 8 1377 #define GLB_ACK_IRQ_MASK_PING_MASK (0x1 << GLB_ACK_IRQ_MASK_PING_SHIFT) 1378 #define GLB_ACK_IRQ_MASK_PING_GET(reg_val) (((reg_val)&GLB_ACK_IRQ_MASK_PING_MASK) >> GLB_ACK_IRQ_MASK_PING_SHIFT) 1379 #define GLB_ACK_IRQ_MASK_PING_SET(reg_val, value) \ 1380 (((reg_val) & ~GLB_ACK_IRQ_MASK_PING_MASK) | \ 1381 (((value) << GLB_ACK_IRQ_MASK_PING_SHIFT) & GLB_ACK_IRQ_MASK_PING_MASK)) 1382 #define GLB_ACK_IRQ_MASK_FIRMWARE_CONFIG_UPDATE_SHIFT 9 1383 #define GLB_ACK_IRQ_MASK_FIRMWARE_CONFIG_UPDATE_MASK \ 1384 (0x1 << GLB_ACK_IRQ_MASK_FIRMWARE_CONFIG_UPDATE_SHIFT) 1385 #define GLB_ACK_IRQ_MASK_FIRMWARE_CONFIG_UPDATE_GET(reg_val) \ 1386 (((reg_val)&GLB_ACK_IRQ_MASK_FIRMWARE_CONFIG_UPDATE_MASK) >> \ 1387 GLB_ACK_IRQ_MASK_FIRMWARE_CONFIG_UPDATE_SHIFT) 1388 #define GLB_ACK_IRQ_MASK_FIRMWARE_CONFIG_UPDATE_SET(reg_val, value) \ 1389 (((reg_val) & ~GLB_ACK_IRQ_MASK_FIRMWARE_CONFIG_UPDATE_MASK) | \ 1390 (((value) << GLB_ACK_IRQ_MASK_FIRMWARE_CONFIG_UPDATE_SHIFT) & \ 1391 GLB_ACK_IRQ_MASK_FIRMWARE_CONFIG_UPDATE_MASK)) 1392 #define GLB_ACK_IRQ_MASK_INACTIVE_COMPUTE_SHIFT 20 1393 #define GLB_ACK_IRQ_MASK_INACTIVE_COMPUTE_MASK (0x1 << GLB_ACK_IRQ_MASK_INACTIVE_COMPUTE_SHIFT) 1394 #define GLB_ACK_IRQ_MASK_INACTIVE_COMPUTE_GET(reg_val) \ 1395 (((reg_val)&GLB_ACK_IRQ_MASK_INACTIVE_COMPUTE_MASK) >> GLB_ACK_IRQ_MASK_INACTIVE_COMPUTE_SHIFT) 1396 #define GLB_ACK_IRQ_MASK_INACTIVE_COMPUTE_SET(reg_val, value) \ 1397 (((reg_val) & ~GLB_ACK_IRQ_MASK_INACTIVE_COMPUTE_MASK) | \ 1398 (((value) << GLB_ACK_IRQ_MASK_INACTIVE_COMPUTE_SHIFT) & GLB_ACK_IRQ_MASK_INACTIVE_COMPUTE_MASK)) 1399 #define GLB_ACK_IRQ_MASK_INACTIVE_FRAGMENT_SHIFT 21 1400 #define GLB_ACK_IRQ_MASK_INACTIVE_FRAGMENT_MASK (0x1 << GLB_ACK_IRQ_MASK_INACTIVE_FRAGMENT_SHIFT) 1401 #define GLB_ACK_IRQ_MASK_INACTIVE_FRAGMENT_GET(reg_val) \ 1402 (((reg_val)&GLB_ACK_IRQ_MASK_INACTIVE_FRAGMENT_MASK) >> GLB_ACK_IRQ_MASK_INACTIVE_FRAGMENT_SHIFT) 1403 #define GLB_ACK_IRQ_MASK_INACTIVE_FRAGMENT_SET(reg_val, value) \ 1404 (((reg_val) & ~GLB_ACK_IRQ_MASK_INACTIVE_FRAGMENT_MASK) | \ 1405 (((value) << GLB_ACK_IRQ_MASK_INACTIVE_FRAGMENT_SHIFT) & GLB_ACK_IRQ_MASK_INACTIVE_FRAGMENT_MASK)) 1406 #define GLB_ACK_IRQ_MASK_INACTIVE_TILER_SHIFT 22 1407 #define GLB_ACK_IRQ_MASK_INACTIVE_TILER_MASK (0x1 << GLB_ACK_IRQ_MASK_INACTIVE_TILER_SHIFT) 1408 #define GLB_ACK_IRQ_MASK_INACTIVE_TILER_GET(reg_val) \ 1409 (((reg_val)&GLB_ACK_IRQ_MASK_INACTIVE_TILER_MASK) >> GLB_ACK_IRQ_MASK_INACTIVE_TILER_SHIFT) 1410 #define GLB_ACK_IRQ_MASK_INACTIVE_TILER_SET(reg_val, value) \ 1411 (((reg_val) & ~GLB_ACK_IRQ_MASK_INACTIVE_TILER_MASK) | \ 1412 (((value) << GLB_ACK_IRQ_MASK_INACTIVE_TILER_SHIFT) & GLB_ACK_IRQ_MASK_INACTIVE_TILER_MASK)) 1413 #define GLB_ACK_IRQ_MASK_PROTM_EXIT_SHIFT 23 1414 #define GLB_ACK_IRQ_MASK_PROTM_EXIT_MASK (0x1 << GLB_ACK_IRQ_MASK_PROTM_EXIT_SHIFT) 1415 #define GLB_ACK_IRQ_MASK_PROTM_EXIT_GET(reg_val) \ 1416 (((reg_val)&GLB_ACK_IRQ_MASK_PROTM_EXIT_MASK) >> GLB_ACK_IRQ_MASK_PROTM_EXIT_SHIFT) 1417 #define GLB_ACK_IRQ_MASK_PROTM_EXIT_SET(reg_val, value) \ 1418 (((reg_val) & ~GLB_ACK_IRQ_MASK_PROTM_EXIT_MASK) | \ 1419 (((value) << GLB_ACK_IRQ_MASK_PROTM_EXIT_SHIFT) & GLB_ACK_IRQ_MASK_PROTM_EXIT_MASK)) 1420 #define GLB_ACK_IRQ_MASK_PRFCNT_THRESHOLD_SHIFT 24 1421 #define GLB_ACK_IRQ_MASK_PRFCNT_THRESHOLD_MASK \ 1422 (0x1 << GLB_ACK_IRQ_MASK_PRFCNT_THRESHOLD_SHIFT) 1423 #define GLB_ACK_IRQ_MASK_PRFCNT_THRESHOLD_GET(reg_val) \ 1424 (((reg_val)&GLB_ACK_IRQ_MASK_PRFCNT_THRESHOLD_MASK) >> \ 1425 GLB_ACK_IRQ_MASK_PRFCNT_THRESHOLD_SHIFT) 1426 #define GLB_ACK_IRQ_MASK_PRFCNT_THRESHOLD_SET(reg_val, value) \ 1427 (((reg_val) & ~GLB_ACK_IRQ_MASK_PRFCNT_THRESHOLD_MASK) | \ 1428 (((value) << GLB_ACK_IRQ_MASK_PRFCNT_THRESHOLD_SHIFT) & \ 1429 GLB_ACK_IRQ_MASK_PRFCNT_THRESHOLD_MASK)) 1430 #define GLB_ACK_IRQ_MASK_PRFCNT_OVERFLOW_SHIFT 25 1431 #define GLB_ACK_IRQ_MASK_PRFCNT_OVERFLOW_MASK \ 1432 (0x1 << GLB_ACK_IRQ_MASK_PRFCNT_OVERFLOW_SHIFT) 1433 #define GLB_ACK_IRQ_MASK_PRFCNT_OVERFLOW_GET(reg_val) \ 1434 (((reg_val)&GLB_ACK_IRQ_MASK_PRFCNT_OVERFLOW_MASK) >> \ 1435 GLB_ACK_IRQ_MASK_PRFCNT_OVERFLOW_SHIFT) 1436 #define GLB_ACK_IRQ_MASK_PRFCNT_OVERFLOW_SET(reg_val, value) \ 1437 (((reg_val) & ~GLB_ACK_IRQ_MASK_PRFCNT_OVERFLOW_MASK) | \ 1438 (((value) << GLB_ACK_IRQ_MASK_PRFCNT_OVERFLOW_SHIFT) & \ 1439 GLB_ACK_IRQ_MASK_PRFCNT_OVERFLOW_MASK)) 1440 #define GLB_ACK_IRQ_MASK_DEBUG_CSF_REQ_SHIFT 30 1441 #define GLB_ACK_IRQ_MASK_DEBUG_CSF_REQ_MASK (0x1 << GLB_ACK_IRQ_MASK_DEBUG_CSF_REQ_SHIFT) 1442 #define GLB_ACK_IRQ_MASK_DEBUG_CSF_REQ_GET(reg_val) \ 1443 (((reg_val)&GLB_ACK_IRQ_MASK_DEBUG_CSF_REQ_MASK) >> GLB_ACK_IRQ_MASK_DEBUG_CSF_REQ_SHIFT) 1444 #define GLB_ACK_IRQ_MASK_DEBUG_CSF_REQ_SET(reg_val, value) \ 1445 (((reg_val) & ~GLB_ACK_IRQ_MASK_DEBUG_CSF_REQ_MASK) | \ 1446 (((value) << GLB_ACK_IRQ_MASK_DEBUG_CSF_REQ_SHIFT) & GLB_ACK_IRQ_MASK_DEBUG_CSF_REQ_MASK)) 1447 #define GLB_ACK_IRQ_MASK_DEBUG_HOST_REQ_SHIFT 31 1448 #define GLB_ACK_IRQ_MASK_DEBUG_HOST_REQ_MASK (0x1 << GLB_ACK_IRQ_MASK_DEBUG_HOST_REQ_SHIFT) 1449 #define GLB_ACK_IRQ_MASK_DEBUG_HOST_REQ_GET(reg_val) \ 1450 (((reg_val)&GLB_ACK_IRQ_MASK_DEBUG_HOST_REQ_MASK) >> GLB_ACK_IRQ_MASK_DEBUG_HOST_REQ_SHIFT) 1451 #define GLB_ACK_IRQ_MASK_DEBUG_HOST_REQ_SET(reg_val, value) \ 1452 (((reg_val) & ~GLB_ACK_IRQ_MASK_DEBUG_HOST_REQ_MASK) | \ 1453 (((value) << GLB_ACK_IRQ_MASK_DEBUG_HOST_REQ_SHIFT) & GLB_ACK_IRQ_MASK_DEBUG_HOST_REQ_MASK)) 1454 1455 /* GLB_PROGRESS_TIMER register */ 1456 #define GLB_PROGRESS_TIMER_TIMEOUT_SHIFT 0 1457 #define GLB_PROGRESS_TIMER_TIMEOUT_MASK (0xFFFFFFFF << GLB_PROGRESS_TIMER_TIMEOUT_SHIFT) 1458 #define GLB_PROGRESS_TIMER_TIMEOUT_GET(reg_val) \ 1459 (((reg_val)&GLB_PROGRESS_TIMER_TIMEOUT_MASK) >> GLB_PROGRESS_TIMER_TIMEOUT_SHIFT) 1460 #define GLB_PROGRESS_TIMER_TIMEOUT_SET(reg_val, value) \ 1461 (((reg_val) & ~GLB_PROGRESS_TIMER_TIMEOUT_MASK) | \ 1462 (((value) << GLB_PROGRESS_TIMER_TIMEOUT_SHIFT) & GLB_PROGRESS_TIMER_TIMEOUT_MASK)) 1463 1464 /* GLB_PWROFF_TIMER register */ 1465 #define GLB_PWROFF_TIMER_TIMEOUT_SHIFT 0 1466 #define GLB_PWROFF_TIMER_TIMEOUT_MASK (0x7FFFFFFF << GLB_PWROFF_TIMER_TIMEOUT_SHIFT) 1467 #define GLB_PWROFF_TIMER_TIMEOUT_GET(reg_val) \ 1468 (((reg_val)&GLB_PWROFF_TIMER_TIMEOUT_MASK) >> GLB_PWROFF_TIMER_TIMEOUT_SHIFT) 1469 #define GLB_PWROFF_TIMER_TIMEOUT_SET(reg_val, value) \ 1470 (((reg_val) & ~GLB_PWROFF_TIMER_TIMEOUT_MASK) | \ 1471 (((value) << GLB_PWROFF_TIMER_TIMEOUT_SHIFT) & GLB_PWROFF_TIMER_TIMEOUT_MASK)) 1472 #define GLB_PWROFF_TIMER_TIMER_SOURCE_SHIFT 31 1473 #define GLB_PWROFF_TIMER_TIMER_SOURCE_MASK (0x1 << GLB_PWROFF_TIMER_TIMER_SOURCE_SHIFT) 1474 #define GLB_PWROFF_TIMER_TIMER_SOURCE_GET(reg_val) \ 1475 (((reg_val)&GLB_PWROFF_TIMER_TIMER_SOURCE_MASK) >> GLB_PWROFF_TIMER_TIMER_SOURCE_SHIFT) 1476 #define GLB_PWROFF_TIMER_TIMER_SOURCE_SET(reg_val, value) \ 1477 (((reg_val) & ~GLB_PWROFF_TIMER_TIMER_SOURCE_MASK) | \ 1478 (((value) << GLB_PWROFF_TIMER_TIMER_SOURCE_SHIFT) & GLB_PWROFF_TIMER_TIMER_SOURCE_MASK)) 1479 /* GLB_PWROFF_TIMER_TIMER_SOURCE values */ 1480 #define GLB_PWROFF_TIMER_TIMER_SOURCE_SYSTEM_TIMESTAMP 0x0 1481 #define GLB_PWROFF_TIMER_TIMER_SOURCE_GPU_COUNTER 0x1 1482 /* End of GLB_PWROFF_TIMER_TIMER_SOURCE values */ 1483 1484 /* GLB_ALLOC_EN register */ 1485 #define GLB_ALLOC_EN_MASK_SHIFT 0 1486 #define GLB_ALLOC_EN_MASK_MASK (GPU_ULL(0xFFFFFFFFFFFFFFFF) << GLB_ALLOC_EN_MASK_SHIFT) 1487 #define GLB_ALLOC_EN_MASK_GET(reg_val) (((reg_val)&GLB_ALLOC_EN_MASK_MASK) >> GLB_ALLOC_EN_MASK_SHIFT) 1488 #define GLB_ALLOC_EN_MASK_SET(reg_val, value) \ 1489 (((reg_val) & ~GLB_ALLOC_EN_MASK_MASK) | (((value) << GLB_ALLOC_EN_MASK_SHIFT) & GLB_ALLOC_EN_MASK_MASK)) 1490 1491 /* GLB_OUTPUT_BLOCK register set definitions */ 1492 1493 /* GLB_ACK register */ 1494 #define GLB_ACK_CFG_PROGRESS_TIMER_SHIFT 1 1495 #define GLB_ACK_CFG_PROGRESS_TIMER_MASK (0x1 << GLB_ACK_CFG_PROGRESS_TIMER_SHIFT) 1496 #define GLB_ACK_CFG_PROGRESS_TIMER_GET(reg_val) \ 1497 (((reg_val)&GLB_ACK_CFG_PROGRESS_TIMER_MASK) >> GLB_ACK_CFG_PROGRESS_TIMER_SHIFT) 1498 #define GLB_ACK_CFG_PROGRESS_TIMER_SET(reg_val, value) \ 1499 (((reg_val) & ~GLB_ACK_CFG_PROGRESS_TIMER_MASK) | \ 1500 (((value) << GLB_ACK_CFG_PROGRESS_TIMER_SHIFT) & GLB_ACK_CFG_PROGRESS_TIMER_MASK)) 1501 #define GLB_ACK_CFG_ALLOC_EN_SHIFT 2 1502 #define GLB_ACK_CFG_ALLOC_EN_MASK (0x1 << GLB_ACK_CFG_ALLOC_EN_SHIFT) 1503 #define GLB_ACK_CFG_ALLOC_EN_GET(reg_val) (((reg_val)&GLB_ACK_CFG_ALLOC_EN_MASK) >> GLB_ACK_CFG_ALLOC_EN_SHIFT) 1504 #define GLB_ACK_CFG_ALLOC_EN_SET(reg_val, value) \ 1505 (((reg_val) & ~GLB_ACK_CFG_ALLOC_EN_MASK) | (((value) << GLB_ACK_CFG_ALLOC_EN_SHIFT) & GLB_ACK_CFG_ALLOC_EN_MASK)) 1506 /* End of GLB_OUTPUT_BLOCK register set definitions */ 1507 1508 /* The following register and fields are for headers before 10.x.7/11.x.4 */ 1509 #define GLB_REQ_IDLE_ENABLE_SHIFT (10) 1510 #define GLB_REQ_REQ_IDLE_ENABLE (1 << GLB_REQ_IDLE_ENABLE_SHIFT) 1511 #define GLB_REQ_REQ_IDLE_DISABLE (0 << GLB_REQ_IDLE_ENABLE_SHIFT) 1512 #define GLB_REQ_IDLE_ENABLE_MASK (0x1 << GLB_REQ_IDLE_ENABLE_SHIFT) 1513 #define GLB_REQ_IDLE_DISABLE_MASK (0x1 << GLB_REQ_IDLE_ENABLE_SHIFT) 1514 #define GLB_REQ_IDLE_EVENT_SHIFT (26) 1515 #define GLB_REQ_IDLE_EVENT_MASK (0x1 << GLB_REQ_IDLE_EVENT_SHIFT) 1516 #define GLB_ACK_IDLE_ENABLE_SHIFT (10) 1517 #define GLB_ACK_ACK_IDLE_ENABLE (1 << GLB_ACK_IDLE_ENABLE_SHIFT) 1518 #define GLB_ACK_ACK_IDLE_DISABLE (0 << GLB_ACK_IDLE_ENABLE_SHIFT) 1519 #define GLB_ACK_IDLE_ENABLE_MASK (0x1 << GLB_ACK_IDLE_ENABLE_SHIFT) 1520 #define GLB_ACK_IDLE_EVENT_SHIFT (26) 1521 #define GLB_ACK_IDLE_EVENT_MASK (0x1 << GLB_REQ_IDLE_EVENT_SHIFT) 1522 1523 #define GLB_ACK_IRQ_MASK_IDLE_EVENT_SHIFT (26) 1524 #define GLB_ACK_IRQ_MASK_IDLE_EVENT_MASK (0x1 << GLB_ACK_IRQ_MASK_IDLE_EVENT_SHIFT) 1525 1526 #define GLB_ACK_IRQ_MASK_IDLE_ENABLE_SHIFT GPU_U(10) 1527 #define GLB_ACK_IRQ_MASK_IDLE_ENABLE_MASK (GPU_U(0x1) << GLB_ACK_IRQ_MASK_IDLE_ENABLE_SHIFT) 1528 1529 #define GLB_IDLE_TIMER (0x0080) 1530 /* GLB_IDLE_TIMER register */ 1531 #define GLB_IDLE_TIMER_TIMEOUT_SHIFT (0) 1532 #define GLB_IDLE_TIMER_TIMEOUT_MASK ((0x7FFFFFFF) << GLB_IDLE_TIMER_TIMEOUT_SHIFT) 1533 #define GLB_IDLE_TIMER_TIMEOUT_GET(reg_val) (((reg_val)&GLB_IDLE_TIMER_TIMEOUT_MASK) >> GLB_IDLE_TIMER_TIMEOUT_SHIFT) 1534 #define GLB_IDLE_TIMER_TIMEOUT_SET(reg_val, value) \ 1535 (((reg_val) & ~GLB_IDLE_TIMER_TIMEOUT_MASK) | \ 1536 (((value) << GLB_IDLE_TIMER_TIMEOUT_SHIFT) & GLB_IDLE_TIMER_TIMEOUT_MASK)) 1537 #define GLB_IDLE_TIMER_TIMER_SOURCE_SHIFT (31) 1538 #define GLB_IDLE_TIMER_TIMER_SOURCE_MASK ((0x1) << GLB_IDLE_TIMER_TIMER_SOURCE_SHIFT) 1539 #define GLB_IDLE_TIMER_TIMER_SOURCE_GET(reg_val) \ 1540 (((reg_val)&GLB_IDLE_TIMER_TIMER_SOURCE_MASK) >> GLB_IDLE_TIMER_TIMER_SOURCE_SHIFT) 1541 #define GLB_IDLE_TIMER_TIMER_SOURCE_SET(reg_val, value) \ 1542 (((reg_val) & ~GLB_IDLE_TIMER_TIMER_SOURCE_MASK) | \ 1543 (((value) << GLB_IDLE_TIMER_TIMER_SOURCE_SHIFT) & GLB_IDLE_TIMER_TIMER_SOURCE_MASK)) 1544 /* GLB_IDLE_TIMER_TIMER_SOURCE values */ 1545 #define GLB_IDLE_TIMER_TIMER_SOURCE_SYSTEM_TIMESTAMP 0x0 1546 #define GLB_IDLE_TIMER_TIMER_SOURCE_GPU_COUNTER 0x1 1547 /* End of GLB_IDLE_TIMER_TIMER_SOURCE values */ 1548 1549 /* GLB_INSTR_FEATURES register */ 1550 #define GLB_INSTR_FEATURES_OFFSET_UPDATE_RATE_SHIFT (0) 1551 #define GLB_INSTR_FEATURES_OFFSET_UPDATE_RATE_MASK ((u32)0xF << GLB_INSTR_FEATURES_OFFSET_UPDATE_RATE_SHIFT) 1552 #define GLB_INSTR_FEATURES_OFFSET_UPDATE_RATE_GET(reg_val) \ 1553 (((reg_val)&GLB_INSTR_FEATURES_OFFSET_UPDATE_RATE_MASK) >> GLB_INSTR_FEATURES_OFFSET_UPDATE_RATE_SHIFT) 1554 #define GLB_INSTR_FEATURES_OFFSET_UPDATE_RATE_SET(reg_val, value) \ 1555 (((reg_val) & ~GLB_INSTR_FEATURES_OFFSET_UPDATE_RATE_MASK) | \ 1556 (((value) << GLB_INSTR_FEATURES_OFFSET_UPDATE_RATE_SHIFT) & GLB_INSTR_FEATURES_OFFSET_UPDATE_RATE_MASK)) 1557 #define GLB_INSTR_FEATURES_EVENT_SIZE_MAX_SHIFT (4) 1558 #define GLB_INSTR_FEATURES_EVENT_SIZE_MAX_MASK ((u32)0xF << GLB_INSTR_FEATURES_EVENT_SIZE_MAX_SHIFT) 1559 #define GLB_INSTR_FEATURES_EVENT_SIZE_MAX_GET(reg_val) \ 1560 (((reg_val)&GLB_INSTR_FEATURES_EVENT_SIZE_MAX_MASK) >> GLB_INSTR_FEATURES_EVENT_SIZE_MAX_SHIFT) 1561 #define GLB_INSTR_FEATURES_EVENT_SIZE_MAX_SET(reg_val, value) \ 1562 (((reg_val) & ~GLB_INSTR_FEATURES_EVENT_SIZE_MAX_MASK) | \ 1563 (((value) << GLB_INSTR_FEATURES_EVENT_SIZE_MAX_SHIFT) & GLB_INSTR_FEATURES_EVENT_SIZE_MAX_MASK)) 1564 1565 #define CSG_STATUS_STATE (0x0018) /* CSG state status register */ 1566 /* CSG_STATUS_STATE register */ 1567 #define CSG_STATUS_STATE_IDLE_SHIFT (0) 1568 #define CSG_STATUS_STATE_IDLE_MASK ((0x1) << CSG_STATUS_STATE_IDLE_SHIFT) 1569 #define CSG_STATUS_STATE_IDLE_GET(reg_val) \ 1570 (((reg_val)&CSG_STATUS_STATE_IDLE_MASK) >> CSG_STATUS_STATE_IDLE_SHIFT) 1571 #define CSG_STATUS_STATE_IDLE_SET(reg_val, value) \ 1572 (((reg_val) & ~CSG_STATUS_STATE_IDLE_MASK) | \ 1573 (((value) << CSG_STATUS_STATE_IDLE_SHIFT) & CSG_STATUS_STATE_IDLE_MASK)) 1574 1575 /* GLB_FEATURES_ITER_TRACE_SUPPORTED register */ 1576 #define GLB_FEATURES_ITER_TRACE_SUPPORTED_SHIFT GPU_U(4) 1577 #define GLB_FEATURES_ITER_TRACE_SUPPORTED_MASK \ 1578 (GPU_U(0x1) << GLB_FEATURES_ITER_TRACE_SUPPORTED_SHIFT) 1579 #define GLB_FEATURES_ITER_TRACE_SUPPORTED_GET(reg_val) \ 1580 (((reg_val)&GLB_FEATURES_ITER_TRACE_SUPPORTED_MASK) >> \ 1581 GLB_FEATURES_ITER_TRACE_SUPPORTED_SHIFT) 1582 #define GLB_FEATURES_ITER_TRACE_SUPPORTED_SET(reg_val, value) \ 1583 (((reg_val) & ~GLB_FEATURES_ITER_TRACE_SUPPORTED_MASK) | \ 1584 (((value) << GLB_FEATURES_ITER_TRACE_SUPPORTED_SHIFT) & \ 1585 GLB_FEATURES_ITER_TRACE_SUPPORTED_MASK)) 1586 1587 /* GLB_REQ_ITER_TRACE_ENABLE register */ 1588 #define GLB_REQ_ITER_TRACE_ENABLE_SHIFT GPU_U(11) 1589 #define GLB_REQ_ITER_TRACE_ENABLE_MASK \ 1590 (GPU_U(0x1) << GLB_REQ_ITER_TRACE_ENABLE_SHIFT) 1591 #define GLB_REQ_ITER_TRACE_ENABLE_GET(reg_val) \ 1592 (((reg_val)&GLB_REQ_ITER_TRACE_ENABLE_MASK) >> \ 1593 GLB_REQ_ITER_TRACE_ENABLE_SHIFT) 1594 #define GLB_REQ_ITER_TRACE_ENABLE_SET(reg_val, value) \ 1595 (((reg_val) & ~GLB_REQ_ITER_TRACE_ENABLE_MASK) | \ 1596 (((value) << GLB_REQ_ITER_TRACE_ENABLE_SHIFT) & \ 1597 GLB_REQ_ITER_TRACE_ENABLE_MASK)) 1598 1599 /* GLB_PRFCNT_CONFIG register */ 1600 #define GLB_PRFCNT_CONFIG_SIZE_SHIFT (0) 1601 #define GLB_PRFCNT_CONFIG_SIZE_MASK (0xFF << GLB_PRFCNT_CONFIG_SIZE_SHIFT) 1602 #define GLB_PRFCNT_CONFIG_SIZE_GET(reg_val) \ 1603 (((reg_val)&GLB_PRFCNT_CONFIG_SIZE_MASK) >> GLB_PRFCNT_CONFIG_SIZE_SHIFT) 1604 #define GLB_PRFCNT_CONFIG_SIZE_SET(reg_val, value) \ 1605 (((reg_val) & ~GLB_PRFCNT_CONFIG_SIZE_MASK) | \ 1606 (((value) << GLB_PRFCNT_CONFIG_SIZE_SHIFT) & GLB_PRFCNT_CONFIG_SIZE_MASK)) 1607 #define GLB_PRFCNT_CONFIG_SET_SELECT_SHIFT GPU_U(8) 1608 #define GLB_PRFCNT_CONFIG_SET_SELECT_MASK (GPU_U(0x3) << GLB_PRFCNT_CONFIG_SET_SELECT_SHIFT) 1609 #define GLB_PRFCNT_CONFIG_SET_SELECT_GET(reg_val) \ 1610 (((reg_val)&GLB_PRFCNT_CONFIG_SET_SELECT_MASK) >> GLB_PRFCNT_CONFIG_SET_SELECT_SHIFT) 1611 #define GLB_PRFCNT_CONFIG_SET_SELECT_SET(reg_val, value) \ 1612 (((reg_val) & ~GLB_PRFCNT_CONFIG_SET_SELECT_MASK) | \ 1613 (((value) << GLB_PRFCNT_CONFIG_SET_SELECT_SHIFT) & GLB_PRFCNT_CONFIG_SET_SELECT_MASK)) 1614 1615 /* GLB_PRFCNT_SIZE register */ 1616 #define GLB_PRFCNT_SIZE_HARDWARE_SIZE_SET_MOD(value) ((value) >> 8) 1617 #define GLB_PRFCNT_SIZE_HARDWARE_SIZE_GET_MOD(value) ((value) << 8) 1618 #define GLB_PRFCNT_SIZE_HARDWARE_SIZE_SHIFT GPU_U(0) 1619 #define GLB_PRFCNT_SIZE_HARDWARE_SIZE_MASK (GPU_U(0xFFFF) << GLB_PRFCNT_SIZE_HARDWARE_SIZE_SHIFT) 1620 #define GLB_PRFCNT_SIZE_HARDWARE_SIZE_GET(reg_val) \ 1621 (GLB_PRFCNT_SIZE_HARDWARE_SIZE_GET_MOD(((reg_val)&GLB_PRFCNT_SIZE_HARDWARE_SIZE_MASK) >> \ 1622 GLB_PRFCNT_SIZE_HARDWARE_SIZE_SHIFT)) 1623 #define GLB_PRFCNT_SIZE_HARDWARE_SIZE_SET(reg_val, value) \ 1624 (((reg_val) & ~GLB_PRFCNT_SIZE_HARDWARE_SIZE_MASK) | \ 1625 ((GLB_PRFCNT_SIZE_HARDWARE_SIZE_SET_MOD(value) << GLB_PRFCNT_SIZE_HARDWARE_SIZE_SHIFT) & \ 1626 GLB_PRFCNT_SIZE_HARDWARE_SIZE_MASK)) 1627 #define GLB_PRFCNT_SIZE_FIRMWARE_SIZE_SET_MOD(value) ((value) >> 8) 1628 #define GLB_PRFCNT_SIZE_FIRMWARE_SIZE_GET_MOD(value) ((value) << 8) 1629 #define GLB_PRFCNT_SIZE_FIRMWARE_SIZE_SHIFT GPU_U(16) 1630 #define GLB_PRFCNT_SIZE_FIRMWARE_SIZE_MASK (GPU_U(0xFFFF) << GLB_PRFCNT_SIZE_FIRMWARE_SIZE_SHIFT) 1631 #define GLB_PRFCNT_SIZE_FIRMWARE_SIZE_GET(reg_val) \ 1632 (GLB_PRFCNT_SIZE_FIRMWARE_SIZE_GET_MOD(((reg_val)&GLB_PRFCNT_SIZE_FIRMWARE_SIZE_MASK) >> \ 1633 GLB_PRFCNT_SIZE_FIRMWARE_SIZE_SHIFT)) 1634 #define GLB_PRFCNT_SIZE_FIRMWARE_SIZE_SET(reg_val, value) \ 1635 (((reg_val) & ~GLB_PRFCNT_SIZE_FIRMWARE_SIZE_MASK) | \ 1636 ((GLB_PRFCNT_SIZE_FIRMWARE_SIZE_SET_MOD(value) << GLB_PRFCNT_SIZE_FIRMWARE_SIZE_SHIFT) & \ 1637 GLB_PRFCNT_SIZE_FIRMWARE_SIZE_MASK)) 1638 1639 /* GLB_DEBUG_REQ register */ 1640 #define GLB_DEBUG_REQ_DEBUG_RUN_SHIFT GPU_U(23) 1641 #define GLB_DEBUG_REQ_DEBUG_RUN_MASK (GPU_U(0x1) << GLB_DEBUG_REQ_DEBUG_RUN_SHIFT) 1642 #define GLB_DEBUG_REQ_DEBUG_RUN_GET(reg_val) \ 1643 (((reg_val)&GLB_DEBUG_REQ_DEBUG_RUN_MASK) >> GLB_DEBUG_REQ_DEBUG_RUN_SHIFT) 1644 #define GLB_DEBUG_REQ_DEBUG_RUN_SET(reg_val, value) \ 1645 (((reg_val) & ~GLB_DEBUG_REQ_DEBUG_RUN_MASK) | \ 1646 (((value) << GLB_DEBUG_REQ_DEBUG_RUN_SHIFT) & GLB_DEBUG_REQ_DEBUG_RUN_MASK)) 1647 1648 #define GLB_DEBUG_REQ_RUN_MODE_SHIFT GPU_U(24) 1649 #define GLB_DEBUG_REQ_RUN_MODE_MASK (GPU_U(0xFF) << GLB_DEBUG_REQ_RUN_MODE_SHIFT) 1650 #define GLB_DEBUG_REQ_RUN_MODE_GET(reg_val) \ 1651 (((reg_val)&GLB_DEBUG_REQ_RUN_MODE_MASK) >> GLB_DEBUG_REQ_RUN_MODE_SHIFT) 1652 #define GLB_DEBUG_REQ_RUN_MODE_SET(reg_val, value) \ 1653 (((reg_val) & ~GLB_DEBUG_REQ_RUN_MODE_MASK) | \ 1654 (((value) << GLB_DEBUG_REQ_RUN_MODE_SHIFT) & GLB_DEBUG_REQ_RUN_MODE_MASK)) 1655 1656 /* GLB_DEBUG_ACK register */ 1657 #define GLB_DEBUG_ACK_DEBUG_RUN_SHIFT GPU_U(23) 1658 #define GLB_DEBUG_ACK_DEBUG_RUN_MASK (GPU_U(0x1) << GLB_DEBUG_ACK_DEBUG_RUN_SHIFT) 1659 #define GLB_DEBUG_ACK_DEBUG_RUN_GET(reg_val) \ 1660 (((reg_val)&GLB_DEBUG_ACK_DEBUG_RUN_MASK) >> GLB_DEBUG_ACK_DEBUG_RUN_SHIFT) 1661 #define GLB_DEBUG_ACK_DEBUG_RUN_SET(reg_val, value) \ 1662 (((reg_val) & ~GLB_DEBUG_ACK_DEBUG_RUN_MASK) | \ 1663 (((value) << GLB_DEBUG_ACK_DEBUG_RUN_SHIFT) & GLB_DEBUG_ACK_DEBUG_RUN_MASK)) 1664 1665 #define GLB_DEBUG_ACK_RUN_MODE_SHIFT GPU_U(24) 1666 #define GLB_DEBUG_ACK_RUN_MODE_MASK (GPU_U(0xFF) << GLB_DEBUG_ACK_RUN_MODE_SHIFT) 1667 #define GLB_DEBUG_ACK_RUN_MODE_GET(reg_val) \ 1668 (((reg_val)&GLB_DEBUG_ACK_RUN_MODE_MASK) >> GLB_DEBUG_ACK_RUN_MODE_SHIFT) 1669 #define GLB_DEBUG_ACK_RUN_MODE_SET(reg_val, value) \ 1670 (((reg_val) & ~GLB_DEBUG_ACK_RUN_MODE_MASK) | \ 1671 (((value) << GLB_DEBUG_ACK_RUN_MODE_SHIFT) & GLB_DEBUG_ACK_RUN_MODE_MASK)) 1672 1673 /* RUN_MODE values */ 1674 #define GLB_DEBUG_RUN_MODE_TYPE_NOP 0x0 1675 #define GLB_DEBUG_RUN_MODE_TYPE_CORE_DUMP 0x1 1676 /* End of RUN_MODE values */ 1677 1678 #endif /* _KBASE_CSF_REGISTERS_H_ */ 1679