1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * SiliconBackplane Chipcommon core hardware definitions. 4 * 5 * The chipcommon core provides chip identification, SB control, 6 * JTAG, 0/1/2 UARTs, clock frequency control, a watchdog interrupt timer, 7 * GPIO interface, extbus, and support for serial and parallel flashes. 8 * 9 * $Id: sbchipc.h 657872 2016-09-02 22:17:34Z $ 10 * 11 * Copyright (C) 1999-2017, Broadcom Corporation 12 * 13 * Unless you and Broadcom execute a separate written software license 14 * agreement governing use of this software, this software is licensed to you 15 * under the terms of the GNU General Public License version 2 (the "GPL"), 16 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 17 * following added to such license: 18 * 19 * As a special exception, the copyright holders of this software give you 20 * permission to link this software with independent modules, and to copy and 21 * distribute the resulting executable under terms of your choice, provided that 22 * you also meet, for each linked independent module, the terms and conditions of 23 * the license of that module. An independent module is a module which is not 24 * derived from this software. The special exception does not apply to any 25 * modifications of the software. 26 * 27 * Notwithstanding the above, under no circumstances may you combine this 28 * software in any way with any other Broadcom software provided under a license 29 * other than the GPL, without Broadcom's express prior written consent. 30 * 31 * 32 * <<Broadcom-WL-IPTag/Open:>> 33 */ 34 35 #ifndef _SBCHIPC_H 36 #define _SBCHIPC_H 37 38 #if !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__) 39 40 /* cpp contortions to concatenate w/arg prescan */ 41 #ifndef PAD 42 #define _PADLINE(line) pad ## line 43 #define _XSTR(line) _PADLINE(line) 44 #define PAD _XSTR(__LINE__) 45 #endif /* PAD */ 46 47 /** 48 * In chipcommon rev 49 the pmu registers have been moved from chipc to the pmu core if the 49 * 'AOBPresent' bit of 'CoreCapabilitiesExt' is set. If this field is set, the traditional chipc to 50 * [pmu|gci|sreng] register interface is deprecated and removed. These register blocks would instead 51 * be assigned their respective chipc-specific address space and connected to the Always On 52 * Backplane via the APB interface. 53 */ 54 typedef volatile struct { 55 uint32 PAD[384]; 56 uint32 pmucontrol; /* 0x600 */ 57 uint32 pmucapabilities; /* 0x604 */ 58 uint32 pmustatus; /* 0x608 */ 59 uint32 res_state; /* 0x60C */ 60 uint32 res_pending; /* 0x610 */ 61 uint32 pmutimer; /* 0x614 */ 62 uint32 min_res_mask; /* 0x618 */ 63 uint32 max_res_mask; /* 0x61C */ 64 uint32 res_table_sel; /* 0x620 */ 65 uint32 res_dep_mask; 66 uint32 res_updn_timer; 67 uint32 res_timer; 68 uint32 clkstretch; 69 uint32 pmuwatchdog; 70 uint32 gpiosel; /* 0x638, rev >= 1 */ 71 uint32 gpioenable; /* 0x63c, rev >= 1 */ 72 uint32 res_req_timer_sel; /* 0x640 */ 73 uint32 res_req_timer; /* 0x644 */ 74 uint32 res_req_mask; /* 0x648 */ 75 uint32 core_cap_ext; /* 0x64C */ 76 uint32 chipcontrol_addr; /* 0x650 */ 77 uint32 chipcontrol_data; /* 0x654 */ 78 uint32 regcontrol_addr; 79 uint32 regcontrol_data; 80 uint32 pllcontrol_addr; 81 uint32 pllcontrol_data; 82 uint32 pmustrapopt; /* 0x668, corerev >= 28 */ 83 uint32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */ 84 uint32 retention_ctl; /* 0x670 */ 85 uint32 ILPPeriod; /* 0x674 */ 86 uint32 PAD[2]; 87 uint32 retention_grpidx; /* 0x680 */ 88 uint32 retention_grpctl; /* 0x684 */ 89 uint32 mac_res_req_timer; /* 0x688 */ 90 uint32 mac_res_req_mask; /* 0x68c */ 91 uint32 PAD[18]; 92 uint32 pmucontrol_ext; /* 0x6d8 */ 93 uint32 slowclkperiod; /* 0x6dc */ 94 uint32 PAD[8]; 95 uint32 pmuintmask0; /* 0x700 */ 96 uint32 pmuintmask1; /* 0x704 */ 97 uint32 PAD[14]; 98 uint32 pmuintstatus; /* 0x740 */ 99 uint32 extwakeupstatus; /* 0x744 */ 100 uint32 watchdog_res_mask; /* 0x748 */ 101 uint32 PAD[1]; /* 0x74C */ 102 uint32 swscratch; /* 0x750 */ 103 uint32 PAD[3]; /* 0x754-0x75C */ 104 uint32 extwakemask[2]; /* 0x760-0x764 */ 105 uint32 PAD[2]; /* 0x768-0x76C */ 106 uint32 extwakereqmask[2]; /* 0x770-0x774 */ 107 uint32 PAD[2]; /* 0x778-0x77C */ 108 uint32 pmuintctrl0; /* 0x780 */ 109 uint32 pmuintctrl1; /* 0x784 */ 110 uint32 PAD[2]; 111 uint32 extwakectrl[2] ; /* 0x790 */ 112 } pmuregs_t; 113 114 typedef struct eci_prerev35 { 115 uint32 eci_output; 116 uint32 eci_control; 117 uint32 eci_inputlo; 118 uint32 eci_inputmi; 119 uint32 eci_inputhi; 120 uint32 eci_inputintpolaritylo; 121 uint32 eci_inputintpolaritymi; 122 uint32 eci_inputintpolarityhi; 123 uint32 eci_intmasklo; 124 uint32 eci_intmaskmi; 125 uint32 eci_intmaskhi; 126 uint32 eci_eventlo; 127 uint32 eci_eventmi; 128 uint32 eci_eventhi; 129 uint32 eci_eventmasklo; 130 uint32 eci_eventmaskmi; 131 uint32 eci_eventmaskhi; 132 uint32 PAD[3]; 133 } eci_prerev35_t; 134 135 typedef struct eci_rev35 { 136 uint32 eci_outputlo; 137 uint32 eci_outputhi; 138 uint32 eci_controllo; 139 uint32 eci_controlhi; 140 uint32 eci_inputlo; 141 uint32 eci_inputhi; 142 uint32 eci_inputintpolaritylo; 143 uint32 eci_inputintpolarityhi; 144 uint32 eci_intmasklo; 145 uint32 eci_intmaskhi; 146 uint32 eci_eventlo; 147 uint32 eci_eventhi; 148 uint32 eci_eventmasklo; 149 uint32 eci_eventmaskhi; 150 uint32 eci_auxtx; 151 uint32 eci_auxrx; 152 uint32 eci_datatag; 153 uint32 eci_uartescvalue; 154 uint32 eci_autobaudctr; 155 uint32 eci_uartfifolevel; 156 } eci_rev35_t; 157 158 typedef struct flash_config { 159 uint32 PAD[19]; 160 /* Flash struct configuration registers (0x18c) for BCM4706 (corerev = 31) */ 161 uint32 flashstrconfig; 162 } flash_config_t; 163 164 typedef volatile struct { 165 uint32 chipid; /* 0x0 */ 166 uint32 capabilities; 167 uint32 corecontrol; /* corerev >= 1 */ 168 uint32 bist; 169 170 /* OTP */ 171 uint32 otpstatus; /* 0x10, corerev >= 10 */ 172 uint32 otpcontrol; 173 uint32 otpprog; 174 uint32 otplayout; /* corerev >= 23 */ 175 176 /* Interrupt control */ 177 uint32 intstatus; /* 0x20 */ 178 uint32 intmask; 179 180 /* Chip specific regs */ 181 uint32 chipcontrol; /* 0x28, rev >= 11 */ 182 uint32 chipstatus; /* 0x2c, rev >= 11 */ 183 184 /* Jtag Master */ 185 uint32 jtagcmd; /* 0x30, rev >= 10 */ 186 uint32 jtagir; 187 uint32 jtagdr; 188 uint32 jtagctrl; 189 190 /* serial flash interface registers */ 191 uint32 flashcontrol; /* 0x40 */ 192 uint32 flashaddress; 193 uint32 flashdata; 194 uint32 otplayoutextension; /* rev >= 35 */ 195 196 /* Silicon backplane configuration broadcast control */ 197 uint32 broadcastaddress; /* 0x50 */ 198 uint32 broadcastdata; 199 200 /* gpio - cleared only by power-on-reset */ 201 uint32 gpiopullup; /* 0x58, corerev >= 20 */ 202 uint32 gpiopulldown; /* 0x5c, corerev >= 20 */ 203 uint32 gpioin; /* 0x60 */ 204 uint32 gpioout; /* 0x64 */ 205 uint32 gpioouten; /* 0x68 */ 206 uint32 gpiocontrol; /* 0x6C */ 207 uint32 gpiointpolarity; /* 0x70 */ 208 uint32 gpiointmask; /* 0x74 */ 209 210 /* GPIO events corerev >= 11 */ 211 uint32 gpioevent; 212 uint32 gpioeventintmask; 213 214 /* Watchdog timer */ 215 uint32 watchdog; /* 0x80 */ 216 217 /* GPIO events corerev >= 11 */ 218 uint32 gpioeventintpolarity; 219 220 /* GPIO based LED powersave registers corerev >= 16 */ 221 uint32 gpiotimerval; /* 0x88 */ 222 uint32 gpiotimeroutmask; 223 224 /* clock control */ 225 uint32 clockcontrol_n; /* 0x90 */ 226 uint32 clockcontrol_sb; /* aka m0 */ 227 uint32 clockcontrol_pci; /* aka m1 */ 228 uint32 clockcontrol_m2; /* mii/uart/mipsref */ 229 uint32 clockcontrol_m3; /* cpu */ 230 uint32 clkdiv; /* corerev >= 3 */ 231 uint32 gpiodebugsel; /* corerev >= 28 */ 232 uint32 capabilities_ext; /* 0xac */ 233 234 /* pll delay registers (corerev >= 4) */ 235 uint32 pll_on_delay; /* 0xb0 */ 236 uint32 fref_sel_delay; 237 uint32 slow_clk_ctl; /* 5 < corerev < 10 */ 238 uint32 PAD; 239 240 /* Instaclock registers (corerev >= 10) */ 241 uint32 system_clk_ctl; /* 0xc0 */ 242 uint32 clkstatestretch; 243 uint32 PAD[2]; 244 245 /* Indirect backplane access (corerev >= 22) */ 246 uint32 bp_addrlow; /* 0xd0 */ 247 uint32 bp_addrhigh; 248 uint32 bp_data; 249 uint32 PAD; 250 uint32 bp_indaccess; 251 /* SPI registers, corerev >= 37 */ 252 uint32 gsioctrl; 253 uint32 gsioaddress; 254 uint32 gsiodata; 255 256 /* More clock dividers (corerev >= 32) */ 257 uint32 clkdiv2; 258 /* FAB ID (corerev >= 40) */ 259 uint32 otpcontrol1; 260 uint32 fabid; /* 0xf8 */ 261 262 /* In AI chips, pointer to erom */ 263 uint32 eromptr; /* 0xfc */ 264 265 /* ExtBus control registers (corerev >= 3) */ 266 uint32 pcmcia_config; /* 0x100 */ 267 uint32 pcmcia_memwait; 268 uint32 pcmcia_attrwait; 269 uint32 pcmcia_iowait; 270 uint32 ide_config; 271 uint32 ide_memwait; 272 uint32 ide_attrwait; 273 uint32 ide_iowait; 274 uint32 prog_config; 275 uint32 prog_waitcount; 276 uint32 flash_config; 277 uint32 flash_waitcount; 278 uint32 SECI_config; /* 0x130 SECI configuration */ 279 uint32 SECI_status; 280 uint32 SECI_statusmask; 281 uint32 SECI_rxnibchanged; 282 283 uint32 PAD[20]; 284 285 /* SROM interface (corerev >= 32) */ 286 uint32 sromcontrol; /* 0x190 */ 287 uint32 sromaddress; 288 uint32 sromdata; 289 uint32 PAD[1]; /* 0x19C */ 290 /* NAND flash registers for BCM4706 (corerev = 31) */ 291 uint32 nflashctrl; /* 0x1a0 */ 292 uint32 nflashconf; 293 uint32 nflashcoladdr; 294 uint32 nflashrowaddr; 295 uint32 nflashdata; 296 uint32 nflashwaitcnt0; /* 0x1b4 */ 297 uint32 PAD[2]; 298 299 uint32 seci_uart_data; /* 0x1C0 */ 300 uint32 seci_uart_bauddiv; 301 uint32 seci_uart_fcr; 302 uint32 seci_uart_lcr; 303 uint32 seci_uart_mcr; 304 uint32 seci_uart_lsr; 305 uint32 seci_uart_msr; 306 uint32 seci_uart_baudadj; 307 /* Clock control and hardware workarounds (corerev >= 20) */ 308 uint32 clk_ctl_st; /* 0x1e0 */ 309 uint32 hw_war; 310 uint32 powerctl; /* 0x1e8 */ 311 uint32 PAD[69]; 312 313 /* UARTs */ 314 uint8 uart0data; /* 0x300 */ 315 uint8 uart0imr; 316 uint8 uart0fcr; 317 uint8 uart0lcr; 318 uint8 uart0mcr; 319 uint8 uart0lsr; 320 uint8 uart0msr; 321 uint8 uart0scratch; 322 uint8 PAD[248]; /* corerev >= 1 */ 323 324 uint8 uart1data; /* 0x400 */ 325 uint8 uart1imr; 326 uint8 uart1fcr; 327 uint8 uart1lcr; 328 uint8 uart1mcr; 329 uint8 uart1lsr; 330 uint8 uart1msr; 331 uint8 uart1scratch; /* 0x407 */ 332 uint32 PAD[62]; 333 334 /* save/restore, corerev >= 48 */ 335 uint32 sr_capability; /* 0x500 */ 336 uint32 sr_control0; /* 0x504 */ 337 uint32 sr_control1; /* 0x508 */ 338 uint32 gpio_control; /* 0x50C */ 339 uint32 PAD[29]; 340 /* 2 SR engines case */ 341 uint32 sr1_control0; /* 0x584 */ 342 uint32 sr1_control1; /* 0x588 */ 343 uint32 PAD[29]; 344 /* PMU registers (corerev >= 20) */ 345 /* Note: all timers driven by ILP clock are updated asynchronously to HT/ALP. 346 * The CPU must read them twice, compare, and retry if different. 347 */ 348 uint32 pmucontrol; /* 0x600 */ 349 uint32 pmucapabilities; 350 uint32 pmustatus; 351 uint32 res_state; 352 uint32 res_pending; 353 uint32 pmutimer; 354 uint32 min_res_mask; 355 uint32 max_res_mask; 356 uint32 res_table_sel; 357 uint32 res_dep_mask; 358 uint32 res_updn_timer; 359 uint32 res_timer; 360 uint32 clkstretch; 361 uint32 pmuwatchdog; 362 uint32 gpiosel; /* 0x638, rev >= 1 */ 363 uint32 gpioenable; /* 0x63c, rev >= 1 */ 364 uint32 res_req_timer_sel; 365 uint32 res_req_timer; 366 uint32 res_req_mask; 367 uint32 core_cap_ext; /* 0x64c */ 368 uint32 chipcontrol_addr; /* 0x650 */ 369 uint32 chipcontrol_data; /* 0x654 */ 370 uint32 regcontrol_addr; 371 uint32 regcontrol_data; 372 uint32 pllcontrol_addr; 373 uint32 pllcontrol_data; 374 uint32 pmustrapopt; /* 0x668, corerev >= 28 */ 375 uint32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */ 376 uint32 retention_ctl; /* 0x670 */ 377 uint32 PAD[3]; 378 uint32 retention_grpidx; /* 0x680 */ 379 uint32 retention_grpctl; /* 0x684 */ 380 uint32 PAD[20]; 381 uint32 pmucontrol_ext; /* 0x6d8 */ 382 uint32 slowclkperiod; /* 0x6dc */ 383 uint32 PAD[8]; 384 uint32 pmuintmask0; /* 0x700 */ 385 uint32 pmuintmask1; /* 0x704 */ 386 uint32 PAD[14]; 387 uint32 pmuintstatus; /* 0x740 */ 388 uint32 PAD[15]; 389 uint32 pmuintctrl0; /* 0x780 */ 390 uint32 PAD[31]; 391 uint16 sromotp[512]; /* 0x800 */ 392 #ifdef CCNFLASH_SUPPORT 393 /* Nand flash MLC controller registers (corerev >= 38) */ 394 uint32 nand_revision; /* 0xC00 */ 395 uint32 nand_cmd_start; 396 uint32 nand_cmd_addr_x; 397 uint32 nand_cmd_addr; 398 uint32 nand_cmd_end_addr; 399 uint32 nand_cs_nand_select; 400 uint32 nand_cs_nand_xor; 401 uint32 PAD; 402 uint32 nand_spare_rd0; 403 uint32 nand_spare_rd4; 404 uint32 nand_spare_rd8; 405 uint32 nand_spare_rd12; 406 uint32 nand_spare_wr0; 407 uint32 nand_spare_wr4; 408 uint32 nand_spare_wr8; 409 uint32 nand_spare_wr12; 410 uint32 nand_acc_control; 411 uint32 PAD; 412 uint32 nand_config; 413 uint32 PAD; 414 uint32 nand_timing_1; 415 uint32 nand_timing_2; 416 uint32 nand_semaphore; 417 uint32 PAD; 418 uint32 nand_devid; 419 uint32 nand_devid_x; 420 uint32 nand_block_lock_status; 421 uint32 nand_intfc_status; 422 uint32 nand_ecc_corr_addr_x; 423 uint32 nand_ecc_corr_addr; 424 uint32 nand_ecc_unc_addr_x; 425 uint32 nand_ecc_unc_addr; 426 uint32 nand_read_error_count; 427 uint32 nand_corr_stat_threshold; 428 uint32 PAD[2]; 429 uint32 nand_read_addr_x; 430 uint32 nand_read_addr; 431 uint32 nand_page_program_addr_x; 432 uint32 nand_page_program_addr; 433 uint32 nand_copy_back_addr_x; 434 uint32 nand_copy_back_addr; 435 uint32 nand_block_erase_addr_x; 436 uint32 nand_block_erase_addr; 437 uint32 nand_inv_read_addr_x; 438 uint32 nand_inv_read_addr; 439 uint32 PAD[2]; 440 uint32 nand_blk_wr_protect; 441 uint32 PAD[3]; 442 uint32 nand_acc_control_cs1; 443 uint32 nand_config_cs1; 444 uint32 nand_timing_1_cs1; 445 uint32 nand_timing_2_cs1; 446 uint32 PAD[20]; 447 uint32 nand_spare_rd16; 448 uint32 nand_spare_rd20; 449 uint32 nand_spare_rd24; 450 uint32 nand_spare_rd28; 451 uint32 nand_cache_addr; 452 uint32 nand_cache_data; 453 uint32 nand_ctrl_config; 454 uint32 nand_ctrl_status; 455 #endif /* CCNFLASH_SUPPORT */ 456 uint32 gci_corecaps0; /* GCI starting at 0xC00 */ 457 uint32 gci_corecaps1; 458 uint32 gci_corecaps2; 459 uint32 gci_corectrl; 460 uint32 gci_corestat; /* 0xC10 */ 461 uint32 gci_intstat; /* 0xC14 */ 462 uint32 gci_intmask; /* 0xC18 */ 463 uint32 gci_wakemask; /* 0xC1C */ 464 uint32 gci_levelintstat; /* 0xC20 */ 465 uint32 gci_eventintstat; /* 0xC24 */ 466 uint32 PAD[6]; 467 uint32 gci_indirect_addr; /* 0xC40 */ 468 uint32 gci_gpioctl; /* 0xC44 */ 469 uint32 gci_gpiostatus; 470 uint32 gci_gpiomask; /* 0xC4C */ 471 uint32 PAD; 472 uint32 gci_miscctl; /* 0xC54 */ 473 uint32 gci_gpiointmask; 474 uint32 gci_gpiowakemask; 475 uint32 gci_input[32]; /* C60 */ 476 uint32 gci_event[32]; /* CE0 */ 477 uint32 gci_output[4]; /* D60 */ 478 uint32 gci_control_0; /* 0xD70 */ 479 uint32 gci_control_1; /* 0xD74 */ 480 uint32 gci_intpolreg; /* 0xD78 */ 481 uint32 gci_levelintmask; /* 0xD7C */ 482 uint32 gci_eventintmask; /* 0xD80 */ 483 uint32 PAD[3]; 484 uint32 gci_inbandlevelintmask; /* 0xD90 */ 485 uint32 gci_inbandeventintmask; /* 0xD94 */ 486 uint32 PAD[2]; 487 uint32 gci_seciauxtx; /* 0xDA0 */ 488 uint32 gci_seciauxrx; /* 0xDA4 */ 489 uint32 gci_secitx_datatag; /* 0xDA8 */ 490 uint32 gci_secirx_datatag; /* 0xDAC */ 491 uint32 gci_secitx_datamask; /* 0xDB0 */ 492 uint32 gci_seciusef0tx_reg; /* 0xDB4 */ 493 uint32 gci_secif0tx_offset; /* 0xDB8 */ 494 uint32 gci_secif0rx_offset; /* 0xDBC */ 495 uint32 gci_secif1tx_offset; /* 0xDC0 */ 496 uint32 gci_rxfifo_common_ctrl; /* 0xDC4 */ 497 uint32 gci_rxfifoctrl; /* 0xDC8 */ 498 uint32 gci_uartreadid; /* DCC */ 499 uint32 gci_seciuartescval; /* DD0 */ 500 uint32 PAD; 501 uint32 gci_secififolevel; /* DD8 */ 502 uint32 gci_seciuartdata; /* DDC */ 503 uint32 gci_secibauddiv; /* DE0 */ 504 uint32 gci_secifcr; /* DE4 */ 505 uint32 gci_secilcr; /* DE8 */ 506 uint32 gci_secimcr; /* DEC */ 507 uint32 gci_secilsr; /* DF0 */ 508 uint32 gci_secimsr; /* DF4 */ 509 uint32 gci_baudadj; /* DF8 */ 510 uint32 PAD; 511 uint32 gci_chipctrl; /* 0xE00 */ 512 uint32 gci_chipsts; /* 0xE04 */ 513 uint32 gci_gpioout; /* 0xE08 */ 514 uint32 gci_gpioout_read; /* 0xE0C */ 515 uint32 gci_mpwaketx; /* 0xE10 */ 516 uint32 gci_mpwakedetect; /* 0xE14 */ 517 uint32 gci_seciin_ctrl; /* 0xE18 */ 518 uint32 gci_seciout_ctrl; /* 0xE1C */ 519 uint32 gci_seciin_auxfifo_en; /* 0xE20 */ 520 uint32 gci_seciout_txen_txbr; /* 0xE24 */ 521 uint32 gci_seciin_rxbrstatus; /* 0xE28 */ 522 uint32 gci_seciin_rxerrstatus; /* 0xE2C */ 523 uint32 gci_seciin_fcstatus; /* 0xE30 */ 524 uint32 gci_seciout_txstatus; /* 0xE34 */ 525 uint32 gci_seciout_txbrstatus; /* 0xE38 */ 526 } chipcregs_t; 527 528 #endif /* !_LANGUAGE_ASSEMBLY && !__ASSEMBLY__ */ 529 530 531 #define CC_CHIPID 0 532 #define CC_CAPABILITIES 4 533 #define CC_CHIPST 0x2c 534 #define CC_EROMPTR 0xfc 535 536 #define CC_OTPST 0x10 537 #define CC_INTSTATUS 0x20 538 #define CC_INTMASK 0x24 539 #define CC_JTAGCMD 0x30 540 #define CC_JTAGIR 0x34 541 #define CC_JTAGDR 0x38 542 #define CC_JTAGCTRL 0x3c 543 #define CC_GPIOPU 0x58 544 #define CC_GPIOPD 0x5c 545 #define CC_GPIOIN 0x60 546 #define CC_GPIOOUT 0x64 547 #define CC_GPIOOUTEN 0x68 548 #define CC_GPIOCTRL 0x6c 549 #define CC_GPIOPOL 0x70 550 #define CC_GPIOINTM 0x74 551 #define CC_GPIOEVENT 0x78 552 #define CC_GPIOEVENTMASK 0x7c 553 #define CC_WATCHDOG 0x80 554 #define CC_GPIOEVENTPOL 0x84 555 #define CC_CLKC_N 0x90 556 #define CC_CLKC_M0 0x94 557 #define CC_CLKC_M1 0x98 558 #define CC_CLKC_M2 0x9c 559 #define CC_CLKC_M3 0xa0 560 #define CC_CLKDIV 0xa4 561 #define CC_CAP_EXT 0xac 562 #define CC_SYS_CLK_CTL 0xc0 563 #define CC_CLKDIV2 0xf0 564 #define CC_CLK_CTL_ST SI_CLK_CTL_ST 565 #define PMU_CTL 0x600 566 #define PMU_CAP 0x604 567 #define PMU_ST 0x608 568 #define PMU_RES_STATE 0x60c 569 #define PMU_RES_PENDING 0x610 570 #define PMU_TIMER 0x614 571 #define PMU_MIN_RES_MASK 0x618 572 #define PMU_MAX_RES_MASK 0x61c 573 #define CC_CHIPCTL_ADDR 0x650 574 #define CC_CHIPCTL_DATA 0x654 575 #define PMU_REG_CONTROL_ADDR 0x658 576 #define PMU_REG_CONTROL_DATA 0x65C 577 #define PMU_PLL_CONTROL_ADDR 0x660 578 #define PMU_PLL_CONTROL_DATA 0x664 579 580 #define CC_SROM_CTRL 0x190 581 #ifdef SROM16K_4364_ADDRSPACE 582 #define CC_SROM_OTP 0xa000 /* SROM/OTP address space */ 583 #else 584 #define CC_SROM_OTP 0x0800 585 #endif 586 #define CC_GCI_INDIRECT_ADDR_REG 0xC40 587 #define CC_GCI_CHIP_CTRL_REG 0xE00 588 #define CC_GCI_CC_OFFSET_2 2 589 #define CC_GCI_CC_OFFSET_5 5 590 #define CC_SWD_CTRL 0x380 591 #define CC_SWD_REQACK 0x384 592 #define CC_SWD_DATA 0x388 593 594 #define CHIPCTRLREG0 0x0 595 #define CHIPCTRLREG1 0x1 596 #define CHIPCTRLREG2 0x2 597 #define CHIPCTRLREG3 0x3 598 #define CHIPCTRLREG4 0x4 599 #define CHIPCTRLREG5 0x5 600 #define CHIPCTRLREG6 0x6 601 #define REGCTRLREG4 0x4 602 #define REGCTRLREG5 0x5 603 #define REGCTRLREG6 0x6 604 #define MINRESMASKREG 0x618 605 #define MAXRESMASKREG 0x61c 606 #define CHIPCTRLADDR 0x650 607 #define CHIPCTRLDATA 0x654 608 #define RSRCTABLEADDR 0x620 609 #define PMU_RES_DEP_MASK 0x624 610 #define RSRCUPDWNTIME 0x628 611 #define PMUREG_RESREQ_MASK 0x68c 612 #define PMUREG_RESREQ_TIMER 0x688 613 #define PMUREG_RESREQ_MASK1 0x6f4 614 #define PMUREG_RESREQ_TIMER1 0x6f0 615 #define EXT_LPO_AVAIL 0x100 616 #define LPO_SEL (1 << 0) 617 #define CC_EXT_LPO_PU 0x200000 618 #define GC_EXT_LPO_PU 0x2 619 #define CC_INT_LPO_PU 0x100000 620 #define GC_INT_LPO_PU 0x1 621 #define EXT_LPO_SEL 0x8 622 #define INT_LPO_SEL 0x4 623 #define ENABLE_FINE_CBUCK_CTRL (1 << 30) 624 #define REGCTRL5_PWM_AUTO_CTRL_MASK 0x007e0000 625 #define REGCTRL5_PWM_AUTO_CTRL_SHIFT 17 626 #define REGCTRL6_PWM_AUTO_CTRL_MASK 0x3fff0000 627 #define REGCTRL6_PWM_AUTO_CTRL_SHIFT 16 628 #define CC_BP_IND_ACCESS_START_SHIFT 9 629 #define CC_BP_IND_ACCESS_START_MASK (1 << CC_BP_IND_ACCESS_START_SHIFT) 630 #define CC_BP_IND_ACCESS_RDWR_SHIFT 8 631 #define CC_BP_IND_ACCESS_RDWR_MASK (1 << CC_BP_IND_ACCESS_RDWR_SHIFT) 632 #define CC_BP_IND_ACCESS_ERROR_SHIFT 10 633 #define CC_BP_IND_ACCESS_ERROR_MASK (1 << CC_BP_IND_ACCESS_ERROR_SHIFT) 634 635 #ifdef SR_DEBUG 636 #define SUBCORE_POWER_ON 0x0001 637 #define PHY_POWER_ON 0x0010 638 #define VDDM_POWER_ON 0x0100 639 #define MEMLPLDO_POWER_ON 0x1000 640 #define SUBCORE_POWER_ON_CHK 0x00040000 641 #define PHY_POWER_ON_CHK 0x00080000 642 #define VDDM_POWER_ON_CHK 0x00100000 643 #define MEMLPLDO_POWER_ON_CHK 0x00200000 644 #endif /* SR_DEBUG */ 645 646 #ifdef CCNFLASH_SUPPORT 647 /* NAND flash support */ 648 #define CC_NAND_REVISION 0xC00 649 #define CC_NAND_CMD_START 0xC04 650 #define CC_NAND_CMD_ADDR 0xC0C 651 #define CC_NAND_SPARE_RD_0 0xC20 652 #define CC_NAND_SPARE_RD_4 0xC24 653 #define CC_NAND_SPARE_RD_8 0xC28 654 #define CC_NAND_SPARE_RD_C 0xC2C 655 #define CC_NAND_CONFIG 0xC48 656 #define CC_NAND_DEVID 0xC60 657 #define CC_NAND_DEVID_EXT 0xC64 658 #define CC_NAND_INTFC_STATUS 0xC6C 659 #endif /* CCNFLASH_SUPPORT */ 660 661 /* chipid */ 662 #define CID_ID_MASK 0x0000ffff /**< Chip Id mask */ 663 #define CID_REV_MASK 0x000f0000 /**< Chip Revision mask */ 664 #define CID_REV_SHIFT 16 /**< Chip Revision shift */ 665 #define CID_PKG_MASK 0x00f00000 /**< Package Option mask */ 666 #define CID_PKG_SHIFT 20 /**< Package Option shift */ 667 #define CID_CC_MASK 0x0f000000 /**< CoreCount (corerev >= 4) */ 668 #define CID_CC_SHIFT 24 669 #define CID_TYPE_MASK 0xf0000000 /**< Chip Type */ 670 #define CID_TYPE_SHIFT 28 671 672 /* capabilities */ 673 #define CC_CAP_UARTS_MASK 0x00000003 /**< Number of UARTs */ 674 #define CC_CAP_MIPSEB 0x00000004 /**< MIPS is in big-endian mode */ 675 #define CC_CAP_UCLKSEL 0x00000018 /**< UARTs clock select */ 676 #define CC_CAP_UINTCLK 0x00000008 /**< UARTs are driven by internal divided clock */ 677 #define CC_CAP_UARTGPIO 0x00000020 /**< UARTs own GPIOs 15:12 */ 678 #define CC_CAP_EXTBUS_MASK 0x000000c0 /**< External bus mask */ 679 #define CC_CAP_EXTBUS_NONE 0x00000000 /**< No ExtBus present */ 680 #define CC_CAP_EXTBUS_FULL 0x00000040 /**< ExtBus: PCMCIA, IDE & Prog */ 681 #define CC_CAP_EXTBUS_PROG 0x00000080 /**< ExtBus: ProgIf only */ 682 #define CC_CAP_FLASH_MASK 0x00000700 /**< Type of flash */ 683 #define CC_CAP_PLL_MASK 0x00038000 /**< Type of PLL */ 684 #define CC_CAP_PWR_CTL 0x00040000 /**< Power control */ 685 #define CC_CAP_OTPSIZE 0x00380000 /**< OTP Size (0 = none) */ 686 #define CC_CAP_OTPSIZE_SHIFT 19 /**< OTP Size shift */ 687 #define CC_CAP_OTPSIZE_BASE 5 /**< OTP Size base */ 688 #define CC_CAP_JTAGP 0x00400000 /**< JTAG Master Present */ 689 #define CC_CAP_ROM 0x00800000 /**< Internal boot rom active */ 690 #define CC_CAP_BKPLN64 0x08000000 /**< 64-bit backplane */ 691 #define CC_CAP_PMU 0x10000000 /**< PMU Present, rev >= 20 */ 692 #define CC_CAP_ECI 0x20000000 /**< ECI Present, rev >= 21 */ 693 #define CC_CAP_SROM 0x40000000 /**< Srom Present, rev >= 32 */ 694 #define CC_CAP_NFLASH 0x80000000 /**< Nand flash present, rev >= 35 */ 695 696 #define CC_CAP2_SECI 0x00000001 /**< SECI Present, rev >= 36 */ 697 #define CC_CAP2_GSIO 0x00000002 /**< GSIO (spi/i2c) present, rev >= 37 */ 698 699 /* capabilities extension */ 700 #define CC_CAP_EXT_SECI_PRESENT 0x00000001 /**< SECI present */ 701 #define CC_CAP_EXT_GSIO_PRESENT 0x00000002 /**< GSIO present */ 702 #define CC_CAP_EXT_GCI_PRESENT 0x00000004 /**< GCI present */ 703 #define CC_CAP_EXT_SECI_PUART_PRESENT 0x00000008 /**< UART present */ 704 #define CC_CAP_EXT_AOB_PRESENT 0x00000040 /**< AOB present */ 705 #define CC_CAP_EXT_SWD_PRESENT 0x00000400 /**< SWD present */ 706 707 /* WL Channel Info to BT via GCI - bits 40 - 47 */ 708 #define GCI_WL_CHN_INFO_MASK (0xFF00) 709 /* WL indication of MCHAN enabled/disabled to BT in awdl mode- bit 36 */ 710 #define GCI_WL_MCHAN_BIT_MASK (0x0010) 711 /* WL Strobe to BT */ 712 #define GCI_WL_STROBE_BIT_MASK (0x0020) 713 /* bits [51:48] - reserved for wlan TX pwr index */ 714 /* bits [55:52] btc mode indication */ 715 #define GCI_WL_BTC_MODE_SHIFT (20) 716 #define GCI_WL_BTC_MODE_MASK (0xF << GCI_WL_BTC_MODE_SHIFT) 717 #define GCI_WL_ANT_BIT_MASK (0x00c0) 718 #define GCI_WL_ANT_SHIFT_BITS (6) 719 /* PLL type */ 720 #define PLL_NONE 0x00000000 721 #define PLL_TYPE1 0x00010000 /**< 48MHz base, 3 dividers */ 722 #define PLL_TYPE2 0x00020000 /**< 48MHz, 4 dividers */ 723 #define PLL_TYPE3 0x00030000 /**< 25MHz, 2 dividers */ 724 #define PLL_TYPE4 0x00008000 /**< 48MHz, 4 dividers */ 725 #define PLL_TYPE5 0x00018000 /**< 25MHz, 4 dividers */ 726 #define PLL_TYPE6 0x00028000 /**< 100/200 or 120/240 only */ 727 #define PLL_TYPE7 0x00038000 /**< 25MHz, 4 dividers */ 728 729 /* ILP clock */ 730 #define ILP_CLOCK 32000 731 732 /* ALP clock on pre-PMU chips */ 733 #define ALP_CLOCK 20000000 734 735 #ifdef CFG_SIM 736 #define NS_ALP_CLOCK 84922 737 #define NS_SLOW_ALP_CLOCK 84922 738 #define NS_CPU_CLOCK 534500 739 #define NS_SLOW_CPU_CLOCK 534500 740 #define NS_SI_CLOCK 271750 741 #define NS_SLOW_SI_CLOCK 271750 742 #define NS_FAST_MEM_CLOCK 271750 743 #define NS_MEM_CLOCK 271750 744 #define NS_SLOW_MEM_CLOCK 271750 745 #else 746 #define NS_ALP_CLOCK 125000000 747 #define NS_SLOW_ALP_CLOCK 100000000 748 #define NS_CPU_CLOCK 1000000000 749 #define NS_SLOW_CPU_CLOCK 800000000 750 #define NS_SI_CLOCK 250000000 751 #define NS_SLOW_SI_CLOCK 200000000 752 #define NS_FAST_MEM_CLOCK 800000000 753 #define NS_MEM_CLOCK 533000000 754 #define NS_SLOW_MEM_CLOCK 400000000 755 #endif /* CFG_SIM */ 756 757 #define ALP_CLOCK_53573 40000000 758 759 /* HT clock */ 760 #define HT_CLOCK 80000000 761 762 /* corecontrol */ 763 #define CC_UARTCLKO 0x00000001 /**< Drive UART with internal clock */ 764 #define CC_SE 0x00000002 /**< sync clk out enable (corerev >= 3) */ 765 #define CC_ASYNCGPIO 0x00000004 /**< 1=generate GPIO interrupt without backplane clock */ 766 #define CC_UARTCLKEN 0x00000008 /**< enable UART Clock (corerev > = 21 */ 767 768 /* retention_ctl */ 769 #define RCTL_MEM_RET_SLEEP_LOG_SHIFT 29 770 #define RCTL_MEM_RET_SLEEP_LOG_MASK (1 << RCTL_MEM_RET_SLEEP_LOG_SHIFT) 771 772 /* 4321 chipcontrol */ 773 #define CHIPCTRL_4321A0_DEFAULT 0x3a4 774 #define CHIPCTRL_4321A1_DEFAULT 0x0a4 775 #define CHIPCTRL_4321_PLL_DOWN 0x800000 /**< serdes PLL down override */ 776 777 /* Fields in the otpstatus register in rev >= 21 */ 778 #define OTPS_OL_MASK 0x000000ff 779 #define OTPS_OL_MFG 0x00000001 /**< manuf row is locked */ 780 #define OTPS_OL_OR1 0x00000002 /**< otp redundancy row 1 is locked */ 781 #define OTPS_OL_OR2 0x00000004 /**< otp redundancy row 2 is locked */ 782 #define OTPS_OL_GU 0x00000008 /**< general use region is locked */ 783 #define OTPS_GUP_MASK 0x00000f00 784 #define OTPS_GUP_SHIFT 8 785 #define OTPS_GUP_HW 0x00000100 /**< h/w subregion is programmed */ 786 #define OTPS_GUP_SW 0x00000200 /**< s/w subregion is programmed */ 787 #define OTPS_GUP_CI 0x00000400 /**< chipid/pkgopt subregion is programmed */ 788 #define OTPS_GUP_FUSE 0x00000800 /**< fuse subregion is programmed */ 789 #define OTPS_READY 0x00001000 790 #define OTPS_RV(x) (1 << (16 + (x))) /**< redundancy entry valid */ 791 #define OTPS_RV_MASK 0x0fff0000 792 #define OTPS_PROGOK 0x40000000 793 794 /* Fields in the otpcontrol register in rev >= 21 */ 795 #define OTPC_PROGSEL 0x00000001 796 #define OTPC_PCOUNT_MASK 0x0000000e 797 #define OTPC_PCOUNT_SHIFT 1 798 #define OTPC_VSEL_MASK 0x000000f0 799 #define OTPC_VSEL_SHIFT 4 800 #define OTPC_TMM_MASK 0x00000700 801 #define OTPC_TMM_SHIFT 8 802 #define OTPC_ODM 0x00000800 803 #define OTPC_PROGEN 0x80000000 804 805 /* Fields in the 40nm otpcontrol register in rev >= 40 */ 806 #define OTPC_40NM_PROGSEL_SHIFT 0 807 #define OTPC_40NM_PCOUNT_SHIFT 1 808 #define OTPC_40NM_PCOUNT_WR 0xA 809 #define OTPC_40NM_PCOUNT_V1X 0xB 810 #define OTPC_40NM_REGCSEL_SHIFT 5 811 #define OTPC_40NM_REGCSEL_DEF 0x4 812 #define OTPC_40NM_PROGIN_SHIFT 8 813 #define OTPC_40NM_R2X_SHIFT 10 814 #define OTPC_40NM_ODM_SHIFT 11 815 #define OTPC_40NM_DF_SHIFT 15 816 #define OTPC_40NM_VSEL_SHIFT 16 817 #define OTPC_40NM_VSEL_WR 0xA 818 #define OTPC_40NM_VSEL_V1X 0xA 819 #define OTPC_40NM_VSEL_R1X 0x5 820 #define OTPC_40NM_COFAIL_SHIFT 30 821 822 #define OTPC1_CPCSEL_SHIFT 0 823 #define OTPC1_CPCSEL_DEF 6 824 #define OTPC1_TM_SHIFT 8 825 #define OTPC1_TM_WR 0x84 826 #define OTPC1_TM_V1X 0x84 827 #define OTPC1_TM_R1X 0x4 828 #define OTPC1_CLK_EN_MASK 0x00020000 829 #define OTPC1_CLK_DIV_MASK 0x00FC0000 830 831 /* Fields in otpprog in rev >= 21 and HND OTP */ 832 #define OTPP_COL_MASK 0x000000ff 833 #define OTPP_COL_SHIFT 0 834 #define OTPP_ROW_MASK 0x0000ff00 835 #define OTPP_ROW_MASK9 0x0001ff00 /* for ccrev >= 49 */ 836 #define OTPP_ROW_SHIFT 8 837 #define OTPP_OC_MASK 0x0f000000 838 #define OTPP_OC_SHIFT 24 839 #define OTPP_READERR 0x10000000 840 #define OTPP_VALUE_MASK 0x20000000 841 #define OTPP_VALUE_SHIFT 29 842 #define OTPP_START_BUSY 0x80000000 843 #define OTPP_READ 0x40000000 /* HND OTP */ 844 845 /* Fields in otplayout register */ 846 #define OTPL_HWRGN_OFF_MASK 0x00000FFF 847 #define OTPL_HWRGN_OFF_SHIFT 0 848 #define OTPL_WRAP_REVID_MASK 0x00F80000 849 #define OTPL_WRAP_REVID_SHIFT 19 850 #define OTPL_WRAP_TYPE_MASK 0x00070000 851 #define OTPL_WRAP_TYPE_SHIFT 16 852 #define OTPL_WRAP_TYPE_65NM 0 853 #define OTPL_WRAP_TYPE_40NM 1 854 #define OTPL_WRAP_TYPE_28NM 2 855 #define OTPL_ROW_SIZE_MASK 0x0000F000 856 #define OTPL_ROW_SIZE_SHIFT 12 857 858 /* otplayout reg corerev >= 36 */ 859 #define OTP_CISFORMAT_NEW 0x80000000 860 861 /* Opcodes for OTPP_OC field */ 862 #define OTPPOC_READ 0 863 #define OTPPOC_BIT_PROG 1 864 #define OTPPOC_VERIFY 3 865 #define OTPPOC_INIT 4 866 #define OTPPOC_SET 5 867 #define OTPPOC_RESET 6 868 #define OTPPOC_OCST 7 869 #define OTPPOC_ROW_LOCK 8 870 #define OTPPOC_PRESCN_TEST 9 871 872 /* Opcodes for OTPP_OC field (40NM) */ 873 #define OTPPOC_READ_40NM 0 874 #define OTPPOC_PROG_ENABLE_40NM 1 875 #define OTPPOC_PROG_DISABLE_40NM 2 876 #define OTPPOC_VERIFY_40NM 3 877 #define OTPPOC_WORD_VERIFY_1_40NM 4 878 #define OTPPOC_ROW_LOCK_40NM 5 879 #define OTPPOC_STBY_40NM 6 880 #define OTPPOC_WAKEUP_40NM 7 881 #define OTPPOC_WORD_VERIFY_0_40NM 8 882 #define OTPPOC_PRESCN_TEST_40NM 9 883 #define OTPPOC_BIT_PROG_40NM 10 884 #define OTPPOC_WORDPROG_40NM 11 885 #define OTPPOC_BURNIN_40NM 12 886 #define OTPPOC_AUTORELOAD_40NM 13 887 #define OTPPOC_OVST_READ_40NM 14 888 #define OTPPOC_OVST_PROG_40NM 15 889 890 /* Opcodes for OTPP_OC field (28NM) */ 891 #define OTPPOC_READ_28NM 0 892 #define OTPPOC_READBURST_28NM 1 893 #define OTPPOC_PROG_ENABLE_28NM 2 894 #define OTPPOC_PROG_DISABLE_28NM 3 895 #define OTPPOC_PRESCREEN_28NM 4 896 #define OTPPOC_PRESCREEN_RP_28NM 5 897 #define OTPPOC_FLUSH_28NM 6 898 #define OTPPOC_NOP_28NM 7 899 #define OTPPOC_PROG_ECC_28NM 8 900 #define OTPPOC_PROG_ECC_READ_28NM 9 901 #define OTPPOC_PROG_28NM 10 902 #define OTPPOC_PROGRAM_RP_28NM 11 903 #define OTPPOC_PROGRAM_OVST_28NM 12 904 #define OTPPOC_RELOAD_28NM 13 905 #define OTPPOC_ERASE_28NM 14 906 #define OTPPOC_LOAD_RF_28NM 15 907 #define OTPPOC_CTRL_WR_28NM 16 908 #define OTPPOC_CTRL_RD_28NM 17 909 #define OTPPOC_READ_HP_28NM 18 910 #define OTPPOC_READ_OVST_28NM 19 911 #define OTPPOC_READ_VERIFY0_28NM 20 912 #define OTPPOC_READ_VERIFY1_28NM 21 913 #define OTPPOC_READ_FORCE0_28NM 22 914 #define OTPPOC_READ_FORCE1_28NM 23 915 #define OTPPOC_BURNIN_28NM 24 916 #define OTPPOC_PROGRAM_LOCK_28NM 25 917 #define OTPPOC_PROGRAM_TESTCOL_28NM 26 918 #define OTPPOC_READ_TESTCOL_28NM 27 919 #define OTPPOC_READ_FOUT_28NM 28 920 #define OTPPOC_SFT_RESET_28NM 29 921 922 #define OTPP_OC_MASK_28NM 0x0f800000 923 #define OTPP_OC_SHIFT_28NM 23 924 #define OTPC_PROGEN_28NM 0x8 925 #define OTPC_DBLERRCLR 0x20 926 #define OTPC_CLK_EN_MASK 0x00000040 927 #define OTPC_CLK_DIV_MASK 0x00000F80 928 929 /* Fields in otplayoutextension */ 930 #define OTPLAYOUTEXT_FUSE_MASK 0x3FF 931 932 933 /* Jtagm characteristics that appeared at a given corerev */ 934 #define JTAGM_CREV_OLD 10 /**< Old command set, 16bit max IR */ 935 #define JTAGM_CREV_IRP 22 /**< Able to do pause-ir */ 936 #define JTAGM_CREV_RTI 28 /**< Able to do return-to-idle */ 937 938 /* jtagcmd */ 939 #define JCMD_START 0x80000000 940 #define JCMD_BUSY 0x80000000 941 #define JCMD_STATE_MASK 0x60000000 942 #define JCMD_STATE_TLR 0x00000000 /**< Test-logic-reset */ 943 #define JCMD_STATE_PIR 0x20000000 /**< Pause IR */ 944 #define JCMD_STATE_PDR 0x40000000 /**< Pause DR */ 945 #define JCMD_STATE_RTI 0x60000000 /**< Run-test-idle */ 946 #define JCMD0_ACC_MASK 0x0000f000 947 #define JCMD0_ACC_IRDR 0x00000000 948 #define JCMD0_ACC_DR 0x00001000 949 #define JCMD0_ACC_IR 0x00002000 950 #define JCMD0_ACC_RESET 0x00003000 951 #define JCMD0_ACC_IRPDR 0x00004000 952 #define JCMD0_ACC_PDR 0x00005000 953 #define JCMD0_IRW_MASK 0x00000f00 954 #define JCMD_ACC_MASK 0x000f0000 /**< Changes for corerev 11 */ 955 #define JCMD_ACC_IRDR 0x00000000 956 #define JCMD_ACC_DR 0x00010000 957 #define JCMD_ACC_IR 0x00020000 958 #define JCMD_ACC_RESET 0x00030000 959 #define JCMD_ACC_IRPDR 0x00040000 960 #define JCMD_ACC_PDR 0x00050000 961 #define JCMD_ACC_PIR 0x00060000 962 #define JCMD_ACC_IRDR_I 0x00070000 /**< rev 28: return to run-test-idle */ 963 #define JCMD_ACC_DR_I 0x00080000 /**< rev 28: return to run-test-idle */ 964 #define JCMD_IRW_MASK 0x00001f00 965 #define JCMD_IRW_SHIFT 8 966 #define JCMD_DRW_MASK 0x0000003f 967 968 /* jtagctrl */ 969 #define JCTRL_FORCE_CLK 4 /**< Force clock */ 970 #define JCTRL_EXT_EN 2 /**< Enable external targets */ 971 #define JCTRL_EN 1 /**< Enable Jtag master */ 972 #define JCTRL_TAPSEL_BIT 0x00000008 /**< JtagMasterCtrl tap_sel bit */ 973 974 /* swdmasterctrl */ 975 #define SWDCTRL_INT_EN 8 /**< Enable internal targets */ 976 #define SWDCTRL_FORCE_CLK 4 /**< Force clock */ 977 #define SWDCTRL_OVJTAG 2 /**< Enable shared SWD/JTAG pins */ 978 #define SWDCTRL_EN 1 /**< Enable Jtag master */ 979 980 /* Fields in clkdiv */ 981 #define CLKD_SFLASH 0x1f000000 982 #define CLKD_SFLASH_SHIFT 24 983 #define CLKD_OTP 0x000f0000 984 #define CLKD_OTP_SHIFT 16 985 #define CLKD_JTAG 0x00000f00 986 #define CLKD_JTAG_SHIFT 8 987 #define CLKD_UART 0x000000ff 988 989 #define CLKD2_SROM 0x00000003 990 #define CLKD2_SWD 0xf8000000 991 #define CLKD2_SWD_SHIFT 27 992 993 /* intstatus/intmask */ 994 #define CI_GPIO 0x00000001 /**< gpio intr */ 995 #define CI_EI 0x00000002 /**< extif intr (corerev >= 3) */ 996 #define CI_TEMP 0x00000004 /**< temp. ctrl intr (corerev >= 15) */ 997 #define CI_SIRQ 0x00000008 /**< serial IRQ intr (corerev >= 15) */ 998 #define CI_ECI 0x00000010 /**< eci intr (corerev >= 21) */ 999 #define CI_PMU 0x00000020 /**< pmu intr (corerev >= 21) */ 1000 #define CI_UART 0x00000040 /**< uart intr (corerev >= 21) */ 1001 #define CI_WDRESET 0x80000000 /**< watchdog reset occurred */ 1002 1003 /* slow_clk_ctl */ 1004 #define SCC_SS_MASK 0x00000007 /**< slow clock source mask */ 1005 #define SCC_SS_LPO 0x00000000 /**< source of slow clock is LPO */ 1006 #define SCC_SS_XTAL 0x00000001 /**< source of slow clock is crystal */ 1007 #define SCC_SS_PCI 0x00000002 /**< source of slow clock is PCI */ 1008 #define SCC_LF 0x00000200 /**< LPOFreqSel, 1: 160Khz, 0: 32KHz */ 1009 #define SCC_LP 0x00000400 /**< LPOPowerDown, 1: LPO is disabled, 1010 * 0: LPO is enabled 1011 */ 1012 #define SCC_FS 0x00000800 /**< ForceSlowClk, 1: sb/cores running on slow clock, 1013 * 0: power logic control 1014 */ 1015 #define SCC_IP 0x00001000 /**< IgnorePllOffReq, 1/0: power logic ignores/honors 1016 * PLL clock disable requests from core 1017 */ 1018 #define SCC_XC 0x00002000 /**< XtalControlEn, 1/0: power logic does/doesn't 1019 * disable crystal when appropriate 1020 */ 1021 #define SCC_XP 0x00004000 /**< XtalPU (RO), 1/0: crystal running/disabled */ 1022 #define SCC_CD_MASK 0xffff0000 /**< ClockDivider (SlowClk = 1/(4+divisor)) */ 1023 #define SCC_CD_SHIFT 16 1024 1025 /* system_clk_ctl */ 1026 #define SYCC_IE 0x00000001 /**< ILPen: Enable Idle Low Power */ 1027 #define SYCC_AE 0x00000002 /**< ALPen: Enable Active Low Power */ 1028 #define SYCC_FP 0x00000004 /**< ForcePLLOn */ 1029 #define SYCC_AR 0x00000008 /**< Force ALP (or HT if ALPen is not set */ 1030 #define SYCC_HR 0x00000010 /**< Force HT */ 1031 #define SYCC_CD_MASK 0xffff0000 /**< ClkDiv (ILP = 1/(4 * (divisor + 1)) */ 1032 #define SYCC_CD_SHIFT 16 1033 1034 /* Indirect backplane access */ 1035 #define BPIA_BYTEEN 0x0000000f 1036 #define BPIA_SZ1 0x00000001 1037 #define BPIA_SZ2 0x00000003 1038 #define BPIA_SZ4 0x00000007 1039 #define BPIA_SZ8 0x0000000f 1040 #define BPIA_WRITE 0x00000100 1041 #define BPIA_START 0x00000200 1042 #define BPIA_BUSY 0x00000200 1043 #define BPIA_ERROR 0x00000400 1044 1045 /* pcmcia/prog/flash_config */ 1046 #define CF_EN 0x00000001 /**< enable */ 1047 #define CF_EM_MASK 0x0000000e /**< mode */ 1048 #define CF_EM_SHIFT 1 1049 #define CF_EM_FLASH 0 /**< flash/asynchronous mode */ 1050 #define CF_EM_SYNC 2 /**< synchronous mode */ 1051 #define CF_EM_PCMCIA 4 /**< pcmcia mode */ 1052 #define CF_DS 0x00000010 /**< destsize: 0=8bit, 1=16bit */ 1053 #define CF_BS 0x00000020 /**< byteswap */ 1054 #define CF_CD_MASK 0x000000c0 /**< clock divider */ 1055 #define CF_CD_SHIFT 6 1056 #define CF_CD_DIV2 0x00000000 /**< backplane/2 */ 1057 #define CF_CD_DIV3 0x00000040 /**< backplane/3 */ 1058 #define CF_CD_DIV4 0x00000080 /**< backplane/4 */ 1059 #define CF_CE 0x00000100 /**< clock enable */ 1060 #define CF_SB 0x00000200 /**< size/bytestrobe (synch only) */ 1061 1062 /* pcmcia_memwait */ 1063 #define PM_W0_MASK 0x0000003f /**< waitcount0 */ 1064 #define PM_W1_MASK 0x00001f00 /**< waitcount1 */ 1065 #define PM_W1_SHIFT 8 1066 #define PM_W2_MASK 0x001f0000 /**< waitcount2 */ 1067 #define PM_W2_SHIFT 16 1068 #define PM_W3_MASK 0x1f000000 /**< waitcount3 */ 1069 #define PM_W3_SHIFT 24 1070 1071 /* pcmcia_attrwait */ 1072 #define PA_W0_MASK 0x0000003f /**< waitcount0 */ 1073 #define PA_W1_MASK 0x00001f00 /**< waitcount1 */ 1074 #define PA_W1_SHIFT 8 1075 #define PA_W2_MASK 0x001f0000 /**< waitcount2 */ 1076 #define PA_W2_SHIFT 16 1077 #define PA_W3_MASK 0x1f000000 /**< waitcount3 */ 1078 #define PA_W3_SHIFT 24 1079 1080 /* pcmcia_iowait */ 1081 #define PI_W0_MASK 0x0000003f /**< waitcount0 */ 1082 #define PI_W1_MASK 0x00001f00 /**< waitcount1 */ 1083 #define PI_W1_SHIFT 8 1084 #define PI_W2_MASK 0x001f0000 /**< waitcount2 */ 1085 #define PI_W2_SHIFT 16 1086 #define PI_W3_MASK 0x1f000000 /**< waitcount3 */ 1087 #define PI_W3_SHIFT 24 1088 1089 /* prog_waitcount */ 1090 #define PW_W0_MASK 0x0000001f /**< waitcount0 */ 1091 #define PW_W1_MASK 0x00001f00 /**< waitcount1 */ 1092 #define PW_W1_SHIFT 8 1093 #define PW_W2_MASK 0x001f0000 /**< waitcount2 */ 1094 #define PW_W2_SHIFT 16 1095 #define PW_W3_MASK 0x1f000000 /**< waitcount3 */ 1096 #define PW_W3_SHIFT 24 1097 1098 #define PW_W0 0x0000000c 1099 #define PW_W1 0x00000a00 1100 #define PW_W2 0x00020000 1101 #define PW_W3 0x01000000 1102 1103 /* flash_waitcount */ 1104 #define FW_W0_MASK 0x0000003f /**< waitcount0 */ 1105 #define FW_W1_MASK 0x00001f00 /**< waitcount1 */ 1106 #define FW_W1_SHIFT 8 1107 #define FW_W2_MASK 0x001f0000 /**< waitcount2 */ 1108 #define FW_W2_SHIFT 16 1109 #define FW_W3_MASK 0x1f000000 /**< waitcount3 */ 1110 #define FW_W3_SHIFT 24 1111 1112 /* When Srom support present, fields in sromcontrol */ 1113 #define SRC_START 0x80000000 1114 #define SRC_BUSY 0x80000000 1115 #define SRC_OPCODE 0x60000000 1116 #define SRC_OP_READ 0x00000000 1117 #define SRC_OP_WRITE 0x20000000 1118 #define SRC_OP_WRDIS 0x40000000 1119 #define SRC_OP_WREN 0x60000000 1120 #define SRC_OTPSEL 0x00000010 1121 #define SRC_OTPPRESENT 0x00000020 1122 #define SRC_LOCK 0x00000008 1123 #define SRC_SIZE_MASK 0x00000006 1124 #define SRC_SIZE_1K 0x00000000 1125 #define SRC_SIZE_4K 0x00000002 1126 #define SRC_SIZE_16K 0x00000004 1127 #define SRC_SIZE_SHIFT 1 1128 #define SRC_PRESENT 0x00000001 1129 1130 /* Fields in pmucontrol */ 1131 #define PCTL_ILP_DIV_MASK 0xffff0000 1132 #define PCTL_ILP_DIV_SHIFT 16 1133 #define PCTL_LQ_REQ_EN 0x00008000 1134 #define PCTL_PLL_PLLCTL_UPD 0x00000400 /**< rev 2 */ 1135 #define PCTL_NOILP_ON_WAIT 0x00000200 /**< rev 1 */ 1136 #define PCTL_HT_REQ_EN 0x00000100 1137 #define PCTL_ALP_REQ_EN 0x00000080 1138 #define PCTL_XTALFREQ_MASK 0x0000007c 1139 #define PCTL_XTALFREQ_SHIFT 2 1140 #define PCTL_ILP_DIV_EN 0x00000002 1141 #define PCTL_LPO_SEL 0x00000001 1142 1143 /* Fields in pmucontrol_ext */ 1144 #define PCTL_EXT_FASTLPO_ENAB 0x00000080 1145 #define PCTL_EXT_FASTLPO_SWENAB 0x00000200 1146 #define PCTL_EXT_FASTLPO_PCIE_SWENAB 0x00004000 /**< rev33 for FLL1M */ 1147 1148 #define DEFAULT_43012_MIN_RES_MASK 0x0f8bfe77 1149 1150 /* Retention Control */ 1151 #define PMU_RCTL_CLK_DIV_SHIFT 0 1152 #define PMU_RCTL_CHAIN_LEN_SHIFT 12 1153 #define PMU_RCTL_MACPHY_DISABLE_SHIFT 26 1154 #define PMU_RCTL_MACPHY_DISABLE_MASK (1 << 26) 1155 #define PMU_RCTL_LOGIC_DISABLE_SHIFT 27 1156 #define PMU_RCTL_LOGIC_DISABLE_MASK (1 << 27) 1157 #define PMU_RCTL_MEMSLP_LOG_SHIFT 28 1158 #define PMU_RCTL_MEMSLP_LOG_MASK (1 << 28) 1159 #define PMU_RCTL_MEMRETSLP_LOG_SHIFT 29 1160 #define PMU_RCTL_MEMRETSLP_LOG_MASK (1 << 29) 1161 1162 /* Retention Group Control */ 1163 #define PMU_RCTLGRP_CHAIN_LEN_SHIFT 0 1164 #define PMU_RCTLGRP_RMODE_ENABLE_SHIFT 14 1165 #define PMU_RCTLGRP_RMODE_ENABLE_MASK (1 << 14) 1166 #define PMU_RCTLGRP_DFT_ENABLE_SHIFT 15 1167 #define PMU_RCTLGRP_DFT_ENABLE_MASK (1 << 15) 1168 #define PMU_RCTLGRP_NSRST_DISABLE_SHIFT 16 1169 #define PMU_RCTLGRP_NSRST_DISABLE_MASK (1 << 16) 1170 /* Retention Group Control special for 4334 */ 1171 #define PMU4334_RCTLGRP_CHAIN_LEN_GRP0 338 1172 #define PMU4334_RCTLGRP_CHAIN_LEN_GRP1 315 1173 /* Retention Group Control special for 43341 */ 1174 #define PMU43341_RCTLGRP_CHAIN_LEN_GRP0 366 1175 #define PMU43341_RCTLGRP_CHAIN_LEN_GRP1 330 1176 1177 /* Fields in clkstretch */ 1178 #define CSTRETCH_HT 0xffff0000 1179 #define CSTRETCH_ALP 0x0000ffff 1180 1181 /* gpiotimerval */ 1182 #define GPIO_ONTIME_SHIFT 16 1183 1184 /* clockcontrol_n */ 1185 #define CN_N1_MASK 0x3f /**< n1 control */ 1186 #define CN_N2_MASK 0x3f00 /**< n2 control */ 1187 #define CN_N2_SHIFT 8 1188 #define CN_PLLC_MASK 0xf0000 /**< pll control */ 1189 #define CN_PLLC_SHIFT 16 1190 1191 /* clockcontrol_sb/pci/uart */ 1192 #define CC_M1_MASK 0x3f /**< m1 control */ 1193 #define CC_M2_MASK 0x3f00 /**< m2 control */ 1194 #define CC_M2_SHIFT 8 1195 #define CC_M3_MASK 0x3f0000 /**< m3 control */ 1196 #define CC_M3_SHIFT 16 1197 #define CC_MC_MASK 0x1f000000 /**< mux control */ 1198 #define CC_MC_SHIFT 24 1199 1200 /* N3M Clock control magic field values */ 1201 #define CC_F6_2 0x02 /**< A factor of 2 in */ 1202 #define CC_F6_3 0x03 /**< 6-bit fields like */ 1203 #define CC_F6_4 0x05 /**< N1, M1 or M3 */ 1204 #define CC_F6_5 0x09 1205 #define CC_F6_6 0x11 1206 #define CC_F6_7 0x21 1207 1208 #define CC_F5_BIAS 5 /**< 5-bit fields get this added */ 1209 1210 #define CC_MC_BYPASS 0x08 1211 #define CC_MC_M1 0x04 1212 #define CC_MC_M1M2 0x02 1213 #define CC_MC_M1M2M3 0x01 1214 #define CC_MC_M1M3 0x11 1215 1216 /* Type 2 Clock control magic field values */ 1217 #define CC_T2_BIAS 2 /**< n1, n2, m1 & m3 bias */ 1218 #define CC_T2M2_BIAS 3 /**< m2 bias */ 1219 1220 #define CC_T2MC_M1BYP 1 1221 #define CC_T2MC_M2BYP 2 1222 #define CC_T2MC_M3BYP 4 1223 1224 /* Type 6 Clock control magic field values */ 1225 #define CC_T6_MMASK 1 /**< bits of interest in m */ 1226 #define CC_T6_M0 120000000 /**< sb clock for m = 0 */ 1227 #define CC_T6_M1 100000000 /**< sb clock for m = 1 */ 1228 #define SB2MIPS_T6(sb) (2 * (sb)) 1229 1230 /* Common clock base */ 1231 #define CC_CLOCK_BASE1 24000000 /**< Half the clock freq */ 1232 #define CC_CLOCK_BASE2 12500000 /**< Alternate crystal on some PLLs */ 1233 1234 /* Clock control values for 200MHz in 5350 */ 1235 #define CLKC_5350_N 0x0311 1236 #define CLKC_5350_M 0x04020009 1237 1238 /* Flash types in the chipcommon capabilities register */ 1239 #define FLASH_NONE 0x000 /**< No flash */ 1240 #define SFLASH_ST 0x100 /**< ST serial flash */ 1241 #define SFLASH_AT 0x200 /**< Atmel serial flash */ 1242 #define NFLASH 0x300 1243 #define PFLASH 0x700 /**< Parallel flash */ 1244 #define QSPIFLASH_ST 0x800 1245 #define QSPIFLASH_AT 0x900 1246 1247 /* Bits in the ExtBus config registers */ 1248 #define CC_CFG_EN 0x0001 /**< Enable */ 1249 #define CC_CFG_EM_MASK 0x000e /**< Extif Mode */ 1250 #define CC_CFG_EM_ASYNC 0x0000 /**< Async/Parallel flash */ 1251 #define CC_CFG_EM_SYNC 0x0002 /**< Synchronous */ 1252 #define CC_CFG_EM_PCMCIA 0x0004 /**< PCMCIA */ 1253 #define CC_CFG_EM_IDE 0x0006 /**< IDE */ 1254 #define CC_CFG_DS 0x0010 /**< Data size, 0=8bit, 1=16bit */ 1255 #define CC_CFG_CD_MASK 0x00e0 /**< Sync: Clock divisor, rev >= 20 */ 1256 #define CC_CFG_CE 0x0100 /**< Sync: Clock enable, rev >= 20 */ 1257 #define CC_CFG_SB 0x0200 /**< Sync: Size/Bytestrobe, rev >= 20 */ 1258 #define CC_CFG_IS 0x0400 /**< Extif Sync Clk Select, rev >= 20 */ 1259 1260 /* ExtBus address space */ 1261 #define CC_EB_BASE 0x1a000000 /**< Chipc ExtBus base address */ 1262 #define CC_EB_PCMCIA_MEM 0x1a000000 /**< PCMCIA 0 memory base address */ 1263 #define CC_EB_PCMCIA_IO 0x1a200000 /**< PCMCIA 0 I/O base address */ 1264 #define CC_EB_PCMCIA_CFG 0x1a400000 /**< PCMCIA 0 config base address */ 1265 #define CC_EB_IDE 0x1a800000 /**< IDE memory base */ 1266 #define CC_EB_PCMCIA1_MEM 0x1a800000 /**< PCMCIA 1 memory base address */ 1267 #define CC_EB_PCMCIA1_IO 0x1aa00000 /**< PCMCIA 1 I/O base address */ 1268 #define CC_EB_PCMCIA1_CFG 0x1ac00000 /**< PCMCIA 1 config base address */ 1269 #define CC_EB_PROGIF 0x1b000000 /**< ProgIF Async/Sync base address */ 1270 1271 1272 /* Start/busy bit in flashcontrol */ 1273 #define SFLASH_OPCODE 0x000000ff 1274 #define SFLASH_ACTION 0x00000700 1275 #define SFLASH_CS_ACTIVE 0x00001000 /**< Chip Select Active, rev >= 20 */ 1276 #define SFLASH_START 0x80000000 1277 #define SFLASH_BUSY SFLASH_START 1278 1279 /* flashcontrol action codes */ 1280 #define SFLASH_ACT_OPONLY 0x0000 /**< Issue opcode only */ 1281 #define SFLASH_ACT_OP1D 0x0100 /**< opcode + 1 data byte */ 1282 #define SFLASH_ACT_OP3A 0x0200 /**< opcode + 3 addr bytes */ 1283 #define SFLASH_ACT_OP3A1D 0x0300 /**< opcode + 3 addr & 1 data bytes */ 1284 #define SFLASH_ACT_OP3A4D 0x0400 /**< opcode + 3 addr & 4 data bytes */ 1285 #define SFLASH_ACT_OP3A4X4D 0x0500 /**< opcode + 3 addr, 4 don't care & 4 data bytes */ 1286 #define SFLASH_ACT_OP3A1X4D 0x0700 /**< opcode + 3 addr, 1 don't care & 4 data bytes */ 1287 1288 /* flashcontrol action+opcodes for ST flashes */ 1289 #define SFLASH_ST_WREN 0x0006 /**< Write Enable */ 1290 #define SFLASH_ST_WRDIS 0x0004 /**< Write Disable */ 1291 #define SFLASH_ST_RDSR 0x0105 /**< Read Status Register */ 1292 #define SFLASH_ST_WRSR 0x0101 /**< Write Status Register */ 1293 #define SFLASH_ST_READ 0x0303 /**< Read Data Bytes */ 1294 #define SFLASH_ST_PP 0x0302 /**< Page Program */ 1295 #define SFLASH_ST_SE 0x02d8 /**< Sector Erase */ 1296 #define SFLASH_ST_BE 0x00c7 /**< Bulk Erase */ 1297 #define SFLASH_ST_DP 0x00b9 /**< Deep Power-down */ 1298 #define SFLASH_ST_RES 0x03ab /**< Read Electronic Signature */ 1299 #define SFLASH_ST_CSA 0x1000 /**< Keep chip select asserted */ 1300 #define SFLASH_ST_SSE 0x0220 /**< Sub-sector Erase */ 1301 1302 #define SFLASH_ST_READ4B 0x6313 /* Read Data Bytes in 4Byte address */ 1303 #define SFLASH_ST_PP4B 0x6312 /* Page Program in 4Byte address */ 1304 #define SFLASH_ST_SE4B 0x62dc /* Sector Erase in 4Byte address */ 1305 #define SFLASH_ST_SSE4B 0x6221 /* Sub-sector Erase */ 1306 1307 #define SFLASH_MXIC_RDID 0x0390 /* Read Manufacture ID */ 1308 #define SFLASH_MXIC_MFID 0xc2 /* MXIC Manufacture ID */ 1309 1310 /* Status register bits for ST flashes */ 1311 #define SFLASH_ST_WIP 0x01 /**< Write In Progress */ 1312 #define SFLASH_ST_WEL 0x02 /**< Write Enable Latch */ 1313 #define SFLASH_ST_BP_MASK 0x1c /**< Block Protect */ 1314 #define SFLASH_ST_BP_SHIFT 2 1315 #define SFLASH_ST_SRWD 0x80 /**< Status Register Write Disable */ 1316 1317 /* flashcontrol action+opcodes for Atmel flashes */ 1318 #define SFLASH_AT_READ 0x07e8 1319 #define SFLASH_AT_PAGE_READ 0x07d2 1320 #define SFLASH_AT_BUF1_READ 1321 #define SFLASH_AT_BUF2_READ 1322 #define SFLASH_AT_STATUS 0x01d7 1323 #define SFLASH_AT_BUF1_WRITE 0x0384 1324 #define SFLASH_AT_BUF2_WRITE 0x0387 1325 #define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283 1326 #define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286 1327 #define SFLASH_AT_BUF1_PROGRAM 0x0288 1328 #define SFLASH_AT_BUF2_PROGRAM 0x0289 1329 #define SFLASH_AT_PAGE_ERASE 0x0281 1330 #define SFLASH_AT_BLOCK_ERASE 0x0250 1331 #define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382 1332 #define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385 1333 #define SFLASH_AT_BUF1_LOAD 0x0253 1334 #define SFLASH_AT_BUF2_LOAD 0x0255 1335 #define SFLASH_AT_BUF1_COMPARE 0x0260 1336 #define SFLASH_AT_BUF2_COMPARE 0x0261 1337 #define SFLASH_AT_BUF1_REPROGRAM 0x0258 1338 #define SFLASH_AT_BUF2_REPROGRAM 0x0259 1339 1340 /* Status register bits for Atmel flashes */ 1341 #define SFLASH_AT_READY 0x80 1342 #define SFLASH_AT_MISMATCH 0x40 1343 #define SFLASH_AT_ID_MASK 0x38 1344 #define SFLASH_AT_ID_SHIFT 3 1345 1346 /* SPI register bits, corerev >= 37 */ 1347 #define GSIO_START 0x80000000 1348 #define GSIO_BUSY GSIO_START 1349 1350 /* 1351 * These are the UART port assignments, expressed as offsets from the base 1352 * register. These assignments should hold for any serial port based on 1353 * a 8250, 16450, or 16550(A). 1354 */ 1355 1356 #define UART_RX 0 /**< In: Receive buffer (DLAB=0) */ 1357 #define UART_TX 0 /**< Out: Transmit buffer (DLAB=0) */ 1358 #define UART_DLL 0 /**< Out: Divisor Latch Low (DLAB=1) */ 1359 #define UART_IER 1 /**< In/Out: Interrupt Enable Register (DLAB=0) */ 1360 #define UART_DLM 1 /**< Out: Divisor Latch High (DLAB=1) */ 1361 #define UART_IIR 2 /**< In: Interrupt Identity Register */ 1362 #define UART_FCR 2 /**< Out: FIFO Control Register */ 1363 #define UART_LCR 3 /**< Out: Line Control Register */ 1364 #define UART_MCR 4 /**< Out: Modem Control Register */ 1365 #define UART_LSR 5 /**< In: Line Status Register */ 1366 #define UART_MSR 6 /**< In: Modem Status Register */ 1367 #define UART_SCR 7 /**< I/O: Scratch Register */ 1368 #define UART_LCR_DLAB 0x80 /**< Divisor latch access bit */ 1369 #define UART_LCR_WLEN8 0x03 /**< Word length: 8 bits */ 1370 #define UART_MCR_OUT2 0x08 /**< MCR GPIO out 2 */ 1371 #define UART_MCR_LOOP 0x10 /**< Enable loopback test mode */ 1372 #define UART_LSR_RX_FIFO 0x80 /**< Receive FIFO error */ 1373 #define UART_LSR_TDHR 0x40 /**< Data-hold-register empty */ 1374 #define UART_LSR_THRE 0x20 /**< Transmit-hold-register empty */ 1375 #define UART_LSR_BREAK 0x10 /**< Break interrupt */ 1376 #define UART_LSR_FRAMING 0x08 /**< Framing error */ 1377 #define UART_LSR_PARITY 0x04 /**< Parity error */ 1378 #define UART_LSR_OVERRUN 0x02 /**< Overrun error */ 1379 #define UART_LSR_RXRDY 0x01 /**< Receiver ready */ 1380 #define UART_FCR_FIFO_ENABLE 1 /**< FIFO control register bit controlling FIFO enable/disable */ 1381 1382 /* Interrupt Identity Register (IIR) bits */ 1383 #define UART_IIR_FIFO_MASK 0xc0 /**< IIR FIFO disable/enabled mask */ 1384 #define UART_IIR_INT_MASK 0xf /**< IIR interrupt ID source */ 1385 #define UART_IIR_MDM_CHG 0x0 /**< Modem status changed */ 1386 #define UART_IIR_NOINT 0x1 /**< No interrupt pending */ 1387 #define UART_IIR_THRE 0x2 /**< THR empty */ 1388 #define UART_IIR_RCVD_DATA 0x4 /**< Received data available */ 1389 #define UART_IIR_RCVR_STATUS 0x6 /**< Receiver status */ 1390 #define UART_IIR_CHAR_TIME 0xc /**< Character time */ 1391 1392 /* Interrupt Enable Register (IER) bits */ 1393 #define UART_IER_PTIME 128 /**< Programmable THRE Interrupt Mode Enable */ 1394 #define UART_IER_EDSSI 8 /**< enable modem status interrupt */ 1395 #define UART_IER_ELSI 4 /**< enable receiver line status interrupt */ 1396 #define UART_IER_ETBEI 2 /**< enable transmitter holding register empty interrupt */ 1397 #define UART_IER_ERBFI 1 /**< enable data available interrupt */ 1398 1399 /* pmustatus */ 1400 #define PST_SLOW_WR_PENDING 0x0400 1401 #define PST_EXTLPOAVAIL 0x0100 1402 #define PST_WDRESET 0x0080 1403 #define PST_INTPEND 0x0040 1404 #define PST_SBCLKST 0x0030 1405 #define PST_SBCLKST_ILP 0x0010 1406 #define PST_SBCLKST_ALP 0x0020 1407 #define PST_SBCLKST_HT 0x0030 1408 #define PST_ALPAVAIL 0x0008 1409 #define PST_HTAVAIL 0x0004 1410 #define PST_RESINIT 0x0003 1411 #define PST_ILPFASTLPO 0x00010000 1412 1413 /* pmucapabilities */ 1414 #define PCAP_REV_MASK 0x000000ff 1415 #define PCAP_RC_MASK 0x00001f00 1416 #define PCAP_RC_SHIFT 8 1417 #define PCAP_TC_MASK 0x0001e000 1418 #define PCAP_TC_SHIFT 13 1419 #define PCAP_PC_MASK 0x001e0000 1420 #define PCAP_PC_SHIFT 17 1421 #define PCAP_VC_MASK 0x01e00000 1422 #define PCAP_VC_SHIFT 21 1423 #define PCAP_CC_MASK 0x1e000000 1424 #define PCAP_CC_SHIFT 25 1425 #define PCAP5_PC_MASK 0x003e0000 /**< PMU corerev >= 5 */ 1426 #define PCAP5_PC_SHIFT 17 1427 #define PCAP5_VC_MASK 0x07c00000 1428 #define PCAP5_VC_SHIFT 22 1429 #define PCAP5_CC_MASK 0xf8000000 1430 #define PCAP5_CC_SHIFT 27 1431 1432 /* CoreCapabilitiesExtension */ 1433 #define PCAP_EXT_USE_MUXED_ILP_CLK_MASK 0x04000000 1434 1435 /* PMU Resource Request Timer registers */ 1436 /* This is based on PmuRev0 */ 1437 #define PRRT_TIME_MASK 0x03ff 1438 #define PRRT_INTEN 0x0400 1439 #define PRRT_REQ_ACTIVE 0x0800 1440 #define PRRT_ALP_REQ 0x1000 1441 #define PRRT_HT_REQ 0x2000 1442 #define PRRT_HQ_REQ 0x4000 1443 1444 /* PMU Int Control register bits */ 1445 #define PMU_INTC_ALP_REQ 0x1 1446 #define PMU_INTC_HT_REQ 0x2 1447 #define PMU_INTC_HQ_REQ 0x4 1448 1449 /* bit 0 of the PMU interrupt vector is asserted if this mask is enabled */ 1450 #define RSRC_INTR_MASK_TIMER_INT_0 1 1451 1452 /* PMU resource bit position */ 1453 #define PMURES_BIT(bit) (1 << (bit)) 1454 1455 /* PMU resource number limit */ 1456 #define PMURES_MAX_RESNUM 30 1457 1458 /* PMU chip control0 register */ 1459 #define PMU_CHIPCTL0 0 1460 #define PMU43143_CC0_SDIO_DRSTR_OVR (1 << 31) /* sdio drive strength override enable */ 1461 1462 /* clock req types */ 1463 #define PMU_CC1_CLKREQ_TYPE_SHIFT 19 1464 #define PMU_CC1_CLKREQ_TYPE_MASK (1 << PMU_CC1_CLKREQ_TYPE_SHIFT) 1465 1466 #define CLKREQ_TYPE_CONFIG_OPENDRAIN 0 1467 #define CLKREQ_TYPE_CONFIG_PUSHPULL 1 1468 1469 /* PMU chip control1 register */ 1470 #define PMU_CHIPCTL1 1 1471 #define PMU_CC1_RXC_DLL_BYPASS 0x00010000 1472 #define PMU_CC1_ENABLE_BBPLL_PWR_DOWN 0x00000010 1473 1474 #define PMU_CC1_IF_TYPE_MASK 0x00000030 1475 #define PMU_CC1_IF_TYPE_RMII 0x00000000 1476 #define PMU_CC1_IF_TYPE_MII 0x00000010 1477 #define PMU_CC1_IF_TYPE_RGMII 0x00000020 1478 1479 #define PMU_CC1_SW_TYPE_MASK 0x000000c0 1480 #define PMU_CC1_SW_TYPE_EPHY 0x00000000 1481 #define PMU_CC1_SW_TYPE_EPHYMII 0x00000040 1482 #define PMU_CC1_SW_TYPE_EPHYRMII 0x00000080 1483 #define PMU_CC1_SW_TYPE_RGMII 0x000000c0 1484 1485 #define PMU_CC1_ENABLE_CLOSED_LOOP_MASK 0x00000080 1486 #define PMU_CC1_ENABLE_CLOSED_LOOP 0x00000000 1487 1488 /* PMU chip control2 register */ 1489 #define PMU_CC2_RFLDO3P3_PU_FORCE_ON (1 << 15) 1490 #define PMU_CC2_RFLDO3P3_PU_CLEAR 0x00000000 1491 1492 #define PMU_CC2_WL2CDIG_I_PMU_SLEEP (1 << 16) 1493 #define PMU_CHIPCTL2 2 1494 #define PMU_CC2_FORCE_SUBCORE_PWR_SWITCH_ON (1 << 18) 1495 #define PMU_CC2_FORCE_PHY_PWR_SWITCH_ON (1 << 19) 1496 #define PMU_CC2_FORCE_VDDM_PWR_SWITCH_ON (1 << 20) 1497 #define PMU_CC2_FORCE_MEMLPLDO_PWR_SWITCH_ON (1 << 21) 1498 #define PMU_CC2_MASK_WL_DEV_WAKE (1 << 22) 1499 #define PMU_CC2_INV_GPIO_POLARITY_PMU_WAKE (1 << 25) 1500 #define PMU_CC2_GCI2_WAKE (1 << 31) 1501 1502 /* PMU chip control3 register */ 1503 #define PMU_CHIPCTL3 3 1504 #define PMU_CC3_ENABLE_SDIO_WAKEUP_SHIFT 19 1505 #define PMU_CC3_ENABLE_RF_SHIFT 22 1506 #define PMU_CC3_RF_DISABLE_IVALUE_SHIFT 23 1507 1508 /* PMU chip control4 register */ 1509 #define PMU_CHIPCTL4 4 1510 1511 /* 53537 series moved switch_type and gmac_if_type to CC4 [15:14] and [13:12] */ 1512 #define PMU_CC4_IF_TYPE_MASK 0x00003000 1513 #define PMU_CC4_IF_TYPE_RMII 0x00000000 1514 #define PMU_CC4_IF_TYPE_MII 0x00001000 1515 #define PMU_CC4_IF_TYPE_RGMII 0x00002000 1516 1517 #define PMU_CC4_SW_TYPE_MASK 0x0000c000 1518 #define PMU_CC4_SW_TYPE_EPHY 0x00000000 1519 #define PMU_CC4_SW_TYPE_EPHYMII 0x00004000 1520 #define PMU_CC4_SW_TYPE_EPHYRMII 0x00008000 1521 #define PMU_CC4_SW_TYPE_RGMII 0x0000c000 1522 #define PMU_CC4_DISABLE_LQ_AVAIL (1<<27) 1523 1524 /* PMU chip control5 register */ 1525 #define PMU_CHIPCTL5 5 1526 1527 /* PMU chip control6 register */ 1528 #define PMU_CHIPCTL6 6 1529 #define PMU_CC6_ENABLE_CLKREQ_WAKEUP (1 << 4) 1530 #define PMU_CC6_ENABLE_PMU_WAKEUP_ALP (1 << 6) 1531 1532 /* PMU chip control7 register */ 1533 #define PMU_CHIPCTL7 7 1534 #define PMU_CC7_ENABLE_L2REFCLKPAD_PWRDWN (1 << 25) 1535 #define PMU_CC7_ENABLE_MDIO_RESET_WAR (1 << 27) 1536 /* 53537 series have gmca1 gmac_if_type in cc7 [7:6](defalut 0b01) */ 1537 #define PMU_CC7_IF_TYPE_MASK 0x000000c0 1538 #define PMU_CC7_IF_TYPE_RMII 0x00000000 1539 #define PMU_CC7_IF_TYPE_MII 0x00000040 1540 #define PMU_CC7_IF_TYPE_RGMII 0x00000080 1541 1542 #define PMU_CHIPCTL8 8 1543 #define PMU_CHIPCTL9 9 1544 1545 /* PMU corerev and chip specific PLL controls. 1546 * PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary number 1547 * to differentiate different PLLs controlled by the same PMU rev. 1548 */ 1549 /* pllcontrol registers */ 1550 /* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */ 1551 #define PMU0_PLL0_PLLCTL0 0 1552 #define PMU0_PLL0_PC0_PDIV_MASK 1 1553 #define PMU0_PLL0_PC0_PDIV_FREQ 25000 1554 #define PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038 1555 #define PMU0_PLL0_PC0_DIV_ARM_SHIFT 3 1556 #define PMU0_PLL0_PC0_DIV_ARM_BASE 8 1557 1558 /* PC0_DIV_ARM for PLLOUT_ARM */ 1559 #define PMU0_PLL0_PC0_DIV_ARM_110MHZ 0 1560 #define PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1 1561 #define PMU0_PLL0_PC0_DIV_ARM_88MHZ 2 1562 #define PMU0_PLL0_PC0_DIV_ARM_80MHZ 3 /* Default */ 1563 #define PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4 1564 #define PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5 1565 #define PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6 1566 #define PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7 1567 1568 /* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */ 1569 #define PMU0_PLL0_PLLCTL1 1 1570 #define PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000 1571 #define PMU0_PLL0_PC1_WILD_INT_SHIFT 28 1572 #define PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00 1573 #define PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8 1574 #define PMU0_PLL0_PC1_STOP_MOD 0x00000040 1575 1576 /* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */ 1577 #define PMU0_PLL0_PLLCTL2 2 1578 #define PMU0_PLL0_PC2_WILD_INT_MASK 0xf 1579 #define PMU0_PLL0_PC2_WILD_INT_SHIFT 4 1580 1581 /* pllcontrol registers */ 1582 /* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */ 1583 #define PMU1_PLL0_PLLCTL0 0 1584 #define PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000 1585 #define PMU1_PLL0_PC0_P1DIV_SHIFT 20 1586 #define PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000 1587 #define PMU1_PLL0_PC0_P2DIV_SHIFT 24 1588 1589 /* m<x>div */ 1590 #define PMU1_PLL0_PLLCTL1 1 1591 #define PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff 1592 #define PMU1_PLL0_PC1_M1DIV_SHIFT 0 1593 #define PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00 1594 #define PMU1_PLL0_PC1_M2DIV_SHIFT 8 1595 #define PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000 1596 #define PMU1_PLL0_PC1_M3DIV_SHIFT 16 1597 #define PMU1_PLL0_PC1_M4DIV_MASK 0xff000000 1598 #define PMU1_PLL0_PC1_M4DIV_SHIFT 24 1599 #define PMU1_PLL0_PC1_M4DIV_BY_9 9 1600 #define PMU1_PLL0_PC1_M4DIV_BY_18 0x12 1601 #define PMU1_PLL0_PC1_M4DIV_BY_36 0x24 1602 #define PMU1_PLL0_PC1_M4DIV_BY_60 0x3C 1603 1604 #define DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT 8 1605 #define DOT11MAC_880MHZ_CLK_DIVISOR_MASK (0xFF << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) 1606 #define DOT11MAC_880MHZ_CLK_DIVISOR_VAL (0xE << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) 1607 1608 /* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */ 1609 #define PMU1_PLL0_PLLCTL2 2 1610 #define PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff 1611 #define PMU1_PLL0_PC2_M5DIV_SHIFT 0 1612 #define PMU1_PLL0_PC2_M5DIV_BY_12 0xc 1613 #define PMU1_PLL0_PC2_M5DIV_BY_18 0x12 1614 #define PMU1_PLL0_PC2_M5DIV_BY_31 0x1f 1615 #define PMU1_PLL0_PC2_M5DIV_BY_36 0x24 1616 #define PMU1_PLL0_PC2_M5DIV_BY_42 0x2a 1617 #define PMU1_PLL0_PC2_M5DIV_BY_60 0x3c 1618 #define PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00 1619 #define PMU1_PLL0_PC2_M6DIV_SHIFT 8 1620 #define PMU1_PLL0_PC2_M6DIV_BY_18 0x12 1621 #define PMU1_PLL0_PC2_M6DIV_BY_36 0x24 1622 #define PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000 1623 #define PMU1_PLL0_PC2_NDIV_MODE_SHIFT 17 1624 #define PMU1_PLL0_PC2_NDIV_MODE_MASH 1 1625 #define PMU1_PLL0_PC2_NDIV_MODE_MFB 2 /**< recommended for 4319 */ 1626 #define PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000 1627 #define PMU1_PLL0_PC2_NDIV_INT_SHIFT 20 1628 1629 /* ndiv_frac */ 1630 #define PMU1_PLL0_PLLCTL3 3 1631 #define PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff 1632 #define PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0 1633 1634 /* pll_ctrl */ 1635 #define PMU1_PLL0_PLLCTL4 4 1636 1637 /* pll_ctrl, vco_rng, clkdrive_ch<x> */ 1638 #define PMU1_PLL0_PLLCTL5 5 1639 #define PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00 1640 #define PMU1_PLL0_PC5_CLK_DRV_SHIFT 8 1641 #define PMU1_PLL0_PC5_ASSERT_CH_MASK 0x3f000000 1642 #define PMU1_PLL0_PC5_ASSERT_CH_SHIFT 24 1643 #define PMU1_PLL0_PC5_DEASSERT_CH_MASK 0xff000000 1644 1645 #define PMU1_PLL0_PLLCTL6 6 1646 #define PMU1_PLL0_PLLCTL7 7 1647 #define PMU1_PLL0_PLLCTL8 8 1648 1649 #define PMU1_PLLCTL8_OPENLOOP_MASK (1 << 1) 1650 #define PMU_PLL4350_OPENLOOP_MASK (1 << 7) 1651 1652 #define PMU1_PLL0_PLLCTL9 9 1653 1654 #define PMU1_PLL0_PLLCTL10 10 1655 1656 /* PMU rev 2 control words */ 1657 #define PMU2_PHY_PLL_PLLCTL 4 1658 #define PMU2_SI_PLL_PLLCTL 10 1659 1660 /* PMU rev 2 */ 1661 /* pllcontrol registers */ 1662 /* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */ 1663 #define PMU2_PLL_PLLCTL0 0 1664 #define PMU2_PLL_PC0_P1DIV_MASK 0x00f00000 1665 #define PMU2_PLL_PC0_P1DIV_SHIFT 20 1666 #define PMU2_PLL_PC0_P2DIV_MASK 0x0f000000 1667 #define PMU2_PLL_PC0_P2DIV_SHIFT 24 1668 1669 /* m<x>div */ 1670 #define PMU2_PLL_PLLCTL1 1 1671 #define PMU2_PLL_PC1_M1DIV_MASK 0x000000ff 1672 #define PMU2_PLL_PC1_M1DIV_SHIFT 0 1673 #define PMU2_PLL_PC1_M2DIV_MASK 0x0000ff00 1674 #define PMU2_PLL_PC1_M2DIV_SHIFT 8 1675 #define PMU2_PLL_PC1_M3DIV_MASK 0x00ff0000 1676 #define PMU2_PLL_PC1_M3DIV_SHIFT 16 1677 #define PMU2_PLL_PC1_M4DIV_MASK 0xff000000 1678 #define PMU2_PLL_PC1_M4DIV_SHIFT 24 1679 1680 /* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */ 1681 #define PMU2_PLL_PLLCTL2 2 1682 #define PMU2_PLL_PC2_M5DIV_MASK 0x000000ff 1683 #define PMU2_PLL_PC2_M5DIV_SHIFT 0 1684 #define PMU2_PLL_PC2_M6DIV_MASK 0x0000ff00 1685 #define PMU2_PLL_PC2_M6DIV_SHIFT 8 1686 #define PMU2_PLL_PC2_NDIV_MODE_MASK 0x000e0000 1687 #define PMU2_PLL_PC2_NDIV_MODE_SHIFT 17 1688 #define PMU2_PLL_PC2_NDIV_INT_MASK 0x1ff00000 1689 #define PMU2_PLL_PC2_NDIV_INT_SHIFT 20 1690 1691 /* ndiv_frac */ 1692 #define PMU2_PLL_PLLCTL3 3 1693 #define PMU2_PLL_PC3_NDIV_FRAC_MASK 0x00ffffff 1694 #define PMU2_PLL_PC3_NDIV_FRAC_SHIFT 0 1695 1696 /* pll_ctrl */ 1697 #define PMU2_PLL_PLLCTL4 4 1698 1699 /* pll_ctrl, vco_rng, clkdrive_ch<x> */ 1700 #define PMU2_PLL_PLLCTL5 5 1701 #define PMU2_PLL_PC5_CLKDRIVE_CH1_MASK 0x00000f00 1702 #define PMU2_PLL_PC5_CLKDRIVE_CH1_SHIFT 8 1703 #define PMU2_PLL_PC5_CLKDRIVE_CH2_MASK 0x0000f000 1704 #define PMU2_PLL_PC5_CLKDRIVE_CH2_SHIFT 12 1705 #define PMU2_PLL_PC5_CLKDRIVE_CH3_MASK 0x000f0000 1706 #define PMU2_PLL_PC5_CLKDRIVE_CH3_SHIFT 16 1707 #define PMU2_PLL_PC5_CLKDRIVE_CH4_MASK 0x00f00000 1708 #define PMU2_PLL_PC5_CLKDRIVE_CH4_SHIFT 20 1709 #define PMU2_PLL_PC5_CLKDRIVE_CH5_MASK 0x0f000000 1710 #define PMU2_PLL_PC5_CLKDRIVE_CH5_SHIFT 24 1711 #define PMU2_PLL_PC5_CLKDRIVE_CH6_MASK 0xf0000000 1712 #define PMU2_PLL_PC5_CLKDRIVE_CH6_SHIFT 28 1713 1714 /* PMU rev 5 (& 6) */ 1715 #define PMU5_PLL_P1P2_OFF 0 1716 #define PMU5_PLL_P1_MASK 0x0f000000 1717 #define PMU5_PLL_P1_SHIFT 24 1718 #define PMU5_PLL_P2_MASK 0x00f00000 1719 #define PMU5_PLL_P2_SHIFT 20 1720 #define PMU5_PLL_M14_OFF 1 1721 #define PMU5_PLL_MDIV_MASK 0x000000ff 1722 #define PMU5_PLL_MDIV_WIDTH 8 1723 #define PMU5_PLL_NM5_OFF 2 1724 #define PMU5_PLL_NDIV_MASK 0xfff00000 1725 #define PMU5_PLL_NDIV_SHIFT 20 1726 #define PMU5_PLL_NDIV_MODE_MASK 0x000e0000 1727 #define PMU5_PLL_NDIV_MODE_SHIFT 17 1728 #define PMU5_PLL_FMAB_OFF 3 1729 #define PMU5_PLL_MRAT_MASK 0xf0000000 1730 #define PMU5_PLL_MRAT_SHIFT 28 1731 #define PMU5_PLL_ABRAT_MASK 0x08000000 1732 #define PMU5_PLL_ABRAT_SHIFT 27 1733 #define PMU5_PLL_FDIV_MASK 0x07ffffff 1734 #define PMU5_PLL_PLLCTL_OFF 4 1735 #define PMU5_PLL_PCHI_OFF 5 1736 #define PMU5_PLL_PCHI_MASK 0x0000003f 1737 1738 /* pmu XtalFreqRatio */ 1739 #define PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF 1740 #define PMU_XTALFREQ_REG_MEASURE_MASK 0x80000000 1741 #define PMU_XTALFREQ_REG_MEASURE_SHIFT 31 1742 1743 /* Divider allocation in 4716/47162/5356/5357 */ 1744 #define PMU5_MAINPLL_CPU 1 1745 #define PMU5_MAINPLL_MEM 2 1746 #define PMU5_MAINPLL_SI 3 1747 1748 /* 4706 PMU */ 1749 #define PMU4706_MAINPLL_PLL0 0 1750 #define PMU6_4706_PROCPLL_OFF 4 /**< The CPU PLL */ 1751 #define PMU6_4706_PROC_P2DIV_MASK 0x000f0000 1752 #define PMU6_4706_PROC_P2DIV_SHIFT 16 1753 #define PMU6_4706_PROC_P1DIV_MASK 0x0000f000 1754 #define PMU6_4706_PROC_P1DIV_SHIFT 12 1755 #define PMU6_4706_PROC_NDIV_INT_MASK 0x00000ff8 1756 #define PMU6_4706_PROC_NDIV_INT_SHIFT 3 1757 #define PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007 1758 #define PMU6_4706_PROC_NDIV_MODE_SHIFT 0 1759 1760 #define PMU7_PLL_PLLCTL7 7 1761 #define PMU7_PLL_CTL7_M4DIV_MASK 0xff000000 1762 #define PMU7_PLL_CTL7_M4DIV_SHIFT 24 1763 #define PMU7_PLL_CTL7_M4DIV_BY_6 6 1764 #define PMU7_PLL_CTL7_M4DIV_BY_12 0xc 1765 #define PMU7_PLL_CTL7_M4DIV_BY_24 0x18 1766 #define PMU7_PLL_PLLCTL8 8 1767 #define PMU7_PLL_CTL8_M5DIV_MASK 0x000000ff 1768 #define PMU7_PLL_CTL8_M5DIV_SHIFT 0 1769 #define PMU7_PLL_CTL8_M5DIV_BY_8 8 1770 #define PMU7_PLL_CTL8_M5DIV_BY_12 0xc 1771 #define PMU7_PLL_CTL8_M5DIV_BY_24 0x18 1772 #define PMU7_PLL_CTL8_M6DIV_MASK 0x0000ff00 1773 #define PMU7_PLL_CTL8_M6DIV_SHIFT 8 1774 #define PMU7_PLL_CTL8_M6DIV_BY_12 0xc 1775 #define PMU7_PLL_CTL8_M6DIV_BY_24 0x18 1776 #define PMU7_PLL_PLLCTL11 11 1777 #define PMU7_PLL_PLLCTL11_MASK 0xffffff00 1778 #define PMU7_PLL_PLLCTL11_VAL 0x22222200 1779 1780 /* PMU rev 15 */ 1781 #define PMU15_PLL_PLLCTL0 0 1782 #define PMU15_PLL_PC0_CLKSEL_MASK 0x00000003 1783 #define PMU15_PLL_PC0_CLKSEL_SHIFT 0 1784 #define PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC 1785 #define PMU15_PLL_PC0_FREQTGT_SHIFT 2 1786 #define PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000 1787 #define PMU15_PLL_PC0_PRESCALE_SHIFT 22 1788 #define PMU15_PLL_PC0_KPCTRL_MASK 0x07000000 1789 #define PMU15_PLL_PC0_KPCTRL_SHIFT 24 1790 #define PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000 1791 #define PMU15_PLL_PC0_FCNTCTRL_SHIFT 27 1792 #define PMU15_PLL_PC0_FDCMODE_MASK 0x40000000 1793 #define PMU15_PLL_PC0_FDCMODE_SHIFT 30 1794 #define PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000 1795 #define PMU15_PLL_PC0_CTRLBIAS_SHIFT 31 1796 1797 #define PMU15_PLL_PLLCTL1 1 1798 #define PMU15_PLL_PC1_BIAS_CTLM_MASK 0x00000060 1799 #define PMU15_PLL_PC1_BIAS_CTLM_SHIFT 5 1800 #define PMU15_PLL_PC1_BIAS_CTLM_RST_MASK 0x00000040 1801 #define PMU15_PLL_PC1_BIAS_CTLM_RST_SHIFT 6 1802 #define PMU15_PLL_PC1_BIAS_SS_DIVR_MASK 0x0001FF80 1803 #define PMU15_PLL_PC1_BIAS_SS_DIVR_SHIFT 7 1804 #define PMU15_PLL_PC1_BIAS_SS_RSTVAL_MASK 0x03FE0000 1805 #define PMU15_PLL_PC1_BIAS_SS_RSTVAL_SHIFT 17 1806 #define PMU15_PLL_PC1_BIAS_INTG_BW_MASK 0x0C000000 1807 #define PMU15_PLL_PC1_BIAS_INTG_BW_SHIFT 26 1808 #define PMU15_PLL_PC1_BIAS_INTG_BYP_MASK 0x10000000 1809 #define PMU15_PLL_PC1_BIAS_INTG_BYP_SHIFT 28 1810 #define PMU15_PLL_PC1_OPENLP_EN_MASK 0x40000000 1811 #define PMU15_PLL_PC1_OPENLP_EN_SHIFT 30 1812 1813 #define PMU15_PLL_PLLCTL2 2 1814 #define PMU15_PLL_PC2_CTEN_MASK 0x00000001 1815 #define PMU15_PLL_PC2_CTEN_SHIFT 0 1816 1817 #define PMU15_PLL_PLLCTL3 3 1818 #define PMU15_PLL_PC3_DITHER_EN_MASK 0x00000001 1819 #define PMU15_PLL_PC3_DITHER_EN_SHIFT 0 1820 #define PMU15_PLL_PC3_DCOCTLSP_MASK 0xFE000000 1821 #define PMU15_PLL_PC3_DCOCTLSP_SHIFT 25 1822 #define PMU15_PLL_PC3_DCOCTLSP_DIV2EN_MASK 0x01 1823 #define PMU15_PLL_PC3_DCOCTLSP_DIV2EN_SHIFT 0 1824 #define PMU15_PLL_PC3_DCOCTLSP_CH0EN_MASK 0x02 1825 #define PMU15_PLL_PC3_DCOCTLSP_CH0EN_SHIFT 1 1826 #define PMU15_PLL_PC3_DCOCTLSP_CH1EN_MASK 0x04 1827 #define PMU15_PLL_PC3_DCOCTLSP_CH1EN_SHIFT 2 1828 #define PMU15_PLL_PC3_DCOCTLSP_CH0SEL_MASK 0x18 1829 #define PMU15_PLL_PC3_DCOCTLSP_CH0SEL_SHIFT 3 1830 #define PMU15_PLL_PC3_DCOCTLSP_CH1SEL_MASK 0x60 1831 #define PMU15_PLL_PC3_DCOCTLSP_CH1SEL_SHIFT 5 1832 #define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV1 0 1833 #define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV2 1 1834 #define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV3 2 1835 #define PMU15_PLL_PC3_DCOCTLSP_CHSEL_OUTP_DIV5 3 1836 1837 #define PMU15_PLL_PLLCTL4 4 1838 #define PMU15_PLL_PC4_FLLCLK1_DIV_MASK 0x00000007 1839 #define PMU15_PLL_PC4_FLLCLK1_DIV_SHIFT 0 1840 #define PMU15_PLL_PC4_FLLCLK2_DIV_MASK 0x00000038 1841 #define PMU15_PLL_PC4_FLLCLK2_DIV_SHIFT 3 1842 #define PMU15_PLL_PC4_FLLCLK3_DIV_MASK 0x000001C0 1843 #define PMU15_PLL_PC4_FLLCLK3_DIV_SHIFT 6 1844 #define PMU15_PLL_PC4_DBGMODE_MASK 0x00000E00 1845 #define PMU15_PLL_PC4_DBGMODE_SHIFT 9 1846 #define PMU15_PLL_PC4_FLL480_CTLSP_LK_MASK 0x00001000 1847 #define PMU15_PLL_PC4_FLL480_CTLSP_LK_SHIFT 12 1848 #define PMU15_PLL_PC4_FLL480_CTLSP_MASK 0x000FE000 1849 #define PMU15_PLL_PC4_FLL480_CTLSP_SHIFT 13 1850 #define PMU15_PLL_PC4_DINPOL_MASK 0x00100000 1851 #define PMU15_PLL_PC4_DINPOL_SHIFT 20 1852 #define PMU15_PLL_PC4_CLKOUT_PD_MASK 0x00200000 1853 #define PMU15_PLL_PC4_CLKOUT_PD_SHIFT 21 1854 #define PMU15_PLL_PC4_CLKDIV2_PD_MASK 0x00400000 1855 #define PMU15_PLL_PC4_CLKDIV2_PD_SHIFT 22 1856 #define PMU15_PLL_PC4_CLKDIV4_PD_MASK 0x00800000 1857 #define PMU15_PLL_PC4_CLKDIV4_PD_SHIFT 23 1858 #define PMU15_PLL_PC4_CLKDIV8_PD_MASK 0x01000000 1859 #define PMU15_PLL_PC4_CLKDIV8_PD_SHIFT 24 1860 #define PMU15_PLL_PC4_CLKDIV16_PD_MASK 0x02000000 1861 #define PMU15_PLL_PC4_CLKDIV16_PD_SHIFT 25 1862 #define PMU15_PLL_PC4_TEST_EN_MASK 0x04000000 1863 #define PMU15_PLL_PC4_TEST_EN_SHIFT 26 1864 1865 #define PMU15_PLL_PLLCTL5 5 1866 #define PMU15_PLL_PC5_FREQTGT_MASK 0x000FFFFF 1867 #define PMU15_PLL_PC5_FREQTGT_SHIFT 0 1868 #define PMU15_PLL_PC5_DCOCTLSP_MASK 0x07F00000 1869 #define PMU15_PLL_PC5_DCOCTLSP_SHIFT 20 1870 #define PMU15_PLL_PC5_PRESCALE_MASK 0x18000000 1871 #define PMU15_PLL_PC5_PRESCALE_SHIFT 27 1872 1873 #define PMU15_PLL_PLLCTL6 6 1874 #define PMU15_PLL_PC6_FREQTGT_MASK 0x000FFFFF 1875 #define PMU15_PLL_PC6_FREQTGT_SHIFT 0 1876 #define PMU15_PLL_PC6_DCOCTLSP_MASK 0x07F00000 1877 #define PMU15_PLL_PC6_DCOCTLSP_SHIFT 20 1878 #define PMU15_PLL_PC6_PRESCALE_MASK 0x18000000 1879 #define PMU15_PLL_PC6_PRESCALE_SHIFT 27 1880 1881 #define PMU15_FREQTGT_480_DEFAULT 0x19AB1 1882 #define PMU15_FREQTGT_492_DEFAULT 0x1A4F5 1883 #define PMU15_ARM_96MHZ 96000000 /**< 96 Mhz */ 1884 #define PMU15_ARM_98MHZ 98400000 /**< 98.4 Mhz */ 1885 #define PMU15_ARM_97MHZ 97000000 /**< 97 Mhz */ 1886 1887 1888 #define PMU17_PLLCTL2_NDIVTYPE_MASK 0x00000070 1889 #define PMU17_PLLCTL2_NDIVTYPE_SHIFT 4 1890 1891 #define PMU17_PLLCTL2_NDIV_MODE_INT 0 1892 #define PMU17_PLLCTL2_NDIV_MODE_INT1B8 1 1893 #define PMU17_PLLCTL2_NDIV_MODE_MASH111 2 1894 #define PMU17_PLLCTL2_NDIV_MODE_MASH111B8 3 1895 1896 #define PMU17_PLLCTL0_BBPLL_PWRDWN 0 1897 #define PMU17_PLLCTL0_BBPLL_DRST 3 1898 #define PMU17_PLLCTL0_BBPLL_DISBL_CLK 8 1899 1900 /* PLL usage in 4716/47162 */ 1901 #define PMU4716_MAINPLL_PLL0 12 1902 1903 /* PLL usage in 4335 */ 1904 #define PMU4335_PLL0_PC2_P1DIV_MASK 0x000f0000 1905 #define PMU4335_PLL0_PC2_P1DIV_SHIFT 16 1906 #define PMU4335_PLL0_PC2_NDIV_INT_MASK 0xff800000 1907 #define PMU4335_PLL0_PC2_NDIV_INT_SHIFT 23 1908 #define PMU4335_PLL0_PC1_MDIV2_MASK 0x0000ff00 1909 #define PMU4335_PLL0_PC1_MDIV2_SHIFT 8 1910 1911 /* PLL usage in 4347 */ 1912 #define PMU4347_PLL0_PC2_P1DIV_MASK 0x000f0000 1913 #define PMU4347_PLL0_PC2_P1DIV_SHIFT 16 1914 #define PMU4347_PLL0_PC2_NDIV_INT_MASK 0x3ff00000 1915 #define PMU4347_PLL0_PC2_NDIV_INT_SHIFT 20 1916 #define PMU4347_PLL0_PC3_NDIV_FRAC_MASK 0x000fffff 1917 #define PMU4347_PLL0_PC3_NDIV_FRAC_SHIFT 0 1918 #define PMU4347_PLL1_PC5_P1DIV_MASK 0xc0000000 1919 #define PMU4347_PLL1_PC5_P1DIV_SHIFT 30 1920 #define PMU4347_PLL1_PC6_P1DIV_MASK 0x00000003 1921 #define PMU4347_PLL1_PC6_P1DIV_SHIFT 0 1922 #define PMU4347_PLL1_PC6_NDIV_INT_MASK 0x00000ffc 1923 #define PMU4347_PLL1_PC6_NDIV_INT_SHIFT 2 1924 #define PMU4347_PLL1_PC6_NDIV_FRAC_MASK 0xfffff000 1925 #define PMU4347_PLL1_PC6_NDIV_FRAC_SHIFT 12 1926 1927 /* PLL usage in 5356/5357 */ 1928 #define PMU5356_MAINPLL_PLL0 0 1929 #define PMU5357_MAINPLL_PLL0 0 1930 1931 /* 4716/47162 resources */ 1932 #define RES4716_PROC_PLL_ON 0x00000040 1933 #define RES4716_PROC_HT_AVAIL 0x00000080 1934 1935 /* 4716/4717/4718 Chip specific ChipControl register bits */ 1936 #define CCTRL_471X_I2S_PINS_ENABLE 0x0080 /* I2S pins off by default, shared w/ pflash */ 1937 1938 /* 5357 Chip specific ChipControl register bits */ 1939 /* 2nd - 32-bit reg */ 1940 #define CCTRL_5357_I2S_PINS_ENABLE 0x00040000 /* I2S pins enable */ 1941 #define CCTRL_5357_I2CSPI_PINS_ENABLE 0x00080000 /* I2C/SPI pins enable */ 1942 1943 /* 5354 resources */ 1944 #define RES5354_EXT_SWITCHER_PWM 0 /**< 0x00001 */ 1945 #define RES5354_BB_SWITCHER_PWM 1 /**< 0x00002 */ 1946 #define RES5354_BB_SWITCHER_BURST 2 /**< 0x00004 */ 1947 #define RES5354_BB_EXT_SWITCHER_BURST 3 /**< 0x00008 */ 1948 #define RES5354_ILP_REQUEST 4 /**< 0x00010 */ 1949 #define RES5354_RADIO_SWITCHER_PWM 5 /**< 0x00020 */ 1950 #define RES5354_RADIO_SWITCHER_BURST 6 /**< 0x00040 */ 1951 #define RES5354_ROM_SWITCH 7 /**< 0x00080 */ 1952 #define RES5354_PA_REF_LDO 8 /**< 0x00100 */ 1953 #define RES5354_RADIO_LDO 9 /**< 0x00200 */ 1954 #define RES5354_AFE_LDO 10 /**< 0x00400 */ 1955 #define RES5354_PLL_LDO 11 /**< 0x00800 */ 1956 #define RES5354_BG_FILTBYP 12 /**< 0x01000 */ 1957 #define RES5354_TX_FILTBYP 13 /**< 0x02000 */ 1958 #define RES5354_RX_FILTBYP 14 /**< 0x04000 */ 1959 #define RES5354_XTAL_PU 15 /**< 0x08000 */ 1960 #define RES5354_XTAL_EN 16 /**< 0x10000 */ 1961 #define RES5354_BB_PLL_FILTBYP 17 /**< 0x20000 */ 1962 #define RES5354_RF_PLL_FILTBYP 18 /**< 0x40000 */ 1963 #define RES5354_BB_PLL_PU 19 /**< 0x80000 */ 1964 1965 /* 5357 Chip specific ChipControl register bits */ 1966 #define CCTRL5357_EXTPA (1<<14) /* extPA in ChipControl 1, bit 14 */ 1967 #define CCTRL5357_ANT_MUX_2o3 (1<<15) /* 2o3 in ChipControl 1, bit 15 */ 1968 #define CCTRL5357_NFLASH (1<<16) /* Nandflash in ChipControl 1, bit 16 */ 1969 1970 /* 43217 Chip specific ChipControl register bits */ 1971 #define CCTRL43217_EXTPA_C0 (1<<13) /* core0 extPA in ChipControl 1, bit 13 */ 1972 #define CCTRL43217_EXTPA_C1 (1<<8) /* core1 extPA in ChipControl 1, bit 8 */ 1973 1974 /* 43228 Chip specific ChipControl register bits */ 1975 #define CCTRL43228_EXTPA_C0 (1<<14) /* core1 extPA in ChipControl 1, bit 14 */ 1976 #define CCTRL43228_EXTPA_C1 (1<<9) /* core0 extPA in ChipControl 1, bit 1 */ 1977 1978 /* 4328 resources */ 1979 #define RES4328_EXT_SWITCHER_PWM 0 /**< 0x00001 */ 1980 #define RES4328_BB_SWITCHER_PWM 1 /**< 0x00002 */ 1981 #define RES4328_BB_SWITCHER_BURST 2 /**< 0x00004 */ 1982 #define RES4328_BB_EXT_SWITCHER_BURST 3 /**< 0x00008 */ 1983 #define RES4328_ILP_REQUEST 4 /**< 0x00010 */ 1984 #define RES4328_RADIO_SWITCHER_PWM 5 /**< 0x00020 */ 1985 #define RES4328_RADIO_SWITCHER_BURST 6 /**< 0x00040 */ 1986 #define RES4328_ROM_SWITCH 7 /**< 0x00080 */ 1987 #define RES4328_PA_REF_LDO 8 /**< 0x00100 */ 1988 #define RES4328_RADIO_LDO 9 /**< 0x00200 */ 1989 #define RES4328_AFE_LDO 10 /**< 0x00400 */ 1990 #define RES4328_PLL_LDO 11 /**< 0x00800 */ 1991 #define RES4328_BG_FILTBYP 12 /**< 0x01000 */ 1992 #define RES4328_TX_FILTBYP 13 /**< 0x02000 */ 1993 #define RES4328_RX_FILTBYP 14 /**< 0x04000 */ 1994 #define RES4328_XTAL_PU 15 /**< 0x08000 */ 1995 #define RES4328_XTAL_EN 16 /**< 0x10000 */ 1996 #define RES4328_BB_PLL_FILTBYP 17 /**< 0x20000 */ 1997 #define RES4328_RF_PLL_FILTBYP 18 /**< 0x40000 */ 1998 #define RES4328_BB_PLL_PU 19 /**< 0x80000 */ 1999 2000 /* 4325 A0/A1 resources */ 2001 #define RES4325_BUCK_BOOST_BURST 0 /**< 0x00000001 */ 2002 #define RES4325_CBUCK_BURST 1 /**< 0x00000002 */ 2003 #define RES4325_CBUCK_PWM 2 /**< 0x00000004 */ 2004 #define RES4325_CLDO_CBUCK_BURST 3 /**< 0x00000008 */ 2005 #define RES4325_CLDO_CBUCK_PWM 4 /**< 0x00000010 */ 2006 #define RES4325_BUCK_BOOST_PWM 5 /**< 0x00000020 */ 2007 #define RES4325_ILP_REQUEST 6 /**< 0x00000040 */ 2008 #define RES4325_ABUCK_BURST 7 /**< 0x00000080 */ 2009 #define RES4325_ABUCK_PWM 8 /**< 0x00000100 */ 2010 #define RES4325_LNLDO1_PU 9 /**< 0x00000200 */ 2011 #define RES4325_OTP_PU 10 /**< 0x00000400 */ 2012 #define RES4325_LNLDO3_PU 11 /**< 0x00000800 */ 2013 #define RES4325_LNLDO4_PU 12 /**< 0x00001000 */ 2014 #define RES4325_XTAL_PU 13 /**< 0x00002000 */ 2015 #define RES4325_ALP_AVAIL 14 /**< 0x00004000 */ 2016 #define RES4325_RX_PWRSW_PU 15 /**< 0x00008000 */ 2017 #define RES4325_TX_PWRSW_PU 16 /**< 0x00010000 */ 2018 #define RES4325_RFPLL_PWRSW_PU 17 /**< 0x00020000 */ 2019 #define RES4325_LOGEN_PWRSW_PU 18 /**< 0x00040000 */ 2020 #define RES4325_AFE_PWRSW_PU 19 /**< 0x00080000 */ 2021 #define RES4325_BBPLL_PWRSW_PU 20 /**< 0x00100000 */ 2022 #define RES4325_HT_AVAIL 21 /**< 0x00200000 */ 2023 2024 /* 4325 B0/C0 resources */ 2025 #define RES4325B0_CBUCK_LPOM 1 /**< 0x00000002 */ 2026 #define RES4325B0_CBUCK_BURST 2 /**< 0x00000004 */ 2027 #define RES4325B0_CBUCK_PWM 3 /**< 0x00000008 */ 2028 #define RES4325B0_CLDO_PU 4 /**< 0x00000010 */ 2029 2030 /* 4325 C1 resources */ 2031 #define RES4325C1_LNLDO2_PU 12 /**< 0x00001000 */ 2032 2033 /* 4325 chip-specific ChipStatus register bits */ 2034 #define CST4325_SPROM_OTP_SEL_MASK 0x00000003 2035 #define CST4325_DEFCIS_SEL 0 /**< OTP is powered up, use def. CIS, no SPROM */ 2036 #define CST4325_SPROM_SEL 1 /**< OTP is powered up, SPROM is present */ 2037 #define CST4325_OTP_SEL 2 /**< OTP is powered up, no SPROM */ 2038 #define CST4325_OTP_PWRDN 3 /**< OTP is powered down, SPROM is present */ 2039 #define CST4325_SDIO_USB_MODE_MASK 0x00000004 2040 #define CST4325_SDIO_USB_MODE_SHIFT 2 2041 #define CST4325_RCAL_VALID_MASK 0x00000008 2042 #define CST4325_RCAL_VALID_SHIFT 3 2043 #define CST4325_RCAL_VALUE_MASK 0x000001f0 2044 #define CST4325_RCAL_VALUE_SHIFT 4 2045 #define CST4325_PMUTOP_2B_MASK 0x00000200 /**< 1 for 2b, 0 for to 2a */ 2046 #define CST4325_PMUTOP_2B_SHIFT 9 2047 2048 #define RES4329_RESERVED0 0 /**< 0x00000001 */ 2049 #define RES4329_CBUCK_LPOM 1 /**< 0x00000002 */ 2050 #define RES4329_CBUCK_BURST 2 /**< 0x00000004 */ 2051 #define RES4329_CBUCK_PWM 3 /**< 0x00000008 */ 2052 #define RES4329_CLDO_PU 4 /**< 0x00000010 */ 2053 #define RES4329_PALDO_PU 5 /**< 0x00000020 */ 2054 #define RES4329_ILP_REQUEST 6 /**< 0x00000040 */ 2055 #define RES4329_RESERVED7 7 /**< 0x00000080 */ 2056 #define RES4329_RESERVED8 8 /**< 0x00000100 */ 2057 #define RES4329_LNLDO1_PU 9 /**< 0x00000200 */ 2058 #define RES4329_OTP_PU 10 /**< 0x00000400 */ 2059 #define RES4329_RESERVED11 11 /**< 0x00000800 */ 2060 #define RES4329_LNLDO2_PU 12 /**< 0x00001000 */ 2061 #define RES4329_XTAL_PU 13 /**< 0x00002000 */ 2062 #define RES4329_ALP_AVAIL 14 /**< 0x00004000 */ 2063 #define RES4329_RX_PWRSW_PU 15 /**< 0x00008000 */ 2064 #define RES4329_TX_PWRSW_PU 16 /**< 0x00010000 */ 2065 #define RES4329_RFPLL_PWRSW_PU 17 /**< 0x00020000 */ 2066 #define RES4329_LOGEN_PWRSW_PU 18 /**< 0x00040000 */ 2067 #define RES4329_AFE_PWRSW_PU 19 /**< 0x00080000 */ 2068 #define RES4329_BBPLL_PWRSW_PU 20 /**< 0x00100000 */ 2069 #define RES4329_HT_AVAIL 21 /**< 0x00200000 */ 2070 2071 #define CST4329_SPROM_OTP_SEL_MASK 0x00000003 2072 #define CST4329_DEFCIS_SEL 0 /**< OTP is powered up, use def. CIS, no SPROM */ 2073 #define CST4329_SPROM_SEL 1 /**< OTP is powered up, SPROM is present */ 2074 #define CST4329_OTP_SEL 2 /**< OTP is powered up, no SPROM */ 2075 #define CST4329_OTP_PWRDN 3 /**< OTP is powered down, SPROM is present */ 2076 #define CST4329_SPI_SDIO_MODE_MASK 0x00000004 2077 #define CST4329_SPI_SDIO_MODE_SHIFT 2 2078 2079 /* 4312 chip-specific ChipStatus register bits */ 2080 #define CST4312_SPROM_OTP_SEL_MASK 0x00000003 2081 #define CST4312_DEFCIS_SEL 0 /**< OTP is powered up, use def. CIS, no SPROM */ 2082 #define CST4312_SPROM_SEL 1 /**< OTP is powered up, SPROM is present */ 2083 #define CST4312_OTP_SEL 2 /**< OTP is powered up, no SPROM */ 2084 #define CST4312_OTP_BAD 3 /**< OTP is broken, SPROM is present */ 2085 2086 /* 4312 resources (all PMU chips with little memory constraint) */ 2087 #define RES4312_SWITCHER_BURST 0 /**< 0x00000001 */ 2088 #define RES4312_SWITCHER_PWM 1 /**< 0x00000002 */ 2089 #define RES4312_PA_REF_LDO 2 /**< 0x00000004 */ 2090 #define RES4312_CORE_LDO_BURST 3 /**< 0x00000008 */ 2091 #define RES4312_CORE_LDO_PWM 4 /**< 0x00000010 */ 2092 #define RES4312_RADIO_LDO 5 /**< 0x00000020 */ 2093 #define RES4312_ILP_REQUEST 6 /**< 0x00000040 */ 2094 #define RES4312_BG_FILTBYP 7 /**< 0x00000080 */ 2095 #define RES4312_TX_FILTBYP 8 /**< 0x00000100 */ 2096 #define RES4312_RX_FILTBYP 9 /**< 0x00000200 */ 2097 #define RES4312_XTAL_PU 10 /**< 0x00000400 */ 2098 #define RES4312_ALP_AVAIL 11 /**< 0x00000800 */ 2099 #define RES4312_BB_PLL_FILTBYP 12 /**< 0x00001000 */ 2100 #define RES4312_RF_PLL_FILTBYP 13 /**< 0x00002000 */ 2101 #define RES4312_HT_AVAIL 14 /**< 0x00004000 */ 2102 2103 /* 4322 resources */ 2104 #define RES4322_RF_LDO 0 2105 #define RES4322_ILP_REQUEST 1 2106 #define RES4322_XTAL_PU 2 2107 #define RES4322_ALP_AVAIL 3 2108 #define RES4322_SI_PLL_ON 4 2109 #define RES4322_HT_SI_AVAIL 5 2110 #define RES4322_PHY_PLL_ON 6 2111 #define RES4322_HT_PHY_AVAIL 7 2112 #define RES4322_OTP_PU 8 2113 2114 /* 4322 chip-specific ChipStatus register bits */ 2115 #define CST4322_XTAL_FREQ_20_40MHZ 0x00000020 2116 #define CST4322_SPROM_OTP_SEL_MASK 0x000000c0 2117 #define CST4322_SPROM_OTP_SEL_SHIFT 6 2118 #define CST4322_NO_SPROM_OTP 0 /**< no OTP, no SPROM */ 2119 #define CST4322_SPROM_PRESENT 1 /**< SPROM is present */ 2120 #define CST4322_OTP_PRESENT 2 /**< OTP is present */ 2121 #define CST4322_PCI_OR_USB 0x00000100 2122 #define CST4322_BOOT_MASK 0x00000600 2123 #define CST4322_BOOT_SHIFT 9 2124 #define CST4322_BOOT_FROM_SRAM 0 /**< boot from SRAM, ARM in reset */ 2125 #define CST4322_BOOT_FROM_ROM 1 /**< boot from ROM */ 2126 #define CST4322_BOOT_FROM_FLASH 2 /**< boot from FLASH */ 2127 #define CST4322_BOOT_FROM_INVALID 3 2128 #define CST4322_ILP_DIV_EN 0x00000800 2129 #define CST4322_FLASH_TYPE_MASK 0x00001000 2130 #define CST4322_FLASH_TYPE_SHIFT 12 2131 #define CST4322_FLASH_TYPE_SHIFT_ST 0 /**< ST serial FLASH */ 2132 #define CST4322_FLASH_TYPE_SHIFT_ATMEL 1 /**< ATMEL flash */ 2133 #define CST4322_ARM_TAP_SEL 0x00002000 2134 #define CST4322_RES_INIT_MODE_MASK 0x0000c000 2135 #define CST4322_RES_INIT_MODE_SHIFT 14 2136 #define CST4322_RES_INIT_MODE_ILPAVAIL 0 /**< resinitmode: ILP available */ 2137 #define CST4322_RES_INIT_MODE_ILPREQ 1 /**< resinitmode: ILP request */ 2138 #define CST4322_RES_INIT_MODE_ALPAVAIL 2 /**< resinitmode: ALP available */ 2139 #define CST4322_RES_INIT_MODE_HTAVAIL 3 /**< resinitmode: HT available */ 2140 #define CST4322_PCIPLLCLK_GATING 0x00010000 2141 #define CST4322_CLK_SWITCH_PCI_TO_ALP 0x00020000 2142 #define CST4322_PCI_CARDBUS_MODE 0x00040000 2143 2144 /* 43224 chip-specific ChipControl register bits */ 2145 #define CCTRL43224_GPIO_TOGGLE 0x8000 /* gpio[3:0] pins as btcoex or s/w gpio */ 2146 #define CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */ 2147 #define CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */ 2148 2149 /* 43236 resources */ 2150 #define RES43236_REGULATOR 0 2151 #define RES43236_ILP_REQUEST 1 2152 #define RES43236_XTAL_PU 2 2153 #define RES43236_ALP_AVAIL 3 2154 #define RES43236_SI_PLL_ON 4 2155 #define RES43236_HT_SI_AVAIL 5 2156 2157 /* 43236 chip-specific ChipControl register bits */ 2158 #define CCTRL43236_BT_COEXIST (1<<0) /**< 0 disable */ 2159 #define CCTRL43236_SECI (1<<1) /**< 0 SECI is disabled (JATG functional) */ 2160 #define CCTRL43236_EXT_LNA (1<<2) /**< 0 disable */ 2161 #define CCTRL43236_ANT_MUX_2o3 (1<<3) /**< 2o3 mux, chipcontrol bit 3 */ 2162 #define CCTRL43236_GSIO (1<<4) /**< 0 disable */ 2163 2164 /* 43236 Chip specific ChipStatus register bits */ 2165 #define CST43236_SFLASH_MASK 0x00000040 2166 #define CST43236_OTP_SEL_MASK 0x00000080 2167 #define CST43236_OTP_SEL_SHIFT 7 2168 #define CST43236_HSIC_MASK 0x00000100 /**< USB/HSIC */ 2169 #define CST43236_BP_CLK 0x00000200 /**< 120/96Mbps */ 2170 #define CST43236_BOOT_MASK 0x00001800 2171 #define CST43236_BOOT_SHIFT 11 2172 #define CST43236_BOOT_FROM_SRAM 0 /**< boot from SRAM, ARM in reset */ 2173 #define CST43236_BOOT_FROM_ROM 1 /**< boot from ROM */ 2174 #define CST43236_BOOT_FROM_FLASH 2 /**< boot from FLASH */ 2175 #define CST43236_BOOT_FROM_INVALID 3 2176 2177 /* 43237 resources */ 2178 #define RES43237_REGULATOR 0 2179 #define RES43237_ILP_REQUEST 1 2180 #define RES43237_XTAL_PU 2 2181 #define RES43237_ALP_AVAIL 3 2182 #define RES43237_SI_PLL_ON 4 2183 #define RES43237_HT_SI_AVAIL 5 2184 2185 /* 43237 chip-specific ChipControl register bits */ 2186 #define CCTRL43237_BT_COEXIST (1<<0) /**< 0 disable */ 2187 #define CCTRL43237_SECI (1<<1) /**< 0 SECI is disabled (JATG functional) */ 2188 #define CCTRL43237_EXT_LNA (1<<2) /**< 0 disable */ 2189 #define CCTRL43237_ANT_MUX_2o3 (1<<3) /**< 2o3 mux, chipcontrol bit 3 */ 2190 #define CCTRL43237_GSIO (1<<4) /**< 0 disable */ 2191 2192 /* 43237 Chip specific ChipStatus register bits */ 2193 #define CST43237_SFLASH_MASK 0x00000040 2194 #define CST43237_OTP_SEL_MASK 0x00000080 2195 #define CST43237_OTP_SEL_SHIFT 7 2196 #define CST43237_HSIC_MASK 0x00000100 /**< USB/HSIC */ 2197 #define CST43237_BP_CLK 0x00000200 /**< 120/96Mbps */ 2198 #define CST43237_BOOT_MASK 0x00001800 2199 #define CST43237_BOOT_SHIFT 11 2200 #define CST43237_BOOT_FROM_SRAM 0 /**< boot from SRAM, ARM in reset */ 2201 #define CST43237_BOOT_FROM_ROM 1 /**< boot from ROM */ 2202 #define CST43237_BOOT_FROM_FLASH 2 /**< boot from FLASH */ 2203 #define CST43237_BOOT_FROM_INVALID 3 2204 2205 /* 43239 resources */ 2206 #define RES43239_OTP_PU 9 2207 #define RES43239_MACPHY_CLKAVAIL 23 2208 #define RES43239_HT_AVAIL 24 2209 2210 /* 43239 Chip specific ChipStatus register bits */ 2211 #define CST43239_SPROM_MASK 0x00000002 2212 #define CST43239_SFLASH_MASK 0x00000004 2213 #define CST43239_RES_INIT_MODE_SHIFT 7 2214 #define CST43239_RES_INIT_MODE_MASK 0x000001f0 2215 #define CST43239_CHIPMODE_SDIOD(cs) ((cs) & (1 << 15)) /**< SDIO || gSPI */ 2216 #define CST43239_CHIPMODE_USB20D(cs) (~(cs) & (1 << 15)) /**< USB || USBDA */ 2217 #define CST43239_CHIPMODE_SDIO(cs) (((cs) & (1 << 0)) == 0) /**< SDIO */ 2218 #define CST43239_CHIPMODE_GSPI(cs) (((cs) & (1 << 0)) == (1 << 0)) /**< gSPI */ 2219 2220 /* 4324 resources */ 2221 /* 43242 use same PMU as 4324 */ 2222 #define RES4324_LPLDO_PU 0 2223 #define RES4324_RESET_PULLDN_DIS 1 2224 #define RES4324_PMU_BG_PU 2 2225 #define RES4324_HSIC_LDO_PU 3 2226 #define RES4324_CBUCK_LPOM_PU 4 2227 #define RES4324_CBUCK_PFM_PU 5 2228 #define RES4324_CLDO_PU 6 2229 #define RES4324_LPLDO2_LVM 7 2230 #define RES4324_LNLDO1_PU 8 2231 #define RES4324_LNLDO2_PU 9 2232 #define RES4324_LDO3P3_PU 10 2233 #define RES4324_OTP_PU 11 2234 #define RES4324_XTAL_PU 12 2235 #define RES4324_BBPLL_PU 13 2236 #define RES4324_LQ_AVAIL 14 2237 #define RES4324_WL_CORE_READY 17 2238 #define RES4324_ILP_REQ 18 2239 #define RES4324_ALP_AVAIL 19 2240 #define RES4324_PALDO_PU 20 2241 #define RES4324_RADIO_PU 21 2242 #define RES4324_SR_CLK_STABLE 22 2243 #define RES4324_SR_SAVE_RESTORE 23 2244 #define RES4324_SR_PHY_PWRSW 24 2245 #define RES4324_SR_PHY_PIC 25 2246 #define RES4324_SR_SUBCORE_PWRSW 26 2247 #define RES4324_SR_SUBCORE_PIC 27 2248 #define RES4324_SR_MEM_PM0 28 2249 #define RES4324_HT_AVAIL 29 2250 #define RES4324_MACPHY_CLKAVAIL 30 2251 2252 /* 4324 Chip specific ChipStatus register bits */ 2253 #define CST4324_SPROM_MASK 0x00000080 2254 #define CST4324_SFLASH_MASK 0x00400000 2255 #define CST4324_RES_INIT_MODE_SHIFT 10 2256 #define CST4324_RES_INIT_MODE_MASK 0x00000c00 2257 #define CST4324_CHIPMODE_MASK 0x7 2258 #define CST4324_CHIPMODE_SDIOD(cs) ((~(cs)) & (1 << 2)) /**< SDIO || gSPI */ 2259 #define CST4324_CHIPMODE_USB20D(cs) (((cs) & CST4324_CHIPMODE_MASK) == 0x6) /**< USB || USBDA */ 2260 2261 /* 43242 Chip specific ChipStatus register bits */ 2262 #define CST43242_SFLASH_MASK 0x00000008 2263 #define CST43242_SR_HALT (1<<25) 2264 #define CST43242_SR_CHIP_STATUS_2 27 /* bit 27 */ 2265 2266 /* 4331 resources */ 2267 #define RES4331_REGULATOR 0 2268 #define RES4331_ILP_REQUEST 1 2269 #define RES4331_XTAL_PU 2 2270 #define RES4331_ALP_AVAIL 3 2271 #define RES4331_SI_PLL_ON 4 2272 #define RES4331_HT_SI_AVAIL 5 2273 2274 /* 4331 chip-specific ChipControl register bits */ 2275 #define CCTRL4331_BT_COEXIST (1<<0) /**< 0 disable */ 2276 #define CCTRL4331_SECI (1<<1) /**< 0 SECI is disabled (JATG functional) */ 2277 #define CCTRL4331_EXT_LNA_G (1<<2) /**< 0 disable */ 2278 #define CCTRL4331_SPROM_GPIO13_15 (1<<3) /**< sprom/gpio13-15 mux */ 2279 #define CCTRL4331_EXTPA_EN (1<<4) /**< 0 ext pa disable, 1 ext pa enabled */ 2280 #define CCTRL4331_GPIOCLK_ON_SPROMCS (1<<5) /**< set drive out GPIO_CLK on sprom_cs pin */ 2281 #define CCTRL4331_PCIE_MDIO_ON_SPROMCS (1<<6) /**< use sprom_cs pin as PCIE mdio interface */ 2282 #define CCTRL4331_EXTPA_ON_GPIO2_5 (1<<7) /* aband extpa will be at gpio2/5 and sprom_dout */ 2283 #define CCTRL4331_OVR_PIPEAUXCLKEN (1<<8) /**< override core control on pipe_AuxClkEnable */ 2284 #define CCTRL4331_OVR_PIPEAUXPWRDOWN (1<<9) /**< override core control on pipe_AuxPowerDown */ 2285 #define CCTRL4331_PCIE_AUXCLKEN (1<<10) /**< pcie_auxclkenable */ 2286 #define CCTRL4331_PCIE_PIPE_PLLDOWN (1<<11) /**< pcie_pipe_pllpowerdown */ 2287 #define CCTRL4331_EXTPA_EN2 (1<<12) /**< 0 ext pa disable, 1 ext pa enabled */ 2288 #define CCTRL4331_EXT_LNA_A (1<<13) /**< 0 disable */ 2289 #define CCTRL4331_BT_SHD0_ON_GPIO4 (1<<16) /**< enable bt_shd0 at gpio4 */ 2290 #define CCTRL4331_BT_SHD1_ON_GPIO5 (1<<17) /**< enable bt_shd1 at gpio5 */ 2291 #define CCTRL4331_EXTPA_ANA_EN (1<<24) /**< 0 ext pa disable, 1 ext pa enabled */ 2292 2293 /* 4331 Chip specific ChipStatus register bits */ 2294 #define CST4331_XTAL_FREQ 0x00000001 /**< crystal frequency 20/40Mhz */ 2295 #define CST4331_SPROM_OTP_SEL_MASK 0x00000006 2296 #define CST4331_SPROM_OTP_SEL_SHIFT 1 2297 #define CST4331_SPROM_PRESENT 0x00000002 2298 #define CST4331_OTP_PRESENT 0x00000004 2299 #define CST4331_LDO_RF 0x00000008 2300 #define CST4331_LDO_PAR 0x00000010 2301 2302 /* 4315 resource */ 2303 #define RES4315_CBUCK_LPOM 1 /**< 0x00000002 */ 2304 #define RES4315_CBUCK_BURST 2 /**< 0x00000004 */ 2305 #define RES4315_CBUCK_PWM 3 /**< 0x00000008 */ 2306 #define RES4315_CLDO_PU 4 /**< 0x00000010 */ 2307 #define RES4315_PALDO_PU 5 /**< 0x00000020 */ 2308 #define RES4315_ILP_REQUEST 6 /**< 0x00000040 */ 2309 #define RES4315_LNLDO1_PU 9 /**< 0x00000200 */ 2310 #define RES4315_OTP_PU 10 /**< 0x00000400 */ 2311 #define RES4315_LNLDO2_PU 12 /**< 0x00001000 */ 2312 #define RES4315_XTAL_PU 13 /**< 0x00002000 */ 2313 #define RES4315_ALP_AVAIL 14 /**< 0x00004000 */ 2314 #define RES4315_RX_PWRSW_PU 15 /**< 0x00008000 */ 2315 #define RES4315_TX_PWRSW_PU 16 /**< 0x00010000 */ 2316 #define RES4315_RFPLL_PWRSW_PU 17 /**< 0x00020000 */ 2317 #define RES4315_LOGEN_PWRSW_PU 18 /**< 0x00040000 */ 2318 #define RES4315_AFE_PWRSW_PU 19 /**< 0x00080000 */ 2319 #define RES4315_BBPLL_PWRSW_PU 20 /**< 0x00100000 */ 2320 #define RES4315_HT_AVAIL 21 /**< 0x00200000 */ 2321 2322 /* 4315 chip-specific ChipStatus register bits */ 2323 #define CST4315_SPROM_OTP_SEL_MASK 0x00000003 /**< gpio [7:6], SDIO CIS selection */ 2324 #define CST4315_DEFCIS_SEL 0x00000000 /**< use default CIS, OTP is powered up */ 2325 #define CST4315_SPROM_SEL 0x00000001 /**< use SPROM, OTP is powered up */ 2326 #define CST4315_OTP_SEL 0x00000002 /**< use OTP, OTP is powered up */ 2327 #define CST4315_OTP_PWRDN 0x00000003 /**< use SPROM, OTP is powered down */ 2328 #define CST4315_SDIO_MODE 0x00000004 /**< gpio [8], sdio/usb mode */ 2329 #define CST4315_RCAL_VALID 0x00000008 2330 #define CST4315_RCAL_VALUE_MASK 0x000001f0 2331 #define CST4315_RCAL_VALUE_SHIFT 4 2332 #define CST4315_PALDO_EXTPNP 0x00000200 /**< PALDO is configured with external PNP */ 2333 #define CST4315_CBUCK_MODE_MASK 0x00000c00 2334 #define CST4315_CBUCK_MODE_BURST 0x00000400 2335 #define CST4315_CBUCK_MODE_LPBURST 0x00000c00 2336 2337 /* 4319 resources */ 2338 #define RES4319_CBUCK_LPOM 1 /**< 0x00000002 */ 2339 #define RES4319_CBUCK_BURST 2 /**< 0x00000004 */ 2340 #define RES4319_CBUCK_PWM 3 /**< 0x00000008 */ 2341 #define RES4319_CLDO_PU 4 /**< 0x00000010 */ 2342 #define RES4319_PALDO_PU 5 /**< 0x00000020 */ 2343 #define RES4319_ILP_REQUEST 6 /**< 0x00000040 */ 2344 #define RES4319_LNLDO1_PU 9 /**< 0x00000200 */ 2345 #define RES4319_OTP_PU 10 /**< 0x00000400 */ 2346 #define RES4319_LNLDO2_PU 12 /**< 0x00001000 */ 2347 #define RES4319_XTAL_PU 13 /**< 0x00002000 */ 2348 #define RES4319_ALP_AVAIL 14 /**< 0x00004000 */ 2349 #define RES4319_RX_PWRSW_PU 15 /**< 0x00008000 */ 2350 #define RES4319_TX_PWRSW_PU 16 /**< 0x00010000 */ 2351 #define RES4319_RFPLL_PWRSW_PU 17 /**< 0x00020000 */ 2352 #define RES4319_LOGEN_PWRSW_PU 18 /**< 0x00040000 */ 2353 #define RES4319_AFE_PWRSW_PU 19 /**< 0x00080000 */ 2354 #define RES4319_BBPLL_PWRSW_PU 20 /**< 0x00100000 */ 2355 #define RES4319_HT_AVAIL 21 /**< 0x00200000 */ 2356 2357 /* 4319 chip-specific ChipStatus register bits */ 2358 #define CST4319_SPI_CPULESSUSB 0x00000001 2359 #define CST4319_SPI_CLK_POL 0x00000002 2360 #define CST4319_SPI_CLK_PH 0x00000008 2361 #define CST4319_SPROM_OTP_SEL_MASK 0x000000c0 /**< gpio [7:6], SDIO CIS selection */ 2362 #define CST4319_SPROM_OTP_SEL_SHIFT 6 2363 #define CST4319_DEFCIS_SEL 0x00000000 /**< use default CIS, OTP is powered up */ 2364 #define CST4319_SPROM_SEL 0x00000040 /**< use SPROM, OTP is powered up */ 2365 #define CST4319_OTP_SEL 0x00000080 /* use OTP, OTP is powered up */ 2366 #define CST4319_OTP_PWRDN 0x000000c0 /* use SPROM, OTP is powered down */ 2367 #define CST4319_SDIO_USB_MODE 0x00000100 /**< gpio [8], sdio/usb mode */ 2368 #define CST4319_REMAP_SEL_MASK 0x00000600 2369 #define CST4319_ILPDIV_EN 0x00000800 2370 #define CST4319_XTAL_PD_POL 0x00001000 2371 #define CST4319_LPO_SEL 0x00002000 2372 #define CST4319_RES_INIT_MODE 0x0000c000 2373 #define CST4319_PALDO_EXTPNP 0x00010000 /**< PALDO is configured with external PNP */ 2374 #define CST4319_CBUCK_MODE_MASK 0x00060000 2375 #define CST4319_CBUCK_MODE_BURST 0x00020000 2376 #define CST4319_CBUCK_MODE_LPBURST 0x00060000 2377 #define CST4319_RCAL_VALID 0x01000000 2378 #define CST4319_RCAL_VALUE_MASK 0x3e000000 2379 #define CST4319_RCAL_VALUE_SHIFT 25 2380 2381 #define PMU1_PLL0_CHIPCTL0 0 2382 #define PMU1_PLL0_CHIPCTL1 1 2383 #define PMU1_PLL0_CHIPCTL2 2 2384 #define CCTL_4319USB_XTAL_SEL_MASK 0x00180000 2385 #define CCTL_4319USB_XTAL_SEL_SHIFT 19 2386 #define CCTL_4319USB_48MHZ_PLL_SEL 1 2387 #define CCTL_4319USB_24MHZ_PLL_SEL 2 2388 2389 /* PMU resources for 4336 */ 2390 #define RES4336_CBUCK_LPOM 0 2391 #define RES4336_CBUCK_BURST 1 2392 #define RES4336_CBUCK_LP_PWM 2 2393 #define RES4336_CBUCK_PWM 3 2394 #define RES4336_CLDO_PU 4 2395 #define RES4336_DIS_INT_RESET_PD 5 2396 #define RES4336_ILP_REQUEST 6 2397 #define RES4336_LNLDO_PU 7 2398 #define RES4336_LDO3P3_PU 8 2399 #define RES4336_OTP_PU 9 2400 #define RES4336_XTAL_PU 10 2401 #define RES4336_ALP_AVAIL 11 2402 #define RES4336_RADIO_PU 12 2403 #define RES4336_BG_PU 13 2404 #define RES4336_VREG1p4_PU_PU 14 2405 #define RES4336_AFE_PWRSW_PU 15 2406 #define RES4336_RX_PWRSW_PU 16 2407 #define RES4336_TX_PWRSW_PU 17 2408 #define RES4336_BB_PWRSW_PU 18 2409 #define RES4336_SYNTH_PWRSW_PU 19 2410 #define RES4336_MISC_PWRSW_PU 20 2411 #define RES4336_LOGEN_PWRSW_PU 21 2412 #define RES4336_BBPLL_PWRSW_PU 22 2413 #define RES4336_MACPHY_CLKAVAIL 23 2414 #define RES4336_HT_AVAIL 24 2415 #define RES4336_RSVD 25 2416 2417 /* 4336 chip-specific ChipStatus register bits */ 2418 #define CST4336_SPI_MODE_MASK 0x00000001 2419 #define CST4336_SPROM_PRESENT 0x00000002 2420 #define CST4336_OTP_PRESENT 0x00000004 2421 #define CST4336_ARMREMAP_0 0x00000008 2422 #define CST4336_ILPDIV_EN_MASK 0x00000010 2423 #define CST4336_ILPDIV_EN_SHIFT 4 2424 #define CST4336_XTAL_PD_POL_MASK 0x00000020 2425 #define CST4336_XTAL_PD_POL_SHIFT 5 2426 #define CST4336_LPO_SEL_MASK 0x00000040 2427 #define CST4336_LPO_SEL_SHIFT 6 2428 #define CST4336_RES_INIT_MODE_MASK 0x00000180 2429 #define CST4336_RES_INIT_MODE_SHIFT 7 2430 #define CST4336_CBUCK_MODE_MASK 0x00000600 2431 #define CST4336_CBUCK_MODE_SHIFT 9 2432 2433 /* 4336 Chip specific PMU ChipControl register bits */ 2434 #define PCTL_4336_SERIAL_ENAB (1 << 24) 2435 2436 /* 4330 resources */ 2437 #define RES4330_CBUCK_LPOM 0 2438 #define RES4330_CBUCK_BURST 1 2439 #define RES4330_CBUCK_LP_PWM 2 2440 #define RES4330_CBUCK_PWM 3 2441 #define RES4330_CLDO_PU 4 2442 #define RES4330_DIS_INT_RESET_PD 5 2443 #define RES4330_ILP_REQUEST 6 2444 #define RES4330_LNLDO_PU 7 2445 #define RES4330_LDO3P3_PU 8 2446 #define RES4330_OTP_PU 9 2447 #define RES4330_XTAL_PU 10 2448 #define RES4330_ALP_AVAIL 11 2449 #define RES4330_RADIO_PU 12 2450 #define RES4330_BG_PU 13 2451 #define RES4330_VREG1p4_PU_PU 14 2452 #define RES4330_AFE_PWRSW_PU 15 2453 #define RES4330_RX_PWRSW_PU 16 2454 #define RES4330_TX_PWRSW_PU 17 2455 #define RES4330_BB_PWRSW_PU 18 2456 #define RES4330_SYNTH_PWRSW_PU 19 2457 #define RES4330_MISC_PWRSW_PU 20 2458 #define RES4330_LOGEN_PWRSW_PU 21 2459 #define RES4330_BBPLL_PWRSW_PU 22 2460 #define RES4330_MACPHY_CLKAVAIL 23 2461 #define RES4330_HT_AVAIL 24 2462 #define RES4330_5gRX_PWRSW_PU 25 2463 #define RES4330_5gTX_PWRSW_PU 26 2464 #define RES4330_5g_LOGEN_PWRSW_PU 27 2465 2466 /* 4330 chip-specific ChipStatus register bits */ 2467 #define CST4330_CHIPMODE_SDIOD(cs) (((cs) & 0x7) < 6) /**< SDIO || gSPI */ 2468 #define CST4330_CHIPMODE_USB20D(cs) (((cs) & 0x7) >= 6) /**< USB || USBDA */ 2469 #define CST4330_CHIPMODE_SDIO(cs) (((cs) & 0x4) == 0) /**< SDIO */ 2470 #define CST4330_CHIPMODE_GSPI(cs) (((cs) & 0x6) == 4) /**< gSPI */ 2471 #define CST4330_CHIPMODE_USB(cs) (((cs) & 0x7) == 6) /**< USB packet-oriented */ 2472 #define CST4330_CHIPMODE_USBDA(cs) (((cs) & 0x7) == 7) /**< USB Direct Access */ 2473 #define CST4330_OTP_PRESENT 0x00000010 2474 #define CST4330_LPO_AUTODET_EN 0x00000020 2475 #define CST4330_ARMREMAP_0 0x00000040 2476 #define CST4330_SPROM_PRESENT 0x00000080 /**< takes priority over OTP if both set */ 2477 #define CST4330_ILPDIV_EN 0x00000100 2478 #define CST4330_LPO_SEL 0x00000200 2479 #define CST4330_RES_INIT_MODE_SHIFT 10 2480 #define CST4330_RES_INIT_MODE_MASK 0x00000c00 2481 #define CST4330_CBUCK_MODE_SHIFT 12 2482 #define CST4330_CBUCK_MODE_MASK 0x00003000 2483 #define CST4330_CBUCK_POWER_OK 0x00004000 2484 #define CST4330_BB_PLL_LOCKED 0x00008000 2485 #define SOCDEVRAM_BP_ADDR 0x1E000000 2486 #define SOCDEVRAM_ARM_ADDR 0x00800000 2487 2488 /* 4330 Chip specific PMU ChipControl register bits */ 2489 #define PCTL_4330_SERIAL_ENAB (1 << 24) 2490 2491 /* 4330 Chip specific ChipControl register bits */ 2492 #define CCTRL_4330_GPIO_SEL 0x00000001 /* 1=select GPIOs to be muxed out */ 2493 #define CCTRL_4330_ERCX_SEL 0x00000002 /* 1=select ERCX BT coex to be muxed out */ 2494 #define CCTRL_4330_SDIO_HOST_WAKE 0x00000004 /* SDIO: 1=configure GPIO0 for host wake */ 2495 #define CCTRL_4330_JTAG_DISABLE 0x00000008 /* 1=disable JTAG interface on mux'd pins */ 2496 2497 #define PMU_VREG0_ADDR 0 2498 #define PMU_VREG0_I_SR_CNTL_EN_SHIFT 0 2499 #define PMU_VREG0_DISABLE_PULLD_BT_SHIFT 2 2500 #define PMU_VREG0_DISABLE_PULLD_WL_SHIFT 3 2501 #define PMU_VREG0_CBUCKFSW_ADJ_SHIFT 7 2502 #define PMU_VREG0_CBUCKFSW_ADJ_MASK 0x1F 2503 #define PMU_VREG0_RAMP_SEL_SHIFT 13 2504 #define PMU_VREG0_RAMP_SEL_MASK 0x7 2505 #define PMU_VREG0_VFB_RSEL_SHIFT 17 2506 #define PMU_VREG0_VFB_RSEL_MASK 3 2507 2508 #define PMU_VREG4_ADDR 4 2509 2510 #define PMU_VREG4_CLDO_PWM_SHIFT 4 2511 #define PMU_VREG4_CLDO_PWM_MASK 0x7 2512 2513 #define PMU_VREG4_LPLDO1_SHIFT 15 2514 #define PMU_VREG4_LPLDO1_MASK 0x7 2515 #define PMU_VREG4_LPLDO1_1p20V 0 2516 #define PMU_VREG4_LPLDO1_1p15V 1 2517 #define PMU_VREG4_LPLDO1_1p10V 2 2518 #define PMU_VREG4_LPLDO1_1p25V 3 2519 #define PMU_VREG4_LPLDO1_1p05V 4 2520 #define PMU_VREG4_LPLDO1_1p00V 5 2521 #define PMU_VREG4_LPLDO1_0p95V 6 2522 #define PMU_VREG4_LPLDO1_0p90V 7 2523 2524 /* 4350/4345 VREG4 settings */ 2525 #define PMU4350_VREG4_LPLDO1_1p10V 0 2526 #define PMU4350_VREG4_LPLDO1_1p15V 1 2527 #define PMU4350_VREG4_LPLDO1_1p21V 2 2528 #define PMU4350_VREG4_LPLDO1_1p24V 3 2529 #define PMU4350_VREG4_LPLDO1_0p90V 4 2530 #define PMU4350_VREG4_LPLDO1_0p96V 5 2531 #define PMU4350_VREG4_LPLDO1_1p01V 6 2532 #define PMU4350_VREG4_LPLDO1_1p04V 7 2533 2534 #define PMU_VREG4_LPLDO2_LVM_SHIFT 18 2535 #define PMU_VREG4_LPLDO2_LVM_MASK 0x7 2536 #define PMU_VREG4_LPLDO2_HVM_SHIFT 21 2537 #define PMU_VREG4_LPLDO2_HVM_MASK 0x7 2538 #define PMU_VREG4_LPLDO2_LVM_HVM_MASK 0x3f 2539 #define PMU_VREG4_LPLDO2_1p00V 0 2540 #define PMU_VREG4_LPLDO2_1p15V 1 2541 #define PMU_VREG4_LPLDO2_1p20V 2 2542 #define PMU_VREG4_LPLDO2_1p10V 3 2543 #define PMU_VREG4_LPLDO2_0p90V 4 /**< 4 - 7 is 0.90V */ 2544 2545 #define PMU_VREG4_HSICLDO_BYPASS_SHIFT 27 2546 #define PMU_VREG4_HSICLDO_BYPASS_MASK 0x1 2547 2548 #define PMU_VREG5_ADDR 5 2549 #define PMU_VREG5_HSICAVDD_PD_SHIFT 6 2550 #define PMU_VREG5_HSICAVDD_PD_MASK 0x1 2551 #define PMU_VREG5_HSICDVDD_PD_SHIFT 11 2552 #define PMU_VREG5_HSICDVDD_PD_MASK 0x1 2553 2554 /* 4334 resources */ 2555 #define RES4334_LPLDO_PU 0 2556 #define RES4334_RESET_PULLDN_DIS 1 2557 #define RES4334_PMU_BG_PU 2 2558 #define RES4334_HSIC_LDO_PU 3 2559 #define RES4334_CBUCK_LPOM_PU 4 2560 #define RES4334_CBUCK_PFM_PU 5 2561 #define RES4334_CLDO_PU 6 2562 #define RES4334_LPLDO2_LVM 7 2563 #define RES4334_LNLDO_PU 8 2564 #define RES4334_LDO3P3_PU 9 2565 #define RES4334_OTP_PU 10 2566 #define RES4334_XTAL_PU 11 2567 #define RES4334_WL_PWRSW_PU 12 2568 #define RES4334_LQ_AVAIL 13 2569 #define RES4334_LOGIC_RET 14 2570 #define RES4334_MEM_SLEEP 15 2571 #define RES4334_MACPHY_RET 16 2572 #define RES4334_WL_CORE_READY 17 2573 #define RES4334_ILP_REQ 18 2574 #define RES4334_ALP_AVAIL 19 2575 #define RES4334_MISC_PWRSW_PU 20 2576 #define RES4334_SYNTH_PWRSW_PU 21 2577 #define RES4334_RX_PWRSW_PU 22 2578 #define RES4334_RADIO_PU 23 2579 #define RES4334_WL_PMU_PU 24 2580 #define RES4334_VCO_LDO_PU 25 2581 #define RES4334_AFE_LDO_PU 26 2582 #define RES4334_RX_LDO_PU 27 2583 #define RES4334_TX_LDO_PU 28 2584 #define RES4334_HT_AVAIL 29 2585 #define RES4334_MACPHY_CLK_AVAIL 30 2586 2587 /* 4334 chip-specific ChipStatus register bits */ 2588 #define CST4334_CHIPMODE_MASK 7 2589 #define CST4334_SDIO_MODE 0x00000000 2590 #define CST4334_SPI_MODE 0x00000004 2591 #define CST4334_HSIC_MODE 0x00000006 2592 #define CST4334_BLUSB_MODE 0x00000007 2593 #define CST4334_CHIPMODE_HSIC(cs) (((cs) & CST4334_CHIPMODE_MASK) == CST4334_HSIC_MODE) 2594 #define CST4334_OTP_PRESENT 0x00000010 2595 #define CST4334_LPO_AUTODET_EN 0x00000020 2596 #define CST4334_ARMREMAP_0 0x00000040 2597 #define CST4334_SPROM_PRESENT 0x00000080 2598 #define CST4334_ILPDIV_EN_MASK 0x00000100 2599 #define CST4334_ILPDIV_EN_SHIFT 8 2600 #define CST4334_LPO_SEL_MASK 0x00000200 2601 #define CST4334_LPO_SEL_SHIFT 9 2602 #define CST4334_RES_INIT_MODE_MASK 0x00000C00 2603 #define CST4334_RES_INIT_MODE_SHIFT 10 2604 2605 /* 4334 Chip specific PMU ChipControl register bits */ 2606 #define PCTL_4334_GPIO3_ENAB (1 << 3) 2607 2608 /* 4334 Chip control */ 2609 #define CCTRL4334_PMU_WAKEUP_GPIO1 (1 << 0) 2610 #define CCTRL4334_PMU_WAKEUP_HSIC (1 << 1) 2611 #define CCTRL4334_PMU_WAKEUP_AOS (1 << 2) 2612 #define CCTRL4334_HSIC_WAKE_MODE (1 << 3) 2613 #define CCTRL4334_HSIC_INBAND_GPIO1 (1 << 4) 2614 #define CCTRL4334_HSIC_LDO_PU (1 << 23) 2615 2616 /* 4334 Chip control 3 */ 2617 #define CCTRL4334_BLOCK_EXTRNL_WAKE (1 << 4) 2618 #define CCTRL4334_SAVERESTORE_FIX (1 << 5) 2619 2620 /* 43341 Chip control 3 */ 2621 #define CCTRL43341_BLOCK_EXTRNL_WAKE (1 << 13) 2622 #define CCTRL43341_SAVERESTORE_FIX (1 << 14) 2623 #define CCTRL43341_BT_ISO_SEL (1 << 16) 2624 2625 /* 4334 Chip specific ChipControl1 register bits */ 2626 #define CCTRL1_4334_GPIO_SEL (1 << 0) /* 1=select GPIOs to be muxed out */ 2627 #define CCTRL1_4334_ERCX_SEL (1 << 1) /* 1=select ERCX BT coex to be muxed out */ 2628 #define CCTRL1_4334_SDIO_HOST_WAKE (1 << 2) /* SDIO: 1=configure GPIO0 for host wake */ 2629 #define CCTRL1_4334_JTAG_DISABLE (1 << 3) /* 1=disable JTAG interface on mux'd pins */ 2630 #define CCTRL1_4334_UART_ON_4_5 (1 << 28) /**< 1=UART_TX/UART_RX muxed on GPIO_4/5 (4334B0/1) */ 2631 2632 /* 4324 Chip specific ChipControl1 register bits */ 2633 #define CCTRL1_4324_GPIO_SEL (1 << 0) /* 1=select GPIOs to be muxed out */ 2634 #define CCTRL1_4324_SDIO_HOST_WAKE (1 << 2) /* SDIO: 1=configure GPIO0 for host wake */ 2635 2636 /* 43143 chip-specific ChipStatus register bits based on Confluence documentation */ 2637 /* register contains strap values sampled during POR */ 2638 #define CST43143_REMAP_TO_ROM (3 << 0) /* 00=Boot SRAM, 01=Boot ROM, 10=Boot SFLASH */ 2639 #define CST43143_SDIO_EN (1 << 2) /* 0 = USB Enab, SDIO pins are GPIO or I2S */ 2640 #define CST43143_SDIO_ISO (1 << 3) /* 1 = SDIO isolated */ 2641 #define CST43143_USB_CPU_LESS (1 << 4) /* 1 = CPULess mode Enabled */ 2642 #define CST43143_CBUCK_MODE (3 << 6) /* Indicates what controller mode CBUCK is in */ 2643 #define CST43143_POK_CBUCK (1 << 8) /* 1 = 1.2V CBUCK voltage ready */ 2644 #define CST43143_PMU_OVRSPIKE (1 << 9) 2645 #define CST43143_PMU_OVRTEMP (0xF << 10) 2646 #define CST43143_SR_FLL_CAL_DONE (1 << 14) 2647 #define CST43143_USB_PLL_LOCKDET (1 << 15) 2648 #define CST43143_PMU_PLL_LOCKDET (1 << 16) 2649 #define CST43143_CHIPMODE_SDIOD(cs) (((cs) & CST43143_SDIO_EN) != 0) /* SDIO */ 2650 2651 /* 43143 Chip specific ChipControl register bits */ 2652 /* 00: SECI is disabled (JATG functional), 01: 2 wire, 10: 4 wire */ 2653 #define CCTRL_43143_SECI (1<<0) 2654 #define CCTRL_43143_BT_LEGACY (1<<1) 2655 #define CCTRL_43143_I2S_MODE (1<<2) /**< 0: SDIO enabled */ 2656 #define CCTRL_43143_I2S_MASTER (1<<3) /**< 0: I2S MCLK input disabled */ 2657 #define CCTRL_43143_I2S_FULL (1<<4) /**< 0: I2S SDIN and SPDIF_TX inputs disabled */ 2658 #define CCTRL_43143_GSIO (1<<5) /**< 0: sFlash enabled */ 2659 #define CCTRL_43143_RF_SWCTRL_MASK (7<<6) /**< 0: disabled */ 2660 #define CCTRL_43143_RF_SWCTRL_0 (1<<6) 2661 #define CCTRL_43143_RF_SWCTRL_1 (2<<6) 2662 #define CCTRL_43143_RF_SWCTRL_2 (4<<6) 2663 #define CCTRL_43143_RF_XSWCTRL (1<<9) /**< 0: UART enabled */ 2664 #define CCTRL_43143_HOST_WAKE0 (1<<11) /**< 1: SDIO separate interrupt output from GPIO4 */ 2665 #define CCTRL_43143_HOST_WAKE1 (1<<12) /* 1: SDIO separate interrupt output from GPIO16 */ 2666 2667 /* 43143 resources, based on pmu_params.xls V1.19 */ 2668 #define RES43143_EXT_SWITCHER_PWM 0 /**< 0x00001 */ 2669 #define RES43143_XTAL_PU 1 /**< 0x00002 */ 2670 #define RES43143_ILP_REQUEST 2 /**< 0x00004 */ 2671 #define RES43143_ALP_AVAIL 3 /**< 0x00008 */ 2672 #define RES43143_WL_CORE_READY 4 /**< 0x00010 */ 2673 #define RES43143_BBPLL_PWRSW_PU 5 /**< 0x00020 */ 2674 #define RES43143_HT_AVAIL 6 /**< 0x00040 */ 2675 #define RES43143_RADIO_PU 7 /**< 0x00080 */ 2676 #define RES43143_MACPHY_CLK_AVAIL 8 /**< 0x00100 */ 2677 #define RES43143_OTP_PU 9 /**< 0x00200 */ 2678 #define RES43143_LQ_AVAIL 10 /**< 0x00400 */ 2679 2680 #define PMU43143_XTAL_CORE_SIZE_MASK 0x3F 2681 2682 /* 4313 resources */ 2683 #define RES4313_BB_PU_RSRC 0 2684 #define RES4313_ILP_REQ_RSRC 1 2685 #define RES4313_XTAL_PU_RSRC 2 2686 #define RES4313_ALP_AVAIL_RSRC 3 2687 #define RES4313_RADIO_PU_RSRC 4 2688 #define RES4313_BG_PU_RSRC 5 2689 #define RES4313_VREG1P4_PU_RSRC 6 2690 #define RES4313_AFE_PWRSW_RSRC 7 2691 #define RES4313_RX_PWRSW_RSRC 8 2692 #define RES4313_TX_PWRSW_RSRC 9 2693 #define RES4313_BB_PWRSW_RSRC 10 2694 #define RES4313_SYNTH_PWRSW_RSRC 11 2695 #define RES4313_MISC_PWRSW_RSRC 12 2696 #define RES4313_BB_PLL_PWRSW_RSRC 13 2697 #define RES4313_HT_AVAIL_RSRC 14 2698 #define RES4313_MACPHY_CLK_AVAIL_RSRC 15 2699 2700 /* 4313 chip-specific ChipStatus register bits */ 2701 #define CST4313_SPROM_PRESENT 1 2702 #define CST4313_OTP_PRESENT 2 2703 #define CST4313_SPROM_OTP_SEL_MASK 0x00000002 2704 #define CST4313_SPROM_OTP_SEL_SHIFT 0 2705 2706 /* 4313 Chip specific ChipControl register bits */ 2707 #define CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */ 2708 2709 /* PMU respources for 4314 */ 2710 #define RES4314_LPLDO_PU 0 2711 #define RES4314_PMU_SLEEP_DIS 1 2712 #define RES4314_PMU_BG_PU 2 2713 #define RES4314_CBUCK_LPOM_PU 3 2714 #define RES4314_CBUCK_PFM_PU 4 2715 #define RES4314_CLDO_PU 5 2716 #define RES4314_LPLDO2_LVM 6 2717 #define RES4314_WL_PMU_PU 7 2718 #define RES4314_LNLDO_PU 8 2719 #define RES4314_LDO3P3_PU 9 2720 #define RES4314_OTP_PU 10 2721 #define RES4314_XTAL_PU 11 2722 #define RES4314_WL_PWRSW_PU 12 2723 #define RES4314_LQ_AVAIL 13 2724 #define RES4314_LOGIC_RET 14 2725 #define RES4314_MEM_SLEEP 15 2726 #define RES4314_MACPHY_RET 16 2727 #define RES4314_WL_CORE_READY 17 2728 #define RES4314_ILP_REQ 18 2729 #define RES4314_ALP_AVAIL 19 2730 #define RES4314_MISC_PWRSW_PU 20 2731 #define RES4314_SYNTH_PWRSW_PU 21 2732 #define RES4314_RX_PWRSW_PU 22 2733 #define RES4314_RADIO_PU 23 2734 #define RES4314_VCO_LDO_PU 24 2735 #define RES4314_AFE_LDO_PU 25 2736 #define RES4314_RX_LDO_PU 26 2737 #define RES4314_TX_LDO_PU 27 2738 #define RES4314_HT_AVAIL 28 2739 #define RES4314_MACPHY_CLK_AVAIL 29 2740 2741 /* 4314 chip-specific ChipStatus register bits */ 2742 #define CST4314_OTP_ENABLED 0x00200000 2743 2744 /* 43228 resources */ 2745 #define RES43228_NOT_USED 0 2746 #define RES43228_ILP_REQUEST 1 2747 #define RES43228_XTAL_PU 2 2748 #define RES43228_ALP_AVAIL 3 2749 #define RES43228_PLL_EN 4 2750 #define RES43228_HT_PHY_AVAIL 5 2751 2752 /* 43228 chipstatus reg bits */ 2753 #define CST43228_ILP_DIV_EN 0x1 2754 #define CST43228_OTP_PRESENT 0x2 2755 #define CST43228_SERDES_REFCLK_PADSEL 0x4 2756 #define CST43228_SDIO_MODE 0x8 2757 #define CST43228_SDIO_OTP_PRESENT 0x10 2758 #define CST43228_SDIO_RESET 0x20 2759 2760 /* 4706 chipstatus reg bits */ 2761 #define CST4706_PKG_OPTION (1<<0) /* 0: full-featured package 1: low-cost package */ 2762 #define CST4706_SFLASH_PRESENT (1<<1) /* 0: parallel, 1: serial flash is present */ 2763 #define CST4706_SFLASH_TYPE (1<<2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */ 2764 #define CST4706_MIPS_BENDIAN (1<<3) /* 0: little, 1: big endian */ 2765 #define CST4706_PCIE1_DISABLE (1<<5) /* PCIE1 enable strap pin */ 2766 2767 /* 4706 flashstrconfig reg bits */ 2768 #define FLSTRCF4706_MASK 0x000000ff 2769 #define FLSTRCF4706_SF1 0x00000001 /**< 2nd serial flash present */ 2770 #define FLSTRCF4706_PF1 0x00000002 /**< 2nd parallel flash present */ 2771 #define FLSTRCF4706_SF1_TYPE 0x00000004 /**< 2nd serial flash type : 0 : ST, 1 : Atmel */ 2772 #define FLSTRCF4706_NF1 0x00000008 /**< 2nd NAND flash present */ 2773 #define FLSTRCF4706_1ST_MADDR_SEG_MASK 0x000000f0 /**< Valid value mask */ 2774 #define FLSTRCF4706_1ST_MADDR_SEG_4MB 0x00000010 /**< 4MB */ 2775 #define FLSTRCF4706_1ST_MADDR_SEG_8MB 0x00000020 /**< 8MB */ 2776 #define FLSTRCF4706_1ST_MADDR_SEG_16MB 0x00000030 /**< 16MB */ 2777 #define FLSTRCF4706_1ST_MADDR_SEG_32MB 0x00000040 /**< 32MB */ 2778 #define FLSTRCF4706_1ST_MADDR_SEG_64MB 0x00000050 /**< 64MB */ 2779 #define FLSTRCF4706_1ST_MADDR_SEG_128MB 0x00000060 /**< 128MB */ 2780 #define FLSTRCF4706_1ST_MADDR_SEG_256MB 0x00000070 /**< 256MB */ 2781 2782 /* 4360 Chip specific ChipControl register bits */ 2783 #define CCTRL4360_I2C_MODE (1 << 0) 2784 #define CCTRL4360_UART_MODE (1 << 1) 2785 #define CCTRL4360_SECI_MODE (1 << 2) 2786 #define CCTRL4360_BTSWCTRL_MODE (1 << 3) 2787 #define CCTRL4360_DISCRETE_FEMCTRL_MODE (1 << 4) 2788 #define CCTRL4360_DIGITAL_PACTRL_MODE (1 << 5) 2789 #define CCTRL4360_BTSWCTRL_AND_DIGPA_PRESENT (1 << 6) 2790 #define CCTRL4360_EXTRA_GPIO_MODE (1 << 7) 2791 #define CCTRL4360_EXTRA_FEMCTRL_MODE (1 << 8) 2792 #define CCTRL4360_BT_LGCY_MODE (1 << 9) 2793 #define CCTRL4360_CORE2FEMCTRL4_ON (1 << 21) 2794 #define CCTRL4360_SECI_ON_GPIO01 (1 << 24) 2795 2796 /* 4360 Chip specific Regulator Control register bits */ 2797 #define RCTRL4360_RFLDO_PWR_DOWN (1 << 1) 2798 2799 /* 4360 PMU resources and chip status bits */ 2800 #define RES4360_REGULATOR 0 2801 #define RES4360_ILP_AVAIL 1 2802 #define RES4360_ILP_REQ 2 2803 #define RES4360_XTAL_LDO_PU 3 2804 #define RES4360_XTAL_PU 4 2805 #define RES4360_ALP_AVAIL 5 2806 #define RES4360_BBPLLPWRSW_PU 6 2807 #define RES4360_HT_AVAIL 7 2808 #define RES4360_OTP_PU 8 2809 #define RES4360_AVB_PLL_PWRSW_PU 9 2810 #define RES4360_PCIE_TL_CLK_AVAIL 10 2811 2812 #define CST4360_XTAL_40MZ 0x00000001 2813 #define CST4360_SFLASH 0x00000002 2814 #define CST4360_SPROM_PRESENT 0x00000004 2815 #define CST4360_SFLASH_TYPE 0x00000004 2816 #define CST4360_OTP_ENABLED 0x00000008 2817 #define CST4360_REMAP_ROM 0x00000010 2818 #define CST4360_RSRC_INIT_MODE_MASK 0x00000060 2819 #define CST4360_RSRC_INIT_MODE_SHIFT 5 2820 #define CST4360_ILP_DIVEN 0x00000080 2821 #define CST4360_MODE_USB 0x00000100 2822 #define CST4360_SPROM_SIZE_MASK 0x00000600 2823 #define CST4360_SPROM_SIZE_SHIFT 9 2824 #define CST4360_BBPLL_LOCK 0x00000800 2825 #define CST4360_AVBBPLL_LOCK 0x00001000 2826 #define CST4360_USBBBPLL_LOCK 0x00002000 2827 #define CST4360_RSRC_INIT_MODE(cs) ((cs & CST4360_RSRC_INIT_MODE_MASK) >> \ 2828 CST4360_RSRC_INIT_MODE_SHIFT) 2829 2830 #define CCTRL_4360_UART_SEL 0x2 2831 #define CST4360_RSRC_INIT_MODE(cs) ((cs & CST4360_RSRC_INIT_MODE_MASK) >> \ 2832 CST4360_RSRC_INIT_MODE_SHIFT) 2833 2834 #define PMU4360_CC1_GPIO7_OVRD (1<<23) /* GPIO7 override */ 2835 2836 2837 /* 43602 PMU resources based on pmu_params.xls version v0.95 */ 2838 #define RES43602_LPLDO_PU 0 2839 #define RES43602_REGULATOR 1 2840 #define RES43602_PMU_SLEEP 2 2841 #define RES43602_RSVD_3 3 2842 #define RES43602_XTALLDO_PU 4 2843 #define RES43602_SERDES_PU 5 2844 #define RES43602_BBPLL_PWRSW_PU 6 2845 #define RES43602_SR_CLK_START 7 2846 #define RES43602_SR_PHY_PWRSW 8 2847 #define RES43602_SR_SUBCORE_PWRSW 9 2848 #define RES43602_XTAL_PU 10 2849 #define RES43602_PERST_OVR 11 2850 #define RES43602_SR_CLK_STABLE 12 2851 #define RES43602_SR_SAVE_RESTORE 13 2852 #define RES43602_SR_SLEEP 14 2853 #define RES43602_LQ_START 15 2854 #define RES43602_LQ_AVAIL 16 2855 #define RES43602_WL_CORE_RDY 17 2856 #define RES43602_ILP_REQ 18 2857 #define RES43602_ALP_AVAIL 19 2858 #define RES43602_RADIO_PU 20 2859 #define RES43602_RFLDO_PU 21 2860 #define RES43602_HT_START 22 2861 #define RES43602_HT_AVAIL 23 2862 #define RES43602_MACPHY_CLKAVAIL 24 2863 #define RES43602_PARLDO_PU 25 2864 #define RES43602_RSVD_26 26 2865 2866 /* 43602 chip status bits */ 2867 #define CST43602_SPROM_PRESENT (1<<1) 2868 #define CST43602_SPROM_SIZE (1<<10) /* 0 = 16K, 1 = 4K */ 2869 #define CST43602_BBPLL_LOCK (1<<11) 2870 #define CST43602_RF_LDO_OUT_OK (1<<15) /* RF LDO output OK */ 2871 2872 #define PMU43602_CC1_GPIO12_OVRD (1<<28) /* GPIO12 override */ 2873 2874 #define PMU43602_CC2_PCIE_CLKREQ_L_WAKE_EN (1<<1) /* creates gated_pcie_wake, pmu_wakeup logic */ 2875 #define PMU43602_CC2_PCIE_PERST_L_WAKE_EN (1<<2) /* creates gated_pcie_wake, pmu_wakeup logic */ 2876 #define PMU43602_CC2_ENABLE_L2REFCLKPAD_PWRDWN (1<<3) 2877 #define PMU43602_CC2_PMU_WAKE_ALP_AVAIL_EN (1<<5) /* enable pmu_wakeup to request for ALP_AVAIL */ 2878 #define PMU43602_CC2_PERST_L_EXTEND_EN (1<<9) /* extend perst_l until rsc PERST_OVR comes up */ 2879 #define PMU43602_CC2_FORCE_EXT_LPO (1<<19) /* 1=ext LPO clock is the final LPO clock */ 2880 #define PMU43602_CC2_XTAL32_SEL (1<<30) /* 0=ext_clock, 1=xtal */ 2881 2882 #define CC_SR1_43602_SR_ASM_ADDR (0x0) 2883 2884 /* PLL CTL register values for open loop, used during S/R operation */ 2885 #define PMU43602_PLL_CTL6_VAL 0x68000528 2886 #define PMU43602_PLL_CTL7_VAL 0x6 2887 2888 #define PMU43602_CC3_ARMCR4_DBG_CLK (1 << 29) 2889 2890 /* 4365 PMU resources */ 2891 #define RES4365_REGULATOR_PU 0 2892 #define RES4365_XTALLDO_PU 1 2893 #define RES4365_XTAL_PU 2 2894 #define RES4365_CPU_PLLLDO_PU 3 2895 #define RES4365_CPU_PLL_PU 4 2896 #define RES4365_WL_CORE_RDY 5 2897 #define RES4365_ILP_REQ 6 2898 #define RES4365_ALP_AVAIL 7 2899 #define RES4365_HT_AVAIL 8 2900 #define RES4365_BB_PLLLDO_PU 9 2901 #define RES4365_BB_PLL_PU 10 2902 #define RES4365_MINIMU_PU 11 2903 #define RES4365_RADIO_PU 12 2904 #define RES4365_MACPHY_CLK_AVAIL 13 2905 2906 /* 4349 related */ 2907 #define RES4349_LPLDO_PU 0 2908 #define RES4349_BG_PU 1 2909 #define RES4349_PMU_SLEEP 2 2910 #define RES4349_PALDO3P3_PU 3 2911 #define RES4349_CBUCK_LPOM_PU 4 2912 #define RES4349_CBUCK_PFM_PU 5 2913 #define RES4349_COLD_START_WAIT 6 2914 #define RES4349_RSVD_7 7 2915 #define RES4349_LNLDO_PU 8 2916 #define RES4349_XTALLDO_PU 9 2917 #define RES4349_LDO3P3_PU 10 2918 #define RES4349_OTP_PU 11 2919 #define RES4349_XTAL_PU 12 2920 #define RES4349_SR_CLK_START 13 2921 #define RES4349_LQ_AVAIL 14 2922 #define RES4349_LQ_START 15 2923 #define RES4349_PERST_OVR 16 2924 #define RES4349_WL_CORE_RDY 17 2925 #define RES4349_ILP_REQ 18 2926 #define RES4349_ALP_AVAIL 19 2927 #define RES4349_MINI_PMU 20 2928 #define RES4349_RADIO_PU 21 2929 #define RES4349_SR_CLK_STABLE 22 2930 #define RES4349_SR_SAVE_RESTORE 23 2931 #define RES4349_SR_PHY_PWRSW 24 2932 #define RES4349_SR_VDDM_PWRSW 25 2933 #define RES4349_SR_SUBCORE_PWRSW 26 2934 #define RES4349_SR_SLEEP 27 2935 #define RES4349_HT_START 28 2936 #define RES4349_HT_AVAIL 29 2937 #define RES4349_MACPHY_CLKAVAIL 30 2938 2939 /* SR Control0 bits */ 2940 #define CC_SR0_4349_SR_ENG_EN_MASK 0x1 2941 #define CC_SR0_4349_SR_ENG_EN_SHIFT 0 2942 #define CC_SR0_4349_SR_ENG_CLK_EN (1 << 1) 2943 #define CC_SR0_4349_SR_RSRC_TRIGGER (0xC << 2) 2944 #define CC_SR0_4349_SR_WD_MEM_MIN_DIV (0x3 << 6) 2945 #define CC_SR0_4349_SR_MEM_STBY_ALLOW_MSK (1 << 16) 2946 #define CC_SR0_4349_SR_MEM_STBY_ALLOW_SHIFT 16 2947 #define CC_SR0_4349_SR_ENABLE_ILP (1 << 17) 2948 #define CC_SR0_4349_SR_ENABLE_ALP (1 << 18) 2949 #define CC_SR0_4349_SR_ENABLE_HT (1 << 19) 2950 #define CC_SR0_4349_SR_ALLOW_PIC (3 << 20) 2951 #define CC_SR0_4349_SR_PMU_MEM_DISABLE (1 << 30) 2952 2953 /* SR Control0 bits */ 2954 #define CC_SR0_4349_SR_ENG_EN_MASK 0x1 2955 #define CC_SR0_4349_SR_ENG_EN_SHIFT 0 2956 #define CC_SR0_4349_SR_ENG_CLK_EN (1 << 1) 2957 #define CC_SR0_4349_SR_RSRC_TRIGGER (0xC << 2) 2958 #define CC_SR0_4349_SR_WD_MEM_MIN_DIV (0x3 << 6) 2959 #define CC_SR0_4349_SR_MEM_STBY_ALLOW (1 << 16) 2960 #define CC_SR0_4349_SR_ENABLE_ILP (1 << 17) 2961 #define CC_SR0_4349_SR_ENABLE_ALP (1 << 18) 2962 #define CC_SR0_4349_SR_ENABLE_HT (1 << 19) 2963 #define CC_SR0_4349_SR_ALLOW_PIC (3 << 20) 2964 #define CC_SR0_4349_SR_PMU_MEM_DISABLE (1 << 30) 2965 2966 /* SR binary offset is at 8K */ 2967 #define CC_SR1_4349_SR_ASM_ADDR (0x10) 2968 2969 #define CST4349_CHIPMODE_SDIOD(cs) (((cs) & (1 << 6)) != 0) /* SDIO */ 2970 #define CST4349_CHIPMODE_PCIE(cs) (((cs) & (1 << 7)) != 0) /* PCIE */ 2971 2972 #define CST4349_SPROM_PRESENT 0x00000010 2973 2974 #define VREG4_4349_MEMLPLDO_PWRUP_MASK (1 << 31) 2975 #define VREG4_4349_MEMLPLDO_PWRUP_SHIFT (31) 2976 #define VREG4_4349_LPLDO1_OUTPUT_VOLT_ADJ_MASK (0x7 << 15) 2977 #define VREG4_4349_LPLDO1_OUTPUT_VOLT_ADJ_SHIFT (15) 2978 #define CC2_4349_PHY_PWRSE_RST_CNT_MASK (0xF << 0) 2979 #define CC2_4349_PHY_PWRSE_RST_CNT_SHIFT (0) 2980 #define CC2_4349_VDDM_PWRSW_EN_MASK (1 << 20) 2981 #define CC2_4349_VDDM_PWRSW_EN_SHIFT (20) 2982 #define CC2_4349_MEMLPLDO_PWRSW_EN_MASK (1 << 21) 2983 #define CC2_4349_MEMLPLDO_PWRSW_EN_SHIFT (21) 2984 #define CC2_4349_SDIO_AOS_WAKEUP_MASK (1 << 24) 2985 #define CC2_4349_SDIO_AOS_WAKEUP_SHIFT (24) 2986 #define CC2_4349_PMUWAKE_EN_MASK (1 << 31) 2987 #define CC2_4349_PMUWAKE_EN_SHIFT (31) 2988 2989 #define CC5_4349_MAC_PHY_CLK_8_DIV (1 << 27) 2990 2991 #define CC6_4349_PCIE_CLKREQ_WAKEUP_MASK (1 << 4) 2992 #define CC6_4349_PCIE_CLKREQ_WAKEUP_SHIFT (4) 2993 #define CC6_4349_PMU_WAKEUP_ALPAVAIL_MASK (1 << 6) 2994 #define CC6_4349_PMU_WAKEUP_ALPAVAIL_SHIFT (6) 2995 #define CC6_4349_PMU_EN_EXT_PERST_MASK (1 << 13) 2996 #define CC6_4349_PMU_EN_L2_DEASSERT_MASK (1 << 14) 2997 #define CC6_4349_PMU_EN_L2_DEASSERT_SHIF (14) 2998 #define CC6_4349_PMU_ENABLE_L2REFCLKPAD_PWRDWN (1 << 15) 2999 #define CC6_4349_PMU_EN_MDIO_MASK (1 << 16) 3000 #define CC6_4349_PMU_EN_ASSERT_L2_MASK (1 << 25) 3001 3002 3003 /* 4349 GCI function sel values */ 3004 /* 3005 * Reference 3006 * http://hwnbu-twiki.sj.broadcom.com/bin/view/Mwgroup/ToplevelArchitecture4349B0#Function_Sel 3007 */ 3008 #define CC4349_FNSEL_HWDEF (0) 3009 #define CC4349_FNSEL_SAMEASPIN (1) 3010 #define CC4349_FNSEL_GPIO (2) 3011 #define CC4349_FNSEL_FAST_UART (3) 3012 #define CC4349_FNSEL_GCI0 (4) 3013 #define CC4349_FNSEL_GCI1 (5) 3014 #define CC4349_FNSEL_DGB_UART (6) 3015 #define CC4349_FNSEL_I2C (7) 3016 #define CC4349_FNSEL_SPROM (8) 3017 #define CC4349_FNSEL_MISC0 (9) 3018 #define CC4349_FNSEL_MISC1 (10) 3019 #define CC4349_FNSEL_MISC2 (11) 3020 #define CC4349_FNSEL_IND (12) 3021 #define CC4349_FNSEL_PDN (13) 3022 #define CC4349_FNSEL_PUP (14) 3023 #define CC4349_FNSEL_TRISTATE (15) 3024 3025 /* 4364 related */ 3026 #define RES4364_LPLDO_PU 0 3027 #define RES4364_BG_PU 1 3028 #define RES4364_MEMLPLDO_PU 2 3029 #define RES4364_PALDO3P3_PU 3 3030 #define RES4364_CBUCK_1P2 4 3031 #define RES4364_CBUCK_1V8 5 3032 #define RES4364_COLD_START_WAIT 6 3033 #define RES4364_SR_3x3_VDDM_PWRSW 7 3034 #define RES4364_3x3_MACPHY_CLKAVAIL 8 3035 #define RES4364_XTALLDO_PU 9 3036 #define RES4364_LDO3P3_PU 10 3037 #define RES4364_OTP_PU 11 3038 #define RES4364_XTAL_PU 12 3039 #define RES4364_SR_CLK_START 13 3040 #define RES4364_3x3_RADIO_PU 14 3041 #define RES4364_RF_LDO 15 3042 #define RES4364_PERST_OVR 16 3043 #define RES4364_WL_CORE_RDY 17 3044 #define RES4364_ILP_REQ 18 3045 #define RES4364_ALP_AVAIL 19 3046 #define RES4364_1x1_MINI_PMU 20 3047 #define RES4364_1x1_RADIO_PU 21 3048 #define RES4364_SR_CLK_STABLE 22 3049 #define RES4364_SR_SAVE_RESTORE 23 3050 #define RES4364_SR_PHY_PWRSW 24 3051 #define RES4364_SR_VDDM_PWRSW 25 3052 #define RES4364_SR_SUBCORE_PWRSW 26 3053 #define RES4364_SR_SLEEP 27 3054 #define RES4364_HT_START 28 3055 #define RES4364_HT_AVAIL 29 3056 #define RES4364_MACPHY_CLKAVAIL 30 3057 3058 /* 4349 GPIO */ 3059 #define CC4349_PIN_GPIO_00 (0) 3060 #define CC4349_PIN_GPIO_01 (1) 3061 #define CC4349_PIN_GPIO_02 (2) 3062 #define CC4349_PIN_GPIO_03 (3) 3063 #define CC4349_PIN_GPIO_04 (4) 3064 #define CC4349_PIN_GPIO_05 (5) 3065 #define CC4349_PIN_GPIO_06 (6) 3066 #define CC4349_PIN_GPIO_07 (7) 3067 #define CC4349_PIN_GPIO_08 (8) 3068 #define CC4349_PIN_GPIO_09 (9) 3069 #define CC4349_PIN_GPIO_10 (10) 3070 #define CC4349_PIN_GPIO_11 (11) 3071 #define CC4349_PIN_GPIO_12 (12) 3072 #define CC4349_PIN_GPIO_13 (13) 3073 #define CC4349_PIN_GPIO_14 (14) 3074 #define CC4349_PIN_GPIO_15 (15) 3075 #define CC4349_PIN_GPIO_16 (16) 3076 #define CC4349_PIN_GPIO_17 (17) 3077 #define CC4349_PIN_GPIO_18 (18) 3078 #define CC4349_PIN_GPIO_19 (19) 3079 3080 /* Mask used to decide whether HOSTWAKE MUX to be performed or not */ 3081 #define MUXENAB4349_HOSTWAKE_MASK (0x000000f0) /* configure GPIO for SDIO host_wake */ 3082 #define MUXENAB4349_HOSTWAKE_SHIFT 4 3083 #define MUXENAB4349_GETIX(val, name) \ 3084 ((((val) & MUXENAB4349_ ## name ## _MASK) >> MUXENAB4349_ ## name ## _SHIFT) - 1) 3085 3086 #define CR4_4364_RAM_BASE (0x160000) 3087 3088 /* SR binary offset is at 8K */ 3089 #define CC_SR1_4364_SR_CORE0_ASM_ADDR (0x10) 3090 #define CC_SR1_4364_SR_CORE1_ASM_ADDR (0x10) 3091 3092 #define CC_SR0_4364_SR_ENG_EN_MASK 0x1 3093 #define CC_SR0_4364_SR_ENG_EN_SHIFT 0 3094 #define CC_SR0_4364_SR_ENG_CLK_EN (1 << 1) 3095 #define CC_SR0_4364_SR_RSRC_TRIGGER (0xC << 2) 3096 #define CC_SR0_4364_SR_WD_MEM_MIN_DIV (0x3 << 6) 3097 #define CC_SR0_4364_SR_MEM_STBY_ALLOW_MSK (1 << 16) 3098 #define CC_SR0_4364_SR_MEM_STBY_ALLOW_SHIFT 16 3099 #define CC_SR0_4364_SR_ENABLE_ILP (1 << 17) 3100 #define CC_SR0_4364_SR_ENABLE_ALP (1 << 18) 3101 #define CC_SR0_4364_SR_ENABLE_HT (1 << 19) 3102 #define CC_SR0_4364_SR_ALLOW_PIC (3 << 20) 3103 #define CC_SR0_4364_SR_PMU_MEM_DISABLE (1 << 30) 3104 3105 #define PMU_4364_CC1_ENABLE_BBPLL_PWR_DWN (0x1 << 4) 3106 #define PMU_4364_CC1_BBPLL_ARESET_LQ_TIME (0x1 << 8) 3107 #define PMU_4364_CC1_BBPLL_ARESET_HT_UPTIME (0x1 << 10) 3108 #define PMU_4364_CC1_BBPLL_DRESET_LQ_UPTIME (0x1 << 12) 3109 #define PMU_4364_CC1_BBPLL_DRESET_HT_UPTIME (0x4 << 16) 3110 #define PMU_4364_CC1_SUBCORE_PWRSW_UP_DELAY (0x8 << 20) 3111 #define PMU_4364_CC1_SUBCORE_PWRSW_RESET_CNT (0x4 << 24) 3112 3113 #define PMU_4364_CC2_PHY_PWRSW_RESET_CNT (0x2 << 0) 3114 #define PMU_4364_CC2_PHY_PWRSW_RESET_MASK (0x7) 3115 #define PMU_4364_CC2_SEL_CHIPC_IF_FOR_SR (1 << 21) 3116 3117 #define PMU_4364_CC3_MEMLPLDO3x3_PWRSW_FORCE_MASK (1 << 23) 3118 #define PMU_4364_CC3_MEMLPLDO1x1_PWRSW_FORCE_MASK (1 << 24) 3119 #define PMU_4364_CC3_CBUCK1P2_PU_SR_VDDM_REQ_ON (1 << 25) 3120 #define PMU_4364_CC3_MEMLPLDO3x3_PWRSW_FORCE_OFF (0) 3121 #define PMU_4364_CC3_MEMLPLDO1x1_PWRSW_FORCE_OFF (0) 3122 3123 3124 #define PMU_4364_CC5_DISABLE_BBPLL_CLKOUT6_DIV2_MASK (1 << 26) 3125 #define PMU_4364_CC5_ENABLE_ARMCR4_DEBUG_CLK_MASK (1 << 4) 3126 #define PMU_4364_CC5_DISABLE_BBPLL_CLKOUT6_DIV2 (1 << 26) 3127 #define PMU_4364_CC5_ENABLE_ARMCR4_DEBUG_CLK_OFF (0) 3128 3129 #define PMU_4364_CC6_MDI_RESET_MASK (1 << 16) 3130 #define PMU_4364_CC6_USE_CLK_REQ_MASK (1 << 18) 3131 #define PMU_4364_CC6_HIGHER_CLK_REQ_ALP_MASK (1 << 20) 3132 #define PMU_4364_CC6_HT_AVAIL_REQ_ALP_AVAIL_MASK (1 << 21) 3133 #define PMU_4364_CC6_PHY_CLK_REQUESTS_ALP_AVAIL_MASK (1 << 22) 3134 #define PMU_4364_CC6_MDI_RESET (1 << 16) 3135 #define PMU_4364_CC6_USE_CLK_REQ (1 << 18) 3136 3137 #define PMU_4364_CC6_HIGHER_CLK_REQ_ALP (1 << 20) 3138 #define PMU_4364_CC6_HT_AVAIL_REQ_ALP_AVAIL (1 << 21) 3139 #define PMU_4364_CC6_PHY_CLK_REQUESTS_ALP_AVAIL (1 << 22) 3140 3141 #define PMU_4364_VREG0_DISABLE_BT_PULL_DOWN (1 << 2) 3142 #define PMU_4364_VREG1_DISABLE_WL_PULL_DOWN (1 << 2) 3143 3144 #define PMU_VREG_0 (0x0) 3145 #define PMU_VREG_1 (0x1) 3146 #define PMU_VREG_3 (0x3) 3147 #define PMU_VREG_4 (0x4) 3148 #define PMU_VREG_5 (0x5) 3149 #define PMU_VREG_6 (0x6) 3150 3151 #define PMU_4364_VREG3_DISABLE_WPT_REG_ON_PULL_DOWN (1 << 11) 3152 3153 #define PMU_4364_VREG4_MEMLPLDO_PU_ON (1 << 31) 3154 #define PMU_4364_VREG4_LPLPDO_ADJ (3 << 16) 3155 #define PMU_4364_VREG4_LPLPDO_ADJ_MASK (3 << 16) 3156 #define PMU_4364_VREG5_MAC_CLK_1x1_AUTO (0x1 << 18) 3157 #define PMU_4364_VREG5_SR_AUTO (0x1 << 20) 3158 #define PMU_4364_VREG5_BT_PWM_MASK (0x1 << 21) 3159 #define PMU_4364_VREG5_BT_AUTO (0x1 << 22) 3160 #define PMU_4364_VREG5_WL2CLB_DVFS_EN_MASK (0x1 << 23) 3161 #define PMU_4364_VREG5_BT_PWMK (0) 3162 #define PMU_4364_VREG5_WL2CLB_DVFS_EN (0) 3163 3164 #define PMU_4364_VREG6_BBPLL_AUTO (0x1 << 17) 3165 #define PMU_4364_VREG6_MINI_PMU_PWM (0x1 << 18) 3166 #define PMU_4364_VREG6_LNLDO_AUTO (0x1 << 21) 3167 #define PMU_4364_VREG6_PCIE_PWRDN_0_AUTO (0x1 << 23) 3168 #define PMU_4364_VREG6_PCIE_PWRDN_1_AUTO (0x1 << 25) 3169 #define PMU_4364_VREG6_MAC_CLK_3x3_PWM (0x1 << 27) 3170 #define PMU_4364_VREG6_ENABLE_FINE_CTRL (0x1 << 30) 3171 3172 #define PMU_4364_PLL0_DISABLE_CHANNEL6 (0x1 << 18) 3173 3174 #define CC_GCI1_REG (0x1) 3175 #define CC_GCI1_4364_IND_STATE_FOR_GPIO9_11 (0x0ccccccc) 3176 #define CC2_4364_SDIO_AOS_WAKEUP_MASK (1 << 24) 3177 #define CC2_4364_SDIO_AOS_WAKEUP_SHIFT (24) 3178 3179 #define CC6_4364_PCIE_CLKREQ_WAKEUP_MASK (1 << 4) 3180 #define CC6_4364_PCIE_CLKREQ_WAKEUP_SHIFT (4) 3181 #define CC6_4364_PMU_WAKEUP_ALPAVAIL_MASK (1 << 6) 3182 #define CC6_4364_PMU_WAKEUP_ALPAVAIL_SHIFT (6) 3183 3184 #define CST4364_CHIPMODE_SDIOD(cs) (((cs) & (1 << 6)) != 0) /* SDIO */ 3185 #define CST4364_CHIPMODE_PCIE(cs) (((cs) & (1 << 7)) != 0) /* PCIE */ 3186 #define CST4364_SPROM_PRESENT 0x00000010 3187 3188 #define PMU_4364_MACCORE_0_RES_REQ_MASK 0x3FCBF7FF 3189 #define PMU_4364_MACCORE_1_RES_REQ_MASK 0x7FFB3647 3190 3191 3192 #define PMU1_PLL0_SWITCH_MACCLOCK_120MHZ (0) 3193 #define PMU1_PLL0_SWITCH_MACCLOCK_160MHZ (1) 3194 #define TSF_CLK_FRAC_L_4364_120MHZ 0x8889 3195 #define TSF_CLK_FRAC_H_4364_120MHZ 0x8 3196 #define TSF_CLK_FRAC_L_4364_160MHZ 0x6666 3197 #define TSF_CLK_FRAC_H_4364_160MHZ 0x6 3198 #define PMU1_PLL0_PC1_M2DIV_VALUE_120MHZ 8 3199 #define PMU1_PLL0_PC1_M2DIV_VALUE_160MHZ 6 3200 3201 #define CST4347_CHIPMODE_SDIOD(cs) (((cs) & (1 << 6)) != 0) /* SDIO */ 3202 #define CST4347_CHIPMODE_PCIE(cs) (((cs) & (1 << 7)) != 0) /* PCIE */ 3203 #define CST4347_SPROM_PRESENT 0x00000010 3204 3205 /* 43430 PMU resources based on pmu_params.xls */ 3206 #define RES43430_LPLDO_PU 0 3207 #define RES43430_BG_PU 1 3208 #define RES43430_PMU_SLEEP 2 3209 #define RES43430_RSVD_3 3 3210 #define RES43430_CBUCK_LPOM_PU 4 3211 #define RES43430_CBUCK_PFM_PU 5 3212 #define RES43430_COLD_START_WAIT 6 3213 #define RES43430_RSVD_7 7 3214 #define RES43430_LNLDO_PU 8 3215 #define RES43430_RSVD_9 9 3216 #define RES43430_LDO3P3_PU 10 3217 #define RES43430_OTP_PU 11 3218 #define RES43430_XTAL_PU 12 3219 #define RES43430_SR_CLK_START 13 3220 #define RES43430_LQ_AVAIL 14 3221 #define RES43430_LQ_START 15 3222 #define RES43430_RSVD_16 16 3223 #define RES43430_WL_CORE_RDY 17 3224 #define RES43430_ILP_REQ 18 3225 #define RES43430_ALP_AVAIL 19 3226 #define RES43430_MINI_PMU 20 3227 #define RES43430_RADIO_PU 21 3228 #define RES43430_SR_CLK_STABLE 22 3229 #define RES43430_SR_SAVE_RESTORE 23 3230 #define RES43430_SR_PHY_PWRSW 24 3231 #define RES43430_SR_VDDM_PWRSW 25 3232 #define RES43430_SR_SUBCORE_PWRSW 26 3233 #define RES43430_SR_SLEEP 27 3234 #define RES43430_HT_START 28 3235 #define RES43430_HT_AVAIL 29 3236 #define RES43430_MACPHY_CLK_AVAIL 30 3237 3238 /* 43430 chip status bits */ 3239 #define CST43430_SDIO_MODE 0x00000001 3240 #define CST43430_GSPI_MODE 0x00000002 3241 #define CST43430_RSRC_INIT_MODE_0 0x00000080 3242 #define CST43430_RSRC_INIT_MODE_1 0x00000100 3243 #define CST43430_SEL0_SDIO 0x00000200 3244 #define CST43430_SEL1_SDIO 0x00000400 3245 #define CST43430_SEL2_SDIO 0x00000800 3246 #define CST43430_BBPLL_LOCKED 0x00001000 3247 #define CST43430_DBG_INST_DETECT 0x00004000 3248 #define CST43430_CLB2WL_BT_READY 0x00020000 3249 #define CST43430_JTAG_MODE 0x00100000 3250 #define CST43430_HOST_IFACE 0x00400000 3251 #define CST43430_TRIM_EN 0x00800000 3252 #define CST43430_DIN_PACKAGE_OPTION 0x10000000 3253 3254 #define PMU43430_PLL0_PC2_P1DIV_MASK 0x0000000f 3255 #define PMU43430_PLL0_PC2_P1DIV_SHIFT 0 3256 #define PMU43430_PLL0_PC2_NDIV_INT_MASK 0x0000ff80 3257 #define PMU43430_PLL0_PC2_NDIV_INT_SHIFT 7 3258 #define PMU43430_PLL0_PC4_MDIV2_MASK 0x0000ff00 3259 #define PMU43430_PLL0_PC4_MDIV2_SHIFT 8 3260 3261 /* 43430 chip SR definitions */ 3262 #define SRAM_43430_SR_ASM_ADDR 0x7f800 3263 #define CC_SR1_43430_SR_ASM_ADDR ((SRAM_43430_SR_ASM_ADDR - 0x60000) >> 8) 3264 3265 /* 43430 PMU Chip Control bits */ 3266 #define CC2_43430_SDIO_AOS_WAKEUP_MASK (1 << 24) 3267 #define CC2_43430_SDIO_AOS_WAKEUP_SHIFT (24) 3268 3269 3270 #define PMU_MACCORE_0_RES_REQ_TIMER 0x1d000000 3271 #define PMU_MACCORE_0_RES_REQ_MASK 0x5FF2364F 3272 3273 #define PMU_MACCORE_1_RES_REQ_TIMER 0x1d000000 3274 #define PMU_MACCORE_1_RES_REQ_MASK 0x5FF2364F 3275 3276 /* defines to detect active host interface in use */ 3277 #define CHIP_HOSTIF_PCIEMODE 0x1 3278 #define CHIP_HOSTIF_USBMODE 0x2 3279 #define CHIP_HOSTIF_SDIOMODE 0x4 3280 #define CHIP_HOSTIF_PCIE(sih) (si_chip_hostif(sih) == CHIP_HOSTIF_PCIEMODE) 3281 #define CHIP_HOSTIF_USB(sih) (si_chip_hostif(sih) == CHIP_HOSTIF_USBMODE) 3282 #define CHIP_HOSTIF_SDIO(sih) (si_chip_hostif(sih) == CHIP_HOSTIF_SDIOMODE) 3283 3284 /* 4335 resources */ 3285 #define RES4335_LPLDO_PO 0 3286 #define RES4335_PMU_BG_PU 1 3287 #define RES4335_PMU_SLEEP 2 3288 #define RES4335_RSVD_3 3 3289 #define RES4335_CBUCK_LPOM_PU 4 3290 #define RES4335_CBUCK_PFM_PU 5 3291 #define RES4335_RSVD_6 6 3292 #define RES4335_RSVD_7 7 3293 #define RES4335_LNLDO_PU 8 3294 #define RES4335_XTALLDO_PU 9 3295 #define RES4335_LDO3P3_PU 10 3296 #define RES4335_OTP_PU 11 3297 #define RES4335_XTAL_PU 12 3298 #define RES4335_SR_CLK_START 13 3299 #define RES4335_LQ_AVAIL 14 3300 #define RES4335_LQ_START 15 3301 #define RES4335_RSVD_16 16 3302 #define RES4335_WL_CORE_RDY 17 3303 #define RES4335_ILP_REQ 18 3304 #define RES4335_ALP_AVAIL 19 3305 #define RES4335_MINI_PMU 20 3306 #define RES4335_RADIO_PU 21 3307 #define RES4335_SR_CLK_STABLE 22 3308 #define RES4335_SR_SAVE_RESTORE 23 3309 #define RES4335_SR_PHY_PWRSW 24 3310 #define RES4335_SR_VDDM_PWRSW 25 3311 #define RES4335_SR_SUBCORE_PWRSW 26 3312 #define RES4335_SR_SLEEP 27 3313 #define RES4335_HT_START 28 3314 #define RES4335_HT_AVAIL 29 3315 #define RES4335_MACPHY_CLKAVAIL 30 3316 3317 /* 4335 Chip specific ChipStatus register bits */ 3318 #define CST4335_SPROM_MASK 0x00000020 3319 #define CST4335_SFLASH_MASK 0x00000040 3320 #define CST4335_RES_INIT_MODE_SHIFT 7 3321 #define CST4335_RES_INIT_MODE_MASK 0x00000180 3322 #define CST4335_CHIPMODE_MASK 0xF 3323 #define CST4335_CHIPMODE_SDIOD(cs) (((cs) & (1 << 0)) != 0) /* SDIO */ 3324 #define CST4335_CHIPMODE_GSPI(cs) (((cs) & (1 << 1)) != 0) /* gSPI */ 3325 #define CST4335_CHIPMODE_USB20D(cs) (((cs) & (1 << 2)) != 0) /**< HSIC || USBDA */ 3326 #define CST4335_CHIPMODE_PCIE(cs) (((cs) & (1 << 3)) != 0) /* PCIE */ 3327 3328 /* 4335 Chip specific ChipControl1 register bits */ 3329 #define CCTRL1_4335_GPIO_SEL (1 << 0) /* 1=select GPIOs to be muxed out */ 3330 #define CCTRL1_4335_SDIO_HOST_WAKE (1 << 2) /* SDIO: 1=configure GPIO0 for host wake */ 3331 3332 /* 4335 Chip specific ChipControl2 register bits */ 3333 #define CCTRL2_4335_AOSBLOCK (1 << 30) 3334 #define CCTRL2_4335_PMUWAKE (1 << 31) 3335 #define PATCHTBL_SIZE (0x800) 3336 #define CR4_4335_RAM_BASE (0x180000) 3337 #define CR4_4345_LT_C0_RAM_BASE (0x1b0000) 3338 #define CR4_4345_GE_C0_RAM_BASE (0x198000) 3339 #define CR4_4349_RAM_BASE (0x180000) 3340 #define CR4_4349_RAM_BASE_FROM_REV_9 (0x160000) 3341 #define CR4_4350_RAM_BASE (0x180000) 3342 #define CR4_4360_RAM_BASE (0x0) 3343 #define CR4_43602_RAM_BASE (0x180000) 3344 #define CA7_4365_RAM_BASE (0x200000) 3345 3346 #define CR4_4347_RAM_BASE (0x170000) 3347 #define CR4_4362_RAM_BASE (0x170000) 3348 3349 /* 4335 chip OTP present & OTP select bits. */ 3350 #define SPROM4335_OTP_SELECT 0x00000010 3351 #define SPROM4335_OTP_PRESENT 0x00000020 3352 3353 /* 4335 GCI specific bits. */ 3354 #define CC4335_GCI_STRAP_OVERRIDE_SFLASH_PRESENT (1 << 24) 3355 #define CC4335_GCI_STRAP_OVERRIDE_SFLASH_TYPE 25 3356 #define CC4335_GCI_FUNC_SEL_PAD_SDIO 0x00707770 3357 3358 /* SFLASH clkdev specific bits. */ 3359 #define CC4335_SFLASH_CLKDIV_MASK 0x1F000000 3360 #define CC4335_SFLASH_CLKDIV_SHIFT 25 3361 3362 /* 4335 OTP bits for SFLASH. */ 3363 #define CC4335_SROM_OTP_SFLASH 40 3364 #define CC4335_SROM_OTP_SFLASH_PRESENT 0x1 3365 #define CC4335_SROM_OTP_SFLASH_TYPE 0x2 3366 #define CC4335_SROM_OTP_SFLASH_CLKDIV_MASK 0x003C 3367 #define CC4335_SROM_OTP_SFLASH_CLKDIV_SHIFT 2 3368 3369 3370 /* 4335 chip OTP present & OTP select bits. */ 3371 #define SPROM4335_OTP_SELECT 0x00000010 3372 #define SPROM4335_OTP_PRESENT 0x00000020 3373 3374 /* 4335 GCI specific bits. */ 3375 #define CC4335_GCI_STRAP_OVERRIDE_SFLASH_PRESENT (1 << 24) 3376 #define CC4335_GCI_STRAP_OVERRIDE_SFLASH_TYPE 25 3377 #define CC4335_GCI_FUNC_SEL_PAD_SDIO 0x00707770 3378 3379 /* SFLASH clkdev specific bits. */ 3380 #define CC4335_SFLASH_CLKDIV_MASK 0x1F000000 3381 #define CC4335_SFLASH_CLKDIV_SHIFT 25 3382 3383 /* 4335 OTP bits for SFLASH. */ 3384 #define CC4335_SROM_OTP_SFLASH 40 3385 #define CC4335_SROM_OTP_SFLASH_PRESENT 0x1 3386 #define CC4335_SROM_OTP_SFLASH_TYPE 0x2 3387 #define CC4335_SROM_OTP_SFLASH_CLKDIV_MASK 0x003C 3388 #define CC4335_SROM_OTP_SFLASH_CLKDIV_SHIFT 2 3389 3390 /* 4335 resources--END */ 3391 3392 /* 43012 PMU resources based on pmu_params.xls - Start */ 3393 #define RES43012_MEMLPLDO_PU 0 3394 #define RES43012_PMU_SLEEP 1 3395 #define RES43012_FAST_LPO 2 3396 #define RES43012_BTLPO_3P3 3 3397 #define RES43012_SR_POK 4 3398 #define RES43012_DUMMY_PWRSW 5 3399 #define RES43012_DUMMY_LDO3P3 6 3400 #define RES43012_DUMMY_BT_LDO3P3 7 3401 #define RES43012_DUMMY_RADIO 8 3402 #define RES43012_VDDB_VDDRET 9 3403 #define RES43012_HV_LDO3P3 10 3404 #define RES43012_OTP_PU 11 3405 #define RES43012_XTAL_PU 12 3406 #define RES43012_SR_CLK_START 13 3407 #define RES43012_XTAL_STABLE 14 3408 #define RES43012_FCBS 15 3409 #define RES43012_CBUCK_MODE 16 3410 #define RES43012_WL_CORE_RDY 17 3411 #define RES43012_ILP_REQ 18 3412 #define RES43012_ALP_AVAIL 19 3413 #define RES43012_RADIO_LDO 20 3414 #define RES43012_MINI_PMU 21 3415 #define RES43012_DUMMY 22 3416 #define RES43012_SR_SAVE_RESTORE 23 3417 #define RES43012_SR_PHY_PWRSW 24 3418 #define RES43012_SR_VDDB_CLDO 25 3419 #define RES43012_SR_SUBCORE_PWRSW 26 3420 #define RES43012_SR_SLEEP 27 3421 #define RES43012_HT_START 28 3422 #define RES43012_HT_AVAIL 29 3423 #define RES43012_MACPHY_CLK_AVAIL 30 3424 #define CST43012_SPROM_PRESENT 0x00000010 3425 3426 /* PLL usage in 43012 */ 3427 #define PMU43012_PLL0_PC0_NDIV_INT_MASK 0x0000003f 3428 #define PMU43012_PLL0_PC0_NDIV_INT_SHIFT 0 3429 #define PMU43012_PLL0_PC0_NDIV_FRAC_MASK 0xfffffc00 3430 #define PMU43012_PLL0_PC0_NDIV_FRAC_SHIFT 10 3431 #define PMU43012_PLL0_PC3_PDIV_MASK 0x00003c00 3432 #define PMU43012_PLL0_PC3_PDIV_SHIFT 10 3433 #define PMU43012_PLL_NDIV_FRAC_BITS 20 3434 #define PMU43012_PLL_P_DIV_SCALE_BITS 10 3435 3436 #define CCTL_43012_ARM_OFFCOUNT_MASK 0x00000003 3437 #define CCTL_43012_ARM_OFFCOUNT_SHIFT 0 3438 #define CCTL_43012_ARM_ONCOUNT_MASK 0x0000000c 3439 #define CCTL_43012_ARM_ONCOUNT_SHIFT 2 3440 3441 /* PMU Rev >= 30 */ 3442 #define PMU30_ALPCLK_ONEMHZ_ENAB 0x80000000 3443 3444 /* 43012 PMU Chip Control Registers */ 3445 #define PMUCCTL02_43012_SUBCORE_PWRSW_FORCE_ON 0x00000010 3446 #define PMUCCTL02_43012_PHY_PWRSW_FORCE_ON 0x00000040 3447 #define PMUCCTL02_43012_LHL_TIMER_SELECT 0x00000800 3448 #define PMUCCTL02_43012_RFLDO3P3_PU_FORCE_ON 0x00008000 3449 #define PMUCCTL02_43012_WL2CDIG_I_PMU_SLEEP_ENAB 0x00010000 3450 3451 #define PMUCCTL04_43012_BBPLL_ENABLE_PWRDN 0x00100000 3452 #define PMUCCTL04_43012_BBPLL_ENABLE_PWROFF 0x00200000 3453 #define PMUCCTL04_43012_FORCE_BBPLL_ARESET 0x00400000 3454 #define PMUCCTL04_43012_FORCE_BBPLL_DRESET 0x00800000 3455 #define PMUCCTL04_43012_FORCE_BBPLL_PWRDN 0x01000000 3456 #define PMUCCTL04_43012_FORCE_BBPLL_ISOONHIGH 0x02000000 3457 #define PMUCCTL04_43012_FORCE_BBPLL_PWROFF 0x04000000 3458 #define PMUCCTL04_43012_DISABLE_LQ_AVAIL 0x08000000 3459 #define PMUCCTL04_43012_DISABLE_HT_AVAIL 0x10000000 3460 #define PMUCCTL04_43012_USE_LOCK 0x20000000 3461 #define PMUCCTL04_43012_OPEN_LOOP_ENABLE 0x40000000 3462 #define PMUCCTL04_43012_FORCE_OPEN_LOOP 0x80000000 3463 #define PMUCCTL08_43012_XTAL_CORE_SIZE_PMOS_NORMAL_MASK 0x00000FC0 3464 #define PMUCCTL08_43012_XTAL_CORE_SIZE_PMOS_NORMAL_SHIFT 6 3465 #define PMUCCTL08_43012_XTAL_CORE_SIZE_NMOS_NORMAL_MASK 0x00FC0000 3466 #define PMUCCTL08_43012_XTAL_CORE_SIZE_NMOS_NORMAL_SHIFT 18 3467 #define PMUCCTL08_43012_XTAL_SEL_BIAS_RES_NORMAL_MASK 0x07000000 3468 #define PMUCCTL08_43012_XTAL_SEL_BIAS_RES_NORMAL_SHIFT 24 3469 #define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_NORMAL_MASK 0x0003F000 3470 #define PMUCCTL09_43012_XTAL_CORESIZE_BIAS_ADJ_NORMAL_SHIFT 12 3471 #define PMUCCTL09_43012_XTAL_CORESIZE_RES_BYPASS_NORMAL_MASK 0x00000038 3472 #define PMUCCTL09_43012_XTAL_CORESIZE_RES_BYPASS_NORMAL_SHIFT 3 3473 #define PMUCCTL13_43012_FCBS_UP_TRIG_EN 0x00000400 3474 3475 #define PMUCCTL14_43012_ARMCM3_RESET_INITVAL 0x00000001 3476 #define PMUCCTL14_43012_DOT11MAC_CLKEN_INITVAL 0x00000020 3477 #define PMUCCTL14_43012_SDIOD_RESET_INIVAL 0x00000400 3478 #define PMUCCTL14_43012_SDIO_CLK_DMN_RESET_INITVAL 0x00001000 3479 #define PMUCCTL14_43012_SOCRAM_CLKEN_INITVAL 0x00004000 3480 #define PMUCCTL14_43012_M2MDMA_RESET_INITVAL 0x00008000 3481 #define PMUCCTL14_43012_DISABLE_LQ_AVAIL 0x08000000 3482 3483 3484 /* 4345 Chip specific ChipStatus register bits */ 3485 #define CST4345_SPROM_MASK 0x00000020 3486 #define CST4345_SFLASH_MASK 0x00000040 3487 #define CST4345_RES_INIT_MODE_SHIFT 7 3488 #define CST4345_RES_INIT_MODE_MASK 0x00000180 3489 #define CST4345_CHIPMODE_MASK 0x4000F 3490 #define CST4345_CHIPMODE_SDIOD(cs) (((cs) & (1 << 0)) != 0) /* SDIO */ 3491 #define CST4345_CHIPMODE_GSPI(cs) (((cs) & (1 << 1)) != 0) /* gSPI */ 3492 #define CST4345_CHIPMODE_HSIC(cs) (((cs) & (1 << 2)) != 0) /* HSIC */ 3493 #define CST4345_CHIPMODE_PCIE(cs) (((cs) & (1 << 3)) != 0) /* PCIE */ 3494 #define CST4345_CHIPMODE_USB20D(cs) (((cs) & (1 << 18)) != 0) /* USBDA */ 3495 3496 /* 4350 Chipcommon ChipStatus bits */ 3497 #define CST4350_SDIO_MODE 0x00000001 3498 #define CST4350_HSIC20D_MODE 0x00000002 3499 #define CST4350_BP_ON_HSIC_CLK 0x00000004 3500 #define CST4350_PCIE_MODE 0x00000008 3501 #define CST4350_USB20D_MODE 0x00000010 3502 #define CST4350_USB30D_MODE 0x00000020 3503 #define CST4350_SPROM_PRESENT 0x00000040 3504 #define CST4350_RSRC_INIT_MODE_0 0x00000080 3505 #define CST4350_RSRC_INIT_MODE_1 0x00000100 3506 #define CST4350_SEL0_SDIO 0x00000200 3507 #define CST4350_SEL1_SDIO 0x00000400 3508 #define CST4350_SDIO_PAD_MODE 0x00000800 3509 #define CST4350_BBPLL_LOCKED 0x00001000 3510 #define CST4350_USBPLL_LOCKED 0x00002000 3511 #define CST4350_LINE_STATE 0x0000C000 3512 #define CST4350_SERDES_PIPE_PLLLOCK 0x00010000 3513 #define CST4350_BT_READY 0x00020000 3514 #define CST4350_SFLASH_PRESENT 0x00040000 3515 #define CST4350_CPULESS_ENABLE 0x00080000 3516 #define CST4350_STRAP_HOST_IFC_1 0x00100000 3517 #define CST4350_STRAP_HOST_IFC_2 0x00200000 3518 #define CST4350_STRAP_HOST_IFC_3 0x00400000 3519 #define CST4350_RAW_SPROM_PRESENT 0x00800000 3520 #define CST4350_APP_CLK_SWITCH_SEL_RDBACK 0x01000000 3521 #define CST4350_RAW_RSRC_INIT_MODE_0 0x02000000 3522 #define CST4350_SDIO_PAD_VDDIO 0x04000000 3523 #define CST4350_GSPI_MODE 0x08000000 3524 #define CST4350_PACKAGE_OPTION 0xF0000000 3525 #define CST4350_PACKAGE_SHIFT 28 3526 3527 /* package option for 4350 */ 3528 #define CST4350_PACKAGE_WLCSP 0x0 3529 #define CST4350_PACKAGE_PCIE 0x1 3530 #define CST4350_PACKAGE_WLBGA 0x2 3531 #define CST4350_PACKAGE_DBG 0x3 3532 #define CST4350_PACKAGE_USB 0x4 3533 #define CST4350_PACKAGE_USB_HSIC 0x4 3534 3535 #define CST4350_PKG_MODE(cs) ((cs & CST4350_PACKAGE_OPTION) >> CST4350_PACKAGE_SHIFT) 3536 3537 #define CST4350_PKG_WLCSP(cs) (CST4350_PKG_MODE(cs) == (CST4350_PACKAGE_WLCSP)) 3538 #define CST4350_PKG_PCIE(cs) (CST4350_PKG_MODE(cs) == (CST4350_PACKAGE_PCIE)) 3539 #define CST4350_PKG_WLBGA(cs) (CST4350_PKG_MODE(cs) == (CST4350_PACKAGE_WLBGA)) 3540 #define CST4350_PKG_USB(cs) (CST4350_PKG_MODE(cs) == (CST4350_PACKAGE_USB)) 3541 #define CST4350_PKG_USB_HSIC(cs) (CST4350_PKG_MODE(cs) == (CST4350_PACKAGE_USB_HSIC)) 3542 3543 /* 4350C0 USB PACKAGE using raw_sprom_present to indicate 40mHz xtal */ 3544 #define CST4350_PKG_USB_40M(cs) (cs & CST4350_RAW_SPROM_PRESENT) 3545 3546 #define CST4350_CHIPMODE_SDIOD(cs) (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_SDIOD)) 3547 #define CST4350_CHIPMODE_USB20D(cs) ((CST4350_IFC_MODE(cs)) == (CST4350_IFC_MODE_USB20D)) 3548 #define CST4350_CHIPMODE_HSIC20D(cs) (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_HSIC20D)) 3549 #define CST4350_CHIPMODE_HSIC30D(cs) (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_HSIC30D)) 3550 #define CST4350_CHIPMODE_USB30D(cs) (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_USB30D)) 3551 #define CST4350_CHIPMODE_USB30D_WL(cs) (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_USB30D_WL)) 3552 #define CST4350_CHIPMODE_PCIE(cs) (CST4350_IFC_MODE(cs) == (CST4350_IFC_MODE_PCIE)) 3553 3554 /* strap_host_ifc strap value */ 3555 #define CST4350_HOST_IFC_MASK 0x00700000 3556 #define CST4350_HOST_IFC_SHIFT 20 3557 3558 /* host_ifc raw mode */ 3559 #define CST4350_IFC_MODE_SDIOD 0x0 3560 #define CST4350_IFC_MODE_HSIC20D 0x1 3561 #define CST4350_IFC_MODE_HSIC30D 0x2 3562 #define CST4350_IFC_MODE_PCIE 0x3 3563 #define CST4350_IFC_MODE_USB20D 0x4 3564 #define CST4350_IFC_MODE_USB30D 0x5 3565 #define CST4350_IFC_MODE_USB30D_WL 0x6 3566 #define CST4350_IFC_MODE_USB30D_BT 0x7 3567 3568 #define CST4350_IFC_MODE(cs) ((cs & CST4350_HOST_IFC_MASK) >> CST4350_HOST_IFC_SHIFT) 3569 3570 /* 4350 PMU resources */ 3571 #define RES4350_LPLDO_PU 0 3572 #define RES4350_PMU_BG_PU 1 3573 #define RES4350_PMU_SLEEP 2 3574 #define RES4350_RSVD_3 3 3575 #define RES4350_CBUCK_LPOM_PU 4 3576 #define RES4350_CBUCK_PFM_PU 5 3577 #define RES4350_COLD_START_WAIT 6 3578 #define RES4350_RSVD_7 7 3579 #define RES4350_LNLDO_PU 8 3580 #define RES4350_XTALLDO_PU 9 3581 #define RES4350_LDO3P3_PU 10 3582 #define RES4350_OTP_PU 11 3583 #define RES4350_XTAL_PU 12 3584 #define RES4350_SR_CLK_START 13 3585 #define RES4350_LQ_AVAIL 14 3586 #define RES4350_LQ_START 15 3587 #define RES4350_PERST_OVR 16 3588 #define RES4350_WL_CORE_RDY 17 3589 #define RES4350_ILP_REQ 18 3590 #define RES4350_ALP_AVAIL 19 3591 #define RES4350_MINI_PMU 20 3592 #define RES4350_RADIO_PU 21 3593 #define RES4350_SR_CLK_STABLE 22 3594 #define RES4350_SR_SAVE_RESTORE 23 3595 #define RES4350_SR_PHY_PWRSW 24 3596 #define RES4350_SR_VDDM_PWRSW 25 3597 #define RES4350_SR_SUBCORE_PWRSW 26 3598 #define RES4350_SR_SLEEP 27 3599 #define RES4350_HT_START 28 3600 #define RES4350_HT_AVAIL 29 3601 #define RES4350_MACPHY_CLKAVAIL 30 3602 3603 #define MUXENAB4350_UART_MASK (0x0000000f) 3604 #define MUXENAB4350_UART_SHIFT 0 3605 #define MUXENAB4350_HOSTWAKE_MASK (0x000000f0) /**< configure GPIO for host_wake */ 3606 #define MUXENAB4350_HOSTWAKE_SHIFT 4 3607 #define MUXENAB4349_UART_MASK (0xf) 3608 3609 3610 #define CC4350_GPIO_COUNT 16 3611 3612 /* 4350 GCI function sel values */ 3613 #define CC4350_FNSEL_HWDEF (0) 3614 #define CC4350_FNSEL_SAMEASPIN (1) 3615 #define CC4350_FNSEL_UART (2) 3616 #define CC4350_FNSEL_SFLASH (3) 3617 #define CC4350_FNSEL_SPROM (4) 3618 #define CC4350_FNSEL_I2C (5) 3619 #define CC4350_FNSEL_MISC0 (6) 3620 #define CC4350_FNSEL_GCI (7) 3621 #define CC4350_FNSEL_MISC1 (8) 3622 #define CC4350_FNSEL_MISC2 (9) 3623 #define CC4350_FNSEL_PWDOG (10) 3624 #define CC4350_FNSEL_IND (12) 3625 #define CC4350_FNSEL_PDN (13) 3626 #define CC4350_FNSEL_PUP (14) 3627 #define CC4350_FNSEL_TRISTATE (15) 3628 #define CC4350C_FNSEL_UART (3) 3629 3630 3631 /* 4350 GPIO */ 3632 #define CC4350_PIN_GPIO_00 (0) 3633 #define CC4350_PIN_GPIO_01 (1) 3634 #define CC4350_PIN_GPIO_02 (2) 3635 #define CC4350_PIN_GPIO_03 (3) 3636 #define CC4350_PIN_GPIO_04 (4) 3637 #define CC4350_PIN_GPIO_05 (5) 3638 #define CC4350_PIN_GPIO_06 (6) 3639 #define CC4350_PIN_GPIO_07 (7) 3640 #define CC4350_PIN_GPIO_08 (8) 3641 #define CC4350_PIN_GPIO_09 (9) 3642 #define CC4350_PIN_GPIO_10 (10) 3643 #define CC4350_PIN_GPIO_11 (11) 3644 #define CC4350_PIN_GPIO_12 (12) 3645 #define CC4350_PIN_GPIO_13 (13) 3646 #define CC4350_PIN_GPIO_14 (14) 3647 #define CC4350_PIN_GPIO_15 (15) 3648 3649 #define CC4350_RSVD_16_SHIFT 16 3650 3651 #define CC2_4350_PHY_PWRSW_UPTIME_MASK (0xf << 0) 3652 #define CC2_4350_PHY_PWRSW_UPTIME_SHIFT (0) 3653 #define CC2_4350_VDDM_PWRSW_UPDELAY_MASK (0xf << 4) 3654 #define CC2_4350_VDDM_PWRSW_UPDELAY_SHIFT (4) 3655 #define CC2_4350_VDDM_PWRSW_UPTIME_MASK (0xf << 8) 3656 #define CC2_4350_VDDM_PWRSW_UPTIME_SHIFT (8) 3657 #define CC2_4350_SBC_PWRSW_DNDELAY_MASK (0x3 << 12) 3658 #define CC2_4350_SBC_PWRSW_DNDELAY_SHIFT (12) 3659 #define CC2_4350_PHY_PWRSW_DNDELAY_MASK (0x3 << 14) 3660 #define CC2_4350_PHY_PWRSW_DNDELAY_SHIFT (14) 3661 #define CC2_4350_VDDM_PWRSW_DNDELAY_MASK (0x3 << 16) 3662 #define CC2_4350_VDDM_PWRSW_DNDELAY_SHIFT (16) 3663 #define CC2_4350_VDDM_PWRSW_EN_MASK (1 << 20) 3664 #define CC2_4350_VDDM_PWRSW_EN_SHIFT (20) 3665 #define CC2_4350_MEMLPLDO_PWRSW_EN_MASK (1 << 21) 3666 #define CC2_4350_MEMLPLDO_PWRSW_EN_SHIFT (21) 3667 #define CC2_4350_SDIO_AOS_WAKEUP_MASK (1 << 24) 3668 #define CC2_4350_SDIO_AOS_WAKEUP_SHIFT (24) 3669 3670 /* Applies to 4335/4350/4345 */ 3671 #define CC3_SR_CLK_SR_MEM_MASK (1 << 0) 3672 #define CC3_SR_CLK_SR_MEM_SHIFT (0) 3673 #define CC3_SR_BIT1_TBD_MASK (1 << 1) 3674 #define CC3_SR_BIT1_TBD_SHIFT (1) 3675 #define CC3_SR_ENGINE_ENABLE_MASK (1 << 2) 3676 #define CC3_SR_ENGINE_ENABLE_SHIFT (2) 3677 #define CC3_SR_BIT3_TBD_MASK (1 << 3) 3678 #define CC3_SR_BIT3_TBD_SHIFT (3) 3679 #define CC3_SR_MINDIV_FAST_CLK_MASK (0xF << 4) 3680 #define CC3_SR_MINDIV_FAST_CLK_SHIFT (4) 3681 #define CC3_SR_R23_SR2_RISE_EDGE_TRIG_MASK (1 << 8) 3682 #define CC3_SR_R23_SR2_RISE_EDGE_TRIG_SHIFT (8) 3683 #define CC3_SR_R23_SR2_FALL_EDGE_TRIG_MASK (1 << 9) 3684 #define CC3_SR_R23_SR2_FALL_EDGE_TRIG_SHIFT (9) 3685 #define CC3_SR_R23_SR_RISE_EDGE_TRIG_MASK (1 << 10) 3686 #define CC3_SR_R23_SR_RISE_EDGE_TRIG_SHIFT (10) 3687 #define CC3_SR_R23_SR_FALL_EDGE_TRIG_MASK (1 << 11) 3688 #define CC3_SR_R23_SR_FALL_EDGE_TRIG_SHIFT (11) 3689 #define CC3_SR_NUM_CLK_HIGH_MASK (0x7 << 12) 3690 #define CC3_SR_NUM_CLK_HIGH_SHIFT (12) 3691 #define CC3_SR_BIT15_TBD_MASK (1 << 15) 3692 #define CC3_SR_BIT15_TBD_SHIFT (15) 3693 #define CC3_SR_PHY_FUNC_PIC_MASK (1 << 16) 3694 #define CC3_SR_PHY_FUNC_PIC_SHIFT (16) 3695 #define CC3_SR_BIT17_19_TBD_MASK (0x7 << 17) 3696 #define CC3_SR_BIT17_19_TBD_SHIFT (17) 3697 #define CC3_SR_CHIP_TRIGGER_1_MASK (1 << 20) 3698 #define CC3_SR_CHIP_TRIGGER_1_SHIFT (20) 3699 #define CC3_SR_CHIP_TRIGGER_2_MASK (1 << 21) 3700 #define CC3_SR_CHIP_TRIGGER_2_SHIFT (21) 3701 #define CC3_SR_CHIP_TRIGGER_3_MASK (1 << 22) 3702 #define CC3_SR_CHIP_TRIGGER_3_SHIFT (22) 3703 #define CC3_SR_CHIP_TRIGGER_4_MASK (1 << 23) 3704 #define CC3_SR_CHIP_TRIGGER_4_SHIFT (23) 3705 #define CC3_SR_ALLOW_SBC_FUNC_PIC_MASK (1 << 24) 3706 #define CC3_SR_ALLOW_SBC_FUNC_PIC_SHIFT (24) 3707 #define CC3_SR_BIT25_26_TBD_MASK (0x3 << 25) 3708 #define CC3_SR_BIT25_26_TBD_SHIFT (25) 3709 #define CC3_SR_ALLOW_SBC_STBY_MASK (1 << 27) 3710 #define CC3_SR_ALLOW_SBC_STBY_SHIFT (27) 3711 #define CC3_SR_GPIO_MUX_MASK (0xF << 28) 3712 #define CC3_SR_GPIO_MUX_SHIFT (28) 3713 3714 /* Applies to 4335/4350/4345 */ 3715 #define CC4_SR_INIT_ADDR_MASK (0x3FF0000) 3716 #define CC4_4350_SR_ASM_ADDR (0x30) 3717 #define CC4_4350_C0_SR_ASM_ADDR (0x0) 3718 #define CC4_4335_SR_ASM_ADDR (0x48) 3719 #define CC4_4345_SR_ASM_ADDR (0x48) 3720 #define CC4_SR_INIT_ADDR_SHIFT (16) 3721 3722 #define CC4_4350_EN_SR_CLK_ALP_MASK (1 << 30) 3723 #define CC4_4350_EN_SR_CLK_ALP_SHIFT (30) 3724 #define CC4_4350_EN_SR_CLK_HT_MASK (1 << 31) 3725 #define CC4_4350_EN_SR_CLK_HT_SHIFT (31) 3726 3727 #define VREG4_4350_MEMLPDO_PU_MASK (1 << 31) 3728 #define VREG4_4350_MEMLPDO_PU_SHIFT 31 3729 3730 #define VREG6_4350_SR_EXT_CLKDIR_MASK (1 << 20) 3731 #define VREG6_4350_SR_EXT_CLKDIR_SHIFT 20 3732 #define VREG6_4350_SR_EXT_CLKDIV_MASK (0x3 << 21) 3733 #define VREG6_4350_SR_EXT_CLKDIV_SHIFT 21 3734 #define VREG6_4350_SR_EXT_CLKEN_MASK (1 << 23) 3735 #define VREG6_4350_SR_EXT_CLKEN_SHIFT 23 3736 3737 #define CC5_4350_PMU_EN_ASSERT_MASK (1 << 13) 3738 #define CC5_4350_PMU_EN_ASSERT_SHIFT (13) 3739 3740 #define CC6_4350_PCIE_CLKREQ_WAKEUP_MASK (1 << 4) 3741 #define CC6_4350_PCIE_CLKREQ_WAKEUP_SHIFT (4) 3742 #define CC6_4350_PMU_WAKEUP_ALPAVAIL_MASK (1 << 6) 3743 #define CC6_4350_PMU_WAKEUP_ALPAVAIL_SHIFT (6) 3744 #define CC6_4350_PMU_EN_EXT_PERST_MASK (1 << 17) 3745 #define CC6_4350_PMU_EN_EXT_PERST_SHIFT (17) 3746 #define CC6_4350_PMU_EN_WAKEUP_MASK (1 << 18) 3747 #define CC6_4350_PMU_EN_WAKEUP_SHIFT (18) 3748 3749 #define CC7_4350_PMU_EN_ASSERT_L2_MASK (1 << 26) 3750 #define CC7_4350_PMU_EN_ASSERT_L2_SHIFT (26) 3751 #define CC7_4350_PMU_EN_MDIO_MASK (1 << 27) 3752 #define CC7_4350_PMU_EN_MDIO_SHIFT (27) 3753 3754 #define CC6_4345_PMU_EN_PERST_DEASSERT_MASK (1 << 13) 3755 #define CC6_4345_PMU_EN_PERST_DEASSERT_SHIF (13) 3756 #define CC6_4345_PMU_EN_L2_DEASSERT_MASK (1 << 14) 3757 #define CC6_4345_PMU_EN_L2_DEASSERT_SHIF (14) 3758 #define CC6_4345_PMU_EN_ASSERT_L2_MASK (1 << 15) 3759 #define CC6_4345_PMU_EN_ASSERT_L2_SHIFT (15) 3760 #define CC6_4345_PMU_EN_MDIO_MASK (1 << 24) 3761 #define CC6_4345_PMU_EN_MDIO_SHIFT (24) 3762 3763 /* GCI chipcontrol register indices */ 3764 #define CC_GCI_CHIPCTRL_00 (0) 3765 #define CC_GCI_CHIPCTRL_01 (1) 3766 #define CC_GCI_CHIPCTRL_02 (2) 3767 #define CC_GCI_CHIPCTRL_03 (3) 3768 #define CC_GCI_CHIPCTRL_04 (4) 3769 #define CC_GCI_CHIPCTRL_05 (5) 3770 #define CC_GCI_CHIPCTRL_06 (6) 3771 #define CC_GCI_CHIPCTRL_07 (7) 3772 #define CC_GCI_CHIPCTRL_08 (8) 3773 #define CC_GCI_CHIPCTRL_09 (9) 3774 #define CC_GCI_CHIPCTRL_10 (10) 3775 #define CC_GCI_CHIPCTRL_10 (10) 3776 #define CC_GCI_CHIPCTRL_11 (11) 3777 #define CC_GCI_XTAL_BUFSTRG_NFC (0xff << 12) 3778 3779 #define CC_GCI_06_JTAG_SEL_SHIFT 4 3780 #define CC_GCI_06_JTAG_SEL_MASK (1 << 4) 3781 3782 #define CC_GCI_NUMCHIPCTRLREGS(cap1) ((cap1 & 0xF00) >> 8) 3783 3784 /* GCI chipstatus register indices */ 3785 #define GCI_CHIPSTATUS_00 (0) 3786 #define GCI_CHIPSTATUS_01 (1) 3787 #define GCI_CHIPSTATUS_02 (2) 3788 #define GCI_CHIPSTATUS_03 (3) 3789 #define GCI_CHIPSTATUS_04 (4) 3790 #define GCI_CHIPSTATUS_05 (5) 3791 #define GCI_CHIPSTATUS_06 (6) 3792 #define GCI_CHIPSTATUS_07 (7) 3793 #define GCI_CHIPSTATUS_08 (8) 3794 3795 /* 43021 GCI chipstatus registers */ 3796 #define GCI43012_CHIPSTATUS_07_BBPLL_LOCK_MASK (1 << 3) 3797 3798 /* 4345 PMU resources */ 3799 #define RES4345_LPLDO_PU 0 3800 #define RES4345_PMU_BG_PU 1 3801 #define RES4345_PMU_SLEEP 2 3802 #define RES4345_HSICLDO_PU 3 3803 #define RES4345_CBUCK_LPOM_PU 4 3804 #define RES4345_CBUCK_PFM_PU 5 3805 #define RES4345_COLD_START_WAIT 6 3806 #define RES4345_RSVD_7 7 3807 #define RES4345_LNLDO_PU 8 3808 #define RES4345_XTALLDO_PU 9 3809 #define RES4345_LDO3P3_PU 10 3810 #define RES4345_OTP_PU 11 3811 #define RES4345_XTAL_PU 12 3812 #define RES4345_SR_CLK_START 13 3813 #define RES4345_LQ_AVAIL 14 3814 #define RES4345_LQ_START 15 3815 #define RES4345_PERST_OVR 16 3816 #define RES4345_WL_CORE_RDY 17 3817 #define RES4345_ILP_REQ 18 3818 #define RES4345_ALP_AVAIL 19 3819 #define RES4345_MINI_PMU 20 3820 #define RES4345_RADIO_PU 21 3821 #define RES4345_SR_CLK_STABLE 22 3822 #define RES4345_SR_SAVE_RESTORE 23 3823 #define RES4345_SR_PHY_PWRSW 24 3824 #define RES4345_SR_VDDM_PWRSW 25 3825 #define RES4345_SR_SUBCORE_PWRSW 26 3826 #define RES4345_SR_SLEEP 27 3827 #define RES4345_HT_START 28 3828 #define RES4345_HT_AVAIL 29 3829 #define RES4345_MACPHY_CLK_AVAIL 30 3830 3831 /* 43012 pins 3832 * note: only the values set as default/used are added here. 3833 */ 3834 #define CC43012_PIN_GPIO_00 (0) 3835 #define CC43012_PIN_GPIO_01 (1) 3836 #define CC43012_PIN_GPIO_02 (2) 3837 #define CC43012_PIN_GPIO_03 (3) 3838 #define CC43012_PIN_GPIO_04 (4) 3839 #define CC43012_PIN_GPIO_05 (5) 3840 #define CC43012_PIN_GPIO_06 (6) 3841 #define CC43012_PIN_GPIO_07 (7) 3842 #define CC43012_PIN_GPIO_08 (8) 3843 #define CC43012_PIN_GPIO_09 (9) 3844 #define CC43012_PIN_GPIO_10 (10) 3845 #define CC43012_PIN_GPIO_11 (11) 3846 #define CC43012_PIN_GPIO_12 (12) 3847 #define CC43012_PIN_GPIO_13 (13) 3848 #define CC43012_PIN_GPIO_14 (14) 3849 #define CC43012_PIN_GPIO_15 (15) 3850 3851 /* 43012 GCI function sel values */ 3852 #define CC43012_FNSEL_HWDEF (0) 3853 #define CC43012_FNSEL_SAMEASPIN (1) 3854 #define CC43012_FNSEL_GPIO0 (2) 3855 #define CC43012_FNSEL_GPIO1 (3) 3856 #define CC43012_FNSEL_GCI0 (4) 3857 #define CC43012_FNSEL_GCI1 (5) 3858 #define CC43012_FNSEL_DBG_UART (6) 3859 #define CC43012_FNSEL_I2C (7) 3860 #define CC43012_FNSEL_BT_SFLASH (8) 3861 #define CC43012_FNSEL_MISC0 (9) 3862 #define CC43012_FNSEL_MISC1 (10) 3863 #define CC43012_FNSEL_MISC2 (11) 3864 #define CC43012_FNSEL_IND (12) 3865 #define CC43012_FNSEL_PDN (13) 3866 #define CC43012_FNSEL_PUP (14) 3867 #define CC43012_FNSEL_TRI (15) 3868 3869 /* 4335 pins 3870 * note: only the values set as default/used are added here. 3871 */ 3872 #define CC4335_PIN_GPIO_00 (0) 3873 #define CC4335_PIN_GPIO_01 (1) 3874 #define CC4335_PIN_GPIO_02 (2) 3875 #define CC4335_PIN_GPIO_03 (3) 3876 #define CC4335_PIN_GPIO_04 (4) 3877 #define CC4335_PIN_GPIO_05 (5) 3878 #define CC4335_PIN_GPIO_06 (6) 3879 #define CC4335_PIN_GPIO_07 (7) 3880 #define CC4335_PIN_GPIO_08 (8) 3881 #define CC4335_PIN_GPIO_09 (9) 3882 #define CC4335_PIN_GPIO_10 (10) 3883 #define CC4335_PIN_GPIO_11 (11) 3884 #define CC4335_PIN_GPIO_12 (12) 3885 #define CC4335_PIN_GPIO_13 (13) 3886 #define CC4335_PIN_GPIO_14 (14) 3887 #define CC4335_PIN_GPIO_15 (15) 3888 #define CC4335_PIN_SDIO_CLK (16) 3889 #define CC4335_PIN_SDIO_CMD (17) 3890 #define CC4335_PIN_SDIO_DATA0 (18) 3891 #define CC4335_PIN_SDIO_DATA1 (19) 3892 #define CC4335_PIN_SDIO_DATA2 (20) 3893 #define CC4335_PIN_SDIO_DATA3 (21) 3894 #define CC4335_PIN_RF_SW_CTRL_6 (22) 3895 #define CC4335_PIN_RF_SW_CTRL_7 (23) 3896 #define CC4335_PIN_RF_SW_CTRL_8 (24) 3897 #define CC4335_PIN_RF_SW_CTRL_9 (25) 3898 /* Last GPIO Pad */ 3899 #define CC4335_PIN_GPIO_LAST (31) 3900 3901 /* 4335 GCI function sel values 3902 */ 3903 #define CC4335_FNSEL_HWDEF (0) 3904 #define CC4335_FNSEL_SAMEASPIN (1) 3905 #define CC4335_FNSEL_GPIO0 (2) 3906 #define CC4335_FNSEL_GPIO1 (3) 3907 #define CC4335_FNSEL_GCI0 (4) 3908 #define CC4335_FNSEL_GCI1 (5) 3909 #define CC4335_FNSEL_UART (6) 3910 #define CC4335_FNSEL_SFLASH (7) 3911 #define CC4335_FNSEL_SPROM (8) 3912 #define CC4335_FNSEL_MISC0 (9) 3913 #define CC4335_FNSEL_MISC1 (10) 3914 #define CC4335_FNSEL_MISC2 (11) 3915 #define CC4335_FNSEL_IND (12) 3916 #define CC4335_FNSEL_PDN (13) 3917 #define CC4335_FNSEL_PUP (14) 3918 #define CC4335_FNSEL_TRI (15) 3919 3920 /* GCI Core Control Reg */ 3921 #define GCI_CORECTRL_SR_MASK (1 << 0) /**< SECI block Reset */ 3922 #define GCI_CORECTRL_RSL_MASK (1 << 1) /**< ResetSECILogic */ 3923 #define GCI_CORECTRL_ES_MASK (1 << 2) /**< EnableSECI */ 3924 #define GCI_CORECTRL_FSL_MASK (1 << 3) /**< Force SECI Out Low */ 3925 #define GCI_CORECTRL_SOM_MASK (7 << 4) /**< SECI Op Mode */ 3926 #define GCI_CORECTRL_US_MASK (1 << 7) /**< Update SECI */ 3927 #define GCI_CORECTRL_BOS_MASK (1 << 8) /**< Break On Sleep */ 3928 3929 /* 4345 pins 3930 * note: only the values set as default/used are added here. 3931 */ 3932 #define CC4345_PIN_GPIO_00 (0) 3933 #define CC4345_PIN_GPIO_01 (1) 3934 #define CC4345_PIN_GPIO_02 (2) 3935 #define CC4345_PIN_GPIO_03 (3) 3936 #define CC4345_PIN_GPIO_04 (4) 3937 #define CC4345_PIN_GPIO_05 (5) 3938 #define CC4345_PIN_GPIO_06 (6) 3939 #define CC4345_PIN_GPIO_07 (7) 3940 #define CC4345_PIN_GPIO_08 (8) 3941 #define CC4345_PIN_GPIO_09 (9) 3942 #define CC4345_PIN_GPIO_10 (10) 3943 #define CC4345_PIN_GPIO_11 (11) 3944 #define CC4345_PIN_GPIO_12 (12) 3945 #define CC4345_PIN_GPIO_13 (13) 3946 #define CC4345_PIN_GPIO_14 (14) 3947 #define CC4345_PIN_GPIO_15 (15) 3948 #define CC4345_PIN_GPIO_16 (16) 3949 #define CC4345_PIN_SDIO_CLK (17) 3950 #define CC4345_PIN_SDIO_CMD (18) 3951 #define CC4345_PIN_SDIO_DATA0 (19) 3952 #define CC4345_PIN_SDIO_DATA1 (20) 3953 #define CC4345_PIN_SDIO_DATA2 (21) 3954 #define CC4345_PIN_SDIO_DATA3 (22) 3955 #define CC4345_PIN_RF_SW_CTRL_0 (23) 3956 #define CC4345_PIN_RF_SW_CTRL_1 (24) 3957 #define CC4345_PIN_RF_SW_CTRL_2 (25) 3958 #define CC4345_PIN_RF_SW_CTRL_3 (26) 3959 #define CC4345_PIN_RF_SW_CTRL_4 (27) 3960 #define CC4345_PIN_RF_SW_CTRL_5 (28) 3961 #define CC4345_PIN_RF_SW_CTRL_6 (29) 3962 #define CC4345_PIN_RF_SW_CTRL_7 (30) 3963 #define CC4345_PIN_RF_SW_CTRL_8 (31) 3964 #define CC4345_PIN_RF_SW_CTRL_9 (32) 3965 3966 /* 4345 GCI function sel values 3967 */ 3968 #define CC4345_FNSEL_HWDEF (0) 3969 #define CC4345_FNSEL_SAMEASPIN (1) 3970 #define CC4345_FNSEL_GPIO0 (2) 3971 #define CC4345_FNSEL_GPIO1 (3) 3972 #define CC4345_FNSEL_GCI0 (4) 3973 #define CC4345_FNSEL_GCI1 (5) 3974 #define CC4345_FNSEL_UART (6) 3975 #define CC4345_FNSEL_SFLASH (7) 3976 #define CC4345_FNSEL_SPROM (8) 3977 #define CC4345_FNSEL_MISC0 (9) 3978 #define CC4345_FNSEL_MISC1 (10) 3979 #define CC4345_FNSEL_MISC2 (11) 3980 #define CC4345_FNSEL_IND (12) 3981 #define CC4345_FNSEL_PDN (13) 3982 #define CC4345_FNSEL_PUP (14) 3983 #define CC4345_FNSEL_TRI (15) 3984 3985 #define MUXENAB4345_UART_MASK (0x0000000f) 3986 #define MUXENAB4345_UART_SHIFT 0 3987 #define MUXENAB4345_HOSTWAKE_MASK (0x000000f0) 3988 #define MUXENAB4345_HOSTWAKE_SHIFT 4 3989 3990 /* 4349 Group (4349, 4355, 4359) GCI AVS function sel values */ 3991 #define CC4349_GRP_GCI_AVS_CTRL_MASK (0xffe00000) 3992 #define CC4349_GRP_GCI_AVS_CTRL_SHIFT (21) 3993 #define CC4349_GRP_GCI_AVS_CTRL_ENAB (1 << 5) 3994 3995 /* 4345 GCI AVS function sel values */ 3996 #define CC4345_GCI_AVS_CTRL_MASK (0xfc) 3997 #define CC4345_GCI_AVS_CTRL_SHIFT (2) 3998 #define CC4345_GCI_AVS_CTRL_ENAB (1 << 5) 3999 4000 /* 43430 Pin */ 4001 #define CC43430_PIN_GPIO_00 (0) 4002 #define CC43430_PIN_GPIO_01 (1) 4003 #define CC43430_PIN_GPIO_02 (2) 4004 #define CC43430_PIN_GPIO_07 (7) 4005 #define CC43430_PIN_GPIO_08 (8) 4006 #define CC43430_PIN_GPIO_09 (9) 4007 #define CC43430_PIN_GPIO_10 (10) 4008 4009 #define CC43430_FNSEL_SDIO_INT (2) 4010 #define CC43430_FNSEL_6_FAST_UART (6) 4011 #define CC43430_FNSEL_10_FAST_UART (10) 4012 4013 #define MUXENAB43430_UART_MASK (0x0000000f) 4014 #define MUXENAB43430_UART_SHIFT 0 4015 #define MUXENAB43430_HOSTWAKE_MASK (0x000000f0) /* configure GPIO for SDIO host_wake */ 4016 #define MUXENAB43430_HOSTWAKE_SHIFT 4 4017 4018 #define CC43430_FNSEL_SAMEASPIN (1) 4019 #define CC43430_RFSWCTRL_EN_MASK (0x7f8) 4020 #define CC43430_RFSWCTRL_EN_SHIFT (3) 4021 4022 /* GCI GPIO for function sel GCI-0/GCI-1 */ 4023 #define CC_GCI_GPIO_0 (0) 4024 #define CC_GCI_GPIO_1 (1) 4025 #define CC_GCI_GPIO_2 (2) 4026 #define CC_GCI_GPIO_3 (3) 4027 #define CC_GCI_GPIO_4 (4) 4028 #define CC_GCI_GPIO_5 (5) 4029 #define CC_GCI_GPIO_6 (6) 4030 #define CC_GCI_GPIO_7 (7) 4031 #define CC_GCI_GPIO_8 (8) 4032 #define CC_GCI_GPIO_9 (9) 4033 #define CC_GCI_GPIO_10 (10) 4034 #define CC_GCI_GPIO_11 (11) 4035 #define CC_GCI_GPIO_12 (12) 4036 #define CC_GCI_GPIO_13 (13) 4037 #define CC_GCI_GPIO_14 (14) 4038 #define CC_GCI_GPIO_15 (15) 4039 4040 4041 /* indicates Invalid GPIO, e.g. when PAD GPIO doesn't map to GCI GPIO */ 4042 #define CC_GCI_GPIO_INVALID 0xFF 4043 4044 /* find the 4 bit mask given the bit position */ 4045 #define GCIMASK(pos) (((uint32)0xF) << pos) 4046 /* get the value which can be used to directly OR with chipcontrol reg */ 4047 #define GCIPOSVAL(val, pos) ((((uint32)val) << pos) & GCIMASK(pos)) 4048 /* Extract nibble from a given position */ 4049 #define GCIGETNBL(val, pos) ((val >> pos) & 0xF) 4050 4051 4052 /* find the 8 bit mask given the bit position */ 4053 #define GCIMASK_8B(pos) (((uint32)0xFF) << pos) 4054 /* get the value which can be used to directly OR with chipcontrol reg */ 4055 #define GCIPOSVAL_8B(val, pos) ((((uint32)val) << pos) & GCIMASK_8B(pos)) 4056 /* Extract nibble from a given position */ 4057 #define GCIGETNBL_8B(val, pos) ((val >> pos) & 0xFF) 4058 4059 /* find the 4 bit mask given the bit position */ 4060 #define GCIMASK_4B(pos) (((uint32)0xF) << pos) 4061 /* get the value which can be used to directly OR with chipcontrol reg */ 4062 #define GCIPOSVAL_4B(val, pos) ((((uint32)val) << pos) & GCIMASK_4B(pos)) 4063 /* Extract nibble from a given position */ 4064 #define GCIGETNBL_4B(val, pos) ((val >> pos) & 0xF) 4065 4066 4067 /* 4335 GCI Intstatus(Mask)/WakeMask Register bits. */ 4068 #define GCI_INTSTATUS_RBI (1 << 0) /**< Rx Break Interrupt */ 4069 #define GCI_INTSTATUS_UB (1 << 1) /**< UART Break Interrupt */ 4070 #define GCI_INTSTATUS_SPE (1 << 2) /**< SECI Parity Error Interrupt */ 4071 #define GCI_INTSTATUS_SFE (1 << 3) /**< SECI Framing Error Interrupt */ 4072 #define GCI_INTSTATUS_SRITI (1 << 9) /**< SECI Rx Idle Timer Interrupt */ 4073 #define GCI_INTSTATUS_STFF (1 << 10) /**< SECI Tx FIFO Full Interrupt */ 4074 #define GCI_INTSTATUS_STFAE (1 << 11) /**< SECI Tx FIFO Almost Empty Intr */ 4075 #define GCI_INTSTATUS_SRFAF (1 << 12) /**< SECI Rx FIFO Almost Full */ 4076 #define GCI_INTSTATUS_SRFNE (1 << 14) /**< SECI Rx FIFO Not Empty */ 4077 #define GCI_INTSTATUS_SRFOF (1 << 15) /**< SECI Rx FIFO Not Empty Timeout */ 4078 #define GCI_INTSTATUS_GPIOINT (1 << 25) /**< GCIGpioInt */ 4079 #define GCI_INTSTATUS_GPIOWAKE (1 << 26) /**< GCIGpioWake */ 4080 4081 /* 4335 GCI IntMask Register bits. */ 4082 #define GCI_INTMASK_RBI (1 << 0) /**< Rx Break Interrupt */ 4083 #define GCI_INTMASK_UB (1 << 1) /**< UART Break Interrupt */ 4084 #define GCI_INTMASK_SPE (1 << 2) /**< SECI Parity Error Interrupt */ 4085 #define GCI_INTMASK_SFE (1 << 3) /**< SECI Framing Error Interrupt */ 4086 #define GCI_INTMASK_SRITI (1 << 9) /**< SECI Rx Idle Timer Interrupt */ 4087 #define GCI_INTMASK_STFF (1 << 10) /**< SECI Tx FIFO Full Interrupt */ 4088 #define GCI_INTMASK_STFAE (1 << 11) /**< SECI Tx FIFO Almost Empty Intr */ 4089 #define GCI_INTMASK_SRFAF (1 << 12) /**< SECI Rx FIFO Almost Full */ 4090 #define GCI_INTMASK_SRFNE (1 << 14) /**< SECI Rx FIFO Not Empty */ 4091 #define GCI_INTMASK_SRFOF (1 << 15) /**< SECI Rx FIFO Not Empty Timeout */ 4092 #define GCI_INTMASK_GPIOINT (1 << 25) /**< GCIGpioInt */ 4093 #define GCI_INTMASK_GPIOWAKE (1 << 26) /**< GCIGpioWake */ 4094 4095 /* 4335 GCI WakeMask Register bits. */ 4096 #define GCI_WAKEMASK_RBI (1 << 0) /**< Rx Break Interrupt */ 4097 #define GCI_WAKEMASK_UB (1 << 1) /**< UART Break Interrupt */ 4098 #define GCI_WAKEMASK_SPE (1 << 2) /**< SECI Parity Error Interrupt */ 4099 #define GCI_WAKEMASK_SFE (1 << 3) /**< SECI Framing Error Interrupt */ 4100 #define GCI_WAKE_SRITI (1 << 9) /**< SECI Rx Idle Timer Interrupt */ 4101 #define GCI_WAKEMASK_STFF (1 << 10) /**< SECI Tx FIFO Full Interrupt */ 4102 #define GCI_WAKEMASK_STFAE (1 << 11) /**< SECI Tx FIFO Almost Empty Intr */ 4103 #define GCI_WAKEMASK_SRFAF (1 << 12) /**< SECI Rx FIFO Almost Full */ 4104 #define GCI_WAKEMASK_SRFNE (1 << 14) /**< SECI Rx FIFO Not Empty */ 4105 #define GCI_WAKEMASK_SRFOF (1 << 15) /**< SECI Rx FIFO Not Empty Timeout */ 4106 #define GCI_WAKEMASK_GPIOINT (1 << 25) /**< GCIGpioInt */ 4107 #define GCI_WAKEMASK_GPIOWAKE (1 << 26) /**< GCIGpioWake */ 4108 4109 #define GCI_WAKE_ON_GCI_GPIO1 1 4110 #define GCI_WAKE_ON_GCI_GPIO2 2 4111 #define GCI_WAKE_ON_GCI_GPIO3 3 4112 #define GCI_WAKE_ON_GCI_GPIO4 4 4113 #define GCI_WAKE_ON_GCI_GPIO5 5 4114 #define GCI_WAKE_ON_GCI_GPIO6 6 4115 #define GCI_WAKE_ON_GCI_GPIO7 7 4116 #define GCI_WAKE_ON_GCI_GPIO8 8 4117 #define GCI_WAKE_ON_GCI_SECI_IN 9 4118 4119 /* 43012 ULB dividers */ 4120 #define PMU43012_CC0_ULB_DIVMASK 0xfffffc00 4121 #define PMU43012_10MHZ_ULB_DIV ((1 << 0) | (1 << 5)) 4122 #define PMU43012_5MHZ_ULB_DIV ((3 << 0) | (3 << 5)) 4123 #define PMU43012_2P5MHZ_ULB_DIV ((7 << 0) | (7 << 5)) 4124 #define PMU43012_ULB_NO_DIV 0 4125 4126 /* 4335 MUX options. each nibble belongs to a setting. Non-zero value specifies a logic 4127 * for now only UART for bootloader. 4128 */ 4129 #define MUXENAB4335_UART_MASK (0x0000000f) 4130 4131 #define MUXENAB4335_UART_SHIFT 0 4132 #define MUXENAB4335_HOSTWAKE_MASK (0x000000f0) /**< configure GPIO for SDIO host_wake */ 4133 #define MUXENAB4335_HOSTWAKE_SHIFT 4 4134 #define MUXENAB4335_GETIX(val, name) \ 4135 ((((val) & MUXENAB4335_ ## name ## _MASK) >> MUXENAB4335_ ## name ## _SHIFT) - 1) 4136 4137 /* 43012 MUX options */ 4138 #define MUXENAB43012_HOSTWAKE_MASK (0x00000001) 4139 #define MUXENAB43012_GETIX(val, name) (val - 1) 4140 4141 /* 4142 * Maximum delay for the PMU state transition in us. 4143 * This is an upper bound intended for spinwaits etc. 4144 */ 4145 #define PMU_MAX_TRANSITION_DLY 15000 4146 4147 /* PMU resource up transition time in ILP cycles */ 4148 #define PMURES_UP_TRANSITION 2 4149 4150 /* 53573 PMU Resource */ 4151 #define RES53573_REGULATOR_PU 0 4152 #define RES53573_XTALLDO_PU 1 4153 #define RES53573_XTAL_PU 2 4154 #define RES53573_MINI_PMU 3 4155 #define RES53573_RADIO_PU 4 4156 #define RES53573_ILP_REQ 5 4157 #define RES53573_ALP_AVAIL 6 4158 #define RES53573_CPUPLL_LDO_PU 7 4159 #define RES53573_CPU_PLL_PU 8 4160 #define RES53573_WLAN_BB_PLL_PU 9 4161 #define RES53573_MISCPLL_LDO_PU 10 4162 #define RES53573_MISCPLL_PU 11 4163 #define RES53573_AUDIOPLL_PU 12 4164 #define RES53573_PCIEPLL_LDO_PU 13 4165 #define RES53573_PCIEPLL_PU 14 4166 #define RES53573_DDRPLL_LDO_PU 15 4167 #define RES53573_DDRPLL_PU 16 4168 #define RES53573_HT_AVAIL 17 4169 #define RES53573_MACPHY_CLK_AVAIL 18 4170 #define RES53573_OTP_PU 19 4171 #define RES53573_RSVD20 20 4172 4173 /* 53573 Chip status registers */ 4174 #define CST53573_LOCK_CPUPLL 0x00000001 4175 #define CST53573_LOCK_MISCPLL 0x00000002 4176 #define CST53573_LOCK_DDRPLL 0x00000004 4177 #define CST53573_LOCK_PCIEPLL 0x00000008 4178 #define CST53573_EPHY_ENERGY_DET 0x00001f00 4179 #define CST53573_RAW_ENERGY 0x0003e000 4180 #define CST53573_BBPLL_LOCKED_O 0x00040000 4181 #define CST53573_SERDES_PIPE_PLLLOCK 0x00080000 4182 #define CST53573_STRAP_PCIE_EP_MODE 0x00100000 4183 #define CST53573_EPHY_PLL_LOCK 0x00200000 4184 #define CST53573_AUDIO_PLL_LOCKED_O 0x00400000 4185 #define CST53573_PCIE_LINK_IN_L11 0x01000000 4186 #define CST53573_PCIE_LINK_IN_L12 0x02000000 4187 #define CST53573_DIN_PACKAGEOPTION 0xf0000000 4188 4189 /* 53573 Chip control registers macro definitions */ 4190 #define PMU_53573_CHIPCTL1 1 4191 #define PMU_53573_CC1_HT_CLK_REQ_CTRL_MASK 0x00000010 4192 #define PMU_53573_CC1_HT_CLK_REQ_CTRL 0x00000010 4193 4194 #define PMU_53573_CHIPCTL3 3 4195 #define PMU_53573_CC3_ENABLE_CLOSED_LOOP_MASK 0x00000010 4196 #define PMU_53573_CC3_ENABLE_CLOSED_LOOP 0x00000000 4197 #define PMU_53573_CC3_ENABLE_BBPLL_PWRDOWN_MASK 0x00000002 4198 #define PMU_53573_CC3_ENABLE_BBPLL_PWRDOWN 0x00000002 4199 4200 #define CST53573_CHIPMODE_PCIE(cs) FALSE 4201 4202 4203 /* SECI Status (0x134) & Mask (0x138) bits - Rev 35 */ 4204 #define SECI_STAT_BI (1 << 0) /* Break Interrupt */ 4205 #define SECI_STAT_SPE (1 << 1) /* Parity Error */ 4206 #define SECI_STAT_SFE (1 << 2) /* Parity Error */ 4207 #define SECI_STAT_SDU (1 << 3) /* Data Updated */ 4208 #define SECI_STAT_SADU (1 << 4) /* Auxiliary Data Updated */ 4209 #define SECI_STAT_SAS (1 << 6) /* AUX State */ 4210 #define SECI_STAT_SAS2 (1 << 7) /* AUX2 State */ 4211 #define SECI_STAT_SRITI (1 << 8) /* Idle Timer Interrupt */ 4212 #define SECI_STAT_STFF (1 << 9) /* Tx FIFO Full */ 4213 #define SECI_STAT_STFAE (1 << 10) /* Tx FIFO Almost Empty */ 4214 #define SECI_STAT_SRFE (1 << 11) /* Rx FIFO Empty */ 4215 #define SECI_STAT_SRFAF (1 << 12) /* Rx FIFO Almost Full */ 4216 #define SECI_STAT_SFCE (1 << 13) /* Flow Control Event */ 4217 4218 /* SECI configuration */ 4219 #define SECI_MODE_UART 0x0 4220 #define SECI_MODE_SECI 0x1 4221 #define SECI_MODE_LEGACY_3WIRE_BT 0x2 4222 #define SECI_MODE_LEGACY_3WIRE_WLAN 0x3 4223 #define SECI_MODE_HALF_SECI 0x4 4224 4225 #define SECI_RESET (1 << 0) 4226 #define SECI_RESET_BAR_UART (1 << 1) 4227 #define SECI_ENAB_SECI_ECI (1 << 2) 4228 #define SECI_ENAB_SECIOUT_DIS (1 << 3) 4229 #define SECI_MODE_MASK 0x7 4230 #define SECI_MODE_SHIFT 4 /* (bits 5, 6, 7) */ 4231 #define SECI_UPD_SECI (1 << 7) 4232 4233 #define SECI_SLIP_ESC_CHAR 0xDB 4234 #define SECI_SIGNOFF_0 SECI_SLIP_ESC_CHAR 4235 #define SECI_SIGNOFF_1 0 4236 #define SECI_REFRESH_REQ 0xDA 4237 4238 /* seci clk_ctl_st bits */ 4239 #define CLKCTL_STS_HT_AVAIL_REQ (1 << 4) 4240 #define CLKCTL_STS_SECI_CLK_REQ (1 << 8) 4241 #define CLKCTL_STS_SECI_CLK_AVAIL (1 << 24) 4242 4243 #define SECI_UART_MSR_CTS_STATE (1 << 0) 4244 #define SECI_UART_MSR_RTS_STATE (1 << 1) 4245 #define SECI_UART_SECI_IN_STATE (1 << 2) 4246 #define SECI_UART_SECI_IN2_STATE (1 << 3) 4247 4248 /* GCI RX FIFO Control Register */ 4249 #define GCI_RXF_LVL_MASK (0xFF << 0) 4250 #define GCI_RXF_TIMEOUT_MASK (0xFF << 8) 4251 4252 /* GCI UART Registers' Bit definitions */ 4253 /* Seci Fifo Level Register */ 4254 #define SECI_TXF_LVL_MASK (0x3F << 8) 4255 #define TXF_AE_LVL_DEFAULT 0x4 4256 #define SECI_RXF_LVL_FC_MASK (0x3F << 16) 4257 4258 /* SeciUARTFCR Bit definitions */ 4259 #define SECI_UART_FCR_RFR (1 << 0) 4260 #define SECI_UART_FCR_TFR (1 << 1) 4261 #define SECI_UART_FCR_SR (1 << 2) 4262 #define SECI_UART_FCR_THP (1 << 3) 4263 #define SECI_UART_FCR_AB (1 << 4) 4264 #define SECI_UART_FCR_ATOE (1 << 5) 4265 #define SECI_UART_FCR_ARTSOE (1 << 6) 4266 #define SECI_UART_FCR_ABV (1 << 7) 4267 #define SECI_UART_FCR_ALM (1 << 8) 4268 4269 /* SECI UART LCR register bits */ 4270 #define SECI_UART_LCR_STOP_BITS (1 << 0) /* 0 - 1bit, 1 - 2bits */ 4271 #define SECI_UART_LCR_PARITY_EN (1 << 1) 4272 #define SECI_UART_LCR_PARITY (1 << 2) /* 0 - odd, 1 - even */ 4273 #define SECI_UART_LCR_RX_EN (1 << 3) 4274 #define SECI_UART_LCR_LBRK_CTRL (1 << 4) /* 1 => SECI_OUT held low */ 4275 #define SECI_UART_LCR_TXO_EN (1 << 5) 4276 #define SECI_UART_LCR_RTSO_EN (1 << 6) 4277 #define SECI_UART_LCR_SLIPMODE_EN (1 << 7) 4278 #define SECI_UART_LCR_RXCRC_CHK (1 << 8) 4279 #define SECI_UART_LCR_TXCRC_INV (1 << 9) 4280 #define SECI_UART_LCR_TXCRC_LSBF (1 << 10) 4281 #define SECI_UART_LCR_TXCRC_EN (1 << 11) 4282 #define SECI_UART_LCR_RXSYNC_EN (1 << 12) 4283 4284 #define SECI_UART_MCR_TX_EN (1 << 0) 4285 #define SECI_UART_MCR_PRTS (1 << 1) 4286 #define SECI_UART_MCR_SWFLCTRL_EN (1 << 2) 4287 #define SECI_UART_MCR_HIGHRATE_EN (1 << 3) 4288 #define SECI_UART_MCR_LOOPBK_EN (1 << 4) 4289 #define SECI_UART_MCR_AUTO_RTS (1 << 5) 4290 #define SECI_UART_MCR_AUTO_TX_DIS (1 << 6) 4291 #define SECI_UART_MCR_BAUD_ADJ_EN (1 << 7) 4292 #define SECI_UART_MCR_XONOFF_RPT (1 << 9) 4293 4294 /* SeciUARTLSR Bit Mask */ 4295 #define SECI_UART_LSR_RXOVR_MASK (1 << 0) 4296 #define SECI_UART_LSR_RFF_MASK (1 << 1) 4297 #define SECI_UART_LSR_TFNE_MASK (1 << 2) 4298 #define SECI_UART_LSR_TI_MASK (1 << 3) 4299 #define SECI_UART_LSR_TPR_MASK (1 << 4) 4300 #define SECI_UART_LSR_TXHALT_MASK (1 << 5) 4301 4302 /* SeciUARTMSR Bit Mask */ 4303 #define SECI_UART_MSR_CTSS_MASK (1 << 0) 4304 #define SECI_UART_MSR_RTSS_MASK (1 << 1) 4305 #define SECI_UART_MSR_SIS_MASK (1 << 2) 4306 #define SECI_UART_MSR_SIS2_MASK (1 << 3) 4307 4308 /* SeciUARTData Bits */ 4309 #define SECI_UART_DATA_RF_NOT_EMPTY_BIT (1 << 12) 4310 #define SECI_UART_DATA_RF_FULL_BIT (1 << 13) 4311 #define SECI_UART_DATA_RF_OVRFLOW_BIT (1 << 14) 4312 #define SECI_UART_DATA_FIFO_PTR_MASK 0xFF 4313 #define SECI_UART_DATA_RF_RD_PTR_SHIFT 16 4314 #define SECI_UART_DATA_RF_WR_PTR_SHIFT 24 4315 4316 /* LTECX: ltecxmux */ 4317 #define LTECX_EXTRACT_MUX(val, idx) (getbit4(&(val), (idx))) 4318 4319 /* LTECX: ltecxmux MODE */ 4320 #define LTECX_MUX_MODE_IDX 0 4321 #define LTECX_MUX_MODE_WCI2 0x0 4322 #define LTECX_MUX_MODE_GPIO 0x1 4323 4324 4325 /* LTECX GPIO Information Index */ 4326 #define LTECX_NVRAM_FSYNC_IDX 0 4327 #define LTECX_NVRAM_LTERX_IDX 1 4328 #define LTECX_NVRAM_LTETX_IDX 2 4329 #define LTECX_NVRAM_WLPRIO_IDX 3 4330 4331 /* LTECX WCI2 Information Index */ 4332 #define LTECX_NVRAM_WCI2IN_IDX 0 4333 #define LTECX_NVRAM_WCI2OUT_IDX 1 4334 4335 /* LTECX: Macros to get GPIO/FNSEL/GCIGPIO */ 4336 #define LTECX_EXTRACT_PADNUM(val, idx) (getbit8(&(val), (idx))) 4337 #define LTECX_EXTRACT_FNSEL(val, idx) (getbit4(&(val), (idx))) 4338 #define LTECX_EXTRACT_GCIGPIO(val, idx) (getbit4(&(val), (idx))) 4339 4340 /* WLAN channel numbers - used from wifi.h */ 4341 4342 /* WLAN BW */ 4343 #define ECI_BW_20 0x0 4344 #define ECI_BW_25 0x1 4345 #define ECI_BW_30 0x2 4346 #define ECI_BW_35 0x3 4347 #define ECI_BW_40 0x4 4348 #define ECI_BW_45 0x5 4349 #define ECI_BW_50 0x6 4350 #define ECI_BW_ALL 0x7 4351 4352 /* WLAN - number of antenna */ 4353 #define WLAN_NUM_ANT1 TXANT_0 4354 #define WLAN_NUM_ANT2 TXANT_1 4355 4356 /* otpctrl1 0xF4 */ 4357 #define OTPC_FORCE_PWR_OFF 0x02000000 4358 /* chipcommon s/r registers introduced with cc rev >= 48 */ 4359 #define CC_SR_CTL0_ENABLE_MASK 0x1 4360 #define CC_SR_CTL0_ENABLE_SHIFT 0 4361 #define CC_SR_CTL0_EN_SR_ENG_CLK_SHIFT 1 /* sr_clk to sr_memory enable */ 4362 #define CC_SR_CTL0_RSRC_TRIGGER_SHIFT 2 /* Rising edge resource trigger 0 to sr_engine */ 4363 #define CC_SR_CTL0_MIN_DIV_SHIFT 6 /* Min division value for fast clk in sr_engine */ 4364 #define CC_SR_CTL0_EN_SBC_STBY_SHIFT 16 /* Allow Subcore mem StandBy? */ 4365 #define CC_SR_CTL0_EN_SR_ALP_CLK_MASK_SHIFT 18 4366 #define CC_SR_CTL0_EN_SR_HT_CLK_SHIFT 19 4367 #define CC_SR_CTL0_ALLOW_PIC_SHIFT 20 /* Allow pic to separate power domains */ 4368 #define CC_SR_CTL0_MAX_SR_LQ_CLK_CNT_SHIFT 25 4369 #define CC_SR_CTL0_EN_MEM_DISABLE_FOR_SLEEP 30 4370 4371 #define CC_SR_CTL1_SR_INIT_MASK 0x3FF 4372 #define CC_SR_CTL1_SR_INIT_SHIFT 0 4373 4374 #define ECI_INLO_PKTDUR_MASK 0x000000f0 /* [7:4] - 4 bits */ 4375 #define ECI_INLO_PKTDUR_SHIFT 4 4376 4377 /* gci chip control bits */ 4378 #define GCI_GPIO_CHIPCTRL_ENAB_IN_BIT 0 4379 #define GCI_GPIO_CHIPCTRL_ENAB_OP_BIT 1 4380 #define GCI_GPIO_CHIPCTRL_INVERT_BIT 2 4381 #define GCI_GPIO_CHIPCTRL_PULLUP_BIT 3 4382 #define GCI_GPIO_CHIPCTRL_PULLDN_BIT 4 4383 #define GCI_GPIO_CHIPCTRL_ENAB_BTSIG_BIT 5 4384 #define GCI_GPIO_CHIPCTRL_ENAB_OD_OP_BIT 6 4385 #define GCI_GPIO_CHIPCTRL_ENAB_EXT_GPIO_BIT 7 4386 4387 /* gci GPIO input status bits */ 4388 #define GCI_GPIO_STS_VALUE_BIT 0 4389 #define GCI_GPIO_STS_POS_EDGE_BIT 1 4390 #define GCI_GPIO_STS_NEG_EDGE_BIT 2 4391 #define GCI_GPIO_STS_FAST_EDGE_BIT 3 4392 #define GCI_GPIO_STS_CLEAR 0xF 4393 4394 #define GCI_GPIO_STS_VALUE (1 << GCI_GPIO_STS_VALUE_BIT) 4395 4396 /* SR Power Control */ 4397 #define SRPWR_DMN0_PCIE (0) /* PCIE */ 4398 #define SRPWR_DMN0_PCIE_SHIFT (SRPWR_DMN0_PCIE) /* PCIE */ 4399 #define SRPWR_DMN0_PCIE_MASK (1 << SRPWR_DMN0_PCIE_SHIFT) /* PCIE */ 4400 #define SRPWR_DMN1_ARMBPSD (1) /* ARM/BP/SDIO */ 4401 #define SRPWR_DMN1_ARMBPSD_SHIFT (SRPWR_DMN1_ARMBPSD) /* ARM/BP/SDIO */ 4402 #define SRPWR_DMN1_ARMBPSD_MASK (1 << SRPWR_DMN1_ARMBPSD_SHIFT) /* ARM/BP/SDIO */ 4403 #define SRPWR_DMN2_MACAUX (2) /* MAC/Phy Aux */ 4404 #define SRPWR_DMN2_MACAUX_SHIFT (SRPWR_DMN2_MACAUX) /* MAC/Phy Aux */ 4405 #define SRPWR_DMN2_MACAUX_MASK (1 << SRPWR_DMN2_MACAUX_SHIFT) /* MAC/Phy Aux */ 4406 #define SRPWR_DMN3_MACMAIN (3) /* MAC/Phy Main */ 4407 #define SRPWR_DMN3_MACMAIN_SHIFT (SRPWR_DMN3_MACMAIN) /* MAC/Phy Main */ 4408 #define SRPWR_DMN3_MACMAIN_MASK (1 << SRPWR_DMN3_MACMAIN_SHIFT) /* MAC/Phy Main */ 4409 #define SRPWR_DMN_ALL_MASK (0xF) 4410 4411 #define SRPWR_REQON_SHIFT (8) /* PowerOnRequest[11:8] */ 4412 #define SRPWR_REQON_MASK (SRPWR_DMN_ALL_MASK << SRPWR_REQON_SHIFT) 4413 #define SRPWR_STATUS_SHIFT (16) /* ExtPwrStatus[19:16], RO */ 4414 #define SRPWR_STATUS_MASK (SRPWR_DMN_ALL_MASK << SRPWR_STATUS_SHIFT) 4415 #define SRPWR_DMN_SHIFT (28) /* PowerDomain[31:28], RO */ 4416 #define SRPWR_DMN_MASK (SRPWR_DMN_ALL_MASK << SRPWR_DMN_SHIFT) 4417 4418 #endif /* _SBCHIPC_H */ 4419