1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Header file for ATSAMA7G54 4 * 5 * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries. 6 */ 7 8 #ifndef _SAMA7G54_H_ 9 #define _SAMA7G54_H_ 10 11 /* 12 * SAMA7G54 definitions 13 * This file defines all structures and symbols for SAMA7G54: 14 * - registers and bitfields 15 * - peripheral base address 16 * - peripheral ID 17 * - PIO definitions 18 */ 19 20 #define GIC_DISTRIBUTOR_BASE 0xE8C11000 /* Base for GIC distributor interface */ 21 #define GIC_INTERFACE_BASE 0xE8C12000 /* Base address for GIC CPU interface */ 22 #define GICC_SIZE 0x1000 23 #define GICD_SIZE 0x1000 24 25 /* ************************************************************************** */ 26 /* PERIPHERAL ID DEFINITIONS FOR SAMA7G54 */ 27 /* ************************************************************************** */ 28 #define ID_DWDT_SW 0 /* Dual Watchdog Timer, Secure World (DWDT_SW) */ 29 #define ID_DWDT_NSW 1 /* DWDT Non Secure World, interrupt (DWDT_NSW) */ 30 #define ID_DWDT_NSW_ALARM 2 /* DWDT Non Secure World Alarm, interrupt */ 31 #define ID_SCKC 4 /* Slow Clock Controller (SCKC) */ 32 #define ID_SHDWC 5 /* SHutDoWn Controller (SHDWC) */ 33 #define ID_RSTC 6 /* Reset Controller (RSTC) */ 34 #define ID_RTC 7 /* Real-Time Clock (RTC) */ 35 #define ID_RTT 8 /* Real-Time Timer (RTT) */ 36 #define ID_CHIPID 9 /* Chip Identifier (CHIPID) */ 37 #define ID_PMC 10 /* Power Management Controller (PMC) */ 38 #define ID_PIOA 11 /* For PIO 0 to 31 (PIOA) */ 39 #define ID_PIOB 12 /* For PIO 32 to 63, interrupt (PIOB) */ 40 #define ID_PIOC 13 /* For PIO 64 to 95, interrupt (PIOC) */ 41 #define ID_PIOD 14 /* For PIO 96 to 127, interrupt (PIOD) */ 42 #define ID_PIOE 15 /* For PIO 128 to 136, interrupt (PIOE) */ 43 #define ID_SECUMOD 17 /* Security Module (SECUMOD) */ 44 #define ID_SECURAM 18 /* Secret RAM (SECURAM) */ 45 #define ID_SFR 19 /* Special Function Register (SFR) */ 46 #define ID_SFRBU 20 /* Special Function Register in BackUp zone */ 47 #define ID_HSMC 21 /* Static Memory Controller - NAND (HSMC) */ 48 #define ID_XDMAC0 22 /* DMA 0, mem to periph, 32 Channels (XDMAC0) */ 49 #define ID_XDMAC1 23 /* DMA 1, mem to periph, 32 Channels (XDMAC1) */ 50 #define ID_XDMAC2 24 /* DMA 2, mem to mem, 4 Channels (XDMAC2) */ 51 #define ID_ACC 25 /* Analog Comparator Controller (ACC) */ 52 #define ID_ADC 26 /* Analog-to-Digital Converter (ADC) */ 53 #define ID_AES 27 /* Advanced Encryption Standard (AES) */ 54 #define ID_TZAESBASC 28 /* TZ AES Bridge - Address Space Controlller */ 55 #define ID_ASRC 30 /* Asynchronous Sample Rate Converter (ASRC) */ 56 #define ID_CPKCC 32 /* Classic Public Key Cryptography Controller */ 57 #define ID_CSI 33 /* CSI 2 between ISC and MIPI PHY (CSI) */ 58 #define ID_CSI2DC 34 /* CSI to Demultiplexer Controller (CSI2DC) */ 59 #define ID_DDRPUBL 35 /* DDR SDRAM PHY Utility Block "Lite" aka PUBL */ 60 #define ID_DDRUMCTL 36 /* Universal DDR-SDRAM Memory Controller */ 61 #define ID_EIC 37 /* External Interrupt Controller (EIC) */ 62 #define ID_FLEXCOM0 38 /* Flexcom 0 (FLEXCOM0) */ 63 #define ID_FLEXCOM1 39 /* Flexcom 1 (FLEXCOM1) */ 64 #define ID_FLEXCOM2 40 /* Flexcom 2 (FLEXCOM2) */ 65 #define ID_FLEXCOM3 41 /* Flexcom 3 (FLEXCOM3) */ 66 #define ID_FLEXCOM4 42 /* Flexcom 4 (FLEXCOM4) */ 67 #define ID_FLEXCOM5 43 /* Flexcom 5 (FLEXCOM5) */ 68 #define ID_FLEXCOM6 44 /* Flexcom 6 (FLEXCOM6) */ 69 #define ID_FLEXCOM7 45 /* Flexcom 7 (FLEXCOM7) */ 70 #define ID_FLEXCOM8 46 /* Flexcom 8 (FLEXCOM8) */ 71 #define ID_FLEXCOM9 47 /* Flexcom 9 (FLEXCOM9) */ 72 #define ID_FLEXCOM10 48 /* Flexcom 10 (FLEXCOM10) */ 73 #define ID_FLEXCOM11 49 /* Flexcom 11 (FLEXCOM11) */ 74 #define ID_GMAC0 51 /* Gigabit Ethernet MAC (GMAC0) */ 75 #define ID_GMAC1 52 /* Ethernet MAC (GMAC1) */ 76 #define ID_GMAC0_TSU 53 /* GMAC - TSU Generic Clock - No Interrupt */ 77 #define ID_GMAC1_TSU 54 /* EMAC - TSU Generic Clock - No Interrupt */ 78 #define ID_ICM 55 /* Integrity Check Monitor (ICM) */ 79 #define ID_ISC 56 /* Camera Interface (ISC) */ 80 #define ID_I2SMCC0 57 /* Inter-IC Sound Controller 0 (I2SMCC0) */ 81 #define ID_I2SMCC1 58 /* Inter-IC Sound Controller 1 (I2SMCC1) */ 82 #define ID_MATRIX 60 /* HSS AHB Matrix (MATRIX) */ 83 #define ID_MCAN0 61 /* Master CAN 0 (MCAN0) */ 84 #define ID_MCAN1 62 /* Master CAN 1 (MCAN1) */ 85 #define ID_MCAN2 63 /* Master CAN 2 (MCAN2) */ 86 #define ID_MCAN3 64 /* Master CAN 3 (MCAN3) */ 87 #define ID_MCAN4 65 /* Master CAN 4 (MCAN4) */ 88 #define ID_MCAN5 66 /* Master CAN 5 (MCAN5) */ 89 #define ID_OTPC 67 /* One Time Programmable memory Controller */ 90 #define ID_PDMC0 68 /* Pulse Density Modulation Controller 0 */ 91 #define ID_PDMC1 69 /* Pulse Density Modulation Controller 1 */ 92 #define ID_PIT64B0 70 /* 64-bit Periodic Interval Timer 0 (PIT64B0) */ 93 #define ID_PIT64B1 71 /* 64-bit Periodic Interval Timer 1 (PIT64B1) */ 94 #define ID_PIT64B2 72 /* 64-bit Periodic Interval Timer 2 (PIT64B2) */ 95 #define ID_PIT64B3 73 /* 64-bit Periodic Interval Timer 3 (PIT64B3) */ 96 #define ID_PIT64B4 74 /* 64-bit Periodic Interval Timer 4 (PIT64B4) */ 97 #define ID_PIT64B5 75 /* 64-bit Periodic Interval Timer 5 (PIT64B5) */ 98 #define ID_PWM 77 /* Pulse Width Modulation (PWM) */ 99 #define ID_QSPI0 78 /* Quad IO Serial Peripheral Interface 0 */ 100 #define ID_QSPI1 79 /* Quad IO Serial Peripheral Interface 1 */ 101 #define ID_SDMMC0 80 /* Ultra HS SD Host controller 0 (eMMC 5.1) */ 102 #define ID_SDMMC1 81 /* Ultra HS SD Host controller 1 (eMMC 4.51) */ 103 #define ID_SDMMC2 82 /* Ultra HS SD Host controller 2 (eMMC 4.51) */ 104 #define ID_SHA 83 /* Secure Hash Algorithm (SHA) */ 105 #define ID_SPDIFRX 84 /* Sony Philips Digital Interface RX (SPDIFRX) */ 106 #define ID_SPDIFTX 85 /* Sony Philips Digital Interface TX (SPDIFTX) */ 107 #define ID_SSC0 86 /* Synchronous Serial Interface 0 (SSC0) */ 108 #define ID_SSC1 87 /* Synchronous Serial Interface 1 (SSC1) */ 109 #define ID_TC0_CHANNEL0 88 /* 32-bit Timer Counter 0 Channel 0 */ 110 #define ID_TC0_CHANNEL1 89 /* 32-bit Timer Counter 0 Channel 1 interrupt */ 111 #define ID_TC0_CHANNEL2 90 /* 32-bit Timer Counter 0 Channel 2 interrupt */ 112 #define ID_TC1_CHANNEL0 91 /* 32-bit Timer Counter 1 Channel 0 */ 113 #define ID_TC1_CHANNEL1 92 /* 32-bit Timer Counter 1 Channel 1 interrupt */ 114 #define ID_TC1_CHANNEL2 93 /* 32-bit Timer Counter 1 Channel 2 interrupt */ 115 #define ID_TCPCA 94 /* USB Type-C Port Controller A (TCPCA) */ 116 #define ID_TCPCB 95 /* USB Type-C Port Controller B (TCPCB) */ 117 #define ID_TDES 96 /* Triple Data Encryption System (TDES) */ 118 #define ID_TRNG 97 /* True Random Number Generator (TRNG) */ 119 #define ID_TZAESB_NS 98 /* TZAESB Non-Secure (Clocks & Interrupt) */ 120 #define ID_TZAESB_NS_SINT 99 /* TZAESB Non-Secure (Interrupt only) */ 121 #define ID_TZAESB_S 100 /* TZAESB Secure */ 122 #define ID_TZAESB_S_SINT 101 /* TZAESB Secure (Interrupt only) */ 123 #define ID_TZC 102 /* TrustZone Address Space Controller (TZC400) */ 124 #define ID_TZPM 103 /* TrustZone Peripheral Manager (TZPM) */ 125 #define ID_UDPHSA 104 /* USB Device High Speed A (UDPHSA) */ 126 #define ID_UDPHSB 105 /* USB Device High Speed B (UDPHSB) */ 127 #define ID_UHPHS 106 /* USB Host Controller High Speed (UHPHS) */ 128 #define ID_XDMAC0_SINT 112 /* DMA 0, mem to periph, 32 CH, Secure INT */ 129 #define ID_XDMAC1_SINT 113 /* DMA 1, mem to periph, 32 CH, Secure INT */ 130 #define ID_XDMAC2_SINT 114 /* DMA 2, mem to mem, 4 Channels, Secure INT */ 131 #define ID_AES_SINT 115 /* Advanced Encryption Standard, Secure INT */ 132 #define ID_GMAC0_Q1 116 /* GMAC0 Queue 1 */ 133 #define ID_GMAC0_Q2 117 /* GMAC0 Queue 2 */ 134 #define ID_GMAC0_Q3 118 /* GMAC0 Queue 3 */ 135 #define ID_GMAC0_Q4 119 /* GMAC0 Queue 4 */ 136 #define ID_GMAC0_Q5 120 /* GMAC0 Queue 5 */ 137 #define ID_GMAC1_Q1 121 /* GMAC1 Queue 1 */ 138 #define ID_ICM_SINT 122 /* Integrity Check Monitor, Secure INTerrupt */ 139 #define ID_MCAN0_INT1 123 /* MCAN0 interrupt1 (MCAN0_INT1) */ 140 #define ID_MCAN1_INT1 124 /* MCAN1 interrupt1 (MCAN1_INT1) */ 141 #define ID_MCAN2_INT1 125 /* MCAN2 interrupt1 (MCAN2_INT1) */ 142 #define ID_MCAN3_INT1 126 /* MCAN3 interrupt1 (MCAN3_INT1) */ 143 #define ID_MCAN4_INT1 127 /* MCAN4 interrupt1 (MCAN4_INT1) */ 144 #define ID_MCAN5_INT1 128 /* MCAN5 interrupt1 (MCAN5_INT1) */ 145 #define ID_PIOA_SINT 129 /* For PIO 0 to 31, Secure INTerrupt */ 146 #define ID_PIOB_SINT 130 /* For PIO 32 to 63, Secure INTerrupt */ 147 #define ID_PIOC_SINT 131 /* For PIO 64 to 95, Secure INTerrupt */ 148 #define ID_PIOD_SINT 132 /* For PIO 96 to 127, Secure INTerrupt */ 149 #define ID_PIOE_SINT 133 /* For PIO 128 to 136, Secure INTerrupt */ 150 #define ID_PIT64B0_SINT 135 /* 64-bit PIT 0, Secure INTerrupt */ 151 #define ID_PIT64B1_SINT 136 /* 64-bit PIT 1, Secure INTerrupt */ 152 #define ID_PIT64B2_SINT 137 /* 64-bit PIT 2, Secure INTerrupt */ 153 #define ID_PIT64B3_SINT 138 /* 64-bit PIT 3, Secure INTerrupt */ 154 #define ID_PIT64B4_SINT 139 /* 64-bit PIT 4, Secure INTerrupt */ 155 #define ID_PIT64B5_SINT 140 /* 64-bit PIT 5, Secure INTerrupt */ 156 #define ID_SDMMC0_TIMER 141 /* SD Host controller 0 (eMMC 5.1) Timer int */ 157 #define ID_SDMMC1_TIMER 142 /* SD Host controller 1 (eMMC 4.51) Timer int */ 158 #define ID_SDMMC2_TIMER 143 /* SD Host controller 2 (eMMC 4.51) Timer int */ 159 #define ID_SHA_SINT 144 /* Secure Hash Algorithm, Secure INTerrupt */ 160 #define ID_TC0_SINT0 145 /* 32-bit TC 0 Channel 0, Secure INTerrupt */ 161 #define ID_TC0_SINT1 146 /* 32-bit TC 0 Channel 1, Secure INTerrupt */ 162 #define ID_TC0_SINT2 147 /* 32-bit TC 0 Channel 2 (TC0_SINT2) */ 163 #define ID_TC1_SINT0 148 /* 32-bit TC 1 Channel 0, Secure INTerrupt */ 164 #define ID_TC1_SINT1 149 /* 32-bit TC 1 Channel 1, Secure INTerrupt */ 165 #define ID_TC1_SINT2 150 /* 32-bit TC 1 Channel 2, Secure INTerrupt */ 166 #define ID_TDES_SINT 151 /* Triple Data Encryption System, Secure INT */ 167 #define ID_TRNG_SINT 152 /* True Random Number Generator, Secure INT */ 168 #define ID_EXT_IRQ0 153 /* External Interrupt ID0 (FIQ) (EXT_IRQ0) */ 169 #define ID_EXT_IRQ1 154 /* External Interrupt ID1 (IRQ) (EXT_IRQ1) */ 170 171 #define ID_PERIPH_MAX 154 /* Number of peripheral IDs */ 172 173 /* ************************************************************************** */ 174 /* BASE ADDRESS DEFINITIONS FOR SAMA7G54 */ 175 /* ************************************************************************** */ 176 #define ACC_BASE_ADDRESS 0xe1600000 177 #define ADC_BASE_ADDRESS 0xe1000000 178 #define AES_BASE_ADDRESS 0xe1810000 179 #define ASRC_BASE_ADDRESS 0xe1610000 180 #define BSC_BASE_ADDRESS 0xe001d054 181 #define CHIPID_BASE_ADDRESS 0xe0020000 182 #define CSI_BASE_ADDRESS 0xe1400000 183 #define CPKCC_BASE_ADDRESS 0xe000c000 184 #define CSI2DC_BASE_ADDRESS 0xe1404000 185 #define DDRPUBL_BASE_ADDRESS 0xe3804000 186 #define DWDT_BASE_ADDRESS 0xe001c000 187 #define EIC_BASE_ADDRESS 0xe1628000 188 #define FLEXCOM0_BASE_ADDRESS 0xe1818000 189 #define FLEXCOM1_BASE_ADDRESS 0xe181c000 190 #define FLEXCOM2_BASE_ADDRESS 0xe1820000 191 #define FLEXCOM3_BASE_ADDRESS 0xe1824000 192 #define FLEXCOM4_BASE_ADDRESS 0xe2018000 193 #define FLEXCOM5_BASE_ADDRESS 0xe201c000 194 #define FLEXCOM6_BASE_ADDRESS 0xe2020000 195 #define FLEXCOM7_BASE_ADDRESS 0xe2024000 196 #define FLEXCOM8_BASE_ADDRESS 0xe2818000 197 #define FLEXCOM9_BASE_ADDRESS 0xe281c000 198 #define FLEXCOM10_BASE_ADDRESS 0xe2820000 199 #define FLEXCOM11_BASE_ADDRESS 0xe2824000 200 #define GMAC0_BASE_ADDRESS 0xe2800000 201 #define GMAC1_BASE_ADDRESS 0xe2804000 202 #define GPBR_BASE_ADDRESS 0xe001d060 203 #define I2SMCC0_BASE_ADDRESS 0xe161c000 204 #define I2SMCC1_BASE_ADDRESS 0xe1620000 205 #define ICM_BASE_ADDRESS 0xe081c000 206 #define ISC_BASE_ADDRESS 0xe1408000 207 #define MATRIX_BASE_ADDRESS 0xe0804000 208 #define MCAN0_BASE_ADDRESS 0xe0828000 209 #define MCAN1_BASE_ADDRESS 0xe082c000 210 #define MCAN2_BASE_ADDRESS 0xe0830000 211 #define MCAN3_BASE_ADDRESS 0xe0834000 212 #define MCAN4_BASE_ADDRESS 0xe0838000 213 #define MCAN5_BASE_ADDRESS 0xe083c000 214 #define NICGPV_BASE_ADDRESS 0xe8b00000 215 #define OTPC_BASE_ADDRESS 0xe8c00000 216 #define PDMC0_BASE_ADDRESS 0xe1608000 217 #define PDMC1_BASE_ADDRESS 0xe160c000 218 #define PIO_BASE_ADDRESS 0xe0014000 219 #define PIT64B0_BASE_ADDRESS 0xe1800000 220 #define PIT64B1_BASE_ADDRESS 0xe1804000 221 #define PIT64B2_BASE_ADDRESS 0xe1808000 222 #define PIT64B3_BASE_ADDRESS 0xe2004000 223 #define PIT64B4_BASE_ADDRESS 0xe2008000 224 #define PIT64B5_BASE_ADDRESS 0xe2810000 225 #define PMC_BASE_ADDRESS 0xe0018000 226 #define PWM_BASE_ADDRESS 0xe1604000 227 #define QSPI0_BASE_ADDRESS 0xe080c000 228 #define QSPI1_BASE_ADDRESS 0xe0810000 229 #define RSTC_BASE_ADDRESS 0xe001d000 230 #define RTC_BASE_ADDRESS 0xe001d0a8 231 #define RTT_BASE_ADDRESS 0xe001d020 232 #define SCKC_BASE_ADDRESS 0xe001d050 233 #define SDMMC0_BASE_ADDRESS 0xe1204000 234 #define SDMMC1_BASE_ADDRESS 0xe1208000 235 #define SDMMC2_BASE_ADDRESS 0xe120c000 236 #define SECUMOD_BASE_ADDRESS 0xe0004000 237 #define SFR_BASE_ADDRESS 0xe1624000 238 #define SFRBU_BASE_ADDRESS 0xe0008000 239 #define SHA_BASE_ADDRESS 0xe1814000 240 #define SHDWC_BASE_ADDRESS 0xe001d010 241 #define HSMC_BASE_ADDRESS 0xe0808000 242 #define SPDIFRX_BASE_ADDRESS 0xe1614000 243 #define SPDIFTX_BASE_ADDRESS 0xe1618000 244 #define SSC0_BASE_ADDRESS 0xe180c000 245 #define SSC1_BASE_ADDRESS 0xe200c000 246 #define SYSCWP_BASE_ADDRESS 0xe001d0dc 247 #define TC0_BASE_ADDRESS 0xe2814000 248 #define TC1_BASE_ADDRESS 0xe0800000 249 #define TCPCA_BASE_ADDRESS 0xe0840000 250 #define TCPCB_BASE_ADDRESS 0xe0844000 251 #define TDES_BASE_ADDRESS 0xe2014000 252 #define TRNG_BASE_ADDRESS 0xe2010000 253 #define TZAESBNS_BASE_ADDRESS 0xe0820000 254 #define TZAESBS_BASE_ADDRESS 0xe0824000 255 #define TZAESBASC_BASE_ADDRESS 0xe2000000 256 #define TZC_BASE_ADDRESS 0xe3000000 257 #define TZPM_BASE_ADDRESS 0xe0010000 258 #define DDRUMCTL_BASE_ADDRESS 0xe3800000 259 #define UDPHSA_BASE_ADDRESS 0xe0814000 260 #define UDPHSB_BASE_ADDRESS 0xe0818000 261 #define UHPHS_OHCI_BASE_ADDRESS 0x00400000 262 #define UHPHS_EHCI_BASE_ADDRESS 0x00500000 263 #define XDMAC0_BASE_ADDRESS 0xe2808000 264 #define XDMAC1_BASE_ADDRESS 0xe280c000 265 #define XDMAC2_BASE_ADDRESS 0xe1200000 266 267 /* ************************************************************************** */ 268 /* MEMORY MAPPING DEFINITIONS FOR SAMA7G54 */ 269 /* ************************************************************************** */ 270 #define IROM_SIZE 0x00014000 271 #define ECC_ROM_SIZE 0x00018000 272 #define CPKCC_ROM_SIZE 0x00010000 273 #define CPKCC_RAM_SIZE 0x00001000 274 #define IRAM_SIZE 0x00020000 275 #define UDPHS_RAMA_SIZE 0x00100000 276 #define UDPHS_RAMB_SIZE 0x00100000 277 #define UHPHS_OHCI_SIZE 0x00001000 278 #define UHPHS_EHCI_SIZE 0x00100000 279 #define NFC_RAM_SIZE 0x00003000 280 #define NFC_SIZE 0x08000000 281 #define QSPIMEM0_SIZE 0x10000000 282 #define QSPIMEM1_SIZE 0x10000000 283 #define EBI_CS0_SIZE 0x08000000 284 #define EBI_CS1_SIZE 0x08000000 285 #define EBI_CS2_SIZE 0x08000000 286 #define EBI_CS3_SIZE 0x08000000 287 #define DDR_CS_SIZE 0x80000000 288 #define SECURAM_SIZE 0x00004000 289 #define SDMMC0_SIZE 0x00004000 290 #define SDMMC1_SIZE 0x00004000 291 #define SDMMC2_SIZE 0x00004000 292 #define APB_DBG_S_SIZE 0x00060000 293 #define APB_DBG_SIZE 0x00001000 294 #define NICGPV_SIZE 0x00100000 295 #define OTPC_SIZE 0x00001000 296 #define CSI2DC_META_SIZE 0x00002000 297 #define ARM_PERIPH_SIZE 0x00008000 298 #define PERIPHERALS_SIZE 0x10000000 299 300 #define IROM_ADDR 0x00000000 301 #define ECC_ROM_ADDR 0x00020000 302 #define CPKCC_ROM_ADDR 0x00040000 303 #define CPKCC_RAM_ADDR 0x00051000 304 #define IRAM_ADDR 0x00100000 305 #define UDPHS_RAMA_ADDR 0x00200000 306 #define UDPHS_RAMB_ADDR 0x00300000 307 #define UHPHS_OHCI_ADDR 0x00400000 308 #define UHPHS_EHCI_ADDR 0x00500000 309 #define NFC_RAM_ADDR 0x00600000 310 #define NFC_ADDR 0x10000000 311 #define QSPIMEM0_ADDR 0x20000000 312 #define QSPIMEM1_ADDR 0x30000000 313 #define EBI_CS0_ADDR 0x40000000 314 #define EBI_CS1_ADDR 0x48000000 315 #define EBI_CS2_ADDR 0x50000000 316 #define EBI_CS3_ADDR 0x58000000 317 #define DDR_CS_ADDR 0x60000000 318 #define SECURAM_ADDR 0xe0000000 319 #define SDMMC0_ADDR 0xe1204000 320 #define SDMMC1_ADDR 0xe1208000 321 #define SDMMC2_ADDR 0xe120c000 322 #define APB_DBG_S_ADDR 0xe8800000 323 #define APB_DBG_ADDR 0xe8900000 324 #define NICGPV_ADDR 0xe8b00000 325 #define OTPC_ADDR 0xe8c00000 326 #define CSI2DC_META_ADDR 0xe8c02000 327 #define ARM_PERIPH_ADDR 0xe8c10000 328 #define PERIPHERALS_ADDR 0xe0000000 329 330 /* ************************************************************************** */ 331 /* DEVICE SIGNATURES FOR SAMA7G54 */ 332 /* ************************************************************************** */ 333 #define CHIP_JTAGID 0X05B4203F 334 #define CHIP_CIDR 0X80162110 335 #define CHIP_EXID 0X00000000 336 337 #endif /* _SAMA7G54_H_ */ 338 339