1 /* 2 * Copyright (c) 2020-2026, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __CPG_REGS_H__ 8 #define __CPG_REGS_H__ 9 10 #include <platform_def.h> 11 12 /* CPG base address */ 13 #define CPG_BASE PLAT_CPG_BASE 14 15 #define CPG_PLL1_STBY (CPG_BASE + 0x0000) 16 #define CPG_PLL1_CLK1 (CPG_BASE + 0x0004) 17 #define CPG_PLL1_CLK2 (CPG_BASE + 0x0008) 18 #define CPG_PLL1_MON (CPG_BASE + 0x000C) 19 #define CPG_PLL4_STBY (CPG_BASE + 0x0010) 20 #define CPG_PLL4_CLK1 (CPG_BASE + 0x0014) 21 #define CPG_PLL4_CLK2 (CPG_BASE + 0x0018) 22 #define CPG_PLL4_MON (CPG_BASE + 0x001C) 23 #define CPG_PLL6_STBY (CPG_BASE + 0x0020) 24 #define CPG_PLL6_CLK1 (CPG_BASE + 0x0024) 25 #define CPG_PLL6_CLK2 (CPG_BASE + 0x0028) 26 #define CPG_PLL6_MON (CPG_BASE + 0x002C) 27 #define CPG_PLL1_SETTING (CPG_BASE + 0x0040) 28 #define CPG_OTPPLL0_MON (CPG_BASE + 0x0044) 29 #define CPG_OTPPLL1_MON (CPG_BASE + 0x0048) 30 #define CPG_OTPPLL2_MON (CPG_BASE + 0x004C) 31 #define CPG_PLL2_STBY (CPG_BASE + 0x0100) 32 #define CPG_PLL2_CLK1 (CPG_BASE + 0x0104) 33 #define CPG_PLL2_CLK2 (CPG_BASE + 0x0108) 34 #define CPG_PLL2_CLK3 (CPG_BASE + 0x010C) 35 #define CPG_PLL2_CLK4 (CPG_BASE + 0x0110) 36 #define CPG_PLL2_CLK5 (CPG_BASE + 0x0114) 37 #define CPG_PLL2_CLK6 (CPG_BASE + 0x0118) 38 #define CPG_PLL2_MON (CPG_BASE + 0x011C) 39 #define CPG_PLL3_STBY (CPG_BASE + 0x0120) 40 #define CPG_PLL3_CLK1 (CPG_BASE + 0x0124) 41 #define CPG_PLL3_CLK2 (CPG_BASE + 0x0128) 42 #define CPG_PLL3_CLK3 (CPG_BASE + 0x012C) 43 #define CPG_PLL3_CLK4 (CPG_BASE + 0x0130) 44 #define CPG_PLL3_CLK5 (CPG_BASE + 0x0134) 45 #define CPG_PLL3_MON (CPG_BASE + 0x013C) 46 #define CPG_PLL5_STBY (CPG_BASE + 0x0140) 47 #define CPG_PLL5_CLK1 (CPG_BASE + 0x0144) 48 #define CPG_PLL5_CLK2 (CPG_BASE + 0x0148) 49 #define CPG_PLL5_CLK3 (CPG_BASE + 0x014C) 50 #define CPG_PLL5_CLK4 (CPG_BASE + 0x0150) 51 #define CPG_PLL5_CLK5 (CPG_BASE + 0x0154) 52 #define CPG_PLL5_MON (CPG_BASE + 0x015C) 53 #define CPG_PL1_DDIV (CPG_BASE + 0x0200) 54 #define CPG_PL2_DDIV (CPG_BASE + 0x0204) 55 #define CPG_PL3A_DDIV (CPG_BASE + 0x0208) 56 #define CPG_PL3B_DDIV (CPG_BASE + 0x020C) 57 #define CPG_PL6_DDIV (CPG_BASE + 0x0210) 58 #define CPG_PL2SDHI_DSEL (CPG_BASE + 0x0218) 59 #define CPG_PL4_DSEL (CPG_BASE + 0x021C) 60 #define CPG_CLKSTATUS (CPG_BASE + 0x0280) 61 #define CPG_PL1_CA55_SSEL (CPG_BASE + 0x0400) 62 #define CPG_PL2_SSEL (CPG_BASE + 0x0404) 63 #define CPG_PL3_SSEL (CPG_BASE + 0x0408) 64 #define CPG_PL5_SSEL (CPG_BASE + 0x0410) 65 #define CPG_PL6_SSEL (CPG_BASE + 0x0414) 66 #define CPG_PL6_ETH_SSEL (CPG_BASE + 0x0418) 67 #define CPG_PL5_SDIV (CPG_BASE + 0x0420) 68 #define CPG_CLKON_CA55 (CPG_BASE + 0x0500) 69 #define CPG_CLKON_CM33 (CPG_BASE + 0x0504) 70 #define CPG_CLKON_SRAM_ACPU (CPG_BASE + 0x0508) 71 #define CPG_CLKON_SRAM_MCPU (CPG_BASE + 0x050C) 72 #define CPG_CLKON_ROM (CPG_BASE + 0x0510) 73 #define CPG_CLKON_GIC600 (CPG_BASE + 0x0514) 74 #define CPG_CLKON_IA55 (CPG_BASE + 0x0518) 75 #define CPG_CLKON_IM33 (CPG_BASE + 0x051C) 76 #define CPG_CLKON_MHU (CPG_BASE + 0x0520) 77 #define CPG_CLKON_CST (CPG_BASE + 0x0524) 78 #define CPG_CLKON_SYC (CPG_BASE + 0x0528) 79 #define CPG_CLKON_DAMC_REG (CPG_BASE + 0x052C) 80 #define CPG_CLKON_SYSC (CPG_BASE + 0x0530) 81 #define CPG_CLKON_OSTM (CPG_BASE + 0x0534) 82 #define CPG_CLKON_MTU (CPG_BASE + 0x0538) 83 #define CPG_CLKON_POE3 (CPG_BASE + 0x053C) 84 #define CPG_CLKON_WDT (CPG_BASE + 0x0548) 85 #define CPG_CLKON_DDR (CPG_BASE + 0x054C) 86 #define CPG_CLKON_SPI_MULTI (CPG_BASE + 0x0550) 87 #define CPG_CLKON_SDHI (CPG_BASE + 0x0554) 88 #define CPG_CLKON_ISU (CPG_BASE + 0x055C) 89 #define CPG_CLKON_CRU (CPG_BASE + 0x0564) 90 #define CPG_CLKON_MIPI_DSI (CPG_BASE + 0x0568) 91 #define CPG_CLKON_LCDC (CPG_BASE + 0x056C) 92 #define CPG_CLKON_SSI (CPG_BASE + 0x0570) 93 #define CPG_CLKON_SRC (CPG_BASE + 0x0574) 94 #define CPG_CLKON_USB (CPG_BASE + 0x0578) 95 #define CPG_CLKON_ETH (CPG_BASE + 0x057C) 96 #define CPG_CLKON_I2C (CPG_BASE + 0x0580) 97 #define CPG_CLKON_SCIF (CPG_BASE + 0x0584) 98 #define CPG_CLKON_SCI (CPG_BASE + 0x0588) 99 #define CPG_CLKON_IRDA (CPG_BASE + 0x058C) 100 #define CPG_CLKON_RSPI (CPG_BASE + 0x0590) 101 #define CPG_CLKON_CANFD (CPG_BASE + 0x0594) 102 #define CPG_CLKON_GPIO (CPG_BASE + 0x0598) 103 #define CPG_CLKON_TSIPG (CPG_BASE + 0x059C) 104 #define CPG_CLKON_JAUTH (CPG_BASE + 0x05A0) 105 #define CPG_CLKON_OTP (CPG_BASE + 0x05A4) 106 #define CPG_CLKON_ADC (CPG_BASE + 0x05A8) 107 #define CPG_CLKON_TSU (CPG_BASE + 0x05AC) 108 #define CPG_CLKON_BBGU (CPG_BASE + 0x05B0) 109 #define CPG_CLKON_AXI_ACPU_BUS (CPG_BASE + 0x05B4) 110 #define CPG_CLKON_AXI_MCPU_BUS (CPG_BASE + 0x05B8) 111 #define CPG_CLKON_AXI_COM_BUS (CPG_BASE + 0x05BC) 112 #define CPG_CLKON_AXI_VIDEO_BUS (CPG_BASE + 0x05C0) 113 #define CPG_CLKON_PERI_COM (CPG_BASE + 0x05C4) 114 #define CPG_CLKON_REG1_BUS (CPG_BASE + 0x05C8) 115 #define CPG_CLKON_REG0_BUS (CPG_BASE + 0x05CC) 116 #define CPG_CLKON_PERI_CPU (CPG_BASE + 0x05D0) 117 #define CPG_CLKON_PERI_VIDEO (CPG_BASE + 0x05D4) 118 #define CPG_CLKON_PERI_DDR (CPG_BASE + 0x05D8) 119 #define CPG_CLKON_AXI_TZCDDR (CPG_BASE + 0x05DC) 120 #define CPG_CLKON_MTGPGS (CPG_BASE + 0x05E0) 121 #define CPG_CLKON_AXI_DEFAULT_SLV (CPG_BASE + 0x05E4) 122 #define CPG_CLKON_OCTA (CPG_BASE + 0x05F4) 123 #define CPG_CLKMON_CA55 (CPG_BASE + 0x0680) 124 #define CPG_CLKMON_CM33 (CPG_BASE + 0x0684) 125 #define CPG_CLKMON_SRAM_ACPU (CPG_BASE + 0x0688) 126 #define CPG_CLKMON_SRAM_MCPU (CPG_BASE + 0x068C) 127 #define CPG_CLKMON_ROM (CPG_BASE + 0x0690) 128 #define CPG_CLKMON_GIC600 (CPG_BASE + 0x0694) 129 #define CPG_CLKMON_IA55 (CPG_BASE + 0x0698) 130 #define CPG_CLKMON_IM33 (CPG_BASE + 0x069C) 131 #define CPG_CLKMON_MHU (CPG_BASE + 0x06A0) 132 #define CPG_CLKMON_CST (CPG_BASE + 0x06A4) 133 #define CPG_CLKMON_SYC (CPG_BASE + 0x06A8) 134 #define CPG_CLKMON_DAMC_REG (CPG_BASE + 0x06AC) 135 #define CPG_CLKMON_SYSC (CPG_BASE + 0x06B0) 136 #define CPG_CLKMON_OSTM (CPG_BASE + 0x06B4) 137 #define CPG_CLKMON_MTU (CPG_BASE + 0x06B8) 138 #define CPG_CLKMON_POE3 (CPG_BASE + 0x06BC) 139 #define CPG_CLKMON_WDT (CPG_BASE + 0x06C8) 140 #define CPG_CLKMON_DDR (CPG_BASE + 0x06CC) 141 #define CPG_CLKMON_SPI_MULTI (CPG_BASE + 0x06D0) 142 #define CPG_CLKMON_SDHI (CPG_BASE + 0x06D4) 143 #define CPG_CLKMON_ISU (CPG_BASE + 0x06DC) 144 #define CPG_CLKMON_CRU (CPG_BASE + 0x06E4) 145 #define CPG_CLKMON_MIPI_DSI (CPG_BASE + 0x06E8) 146 #define CPG_CLKMON_LCDC (CPG_BASE + 0x06EC) 147 #define CPG_CLKMON_SSI (CPG_BASE + 0x06F0) 148 #define CPG_CLKMON_SRC (CPG_BASE + 0x06F4) 149 #define CPG_CLKMON_USB (CPG_BASE + 0x06F8) 150 #define CPG_CLKMON_ETH (CPG_BASE + 0x06FC) 151 #define CPG_CLKMON_I2C (CPG_BASE + 0x0700) 152 #define CPG_CLKMON_SCIF (CPG_BASE + 0x0704) 153 #define CPG_CLKMON_SCI (CPG_BASE + 0x0708) 154 #define CPG_CLKMON_IRDA (CPG_BASE + 0x070C) 155 #define CPG_CLKMON_RSPI (CPG_BASE + 0x0710) 156 #define CPG_CLKMON_CANFD (CPG_BASE + 0x0714) 157 #define CPG_CLKMON_GPIO (CPG_BASE + 0x0718) 158 #define CPG_CLKMON_TSIPG (CPG_BASE + 0x071C) 159 #define CPG_CLKMON_JAUTH (CPG_BASE + 0x0720) 160 #define CPG_CLKMON_OTP (CPG_BASE + 0x0724) 161 #define CPG_CLKMON_ADC (CPG_BASE + 0x0728) 162 #define CPG_CLKMON_TSU (CPG_BASE + 0x072C) 163 #define CPG_CLKMON_BBGU (CPG_BASE + 0x0730) 164 #define CPG_CLKMON_AXI_ACPU_BUS (CPG_BASE + 0x0734) 165 #define CPG_CLKMON_AXI_MCPU_BUS (CPG_BASE + 0x0738) 166 #define CPG_CLKMON_AXI_COM_BUS (CPG_BASE + 0x073C) 167 #define CPG_CLKMON_AXI_VIDEO_BUS (CPG_BASE + 0x0740) 168 #define CPG_CLKMON_PERI_COM (CPG_BASE + 0x0744) 169 #define CPG_CLKMON_REG1_BUS (CPG_BASE + 0x0748) 170 #define CPG_CLKMON_REG0_BUS (CPG_BASE + 0x074C) 171 #define CPG_CLKMON_PERI_CPU (CPG_BASE + 0x0750) 172 #define CPG_CLKMON_PERI_VIDEO (CPG_BASE + 0x0754) 173 #define CPG_CLKMON_PERI_DDR (CPG_BASE + 0x0758) 174 #define CPG_CLKMON_AXI_TZCDDR (CPG_BASE + 0x075C) 175 #define CPG_CLKMON_MTGPGS (CPG_BASE + 0x0760) 176 #define CPG_CLKMON_AXI_DEFAULT_SLV (CPG_BASE + 0x0764) 177 #define CPG_CLKMON_OCTA (CPG_BASE + 0x0774) 178 #define CPG_RST_CA55 (CPG_BASE + 0x0800) 179 #define CPG_RST_CM33 (CPG_BASE + 0x0804) 180 #define CPG_RST_SRAM_ACPU (CPG_BASE + 0x0808) 181 #define CPG_RST_SRAM_MCPU (CPG_BASE + 0x080C) 182 #define CPG_RST_ROM (CPG_BASE + 0x0810) 183 #define CPG_RST_GIC600 (CPG_BASE + 0x0814) 184 #define CPG_RST_IA55 (CPG_BASE + 0x0818) 185 #define CPG_RST_IM33 (CPG_BASE + 0x081C) 186 #define CPG_RST_MHU (CPG_BASE + 0x0820) 187 #define CPG_RST_CST (CPG_BASE + 0x0824) 188 #define CPG_RST_SYC (CPG_BASE + 0x0828) 189 #define CPG_RST_DMAC (CPG_BASE + 0x082C) 190 #define CPG_RST_SYSC (CPG_BASE + 0x0830) 191 #define CPG_RST_OSTM (CPG_BASE + 0x0834) 192 #define CPG_RST_MTU (CPG_BASE + 0x0838) 193 #define CPG_RST_POE3 (CPG_BASE + 0x083C) 194 #define CPG_RST_WDT (CPG_BASE + 0x0848) 195 #define CPG_RST_DDR (CPG_BASE + 0x084C) 196 #define CPG_RST_SPI (CPG_BASE + 0x0850) 197 #define CPG_RST_SDHI (CPG_BASE + 0x0854) 198 #define CPG_RST_ISU (CPG_BASE + 0x085C) 199 #define CPG_RST_CRU (CPG_BASE + 0x0864) 200 #define CPG_RST_MIPI_DSI (CPG_BASE + 0x0868) 201 #define CPG_RST_LCDC (CPG_BASE + 0x086C) 202 #define CPG_RST_SSIF (CPG_BASE + 0x0870) 203 #define CPG_RST_SRC (CPG_BASE + 0x0874) 204 #define CPG_RST_USB (CPG_BASE + 0x0878) 205 #define CPG_RST_ETH (CPG_BASE + 0x087C) 206 #define CPG_RST_I2C (CPG_BASE + 0x0880) 207 #define CPG_RST_SCIF (CPG_BASE + 0x0884) 208 #define CPG_RST_SCI (CPG_BASE + 0x0888) 209 #define CPG_RST_IRDA (CPG_BASE + 0x088C) 210 #define CPG_RST_RSPI (CPG_BASE + 0x0890) 211 #define CPG_RST_CANFD (CPG_BASE + 0x0894) 212 #define CPG_RST_GPIO (CPG_BASE + 0x0898) 213 #define CPG_RST_TSIPG (CPG_BASE + 0x089C) 214 #define CPG_RST_JAUTH (CPG_BASE + 0x08A0) 215 #define CPG_RST_OTP (CPG_BASE + 0x08A4) 216 #define CPG_RST_ADC (CPG_BASE + 0x08A8) 217 #define CPG_RST_TSU (CPG_BASE + 0x08AC) 218 #define CPG_RST_BBGU (CPG_BASE + 0x08B0) 219 #define CPG_RST_AXI_ACPU_BUS (CPG_BASE + 0x08B4) 220 #define CPG_RST_AXI_MCPU_BUS (CPG_BASE + 0x08B8) 221 #define CPG_RST_AXI_COM_BUS (CPG_BASE + 0x08BC) 222 #define CPG_RST_AXI_VIDEO_BUS (CPG_BASE + 0x08C0) 223 #define CPG_RST_PERI_COM (CPG_BASE + 0x08C4) 224 #define CPG_RST_REG1_BUS (CPG_BASE + 0x08C8) 225 #define CPG_RST_REG0_BUS (CPG_BASE + 0x08CC) 226 #define CPG_RST_PERI_CPU (CPG_BASE + 0x08D0) 227 #define CPG_RST_PERI_VIDEO (CPG_BASE + 0x08D4) 228 #define CPG_RST_PERI_DDR (CPG_BASE + 0x08D8) 229 #define CPG_RST_AXI_TZCDDR (CPG_BASE + 0x08DC) 230 #define CPG_RST_MTGPGS (CPG_BASE + 0x08E0) 231 #define CPG_RST_AXI_DEFAULT_SLV (CPG_BASE + 0x08E4) 232 #define CPG_RST_OCTA (CPG_BASE + 0x08F4) 233 #define CPG_RSTMON_CA55 (CPG_BASE + 0x0980) 234 #define CPG_RSTMON_CM33 (CPG_BASE + 0x0984) 235 #define CPG_RSTMON_SRAM_ACPU (CPG_BASE + 0x0988) 236 #define CPG_RSTMON_SRAM_MCPU (CPG_BASE + 0x098C) 237 #define CPG_RSTMON_ROM (CPG_BASE + 0x0990) 238 #define CPG_RSTMON_GIC600 (CPG_BASE + 0x0994) 239 #define CPG_RSTMON_IA55 (CPG_BASE + 0x0998) 240 #define CPG_RSTMON_IM33 (CPG_BASE + 0x099C) 241 #define CPG_RSTMON_MHU (CPG_BASE + 0x09A0) 242 #define CPG_RSTMON_CST (CPG_BASE + 0x09A4) 243 #define CPG_RSTMON_SYC (CPG_BASE + 0x09A8) 244 #define CPG_RSTMON_DMAC (CPG_BASE + 0x09AC) 245 #define CPG_RSTMON_SYSC (CPG_BASE + 0x09B0) 246 #define CPG_RSTMON_OSTM (CPG_BASE + 0x09B4) 247 #define CPG_RSTMON_MTU (CPG_BASE + 0x09B8) 248 #define CPG_RSTMON_POE3 (CPG_BASE + 0x09BC) 249 #define CPG_RSTMON_WDT (CPG_BASE + 0x09C8) 250 #define CPG_RSTMON_DDR (CPG_BASE + 0x09CC) 251 #define CPG_RSTMON_SPI (CPG_BASE + 0x09D0) 252 #define CPG_RSTMON_SDHI (CPG_BASE + 0x09D4) 253 #define CPG_RSTMON_ISU (CPG_BASE + 0x09DC) 254 #define CPG_RSTMON_CRU (CPG_BASE + 0x09E4) 255 #define CPG_RSTMON_MIPI_DSI (CPG_BASE + 0x09E8) 256 #define CPG_RSTMON_LCDC (CPG_BASE + 0x09EC) 257 #define CPG_RSTMON_SSIF (CPG_BASE + 0x09F0) 258 #define CPG_RSTMON_SRC (CPG_BASE + 0x09F4) 259 #define CPG_RSTMON_USB (CPG_BASE + 0x09F8) 260 #define CPG_RSTMON_ETH (CPG_BASE + 0x09FC) 261 #define CPG_RSTMON_I2C (CPG_BASE + 0x0A00) 262 #define CPG_RSTMON_SCIF (CPG_BASE + 0x0A04) 263 #define CPG_RSTMON_SCI (CPG_BASE + 0x0A08) 264 #define CPG_RSTMON_IRDA (CPG_BASE + 0x0A0C) 265 #define CPG_RSTMON_RSPI (CPG_BASE + 0x0A10) 266 #define CPG_RSTMON_CANFD (CPG_BASE + 0x0A14) 267 #define CPG_RSTMON_GPIO (CPG_BASE + 0x0A18) 268 #define CPG_RSTMON_TSIPG (CPG_BASE + 0x0A1C) 269 #define CPG_RSTMON_JAUTH (CPG_BASE + 0x0A20) 270 #define CPG_RSTMON_OTP (CPG_BASE + 0x0A24) 271 #define CPG_RSTMON_ADC (CPG_BASE + 0x0A28) 272 #define CPG_RSTMON_TSU (CPG_BASE + 0x0A2C) 273 #define CPG_RSTMON_BBGU (CPG_BASE + 0x0A30) 274 #define CPG_RSTMON_AXI_ACPU_BUS (CPG_BASE + 0x0A34) 275 #define CPG_RSTMON_AXI_MCPU_BUS (CPG_BASE + 0x0A38) 276 #define CPG_RSTMON_AXI_COM_BUS (CPG_BASE + 0x0A3C) 277 #define CPG_RSTMON_AXI_VIDEO_BUS (CPG_BASE + 0x0A40) 278 #define CPG_RSTMON_PERI_COM (CPG_BASE + 0x0A44) 279 #define CPG_RSTMON_REG1_BUS (CPG_BASE + 0x0A48) 280 #define CPG_RSTMON_REG0_BUS (CPG_BASE + 0x0A4C) 281 #define CPG_RSTMON_PERI_CPU (CPG_BASE + 0x0A50) 282 #define CPG_RSTMON_PERI_VIDEO (CPG_BASE + 0x0A54) 283 #define CPG_RSTMON_PERI_DDR (CPG_BASE + 0x0A58) 284 #define CPG_RSTMON_AXI_TZCDDR (CPG_BASE + 0x0A5C) 285 #define CPG_RSTMON_MTGPGS (CPG_BASE + 0x0A60) 286 #define CPG_RSTMON_AXI_DEFAULT_SLV (CPG_BASE + 0x0A64) 287 #define CPG_RSTMON_OCTA (CPG_BASE + 0x0A74) 288 #define CPG_EN_OSTM (CPG_BASE + 0x0B00) 289 #define CPG_WDTOVF_RST (CPG_BASE + 0x0B10) 290 #define CPG_WDTRST_SEL (CPG_BASE + 0x0B14) 291 #define CPG_DBGRST (CPG_BASE + 0x0B20) 292 #define CPG_CLUSTER_PCHMON (CPG_BASE + 0x0B30) 293 #define CPG_CLUSTER_PCHCTL (CPG_BASE + 0x0B34) 294 #define CPG_CORE0_PCHMON (CPG_BASE + 0x0B38) 295 #define CPG_CORE0_PCHCTL (CPG_BASE + 0x0B3C) 296 #define CPG_CORE1_PCHMON (CPG_BASE + 0x0B40) 297 #define CPG_CORE1_PCHCTL (CPG_BASE + 0x0B44) 298 #define CPG_BUS_ACPU_MSTOP (CPG_BASE + 0x0B60) 299 #define CPG_BUS_MCPU1_MSTOP (CPG_BASE + 0x0B64) 300 #define CPG_BUS_MCPU2_MSTOP (CPG_BASE + 0x0B68) 301 #define CPG_BUS_PERI_COM_MSTOP (CPG_BASE + 0x0B6C) 302 #define CPG_BUS_PERI_CPU_MSTOP (CPG_BASE + 0x0B70) 303 #define CPG_BUS_PERI_DDR_MSTOP (CPG_BASE + 0x0B74) 304 #define CPG_BUS_PERI_VIDEO_MSTOP (CPG_BASE + 0x0B78) 305 #define CPG_BUS_REG0_MSTOP (CPG_BASE + 0x0B7C) 306 #define CPG_BUS_REG1_MSTOP (CPG_BASE + 0x0B80) 307 #define CPG_BUS_TZCDDR_MSTOP (CPG_BASE + 0x0B84) 308 #define CPG_MHU_MSTOP (CPG_BASE + 0x0B88) 309 #define CPG_BUS_PERI_STP_MSTOP (CPG_BASE + 0x0B8C) 310 #define CPG_BUS_MCPU3_MSTOP (CPG_BASE + 0x0B90) 311 #define CPG_OTHERFUNC1_REG (CPG_BASE + 0x0BE8) 312 #define CPG_OTHERFUNC2_REG (CPG_BASE + 0x0BEC) 313 314 #define PLL1_STBY_RESETB BIT(0) 315 #define PLL1_STBY_SSC_EN BIT(2) 316 #define PLL1_STBY_SSC_MODE0 BIT(4) 317 #define PLL1_STBY_SSC_MODE1 BIT(5) 318 #define PLL1_STBY_RESETB_WEN BIT(16) 319 #define PLL1_STBY_SSC_EN_WEN BIT(18) 320 #define PLL1_STBY_SSC_MODE_WEN BIT(20) 321 #define PLL1_CLK1_DIV_P_24M (1 << 0) 322 #define PLL1_CLK1_DIV_P_12M (2 << 0) 323 #define PLL1_CLK1_DIV_P_8M (3 << 0) 324 #define PLL1_CLK1_DIV_P_6M (4 << 0) 325 #define PLL1_CLK2_DIV_S_RATIO1 (0 << 0) 326 #define PLL1_CLK2_DIV_S_RATIO2 (1 << 0) 327 #define PLL1_CLK2_DIV_S_RATIO4 (2 << 0) 328 #define PLL1_CLK2_DIV_S_RATIO8 (3 << 0) 329 #define PLL1_CLK2_DIV_S_RATIO16 (4 << 0) 330 #define PLL1_CLK2_DIV_S_RATIO32 (5 << 0) 331 #define PLL1_CLK2_DIV_S_RATIO64 (6 << 0) 332 #define PLL1_MON_PLL1_RESETB BIT(0) 333 #define PLL1_MON_PLL1_LOCK BIT(4) 334 #define PLL4_STBY_RESETB BIT(0) 335 #define PLL4_STBY_SSC_EN BIT(2) 336 #define PLL4_STBY_SSC_MODE0 BIT(4) 337 #define PLL4_STBY_SSC_MODE1 BIT(5) 338 #define PLL4_STBY_RESETB_WEN BIT(16) 339 #define PLL4_STBY_SSC_EN_WEN BIT(18) 340 #define PLL4_STBY_SSC_MODE_WEN BIT(20) 341 #define PLL4_CLK1_DIV_P_24M (1 << 0) 342 #define PLL4_CLK1_DIV_P_12M (2 << 0) 343 #define PLL4_CLK1_DIV_P_8M (3 << 0) 344 #define PLL4_CLK1_DIV_P_6M (4 << 0) 345 #define PLL4_CLK2_DIV_S_RATIO1 (0 << 0) 346 #define PLL4_CLK2_DIV_S_RATIO2 (1 << 0) 347 #define PLL4_CLK2_DIV_S_RATIO4 (2 << 0) 348 #define PLL4_CLK2_DIV_S_RATIO8 (3 << 0) 349 #define PLL4_CLK2_DIV_S_RATIO16 (4 << 0) 350 #define PLL4_CLK2_DIV_S_RATIO32 (5 << 0) 351 #define PLL4_CLK2_DIV_S_RATIO64 (6 << 0) 352 #define PLL4_MON_PLL4_RESETB BIT(0) 353 #define PLL4_MON_PLL4_LOCK BIT(4) 354 #define PLL6_STBY_RESETB BIT(0) 355 #define PLL6_STBY_SSC_EN BIT(2) 356 #define PLL6_STBY_SSC_MODE0 BIT(4) 357 #define PLL6_STBY_SSC_MODE1 BIT(5) 358 #define PLL6_STBY_RESETB_WEN BIT(16) 359 #define PLL6_STBY_SSC_EN_WEN BIT(18) 360 #define PLL6_STBY_SSC_MODE_WEN BIT(20) 361 #define PLL6_CLK1_DIV_P_24M (1 << 0) 362 #define PLL6_CLK1_DIV_P_12M (2 << 0) 363 #define PLL6_CLK1_DIV_P_8M (3 << 0) 364 #define PLL6_CLK1_DIV_P_6M (4 << 0) 365 #define PLL6_CLK2_DIV_S_RATIO1 (0 << 0) 366 #define PLL6_CLK2_DIV_S_RATIO2 (1 << 0) 367 #define PLL6_CLK2_DIV_S_RATIO4 (2 << 0) 368 #define PLL6_CLK2_DIV_S_RATIO8 (3 << 0) 369 #define PLL6_CLK2_DIV_S_RATIO16 (4 << 0) 370 #define PLL6_CLK2_DIV_S_RATIO32 (5 << 0) 371 #define PLL6_CLK2_DIV_S_RATIO64 (6 << 0) 372 #define PLL6_MON_PLL6_RESETB BIT(0) 373 #define PLL6_MON_PLL6_LOCK BIT(4) 374 #define PLL1_SETTING_SEL_PLL1 BIT(0) 375 #define PLL1_SETTING_SEL_PLL1_WEN BIT(16) 376 #define PLL_CLK_DIV_M_SET(a, b) (mmio_write_32(a, ((mmio_read_32(a)) | (b << 6)))) 377 #define PLL_CLK_DIV_K_SET(a, b) (mmio_write_32(a, ((mmio_read_32(a)) | (b << 16)))) 378 #define PLL_CLK_MRR_SET(a, b) (mmio_write_32(a, ((mmio_read_32(a)) | (b << 8)))) 379 #define PLL_CLK_MFR_SET(a, b) (mmio_write_32(a, ((mmio_read_32(a)) | (b << 16)))) 380 381 #define PLL2_STBY_RESETB BIT(0) 382 #define PLL2_STBY_SSC_EN BIT(2) 383 #define PLL2_STBY_DOWNSPREAD BIT(4) 384 #define PLL2_STBY_RESETB_WEN BIT(16) 385 #define PLL2_STBY_SSC_EN_WEN BIT(18) 386 #define PLL2_STBY_DOWNSPREAD_WEN BIT(20) 387 #define PLL2_CLK1_POSTDIV1_WEN BIT(16) 388 #define PLL2_CLK1_POSTDIV2_WEN BIT(20) 389 #define PLL2_CLK1_REFDIV_WEN BIT(24) 390 #define PLL2_CLK2_DACPD BIT(0) 391 #define PLL2_CLK2_DSMPD BIT(2) 392 #define PLL2_CLK2_FOUT4PHASEPD BIT(4) 393 #define PLL2_CLK2_FOUTPOSTDIVPD BIT(6) 394 #define PLL2_CLK2_FOUTVCOPD BIT(8) 395 #define PLL2_CLK2_DACPD_WEN BIT(16) 396 #define PLL2_CLK2_DSMPD_WEN BIT(18) 397 #define PLL2_CLK2_FOUT4PHASEPD_WEN BIT(20) 398 #define PLL2_CLK2_FOUTPOSTDIVPD_WEN BIT(22) 399 #define PLL2_CLK2_FOUTVCOPD_WEN BIT(24) 400 #define PLL2_CLK6_SEL_EXTWAVE BIT(0) 401 #define PLL2_CLK6_SEL_EXTWAVE_WEN BIT(16) 402 #define PLL2_MON_PLL2_RESETB BIT(0) 403 #define PLL2_MON_PLL2_LOCK BIT(4) 404 #define PLL3_STBY_RESETB BIT(0) 405 #define PLL3_STBY_SSC_EN BIT(2) 406 #define PLL3_STBY_DOWNSPREAD BIT(4) 407 #define PLL3_STBY_RESETB_WEN BIT(16) 408 #define PLL3_STBY_SSC_EN_WEN BIT(18) 409 #define PLL3_STBY_DOWNSPREAD_WEN BIT(20) 410 #define PLL3_CLK1_POSTDIV1_WEN BIT(16) 411 #define PLL3_CLK1_POSTDIV2_WEN BIT(20) 412 #define PLL3_CLK1_REFDIV_WEN BIT(24) 413 #define PLL3_CLK2_DACPD BIT(0) 414 #define PLL3_CLK2_DSMPD BIT(2) 415 #define PLL3_CLK2_FOUT4PHASEPD BIT(4) 416 #define PLL3_CLK2_FOUTPOSTDIVPD BIT(6) 417 #define PLL3_CLK2_FOUTVCOPD BIT(8) 418 #define PLL3_CLK2_DACPD_WEN BIT(16) 419 #define PLL3_CLK2_DSMPD_WEN BIT(18) 420 #define PLL3_CLK2_FOUT4PHASEPD_WEN BIT(20) 421 #define PLL3_CLK2_FOUTPOSTDIVPD_WEN BIT(22) 422 #define PLL3_CLK2_FOUTVCOPD_WEN BIT(24) 423 #define PLL3_CLK6_SEL_EXTWAVE BIT(0) 424 #define PLL3_CLK6_SEL_EXTWAVE_WEN BIT(16) 425 #define PLL3_MON_PLL3_RESETB BIT(0) 426 #define PLL3_MON_PLL3_LOCK BIT(4) 427 #define PLL5_STBY_RESETB BIT(0) 428 #define PLL5_STBY_SSC_EN BIT(2) 429 #define PLL5_STBY_DOWNSPREAD BIT(4) 430 #define PLL5_STBY_RESETB_WEN BIT(16) 431 #define PLL5_STBY_SSC_EN_WEN BIT(18) 432 #define PLL5_STBY_DOWNSPREAD_WEN BIT(20) 433 #define PLL5_CLK1_POSTDIV1_WEN BIT(16) 434 #define PLL5_CLK1_POSTDIV2_WEN BIT(20) 435 #define PLL5_CLK1_REFDIV_WEN BIT(24) 436 #define PLL5_CLK2_DACPD BIT(0) 437 #define PLL5_CLK2_DSMPD BIT(2) 438 #define PLL5_CLK2_FOUT4PHASEPD BIT(4) 439 #define PLL5_CLK2_FOUTPOSTDIVPD BIT(6) 440 #define PLL5_CLK2_FOUTVCOPD BIT(8) 441 #define PLL5_CLK2_DACPD_WEN BIT(16) 442 #define PLL5_CLK2_DSMPD_WEN BIT(18) 443 #define PLL5_CLK2_FOUT4PHASEPD_WEN BIT(20) 444 #define PLL5_CLK2_FOUTPOSTDIVPD_WEN BIT(22) 445 #define PLL5_CLK2_FOUTVCOPD_WEN BIT(24) 446 #define PLL5_CLK6_SEL_EXTWAVE BIT(0) 447 #define PLL5_CLK6_SEL_EXTWAVE_WEN BIT(16) 448 #define PLL5_MON_PLL5_RESETB BIT(0) 449 #define PLL5_MON_PLL5_LOCK BIT(4) 450 451 #define PLL_CLK_POSTDIV1_SET(a, b) (mmio_write_32(a, ((mmio_read_32(a)) | (b << 0)))) 452 #define PLL_CLK_POSTDIV2_SET(a, b) (mmio_write_32(a, ((mmio_read_32(a)) | (b << 4)))) 453 #define PLL_CLK_REFDIV_SET(a, b) (mmio_write_32(a, ((mmio_read_32(a)) | (b << 8)))) 454 #define PLL_CLK_DIVVAL_SET(a, b) (mmio_write_32(a, ((mmio_read_32(a)) | (b << 0)))) 455 #define PLL_CLK_FRACIN_SET(a, b) (mmio_write_32(a, ((mmio_read_32(a)) | (b << 8)))) 456 #define PLL_CLK_EXT_MAXADDR_SET(a, b) (mmio_write_32(a, ((mmio_read_32(a)) | (b << 0)))) 457 #define PLL_CLK_INITIN_SET(a, b) (mmio_write_32(a, ((mmio_read_32(a)) | (b << 16)))) 458 #define PLL_CLK_SPREAD_SET(a, b) (mmio_write_32(a, ((mmio_read_32(a)) | (b << 0)))) 459 460 #define PL1_DDIV_DIVPL1_SET_1_1 (0 << 0) 461 #define PL1_DDIV_DIVPL1_SET_1_2 (1 << 0) 462 #define PL1_DDIV_DIVPL1_SET_1_4 (2 << 0) 463 #define PL1_DDIV_DIVPL1_SET_1_8 (3 << 0) 464 #define PL1_DDIV_DIVPL1_SET_WEN (1 << 16) 465 #define PL2_DDIV_DIVPL2A_SET_1_1 (0 << 0) 466 #define PL2_DDIV_DIVPL2A_SET_1_2 (1 << 0) 467 #define PL2_DDIV_DIVPL2A_SET_1_4 (2 << 0) 468 #define PL2_DDIV_DIVPL2A_SET_1_8 (3 << 0) 469 #define PL2_DDIV_DIVPL2A_SET_1_32 (4 << 0) 470 #define PL2_DDIV_DIVPL2B_SET_1_1 (0 << 4) 471 #define PL2_DDIV_DIVPL2B_SET_1_2 (1 << 4) 472 #define PL2_DDIV_DIVPL2B_SET_1_4 (2 << 4) 473 #define PL2_DDIV_DIVPL2B_SET_1_8 (3 << 4) 474 #define PL2_DDIV_DIVPL2B_SET_1_32 (4 << 4) 475 #define PL2_DDIV_DIVPL2C_SET_1_1 (0 << 8) 476 #define PL2_DDIV_DIVPL2C_SET_1_2 (1 << 8) 477 #define PL2_DDIV_DIVPL2C_SET_1_4 (2 << 8) 478 #define PL2_DDIV_DIVPL2C_SET_1_8 (3 << 8) 479 #define PL2_DDIV_DIVPL2C_SET_1_32 (4 << 8) 480 #define PL2_DDIV_DIVDSILPCLK_SET_1_16 (0 << 12) 481 #define PL2_DDIV_DIVDSILPCLK_SET_1_32 (1 << 12) 482 #define PL2_DDIV_DIVDSILPCLK_SET_1_64 (2 << 12) 483 #define PL2_DDIV_DIVDSILPCLK_SET_1_128 (3 << 12) 484 #define PL2_DDIV_DIVPL2A_WEN BIT(16) 485 #define PL2_DDIV_DIVPL2B_WEN BIT(20) 486 #define PL2_DDIV_DIVPL2C_WEN BIT(24) 487 #define PL2_DDIV_DIVDSILPCLK_WEN BIT(28) 488 #define PL3A_DDIV_DIVPL3A_SET_1_1 (0 << 0) 489 #define PL3A_DDIV_DIVPL3A_SET_1_2 (1 << 0) 490 #define PL3A_DDIV_DIVPL3A_SET_1_4 (2 << 0) 491 #define PL3A_DDIV_DIVPL3A_SET_1_8 (3 << 0) 492 #define PL3A_DDIV_DIVPL3A_SET_1_32 (4 << 0) 493 #define PL3A_DDIV_DIVPL3B_SET_1_1 (0 << 0) 494 #define PL3A_DDIV_DIVPL3B_SET_1_2 (1 << 0) 495 #define PL3A_DDIV_DIVPL3B_SET_1_4 (2 << 0) 496 #define PL3A_DDIV_DIVPL3B_SET_1_8 (3 << 0) 497 #define PL3A_DDIV_DIVPL3B_SET_1_32 (4 << 0) 498 #define PL3A_DDIV_DIVPL3C_SET_1_1 (0 << 0) 499 #define PL3A_DDIV_DIVPL3C_SET_1_2 (1 << 0) 500 #define PL3A_DDIV_DIVPL3C_SET_1_4 (2 << 0) 501 #define PL3A_DDIV_DIVPL3C_SET_1_8 (3 << 0) 502 #define PL3A_DDIV_DIVPL3C_SET_1_32 (4 << 0) 503 #define PL3A_DDIV_DIVPL3F_SET_1_1 (0 << 0) 504 #define PL3A_DDIV_DIVPL3F_SET_1_2 (1 << 0) 505 #define PL3A_DDIV_DIVPL3F_SET_1_4 (2 << 0) 506 #define PL3A_DDIV_DIVPL3F_SET_1_8 (3 << 0) 507 #define PL3A_DDIV_DIVPL3F_SET_1_32 (4 << 0) 508 #define PL3A_DDIV_DIVPL3A_WEN BIT(16) 509 #define PL3A_DDIV_DIVPL3B_WEN BIT(20) 510 #define PL3A_DDIV_DIVPL3C_WEN BIT(24) 511 #define PL3A_DDIV_DIVPL3F_WEN BIT(28) 512 #define PL3B_DDIV_DIVPL3CLK200FIX_SET_1_1 (0 << 0) 513 #define PL3B_DDIV_DIVPL3CLK200FIX_SET_1_2 (1 << 0) 514 #define PL3B_DDIV_DIVPL3CLK200FIX_SET_1_4 (2 << 0) 515 #define PL3B_DDIV_DIVPL3CLK200FIX_SET_1_8 (3 << 0) 516 #define PL3B_DDIV_DIVPL3CLK200FIX_SET_1_32 (4 << 0) 517 #define PL3B_DDIV_DIVPL3CLK200FIX_WEN BIT(16) 518 #define PL6_DDIV_DIVGPU_SET_1_1 (0 << 0) 519 #define PL6_DDIV_DIVGPU_SET_1_2 (1 << 0) 520 #define PL6_DDIV_DIVGPU_SET_1_4 (2 << 0) 521 #define PL6_DDIV_DIVGPU_SET_1_8 (3 << 0) 522 #define PL6_DDIV_DIVGPU_WEN BIT(16) 523 #define PL2SDHI_DSEL_SEL_SDHI0_SET_CLK533FIX_C (1 << 0) 524 #define PL2SDHI_DSEL_SEL_SDHI0_SET_DIV_PLL2_DIV8 (2 << 0) 525 #define PL2SDHI_DSEL_SEL_SDHI0_SET_DIV_PLL2_DIV12 (3 << 0) 526 #define PL2SDHI_DSEL_SEL_SDHI1_SET_CLK533FIX_C (1 << 4) 527 #define PL2SDHI_DSEL_SEL_SDHI1_SET_DIV_PLL2_DIV8 (2 << 4) 528 #define PL2SDHI_DSEL_SEL_SDHI1_SET_DIV_PLL2_DIV12 (3 << 4) 529 #define PL2SDHI_DSEL_SEL_SDHI0_WEN BIT(16) 530 #define PL2SDHI_DSEL_SEL_SDHI1_WEN BIT(20) 531 #define PL4_DSEL_SEL_PLL4_SET BIT(0) 532 #define PL4_DSEL_SEL_PLL4_WEN BIT(16) 533 #define CLKSTATUS_DIVPL1_STS BIT(0) 534 #define CLKSTATUS_DIVPL2A_STS BIT(4) 535 #define CLKSTATUS_DIVPL2B_STS BIT(5) 536 #define CLKSTATUS_DIVPL2C_STS BIT(6) 537 #define CLKSTATUS_DIVDSILPCLK_STS BIT(7) 538 #define CLKSTATUS_DIVPL3A_STS BIT(8) 539 #define CLKSTATUS_DIVPL3B_STS BIT(9) 540 #define CLKSTATUS_DIVPL3C_STS BIT(10) 541 #define CLKSTATUS_DIVPL3CLK200FIX_STS BIT(11) 542 #define CLKSTATUS_DIVPL3F_STS BIT(12) 543 #define CLKSTATUS_DIVGPU_STS BIT(20) 544 #define CLKSTATUS_SELSDHI0_STS BIT(28) 545 #define CLKSTATUS_SELSDHI1_STS BIT(29) 546 #define CLKSTATUS_SELPLL4_STS BIT(31) 547 #define PL1_CA55_SSEL_SEL_PLL1_SET BIT(0) 548 #define PL1_CA55_SSEL_SEL_PLL1_WEN BIT(16) 549 #define PL2_SSEL_SEL_PLL2_1_SET BIT(0) 550 #define PL2_SSEL_SEL_PLL2_2_SET BIT(4) 551 #define PL2_SSEL_SEL_PLL2_1_WEN BIT(16) 552 #define PL2_SSEL_SEL_PLL2_2_WEN BIT(20) 553 #define PL3_SSEL_SEL_PLL3_1_SET BIT(0) 554 #define PL3_SSEL_SEL_PLL3_2_SET BIT(4) 555 #define PL3_SSEL_SEL_PLL3_3_SET BIT(8) 556 #define PL3_SSEL_SEL_PLL3_5_SET BIT(12) 557 #define PL3_SSEL_SEL_PLL3_1_WEN BIT(16) 558 #define PL3_SSEL_SEL_PLL3_2_WEN BIT(20) 559 #define PL3_SSEL_SEL_PLL3_3_WEN BIT(24) 560 #define PL3_SSEL_SEL_PLL3_5_WEN BIT(28) 561 #define PL5_SSEL_SEL_PLL5_1_SET BIT(0) 562 #define PL5_SSEL_SEL_PLL5_2_SET BIT(4) 563 #define PL5_SSEL_SEL_PLL5_1_WEN BIT(16) 564 #define PL5_SSEL_SEL_PLL5_2_WEN BIT(20) 565 #define PL6_SSEL_SEL_PLL6_1_SET BIT(0) 566 #define PL6_SSEL_SEL_GPU1_1_SET BIT(4) 567 #define PL6_SSEL_SEL_GPU1_2_SET BIT(8) 568 #define PL6_SSEL_SEL_GPU2_SET BIT(12) 569 #define PL6_SSEL_SEL_PLL6_1_WEN BIT(16) 570 #define PL6_SSEL_SEL_GPU1_1_WEN BIT(20) 571 #define PL6_SSEL_SEL_GPU1_2_WEN BIT(24) 572 #define PL6_SSEL_SEL_GPU2_WEN BIT(28) 573 #define PL6_ETH_SSEL_SEL_PLL6_2_SET BIT(0) 574 #define PL6_ETH_SSEL_SEL_ETH_SET BIT(4) 575 #define PL6_ETH_SSEL_SEL_PLL6_2_WEN BIT(16) 576 #define PL6_ETH_SSEL_SEL_ETH_WEN BIT(20) 577 #define PL5_SDIV_DIVDSIA_SET_1_1 (0 << 0) 578 #define PL5_SDIV_DIVDSIA_SET_1_2 (1 << 0) 579 #define PL5_SDIV_DIVDSIA_SET_1_4 (2 << 0) 580 #define PL5_SDIV_DIVDSIA_SET_1_8 (3 << 0) 581 #define PL5_SDIV_DIVDSIB_SET_1_1 (0 << 8) 582 #define PL5_SDIV_DIVDSIB_SET_1_2 (1 << 8) 583 #define PL5_SDIV_DIVDSIB_SET_1_3 (2 << 8) 584 #define PL5_SDIV_DIVDSIB_SET_1_4 (3 << 8) 585 #define PL5_SDIV_DIVDSIB_SET_1_5 (4 << 8) 586 #define PL5_SDIV_DIVDSIB_SET_1_6 (5 << 8) 587 #define PL5_SDIV_DIVDSIB_SET_1_7 (6 << 8) 588 #define PL5_SDIV_DIVDSIB_SET_1_8 (7 << 8) 589 #define PL5_SDIV_DIVDSIB_SET_1_9 (8 << 8) 590 #define PL5_SDIV_DIVDSIB_SET_1_10 (9 << 8) 591 #define PL5_SDIV_DIVDSIB_SET_1_11 (10 << 8) 592 #define PL5_SDIV_DIVDSIB_SET_1_12 (11 << 8) 593 #define PL5_SDIV_DIVDSIB_SET_1_13 (12 << 8) 594 #define PL5_SDIV_DIVDSIB_SET_1_14 (13 << 8) 595 #define PL5_SDIV_DIVDSIB_SET_1_15 (14 << 8) 596 #define PL5_SDIV_DIVDSIB_SET_1_16 (15 << 8) 597 #define PL5_SDIV_DIVDSA_WEN BIT(16) 598 #define PL5_SDIV_DIVSDIB_WEN BIT(24) 599 #define CLKON_CLK0_ON BIT(0) 600 #define CLKON_CLK0_ON_WEN BIT(16) 601 #define CLKMON_UNIT0_CLK_MON BIT(0) 602 #define RST_UNIT0_RSTB BIT(0) 603 #define RST_UNIT0_RST_WEN BIT(16) 604 #define RSTMON_UNIT0_RST_MON BIT(0) 605 #define EN_OSTM_EN0_ON BIT(0) 606 #define EN_OSTM_EN1_ON BIT(1) 607 #define EN_OSTM_EN2_ON BIT(2) 608 #define EN_OSTM_EN0_WEN BIT(16) 609 #define EN_OSTM_EN1_WEN BIT(17) 610 #define EN_OSTM_EN2_WEN BIT(18) 611 #define WDTOVF_RST_WDTOVF0 BIT(0) 612 #define WDTOVF_RST_WDTOVF1 BIT(1) 613 #define WDTOVF_RST_WDTOVF2 BIT(2) 614 #define WDTOVF_RST_WDTOVF3 BIT(3) 615 #define WDTOVF_RST_WDTOVF0_WEN BIT(16) 616 #define WDTOVF_RST_WDTOVF1_WEN BIT(17) 617 #define WDTOVF_RST_WDTOVF2_WEN BIT(18) 618 #define WDTOVF_RST_WDTOVF3_WEN BIT(19) 619 #define WDTRST_SEL_WDTRSTSEL0 BIT(0) 620 #define WDTRST_SEL_WDTRSTSEL1 BIT(1) 621 #define WDTRST_SEL_WDTRSTSEL2 BIT(2) 622 #define WDTRST_SEL_WDTRSTSEL3 BIT(3) 623 #define WDTRST_SEL_WDTRSTSEL4 BIT(4) 624 #define WDTRST_SEL_WDTRSTSEL5 BIT(5) 625 #define WDTRST_SEL_WDTRSTSEL6 BIT(6) 626 #define WDTRST_SEL_WDTRSTSEL7 BIT(7) 627 #define WDTRST_SEL_WDTRSTSEL8 BIT(8) 628 #define WDTRST_SEL_WDTRSTSEL9 BIT(9) 629 #define WDTRST_SEL_WDTRSTSEL10 BIT(10) 630 #define WDTRST_SEL_WDTRSTSEL0_WEN BIT(16) 631 #define WDTRST_SEL_WDTRSTSEL1_WEN BIT(17) 632 #define WDTRST_SEL_WDTRSTSEL2_WEN BIT(18) 633 #define WDTRST_SEL_WDTRSTSEL3_WEN BIT(19) 634 #define WDTRST_SEL_WDTRSTSEL4_WEN BIT(20) 635 #define WDTRST_SEL_WDTRSTSEL5_WEN BIT(21) 636 #define WDTRST_SEL_WDTRSTSEL6_WEN BIT(22) 637 #define WDTRST_SEL_WDTRSTSEL7_WEN BIT(23) 638 #define WDTRST_SEL_WDTRSTSEL8_WEN BIT(24) 639 #define WDTRST_SEL_WDTRSTSEL9_WEN BIT(25) 640 #define WDTRST_SEL_WDTRSTSEL10_WEN BIT(26) 641 #define DBGRST_UNIT0_RSTB BIT(0) 642 #define DBGRST_UNIT0_RST_WEN BIT(16) 643 #define CLUSTER_PCHMON_PACCEPT_MON BIT(0) 644 #define CLUSTER_PCHMON_PDENY_MON BIT(1) 645 #define CLUSTER_PCHCTL_PREQ_SET BIT(0) 646 #define CLUSTER_PCHCTL_PSTATE0_SET_ON (0x48 << 16) 647 #define CLUSTER_PCHCTL_PSTATE0_SET_OFF (0x00 << 16) 648 #define CORE0_PCHMON_PACCEPT0_MON BIT(0) 649 #define CORE0_PCHMON_PDENY0_MON BIT(1) 650 #define CORE0_PCHCTL_PREQ0_SET BIT(0) 651 #define CORE0_PCHCTL_PSTATE0_SET_ON (0x08 << 16) 652 #define CORE0_PCHCTL_PSTATE0_SET_OFF_EMULATED (0x01 << 16) 653 #define CORE0_PCHCTL_PSTATE0_SET_OFF (0x00 << 16) 654 #define CORE1_PCHMON_PACCEPT1_MON BIT(0) 655 #define CORE1_PCHMON_PDENY1_MON BIT(1) 656 #define CORE1_PCHCTL_PREQ1_SET BIT(0) 657 #define CORE1_PCHCTL_PSTATE1_SET_ON (0x08 << 16) 658 #define CORE1_PCHCTL_PSTATE1_SET_OFF_EMULATED (0x01 << 16) 659 #define CORE1_PCHCTL_PSTATE1_SET_OFF (0x00 << 16) 660 #define BUS_MSTOP_MSTOPMODE_SET BIT(0) 661 #define BUS_MSTOP_MSTOPMODE_SET_WEN BIT(16) 662 #define OTHERFUNC1_REG_RES0_SET BIT(0) 663 #define OTHERFUNC1_REG_RES0_ON_WEN BIT(16) 664 #define OTHERFUNC2_REG_RES0_SET BIT(0) 665 #define OTHERFUNC2_REG_RES0_ON_WEN BIT(16) 666 667 #define BIT0_ON BIT(0) 668 #define BIT1_ON BIT(1) 669 #define BIT2_ON BIT(2) 670 #define BIT3_ON BIT(3) 671 #define BIT4_ON BIT(4) 672 #define BIT5_ON BIT(5) 673 #define BIT6_ON BIT(6) 674 #define BIT7_ON BIT(7) 675 #define BIT8_ON BIT(8) 676 #define BIT9_ON BIT(9) 677 #define BIT10_ON BIT(10) 678 #define BIT11_ON BIT(11) 679 #define BIT12_ON BIT(12) 680 #define BIT13_ON BIT(13) 681 #define BIT14_ON BIT(14) 682 #define BIT15_ON BIT(15) 683 #define BIT16_ON BIT(16) 684 #define BIT17_ON BIT(17) 685 #define BIT18_ON BIT(18) 686 #define BIT19_ON BIT(19) 687 #define BIT20_ON BIT(20) 688 #define BIT21_ON BIT(21) 689 #define BIT22_ON BIT(22) 690 #define BIT23_ON BIT(23) 691 #define BIT24_ON BIT(24) 692 #define BIT25_ON BIT(25) 693 #define BIT26_ON BIT(26) 694 #define BIT27_ON BIT(27) 695 #define BIT28_ON BIT(28) 696 #define BIT29_ON BIT(29) 697 #define BIT30_ON BIT(30) 698 #define BIT31_ON BIT(31) 699 700 #endif /* __CPG_REGS_H__ */ 701