1 /* 2 * Copyright (c) 2021-2026, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A715_H 8 #define CORTEX_A715_H 9 10 #define CORTEX_A715_MIDR U(0x410FD4D0) 11 12 /* Cortex-A715 loop count for CVE-2022-23960 mitigation */ 13 #define CORTEX_A715_BHB_LOOP_COUNT U(38) 14 15 /******************************************************************************* 16 * CPU Register Mappings 17 ******************************************************************************/ 18 #define CORTEX_A715_CPUCFR_EL1 S3_0_C15_C0_0 19 #define CORTEX_A715_CPUACTLR_EL1 S3_0_C15_C1_0 20 #define CORTEX_A715_CPUACTLR2_EL1 S3_0_C15_C1_1 21 #define CORTEX_A715_CPUACTLR3_EL1 S3_0_C15_C1_2 22 #define CORTEX_A715_CPUACTLR4_EL1 S3_0_C15_C1_3 23 #define CORTEX_A715_CPUECTLR_EL1 S3_0_C15_C1_4 24 #define CORTEX_A715_CPUECTLR2_EL1 S3_0_C15_C1_5 25 #define CORTEX_A715_CPUPSELR_EL3 S3_6_C15_C8_0 26 #define CORTEX_A715_CPUPCR_EL3 S3_6_C15_C8_1 27 #define CORTEX_A715_CPUPOR_EL3 S3_6_C15_C8_2 28 #define CORTEX_A715_CPUPMR_EL3 S3_6_C15_C8_3 29 30 /******************************************************************************* 31 * CPU Power Control register specific definitions 32 ******************************************************************************/ 33 #define CORTEX_A715_CPUPWRCTLR_EL1 S3_0_C15_C2_7 34 #define CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 35 36 #ifndef __ASSEMBLER__ 37 long check_erratum_cortex_a715_3699560(long cpu_rev); 38 #endif /* __ASSEMBLER__ */ 39 40 #endif /* CORTEX_A715_H */ 41