1 /* 2 * Copyright (c) 2021-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <lib/utils_def.h> 12 #include <lib/xlat_tables/xlat_tables_defs.h> 13 #include <plat/arm/board/common/rotpk/rotpk_def.h> 14 #include <plat/arm/board/common/v2m_def.h> 15 #include <plat/arm/common/arm_spm_def.h> 16 #include <plat/arm/common/smccc_def.h> 17 #include <plat/common/common_def.h> 18 #include <plat/arm/soc/common/soc_css_def.h> 19 20 /* Special value used to verify platform parameters from BL2 to BL31 */ 21 #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) 22 23 /* PL011 UART related constants */ 24 #ifdef V2M_IOFPGA_UART0_CLK_IN_HZ 25 #undef V2M_IOFPGA_UART0_CLK_IN_HZ 26 #endif 27 28 #ifdef V2M_IOFPGA_UART1_CLK_IN_HZ 29 #undef V2M_IOFPGA_UART1_CLK_IN_HZ 30 #endif 31 32 #define V2M_IOFPGA_UART0_CLK_IN_HZ 50000000 33 #define V2M_IOFPGA_UART1_CLK_IN_HZ 50000000 34 35 /* Core/Cluster/Thread counts for corstone1000 */ 36 #define CORSTONE1000_CLUSTER_COUNT U(1) 37 #define CORSTONE1000_MAX_CPUS_PER_CLUSTER U(4) 38 #define CORSTONE1000_MAX_PE_PER_CPU U(1) 39 #define CORSTONE1000_PRIMARY_CPU U(0) 40 41 #define PLAT_ARM_CLUSTER_COUNT CORSTONE1000_CLUSTER_COUNT 42 43 #define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \ 44 CORSTONE1000_MAX_CPUS_PER_CLUSTER * \ 45 CORSTONE1000_MAX_PE_PER_CPU) 46 47 /* UART related constants */ 48 #define PLAT_ARM_BOOT_UART_BASE 0x1a510000 49 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 50 #define PLAT_ARM_RUN_UART_BASE 0x1a520000 51 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 52 #define ARM_CONSOLE_BAUDRATE 115200 53 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 54 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 55 56 /* Memory related constants */ 57 58 /* Memory mappings of where the BLs in the FIP are copied to 59 * 60 * <ARM_TRUSTED_SRAM_BASE> = 0x02000000 61 * partition size: sizeof(meminfo_t) = 16 bytes 62 * content: memory info area used by the next BL 63 * 64 * <ARM_FW_CONFIG_BASE> = 0x02000010 65 * partition size: 4080 bytes 66 * 67 * <ARM_BL2_MEM_DESC_BASE> = 0x02001000 68 * partition size: 4 KB 69 * content: Area where BL2 copies the images descriptors 70 * 71 * <ARM_BL_RAM_BASE> = <BL32_BASE> = 0x02002000 72 * partition size: 3752 KB 73 * content: BL32 (optee-os) 74 * 75 * <CORSTONE1000_TOS_FW_CONFIG_BASE> = 0x023AC000 76 * partition size: 8 KB 77 * content: BL32 config (TOS_FW_CONFIG) 78 * 79 * <BL31_BASE> = 0x023AE000 80 * partition size: 140 KB 81 * content: BL31 82 * 83 * <BL2_SIGNATURE_BASE> = 0x023D1000 84 * partition size: 4 KB 85 * content: MCUBOOT data needed to verify TF-A BL2 86 * 87 * <BL2_BASE> = 0x023D2000 88 * partition size: 176 KB 89 * content: BL2 90 * 91 * <BL33_BASE> = 0x80000000 92 * partition size: 12 MB 93 * content: BL33 (U-Boot) 94 */ 95 96 /* DDR memory */ 97 #define ARM_DRAM1_BASE UL(0x80000000) 98 #define ARM_DRAM1_SIZE (SZ_2G) /* 2GB*/ 99 #define ARM_DRAM1_END (ARM_DRAM1_BASE + ARM_DRAM1_SIZE - 1) 100 101 /* DRAM1 and DRAM2 are the same for corstone1000 */ 102 #define ARM_DRAM2_BASE ARM_DRAM1_BASE 103 #define ARM_DRAM2_SIZE ARM_DRAM1_SIZE 104 #define ARM_DRAM2_END ARM_DRAM1_END 105 106 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 107 #define ARM_NS_DRAM1_SIZE ARM_DRAM1_SIZE 108 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE - 1) 109 110 /* The first 8 KB of Trusted SRAM are used as shared memory */ 111 #define ARM_TRUSTED_SRAM_BASE UL(0x02000000) 112 #define ARM_SHARED_RAM_SIZE (SZ_8K) /* 8 KB */ 113 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 114 115 #ifdef CORSTONE1000_CORTEX_A320 116 #define TOTAL_SECURE_SRAM_SIZE (SZ_4M) 117 #define TOTAL_NONSECURE_SRAM_SIZE (SZ_4M) 118 #define PLAT_ARM_TRUSTED_SRAM_SIZE (TOTAL_SECURE_SRAM_SIZE - \ 119 ARM_SHARED_RAM_SIZE) 120 #else 121 /* The remaining Trusted SRAM is used to load the BL images */ 122 #define TOTAL_SRAM_SIZE (SZ_4M) /* 4 MB */ 123 124 125 #define PLAT_ARM_TRUSTED_SRAM_SIZE (TOTAL_SRAM_SIZE - \ 126 ARM_SHARED_RAM_SIZE) 127 #endif 128 129 #define PLAT_ARM_MAX_BL2_SIZE (180 * SZ_1K) /* 180 KB */ 130 131 #define PLAT_ARM_MAX_BL31_SIZE (140 * SZ_1K) /* 140 KB */ 132 133 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE) 134 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 135 ARM_SHARED_RAM_SIZE) 136 137 #define BL2_SIGNATURE_SIZE (SZ_4K) /* 4 KB */ 138 139 #define BL2_SIGNATURE_BASE (BL2_LIMIT - PLAT_ARM_MAX_BL2_SIZE) 140 #define BL2_BASE (BL2_LIMIT - \ 141 PLAT_ARM_MAX_BL2_SIZE + \ 142 BL2_SIGNATURE_SIZE) 143 #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 144 145 #define BL31_BASE (BL2_SIGNATURE_BASE - PLAT_ARM_MAX_BL31_SIZE) 146 #define BL31_LIMIT BL2_SIGNATURE_BASE 147 148 #define CORSTONE1000_TOS_FW_CONFIG_BASE (BL31_BASE - \ 149 CORSTONE1000_TOS_FW_CONFIG_SIZE) 150 #define CORSTONE1000_TOS_FW_CONFIG_SIZE (SZ_8K) /* 8 KB */ 151 #define CORSTONE1000_TOS_FW_CONFIG_LIMIT BL31_BASE 152 153 #define BL32_BASE ARM_BL_RAM_BASE 154 #define PLAT_ARM_MAX_BL32_SIZE (CORSTONE1000_TOS_FW_CONFIG_BASE - BL32_BASE) 155 156 #define BL32_LIMIT (BL32_BASE + PLAT_ARM_MAX_BL32_SIZE) 157 158 /* SPD_spmd settings */ 159 160 #define PLAT_ARM_SPMC_BASE BL32_BASE 161 #define PLAT_ARM_SPMC_SIZE PLAT_ARM_MAX_BL32_SIZE 162 163 /* NS memory */ 164 165 #define BL33_BASE ARM_DRAM1_BASE 166 #define PLAT_ARM_MAX_BL33_SIZE (12 * SZ_1M) /* 12 MB*/ 167 #define BL33_LIMIT (ARM_DRAM1_BASE + PLAT_ARM_MAX_BL33_SIZE) 168 169 /* end of the definition of SRAM memory layout */ 170 171 /* NOR Flash */ 172 173 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 174 #define PLAT_ARM_NVM_SIZE (SZ_32M) /* 32 MB */ 175 #define PLAT_ARM_FIP_MAX_SIZE UL(0x1ff000) /* 1.996 MB */ 176 #define PLAT_ARM_FLASH_IMAGE_BASE UL(0x08000000) 177 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE PLAT_ARM_FIP_MAX_SIZE 178 179 /* FIP Information */ 180 #define FIP_SIGNATURE_AREA_SIZE (0x1000) /* 4 KB */ 181 182 /* 183 * Some data must be aligned on the biggest cache line size in the platform. 184 * This is known only to the platform as it might have a combination of 185 * integrated and external caches. 186 */ 187 #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) 188 #define ARM_CACHE_WRITEBACK_SHIFT 6 189 190 /* 191 * Define FW_CONFIG area base and limit. Leave enough space for BL2 meminfo. 192 * FW_CONFIG is intended to host the device tree. Currently, This area is not 193 * used because corstone1000 platform doesn't use a device tree at TF-A level. 194 */ 195 #define ARM_FW_CONFIG_BASE (ARM_SHARED_RAM_BASE + sizeof(meminfo_t)) 196 #define ARM_FW_CONFIG_LIMIT (ARM_SHARED_RAM_BASE + \ 197 (ARM_SHARED_RAM_SIZE >> 1)) 198 199 /* 200 * Boot parameters passed from BL2 to BL31/BL32 are stored here 201 */ 202 #define ARM_BL2_MEM_DESC_BASE ARM_FW_CONFIG_LIMIT 203 #define ARM_BL2_MEM_DESC_LIMIT ARM_BL_RAM_BASE 204 205 /* 206 * The max number of regions like RO(code), coherent and data required by 207 * different BL stages which need to be mapped in the MMU. 208 */ 209 #define ARM_BL_REGIONS 3 210 #define PLAT_ARM_MMAP_ENTRIES 8 211 #define MAX_XLAT_TABLES 5 212 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) 213 #define MAX_IO_DEVICES 2 214 #define MAX_IO_HANDLES 3 215 #define MAX_IO_BLOCK_DEVICES 1 216 217 /* GIC related constants */ 218 #ifdef CORSTONE1000_CORTEX_A320 219 #define PLAT_ARM_GICD_BASE 0x1C000000 220 #define PLAT_ARM_GICR_BASE 0x1C040000 221 #else 222 #define PLAT_ARM_GICD_BASE 0x1C010000 223 #define PLAT_ARM_GICC_BASE 0x1C02F000 224 #endif 225 226 /* MHUv2 Secure Channel receiver and sender */ 227 #define PLAT_SDK700_MHU0_SEND 0x1B800000 228 #define PLAT_SDK700_MHU0_RECV 0x1B810000 229 230 /* Timer/watchdog related constants */ 231 #define ARM_SYS_CNTCTL_BASE UL(0x1a200000) 232 #define ARM_SYS_CNTREAD_BASE UL(0x1a210000) 233 #define ARM_SYS_TIMCTL_BASE UL(0x1a220000) 234 235 #define SECURE_WATCHDOG_ADDR_CTRL_REG 0x1A320000 236 #define SECURE_WATCHDOG_ADDR_VAL_REG 0x1A320008 237 #define SECURE_WATCHDOG_MASK_ENABLE 0x01 238 #define SECURE_WATCHDOG_COUNTDOWN_VAL 0x1000 239 240 #define SYS_COUNTER_FREQ_IN_TICKS UL(50000000) /* 50MHz */ 241 242 #define CORSTONE1000_IRQ_TZ_WDOG 32 243 #define CORSTONE1000_IRQ_SEC_SYS_TIMER 34 244 245 #define PLAT_MAX_PWR_LVL 2 246 /* 247 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 248 * power levels have a 1:1 mapping with the MPIDR affinity levels. 249 */ 250 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 251 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 252 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 253 254 /* 255 * Macros for local power states in ARM platforms encoded by State-ID field 256 * within the power-state parameter. 257 */ 258 /* Local power state for power domains in Run state. */ 259 #define ARM_LOCAL_STATE_RUN U(0) 260 /* Local power state for retention. Valid only for CPU power domains */ 261 #define ARM_LOCAL_STATE_RET U(1) 262 /* Local power state for OFF/power-down. Valid for CPU and cluster 263 * power domains 264 */ 265 #define ARM_LOCAL_STATE_OFF U(2) 266 267 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 268 269 #if defined(CORSTONE1000_FVP_MULTICORE) 270 /* The secondary core entrypoint address points to bl31_warm_entrypoint 271 * and the address size is 8 bytes */ 272 #define CORSTONE1000_SECONDARY_CORE_ENTRYPOINT_ADDRESS_SIZE UL(0x8) 273 274 #define CORSTONE1000_SECONDARY_CORE_HOLD_BASE (PLAT_ARM_TRUSTED_MAILBOX_BASE + \ 275 CORSTONE1000_SECONDARY_CORE_ENTRYPOINT_ADDRESS_SIZE) 276 #define CORSTONE1000_SECONDARY_CORE_STATE_WAIT ULL(0) 277 #define CORSTONE1000_SECONDARY_CORE_STATE_GO ULL(1) 278 #define CORSTONE1000_SECONDARY_CORE_HOLD_SHIFT ULL(3) 279 #endif 280 281 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 282 283 #define PLAT_ARM_NS_IMAGE_BASE (BL33_BASE) 284 285 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 286 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 287 288 /* 289 * This macro defines the deepest retention state possible. A higher state 290 * ID will represent an invalid or a power down state. 291 */ 292 #define PLAT_MAX_RET_STATE 1 293 294 /* 295 * This macro defines the deepest power down states possible. Any state ID 296 * higher than this is invalid. 297 */ 298 #define PLAT_MAX_OFF_STATE 2 299 300 #define PLATFORM_STACK_SIZE UL(0x440) 301 302 #define CORSTONE1000_EXTERNAL_FLASH MAP_REGION_FLAT( \ 303 PLAT_ARM_NVM_BASE, \ 304 PLAT_ARM_NVM_SIZE, \ 305 MT_DEVICE | MT_RO | MT_SECURE) 306 307 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 308 ARM_SHARED_RAM_BASE, \ 309 ARM_SHARED_RAM_SIZE, \ 310 MT_MEMORY | MT_RW | MT_SECURE) 311 312 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 313 ARM_NS_DRAM1_BASE, \ 314 ARM_NS_DRAM1_SIZE, \ 315 MT_MEMORY | MT_RW | MT_NS) 316 317 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 318 BL_CODE_BASE, \ 319 (BL_CODE_END - BL_CODE_BASE), \ 320 MT_CODE | MT_SECURE), \ 321 MAP_REGION_FLAT( \ 322 BL_RO_DATA_BASE, \ 323 (BL_RO_DATA_END - BL_RO_DATA_BASE), \ 324 MT_RO_DATA | MT_SECURE) 325 #if USE_COHERENT_MEM 326 #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 327 BL_COHERENT_RAM_BASE, \ 328 (BL_COHERENT_RAM_END \ 329 - BL_COHERENT_RAM_BASE), \ 330 MT_DEVICE | MT_RW | MT_SECURE) 331 #endif 332 333 /* 334 * Map the region for the optional device tree configuration with read and 335 * write permissions 336 */ 337 #define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT( \ 338 ARM_FW_CONFIG_BASE, \ 339 (ARM_FW_CONFIG_LIMIT \ 340 - ARM_FW_CONFIG_BASE), \ 341 MT_MEMORY | MT_RW | MT_SECURE) 342 343 #define CORSTONE1000_DEVICE_BASE (0x1A000000) 344 #define CORSTONE1000_DEVICE_SIZE (0x26000000) 345 #define CORSTONE1000_MAP_DEVICE MAP_REGION_FLAT( \ 346 CORSTONE1000_DEVICE_BASE, \ 347 CORSTONE1000_DEVICE_SIZE, \ 348 MT_DEVICE | MT_RW | MT_SECURE) 349 #ifdef CORSTONE1000_CORTEX_A320 350 #define ARM_ETHOS_U85_BASE UL(0x1A050000) 351 #define ARM_ETHOS_U85_SIZE UL(0x4000) 352 #define ARM_MAP_ETHOS_U85 MAP_REGION_FLAT( \ 353 ARM_ETHOS_U85_BASE, \ 354 ARM_ETHOS_U85_SIZE, \ 355 MT_DEVICE | MT_RW | MT_NS) 356 357 #define ARM_NONSECURE_SRAM_BASE (ARM_TRUSTED_SRAM_BASE + TOTAL_SECURE_SRAM_SIZE) 358 #define ARM_MAP_NONSECURE_SRAM MAP_REGION_FLAT( \ 359 ARM_NONSECURE_SRAM_BASE, \ 360 TOTAL_NONSECURE_SRAM_SIZE, \ 361 MT_MEMORY | MT_RW | MT_NS) 362 #endif 363 364 #define ARM_IRQ_SEC_PHY_TIMER 29 365 366 #define ARM_IRQ_SEC_SGI_0 8 367 #define ARM_IRQ_SEC_SGI_1 9 368 #define ARM_IRQ_SEC_SGI_2 10 369 #define ARM_IRQ_SEC_SGI_3 11 370 #define ARM_IRQ_SEC_SGI_4 12 371 #define ARM_IRQ_SEC_SGI_5 13 372 #define ARM_IRQ_SEC_SGI_6 14 373 #define ARM_IRQ_SEC_SGI_7 15 374 375 /* 376 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 377 * terminology. On a GICv2 system or mode, the lists will be merged and treated 378 * as Group 0 interrupts. 379 */ 380 #define ARM_G1S_IRQ_PROPS(grp) \ 381 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ 382 (grp), GIC_INTR_CFG_LEVEL), \ 383 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ 384 (grp), GIC_INTR_CFG_EDGE), \ 385 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ 386 (grp), GIC_INTR_CFG_EDGE), \ 387 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ 388 (grp), GIC_INTR_CFG_EDGE), \ 389 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ 390 (grp), GIC_INTR_CFG_EDGE), \ 391 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ 392 (grp), GIC_INTR_CFG_EDGE), \ 393 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ 394 (grp), GIC_INTR_CFG_EDGE) 395 396 #define ARM_G0_IRQ_PROPS(grp) \ 397 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 398 GIC_INTR_CFG_EDGE) 399 400 /* 401 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 402 * terminology. On a GICv2 system or mode, the lists will be merged and treated 403 * as Group 0 interrupts. 404 */ 405 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 406 ARM_G1S_IRQ_PROPS(grp), \ 407 INTR_PROP_DESC(CORSTONE1000_IRQ_TZ_WDOG, \ 408 GIC_HIGHEST_SEC_PRIORITY, \ 409 (grp), GIC_INTR_CFG_LEVEL), \ 410 INTR_PROP_DESC(CORSTONE1000_IRQ_SEC_SYS_TIMER, \ 411 GIC_HIGHEST_SEC_PRIORITY, \ 412 (grp), GIC_INTR_CFG_LEVEL) 413 414 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 415 416 #endif /* PLATFORM_DEF_H */ 417