1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * QorIQ P1 Tower boards configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #if defined(CONFIG_TWR_P1025) 14 #define CONFIG_BOARDNAME "TWR-P1025" 15 #define CONFIG_PHY_ATHEROS 16 #define CONFIG_QE 17 #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Conversion of LBC addr */ 18 #define CONFIG_SYS_LBC_LCRR 0x80000002 /* LB clock ratio reg */ 19 #endif 20 21 #ifdef CONFIG_SDCARD 22 #define CONFIG_RAMBOOT_SDCARD 23 #define CONFIG_SYS_RAMBOOT 24 #define CONFIG_SYS_EXTRA_ENV_RELOC 25 #define CONFIG_SYS_TEXT_BASE 0x11000000 26 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 27 #endif 28 29 #ifndef CONFIG_SYS_TEXT_BASE 30 #define CONFIG_SYS_TEXT_BASE 0xeff40000 31 #endif 32 33 #ifndef CONFIG_RESET_VECTOR_ADDRESS 34 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 35 #endif 36 37 #ifndef CONFIG_SYS_MONITOR_BASE 38 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 39 #endif 40 41 #define CONFIG_MP 42 43 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 44 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 45 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 46 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 47 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 48 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 49 50 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 51 #define CONFIG_ENV_OVERWRITE 52 53 #define CONFIG_SATA_SIL3114 54 #define CONFIG_SYS_SATA_MAX_DEVICE 2 55 #define CONFIG_LIBATA 56 #define CONFIG_LBA48 57 58 #ifndef __ASSEMBLY__ 59 extern unsigned long get_board_sys_clk(unsigned long dummy); 60 #endif 61 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for TWR-P1025 */ 62 63 #define CONFIG_DDR_CLK_FREQ 66666666 64 65 #define CONFIG_HWCONFIG 66 /* 67 * These can be toggled for performance analysis, otherwise use default. 68 */ 69 #define CONFIG_L2_CACHE 70 #define CONFIG_BTB 71 72 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 73 #define CONFIG_SYS_MEMTEST_END 0x1fffffff 74 75 #define CONFIG_SYS_CCSRBAR 0xffe00000 76 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 77 78 /* DDR Setup */ 79 80 #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M 81 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 82 83 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) 84 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 85 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 86 87 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 88 89 /* Default settings for DDR3 */ 90 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f 91 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 92 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 93 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 94 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 95 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 96 97 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 98 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 99 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 100 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 101 102 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 103 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655a608 104 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 105 #define CONFIG_SYS_DDR_RCW_1 0x00000000 106 #define CONFIG_SYS_DDR_RCW_2 0x00000000 107 #define CONFIG_SYS_DDR_CONTROL 0xc70c0000 /* Type = DDR3 */ 108 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050 109 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 110 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 111 112 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 113 #define CONFIG_SYS_DDR_TIMING_0 0x00220004 114 #define CONFIG_SYS_DDR_TIMING_1 0x5c5b6544 115 #define CONFIG_SYS_DDR_TIMING_2 0x0fa880de 116 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 117 #define CONFIG_SYS_DDR_MODE_1 0x80461320 118 #define CONFIG_SYS_DDR_MODE_2 0x00008000 119 #define CONFIG_SYS_DDR_INTERVAL 0x09480000 120 121 /* 122 * Memory map 123 * 124 * 0x0000_0000 0x1fff_ffff DDR Up to 512MB cacheable 125 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) 126 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 127 * 128 * Localbus 129 * 0xe000_0000 0xe002_0000 SSD1289 128K non-cacheable 130 * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable 131 * 132 * 0xff90_0000 0xff97_ffff L2 SRAM Up to 512K cacheable 133 * 0xffd0_0000 0xffd0_3fff init ram 16K Cacheable 134 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 135 */ 136 137 /* 138 * Local Bus Definitions 139 */ 140 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 141 #define CONFIG_SYS_FLASH_BASE 0xec000000 142 143 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 144 145 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \ 146 | BR_PS_16 | BR_V) 147 148 #define CONFIG_FLASH_OR_PRELIM 0xfc0000b1 149 150 #define CONFIG_SYS_SSD_BASE 0xe0000000 151 #define CONFIG_SYS_SSD_BASE_PHYS CONFIG_SYS_SSD_BASE 152 #define CONFIG_SSD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \ 153 BR_PS_16 | BR_V) 154 #define CONFIG_SSD_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ 155 OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \ 156 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) 157 158 #define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM 159 #define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM 160 161 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 162 #define CONFIG_SYS_FLASH_QUIET_TEST 163 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 164 165 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 166 167 #undef CONFIG_SYS_FLASH_CHECKSUM 168 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 169 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 170 171 #define CONFIG_FLASH_CFI_DRIVER 172 #define CONFIG_SYS_FLASH_CFI 173 #define CONFIG_SYS_FLASH_EMPTY_INFO 174 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 175 176 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 177 178 #define CONFIG_SYS_INIT_RAM_LOCK 179 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 180 /* Initial L1 address */ 181 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR 182 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 183 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 184 /* Size of used area in RAM */ 185 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 186 187 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 188 GENERATED_GBL_DATA_SIZE) 189 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 190 191 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 192 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ 193 194 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 195 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 196 197 /* Serial Port 198 * open - index 2 199 * shorted - index 1 200 */ 201 #define CONFIG_CONS_INDEX 1 202 #undef CONFIG_SERIAL_SOFTWARE_FIFO 203 #define CONFIG_SYS_NS16550_SERIAL 204 #define CONFIG_SYS_NS16550_REG_SIZE 1 205 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 206 207 #define CONFIG_SYS_BAUDRATE_TABLE \ 208 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 209 210 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 211 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 212 213 /* I2C */ 214 #define CONFIG_SYS_I2C 215 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 216 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C spd and slave address */ 217 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 218 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 219 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 220 221 /* 222 * I2C2 EEPROM 223 */ 224 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C spd and slave address */ 225 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 226 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 227 228 #define CONFIG_SYS_I2C_PCA9555_ADDR 0x23 229 230 /* enable read and write access to EEPROM */ 231 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 232 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 233 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 234 235 /* 236 * eSPI - Enhanced SPI 237 */ 238 #define CONFIG_HARD_SPI 239 240 #if defined(CONFIG_PCI) 241 /* 242 * General PCI 243 * Memory space is mapped 1-1, but I/O space must start from 0. 244 */ 245 246 /* controller 2, direct to uli, tgtid 2, Base address 9000 */ 247 #define CONFIG_SYS_PCIE2_NAME "TWR-ELEV PCIe SLOT" 248 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 249 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 250 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 251 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 252 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 253 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 254 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 255 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 256 257 /* controller 1, tgtid 1, Base address a000 */ 258 #define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" 259 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 260 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 261 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 262 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 263 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 264 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 265 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 266 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 267 268 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 269 #endif /* CONFIG_PCI */ 270 271 #if defined(CONFIG_TSEC_ENET) 272 273 #define CONFIG_MII /* MII PHY management */ 274 #define CONFIG_TSEC1 275 #define CONFIG_TSEC1_NAME "eTSEC1" 276 #undef CONFIG_TSEC2 277 #undef CONFIG_TSEC2_NAME 278 #define CONFIG_TSEC3 279 #define CONFIG_TSEC3_NAME "eTSEC3" 280 281 #define TSEC1_PHY_ADDR 2 282 #define TSEC2_PHY_ADDR 0 283 #define TSEC3_PHY_ADDR 1 284 285 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 286 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 287 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 288 289 #define TSEC1_PHYIDX 0 290 #define TSEC2_PHYIDX 0 291 #define TSEC3_PHYIDX 0 292 293 #define CONFIG_ETHPRIME "eTSEC1" 294 295 #define CONFIG_HAS_ETH0 296 #define CONFIG_HAS_ETH1 297 #undef CONFIG_HAS_ETH2 298 #endif /* CONFIG_TSEC_ENET */ 299 300 #ifdef CONFIG_QE 301 /* QE microcode/firmware address */ 302 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 303 #define CONFIG_SYS_QE_FW_ADDR 0xefec0000 304 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 305 #endif /* CONFIG_QE */ 306 307 #ifdef CONFIG_TWR_P1025 308 /* 309 * QE UEC ethernet configuration 310 */ 311 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 312 313 #undef CONFIG_UEC_ETH 314 #define CONFIG_PHY_MODE_NEED_CHANGE 315 316 #define CONFIG_UEC_ETH1 /* ETH1 */ 317 #define CONFIG_HAS_ETH0 318 319 #ifdef CONFIG_UEC_ETH1 320 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 321 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ 322 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ 323 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 324 #define CONFIG_SYS_UEC1_PHY_ADDR 0x18 /* 0x18 for MII */ 325 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII 326 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 327 #endif /* CONFIG_UEC_ETH1 */ 328 329 #define CONFIG_UEC_ETH5 /* ETH5 */ 330 #define CONFIG_HAS_ETH1 331 332 #ifdef CONFIG_UEC_ETH5 333 #define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ 334 #define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE 335 #define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ 336 #define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH 337 #define CONFIG_SYS_UEC5_PHY_ADDR 0x19 /* 0x19 for RMII */ 338 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 339 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 340 #endif /* CONFIG_UEC_ETH5 */ 341 #endif /* CONFIG_TWR-P1025 */ 342 343 /* 344 * Dynamic MTD Partition support with mtdparts 345 */ 346 #define CONFIG_FLASH_CFI_MTD 347 #define MTDIDS_DEFAULT "nor0=ec000000.nor" 348 #define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:256k(vsc7385-firmware)," \ 349 "256k(dtb),5632k(kernel),57856k(fs)," \ 350 "256k(qe-ucode-firmware),1280k(u-boot)" 351 352 /* 353 * Environment 354 */ 355 #ifdef CONFIG_SYS_RAMBOOT 356 #ifdef CONFIG_RAMBOOT_SDCARD 357 #define CONFIG_ENV_SIZE 0x2000 358 #define CONFIG_SYS_MMC_ENV_DEV 0 359 #else 360 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 361 #define CONFIG_ENV_SIZE 0x2000 362 #endif 363 #else 364 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 365 #define CONFIG_ENV_SIZE 0x2000 366 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 367 #endif 368 369 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 370 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 371 372 /* 373 * USB 374 */ 375 #define CONFIG_HAS_FSL_DR_USB 376 377 #if defined(CONFIG_HAS_FSL_DR_USB) 378 #ifdef CONFIG_USB_EHCI_HCD 379 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 380 #define CONFIG_USB_EHCI_FSL 381 #endif 382 #endif 383 384 #ifdef CONFIG_MMC 385 #define CONFIG_FSL_ESDHC 386 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 387 #endif 388 389 #undef CONFIG_WATCHDOG /* watchdog disabled */ 390 391 /* 392 * Miscellaneous configurable options 393 */ 394 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 395 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 396 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 397 398 /* 399 * For booting Linux, the board info and command line data 400 * have to be in the first 64 MB of memory, since this is 401 * the maximum mapped by the Linux kernel during initialization. 402 */ 403 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ 404 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 405 406 /* 407 * Environment Configuration 408 */ 409 #define CONFIG_HOSTNAME unknown 410 #define CONFIG_ROOTPATH "/opt/nfsroot" 411 #define CONFIG_BOOTFILE "uImage" 412 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 413 414 /* default location for tftp and bootm */ 415 #define CONFIG_LOADADDR 1000000 416 417 #define CONFIG_EXTRA_ENV_SETTINGS \ 418 "netdev=eth0\0" \ 419 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 420 "loadaddr=1000000\0" \ 421 "bootfile=uImage\0" \ 422 "dtbfile=twr-p1025twr.dtb\0" \ 423 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 424 "qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0" \ 425 "tftpflash=tftpboot $loadaddr $uboot; " \ 426 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 427 "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 428 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 429 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 430 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 431 "kernelflash=tftpboot $loadaddr $bootfile; " \ 432 "protect off 0xefa80000 +$filesize; " \ 433 "erase 0xefa80000 +$filesize; " \ 434 "cp.b $loadaddr 0xefa80000 $filesize; " \ 435 "protect on 0xefa80000 +$filesize; " \ 436 "cmp.b $loadaddr 0xefa80000 $filesize\0" \ 437 "dtbflash=tftpboot $loadaddr $dtbfile; " \ 438 "protect off 0xefe80000 +$filesize; " \ 439 "erase 0xefe80000 +$filesize; " \ 440 "cp.b $loadaddr 0xefe80000 $filesize; " \ 441 "protect on 0xefe80000 +$filesize; " \ 442 "cmp.b $loadaddr 0xefe80000 $filesize\0" \ 443 "ramdiskflash=tftpboot $loadaddr $ramdiskfile; " \ 444 "protect off 0xeeb80000 +$filesize; " \ 445 "erase 0xeeb80000 +$filesize; " \ 446 "cp.b $loadaddr 0xeeb80000 $filesize; " \ 447 "protect on 0xeeb80000 +$filesize; " \ 448 "cmp.b $loadaddr 0xeeb80000 $filesize\0" \ 449 "qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; " \ 450 "protect off 0xefec0000 +$filesize; " \ 451 "erase 0xefec0000 +$filesize; " \ 452 "cp.b $loadaddr 0xefec0000 $filesize; " \ 453 "protect on 0xefec0000 +$filesize; " \ 454 "cmp.b $loadaddr 0xefec0000 $filesize\0" \ 455 "consoledev=ttyS0\0" \ 456 "ramdiskaddr=2000000\0" \ 457 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 458 "fdtaddr=1e00000\0" \ 459 "bdev=sda1\0" \ 460 "norbootaddr=ef080000\0" \ 461 "norfdtaddr=ef040000\0" \ 462 "ramdisk_size=120000\0" \ 463 "usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \ 464 "console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000" 465 466 #define CONFIG_NFSBOOTCOMMAND \ 467 "setenv bootargs root=/dev/nfs rw " \ 468 "nfsroot=$serverip:$rootpath " \ 469 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 470 "console=$consoledev,$baudrate $othbootargs;" \ 471 "tftp $loadaddr $bootfile&&" \ 472 "tftp $fdtaddr $fdtfile&&" \ 473 "bootm $loadaddr - $fdtaddr" 474 475 #define CONFIG_HDBOOT \ 476 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 477 "console=$consoledev,$baudrate $othbootargs;" \ 478 "usb start;" \ 479 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 480 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 481 "bootm $loadaddr - $fdtaddr" 482 483 #define CONFIG_USB_FAT_BOOT \ 484 "setenv bootargs root=/dev/ram rw " \ 485 "console=$consoledev,$baudrate $othbootargs " \ 486 "ramdisk_size=$ramdisk_size;" \ 487 "usb start;" \ 488 "fatload usb 0:2 $loadaddr $bootfile;" \ 489 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 490 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 491 "bootm $loadaddr $ramdiskaddr $fdtaddr" 492 493 #define CONFIG_USB_EXT2_BOOT \ 494 "setenv bootargs root=/dev/ram rw " \ 495 "console=$consoledev,$baudrate $othbootargs " \ 496 "ramdisk_size=$ramdisk_size;" \ 497 "usb start;" \ 498 "ext2load usb 0:4 $loadaddr $bootfile;" \ 499 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 500 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 501 "bootm $loadaddr $ramdiskaddr $fdtaddr" 502 503 #define CONFIG_NORBOOT \ 504 "setenv bootargs root=/dev/mtdblock3 rw " \ 505 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ 506 "bootm $norbootaddr - $norfdtaddr" 507 508 #define CONFIG_RAMBOOTCOMMAND_TFTP \ 509 "setenv bootargs root=/dev/ram rw " \ 510 "console=$consoledev,$baudrate $othbootargs " \ 511 "ramdisk_size=$ramdisk_size;" \ 512 "tftp $ramdiskaddr $ramdiskfile;" \ 513 "tftp $loadaddr $bootfile;" \ 514 "tftp $fdtaddr $fdtfile;" \ 515 "bootm $loadaddr $ramdiskaddr $fdtaddr" 516 517 #define CONFIG_RAMBOOTCOMMAND \ 518 "setenv bootargs root=/dev/ram rw " \ 519 "console=$consoledev,$baudrate $othbootargs " \ 520 "ramdisk_size=$ramdisk_size;" \ 521 "bootm 0xefa80000 0xeeb80000 0xefe80000" 522 523 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 524 525 #endif /* __CONFIG_H */ 526