1# 2# Multifunction miscellaneous devices 3# 4 5menu "Multifunction device drivers" 6 7config MISC 8 bool "Enable Driver Model for Misc drivers" 9 depends on DM 10 help 11 Enable driver model for miscellaneous devices. This class is 12 used only for those do not fit other more general classes. A 13 set of generic read, write and ioctl methods may be used to 14 access the device. 15 16config SPL_MISC 17 bool "Enable Driver Model for Misc drivers in SPL" 18 depends on SPL_DM 19 help 20 Enable driver model for miscellaneous devices. This class is 21 used only for those do not fit other more general classes. A 22 set of generic read, write and ioctl methods may be used to 23 access the device. 24 25config TPL_MISC 26 bool "Enable Driver Model for Misc drivers in TPL" 27 depends on TPL_DM 28 help 29 Enable driver model for miscellaneous devices. This class is 30 used only for those do not fit other more general classes. A 31 set of generic read, write and ioctl methods may be used to 32 access the device. 33 34config MISC_DECOMPRESS 35 bool "Enable misc decompress driver support" 36 depends on MISC 37 help 38 Enable misc decompress driver support. 39 40config SPL_MISC_DECOMPRESS 41 bool "Enable misc decompress driver support in SPL" 42 depends on SPL_MISC 43 help 44 Enable misc decompress driver support in spl. 45 46config ALTERA_SYSID 47 bool "Altera Sysid support" 48 depends on MISC 49 help 50 Select this to enable a sysid for Altera devices. Please find 51 details on the "Embedded Peripherals IP User Guide" of Altera. 52 53config ATSHA204A 54 bool "Support for Atmel ATSHA204A module" 55 depends on MISC 56 help 57 Enable support for I2C connected Atmel's ATSHA204A 58 CryptoAuthentication module found for example on the Turris Omnia 59 board. 60 61config ROCKCHIP_EFUSE 62 bool "Rockchip e-fuse support" 63 depends on MISC 64 help 65 Enable (read-only) access for the e-fuse block found in Rockchip 66 SoCs: accesses can either be made using byte addressing and a length 67 or through child-nodes that are generated based on the e-fuse map 68 retrieved from the DTS. 69 70 This driver currently supports the RK3399 only, but can easily be 71 extended (by porting the read function from the Linux kernel sources) 72 to support other recent Rockchip devices. 73 74config ROCKCHIP_OTP 75 bool "Rockchip OTP Support" 76 depends on MISC 77 help 78 This is a simple drive to dump specified values of Rockchip SoC 79 from otp, such as cpu-leakage. 80 81config ROCKCHIP_HW_DECOMPRESS 82 bool "Rockchip HardWare Decompress Support" 83 depends on MISC_DECOMPRESS 84 help 85 This driver support Decompress IP built-in Rockchip SoC, support 86 LZ4, GZIP, PNG, ZLIB. 87 88config SPL_ROCKCHIP_HW_DECOMPRESS 89 bool "Rockchip HardWare Decompress Support" 90 depends on SPL_MISC_DECOMPRESS 91 help 92 This driver support Decompress IP built-in Rockchip SoC, support 93 LZ4, GZIP, PNG, ZLIB. 94 95config ROCKCHIP_SECURE_OTP 96 bool "Rockchip Secure OTP Support" 97 depends on MISC && !OPTEE_CLIENT 98 help 99 Support read & write secure otp. 100 101config SPL_ROCKCHIP_SECURE_OTP 102 bool "Rockchip Secure OTP Support in spl" 103 depends on SPL_MISC 104 help 105 Support read & write secure otp in spl. 106 107config CMD_CROS_EC 108 bool "Enable crosec command" 109 depends on CROS_EC 110 help 111 Enable command-line access to the Chrome OS EC (Embedded 112 Controller). This provides the 'crosec' command which has 113 a number of sub-commands for performing EC tasks such as 114 updating its flash, accessing a small saved context area 115 and talking to the I2C bus behind the EC (if there is one). 116 117config CROS_EC 118 bool "Enable Chrome OS EC" 119 help 120 Enable access to the Chrome OS EC. This is a separate 121 microcontroller typically available on a SPI bus on Chromebooks. It 122 provides access to the keyboard, some internal storage and may 123 control access to the battery and main PMIC depending on the 124 device. You can use the 'crosec' command to access it. 125 126config CROS_EC_I2C 127 bool "Enable Chrome OS EC I2C driver" 128 depends on CROS_EC 129 help 130 Enable I2C access to the Chrome OS EC. This is used on older 131 ARM Chromebooks such as snow and spring before the standard bus 132 changed to SPI. The EC will accept commands across the I2C using 133 a special message protocol, and provide responses. 134 135config CROS_EC_LPC 136 bool "Enable Chrome OS EC LPC driver" 137 depends on CROS_EC 138 help 139 Enable I2C access to the Chrome OS EC. This is used on x86 140 Chromebooks such as link and falco. The keyboard is provided 141 through a legacy port interface, so on x86 machines the main 142 function of the EC is power and thermal management. 143 144config CROS_EC_SANDBOX 145 bool "Enable Chrome OS EC sandbox driver" 146 depends on CROS_EC && SANDBOX 147 help 148 Enable a sandbox emulation of the Chrome OS EC. This supports 149 keyboard (use the -l flag to enable the LCD), verified boot context, 150 EC flash read/write/erase support and a few other things. It is 151 enough to perform a Chrome OS verified boot on sandbox. 152 153config CROS_EC_SPI 154 bool "Enable Chrome OS EC SPI driver" 155 depends on CROS_EC 156 help 157 Enable SPI access to the Chrome OS EC. This is used on newer 158 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface 159 provides a faster and more robust interface than I2C but the bugs 160 are less interesting. 161 162config DS4510 163 bool "Enable support for DS4510 CPU supervisor" 164 help 165 Enable support for the Maxim DS4510 CPU supervisor. It has an 166 integrated 64-byte EEPROM, four programmable non-volatile I/O pins 167 and a configurable timer for the supervisor function. The device is 168 connected over I2C. 169 170config FSL_SEC_MON 171 bool "Enable FSL SEC_MON Driver" 172 help 173 Freescale Security Monitor block is responsible for monitoring 174 system states. 175 Security Monitor can be transitioned on any security failures, 176 like software violations or hardware security violations. 177 178config MXC_OCOTP 179 bool "Enable MXC OCOTP Driver" 180 help 181 If you say Y here, you will get support for the One Time 182 Programmable memory pages that are stored on the some 183 Freescale i.MX processors. 184 185config NUVOTON_NCT6102D 186 bool "Enable Nuvoton NCT6102D Super I/O driver" 187 help 188 If you say Y here, you will get support for the Nuvoton 189 NCT6102D Super I/O driver. This can be used to enable or 190 disable the legacy UART, the watchdog or other devices 191 in the Nuvoton Super IO chips on X86 platforms. 192 193config PWRSEQ 194 bool "Enable power-sequencing drivers" 195 depends on DM 196 help 197 Power-sequencing drivers provide support for controlling power for 198 devices. They are typically referenced by a phandle from another 199 device. When the device is started up, its power sequence can be 200 initiated. 201 202config SPL_PWRSEQ 203 bool "Enable power-sequencing drivers for SPL" 204 depends on PWRSEQ 205 help 206 Power-sequencing drivers provide support for controlling power for 207 devices. They are typically referenced by a phandle from another 208 device. When the device is started up, its power sequence can be 209 initiated. 210 211config PCA9551_LED 212 bool "Enable PCA9551 LED driver" 213 help 214 Enable driver for PCA9551 LED controller. This controller 215 is connected via I2C. So I2C needs to be enabled. 216 217config PCA9551_I2C_ADDR 218 hex "I2C address of PCA9551 LED controller" 219 depends on PCA9551_LED 220 default 0x60 221 help 222 The I2C address of the PCA9551 LED controller. 223 224config TEGRA_CAR 225 bool "Enable support for the Tegra CAR driver" 226 depends on TEGRA_NO_BPMP 227 help 228 The Tegra CAR (Clock and Reset Controller) is a HW module that 229 controls almost all clocks and resets in a Tegra SoC. 230 231config TEGRA186_BPMP 232 bool "Enable support for the Tegra186 BPMP driver" 233 depends on TEGRA186 234 help 235 The Tegra BPMP (Boot and Power Management Processor) is a separate 236 auxiliary CPU embedded into Tegra to perform power management work, 237 and controls related features such as clocks, resets, power domains, 238 PMIC I2C bus, etc. This driver provides the core low-level 239 communication path by which feature-specific drivers (such as clock) 240 can make requests to the BPMP. This driver is similar to an MFD 241 driver in the Linux kernel. 242 243config WINBOND_W83627 244 bool "Enable Winbond Super I/O driver" 245 help 246 If you say Y here, you will get support for the Winbond 247 W83627 Super I/O driver. This can be used to enable the 248 legacy UART or other devices in the Winbond Super IO chips 249 on X86 platforms. 250 251config QFW 252 bool 253 help 254 Hidden option to enable QEMU fw_cfg interface. This will be selected by 255 either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. 256 257config I2C_EEPROM 258 bool "Enable driver for generic I2C-attached EEPROMs" 259 depends on MISC 260 help 261 Enable a generic driver for EEPROMs attached via I2C. 262 263if I2C_EEPROM 264 265config SYS_I2C_EEPROM_ADDR 266 hex "Chip address of the EEPROM device" 267 default 0 268 269config SYS_I2C_EEPROM_BUS 270 int "I2C bus of the EEPROM device." 271 default 0 272 273config SYS_EEPROM_SIZE 274 int "Size in bytes of the EEPROM device" 275 default 256 276 277config SYS_EEPROM_PAGE_WRITE_BITS 278 int "Number of bits used to address bytes in a single page" 279 default 0 280 help 281 The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. 282 A 64 byte page, for example would require six bits. 283 284config SYS_EEPROM_PAGE_WRITE_DELAY_MS 285 int "Number of milliseconds to delay between page writes" 286 default 0 287 288config SYS_I2C_EEPROM_ADDR_LEN 289 int "Length in bytes of the EEPROM memory array address" 290 default 1 291 help 292 Note: This is NOT the chip address length! 293 294config SYS_I2C_EEPROM_ADDR_OVERFLOW 295 hex "EEPROM Address Overflow" 296 default 0 297 help 298 EEPROM chips that implement "address overflow" are ones 299 like Catalyst 24WC04/08/16 which has 9/10/11 bits of 300 address and the extra bits end up in the "chip address" bit 301 slots. This makes a 24WC08 (1Kbyte) chip look like four 256 302 byte chips. 303 304endif 305 306 307endmenu 308