1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_HAS_BINFMT_FLAT 7 select ARCH_HAS_DEBUG_VIRTUAL if MMU 8 select ARCH_HAS_DEVMEM_IS_ALLOWED 9 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 10 select ARCH_HAS_ELF_RANDOMIZE 11 select ARCH_HAS_FORTIFY_SOURCE 12 select ARCH_HAS_KEEPINITRD 13 select ARCH_HAS_KCOV 14 select ARCH_HAS_MEMBARRIER_SYNC_CORE 15 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 16 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 17 select ARCH_HAS_PHYS_TO_DMA 18 select ARCH_HAS_SETUP_DMA_OPS 19 select ARCH_HAS_SET_MEMORY 20 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 21 select ARCH_HAS_STRICT_MODULE_RWX if MMU && (!ROCKCHIP_MINI_KERNEL || STRICT_KERNEL_RWX) 22 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB 23 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB 24 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 25 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 26 select ARCH_HAVE_CUSTOM_GPIO_H 27 select ARCH_HAS_GCOV_PROFILE_ALL 28 select ARCH_KEEP_MEMBLOCK 29 select ARCH_MIGHT_HAVE_PC_PARPORT 30 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 33 select ARCH_SUPPORTS_ATOMIC_RMW 34 select ARCH_USE_BUILTIN_BSWAP 35 select ARCH_USE_CMPXCHG_LOCKREF 36 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 37 select ARCH_WANT_IPC_PARSE_VERSION 38 select ARCH_WANT_LD_ORPHAN_WARN 39 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 40 select BUILDTIME_TABLE_SORT if MMU 41 select CLONE_BACKWARDS 42 select CPU_PM if SUSPEND || CPU_IDLE 43 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 44 select DMA_DECLARE_COHERENT 45 select DMA_OPS 46 select DMA_REMAP if MMU 47 select EDAC_SUPPORT 48 select EDAC_ATOMIC_SCRUB 49 select GENERIC_ALLOCATOR 50 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 51 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 52 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 53 select GENERIC_IRQ_IPI if SMP 54 select ARCH_WANTS_IRQ_RAW if GENERIC_IRQ_IPI 55 select GENERIC_CPU_AUTOPROBE 56 select GENERIC_EARLY_IOREMAP 57 select GENERIC_IDLE_POLL_SETUP 58 select GENERIC_IRQ_PROBE 59 select GENERIC_IRQ_SHOW 60 select GENERIC_IRQ_SHOW_LEVEL 61 select GENERIC_PCI_IOMAP 62 select GENERIC_SCHED_CLOCK 63 select GENERIC_SMP_IDLE_THREAD 64 select GENERIC_STRNCPY_FROM_USER 65 select GENERIC_STRNLEN_USER 66 select HANDLE_DOMAIN_IRQ 67 select HARDIRQS_SW_RESEND 68 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 69 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 70 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 71 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 72 select HAVE_ARCH_MMAP_RND_BITS if MMU 73 select HAVE_ARCH_SECCOMP 74 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 75 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 76 select HAVE_ARCH_TRACEHOOK 77 select HAVE_ARM_SMCCC if CPU_V7 78 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 79 select HAVE_CONTEXT_TRACKING 80 select HAVE_C_RECORDMCOUNT 81 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 82 select HAVE_DMA_CONTIGUOUS if MMU 83 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 84 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 85 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 86 select HAVE_EXIT_THREAD 87 select HAVE_FAST_GUP if ARM_LPAE 88 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 89 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 90 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 91 select HAVE_FUTEX_CMPXCHG if FUTEX 92 select HAVE_GCC_PLUGINS 93 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 94 select HAVE_IDE if PCI || ISA || PCMCIA 95 select HAVE_IRQ_TIME_ACCOUNTING 96 select HAVE_KERNEL_GZIP 97 select HAVE_KERNEL_LZ4 98 select HAVE_KERNEL_LZMA 99 select HAVE_KERNEL_LZO 100 select HAVE_KERNEL_XZ 101 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 102 select HAVE_KRETPROBES if HAVE_KPROBES 103 select HAVE_MOD_ARCH_SPECIFIC 104 select HAVE_NMI 105 select HAVE_OPROFILE if HAVE_PERF_EVENTS 106 select HAVE_OPTPROBES if !THUMB2_KERNEL 107 select HAVE_PERF_EVENTS 108 select HAVE_PERF_REGS 109 select HAVE_PERF_USER_STACK_DUMP 110 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 111 select HAVE_REGS_AND_STACK_ACCESS_API 112 select HAVE_RSEQ 113 select HAVE_STACKPROTECTOR 114 select HAVE_SYSCALL_TRACEPOINTS 115 select HAVE_UID16 116 select HAVE_VIRT_CPU_ACCOUNTING_GEN 117 select IRQ_FORCED_THREADING 118 select MODULES_USE_ELF_REL 119 select NEED_DMA_MAP_STATE 120 select OF_EARLY_FLATTREE if OF 121 select OLD_SIGACTION 122 select OLD_SIGSUSPEND3 123 select PCI_SYSCALL if PCI 124 select PERF_USE_VMALLOC 125 select RTC_LIB 126 select SET_FS 127 select SYS_SUPPORTS_APM_EMULATION 128 # Above selects are sorted alphabetically; please add new ones 129 # according to that. Thanks. 130 help 131 The ARM series is a line of low-power-consumption RISC chip designs 132 licensed by ARM Ltd and targeted at embedded applications and 133 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 134 manufactured, but legacy ARM-based PC hardware remains popular in 135 Europe. There is an ARM Linux project with a web page at 136 <http://www.arm.linux.org.uk/>. 137 138config ARM_HAS_SG_CHAIN 139 bool 140 141config ARM_DMA_USE_IOMMU 142 bool 143 select ARM_HAS_SG_CHAIN 144 select NEED_SG_DMA_LENGTH 145 146if ARM_DMA_USE_IOMMU 147 148config ARM_DMA_IOMMU_ALIGNMENT 149 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 150 range 4 9 151 default 8 152 help 153 DMA mapping framework by default aligns all buffers to the smallest 154 PAGE_SIZE order which is greater than or equal to the requested buffer 155 size. This works well for buffers up to a few hundreds kilobytes, but 156 for larger buffers it just a waste of address space. Drivers which has 157 relatively small addressing window (like 64Mib) might run out of 158 virtual space with just a few allocations. 159 160 With this parameter you can specify the maximum PAGE_SIZE order for 161 DMA IOMMU buffers. Larger buffers will be aligned only to this 162 specified order. The order is expressed as a power of two multiplied 163 by the PAGE_SIZE. 164 165endif 166 167config SYS_SUPPORTS_APM_EMULATION 168 bool 169 170config HAVE_TCM 171 bool 172 select GENERIC_ALLOCATOR 173 174config HAVE_PROC_CPU 175 bool 176 177config NO_IOPORT_MAP 178 bool 179 180config SBUS 181 bool 182 183config STACKTRACE_SUPPORT 184 bool 185 default y 186 187config LOCKDEP_SUPPORT 188 bool 189 default y 190 191config TRACE_IRQFLAGS_SUPPORT 192 bool 193 default !CPU_V7M 194 195config ARCH_HAS_ILOG2_U32 196 bool 197 198config ARCH_HAS_ILOG2_U64 199 bool 200 201config ARCH_HAS_BANDGAP 202 bool 203 204config FIX_EARLYCON_MEM 205 def_bool y if MMU 206 207config GENERIC_HWEIGHT 208 bool 209 default y 210 211config GENERIC_CALIBRATE_DELAY 212 bool 213 default y 214 215config ARCH_MAY_HAVE_PC_FDC 216 bool 217 218config ZONE_DMA 219 bool 220 221config ARCH_SUPPORTS_UPROBES 222 def_bool y 223 224config ARCH_HAS_DMA_SET_COHERENT_MASK 225 bool 226 227config GENERIC_ISA_DMA 228 bool 229 230config FIQ 231 bool 232 233config NEED_RET_TO_USER 234 bool 235 236config ARCH_MTD_XIP 237 bool 238 239config ARM_PATCH_PHYS_VIRT 240 bool "Patch physical to virtual translations at runtime" if EMBEDDED 241 default y 242 depends on !XIP_KERNEL && MMU 243 help 244 Patch phys-to-virt and virt-to-phys translation functions at 245 boot and module load time according to the position of the 246 kernel in system memory. 247 248 This can only be used with non-XIP MMU kernels where the base 249 of physical memory is at a 16MB boundary. 250 251 Only disable this option if you know that you do not require 252 this feature (eg, building a kernel for a single machine) and 253 you need to shrink the kernel to the minimal size. 254 255config NEED_MACH_IO_H 256 bool 257 help 258 Select this when mach/io.h is required to provide special 259 definitions for this platform. The need for mach/io.h should 260 be avoided when possible. 261 262config NEED_MACH_MEMORY_H 263 bool 264 help 265 Select this when mach/memory.h is required to provide special 266 definitions for this platform. The need for mach/memory.h should 267 be avoided when possible. 268 269config PHYS_OFFSET 270 hex "Physical address of main memory" if MMU 271 depends on !ARM_PATCH_PHYS_VIRT 272 default DRAM_BASE if !MMU 273 default 0x00000000 if ARCH_EBSA110 || \ 274 ARCH_FOOTBRIDGE 275 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 276 default 0x20000000 if ARCH_S5PV210 277 default 0xc0000000 if ARCH_SA1100 278 help 279 Please provide the physical address corresponding to the 280 location of main memory in your system. 281 282config GENERIC_BUG 283 def_bool y 284 depends on BUG 285 286config PGTABLE_LEVELS 287 int 288 default 3 if ARM_LPAE 289 default 2 290 291menu "System Type" 292 293config MMU 294 bool "MMU-based Paged Memory Management Support" 295 default y 296 help 297 Select if you want MMU-based virtualised addressing space 298 support by paged memory management. If unsure, say 'Y'. 299 300config ARCH_MMAP_RND_BITS_MIN 301 default 8 302 303config ARCH_MMAP_RND_BITS_MAX 304 default 14 if PAGE_OFFSET=0x40000000 305 default 15 if PAGE_OFFSET=0x80000000 306 default 16 307 308# 309# The "ARM system type" choice list is ordered alphabetically by option 310# text. Please add new entries in the option alphabetic order. 311# 312choice 313 prompt "ARM system type" 314 default ARM_SINGLE_ARMV7M if !MMU 315 default ARCH_MULTIPLATFORM if MMU 316 317config ARCH_MULTIPLATFORM 318 bool "Allow multiple platforms to be selected" 319 depends on MMU 320 select ARCH_FLATMEM_ENABLE 321 select ARCH_SPARSEMEM_ENABLE 322 select ARCH_SELECT_MEMORY_MODEL 323 select ARM_HAS_SG_CHAIN 324 select ARM_PATCH_PHYS_VIRT 325 select AUTO_ZRELADDR 326 select TIMER_OF 327 select COMMON_CLK 328 select GENERIC_CLOCKEVENTS 329 select GENERIC_IRQ_MULTI_HANDLER 330 select HAVE_PCI 331 select PCI_DOMAINS_GENERIC if PCI 332 select SPARSE_IRQ 333 select USE_OF 334 335config ARM_SINGLE_ARMV7M 336 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 337 depends on !MMU 338 select ARM_NVIC 339 select AUTO_ZRELADDR 340 select TIMER_OF 341 select COMMON_CLK 342 select CPU_V7M 343 select GENERIC_CLOCKEVENTS 344 select NO_IOPORT_MAP 345 select SPARSE_IRQ 346 select USE_OF 347 348config ARCH_EBSA110 349 bool "EBSA-110" 350 select ARCH_USES_GETTIMEOFFSET 351 select CPU_SA110 352 select ISA 353 select NEED_MACH_IO_H 354 select NEED_MACH_MEMORY_H 355 select NO_IOPORT_MAP 356 help 357 This is an evaluation board for the StrongARM processor available 358 from Digital. It has limited hardware on-board, including an 359 Ethernet interface, two PCMCIA sockets, two serial ports and a 360 parallel port. 361 362config ARCH_EP93XX 363 bool "EP93xx-based" 364 select ARCH_SPARSEMEM_ENABLE 365 select ARM_AMBA 366 imply ARM_PATCH_PHYS_VIRT 367 select ARM_VIC 368 select AUTO_ZRELADDR 369 select CLKDEV_LOOKUP 370 select CLKSRC_MMIO 371 select CPU_ARM920T 372 select GENERIC_CLOCKEVENTS 373 select GPIOLIB 374 select HAVE_LEGACY_CLK 375 help 376 This enables support for the Cirrus EP93xx series of CPUs. 377 378config ARCH_FOOTBRIDGE 379 bool "FootBridge" 380 select CPU_SA110 381 select FOOTBRIDGE 382 select GENERIC_CLOCKEVENTS 383 select HAVE_IDE 384 select NEED_MACH_IO_H if !MMU 385 select NEED_MACH_MEMORY_H 386 help 387 Support for systems based on the DC21285 companion chip 388 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 389 390config ARCH_IOP32X 391 bool "IOP32x-based" 392 depends on MMU 393 select CPU_XSCALE 394 select GPIO_IOP 395 select GPIOLIB 396 select NEED_RET_TO_USER 397 select FORCE_PCI 398 select PLAT_IOP 399 help 400 Support for Intel's 80219 and IOP32X (XScale) family of 401 processors. 402 403config ARCH_IXP4XX 404 bool "IXP4xx-based" 405 depends on MMU 406 select ARCH_HAS_DMA_SET_COHERENT_MASK 407 select ARCH_SUPPORTS_BIG_ENDIAN 408 select CPU_XSCALE 409 select DMABOUNCE if PCI 410 select GENERIC_CLOCKEVENTS 411 select GENERIC_IRQ_MULTI_HANDLER 412 select GPIO_IXP4XX 413 select GPIOLIB 414 select HAVE_PCI 415 select IXP4XX_IRQ 416 select IXP4XX_TIMER 417 select NEED_MACH_IO_H 418 select USB_EHCI_BIG_ENDIAN_DESC 419 select USB_EHCI_BIG_ENDIAN_MMIO 420 help 421 Support for Intel's IXP4XX (XScale) family of processors. 422 423config ARCH_DOVE 424 bool "Marvell Dove" 425 select CPU_PJ4 426 select GENERIC_CLOCKEVENTS 427 select GENERIC_IRQ_MULTI_HANDLER 428 select GPIOLIB 429 select HAVE_PCI 430 select MVEBU_MBUS 431 select PINCTRL 432 select PINCTRL_DOVE 433 select PLAT_ORION_LEGACY 434 select SPARSE_IRQ 435 select PM_GENERIC_DOMAINS if PM 436 help 437 Support for the Marvell Dove SoC 88AP510 438 439config ARCH_PXA 440 bool "PXA2xx/PXA3xx-based" 441 depends on MMU 442 select ARCH_MTD_XIP 443 select ARM_CPU_SUSPEND if PM 444 select AUTO_ZRELADDR 445 select COMMON_CLK 446 select CLKSRC_PXA 447 select CLKSRC_MMIO 448 select TIMER_OF 449 select CPU_XSCALE if !CPU_XSC3 450 select GENERIC_CLOCKEVENTS 451 select GENERIC_IRQ_MULTI_HANDLER 452 select GPIO_PXA 453 select GPIOLIB 454 select HAVE_IDE 455 select IRQ_DOMAIN 456 select PLAT_PXA 457 select SPARSE_IRQ 458 help 459 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 460 461config ARCH_RPC 462 bool "RiscPC" 463 depends on MMU 464 select ARCH_ACORN 465 select ARCH_MAY_HAVE_PC_FDC 466 select ARCH_SPARSEMEM_ENABLE 467 select ARM_HAS_SG_CHAIN 468 select CPU_SA110 469 select FIQ 470 select HAVE_IDE 471 select HAVE_PATA_PLATFORM 472 select ISA_DMA_API 473 select NEED_MACH_IO_H 474 select NEED_MACH_MEMORY_H 475 select NO_IOPORT_MAP 476 help 477 On the Acorn Risc-PC, Linux can support the internal IDE disk and 478 CD-ROM interface, serial and parallel port, and the floppy drive. 479 480config ARCH_SA1100 481 bool "SA1100-based" 482 select ARCH_MTD_XIP 483 select ARCH_SPARSEMEM_ENABLE 484 select CLKSRC_MMIO 485 select CLKSRC_PXA 486 select TIMER_OF if OF 487 select COMMON_CLK 488 select CPU_FREQ 489 select CPU_SA1100 490 select GENERIC_CLOCKEVENTS 491 select GENERIC_IRQ_MULTI_HANDLER 492 select GPIOLIB 493 select HAVE_IDE 494 select IRQ_DOMAIN 495 select ISA 496 select NEED_MACH_MEMORY_H 497 select SPARSE_IRQ 498 help 499 Support for StrongARM 11x0 based boards. 500 501config ARCH_S3C24XX 502 bool "Samsung S3C24XX SoCs" 503 select ATAGS 504 select CLKSRC_SAMSUNG_PWM 505 select GENERIC_CLOCKEVENTS 506 select GPIO_SAMSUNG 507 select GPIOLIB 508 select GENERIC_IRQ_MULTI_HANDLER 509 select HAVE_S3C2410_I2C if I2C 510 select HAVE_S3C_RTC if RTC_CLASS 511 select NEED_MACH_IO_H 512 select S3C2410_WATCHDOG 513 select SAMSUNG_ATAGS 514 select USE_OF 515 select WATCHDOG 516 help 517 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 518 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 519 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 520 Samsung SMDK2410 development board (and derivatives). 521 522config ARCH_OMAP1 523 bool "TI OMAP1" 524 depends on MMU 525 select ARCH_OMAP 526 select CLKDEV_LOOKUP 527 select CLKSRC_MMIO 528 select GENERIC_CLOCKEVENTS 529 select GENERIC_IRQ_CHIP 530 select GENERIC_IRQ_MULTI_HANDLER 531 select GPIOLIB 532 select HAVE_IDE 533 select HAVE_LEGACY_CLK 534 select IRQ_DOMAIN 535 select NEED_MACH_IO_H if PCCARD 536 select NEED_MACH_MEMORY_H 537 select SPARSE_IRQ 538 help 539 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 540 541endchoice 542 543menu "Multiple platform selection" 544 depends on ARCH_MULTIPLATFORM 545 546comment "CPU Core family selection" 547 548config ARCH_MULTI_V4 549 bool "ARMv4 based platforms (FA526)" 550 depends on !ARCH_MULTI_V6_V7 551 select ARCH_MULTI_V4_V5 552 select CPU_FA526 553 554config ARCH_MULTI_V4T 555 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 556 depends on !ARCH_MULTI_V6_V7 557 select ARCH_MULTI_V4_V5 558 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 559 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 560 CPU_ARM925T || CPU_ARM940T) 561 562config ARCH_MULTI_V5 563 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 564 depends on !ARCH_MULTI_V6_V7 565 select ARCH_MULTI_V4_V5 566 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 567 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 568 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 569 570config ARCH_MULTI_V4_V5 571 bool 572 573config ARCH_MULTI_V6 574 bool "ARMv6 based platforms (ARM11)" 575 select ARCH_MULTI_V6_V7 576 select CPU_V6K 577 578config ARCH_MULTI_V7 579 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 580 default y 581 select ARCH_MULTI_V6_V7 582 select CPU_V7 583 select HAVE_SMP 584 585config ARCH_MULTI_V6_V7 586 bool 587 select MIGHT_HAVE_CACHE_L2X0 588 589config ARCH_MULTI_CPU_AUTO 590 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 591 select ARCH_MULTI_V5 592 593endmenu 594 595config ARCH_VIRT 596 bool "Dummy Virtual Machine" 597 depends on ARCH_MULTI_V7 598 select ARM_AMBA 599 select ARM_GIC 600 select ARM_GIC_V2M if PCI 601 select ARM_GIC_V3 602 select ARM_GIC_V3_ITS if PCI 603 select ARM_PSCI 604 select HAVE_ARM_ARCH_TIMER 605 select ARCH_SUPPORTS_BIG_ENDIAN 606 607# 608# This is sorted alphabetically by mach-* pathname. However, plat-* 609# Kconfigs may be included either alphabetically (according to the 610# plat- suffix) or along side the corresponding mach-* source. 611# 612source "arch/arm/mach-actions/Kconfig" 613 614source "arch/arm/mach-alpine/Kconfig" 615 616source "arch/arm/mach-artpec/Kconfig" 617 618source "arch/arm/mach-asm9260/Kconfig" 619 620source "arch/arm/mach-aspeed/Kconfig" 621 622source "arch/arm/mach-at91/Kconfig" 623 624source "arch/arm/mach-axxia/Kconfig" 625 626source "arch/arm/mach-bcm/Kconfig" 627 628source "arch/arm/mach-berlin/Kconfig" 629 630source "arch/arm/mach-clps711x/Kconfig" 631 632source "arch/arm/mach-cns3xxx/Kconfig" 633 634source "arch/arm/mach-davinci/Kconfig" 635 636source "arch/arm/mach-digicolor/Kconfig" 637 638source "arch/arm/mach-dove/Kconfig" 639 640source "arch/arm/mach-ep93xx/Kconfig" 641 642source "arch/arm/mach-exynos/Kconfig" 643 644source "arch/arm/mach-footbridge/Kconfig" 645 646source "arch/arm/mach-gemini/Kconfig" 647 648source "arch/arm/mach-highbank/Kconfig" 649 650source "arch/arm/mach-hisi/Kconfig" 651 652source "arch/arm/mach-imx/Kconfig" 653 654source "arch/arm/mach-integrator/Kconfig" 655 656source "arch/arm/mach-iop32x/Kconfig" 657 658source "arch/arm/mach-ixp4xx/Kconfig" 659 660source "arch/arm/mach-keystone/Kconfig" 661 662source "arch/arm/mach-lpc32xx/Kconfig" 663 664source "arch/arm/mach-mediatek/Kconfig" 665 666source "arch/arm/mach-meson/Kconfig" 667 668source "arch/arm/mach-milbeaut/Kconfig" 669 670source "arch/arm/mach-mmp/Kconfig" 671 672source "arch/arm/mach-moxart/Kconfig" 673 674source "arch/arm/mach-mstar/Kconfig" 675 676source "arch/arm/mach-mv78xx0/Kconfig" 677 678source "arch/arm/mach-mvebu/Kconfig" 679 680source "arch/arm/mach-mxs/Kconfig" 681 682source "arch/arm/mach-nomadik/Kconfig" 683 684source "arch/arm/mach-npcm/Kconfig" 685 686source "arch/arm/mach-nspire/Kconfig" 687 688source "arch/arm/plat-omap/Kconfig" 689 690source "arch/arm/mach-omap1/Kconfig" 691 692source "arch/arm/mach-omap2/Kconfig" 693 694source "arch/arm/mach-orion5x/Kconfig" 695 696source "arch/arm/mach-oxnas/Kconfig" 697 698source "arch/arm/mach-picoxcell/Kconfig" 699 700source "arch/arm/mach-prima2/Kconfig" 701 702source "arch/arm/mach-pxa/Kconfig" 703source "arch/arm/plat-pxa/Kconfig" 704 705source "arch/arm/mach-qcom/Kconfig" 706 707source "arch/arm/mach-rda/Kconfig" 708 709source "arch/arm/mach-realtek/Kconfig" 710 711source "arch/arm/mach-realview/Kconfig" 712 713source "arch/arm/mach-rockchip/Kconfig" 714 715source "arch/arm/mach-s3c/Kconfig" 716 717source "arch/arm/mach-s5pv210/Kconfig" 718 719source "arch/arm/mach-sa1100/Kconfig" 720 721source "arch/arm/mach-shmobile/Kconfig" 722 723source "arch/arm/mach-socfpga/Kconfig" 724 725source "arch/arm/mach-spear/Kconfig" 726 727source "arch/arm/mach-sti/Kconfig" 728 729source "arch/arm/mach-stm32/Kconfig" 730 731source "arch/arm/mach-sunxi/Kconfig" 732 733source "arch/arm/mach-tango/Kconfig" 734 735source "arch/arm/mach-tegra/Kconfig" 736 737source "arch/arm/mach-u300/Kconfig" 738 739source "arch/arm/mach-uniphier/Kconfig" 740 741source "arch/arm/mach-ux500/Kconfig" 742 743source "arch/arm/mach-versatile/Kconfig" 744 745source "arch/arm/mach-vexpress/Kconfig" 746 747source "arch/arm/mach-vt8500/Kconfig" 748 749source "arch/arm/mach-zx/Kconfig" 750 751source "arch/arm/mach-zynq/Kconfig" 752 753# ARMv7-M architecture 754config ARCH_EFM32 755 bool "Energy Micro efm32" 756 depends on ARM_SINGLE_ARMV7M 757 select GPIOLIB 758 help 759 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 760 processors. 761 762config ARCH_LPC18XX 763 bool "NXP LPC18xx/LPC43xx" 764 depends on ARM_SINGLE_ARMV7M 765 select ARCH_HAS_RESET_CONTROLLER 766 select ARM_AMBA 767 select CLKSRC_LPC32XX 768 select PINCTRL 769 help 770 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 771 high performance microcontrollers. 772 773config ARCH_MPS2 774 bool "ARM MPS2 platform" 775 depends on ARM_SINGLE_ARMV7M 776 select ARM_AMBA 777 select CLKSRC_MPS2 778 help 779 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 780 with a range of available cores like Cortex-M3/M4/M7. 781 782 Please, note that depends which Application Note is used memory map 783 for the platform may vary, so adjustment of RAM base might be needed. 784 785# Definitions to make life easier 786config ARCH_ACORN 787 bool 788 789config PLAT_IOP 790 bool 791 select GENERIC_CLOCKEVENTS 792 793config PLAT_ORION 794 bool 795 select CLKSRC_MMIO 796 select COMMON_CLK 797 select GENERIC_IRQ_CHIP 798 select IRQ_DOMAIN 799 800config PLAT_ORION_LEGACY 801 bool 802 select PLAT_ORION 803 804config PLAT_PXA 805 bool 806 807config PLAT_VERSATILE 808 bool 809 810source "arch/arm/mm/Kconfig" 811 812config IWMMXT 813 bool "Enable iWMMXt support" 814 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 815 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 816 help 817 Enable support for iWMMXt context switching at run time if 818 running on a CPU that supports it. 819 820if !MMU 821source "arch/arm/Kconfig-nommu" 822endif 823 824config PJ4B_ERRATA_4742 825 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 826 depends on CPU_PJ4B && MACH_ARMADA_370 827 default y 828 help 829 When coming out of either a Wait for Interrupt (WFI) or a Wait for 830 Event (WFE) IDLE states, a specific timing sensitivity exists between 831 the retiring WFI/WFE instructions and the newly issued subsequent 832 instructions. This sensitivity can result in a CPU hang scenario. 833 Workaround: 834 The software must insert either a Data Synchronization Barrier (DSB) 835 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 836 instruction 837 838config ARM_ERRATA_326103 839 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 840 depends on CPU_V6 841 help 842 Executing a SWP instruction to read-only memory does not set bit 11 843 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 844 treat the access as a read, preventing a COW from occurring and 845 causing the faulting task to livelock. 846 847config ARM_ERRATA_411920 848 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 849 depends on CPU_V6 || CPU_V6K 850 help 851 Invalidation of the Instruction Cache operation can 852 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 853 It does not affect the MPCore. This option enables the ARM Ltd. 854 recommended workaround. 855 856config ARM_ERRATA_430973 857 bool "ARM errata: Stale prediction on replaced interworking branch" 858 depends on CPU_V7 859 help 860 This option enables the workaround for the 430973 Cortex-A8 861 r1p* erratum. If a code sequence containing an ARM/Thumb 862 interworking branch is replaced with another code sequence at the 863 same virtual address, whether due to self-modifying code or virtual 864 to physical address re-mapping, Cortex-A8 does not recover from the 865 stale interworking branch prediction. This results in Cortex-A8 866 executing the new code sequence in the incorrect ARM or Thumb state. 867 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 868 and also flushes the branch target cache at every context switch. 869 Note that setting specific bits in the ACTLR register may not be 870 available in non-secure mode. 871 872config ARM_ERRATA_458693 873 bool "ARM errata: Processor deadlock when a false hazard is created" 874 depends on CPU_V7 875 depends on !ARCH_MULTIPLATFORM 876 help 877 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 878 erratum. For very specific sequences of memory operations, it is 879 possible for a hazard condition intended for a cache line to instead 880 be incorrectly associated with a different cache line. This false 881 hazard might then cause a processor deadlock. The workaround enables 882 the L1 caching of the NEON accesses and disables the PLD instruction 883 in the ACTLR register. Note that setting specific bits in the ACTLR 884 register may not be available in non-secure mode. 885 886config ARM_ERRATA_460075 887 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 888 depends on CPU_V7 889 depends on !ARCH_MULTIPLATFORM 890 help 891 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 892 erratum. Any asynchronous access to the L2 cache may encounter a 893 situation in which recent store transactions to the L2 cache are lost 894 and overwritten with stale memory contents from external memory. The 895 workaround disables the write-allocate mode for the L2 cache via the 896 ACTLR register. Note that setting specific bits in the ACTLR register 897 may not be available in non-secure mode. 898 899config ARM_ERRATA_742230 900 bool "ARM errata: DMB operation may be faulty" 901 depends on CPU_V7 && SMP 902 depends on !ARCH_MULTIPLATFORM 903 help 904 This option enables the workaround for the 742230 Cortex-A9 905 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 906 between two write operations may not ensure the correct visibility 907 ordering of the two writes. This workaround sets a specific bit in 908 the diagnostic register of the Cortex-A9 which causes the DMB 909 instruction to behave as a DSB, ensuring the correct behaviour of 910 the two writes. 911 912config ARM_ERRATA_742231 913 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 914 depends on CPU_V7 && SMP 915 depends on !ARCH_MULTIPLATFORM 916 help 917 This option enables the workaround for the 742231 Cortex-A9 918 (r2p0..r2p2) erratum. Under certain conditions, specific to the 919 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 920 accessing some data located in the same cache line, may get corrupted 921 data due to bad handling of the address hazard when the line gets 922 replaced from one of the CPUs at the same time as another CPU is 923 accessing it. This workaround sets specific bits in the diagnostic 924 register of the Cortex-A9 which reduces the linefill issuing 925 capabilities of the processor. 926 927config ARM_ERRATA_643719 928 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 929 depends on CPU_V7 && SMP 930 default y 931 help 932 This option enables the workaround for the 643719 Cortex-A9 (prior to 933 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 934 register returns zero when it should return one. The workaround 935 corrects this value, ensuring cache maintenance operations which use 936 it behave as intended and avoiding data corruption. 937 938config ARM_ERRATA_720789 939 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 940 depends on CPU_V7 941 help 942 This option enables the workaround for the 720789 Cortex-A9 (prior to 943 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 944 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 945 As a consequence of this erratum, some TLB entries which should be 946 invalidated are not, resulting in an incoherency in the system page 947 tables. The workaround changes the TLB flushing routines to invalidate 948 entries regardless of the ASID. 949 950config ARM_ERRATA_743622 951 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 952 depends on CPU_V7 953 depends on !ARCH_MULTIPLATFORM 954 help 955 This option enables the workaround for the 743622 Cortex-A9 956 (r2p*) erratum. Under very rare conditions, a faulty 957 optimisation in the Cortex-A9 Store Buffer may lead to data 958 corruption. This workaround sets a specific bit in the diagnostic 959 register of the Cortex-A9 which disables the Store Buffer 960 optimisation, preventing the defect from occurring. This has no 961 visible impact on the overall performance or power consumption of the 962 processor. 963 964config ARM_ERRATA_751472 965 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 966 depends on CPU_V7 967 depends on !ARCH_MULTIPLATFORM 968 help 969 This option enables the workaround for the 751472 Cortex-A9 (prior 970 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 971 completion of a following broadcasted operation if the second 972 operation is received by a CPU before the ICIALLUIS has completed, 973 potentially leading to corrupted entries in the cache or TLB. 974 975config ARM_ERRATA_754322 976 bool "ARM errata: possible faulty MMU translations following an ASID switch" 977 depends on CPU_V7 978 help 979 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 980 r3p*) erratum. A speculative memory access may cause a page table walk 981 which starts prior to an ASID switch but completes afterwards. This 982 can populate the micro-TLB with a stale entry which may be hit with 983 the new ASID. This workaround places two dsb instructions in the mm 984 switching code so that no page table walks can cross the ASID switch. 985 986config ARM_ERRATA_754327 987 bool "ARM errata: no automatic Store Buffer drain" 988 depends on CPU_V7 && SMP 989 help 990 This option enables the workaround for the 754327 Cortex-A9 (prior to 991 r2p0) erratum. The Store Buffer does not have any automatic draining 992 mechanism and therefore a livelock may occur if an external agent 993 continuously polls a memory location waiting to observe an update. 994 This workaround defines cpu_relax() as smp_mb(), preventing correctly 995 written polling loops from denying visibility of updates to memory. 996 997config ARM_ERRATA_364296 998 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 999 depends on CPU_V6 1000 help 1001 This options enables the workaround for the 364296 ARM1136 1002 r0p2 erratum (possible cache data corruption with 1003 hit-under-miss enabled). It sets the undocumented bit 31 in 1004 the auxiliary control register and the FI bit in the control 1005 register, thus disabling hit-under-miss without putting the 1006 processor into full low interrupt latency mode. ARM11MPCore 1007 is not affected. 1008 1009config ARM_ERRATA_764369 1010 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1011 depends on CPU_V7 && SMP 1012 help 1013 This option enables the workaround for erratum 764369 1014 affecting Cortex-A9 MPCore with two or more processors (all 1015 current revisions). Under certain timing circumstances, a data 1016 cache line maintenance operation by MVA targeting an Inner 1017 Shareable memory region may fail to proceed up to either the 1018 Point of Coherency or to the Point of Unification of the 1019 system. This workaround adds a DSB instruction before the 1020 relevant cache maintenance functions and sets a specific bit 1021 in the diagnostic control register of the SCU. 1022 1023config ARM_ERRATA_775420 1024 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1025 depends on CPU_V7 1026 help 1027 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1028 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 1029 operation aborts with MMU exception, it might cause the processor 1030 to deadlock. This workaround puts DSB before executing ISB if 1031 an abort may occur on cache maintenance. 1032 1033config ARM_ERRATA_798181 1034 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1035 depends on CPU_V7 && SMP 1036 help 1037 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1038 adequately shooting down all use of the old entries. This 1039 option enables the Linux kernel workaround for this erratum 1040 which sends an IPI to the CPUs that are running the same ASID 1041 as the one being invalidated. 1042 1043config ARM_ERRATA_773022 1044 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1045 depends on CPU_V7 1046 help 1047 This option enables the workaround for the 773022 Cortex-A15 1048 (up to r0p4) erratum. In certain rare sequences of code, the 1049 loop buffer may deliver incorrect instructions. This 1050 workaround disables the loop buffer to avoid the erratum. 1051 1052config ARM_ERRATA_818325_852422 1053 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1054 depends on CPU_V7 1055 help 1056 This option enables the workaround for: 1057 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1058 instruction might deadlock. Fixed in r0p1. 1059 - Cortex-A12 852422: Execution of a sequence of instructions might 1060 lead to either a data corruption or a CPU deadlock. Not fixed in 1061 any Cortex-A12 cores yet. 1062 This workaround for all both errata involves setting bit[12] of the 1063 Feature Register. This bit disables an optimisation applied to a 1064 sequence of 2 instructions that use opposing condition codes. 1065 1066config ARM_ERRATA_821420 1067 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1068 depends on CPU_V7 1069 help 1070 This option enables the workaround for the 821420 Cortex-A12 1071 (all revs) erratum. In very rare timing conditions, a sequence 1072 of VMOV to Core registers instructions, for which the second 1073 one is in the shadow of a branch or abort, can lead to a 1074 deadlock when the VMOV instructions are issued out-of-order. 1075 1076config ARM_ERRATA_825619 1077 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1078 depends on CPU_V7 1079 help 1080 This option enables the workaround for the 825619 Cortex-A12 1081 (all revs) erratum. Within rare timing constraints, executing a 1082 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1083 and Device/Strongly-Ordered loads and stores might cause deadlock 1084 1085config ARM_ERRATA_857271 1086 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1087 depends on CPU_V7 1088 help 1089 This option enables the workaround for the 857271 Cortex-A12 1090 (all revs) erratum. Under very rare timing conditions, the CPU might 1091 hang. The workaround is expected to have a < 1% performance impact. 1092 1093config ARM_ERRATA_852421 1094 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1095 depends on CPU_V7 1096 help 1097 This option enables the workaround for the 852421 Cortex-A17 1098 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1099 execution of a DMB ST instruction might fail to properly order 1100 stores from GroupA and stores from GroupB. 1101 1102config ARM_ERRATA_852423 1103 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1104 depends on CPU_V7 1105 help 1106 This option enables the workaround for: 1107 - Cortex-A17 852423: Execution of a sequence of instructions might 1108 lead to either a data corruption or a CPU deadlock. Not fixed in 1109 any Cortex-A17 cores yet. 1110 This is identical to Cortex-A12 erratum 852422. It is a separate 1111 config option from the A12 erratum due to the way errata are checked 1112 for and handled. 1113 1114config ARM_ERRATA_857272 1115 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1116 depends on CPU_V7 1117 help 1118 This option enables the workaround for the 857272 Cortex-A17 erratum. 1119 This erratum is not known to be fixed in any A17 revision. 1120 This is identical to Cortex-A12 erratum 857271. It is a separate 1121 config option from the A12 erratum due to the way errata are checked 1122 for and handled. 1123 1124endmenu 1125 1126source "arch/arm/common/Kconfig" 1127 1128menu "Bus support" 1129 1130config ISA 1131 bool 1132 help 1133 Find out whether you have ISA slots on your motherboard. ISA is the 1134 name of a bus system, i.e. the way the CPU talks to the other stuff 1135 inside your box. Other bus systems are PCI, EISA, MicroChannel 1136 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1137 newer boards don't support it. If you have ISA, say Y, otherwise N. 1138 1139# Select ISA DMA controller support 1140config ISA_DMA 1141 bool 1142 select ISA_DMA_API 1143 1144# Select ISA DMA interface 1145config ISA_DMA_API 1146 bool 1147 1148config PCI_NANOENGINE 1149 bool "BSE nanoEngine PCI support" 1150 depends on SA1100_NANOENGINE 1151 help 1152 Enable PCI on the BSE nanoEngine board. 1153 1154config ARM_ERRATA_814220 1155 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1156 depends on CPU_V7 1157 help 1158 The v7 ARM states that all cache and branch predictor maintenance 1159 operations that do not specify an address execute, relative to 1160 each other, in program order. 1161 However, because of this erratum, an L2 set/way cache maintenance 1162 operation can overtake an L1 set/way cache maintenance operation. 1163 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1164 r0p4, r0p5. 1165 1166endmenu 1167 1168menu "Kernel Features" 1169 1170config HAVE_SMP 1171 bool 1172 help 1173 This option should be selected by machines which have an SMP- 1174 capable CPU. 1175 1176 The only effect of this option is to make the SMP-related 1177 options available to the user for configuration. 1178 1179config SMP 1180 bool "Symmetric Multi-Processing" 1181 depends on CPU_V6K || CPU_V7 1182 depends on GENERIC_CLOCKEVENTS 1183 depends on HAVE_SMP 1184 depends on MMU || ARM_MPU 1185 select IRQ_WORK 1186 help 1187 This enables support for systems with more than one CPU. If you have 1188 a system with only one CPU, say N. If you have a system with more 1189 than one CPU, say Y. 1190 1191 If you say N here, the kernel will run on uni- and multiprocessor 1192 machines, but will use only one CPU of a multiprocessor machine. If 1193 you say Y here, the kernel will run on many, but not all, 1194 uniprocessor machines. On a uniprocessor machine, the kernel 1195 will run faster if you say N here. 1196 1197 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1198 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1199 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1200 1201 If you don't know what to do here, say N. 1202 1203config SMP_ON_UP 1204 bool "Allow booting SMP kernel on uniprocessor systems" 1205 depends on SMP && !XIP_KERNEL && MMU 1206 default y 1207 help 1208 SMP kernels contain instructions which fail on non-SMP processors. 1209 Enabling this option allows the kernel to modify itself to make 1210 these instructions safe. Disabling it allows about 1K of space 1211 savings. 1212 1213 If you don't know what to do here, say Y. 1214 1215config ARM_CPU_TOPOLOGY 1216 bool "Support cpu topology definition" 1217 depends on SMP && CPU_V7 1218 default y 1219 help 1220 Support ARM cpu topology definition. The MPIDR register defines 1221 affinity between processors which is then used to describe the cpu 1222 topology of an ARM System. 1223 1224config SCHED_MC 1225 bool "Multi-core scheduler support" 1226 depends on ARM_CPU_TOPOLOGY 1227 help 1228 Multi-core scheduler support improves the CPU scheduler's decision 1229 making when dealing with multi-core CPU chips at a cost of slightly 1230 increased overhead in some places. If unsure say N here. 1231 1232config SCHED_SMT 1233 bool "SMT scheduler support" 1234 depends on ARM_CPU_TOPOLOGY 1235 help 1236 Improves the CPU scheduler's decision making when dealing with 1237 MultiThreading at a cost of slightly increased overhead in some 1238 places. If unsure say N here. 1239 1240config HAVE_ARM_SCU 1241 bool 1242 help 1243 This option enables support for the ARM snoop control unit 1244 1245config HAVE_ARM_ARCH_TIMER 1246 bool "Architected timer support" 1247 depends on CPU_V7 1248 select ARM_ARCH_TIMER 1249 help 1250 This option enables support for the ARM architected timer 1251 1252config HAVE_ARM_TWD 1253 bool 1254 help 1255 This options enables support for the ARM timer and watchdog unit 1256 1257config MCPM 1258 bool "Multi-Cluster Power Management" 1259 depends on CPU_V7 && SMP 1260 help 1261 This option provides the common power management infrastructure 1262 for (multi-)cluster based systems, such as big.LITTLE based 1263 systems. 1264 1265config MCPM_QUAD_CLUSTER 1266 bool 1267 depends on MCPM 1268 help 1269 To avoid wasting resources unnecessarily, MCPM only supports up 1270 to 2 clusters by default. 1271 Platforms with 3 or 4 clusters that use MCPM must select this 1272 option to allow the additional clusters to be managed. 1273 1274config BIG_LITTLE 1275 bool "big.LITTLE support (Experimental)" 1276 depends on CPU_V7 && SMP 1277 select MCPM 1278 help 1279 This option enables support selections for the big.LITTLE 1280 system architecture. 1281 1282config BL_SWITCHER 1283 bool "big.LITTLE switcher support" 1284 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1285 select CPU_PM 1286 help 1287 The big.LITTLE "switcher" provides the core functionality to 1288 transparently handle transition between a cluster of A15's 1289 and a cluster of A7's in a big.LITTLE system. 1290 1291config BL_SWITCHER_DUMMY_IF 1292 tristate "Simple big.LITTLE switcher user interface" 1293 depends on BL_SWITCHER && DEBUG_KERNEL 1294 help 1295 This is a simple and dummy char dev interface to control 1296 the big.LITTLE switcher core code. It is meant for 1297 debugging purposes only. 1298 1299choice 1300 prompt "Memory split" 1301 depends on MMU 1302 default VMSPLIT_3G 1303 help 1304 Select the desired split between kernel and user memory. 1305 1306 If you are not absolutely sure what you are doing, leave this 1307 option alone! 1308 1309 config VMSPLIT_3G 1310 bool "3G/1G user/kernel split" 1311 config VMSPLIT_3G_OPT 1312 depends on !ARM_LPAE 1313 bool "3G/1G user/kernel split (for full 1G low memory)" 1314 config VMSPLIT_2G 1315 bool "2G/2G user/kernel split" 1316 config VMSPLIT_1G 1317 bool "1G/3G user/kernel split" 1318endchoice 1319 1320config PAGE_OFFSET 1321 hex 1322 default PHYS_OFFSET if !MMU 1323 default 0x40000000 if VMSPLIT_1G 1324 default 0x80000000 if VMSPLIT_2G 1325 default 0xB0000000 if VMSPLIT_3G_OPT 1326 default 0xC0000000 1327 1328config NR_CPUS 1329 int "Maximum number of CPUs (2-32)" 1330 range 2 32 1331 depends on SMP 1332 default "4" 1333 1334config HOTPLUG_CPU 1335 bool "Support for hot-pluggable CPUs" 1336 depends on SMP 1337 select GENERIC_IRQ_MIGRATION 1338 help 1339 Say Y here to experiment with turning CPUs off and on. CPUs 1340 can be controlled through /sys/devices/system/cpu. 1341 1342config ARM_PSCI 1343 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1344 depends on HAVE_ARM_SMCCC 1345 select ARM_PSCI_FW 1346 help 1347 Say Y here if you want Linux to communicate with system firmware 1348 implementing the PSCI specification for CPU-centric power 1349 management operations described in ARM document number ARM DEN 1350 0022A ("Power State Coordination Interface System Software on 1351 ARM processors"). 1352 1353# The GPIO number here must be sorted by descending number. In case of 1354# a multiplatform kernel, we just want the highest value required by the 1355# selected platforms. 1356config ARCH_NR_GPIO 1357 int 1358 default 2048 if ARCH_SOCFPGA 1359 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1360 ARCH_ZYNQ || ARCH_ASPEED 1361 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1362 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1363 default 416 if ARCH_SUNXI 1364 default 392 if ARCH_U8500 1365 default 352 if ARCH_VT8500 1366 default 288 if ARCH_ROCKCHIP 1367 default 264 if MACH_H4700 1368 default 0 1369 help 1370 Maximum number of GPIOs in the system. 1371 1372 If unsure, leave the default value. 1373 1374config HZ_FIXED 1375 int 1376 default 200 if ARCH_EBSA110 1377 default 128 if SOC_AT91RM9200 1378 default 0 1379 1380choice 1381 depends on HZ_FIXED = 0 1382 prompt "Timer frequency" 1383 1384config HZ_100 1385 bool "100 Hz" 1386 1387config HZ_200 1388 bool "200 Hz" 1389 1390config HZ_250 1391 bool "250 Hz" 1392 1393config HZ_300 1394 bool "300 Hz" 1395 1396config HZ_500 1397 bool "500 Hz" 1398 1399config HZ_1000 1400 bool "1000 Hz" 1401 1402endchoice 1403 1404config HZ 1405 int 1406 default HZ_FIXED if HZ_FIXED != 0 1407 default 100 if HZ_100 1408 default 200 if HZ_200 1409 default 250 if HZ_250 1410 default 300 if HZ_300 1411 default 500 if HZ_500 1412 default 1000 1413 1414config SCHED_HRTICK 1415 def_bool HIGH_RES_TIMERS 1416 1417config THUMB2_KERNEL 1418 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1419 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1420 default y if CPU_THUMBONLY 1421 select ARM_UNWIND 1422 help 1423 By enabling this option, the kernel will be compiled in 1424 Thumb-2 mode. 1425 1426 If unsure, say N. 1427 1428config ARM_PATCH_IDIV 1429 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1430 depends on CPU_32v7 && !XIP_KERNEL 1431 default y 1432 help 1433 The ARM compiler inserts calls to __aeabi_idiv() and 1434 __aeabi_uidiv() when it needs to perform division on signed 1435 and unsigned integers. Some v7 CPUs have support for the sdiv 1436 and udiv instructions that can be used to implement those 1437 functions. 1438 1439 Enabling this option allows the kernel to modify itself to 1440 replace the first two instructions of these library functions 1441 with the sdiv or udiv plus "bx lr" instructions when the CPU 1442 it is running on supports them. Typically this will be faster 1443 and less power intensive than running the original library 1444 code to do integer division. 1445 1446config AEABI 1447 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1448 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1449 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1450 help 1451 This option allows for the kernel to be compiled using the latest 1452 ARM ABI (aka EABI). This is only useful if you are using a user 1453 space environment that is also compiled with EABI. 1454 1455 Since there are major incompatibilities between the legacy ABI and 1456 EABI, especially with regard to structure member alignment, this 1457 option also changes the kernel syscall calling convention to 1458 disambiguate both ABIs and allow for backward compatibility support 1459 (selected with CONFIG_OABI_COMPAT). 1460 1461 To use this you need GCC version 4.0.0 or later. 1462 1463config OABI_COMPAT 1464 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1465 depends on AEABI && !THUMB2_KERNEL 1466 help 1467 This option preserves the old syscall interface along with the 1468 new (ARM EABI) one. It also provides a compatibility layer to 1469 intercept syscalls that have structure arguments which layout 1470 in memory differs between the legacy ABI and the new ARM EABI 1471 (only for non "thumb" binaries). This option adds a tiny 1472 overhead to all syscalls and produces a slightly larger kernel. 1473 1474 The seccomp filter system will not be available when this is 1475 selected, since there is no way yet to sensibly distinguish 1476 between calling conventions during filtering. 1477 1478 If you know you'll be using only pure EABI user space then you 1479 can say N here. If this option is not selected and you attempt 1480 to execute a legacy ABI binary then the result will be 1481 UNPREDICTABLE (in fact it can be predicted that it won't work 1482 at all). If in doubt say N. 1483 1484config ARCH_SELECT_MEMORY_MODEL 1485 bool 1486 1487config ARCH_FLATMEM_ENABLE 1488 bool 1489 1490config ARCH_SPARSEMEM_ENABLE 1491 bool 1492 select SPARSEMEM_STATIC if SPARSEMEM 1493 1494config HAVE_ARCH_PFN_VALID 1495 def_bool y 1496 1497config HIGHMEM 1498 bool "High Memory Support" 1499 depends on MMU 1500 help 1501 The address space of ARM processors is only 4 Gigabytes large 1502 and it has to accommodate user address space, kernel address 1503 space as well as some memory mapped IO. That means that, if you 1504 have a large amount of physical memory and/or IO, not all of the 1505 memory can be "permanently mapped" by the kernel. The physical 1506 memory that is not permanently mapped is called "high memory". 1507 1508 Depending on the selected kernel/user memory split, minimum 1509 vmalloc space and actual amount of RAM, you may not need this 1510 option which should result in a slightly faster kernel. 1511 1512 If unsure, say n. 1513 1514config HIGHPTE 1515 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1516 depends on HIGHMEM 1517 default y 1518 help 1519 The VM uses one page of physical memory for each page table. 1520 For systems with a lot of processes, this can use a lot of 1521 precious low memory, eventually leading to low memory being 1522 consumed by page tables. Setting this option will allow 1523 user-space 2nd level page tables to reside in high memory. 1524 1525config CPU_SW_DOMAIN_PAN 1526 bool "Enable use of CPU domains to implement privileged no-access" 1527 depends on MMU && !ARM_LPAE 1528 default y 1529 help 1530 Increase kernel security by ensuring that normal kernel accesses 1531 are unable to access userspace addresses. This can help prevent 1532 use-after-free bugs becoming an exploitable privilege escalation 1533 by ensuring that magic values (such as LIST_POISON) will always 1534 fault when dereferenced. 1535 1536 CPUs with low-vector mappings use a best-efforts implementation. 1537 Their lower 1MB needs to remain accessible for the vectors, but 1538 the remainder of userspace will become appropriately inaccessible. 1539 1540config HW_PERF_EVENTS 1541 def_bool y 1542 depends on ARM_PMU 1543 1544config SYS_SUPPORTS_HUGETLBFS 1545 def_bool y 1546 depends on ARM_LPAE 1547 1548config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1549 def_bool y 1550 depends on ARM_LPAE 1551 1552config ARCH_WANT_GENERAL_HUGETLB 1553 def_bool y 1554 1555config ARM_MODULE_PLTS 1556 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1557 depends on MODULES 1558 default y 1559 help 1560 Allocate PLTs when loading modules so that jumps and calls whose 1561 targets are too far away for their relative offsets to be encoded 1562 in the instructions themselves can be bounced via veneers in the 1563 module's PLT. This allows modules to be allocated in the generic 1564 vmalloc area after the dedicated module memory area has been 1565 exhausted. The modules will use slightly more memory, but after 1566 rounding up to page size, the actual memory footprint is usually 1567 the same. 1568 1569 Disabling this is usually safe for small single-platform 1570 configurations. If unsure, say y. 1571 1572config FORCE_MAX_ZONEORDER 1573 int "Maximum zone order" 1574 default "12" if SOC_AM33XX 1575 default "9" if SA1111 || ARCH_EFM32 1576 default "11" 1577 help 1578 The kernel memory allocator divides physically contiguous memory 1579 blocks into "zones", where each zone is a power of two number of 1580 pages. This option selects the largest power of two that the kernel 1581 keeps in the memory allocator. If you need to allocate very large 1582 blocks of physically contiguous memory, then you may need to 1583 increase this value. 1584 1585 This config option is actually maximum order plus one. For example, 1586 a value of 11 means that the largest free memory block is 2^10 pages. 1587 1588config ALIGNMENT_TRAP 1589 bool 1590 depends on CPU_CP15_MMU 1591 default y if !ARCH_EBSA110 1592 select HAVE_PROC_CPU if PROC_FS 1593 help 1594 ARM processors cannot fetch/store information which is not 1595 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1596 address divisible by 4. On 32-bit ARM processors, these non-aligned 1597 fetch/store instructions will be emulated in software if you say 1598 here, which has a severe performance impact. This is necessary for 1599 correct operation of some network protocols. With an IP-only 1600 configuration it is safe to say N, otherwise say Y. 1601 1602config UACCESS_WITH_MEMCPY 1603 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1604 depends on MMU 1605 default y if CPU_FEROCEON 1606 help 1607 Implement faster copy_to_user and clear_user methods for CPU 1608 cores where a 8-word STM instruction give significantly higher 1609 memory write throughput than a sequence of individual 32bit stores. 1610 1611 A possible side effect is a slight increase in scheduling latency 1612 between threads sharing the same address space if they invoke 1613 such copy operations with large buffers. 1614 1615 However, if the CPU data cache is using a write-allocate mode, 1616 this option is unlikely to provide any performance gain. 1617 1618config PARAVIRT 1619 bool "Enable paravirtualization code" 1620 help 1621 This changes the kernel so it can modify itself when it is run 1622 under a hypervisor, potentially improving performance significantly 1623 over full virtualization. 1624 1625config PARAVIRT_TIME_ACCOUNTING 1626 bool "Paravirtual steal time accounting" 1627 select PARAVIRT 1628 help 1629 Select this option to enable fine granularity task steal time 1630 accounting. Time spent executing other tasks in parallel with 1631 the current vCPU is discounted from the vCPU power. To account for 1632 that, there can be a small performance impact. 1633 1634 If in doubt, say N here. 1635 1636config XEN_DOM0 1637 def_bool y 1638 depends on XEN 1639 1640config XEN 1641 bool "Xen guest support on ARM" 1642 depends on ARM && AEABI && OF 1643 depends on CPU_V7 && !CPU_V6 1644 depends on !GENERIC_ATOMIC64 1645 depends on MMU 1646 select ARCH_DMA_ADDR_T_64BIT 1647 select ARM_PSCI 1648 select SWIOTLB 1649 select SWIOTLB_XEN 1650 select PARAVIRT 1651 help 1652 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1653 1654config STACKPROTECTOR_PER_TASK 1655 bool "Use a unique stack canary value for each task" 1656 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA 1657 select GCC_PLUGIN_ARM_SSP_PER_TASK 1658 default y 1659 help 1660 Due to the fact that GCC uses an ordinary symbol reference from 1661 which to load the value of the stack canary, this value can only 1662 change at reboot time on SMP systems, and all tasks running in the 1663 kernel's address space are forced to use the same canary value for 1664 the entire duration that the system is up. 1665 1666 Enable this option to switch to a different method that uses a 1667 different canary value for each task. 1668 1669endmenu 1670 1671menu "Boot options" 1672 1673config USE_OF 1674 bool "Flattened Device Tree support" 1675 select IRQ_DOMAIN 1676 select OF 1677 help 1678 Include support for flattened device tree machine descriptions. 1679 1680config ATAGS 1681 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1682 default y 1683 help 1684 This is the traditional way of passing data to the kernel at boot 1685 time. If you are solely relying on the flattened device tree (or 1686 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1687 to remove ATAGS support from your kernel binary. If unsure, 1688 leave this to y. 1689 1690config DEPRECATED_PARAM_STRUCT 1691 bool "Provide old way to pass kernel parameters" 1692 depends on ATAGS 1693 help 1694 This was deprecated in 2001 and announced to live on for 5 years. 1695 Some old boot loaders still use this way. 1696 1697# Compressed boot loader in ROM. Yes, we really want to ask about 1698# TEXT and BSS so we preserve their values in the config files. 1699config ZBOOT_ROM_TEXT 1700 hex "Compressed ROM boot loader base address" 1701 default 0x0 1702 help 1703 The physical address at which the ROM-able zImage is to be 1704 placed in the target. Platforms which normally make use of 1705 ROM-able zImage formats normally set this to a suitable 1706 value in their defconfig file. 1707 1708 If ZBOOT_ROM is not enabled, this has no effect. 1709 1710config ZBOOT_ROM_BSS 1711 hex "Compressed ROM boot loader BSS address" 1712 default 0x0 1713 help 1714 The base address of an area of read/write memory in the target 1715 for the ROM-able zImage which must be available while the 1716 decompressor is running. It must be large enough to hold the 1717 entire decompressed kernel plus an additional 128 KiB. 1718 Platforms which normally make use of ROM-able zImage formats 1719 normally set this to a suitable value in their defconfig file. 1720 1721 If ZBOOT_ROM is not enabled, this has no effect. 1722 1723config ZBOOT_ROM 1724 bool "Compressed boot loader in ROM/flash" 1725 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1726 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1727 help 1728 Say Y here if you intend to execute your compressed kernel image 1729 (zImage) directly from ROM or flash. If unsure, say N. 1730 1731config ARM_APPENDED_DTB 1732 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1733 depends on OF 1734 help 1735 With this option, the boot code will look for a device tree binary 1736 (DTB) appended to zImage 1737 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1738 1739 This is meant as a backward compatibility convenience for those 1740 systems with a bootloader that can't be upgraded to accommodate 1741 the documented boot protocol using a device tree. 1742 1743 Beware that there is very little in terms of protection against 1744 this option being confused by leftover garbage in memory that might 1745 look like a DTB header after a reboot if no actual DTB is appended 1746 to zImage. Do not leave this option active in a production kernel 1747 if you don't intend to always append a DTB. Proper passing of the 1748 location into r2 of a bootloader provided DTB is always preferable 1749 to this option. 1750 1751config ARM_ATAG_DTB_COMPAT 1752 bool "Supplement the appended DTB with traditional ATAG information" 1753 depends on ARM_APPENDED_DTB 1754 help 1755 Some old bootloaders can't be updated to a DTB capable one, yet 1756 they provide ATAGs with memory configuration, the ramdisk address, 1757 the kernel cmdline string, etc. Such information is dynamically 1758 provided by the bootloader and can't always be stored in a static 1759 DTB. To allow a device tree enabled kernel to be used with such 1760 bootloaders, this option allows zImage to extract the information 1761 from the ATAG list and store it at run time into the appended DTB. 1762 1763choice 1764 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1765 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1766 1767config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1768 bool "Use bootloader kernel arguments if available" 1769 help 1770 Uses the command-line options passed by the boot loader instead of 1771 the device tree bootargs property. If the boot loader doesn't provide 1772 any, the device tree bootargs property will be used. 1773 1774config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1775 bool "Extend with bootloader kernel arguments" 1776 help 1777 The command-line arguments provided by the boot loader will be 1778 appended to the the device tree bootargs property. 1779 1780endchoice 1781 1782config CMDLINE 1783 string "Default kernel command string" 1784 default "" 1785 help 1786 On some architectures (EBSA110 and CATS), there is currently no way 1787 for the boot loader to pass arguments to the kernel. For these 1788 architectures, you should supply some command-line options at build 1789 time by entering them here. As a minimum, you should specify the 1790 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1791 1792choice 1793 prompt "Kernel command line type" if CMDLINE != "" 1794 default CMDLINE_FROM_BOOTLOADER 1795 1796config CMDLINE_FROM_BOOTLOADER 1797 bool "Use bootloader kernel arguments if available" 1798 help 1799 Uses the command-line options passed by the boot loader. If 1800 the boot loader doesn't provide any, the default kernel command 1801 string provided in CMDLINE will be used. 1802 1803config CMDLINE_EXTEND 1804 bool "Extend bootloader kernel arguments" 1805 help 1806 The command-line arguments provided by the boot loader will be 1807 appended to the default kernel command string. 1808 1809config CMDLINE_FORCE 1810 bool "Always use the default kernel command string" 1811 help 1812 Always use the default kernel command string, even if the boot 1813 loader passes other arguments to the kernel. 1814 This is useful if you cannot or don't want to change the 1815 command-line options your boot loader passes to the kernel. 1816endchoice 1817 1818config XIP_KERNEL 1819 bool "Kernel Execute-In-Place from ROM" 1820 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1821 help 1822 Execute-In-Place allows the kernel to run from non-volatile storage 1823 directly addressable by the CPU, such as NOR flash. This saves RAM 1824 space since the text section of the kernel is not loaded from flash 1825 to RAM. Read-write sections, such as the data section and stack, 1826 are still copied to RAM. The XIP kernel is not compressed since 1827 it has to run directly from flash, so it will take more space to 1828 store it. The flash address used to link the kernel object files, 1829 and for storing it, is configuration dependent. Therefore, if you 1830 say Y here, you must know the proper physical address where to 1831 store the kernel image depending on your own flash memory usage. 1832 1833 Also note that the make target becomes "make xipImage" rather than 1834 "make zImage" or "make Image". The final kernel binary to put in 1835 ROM memory will be arch/arm/boot/xipImage. 1836 1837 If unsure, say N. 1838 1839config XIP_PHYS_ADDR 1840 hex "XIP Kernel Physical Location" 1841 depends on XIP_KERNEL 1842 default "0x00080000" 1843 help 1844 This is the physical address in your flash memory the kernel will 1845 be linked for and stored to. This address is dependent on your 1846 own flash usage. 1847 1848config XIP_DEFLATED_DATA 1849 bool "Store kernel .data section compressed in ROM" 1850 depends on XIP_KERNEL 1851 select ZLIB_INFLATE 1852 help 1853 Before the kernel is actually executed, its .data section has to be 1854 copied to RAM from ROM. This option allows for storing that data 1855 in compressed form and decompressed to RAM rather than merely being 1856 copied, saving some precious ROM space. A possible drawback is a 1857 slightly longer boot delay. 1858 1859config KEXEC 1860 bool "Kexec system call (EXPERIMENTAL)" 1861 depends on (!SMP || PM_SLEEP_SMP) 1862 depends on MMU 1863 select KEXEC_CORE 1864 help 1865 kexec is a system call that implements the ability to shutdown your 1866 current kernel, and to start another kernel. It is like a reboot 1867 but it is independent of the system firmware. And like a reboot 1868 you can start any kernel with it, not just Linux. 1869 1870 It is an ongoing process to be certain the hardware in a machine 1871 is properly shutdown, so do not be surprised if this code does not 1872 initially work for you. 1873 1874config ATAGS_PROC 1875 bool "Export atags in procfs" 1876 depends on ATAGS && KEXEC 1877 default y 1878 help 1879 Should the atags used to boot the kernel be exported in an "atags" 1880 file in procfs. Useful with kexec. 1881 1882config CRASH_DUMP 1883 bool "Build kdump crash kernel (EXPERIMENTAL)" 1884 help 1885 Generate crash dump after being started by kexec. This should 1886 be normally only set in special crash dump kernels which are 1887 loaded in the main kernel with kexec-tools into a specially 1888 reserved region and then later executed after a crash by 1889 kdump/kexec. The crash dump kernel must be compiled to a 1890 memory address not used by the main kernel 1891 1892 For more details see Documentation/admin-guide/kdump/kdump.rst 1893 1894config AUTO_ZRELADDR 1895 bool "Auto calculation of the decompressed kernel image address" 1896 help 1897 ZRELADDR is the physical address where the decompressed kernel 1898 image will be placed. If AUTO_ZRELADDR is selected, the address 1899 will be determined at run-time by masking the current IP with 1900 0xf8000000. This assumes the zImage being placed in the first 128MB 1901 from start of memory. 1902 1903config EFI_STUB 1904 bool 1905 1906config EFI 1907 bool "UEFI runtime support" 1908 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1909 select UCS2_STRING 1910 select EFI_PARAMS_FROM_FDT 1911 select EFI_STUB 1912 select EFI_GENERIC_STUB 1913 select EFI_RUNTIME_WRAPPERS 1914 help 1915 This option provides support for runtime services provided 1916 by UEFI firmware (such as non-volatile variables, realtime 1917 clock, and platform reset). A UEFI stub is also provided to 1918 allow the kernel to be booted as an EFI application. This 1919 is only useful for kernels that may run on systems that have 1920 UEFI firmware. 1921 1922config DMI 1923 bool "Enable support for SMBIOS (DMI) tables" 1924 depends on EFI 1925 default y 1926 help 1927 This enables SMBIOS/DMI feature for systems. 1928 1929 This option is only useful on systems that have UEFI firmware. 1930 However, even with this option, the resultant kernel should 1931 continue to boot on existing non-UEFI platforms. 1932 1933 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1934 i.e., the the practice of identifying the platform via DMI to 1935 decide whether certain workarounds for buggy hardware and/or 1936 firmware need to be enabled. This would require the DMI subsystem 1937 to be enabled much earlier than we do on ARM, which is non-trivial. 1938 1939endmenu 1940 1941menu "CPU Power Management" 1942 1943source "drivers/cpufreq/Kconfig" 1944 1945source "drivers/cpuidle/Kconfig" 1946 1947endmenu 1948 1949menu "Floating point emulation" 1950 1951comment "At least one emulation must be selected" 1952 1953config FPE_NWFPE 1954 bool "NWFPE math emulation" 1955 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1956 help 1957 Say Y to include the NWFPE floating point emulator in the kernel. 1958 This is necessary to run most binaries. Linux does not currently 1959 support floating point hardware so you need to say Y here even if 1960 your machine has an FPA or floating point co-processor podule. 1961 1962 You may say N here if you are going to load the Acorn FPEmulator 1963 early in the bootup. 1964 1965config FPE_NWFPE_XP 1966 bool "Support extended precision" 1967 depends on FPE_NWFPE 1968 help 1969 Say Y to include 80-bit support in the kernel floating-point 1970 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1971 Note that gcc does not generate 80-bit operations by default, 1972 so in most cases this option only enlarges the size of the 1973 floating point emulator without any good reason. 1974 1975 You almost surely want to say N here. 1976 1977config FPE_FASTFPE 1978 bool "FastFPE math emulation (EXPERIMENTAL)" 1979 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1980 help 1981 Say Y here to include the FAST floating point emulator in the kernel. 1982 This is an experimental much faster emulator which now also has full 1983 precision for the mantissa. It does not support any exceptions. 1984 It is very simple, and approximately 3-6 times faster than NWFPE. 1985 1986 It should be sufficient for most programs. It may be not suitable 1987 for scientific calculations, but you have to check this for yourself. 1988 If you do not feel you need a faster FP emulation you should better 1989 choose NWFPE. 1990 1991config VFP 1992 bool "VFP-format floating point maths" 1993 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1994 help 1995 Say Y to include VFP support code in the kernel. This is needed 1996 if your hardware includes a VFP unit. 1997 1998 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1999 release notes and additional status information. 2000 2001 Say N if your target does not have VFP hardware. 2002 2003config VFPv3 2004 bool 2005 depends on VFP 2006 default y if CPU_V7 2007 2008config NEON 2009 bool "Advanced SIMD (NEON) Extension support" 2010 depends on VFPv3 && CPU_V7 2011 help 2012 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2013 Extension. 2014 2015config KERNEL_MODE_NEON 2016 bool "Support for NEON in kernel mode" 2017 depends on NEON && AEABI 2018 help 2019 Say Y to include support for NEON in kernel mode. 2020 2021endmenu 2022 2023menu "Power management options" 2024 2025source "kernel/power/Kconfig" 2026 2027config ARCH_SUSPEND_POSSIBLE 2028 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2029 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2030 def_bool y 2031 2032config ARM_CPU_SUSPEND 2033 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2034 depends on ARCH_SUSPEND_POSSIBLE 2035 2036config ARCH_HIBERNATION_POSSIBLE 2037 bool 2038 depends on MMU 2039 default y if ARCH_SUSPEND_POSSIBLE 2040 2041endmenu 2042 2043source "drivers/firmware/Kconfig" 2044 2045if CRYPTO 2046source "arch/arm/crypto/Kconfig" 2047endif 2048 2049source "arch/arm/Kconfig.assembler" 2050