1menu "mpc85xx CPU" 2 depends on MPC85xx 3 4config SYS_CPU 5 default "mpc85xx" 6 7config CMD_ERRATA 8 bool "Enable the 'errata' command" 9 depends on MPC85xx 10 default y 11 help 12 This enables the 'errata' command which displays a list of errata 13 work-arounds which are enabled for the current board. 14 15choice 16 prompt "Target select" 17 optional 18 19config TARGET_SBC8548 20 bool "Support sbc8548" 21 select ARCH_MPC8548 22 23config TARGET_SOCRATES 24 bool "Support socrates" 25 select ARCH_MPC8544 26 27config TARGET_B4420QDS 28 bool "Support B4420QDS" 29 select ARCH_B4420 30 select SUPPORT_SPL 31 select PHYS_64BIT 32 imply PANIC_HANG 33 34config TARGET_B4860QDS 35 bool "Support B4860QDS" 36 select ARCH_B4860 37 select BOARD_LATE_INIT if CHAIN_OF_TRUST 38 select SUPPORT_SPL 39 select PHYS_64BIT 40 imply PANIC_HANG 41 42config TARGET_BSC9131RDB 43 bool "Support BSC9131RDB" 44 select ARCH_BSC9131 45 select SUPPORT_SPL 46 select BOARD_EARLY_INIT_F 47 48config TARGET_BSC9132QDS 49 bool "Support BSC9132QDS" 50 select ARCH_BSC9132 51 select BOARD_LATE_INIT if CHAIN_OF_TRUST 52 select SUPPORT_SPL 53 select BOARD_EARLY_INIT_F 54 55config TARGET_C29XPCIE 56 bool "Support C29XPCIE" 57 select ARCH_C29X 58 select BOARD_LATE_INIT if CHAIN_OF_TRUST 59 select SUPPORT_SPL 60 select SUPPORT_TPL 61 select PHYS_64BIT 62 imply PANIC_HANG 63 64config TARGET_P3041DS 65 bool "Support P3041DS" 66 select PHYS_64BIT 67 select ARCH_P3041 68 select BOARD_LATE_INIT if CHAIN_OF_TRUST 69 imply CMD_SATA 70 imply PANIC_HANG 71 72config TARGET_P4080DS 73 bool "Support P4080DS" 74 select PHYS_64BIT 75 select ARCH_P4080 76 select BOARD_LATE_INIT if CHAIN_OF_TRUST 77 imply CMD_SATA 78 imply PANIC_HANG 79 80config TARGET_P5020DS 81 bool "Support P5020DS" 82 select PHYS_64BIT 83 select ARCH_P5020 84 select BOARD_LATE_INIT if CHAIN_OF_TRUST 85 imply CMD_SATA 86 imply PANIC_HANG 87 88config TARGET_P5040DS 89 bool "Support P5040DS" 90 select PHYS_64BIT 91 select ARCH_P5040 92 select BOARD_LATE_INIT if CHAIN_OF_TRUST 93 imply CMD_SATA 94 imply PANIC_HANG 95 96config TARGET_MPC8536DS 97 bool "Support MPC8536DS" 98 select ARCH_MPC8536 99# Use DDR3 controller with DDR2 DIMMs on this board 100 select SYS_FSL_DDRC_GEN3 101 imply CMD_SATA 102 103config TARGET_MPC8541CDS 104 bool "Support MPC8541CDS" 105 select ARCH_MPC8541 106 107config TARGET_MPC8544DS 108 bool "Support MPC8544DS" 109 select ARCH_MPC8544 110 imply PANIC_HANG 111 112config TARGET_MPC8548CDS 113 bool "Support MPC8548CDS" 114 select ARCH_MPC8548 115 116config TARGET_MPC8555CDS 117 bool "Support MPC8555CDS" 118 select ARCH_MPC8555 119 120config TARGET_MPC8568MDS 121 bool "Support MPC8568MDS" 122 select ARCH_MPC8568 123 124config TARGET_MPC8569MDS 125 bool "Support MPC8569MDS" 126 select ARCH_MPC8569 127 128config TARGET_MPC8572DS 129 bool "Support MPC8572DS" 130 select ARCH_MPC8572 131# Use DDR3 controller with DDR2 DIMMs on this board 132 select SYS_FSL_DDRC_GEN3 133 imply SCSI 134 imply PANIC_HANG 135 136config TARGET_P1010RDB_PA 137 bool "Support P1010RDB_PA" 138 select ARCH_P1010 139 select BOARD_LATE_INIT if CHAIN_OF_TRUST 140 select SUPPORT_SPL 141 select SUPPORT_TPL 142 imply CMD_EEPROM 143 imply CMD_SATA 144 imply PANIC_HANG 145 146config TARGET_P1010RDB_PB 147 bool "Support P1010RDB_PB" 148 select ARCH_P1010 149 select BOARD_LATE_INIT if CHAIN_OF_TRUST 150 select SUPPORT_SPL 151 select SUPPORT_TPL 152 imply CMD_EEPROM 153 imply CMD_SATA 154 imply PANIC_HANG 155 156config TARGET_P1022DS 157 bool "Support P1022DS" 158 select ARCH_P1022 159 select SUPPORT_SPL 160 select SUPPORT_TPL 161 imply CMD_SATA 162 163config TARGET_P1023RDB 164 bool "Support P1023RDB" 165 select ARCH_P1023 166 imply CMD_EEPROM 167 imply PANIC_HANG 168 169config TARGET_P1020MBG 170 bool "Support P1020MBG-PC" 171 select SUPPORT_SPL 172 select SUPPORT_TPL 173 select ARCH_P1020 174 imply CMD_EEPROM 175 imply CMD_SATA 176 imply PANIC_HANG 177 178config TARGET_P1020RDB_PC 179 bool "Support P1020RDB-PC" 180 select SUPPORT_SPL 181 select SUPPORT_TPL 182 select ARCH_P1020 183 imply CMD_EEPROM 184 imply CMD_SATA 185 imply PANIC_HANG 186 187config TARGET_P1020RDB_PD 188 bool "Support P1020RDB-PD" 189 select SUPPORT_SPL 190 select SUPPORT_TPL 191 select ARCH_P1020 192 imply CMD_EEPROM 193 imply CMD_SATA 194 imply PANIC_HANG 195 196config TARGET_P1020UTM 197 bool "Support P1020UTM" 198 select SUPPORT_SPL 199 select SUPPORT_TPL 200 select ARCH_P1020 201 imply CMD_EEPROM 202 imply CMD_SATA 203 imply PANIC_HANG 204 205config TARGET_P1021RDB 206 bool "Support P1021RDB" 207 select SUPPORT_SPL 208 select SUPPORT_TPL 209 select ARCH_P1021 210 imply CMD_EEPROM 211 imply CMD_SATA 212 imply PANIC_HANG 213 214config TARGET_P1024RDB 215 bool "Support P1024RDB" 216 select SUPPORT_SPL 217 select SUPPORT_TPL 218 select ARCH_P1024 219 imply CMD_EEPROM 220 imply CMD_SATA 221 imply PANIC_HANG 222 223config TARGET_P1025RDB 224 bool "Support P1025RDB" 225 select SUPPORT_SPL 226 select SUPPORT_TPL 227 select ARCH_P1025 228 imply CMD_EEPROM 229 imply CMD_SATA 230 231config TARGET_P2020RDB 232 bool "Support P2020RDB-PC" 233 select SUPPORT_SPL 234 select SUPPORT_TPL 235 select ARCH_P2020 236 imply CMD_EEPROM 237 imply CMD_SATA 238 239config TARGET_P1_TWR 240 bool "Support p1_twr" 241 select ARCH_P1025 242 243config TARGET_P2041RDB 244 bool "Support P2041RDB" 245 select ARCH_P2041 246 select BOARD_LATE_INIT if CHAIN_OF_TRUST 247 select PHYS_64BIT 248 imply CMD_SATA 249 250config TARGET_QEMU_PPCE500 251 bool "Support qemu-ppce500" 252 select ARCH_QEMU_E500 253 select PHYS_64BIT 254 255config TARGET_T1024QDS 256 bool "Support T1024QDS" 257 select ARCH_T1024 258 select BOARD_LATE_INIT if CHAIN_OF_TRUST 259 select SUPPORT_SPL 260 select PHYS_64BIT 261 imply CMD_EEPROM 262 imply CMD_SATA 263 264config TARGET_T1023RDB 265 bool "Support T1023RDB" 266 select ARCH_T1023 267 select BOARD_LATE_INIT if CHAIN_OF_TRUST 268 select SUPPORT_SPL 269 select PHYS_64BIT 270 imply CMD_EEPROM 271 imply PANIC_HANG 272 273config TARGET_T1024RDB 274 bool "Support T1024RDB" 275 select ARCH_T1024 276 select BOARD_LATE_INIT if CHAIN_OF_TRUST 277 select SUPPORT_SPL 278 select PHYS_64BIT 279 imply CMD_EEPROM 280 imply PANIC_HANG 281 282config TARGET_T1040QDS 283 bool "Support T1040QDS" 284 select ARCH_T1040 285 select BOARD_LATE_INIT if CHAIN_OF_TRUST 286 select PHYS_64BIT 287 imply CMD_EEPROM 288 imply CMD_SATA 289 imply PANIC_HANG 290 291config TARGET_T1040RDB 292 bool "Support T1040RDB" 293 select ARCH_T1040 294 select BOARD_LATE_INIT if CHAIN_OF_TRUST 295 select SUPPORT_SPL 296 select PHYS_64BIT 297 imply CMD_SATA 298 imply PANIC_HANG 299 300config TARGET_T1040D4RDB 301 bool "Support T1040D4RDB" 302 select ARCH_T1040 303 select BOARD_LATE_INIT if CHAIN_OF_TRUST 304 select SUPPORT_SPL 305 select PHYS_64BIT 306 imply CMD_SATA 307 imply PANIC_HANG 308 309config TARGET_T1042RDB 310 bool "Support T1042RDB" 311 select ARCH_T1042 312 select BOARD_LATE_INIT if CHAIN_OF_TRUST 313 select SUPPORT_SPL 314 select PHYS_64BIT 315 imply CMD_SATA 316 317config TARGET_T1042D4RDB 318 bool "Support T1042D4RDB" 319 select ARCH_T1042 320 select BOARD_LATE_INIT if CHAIN_OF_TRUST 321 select SUPPORT_SPL 322 select PHYS_64BIT 323 imply CMD_SATA 324 imply PANIC_HANG 325 326config TARGET_T1042RDB_PI 327 bool "Support T1042RDB_PI" 328 select ARCH_T1042 329 select BOARD_LATE_INIT if CHAIN_OF_TRUST 330 select SUPPORT_SPL 331 select PHYS_64BIT 332 imply CMD_SATA 333 imply PANIC_HANG 334 335config TARGET_T2080QDS 336 bool "Support T2080QDS" 337 select ARCH_T2080 338 select BOARD_LATE_INIT if CHAIN_OF_TRUST 339 select SUPPORT_SPL 340 select PHYS_64BIT 341 imply CMD_SATA 342 343config TARGET_T2080RDB 344 bool "Support T2080RDB" 345 select ARCH_T2080 346 select BOARD_LATE_INIT if CHAIN_OF_TRUST 347 select SUPPORT_SPL 348 select PHYS_64BIT 349 imply CMD_SATA 350 imply PANIC_HANG 351 352config TARGET_T2081QDS 353 bool "Support T2081QDS" 354 select ARCH_T2081 355 select SUPPORT_SPL 356 select PHYS_64BIT 357 358config TARGET_T4160QDS 359 bool "Support T4160QDS" 360 select ARCH_T4160 361 select BOARD_LATE_INIT if CHAIN_OF_TRUST 362 select SUPPORT_SPL 363 select PHYS_64BIT 364 imply CMD_SATA 365 imply PANIC_HANG 366 367config TARGET_T4160RDB 368 bool "Support T4160RDB" 369 select ARCH_T4160 370 select SUPPORT_SPL 371 select PHYS_64BIT 372 imply PANIC_HANG 373 374config TARGET_T4240QDS 375 bool "Support T4240QDS" 376 select ARCH_T4240 377 select BOARD_LATE_INIT if CHAIN_OF_TRUST 378 select SUPPORT_SPL 379 select PHYS_64BIT 380 imply CMD_SATA 381 imply PANIC_HANG 382 383config TARGET_T4240RDB 384 bool "Support T4240RDB" 385 select ARCH_T4240 386 select SUPPORT_SPL 387 select PHYS_64BIT 388 imply CMD_SATA 389 imply PANIC_HANG 390 391config TARGET_CONTROLCENTERD 392 bool "Support controlcenterd" 393 select ARCH_P1022 394 395config TARGET_KMP204X 396 bool "Support kmp204x" 397 select ARCH_P2041 398 select PHYS_64BIT 399 imply CMD_CRAMFS 400 imply FS_CRAMFS 401 402config TARGET_XPEDITE520X 403 bool "Support xpedite520x" 404 select ARCH_MPC8548 405 406config TARGET_XPEDITE537X 407 bool "Support xpedite537x" 408 select ARCH_MPC8572 409# Use DDR3 controller with DDR2 DIMMs on this board 410 select SYS_FSL_DDRC_GEN3 411 412config TARGET_XPEDITE550X 413 bool "Support xpedite550x" 414 select ARCH_P2020 415 416config TARGET_UCP1020 417 bool "Support uCP1020" 418 select ARCH_P1020 419 imply CMD_SATA 420 imply PANIC_HANG 421 422config TARGET_CYRUS_P5020 423 bool "Support Varisys Cyrus P5020" 424 select ARCH_P5020 425 select PHYS_64BIT 426 imply PANIC_HANG 427 428config TARGET_CYRUS_P5040 429 bool "Support Varisys Cyrus P5040" 430 select ARCH_P5040 431 select PHYS_64BIT 432 imply PANIC_HANG 433 434endchoice 435 436config ARCH_B4420 437 bool 438 select E500MC 439 select E6500 440 select FSL_LAW 441 select SYS_FSL_DDR_VER_47 442 select SYS_FSL_ERRATUM_A004477 443 select SYS_FSL_ERRATUM_A005871 444 select SYS_FSL_ERRATUM_A006379 445 select SYS_FSL_ERRATUM_A006384 446 select SYS_FSL_ERRATUM_A006475 447 select SYS_FSL_ERRATUM_A006593 448 select SYS_FSL_ERRATUM_A007075 449 select SYS_FSL_ERRATUM_A007186 450 select SYS_FSL_ERRATUM_A007212 451 select SYS_FSL_ERRATUM_A009942 452 select SYS_FSL_HAS_DDR3 453 select SYS_FSL_HAS_SEC 454 select SYS_FSL_QORIQ_CHASSIS2 455 select SYS_FSL_SEC_BE 456 select SYS_FSL_SEC_COMPAT_4 457 select SYS_PPC64 458 select FSL_IFC 459 imply CMD_EEPROM 460 imply CMD_NAND 461 imply CMD_REGINFO 462 463config ARCH_B4860 464 bool 465 select E500MC 466 select E6500 467 select FSL_LAW 468 select SYS_FSL_DDR_VER_47 469 select SYS_FSL_ERRATUM_A004477 470 select SYS_FSL_ERRATUM_A005871 471 select SYS_FSL_ERRATUM_A006379 472 select SYS_FSL_ERRATUM_A006384 473 select SYS_FSL_ERRATUM_A006475 474 select SYS_FSL_ERRATUM_A006593 475 select SYS_FSL_ERRATUM_A007075 476 select SYS_FSL_ERRATUM_A007186 477 select SYS_FSL_ERRATUM_A007212 478 select SYS_FSL_ERRATUM_A007907 479 select SYS_FSL_ERRATUM_A009942 480 select SYS_FSL_HAS_DDR3 481 select SYS_FSL_HAS_SEC 482 select SYS_FSL_QORIQ_CHASSIS2 483 select SYS_FSL_SEC_BE 484 select SYS_FSL_SEC_COMPAT_4 485 select SYS_PPC64 486 select FSL_IFC 487 imply CMD_EEPROM 488 imply CMD_NAND 489 imply CMD_REGINFO 490 491config ARCH_BSC9131 492 bool 493 select FSL_LAW 494 select SYS_FSL_DDR_VER_44 495 select SYS_FSL_ERRATUM_A004477 496 select SYS_FSL_ERRATUM_A005125 497 select SYS_FSL_ERRATUM_ESDHC111 498 select SYS_FSL_HAS_DDR3 499 select SYS_FSL_HAS_SEC 500 select SYS_FSL_SEC_BE 501 select SYS_FSL_SEC_COMPAT_4 502 select FSL_IFC 503 imply CMD_EEPROM 504 imply CMD_NAND 505 imply CMD_REGINFO 506 507config ARCH_BSC9132 508 bool 509 select FSL_LAW 510 select SYS_FSL_DDR_VER_46 511 select SYS_FSL_ERRATUM_A004477 512 select SYS_FSL_ERRATUM_A005125 513 select SYS_FSL_ERRATUM_A005434 514 select SYS_FSL_ERRATUM_ESDHC111 515 select SYS_FSL_ERRATUM_I2C_A004447 516 select SYS_FSL_ERRATUM_IFC_A002769 517 select SYS_FSL_HAS_DDR3 518 select SYS_FSL_HAS_SEC 519 select SYS_FSL_SEC_BE 520 select SYS_FSL_SEC_COMPAT_4 521 select SYS_PPC_E500_USE_DEBUG_TLB 522 select FSL_IFC 523 imply CMD_EEPROM 524 imply CMD_MTDPARTS 525 imply CMD_NAND 526 imply CMD_PCI 527 imply CMD_REGINFO 528 529config ARCH_C29X 530 bool 531 select FSL_LAW 532 select SYS_FSL_DDR_VER_46 533 select SYS_FSL_ERRATUM_A005125 534 select SYS_FSL_ERRATUM_ESDHC111 535 select SYS_FSL_HAS_DDR3 536 select SYS_FSL_HAS_SEC 537 select SYS_FSL_SEC_BE 538 select SYS_FSL_SEC_COMPAT_6 539 select SYS_PPC_E500_USE_DEBUG_TLB 540 select FSL_IFC 541 imply CMD_NAND 542 imply CMD_PCI 543 imply CMD_REGINFO 544 545config ARCH_MPC8536 546 bool 547 select FSL_LAW 548 select SYS_FSL_ERRATUM_A004508 549 select SYS_FSL_ERRATUM_A005125 550 select SYS_FSL_HAS_DDR2 551 select SYS_FSL_HAS_DDR3 552 select SYS_FSL_HAS_SEC 553 select SYS_FSL_SEC_BE 554 select SYS_FSL_SEC_COMPAT_2 555 select SYS_PPC_E500_USE_DEBUG_TLB 556 select FSL_ELBC 557 imply CMD_NAND 558 imply CMD_SATA 559 imply CMD_REGINFO 560 561config ARCH_MPC8540 562 bool 563 select FSL_LAW 564 select SYS_FSL_HAS_DDR1 565 566config ARCH_MPC8541 567 bool 568 select FSL_LAW 569 select SYS_FSL_HAS_DDR1 570 select SYS_FSL_HAS_SEC 571 select SYS_FSL_SEC_BE 572 select SYS_FSL_SEC_COMPAT_2 573 574config ARCH_MPC8544 575 bool 576 select FSL_LAW 577 select SYS_FSL_ERRATUM_A005125 578 select SYS_FSL_HAS_DDR2 579 select SYS_FSL_HAS_SEC 580 select SYS_FSL_SEC_BE 581 select SYS_FSL_SEC_COMPAT_2 582 select SYS_PPC_E500_USE_DEBUG_TLB 583 select FSL_ELBC 584 585config ARCH_MPC8548 586 bool 587 select FSL_LAW 588 select SYS_FSL_ERRATUM_A005125 589 select SYS_FSL_ERRATUM_NMG_DDR120 590 select SYS_FSL_ERRATUM_NMG_LBC103 591 select SYS_FSL_ERRATUM_NMG_ETSEC129 592 select SYS_FSL_ERRATUM_I2C_A004447 593 select SYS_FSL_HAS_DDR2 594 select SYS_FSL_HAS_DDR1 595 select SYS_FSL_HAS_SEC 596 select SYS_FSL_SEC_BE 597 select SYS_FSL_SEC_COMPAT_2 598 select SYS_PPC_E500_USE_DEBUG_TLB 599 imply CMD_REGINFO 600 601config ARCH_MPC8555 602 bool 603 select FSL_LAW 604 select SYS_FSL_HAS_DDR1 605 select SYS_FSL_HAS_SEC 606 select SYS_FSL_SEC_BE 607 select SYS_FSL_SEC_COMPAT_2 608 609config ARCH_MPC8560 610 bool 611 select FSL_LAW 612 select SYS_FSL_HAS_DDR1 613 614config ARCH_MPC8568 615 bool 616 select FSL_LAW 617 select SYS_FSL_HAS_DDR2 618 select SYS_FSL_HAS_SEC 619 select SYS_FSL_SEC_BE 620 select SYS_FSL_SEC_COMPAT_2 621 622config ARCH_MPC8569 623 bool 624 select FSL_LAW 625 select SYS_FSL_ERRATUM_A004508 626 select SYS_FSL_ERRATUM_A005125 627 select SYS_FSL_HAS_DDR3 628 select SYS_FSL_HAS_SEC 629 select SYS_FSL_SEC_BE 630 select SYS_FSL_SEC_COMPAT_2 631 select FSL_ELBC 632 imply CMD_NAND 633 634config ARCH_MPC8572 635 bool 636 select FSL_LAW 637 select SYS_FSL_ERRATUM_A004508 638 select SYS_FSL_ERRATUM_A005125 639 select SYS_FSL_ERRATUM_DDR_115 640 select SYS_FSL_ERRATUM_DDR111_DDR134 641 select SYS_FSL_HAS_DDR2 642 select SYS_FSL_HAS_DDR3 643 select SYS_FSL_HAS_SEC 644 select SYS_FSL_SEC_BE 645 select SYS_FSL_SEC_COMPAT_2 646 select SYS_PPC_E500_USE_DEBUG_TLB 647 select FSL_ELBC 648 imply CMD_NAND 649 650config ARCH_P1010 651 bool 652 select FSL_LAW 653 select SYS_FSL_ERRATUM_A004477 654 select SYS_FSL_ERRATUM_A004508 655 select SYS_FSL_ERRATUM_A005125 656 select SYS_FSL_ERRATUM_A006261 657 select SYS_FSL_ERRATUM_A007075 658 select SYS_FSL_ERRATUM_ESDHC111 659 select SYS_FSL_ERRATUM_I2C_A004447 660 select SYS_FSL_ERRATUM_IFC_A002769 661 select SYS_FSL_ERRATUM_P1010_A003549 662 select SYS_FSL_ERRATUM_SEC_A003571 663 select SYS_FSL_ERRATUM_IFC_A003399 664 select SYS_FSL_HAS_DDR3 665 select SYS_FSL_HAS_SEC 666 select SYS_FSL_SEC_BE 667 select SYS_FSL_SEC_COMPAT_4 668 select SYS_PPC_E500_USE_DEBUG_TLB 669 select FSL_IFC 670 imply CMD_EEPROM 671 imply CMD_MTDPARTS 672 imply CMD_NAND 673 imply CMD_SATA 674 imply CMD_PCI 675 imply CMD_REGINFO 676 677config ARCH_P1011 678 bool 679 select FSL_LAW 680 select SYS_FSL_ERRATUM_A004508 681 select SYS_FSL_ERRATUM_A005125 682 select SYS_FSL_ERRATUM_ELBC_A001 683 select SYS_FSL_ERRATUM_ESDHC111 684 select SYS_FSL_HAS_DDR3 685 select SYS_FSL_HAS_SEC 686 select SYS_FSL_SEC_BE 687 select SYS_FSL_SEC_COMPAT_2 688 select SYS_PPC_E500_USE_DEBUG_TLB 689 select FSL_ELBC 690 691config ARCH_P1020 692 bool 693 select FSL_LAW 694 select SYS_FSL_ERRATUM_A004508 695 select SYS_FSL_ERRATUM_A005125 696 select SYS_FSL_ERRATUM_ELBC_A001 697 select SYS_FSL_ERRATUM_ESDHC111 698 select SYS_FSL_HAS_DDR3 699 select SYS_FSL_HAS_SEC 700 select SYS_FSL_SEC_BE 701 select SYS_FSL_SEC_COMPAT_2 702 select SYS_PPC_E500_USE_DEBUG_TLB 703 select FSL_ELBC 704 imply CMD_NAND 705 imply CMD_SATA 706 imply CMD_PCI 707 imply CMD_REGINFO 708 709config ARCH_P1021 710 bool 711 select FSL_LAW 712 select SYS_FSL_ERRATUM_A004508 713 select SYS_FSL_ERRATUM_A005125 714 select SYS_FSL_ERRATUM_ELBC_A001 715 select SYS_FSL_ERRATUM_ESDHC111 716 select SYS_FSL_HAS_DDR3 717 select SYS_FSL_HAS_SEC 718 select SYS_FSL_SEC_BE 719 select SYS_FSL_SEC_COMPAT_2 720 select SYS_PPC_E500_USE_DEBUG_TLB 721 select FSL_ELBC 722 imply CMD_REGINFO 723 imply CMD_NAND 724 imply CMD_SATA 725 imply CMD_REGINFO 726 727config ARCH_P1022 728 bool 729 select FSL_LAW 730 select SYS_FSL_ERRATUM_A004477 731 select SYS_FSL_ERRATUM_A004508 732 select SYS_FSL_ERRATUM_A005125 733 select SYS_FSL_ERRATUM_ELBC_A001 734 select SYS_FSL_ERRATUM_ESDHC111 735 select SYS_FSL_ERRATUM_SATA_A001 736 select SYS_FSL_HAS_DDR3 737 select SYS_FSL_HAS_SEC 738 select SYS_FSL_SEC_BE 739 select SYS_FSL_SEC_COMPAT_2 740 select SYS_PPC_E500_USE_DEBUG_TLB 741 select FSL_ELBC 742 743config ARCH_P1023 744 bool 745 select FSL_LAW 746 select SYS_FSL_ERRATUM_A004508 747 select SYS_FSL_ERRATUM_A005125 748 select SYS_FSL_ERRATUM_I2C_A004447 749 select SYS_FSL_HAS_DDR3 750 select SYS_FSL_HAS_SEC 751 select SYS_FSL_SEC_BE 752 select SYS_FSL_SEC_COMPAT_4 753 select FSL_ELBC 754 755config ARCH_P1024 756 bool 757 select FSL_LAW 758 select SYS_FSL_ERRATUM_A004508 759 select SYS_FSL_ERRATUM_A005125 760 select SYS_FSL_ERRATUM_ELBC_A001 761 select SYS_FSL_ERRATUM_ESDHC111 762 select SYS_FSL_HAS_DDR3 763 select SYS_FSL_HAS_SEC 764 select SYS_FSL_SEC_BE 765 select SYS_FSL_SEC_COMPAT_2 766 select SYS_PPC_E500_USE_DEBUG_TLB 767 select FSL_ELBC 768 imply CMD_EEPROM 769 imply CMD_NAND 770 imply CMD_SATA 771 imply CMD_PCI 772 imply CMD_REGINFO 773 774config ARCH_P1025 775 bool 776 select FSL_LAW 777 select SYS_FSL_ERRATUM_A004508 778 select SYS_FSL_ERRATUM_A005125 779 select SYS_FSL_ERRATUM_ELBC_A001 780 select SYS_FSL_ERRATUM_ESDHC111 781 select SYS_FSL_HAS_DDR3 782 select SYS_FSL_HAS_SEC 783 select SYS_FSL_SEC_BE 784 select SYS_FSL_SEC_COMPAT_2 785 select SYS_PPC_E500_USE_DEBUG_TLB 786 select FSL_ELBC 787 imply CMD_SATA 788 imply CMD_REGINFO 789 790config ARCH_P2020 791 bool 792 select FSL_LAW 793 select SYS_FSL_ERRATUM_A004477 794 select SYS_FSL_ERRATUM_A004508 795 select SYS_FSL_ERRATUM_A005125 796 select SYS_FSL_ERRATUM_ESDHC111 797 select SYS_FSL_ERRATUM_ESDHC_A001 798 select SYS_FSL_HAS_DDR3 799 select SYS_FSL_HAS_SEC 800 select SYS_FSL_SEC_BE 801 select SYS_FSL_SEC_COMPAT_2 802 select SYS_PPC_E500_USE_DEBUG_TLB 803 select FSL_ELBC 804 imply CMD_EEPROM 805 imply CMD_NAND 806 imply CMD_REGINFO 807 808config ARCH_P2041 809 bool 810 select E500MC 811 select FSL_LAW 812 select SYS_FSL_ERRATUM_A004510 813 select SYS_FSL_ERRATUM_A004849 814 select SYS_FSL_ERRATUM_A006261 815 select SYS_FSL_ERRATUM_CPU_A003999 816 select SYS_FSL_ERRATUM_DDR_A003 817 select SYS_FSL_ERRATUM_DDR_A003474 818 select SYS_FSL_ERRATUM_ESDHC111 819 select SYS_FSL_ERRATUM_I2C_A004447 820 select SYS_FSL_ERRATUM_NMG_CPU_A011 821 select SYS_FSL_ERRATUM_SRIO_A004034 822 select SYS_FSL_ERRATUM_USB14 823 select SYS_FSL_HAS_DDR3 824 select SYS_FSL_HAS_SEC 825 select SYS_FSL_QORIQ_CHASSIS1 826 select SYS_FSL_SEC_BE 827 select SYS_FSL_SEC_COMPAT_4 828 select FSL_ELBC 829 imply CMD_NAND 830 831config ARCH_P3041 832 bool 833 select E500MC 834 select FSL_LAW 835 select SYS_FSL_DDR_VER_44 836 select SYS_FSL_ERRATUM_A004510 837 select SYS_FSL_ERRATUM_A004849 838 select SYS_FSL_ERRATUM_A005812 839 select SYS_FSL_ERRATUM_A006261 840 select SYS_FSL_ERRATUM_CPU_A003999 841 select SYS_FSL_ERRATUM_DDR_A003 842 select SYS_FSL_ERRATUM_DDR_A003474 843 select SYS_FSL_ERRATUM_ESDHC111 844 select SYS_FSL_ERRATUM_I2C_A004447 845 select SYS_FSL_ERRATUM_NMG_CPU_A011 846 select SYS_FSL_ERRATUM_SRIO_A004034 847 select SYS_FSL_ERRATUM_USB14 848 select SYS_FSL_HAS_DDR3 849 select SYS_FSL_HAS_SEC 850 select SYS_FSL_QORIQ_CHASSIS1 851 select SYS_FSL_SEC_BE 852 select SYS_FSL_SEC_COMPAT_4 853 select FSL_ELBC 854 imply CMD_NAND 855 imply CMD_SATA 856 imply CMD_REGINFO 857 858config ARCH_P4080 859 bool 860 select E500MC 861 select FSL_LAW 862 select SYS_FSL_DDR_VER_44 863 select SYS_FSL_ERRATUM_A004510 864 select SYS_FSL_ERRATUM_A004580 865 select SYS_FSL_ERRATUM_A004849 866 select SYS_FSL_ERRATUM_A005812 867 select SYS_FSL_ERRATUM_A007075 868 select SYS_FSL_ERRATUM_CPC_A002 869 select SYS_FSL_ERRATUM_CPC_A003 870 select SYS_FSL_ERRATUM_CPU_A003999 871 select SYS_FSL_ERRATUM_DDR_A003 872 select SYS_FSL_ERRATUM_DDR_A003474 873 select SYS_FSL_ERRATUM_ELBC_A001 874 select SYS_FSL_ERRATUM_ESDHC111 875 select SYS_FSL_ERRATUM_ESDHC13 876 select SYS_FSL_ERRATUM_ESDHC135 877 select SYS_FSL_ERRATUM_I2C_A004447 878 select SYS_FSL_ERRATUM_NMG_CPU_A011 879 select SYS_FSL_ERRATUM_SRIO_A004034 880 select SYS_P4080_ERRATUM_CPU22 881 select SYS_P4080_ERRATUM_PCIE_A003 882 select SYS_P4080_ERRATUM_SERDES8 883 select SYS_P4080_ERRATUM_SERDES9 884 select SYS_P4080_ERRATUM_SERDES_A001 885 select SYS_P4080_ERRATUM_SERDES_A005 886 select SYS_FSL_HAS_DDR3 887 select SYS_FSL_HAS_SEC 888 select SYS_FSL_QORIQ_CHASSIS1 889 select SYS_FSL_SEC_BE 890 select SYS_FSL_SEC_COMPAT_4 891 select FSL_ELBC 892 imply CMD_SATA 893 imply CMD_REGINFO 894 895config ARCH_P5020 896 bool 897 select E500MC 898 select FSL_LAW 899 select SYS_FSL_DDR_VER_44 900 select SYS_FSL_ERRATUM_A004510 901 select SYS_FSL_ERRATUM_A006261 902 select SYS_FSL_ERRATUM_DDR_A003 903 select SYS_FSL_ERRATUM_DDR_A003474 904 select SYS_FSL_ERRATUM_ESDHC111 905 select SYS_FSL_ERRATUM_I2C_A004447 906 select SYS_FSL_ERRATUM_SRIO_A004034 907 select SYS_FSL_ERRATUM_USB14 908 select SYS_FSL_HAS_DDR3 909 select SYS_FSL_HAS_SEC 910 select SYS_FSL_QORIQ_CHASSIS1 911 select SYS_FSL_SEC_BE 912 select SYS_FSL_SEC_COMPAT_4 913 select SYS_PPC64 914 select FSL_ELBC 915 imply CMD_SATA 916 imply CMD_REGINFO 917 918config ARCH_P5040 919 bool 920 select E500MC 921 select FSL_LAW 922 select SYS_FSL_DDR_VER_44 923 select SYS_FSL_ERRATUM_A004510 924 select SYS_FSL_ERRATUM_A004699 925 select SYS_FSL_ERRATUM_A005812 926 select SYS_FSL_ERRATUM_A006261 927 select SYS_FSL_ERRATUM_DDR_A003 928 select SYS_FSL_ERRATUM_DDR_A003474 929 select SYS_FSL_ERRATUM_ESDHC111 930 select SYS_FSL_ERRATUM_USB14 931 select SYS_FSL_HAS_DDR3 932 select SYS_FSL_HAS_SEC 933 select SYS_FSL_QORIQ_CHASSIS1 934 select SYS_FSL_SEC_BE 935 select SYS_FSL_SEC_COMPAT_4 936 select SYS_PPC64 937 select FSL_ELBC 938 imply CMD_SATA 939 imply CMD_REGINFO 940 941config ARCH_QEMU_E500 942 bool 943 944config ARCH_T1023 945 bool 946 select E500MC 947 select FSL_LAW 948 select SYS_FSL_DDR_VER_50 949 select SYS_FSL_ERRATUM_A008378 950 select SYS_FSL_ERRATUM_A009663 951 select SYS_FSL_ERRATUM_A009942 952 select SYS_FSL_ERRATUM_ESDHC111 953 select SYS_FSL_HAS_DDR3 954 select SYS_FSL_HAS_DDR4 955 select SYS_FSL_HAS_SEC 956 select SYS_FSL_QORIQ_CHASSIS2 957 select SYS_FSL_SEC_BE 958 select SYS_FSL_SEC_COMPAT_5 959 select FSL_IFC 960 imply CMD_EEPROM 961 imply CMD_NAND 962 imply CMD_REGINFO 963 964config ARCH_T1024 965 bool 966 select E500MC 967 select FSL_LAW 968 select SYS_FSL_DDR_VER_50 969 select SYS_FSL_ERRATUM_A008378 970 select SYS_FSL_ERRATUM_A009663 971 select SYS_FSL_ERRATUM_A009942 972 select SYS_FSL_ERRATUM_ESDHC111 973 select SYS_FSL_HAS_DDR3 974 select SYS_FSL_HAS_DDR4 975 select SYS_FSL_HAS_SEC 976 select SYS_FSL_QORIQ_CHASSIS2 977 select SYS_FSL_SEC_BE 978 select SYS_FSL_SEC_COMPAT_5 979 select FSL_IFC 980 imply CMD_EEPROM 981 imply CMD_NAND 982 imply CMD_MTDPARTS 983 imply CMD_REGINFO 984 985config ARCH_T1040 986 bool 987 select E500MC 988 select FSL_LAW 989 select SYS_FSL_DDR_VER_50 990 select SYS_FSL_ERRATUM_A008044 991 select SYS_FSL_ERRATUM_A008378 992 select SYS_FSL_ERRATUM_A009663 993 select SYS_FSL_ERRATUM_A009942 994 select SYS_FSL_ERRATUM_ESDHC111 995 select SYS_FSL_HAS_DDR3 996 select SYS_FSL_HAS_DDR4 997 select SYS_FSL_HAS_SEC 998 select SYS_FSL_QORIQ_CHASSIS2 999 select SYS_FSL_SEC_BE 1000 select SYS_FSL_SEC_COMPAT_5 1001 select FSL_IFC 1002 imply CMD_MTDPARTS 1003 imply CMD_NAND 1004 imply CMD_SATA 1005 imply CMD_REGINFO 1006 1007config ARCH_T1042 1008 bool 1009 select E500MC 1010 select FSL_LAW 1011 select SYS_FSL_DDR_VER_50 1012 select SYS_FSL_ERRATUM_A008044 1013 select SYS_FSL_ERRATUM_A008378 1014 select SYS_FSL_ERRATUM_A009663 1015 select SYS_FSL_ERRATUM_A009942 1016 select SYS_FSL_ERRATUM_ESDHC111 1017 select SYS_FSL_HAS_DDR3 1018 select SYS_FSL_HAS_DDR4 1019 select SYS_FSL_HAS_SEC 1020 select SYS_FSL_QORIQ_CHASSIS2 1021 select SYS_FSL_SEC_BE 1022 select SYS_FSL_SEC_COMPAT_5 1023 select FSL_IFC 1024 imply CMD_MTDPARTS 1025 imply CMD_NAND 1026 imply CMD_SATA 1027 imply CMD_REGINFO 1028 1029config ARCH_T2080 1030 bool 1031 select E500MC 1032 select E6500 1033 select FSL_LAW 1034 select SYS_FSL_DDR_VER_47 1035 select SYS_FSL_ERRATUM_A006379 1036 select SYS_FSL_ERRATUM_A006593 1037 select SYS_FSL_ERRATUM_A007186 1038 select SYS_FSL_ERRATUM_A007212 1039 select SYS_FSL_ERRATUM_A007815 1040 select SYS_FSL_ERRATUM_A007907 1041 select SYS_FSL_ERRATUM_A009942 1042 select SYS_FSL_ERRATUM_ESDHC111 1043 select SYS_FSL_HAS_DDR3 1044 select SYS_FSL_HAS_SEC 1045 select SYS_FSL_QORIQ_CHASSIS2 1046 select SYS_FSL_SEC_BE 1047 select SYS_FSL_SEC_COMPAT_4 1048 select SYS_PPC64 1049 select FSL_IFC 1050 imply CMD_SATA 1051 imply CMD_NAND 1052 imply CMD_REGINFO 1053 1054config ARCH_T2081 1055 bool 1056 select E500MC 1057 select E6500 1058 select FSL_LAW 1059 select SYS_FSL_DDR_VER_47 1060 select SYS_FSL_ERRATUM_A006379 1061 select SYS_FSL_ERRATUM_A006593 1062 select SYS_FSL_ERRATUM_A007186 1063 select SYS_FSL_ERRATUM_A007212 1064 select SYS_FSL_ERRATUM_A009942 1065 select SYS_FSL_ERRATUM_ESDHC111 1066 select SYS_FSL_HAS_DDR3 1067 select SYS_FSL_HAS_SEC 1068 select SYS_FSL_QORIQ_CHASSIS2 1069 select SYS_FSL_SEC_BE 1070 select SYS_FSL_SEC_COMPAT_4 1071 select SYS_PPC64 1072 select FSL_IFC 1073 imply CMD_NAND 1074 imply CMD_REGINFO 1075 1076config ARCH_T4160 1077 bool 1078 select E500MC 1079 select E6500 1080 select FSL_LAW 1081 select SYS_FSL_DDR_VER_47 1082 select SYS_FSL_ERRATUM_A004468 1083 select SYS_FSL_ERRATUM_A005871 1084 select SYS_FSL_ERRATUM_A006379 1085 select SYS_FSL_ERRATUM_A006593 1086 select SYS_FSL_ERRATUM_A007186 1087 select SYS_FSL_ERRATUM_A007798 1088 select SYS_FSL_ERRATUM_A009942 1089 select SYS_FSL_HAS_DDR3 1090 select SYS_FSL_HAS_SEC 1091 select SYS_FSL_QORIQ_CHASSIS2 1092 select SYS_FSL_SEC_BE 1093 select SYS_FSL_SEC_COMPAT_4 1094 select SYS_PPC64 1095 select FSL_IFC 1096 imply CMD_SATA 1097 imply CMD_NAND 1098 imply CMD_REGINFO 1099 1100config ARCH_T4240 1101 bool 1102 select E500MC 1103 select E6500 1104 select FSL_LAW 1105 select SYS_FSL_DDR_VER_47 1106 select SYS_FSL_ERRATUM_A004468 1107 select SYS_FSL_ERRATUM_A005871 1108 select SYS_FSL_ERRATUM_A006261 1109 select SYS_FSL_ERRATUM_A006379 1110 select SYS_FSL_ERRATUM_A006593 1111 select SYS_FSL_ERRATUM_A007186 1112 select SYS_FSL_ERRATUM_A007798 1113 select SYS_FSL_ERRATUM_A007815 1114 select SYS_FSL_ERRATUM_A007907 1115 select SYS_FSL_ERRATUM_A009942 1116 select SYS_FSL_HAS_DDR3 1117 select SYS_FSL_HAS_SEC 1118 select SYS_FSL_QORIQ_CHASSIS2 1119 select SYS_FSL_SEC_BE 1120 select SYS_FSL_SEC_COMPAT_4 1121 select SYS_PPC64 1122 select FSL_IFC 1123 imply CMD_SATA 1124 imply CMD_NAND 1125 imply CMD_REGINFO 1126 1127config BOOKE 1128 bool 1129 default y 1130 1131config E500 1132 bool 1133 default y 1134 help 1135 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc 1136 1137config E500MC 1138 bool 1139 imply CMD_PCI 1140 help 1141 Enble PowerPC E500MC core 1142 1143config E6500 1144 bool 1145 help 1146 Enable PowerPC E6500 core 1147 1148config FSL_LAW 1149 bool 1150 help 1151 Use Freescale common code for Local Access Window 1152 1153config SECURE_BOOT 1154 bool "Secure Boot" 1155 help 1156 Enable Freescale Secure Boot feature. Normally selected 1157 by defconfig. If unsure, do not change. 1158 1159config MAX_CPUS 1160 int "Maximum number of CPUs permitted for MPC85xx" 1161 default 12 if ARCH_T4240 1162 default 8 if ARCH_P4080 || \ 1163 ARCH_T4160 1164 default 4 if ARCH_B4860 || \ 1165 ARCH_P2041 || \ 1166 ARCH_P3041 || \ 1167 ARCH_P5040 || \ 1168 ARCH_T1040 || \ 1169 ARCH_T1042 || \ 1170 ARCH_T2080 || \ 1171 ARCH_T2081 1172 default 2 if ARCH_B4420 || \ 1173 ARCH_BSC9132 || \ 1174 ARCH_MPC8572 || \ 1175 ARCH_P1020 || \ 1176 ARCH_P1021 || \ 1177 ARCH_P1022 || \ 1178 ARCH_P1023 || \ 1179 ARCH_P1024 || \ 1180 ARCH_P1025 || \ 1181 ARCH_P2020 || \ 1182 ARCH_P5020 || \ 1183 ARCH_T1023 || \ 1184 ARCH_T1024 1185 default 1 1186 help 1187 Set this number to the maximum number of possible CPUs in the SoC. 1188 SoCs may have multiple clusters with each cluster may have multiple 1189 ports. If some ports are reserved but higher ports are used for 1190 cores, count the reserved ports. This will allocate enough memory 1191 in spin table to properly handle all cores. 1192 1193config SYS_CCSRBAR_DEFAULT 1194 hex "Default CCSRBAR address" 1195 default 0xff700000 if ARCH_BSC9131 || \ 1196 ARCH_BSC9132 || \ 1197 ARCH_C29X || \ 1198 ARCH_MPC8536 || \ 1199 ARCH_MPC8540 || \ 1200 ARCH_MPC8541 || \ 1201 ARCH_MPC8544 || \ 1202 ARCH_MPC8548 || \ 1203 ARCH_MPC8555 || \ 1204 ARCH_MPC8560 || \ 1205 ARCH_MPC8568 || \ 1206 ARCH_MPC8569 || \ 1207 ARCH_MPC8572 || \ 1208 ARCH_P1010 || \ 1209 ARCH_P1011 || \ 1210 ARCH_P1020 || \ 1211 ARCH_P1021 || \ 1212 ARCH_P1022 || \ 1213 ARCH_P1024 || \ 1214 ARCH_P1025 || \ 1215 ARCH_P2020 1216 default 0xff600000 if ARCH_P1023 1217 default 0xfe000000 if ARCH_B4420 || \ 1218 ARCH_B4860 || \ 1219 ARCH_P2041 || \ 1220 ARCH_P3041 || \ 1221 ARCH_P4080 || \ 1222 ARCH_P5020 || \ 1223 ARCH_P5040 || \ 1224 ARCH_T1023 || \ 1225 ARCH_T1024 || \ 1226 ARCH_T1040 || \ 1227 ARCH_T1042 || \ 1228 ARCH_T2080 || \ 1229 ARCH_T2081 || \ 1230 ARCH_T4160 || \ 1231 ARCH_T4240 1232 default 0xe0000000 if ARCH_QEMU_E500 1233 help 1234 Default value of CCSRBAR comes from power-on-reset. It 1235 is fixed on each SoC. Some SoCs can have different value 1236 if changed by pre-boot regime. The value here must match 1237 the current value in SoC. If not sure, do not change. 1238 1239config SYS_FSL_ERRATUM_A004468 1240 bool 1241 1242config SYS_FSL_ERRATUM_A004477 1243 bool 1244 1245config SYS_FSL_ERRATUM_A004508 1246 bool 1247 1248config SYS_FSL_ERRATUM_A004580 1249 bool 1250 1251config SYS_FSL_ERRATUM_A004699 1252 bool 1253 1254config SYS_FSL_ERRATUM_A004849 1255 bool 1256 1257config SYS_FSL_ERRATUM_A004510 1258 bool 1259 1260config SYS_FSL_ERRATUM_A004510_SVR_REV 1261 hex 1262 depends on SYS_FSL_ERRATUM_A004510 1263 default 0x20 if ARCH_P4080 1264 default 0x10 1265 1266config SYS_FSL_ERRATUM_A004510_SVR_REV2 1267 hex 1268 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041)) 1269 default 0x11 1270 1271config SYS_FSL_ERRATUM_A005125 1272 bool 1273 1274config SYS_FSL_ERRATUM_A005434 1275 bool 1276 1277config SYS_FSL_ERRATUM_A005812 1278 bool 1279 1280config SYS_FSL_ERRATUM_A005871 1281 bool 1282 1283config SYS_FSL_ERRATUM_A006261 1284 bool 1285 1286config SYS_FSL_ERRATUM_A006379 1287 bool 1288 1289config SYS_FSL_ERRATUM_A006384 1290 bool 1291 1292config SYS_FSL_ERRATUM_A006475 1293 bool 1294 1295config SYS_FSL_ERRATUM_A006593 1296 bool 1297 1298config SYS_FSL_ERRATUM_A007075 1299 bool 1300 1301config SYS_FSL_ERRATUM_A007186 1302 bool 1303 1304config SYS_FSL_ERRATUM_A007212 1305 bool 1306 1307config SYS_FSL_ERRATUM_A007815 1308 bool 1309 1310config SYS_FSL_ERRATUM_A007798 1311 bool 1312 1313config SYS_FSL_ERRATUM_A007907 1314 bool 1315 1316config SYS_FSL_ERRATUM_A008044 1317 bool 1318 1319config SYS_FSL_ERRATUM_CPC_A002 1320 bool 1321 1322config SYS_FSL_ERRATUM_CPC_A003 1323 bool 1324 1325config SYS_FSL_ERRATUM_CPU_A003999 1326 bool 1327 1328config SYS_FSL_ERRATUM_ELBC_A001 1329 bool 1330 1331config SYS_FSL_ERRATUM_I2C_A004447 1332 bool 1333 1334config SYS_FSL_A004447_SVR_REV 1335 hex 1336 depends on SYS_FSL_ERRATUM_I2C_A004447 1337 default 0x00 if ARCH_MPC8548 1338 default 0x10 if ARCH_P1010 1339 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132 1340 default 0x20 if ARCH_P3041 || ARCH_P4080 || ARCH_P5020 1341 1342config SYS_FSL_ERRATUM_IFC_A002769 1343 bool 1344 1345config SYS_FSL_ERRATUM_IFC_A003399 1346 bool 1347 1348config SYS_FSL_ERRATUM_NMG_CPU_A011 1349 bool 1350 1351config SYS_FSL_ERRATUM_NMG_ETSEC129 1352 bool 1353 1354config SYS_FSL_ERRATUM_NMG_LBC103 1355 bool 1356 1357config SYS_FSL_ERRATUM_P1010_A003549 1358 bool 1359 1360config SYS_FSL_ERRATUM_SATA_A001 1361 bool 1362 1363config SYS_FSL_ERRATUM_SEC_A003571 1364 bool 1365 1366config SYS_FSL_ERRATUM_SRIO_A004034 1367 bool 1368 1369config SYS_FSL_ERRATUM_USB14 1370 bool 1371 1372config SYS_P4080_ERRATUM_CPU22 1373 bool 1374 1375config SYS_P4080_ERRATUM_PCIE_A003 1376 bool 1377 1378config SYS_P4080_ERRATUM_SERDES8 1379 bool 1380 1381config SYS_P4080_ERRATUM_SERDES9 1382 bool 1383 1384config SYS_P4080_ERRATUM_SERDES_A001 1385 bool 1386 1387config SYS_P4080_ERRATUM_SERDES_A005 1388 bool 1389 1390config SYS_FSL_QORIQ_CHASSIS1 1391 bool 1392 1393config SYS_FSL_QORIQ_CHASSIS2 1394 bool 1395 1396config SYS_FSL_NUM_LAWS 1397 int "Number of local access windows" 1398 depends on FSL_LAW 1399 default 32 if ARCH_B4420 || \ 1400 ARCH_B4860 || \ 1401 ARCH_P2041 || \ 1402 ARCH_P3041 || \ 1403 ARCH_P4080 || \ 1404 ARCH_P5020 || \ 1405 ARCH_P5040 || \ 1406 ARCH_T2080 || \ 1407 ARCH_T2081 || \ 1408 ARCH_T4160 || \ 1409 ARCH_T4240 1410 default 16 if ARCH_T1023 || \ 1411 ARCH_T1024 || \ 1412 ARCH_T1040 || \ 1413 ARCH_T1042 1414 default 12 if ARCH_BSC9131 || \ 1415 ARCH_BSC9132 || \ 1416 ARCH_C29X || \ 1417 ARCH_MPC8536 || \ 1418 ARCH_MPC8572 || \ 1419 ARCH_P1010 || \ 1420 ARCH_P1011 || \ 1421 ARCH_P1020 || \ 1422 ARCH_P1021 || \ 1423 ARCH_P1022 || \ 1424 ARCH_P1023 || \ 1425 ARCH_P1024 || \ 1426 ARCH_P1025 || \ 1427 ARCH_P2020 1428 default 10 if ARCH_MPC8544 || \ 1429 ARCH_MPC8548 || \ 1430 ARCH_MPC8568 || \ 1431 ARCH_MPC8569 1432 default 8 if ARCH_MPC8540 || \ 1433 ARCH_MPC8541 || \ 1434 ARCH_MPC8555 || \ 1435 ARCH_MPC8560 1436 help 1437 Number of local access windows. This is fixed per SoC. 1438 If not sure, do not change. 1439 1440config SYS_FSL_THREADS_PER_CORE 1441 int 1442 default 2 if E6500 1443 default 1 1444 1445config SYS_NUM_TLBCAMS 1446 int "Number of TLB CAM entries" 1447 default 64 if E500MC 1448 default 16 1449 help 1450 Number of TLB CAM entries for Book-E chips. 64 for E500MC, 1451 16 for other E500 SoCs. 1452 1453config SYS_PPC64 1454 bool 1455 1456config SYS_PPC_E500_USE_DEBUG_TLB 1457 bool 1458 1459config FSL_IFC 1460 bool 1461 1462config FSL_ELBC 1463 bool 1464 1465config SYS_PPC_E500_DEBUG_TLB 1466 int "Temporary TLB entry for external debugger" 1467 depends on SYS_PPC_E500_USE_DEBUG_TLB 1468 default 0 if ARCH_MPC8544 || ARCH_MPC8548 1469 default 1 if ARCH_MPC8536 1470 default 2 if ARCH_MPC8572 || \ 1471 ARCH_P1011 || \ 1472 ARCH_P1020 || \ 1473 ARCH_P1021 || \ 1474 ARCH_P1022 || \ 1475 ARCH_P1024 || \ 1476 ARCH_P1025 || \ 1477 ARCH_P2020 1478 default 3 if ARCH_P1010 || \ 1479 ARCH_BSC9132 || \ 1480 ARCH_C29X 1481 help 1482 Select a temporary TLB entry to be used during boot to work 1483 around limitations in e500v1 and e500v2 external debugger 1484 support. This reduces the portions of the boot code where 1485 breakpoints and single stepping do not work. The value of this 1486 symbol should be set to the TLB1 entry to be used for this 1487 purpose. If unsure, do not change. 1488 1489config SYS_FSL_IFC_CLK_DIV 1490 int "Divider of platform clock" 1491 depends on FSL_IFC 1492 default 2 if ARCH_B4420 || \ 1493 ARCH_B4860 || \ 1494 ARCH_T1024 || \ 1495 ARCH_T1023 || \ 1496 ARCH_T1040 || \ 1497 ARCH_T1042 || \ 1498 ARCH_T4160 || \ 1499 ARCH_T4240 1500 default 1 1501 help 1502 Defines divider of platform clock(clock input to 1503 IFC controller). 1504 1505config SYS_FSL_LBC_CLK_DIV 1506 int "Divider of platform clock" 1507 depends on FSL_ELBC || ARCH_MPC8540 || \ 1508 ARCH_MPC8548 || ARCH_MPC8541 || \ 1509 ARCH_MPC8555 || ARCH_MPC8560 || \ 1510 ARCH_MPC8568 1511 1512 default 2 if ARCH_P2041 || \ 1513 ARCH_P3041 || \ 1514 ARCH_P4080 || \ 1515 ARCH_P5020 || \ 1516 ARCH_P5040 1517 default 1 1518 1519 help 1520 Defines divider of platform clock(clock input to 1521 eLBC controller). 1522 1523source "board/freescale/b4860qds/Kconfig" 1524source "board/freescale/bsc9131rdb/Kconfig" 1525source "board/freescale/bsc9132qds/Kconfig" 1526source "board/freescale/c29xpcie/Kconfig" 1527source "board/freescale/corenet_ds/Kconfig" 1528source "board/freescale/mpc8536ds/Kconfig" 1529source "board/freescale/mpc8541cds/Kconfig" 1530source "board/freescale/mpc8544ds/Kconfig" 1531source "board/freescale/mpc8548cds/Kconfig" 1532source "board/freescale/mpc8555cds/Kconfig" 1533source "board/freescale/mpc8568mds/Kconfig" 1534source "board/freescale/mpc8569mds/Kconfig" 1535source "board/freescale/mpc8572ds/Kconfig" 1536source "board/freescale/p1010rdb/Kconfig" 1537source "board/freescale/p1022ds/Kconfig" 1538source "board/freescale/p1023rdb/Kconfig" 1539source "board/freescale/p1_p2_rdb_pc/Kconfig" 1540source "board/freescale/p1_twr/Kconfig" 1541source "board/freescale/p2041rdb/Kconfig" 1542source "board/freescale/qemu-ppce500/Kconfig" 1543source "board/freescale/t102xqds/Kconfig" 1544source "board/freescale/t102xrdb/Kconfig" 1545source "board/freescale/t1040qds/Kconfig" 1546source "board/freescale/t104xrdb/Kconfig" 1547source "board/freescale/t208xqds/Kconfig" 1548source "board/freescale/t208xrdb/Kconfig" 1549source "board/freescale/t4qds/Kconfig" 1550source "board/freescale/t4rdb/Kconfig" 1551source "board/gdsys/p1022/Kconfig" 1552source "board/keymile/kmp204x/Kconfig" 1553source "board/sbc8548/Kconfig" 1554source "board/socrates/Kconfig" 1555source "board/varisys/cyrus/Kconfig" 1556source "board/xes/xpedite520x/Kconfig" 1557source "board/xes/xpedite537x/Kconfig" 1558source "board/xes/xpedite550x/Kconfig" 1559source "board/Arcturus/ucp1020/Kconfig" 1560 1561endmenu 1562