1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2008-2018 Fuzhou Rockchip Electronics Co., Ltd
4 *
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
6 */
7
8 #include <asm/arch/cpu.h>
9 #include <config.h>
10 #include <common.h>
11 #include <errno.h>
12 #include <dm.h>
13 #include <div64.h>
14 #include <asm/io.h>
15 #include <linux/ioport.h>
16 #include <linux/iopoll.h>
17 #include <linux/math64.h>
18
19 #include "rockchip_phy.h"
20
21 #define USEC_PER_SEC 1000000LL
22 #define PSEC_PER_SEC 1000000000000LL
23
24 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
25
26 /*
27 * The offset address[7:0] is distributed two parts, one from the bit7 to bit5
28 * is the first address, the other from the bit4 to bit0 is the second address.
29 * when you configure the registers, you must set both of them. The Clock Lane
30 * and Data Lane use the same registers with the same second address, but the
31 * first address is different.
32 */
33 #define FIRST_ADDRESS(x) (((x) & 0x7) << 5)
34 #define SECOND_ADDRESS(x) (((x) & 0x1f) << 0)
35 #define PHY_REG(first, second) (FIRST_ADDRESS(first) | \
36 SECOND_ADDRESS(second))
37
38 /* Analog Register Part: reg00 */
39 #define BANDGAP_POWER_MASK BIT(7)
40 #define BANDGAP_POWER_DOWN BIT(7)
41 #define BANDGAP_POWER_ON 0
42 #define LANE_EN_MASK GENMASK(6, 2)
43 #define LANE_EN_CK BIT(6)
44 #define LANE_EN_3 BIT(5)
45 #define LANE_EN_2 BIT(4)
46 #define LANE_EN_1 BIT(3)
47 #define LANE_EN_0 BIT(2)
48 #define POWER_WORK_MASK GENMASK(1, 0)
49 #define POWER_WORK_ENABLE UPDATE(1, 1, 0)
50 #define POWER_WORK_DISABLE UPDATE(2, 1, 0)
51 /* Analog Register Part: reg01 */
52 #define REG_SYNCRST_MASK BIT(2)
53 #define REG_SYNCRST_RESET BIT(2)
54 #define REG_SYNCRST_NORMAL 0
55 #define REG_LDOPD_MASK BIT(1)
56 #define REG_LDOPD_POWER_DOWN BIT(1)
57 #define REG_LDOPD_POWER_ON 0
58 #define REG_PLLPD_MASK BIT(0)
59 #define REG_PLLPD_POWER_DOWN BIT(0)
60 #define REG_PLLPD_POWER_ON 0
61 /* Analog Register Part: reg03 */
62 #define REG_FBDIV_HI_MASK BIT(5)
63 #define REG_FBDIV_HI(x) UPDATE(x, 5, 5)
64 #define REG_PREDIV_MASK GENMASK(4, 0)
65 #define REG_PREDIV(x) UPDATE(x, 4, 0)
66 /* Analog Register Part: reg04 */
67 #define REG_FBDIV_LO_MASK GENMASK(7, 0)
68 #define REG_FBDIV_LO(x) UPDATE(x, 7, 0)
69 /* Analog Register Part: reg05 */
70 #define SAMPLE_CLOCK_PHASE_MASK GENMASK(6, 4)
71 #define SAMPLE_CLOCK_PHASE(x) UPDATE(x, 6, 4)
72 #define CLOCK_LANE_SKEW_PHASE_MASK GENMASK(2, 0)
73 #define CLOCK_LANE_SKEW_PHASE(x) UPDATE(x, 2, 0)
74 /* Analog Register Part: reg06 */
75 #define DATA_LANE_3_SKEW_PHASE_MASK GENMASK(6, 4)
76 #define DATA_LANE_3_SKEW_PHASE(x) UPDATE(x, 6, 4)
77 #define DATA_LANE_2_SKEW_PHASE_MASK GENMASK(2, 0)
78 #define DATA_LANE_2_SKEW_PHASE(x) UPDATE(x, 2, 0)
79 /* Analog Register Part: reg07 */
80 #define DATA_LANE_1_SKEW_PHASE_MASK GENMASK(6, 4)
81 #define DATA_LANE_1_SKEW_PHASE(x) UPDATE(x, 6, 4)
82 #define DATA_LANE_0_SKEW_PHASE_MASK GENMASK(2, 0)
83 #define DATA_LANE_0_SKEW_PHASE(x) UPDATE(x, 2, 0)
84 /* Analog Register Part: reg08 */
85 #define PRE_EMPHASIS_ENABLE_MASK BIT(7)
86 #define PRE_EMPHASIS_ENABLE BIT(7)
87 #define PRE_EMPHASIS_DISABLE 0
88 #define PLL_POST_DIV_ENABLE_MASK BIT(5)
89 #define PLL_POST_DIV_ENABLE BIT(5)
90 #define PLL_POST_DIV_DISABLE 0
91 #define DATA_LANE_VOD_RANGE_SET_MASK GENMASK(3, 0)
92 #define DATA_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0)
93 #define SAMPLE_CLOCK_DIRECTION_MASK BIT(4)
94 #define SAMPLE_CLOCK_DIRECTION_REVERSE BIT(4)
95 #define SAMPLE_CLOCK_DIRECTION_FORWARD 0
96 #define LOWFRE_EN_MASK BIT(5)
97 #define PLL_OUTPUT_FREQUENCY_DIV_BY_1 0
98 #define PLL_OUTPUT_FREQUENCY_DIV_BY_2 1
99 /* Analog Register Part: reg0b */
100 #define CLOCK_LANE_VOD_RANGE_SET_MASK GENMASK(3, 0)
101 #define CLOCK_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0)
102 #define VOD_MIN_RANGE 0x1
103 #define VOD_MID_RANGE 0x3
104 #define VOD_BIG_RANGE 0x7
105 #define VOD_MAX_RANGE 0xf
106 /* Analog Register Part: reg1e */
107 #define PLL_MODE_SEL_MASK GENMASK(6, 5)
108 #define PLL_MODE_SEL_LVDS_MODE 0
109 #define PLL_MODE_SEL_MIPI_MODE BIT(5)
110
111 /* Digital Register Part: reg00 */
112 #define REG_DIG_RSTN_MASK BIT(0)
113 #define REG_DIG_RSTN_NORMAL BIT(0)
114 #define REG_DIG_RSTN_RESET 0
115 /* Digital Register Part: reg01 */
116 #define INVERT_TXCLKESC_MASK BIT(1)
117 #define INVERT_TXCLKESC_ENABLE BIT(1)
118 #define INVERT_TXCLKESC_DISABLE 0
119 #define INVERT_TXBYTECLKHS_MASK BIT(0)
120 #define INVERT_TXBYTECLKHS_ENABLE BIT(0)
121 #define INVERT_TXBYTECLKHS_DISABLE 0
122 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg05 */
123 #define T_LPX_CNT_MASK GENMASK(5, 0)
124 #define T_LPX_CNT(x) UPDATE(x, 5, 0)
125 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg06 */
126 #define T_HS_ZERO_CNT_HI_MASK BIT(7)
127 #define T_HS_ZERO_CNT_HI(x) UPDATE(x, 7, 7)
128 #define T_HS_PREPARE_CNT_MASK GENMASK(6, 0)
129 #define T_HS_PREPARE_CNT(x) UPDATE(x, 6, 0)
130 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg07 */
131 #define T_HS_ZERO_CNT_LO_MASK GENMASK(5, 0)
132 #define T_HS_ZERO_CNT_LO(x) UPDATE(x, 5, 0)
133 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg08 */
134 #define T_HS_TRAIL_CNT_MASK GENMASK(6, 0)
135 #define T_HS_TRAIL_CNT(x) UPDATE(x, 6, 0)
136 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg09 */
137 #define T_HS_EXIT_CNT_LO_MASK GENMASK(4, 0)
138 #define T_HS_EXIT_CNT_LO(x) UPDATE(x, 4, 0)
139 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0a */
140 #define T_CLK_POST_CNT_LO_MASK GENMASK(3, 0)
141 #define T_CLK_POST_CNT_LO(x) UPDATE(x, 3, 0)
142 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0c */
143 #define LPDT_TX_PPI_SYNC_MASK BIT(2)
144 #define LPDT_TX_PPI_SYNC_ENABLE BIT(2)
145 #define LPDT_TX_PPI_SYNC_DISABLE 0
146 #define T_WAKEUP_CNT_HI_MASK GENMASK(1, 0)
147 #define T_WAKEUP_CNT_HI(x) UPDATE(x, 1, 0)
148 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0d */
149 #define T_WAKEUP_CNT_LO_MASK GENMASK(7, 0)
150 #define T_WAKEUP_CNT_LO(x) UPDATE(x, 7, 0)
151 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0e */
152 #define T_CLK_PRE_CNT_MASK GENMASK(3, 0)
153 #define T_CLK_PRE_CNT(x) UPDATE(x, 3, 0)
154 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg10 */
155 #define T_CLK_POST_HI_MASK GENMASK(7, 6)
156 #define T_CLK_POST_HI(x) UPDATE(x, 7, 6)
157 #define T_TA_GO_CNT_MASK GENMASK(5, 0)
158 #define T_TA_GO_CNT(x) UPDATE(x, 5, 0)
159 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg11 */
160 #define T_HS_EXIT_CNT_HI_MASK BIT(6)
161 #define T_HS_EXIT_CNT_HI(x) UPDATE(x, 6, 6)
162 #define T_TA_SURE_CNT_MASK GENMASK(5, 0)
163 #define T_TA_SURE_CNT(x) UPDATE(x, 5, 0)
164 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg12 */
165 #define T_TA_WAIT_CNT_MASK GENMASK(5, 0)
166 #define T_TA_WAIT_CNT(x) UPDATE(x, 5, 0)
167 /* LVDS Register Part: reg00 */
168 #define LVDS_DIGITAL_INTERNAL_RESET_MASK BIT(2)
169 #define LVDS_DIGITAL_INTERNAL_RESET_DISABLE BIT(2)
170 #define LVDS_DIGITAL_INTERNAL_RESET_ENABLE 0
171 /* LVDS Register Part: reg01 */
172 #define LVDS_DIGITAL_INTERNAL_ENABLE_MASK BIT(7)
173 #define LVDS_DIGITAL_INTERNAL_ENABLE BIT(7)
174 #define LVDS_DIGITAL_INTERNAL_DISABLE 0
175 /* LVDS Register Part: reg03 */
176 #define MODE_ENABLE_MASK GENMASK(2, 0)
177 #define TTL_MODE_ENABLE BIT(2)
178 #define LVDS_MODE_ENABLE BIT(1)
179 #define MIPI_MODE_ENABLE BIT(0)
180 /* LVDS Register Part: reg04 */
181 #define LVDS_VCOM_MASK GENMASK(5, 4)
182 #define LVDS_VCOM(x) UPDATE(x, 5, 4)
183 #define LVDS_VOD_MASK GENMASK(7, 6)
184 #define LVDS_VOD(x) UPDATE(x, 7, 6)
185 /* LVDS Register Part: reg0b */
186 #define LVDS_LANE_EN_MASK GENMASK(7, 3)
187 #define LVDS_DATA_LANE0_EN BIT(7)
188 #define LVDS_DATA_LANE1_EN BIT(6)
189 #define LVDS_DATA_LANE2_EN BIT(5)
190 #define LVDS_DATA_LANE3_EN BIT(4)
191 #define LVDS_CLK_LANE_EN BIT(3)
192 #define LVDS_PLL_POWER_MASK BIT(2)
193 #define LVDS_PLL_POWER_OFF BIT(2)
194 #define LVDS_PLL_POWER_ON 0
195 #define LVDS_BANDGAP_POWER_MASK BIT(0)
196 #define LVDS_BANDGAP_POWER_DOWN BIT(0)
197 #define LVDS_BANDGAP_POWER_ON 0
198
199 #define DSI_PHY_RSTZ 0xa0
200 #define PHY_ENABLECLK BIT(2)
201 #define DSI_PHY_STATUS 0xb0
202 #define PHY_LOCK BIT(0)
203
204 enum soc_type {
205 PX30_VIDEO_PHY,
206 PX30S_VIDEO_PHY,
207 RK3128_VIDEO_PHY,
208 RK3368_VIDEO_PHY,
209 RK3568_VIDEO_PHY,
210 };
211
212 enum phy_max_rate {
213 MAX_1GHZ,
214 MAX_2_5GHZ,
215 };
216
217 struct inno_video_mipi_dphy_timing {
218 unsigned int max_lane_mbps;
219 u8 lpx;
220 u8 hs_prepare;
221 u8 clk_lane_hs_zero;
222 u8 data_lane_hs_zero;
223 u8 hs_trail;
224 };
225
226 struct inno_video_mipi_dphy_info {
227 const struct inno_video_mipi_dphy_timing *inno_mipi_dphy_timing_table;
228 const unsigned int num_timings;
229 enum phy_max_rate phy_max_rate;
230 };
231
232 static const
233 struct inno_video_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1GHz[] = {
234 { 110, 0x0, 0x20, 0x16, 0x02, 0x22},
235 { 150, 0x0, 0x06, 0x16, 0x03, 0x45},
236 { 200, 0x0, 0x18, 0x17, 0x04, 0x0b},
237 { 250, 0x0, 0x05, 0x17, 0x05, 0x16},
238 { 300, 0x0, 0x51, 0x18, 0x06, 0x2c},
239 { 400, 0x0, 0x64, 0x19, 0x07, 0x33},
240 { 500, 0x0, 0x20, 0x1b, 0x07, 0x4e},
241 { 600, 0x0, 0x6a, 0x1d, 0x08, 0x3a},
242 { 700, 0x0, 0x3e, 0x1e, 0x08, 0x6a},
243 { 800, 0x0, 0x21, 0x1f, 0x09, 0x29},
244 {1000, 0x0, 0x09, 0x20, 0x09, 0x27},
245 };
246
247 static const
248 struct inno_video_mipi_dphy_timing inno_mipi_dphy_timing_table_max_2_5GHz[] = {
249 { 110, 0x02, 0x7f, 0x16, 0x02, 0x02},
250 { 150, 0x02, 0x7f, 0x16, 0x03, 0x02},
251 { 200, 0x02, 0x7f, 0x17, 0x04, 0x02},
252 { 250, 0x02, 0x7f, 0x17, 0x05, 0x04},
253 { 300, 0x02, 0x7f, 0x18, 0x06, 0x04},
254 { 400, 0x03, 0x7e, 0x19, 0x07, 0x04},
255 { 500, 0x03, 0x7c, 0x1b, 0x07, 0x08},
256 { 600, 0x03, 0x70, 0x1d, 0x08, 0x10},
257 { 700, 0x05, 0x40, 0x1e, 0x08, 0x30},
258 { 800, 0x05, 0x02, 0x1f, 0x09, 0x30},
259 {1000, 0x05, 0x08, 0x20, 0x09, 0x30},
260 {1200, 0x06, 0x03, 0x32, 0x14, 0x0f},
261 {1400, 0x09, 0x03, 0x32, 0x14, 0x0f},
262 {1600, 0x0d, 0x42, 0x36, 0x0e, 0x0f},
263 {1800, 0x0e, 0x47, 0x7a, 0x0e, 0x0f},
264 {2000, 0x11, 0x64, 0x7a, 0x0e, 0x0b},
265 {2200, 0x13, 0x64, 0x7e, 0x15, 0x0b},
266 {2400, 0x13, 0x33, 0x7f, 0x15, 0x6a},
267 {2500, 0x15, 0x54, 0x7f, 0x15, 0x6a},
268 };
269
270 const struct inno_video_mipi_dphy_info inno_video_mipi_dphy_max_1GHz = {
271 .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1GHz,
272 .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1GHz),
273 .phy_max_rate = MAX_1GHZ,
274 };
275
276 const struct inno_video_mipi_dphy_info inno_video_mipi_dphy_max_2_5GHz = {
277 .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5GHz,
278 .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5GHz),
279 .phy_max_rate = MAX_2_5GHZ,
280 };
281
282 struct mipi_dphy_timing {
283 unsigned int clkmiss;
284 unsigned int clkpost;
285 unsigned int clkpre;
286 unsigned int clkprepare;
287 unsigned int clksettle;
288 unsigned int clktermen;
289 unsigned int clktrail;
290 unsigned int clkzero;
291 unsigned int dtermen;
292 unsigned int eot;
293 unsigned int hsexit;
294 unsigned int hsprepare;
295 unsigned int hszero;
296 unsigned int hssettle;
297 unsigned int hsskip;
298 unsigned int hstrail;
299 unsigned int init;
300 unsigned int lpx;
301 unsigned int taget;
302 unsigned int tago;
303 unsigned int tasure;
304 unsigned int wakeup;
305 };
306
307 struct inno_video_phy {
308 struct udevice *dev;
309 enum phy_mode mode;
310 const struct inno_video_mipi_dphy_info *mipi_dphy_info;
311 struct resource phy;
312 struct resource host;
313 int lanes;
314 struct {
315 u8 prediv;
316 u16 fbdiv;
317 unsigned long rate;
318 } pll;
319 u32 lvds_vcom;
320 u32 lvds_vod;
321 };
322
323 enum {
324 REGISTER_PART_ANALOG,
325 REGISTER_PART_DIGITAL,
326 REGISTER_PART_CLOCK_LANE,
327 REGISTER_PART_DATA0_LANE,
328 REGISTER_PART_DATA1_LANE,
329 REGISTER_PART_DATA2_LANE,
330 REGISTER_PART_DATA3_LANE,
331 REGISTER_PART_LVDS,
332 };
333
phy_update_bits(struct inno_video_phy * inno,u8 first,u8 second,u8 mask,u8 val)334 static inline void phy_update_bits(struct inno_video_phy *inno,
335 u8 first, u8 second, u8 mask, u8 val)
336 {
337 u32 reg = PHY_REG(first, second) << 2;
338 u32 tmp, orig;
339
340 orig = readl(inno->phy.start + reg);
341 tmp = orig & ~mask;
342 tmp |= val & mask;
343 writel(tmp, inno->phy.start + reg);
344 }
345
host_update_bits(struct inno_video_phy * inno,u32 reg,u32 mask,u32 val)346 static inline void host_update_bits(struct inno_video_phy *inno,
347 u32 reg, u32 mask, u32 val)
348 {
349 u32 tmp, orig;
350
351 orig = readl(inno->host.start + reg);
352 tmp = orig & ~mask;
353 tmp |= val & mask;
354 writel(tmp, inno->host.start + reg);
355 }
356
mipi_dphy_timing_get_default(struct mipi_dphy_timing * timing,unsigned long period)357 static void mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing,
358 unsigned long period)
359 {
360 /* Global Operation Timing Parameters */
361 timing->clkmiss = 0;
362 timing->clkpost = 70000 + 52 * period;
363 timing->clkpre = 8 * period;
364 timing->clkprepare = 65000;
365 timing->clksettle = 95000;
366 timing->clktermen = 0;
367 timing->clktrail = 80000;
368 timing->clkzero = 260000;
369 timing->dtermen = 0;
370 timing->eot = 0;
371 timing->hsexit = 120000;
372 timing->hsprepare = 65000 + 4 * period;
373 timing->hszero = 145000 + 6 * period;
374 timing->hssettle = 85000 + 6 * period;
375 timing->hsskip = 40000;
376 timing->hstrail = max(8 * period, 60000 + 4 * period);
377 timing->init = 100000000;
378 timing->lpx = 60000;
379 timing->taget = 5 * timing->lpx;
380 timing->tago = 4 * timing->lpx;
381 timing->tasure = 2 * timing->lpx;
382 timing->wakeup = 1000000000;
383 }
384
385 static const struct inno_video_mipi_dphy_timing *
inno_mipi_dphy_get_timing(struct inno_video_phy * inno)386 inno_mipi_dphy_get_timing(struct inno_video_phy *inno)
387 {
388 const struct inno_video_mipi_dphy_timing *timings;
389 unsigned int num_timings;
390 unsigned int lane_mbps = inno->pll.rate / USEC_PER_SEC;
391 unsigned int i;
392
393 timings = inno->mipi_dphy_info->inno_mipi_dphy_timing_table;
394 num_timings = inno->mipi_dphy_info->num_timings;
395
396 for (i = 0; i < num_timings; i++)
397 if (lane_mbps <= timings[i].max_lane_mbps)
398 break;
399
400 if (i == num_timings)
401 --i;
402
403 return &timings[i];
404 }
405
inno_mipi_dphy_max_2_5GHz_pll_enable(struct inno_video_phy * inno)406 static void inno_mipi_dphy_max_2_5GHz_pll_enable(struct inno_video_phy *inno)
407 {
408 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
409 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv));
410 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
411 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv >> 8));
412 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
413 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv));
414 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
415 PLL_POST_DIV_ENABLE_MASK, PLL_POST_DIV_ENABLE);
416 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b,
417 CLOCK_LANE_VOD_RANGE_SET_MASK,
418 CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE));
419 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
420 REG_LDOPD_MASK | REG_PLLPD_MASK,
421 REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON);
422 }
423
inno_mipi_dphy_max_1GHz_pll_enable(struct inno_video_phy * inno)424 static void inno_mipi_dphy_max_1GHz_pll_enable(struct inno_video_phy *inno)
425 {
426 /* Configure PLL */
427 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
428 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv));
429 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
430 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv >> 8));
431 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
432 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv));
433 /* Enable PLL and LDO */
434 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
435 REG_LDOPD_MASK | REG_PLLPD_MASK,
436 REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON);
437 }
438
inno_mipi_dphy_reset(struct inno_video_phy * inno)439 static void inno_mipi_dphy_reset(struct inno_video_phy *inno)
440 {
441 /* Reset analog */
442 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
443 REG_SYNCRST_MASK, REG_SYNCRST_RESET);
444 udelay(1);
445 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
446 REG_SYNCRST_MASK, REG_SYNCRST_NORMAL);
447 /* Reset digital */
448 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
449 REG_DIG_RSTN_MASK, REG_DIG_RSTN_RESET);
450 udelay(1);
451 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
452 REG_DIG_RSTN_MASK, REG_DIG_RSTN_NORMAL);
453 }
454
inno_mipi_dphy_timing_init(struct inno_video_phy * inno)455 static void inno_mipi_dphy_timing_init(struct inno_video_phy *inno)
456 {
457 struct mipi_dphy_timing gotp;
458 u32 t_txbyteclkhs, t_txclkesc, ui;
459 u32 txbyteclkhs, txclkesc, esc_clk_div;
460 u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait;
461 u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero;
462 const struct inno_video_mipi_dphy_timing *timing;
463 unsigned int i;
464
465 txbyteclkhs = inno->pll.rate / 8;
466 t_txbyteclkhs = div_u64(PSEC_PER_SEC, txbyteclkhs);
467 esc_clk_div = DIV_ROUND_UP(txbyteclkhs, 20000000);
468 txclkesc = txbyteclkhs / esc_clk_div;
469 t_txclkesc = div_u64(PSEC_PER_SEC, txclkesc);
470
471 ui = div_u64(PSEC_PER_SEC, inno->pll.rate);
472
473 memset(&gotp, 0, sizeof(gotp));
474 mipi_dphy_timing_get_default(&gotp, ui);
475
476 /*
477 * The value of counter for HS Ths-exit
478 * Ths-exit = Tpin_txbyteclkhs * value
479 */
480 hs_exit = DIV_ROUND_UP(gotp.hsexit, t_txbyteclkhs);
481 /*
482 * The value of counter for HS Tclk-post
483 * Tclk-post = Tpin_txbyteclkhs * value
484 */
485 clk_post = DIV_ROUND_UP(gotp.clkpost, t_txbyteclkhs);
486 /*
487 * The value of counter for HS Tclk-pre
488 * Tclk-pre = Tpin_txbyteclkhs * value
489 */
490 clk_pre = DIV_ROUND_UP(gotp.clkpre, t_txbyteclkhs);
491
492 /*
493 * The value of counter for HS Tlpx Time
494 * Tlpx = Tpin_txbyteclkhs * (2 + value)
495 */
496 lpx = DIV_ROUND_UP(gotp.lpx, t_txbyteclkhs);
497 if (lpx >= 2)
498 lpx -= 2;
499
500 /*
501 * The value of counter for HS Tta-go
502 * Tta-go for turnaround
503 * Tta-go = Ttxclkesc * value
504 */
505 ta_go = DIV_ROUND_UP(gotp.tago, t_txclkesc);
506 /*
507 * The value of counter for HS Tta-sure
508 * Tta-sure for turnaround
509 * Tta-sure = Ttxclkesc * value
510 */
511 ta_sure = DIV_ROUND_UP(gotp.tasure, t_txclkesc);
512 /*
513 * The value of counter for HS Tta-wait
514 * Tta-wait for turnaround
515 * Tta-wait = Ttxclkesc * value
516 */
517 ta_wait = DIV_ROUND_UP(gotp.taget, t_txclkesc);
518
519 timing = inno_mipi_dphy_get_timing(inno);
520
521 /*
522 * The value of counter for HS Tlpx Time
523 * Tlpx = Tpin_txbyteclkhs * (2 + value)
524 */
525 if (inno->mipi_dphy_info->phy_max_rate == MAX_1GHZ) {
526 lpx = DIV_ROUND_UP(gotp.lpx, t_txbyteclkhs);
527 if (lpx >= 2)
528 lpx -= 2;
529 } else {
530 lpx = timing->lpx;
531 }
532
533 hs_prepare = timing->hs_prepare;
534 hs_trail = timing->hs_trail;
535 clk_lane_hs_zero = timing->clk_lane_hs_zero;
536 data_lane_hs_zero = timing->data_lane_hs_zero;
537 wakeup = 0x3ff;
538
539 for (i = REGISTER_PART_CLOCK_LANE; i <= REGISTER_PART_DATA3_LANE; i++) {
540 if (i == REGISTER_PART_CLOCK_LANE)
541 hs_zero = clk_lane_hs_zero;
542 else
543 hs_zero = data_lane_hs_zero;
544
545 phy_update_bits(inno, i, 0x05, T_LPX_CNT_MASK,
546 T_LPX_CNT(lpx));
547 phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK,
548 T_HS_PREPARE_CNT(hs_prepare));
549
550 if (inno->mipi_dphy_info->phy_max_rate == MAX_2_5GHZ)
551 phy_update_bits(inno, i, 0x06, T_HS_ZERO_CNT_HI_MASK,
552 T_HS_ZERO_CNT_HI(hs_zero >> 6));
553
554 phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_LO_MASK,
555 T_HS_ZERO_CNT_LO(hs_zero));
556 phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK,
557 T_HS_TRAIL_CNT(hs_trail));
558
559 if (inno->mipi_dphy_info->phy_max_rate == MAX_2_5GHZ)
560 phy_update_bits(inno, i, 0x11, T_HS_EXIT_CNT_HI_MASK,
561 T_HS_EXIT_CNT_HI(hs_exit >> 5));
562
563 phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_LO_MASK,
564 T_HS_EXIT_CNT_LO(hs_exit));
565
566 if (inno->mipi_dphy_info->phy_max_rate == MAX_2_5GHZ)
567 phy_update_bits(inno, i, 0x10, T_CLK_POST_HI_MASK,
568 T_CLK_POST_HI(clk_post >> 4));
569
570 phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_LO_MASK,
571 T_CLK_POST_CNT_LO(clk_post));
572 phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK,
573 T_CLK_PRE_CNT(clk_pre));
574 phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK,
575 T_WAKEUP_CNT_HI(wakeup >> 8));
576 phy_update_bits(inno, i, 0x0d, T_WAKEUP_CNT_LO_MASK,
577 T_WAKEUP_CNT_LO(wakeup));
578 phy_update_bits(inno, i, 0x10, T_TA_GO_CNT_MASK,
579 T_TA_GO_CNT(ta_go));
580 phy_update_bits(inno, i, 0x11, T_TA_SURE_CNT_MASK,
581 T_TA_SURE_CNT(ta_sure));
582 phy_update_bits(inno, i, 0x12, T_TA_WAIT_CNT_MASK,
583 T_TA_WAIT_CNT(ta_wait));
584 }
585 }
586
inno_mipi_dphy_lane_enable(struct inno_video_phy * inno)587 static void inno_mipi_dphy_lane_enable(struct inno_video_phy *inno)
588 {
589 u8 val = LANE_EN_CK;
590
591 switch (inno->lanes) {
592 case 1:
593 val |= LANE_EN_0;
594 break;
595 case 2:
596 val |= LANE_EN_1 | LANE_EN_0;
597 break;
598 case 3:
599 val |= LANE_EN_2 | LANE_EN_1 | LANE_EN_0;
600 break;
601 case 4:
602 default:
603 val |= LANE_EN_3 | LANE_EN_2 | LANE_EN_1 | LANE_EN_0;
604 break;
605 }
606
607 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, val);
608 }
609
inno_video_phy_mipi_mode_enable(struct inno_video_phy * inno)610 static void inno_video_phy_mipi_mode_enable(struct inno_video_phy *inno)
611 {
612 struct rockchip_phy *phy =
613 (struct rockchip_phy *)dev_get_driver_data(inno->dev);
614
615 /* Select MIPI mode */
616 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
617 MODE_ENABLE_MASK, MIPI_MODE_ENABLE);
618
619 /* set px30 pin_txclkesc_0 invert disable */
620 if (phy->soc_type == PX30_VIDEO_PHY || phy->soc_type == PX30S_VIDEO_PHY)
621 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x01,
622 INVERT_TXCLKESC_MASK, INVERT_TXCLKESC_DISABLE);
623
624 if (inno->mipi_dphy_info->phy_max_rate == MAX_2_5GHZ)
625 inno_mipi_dphy_max_2_5GHz_pll_enable(inno);
626 else
627 inno_mipi_dphy_max_1GHz_pll_enable(inno);
628
629 inno_mipi_dphy_reset(inno);
630 inno_mipi_dphy_timing_init(inno);
631 inno_mipi_dphy_lane_enable(inno);
632 }
633
inno_dsiphy_lvds_voltage_set(struct inno_video_phy * inno)634 static void inno_dsiphy_lvds_voltage_set(struct inno_video_phy *inno)
635 {
636 u32 val = 0;
637
638 /* This version of inno phy does not have voltage register, skip it. */
639 if (inno->mipi_dphy_info->phy_max_rate == MAX_1GHZ)
640 return;
641
642 if (inno->lvds_vcom >= 1000)
643 val |= LVDS_VCOM(3);
644 else if (inno->lvds_vcom >= 950)
645 val |= LVDS_VCOM(2);
646 else if (inno->lvds_vcom >= 900)
647 val |= LVDS_VCOM(0);
648 else
649 val |= LVDS_VCOM(1); /* 850mV */
650
651 if (inno->lvds_vod >= 400)
652 val |= LVDS_VOD(3);
653 else if (inno->lvds_vod >= 350)
654 val |= LVDS_VOD(2);
655 else if (inno->lvds_vod >= 300)
656 val |= LVDS_VOD(1);
657 else
658 val |= LVDS_VOD(0); /* 250mV */
659
660 phy_update_bits(inno, REGISTER_PART_LVDS, 0x04, LVDS_VCOM_MASK | LVDS_VOD_MASK, val);
661 }
662
inno_video_phy_lvds_mode_enable(struct inno_video_phy * inno)663 static void inno_video_phy_lvds_mode_enable(struct inno_video_phy *inno)
664 {
665 u8 prediv = 2;
666 u16 fbdiv = 28;
667 u32 val;
668 int ret;
669
670 /* Sample clock reverse direction */
671 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
672 SAMPLE_CLOCK_DIRECTION_MASK | LOWFRE_EN_MASK,
673 SAMPLE_CLOCK_DIRECTION_REVERSE |
674 PLL_OUTPUT_FREQUENCY_DIV_BY_1);
675
676 /* Reset LVDS digital logic */
677 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
678 LVDS_DIGITAL_INTERNAL_RESET_MASK,
679 LVDS_DIGITAL_INTERNAL_RESET_ENABLE);
680 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
681 LVDS_DIGITAL_INTERNAL_RESET_MASK,
682 LVDS_DIGITAL_INTERNAL_RESET_DISABLE);
683 inno_dsiphy_lvds_voltage_set(inno);
684 /* Select LVDS mode */
685 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
686 MODE_ENABLE_MASK, LVDS_MODE_ENABLE);
687
688 /* Configure PLL */
689 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
690 REG_PREDIV_MASK, REG_PREDIV(prediv));
691 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
692 REG_FBDIV_HI_MASK, REG_FBDIV_HI(fbdiv >> 8));
693 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
694 REG_FBDIV_LO_MASK, REG_FBDIV_LO(fbdiv));
695 phy_update_bits(inno, REGISTER_PART_LVDS, 0x08, 0xff, 0xfc);
696
697 /* Enable PLL and Bandgap */
698 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
699 LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK,
700 LVDS_PLL_POWER_ON | LVDS_BANDGAP_POWER_ON);
701
702 ret = readl_poll_timeout(inno->host.start + DSI_PHY_STATUS,
703 val, val & PHY_LOCK, 10000);
704 if (ret)
705 dev_err(phy->dev, "PLL is not lock\n");
706
707 /* Select PLL mode */
708 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1e,
709 PLL_MODE_SEL_MASK, PLL_MODE_SEL_LVDS_MODE);
710
711 /* Enable LVDS digital logic */
712 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
713 LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
714 LVDS_DIGITAL_INTERNAL_ENABLE);
715 /* Enable LVDS analog driver */
716 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
717 LVDS_LANE_EN_MASK, LVDS_CLK_LANE_EN |
718 LVDS_DATA_LANE0_EN | LVDS_DATA_LANE1_EN |
719 LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN);
720 }
721
inno_video_phy_ttl_mode_enable(struct inno_video_phy * inno)722 static void inno_video_phy_ttl_mode_enable(struct inno_video_phy *inno)
723 {
724 /* Reset digital logic */
725 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
726 LVDS_DIGITAL_INTERNAL_RESET_MASK,
727 LVDS_DIGITAL_INTERNAL_RESET_ENABLE);
728 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
729 LVDS_DIGITAL_INTERNAL_RESET_MASK,
730 LVDS_DIGITAL_INTERNAL_RESET_DISABLE);
731
732 /* Select TTL mode */
733 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
734 MODE_ENABLE_MASK, TTL_MODE_ENABLE);
735 /* Enable digital logic */
736 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
737 LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
738 LVDS_DIGITAL_INTERNAL_ENABLE);
739 /* Enable analog driver */
740 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
741 LVDS_LANE_EN_MASK, LVDS_CLK_LANE_EN |
742 LVDS_DATA_LANE0_EN | LVDS_DATA_LANE1_EN |
743 LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN);
744 /* Enable for clk lane in TTL mode */
745 host_update_bits(inno, DSI_PHY_RSTZ, PHY_ENABLECLK, PHY_ENABLECLK);
746 }
747
inno_video_phy_power_on(struct rockchip_phy * phy)748 static int inno_video_phy_power_on(struct rockchip_phy *phy)
749 {
750 struct inno_video_phy *inno = dev_get_priv(phy->dev);
751
752 /* Bandgap power on */
753 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
754 BANDGAP_POWER_MASK, BANDGAP_POWER_ON);
755 /* Enable power work */
756 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
757 POWER_WORK_MASK, POWER_WORK_ENABLE);
758
759 switch (inno->mode) {
760 case PHY_MODE_MIPI_DPHY:
761 inno_video_phy_mipi_mode_enable(inno);
762 break;
763 case PHY_MODE_VIDEO_LVDS:
764 inno_video_phy_lvds_mode_enable(inno);
765 break;
766 case PHY_MODE_VIDEO_TTL:
767 inno_video_phy_ttl_mode_enable(inno);
768 break;
769 default:
770 return -EINVAL;
771 }
772
773 return 0;
774 }
775
inno_video_phy_power_off(struct rockchip_phy * phy)776 static int inno_video_phy_power_off(struct rockchip_phy *phy)
777 {
778 struct inno_video_phy *inno = dev_get_priv(phy->dev);
779
780 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, 0);
781 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
782 REG_LDOPD_MASK | REG_PLLPD_MASK,
783 REG_LDOPD_POWER_DOWN | REG_PLLPD_POWER_DOWN);
784 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
785 POWER_WORK_MASK, POWER_WORK_DISABLE);
786 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
787 BANDGAP_POWER_MASK, BANDGAP_POWER_DOWN);
788
789 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, LVDS_LANE_EN_MASK, 0);
790 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
791 LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
792 LVDS_DIGITAL_INTERNAL_DISABLE);
793 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
794 LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK,
795 LVDS_PLL_POWER_OFF | LVDS_BANDGAP_POWER_DOWN);
796
797 return 0;
798 }
799
inno_video_phy_pll_round_rate(unsigned long prate,unsigned long rate,u8 * prediv,u16 * fbdiv)800 static unsigned long inno_video_phy_pll_round_rate(unsigned long prate,
801 unsigned long rate,
802 u8 *prediv, u16 *fbdiv)
803 {
804 unsigned long best_freq = 0;
805 unsigned long fref, fout;
806 u8 min_prediv, max_prediv;
807 u8 _prediv, best_prediv = 1;
808 u16 _fbdiv, best_fbdiv = 1;
809 u32 min_delta = 0xffffffff;
810
811 /*
812 * The PLL output frequency can be calculated using a simple formula:
813 * PLL_Output_Frequency = (FREF / PREDIV * FBDIV) / 2
814 * PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2
815 */
816 fref = prate / 2;
817 if (rate > 1000000000UL)
818 fout = 1000000000UL;
819 else
820 fout = rate;
821
822 /* 5Mhz < Fref / prediv < 40MHz */
823 min_prediv = DIV_ROUND_UP(fref, 40000000);
824 max_prediv = fref / 5000000;
825
826 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
827 u64 tmp;
828 u32 delta;
829
830 tmp = (u64)fout * _prediv;
831 do_div(tmp, fref);
832 _fbdiv = tmp;
833
834 /*
835 * The all possible settings of feedback divider are
836 * 12, 13, 14, 16, ~ 511
837 */
838 if (_fbdiv == 15)
839 continue;
840
841 if (_fbdiv < 12 || _fbdiv > 511)
842 continue;
843
844 tmp = (u64)_fbdiv * fref;
845 do_div(tmp, _prediv);
846
847 delta = abs(fout - tmp);
848 if (!delta) {
849 best_prediv = _prediv;
850 best_fbdiv = _fbdiv;
851 best_freq = tmp;
852 break;
853 } else if (delta < min_delta) {
854 best_prediv = _prediv;
855 best_fbdiv = _fbdiv;
856 best_freq = tmp;
857 min_delta = delta;
858 }
859 }
860
861 if (best_freq) {
862 *prediv = best_prediv;
863 *fbdiv = best_fbdiv;
864 }
865
866 return best_freq;
867 }
868
inno_video_phy_set_pll(struct rockchip_phy * phy,unsigned long rate)869 static unsigned long inno_video_phy_set_pll(struct rockchip_phy *phy,
870 unsigned long rate)
871 {
872 struct inno_video_phy *inno = dev_get_priv(phy->dev);
873 unsigned long fin, fout;
874 u16 fbdiv = 1;
875 u8 prediv = 1;
876
877 fin = 24000000;
878 fout = inno_video_phy_pll_round_rate(fin, rate, &prediv, &fbdiv);
879
880 dev_dbg(phy->dev, "fin=%lu, fout=%lu, prediv=%u, fbdiv=%u\n",
881 fin, fout, prediv, fbdiv);
882
883 inno->pll.prediv = prediv;
884 inno->pll.fbdiv = fbdiv;
885 inno->pll.rate = fout;
886
887 return fout;
888 }
889
inno_video_phy_set_mode(struct rockchip_phy * phy,enum phy_mode mode)890 static int inno_video_phy_set_mode(struct rockchip_phy *phy,
891 enum phy_mode mode)
892 {
893 struct inno_video_phy *inno = dev_get_priv(phy->dev);
894
895 switch (mode) {
896 case PHY_MODE_MIPI_DPHY:
897 case PHY_MODE_VIDEO_LVDS:
898 case PHY_MODE_VIDEO_TTL:
899 inno->mode = mode;
900 break;
901 default:
902 return -EINVAL;
903 }
904
905 return 0;
906 }
907
inno_video_phy_probe(struct udevice * dev)908 static int inno_video_phy_probe(struct udevice *dev)
909 {
910 struct inno_video_phy *inno = dev_get_priv(dev);
911 struct rockchip_phy *tmp_phy;
912 struct rockchip_phy *phy;
913 int ret;
914
915 phy = calloc(1, sizeof(*phy));
916 if (!phy)
917 return -ENOMEM;
918
919 tmp_phy = (struct rockchip_phy *)dev_get_driver_data(dev);
920 dev->driver_data = (ulong)phy;
921 memcpy(phy, tmp_phy, sizeof(*phy));
922
923 inno->dev = dev;
924 inno->mipi_dphy_info = phy->data;
925 if (soc_is_px30s())
926 inno->mipi_dphy_info = &inno_video_mipi_dphy_max_2_5GHz;
927
928 inno->lanes = ofnode_read_u32_default(dev->node, "inno,lanes", 4);
929 inno->lvds_vcom = ofnode_read_u32_default(dev->node, "inno,lvds-vcom", 950);
930 inno->lvds_vod = ofnode_read_u32_default(dev->node, "inno,lvds-vod", 350);
931
932 ret = dev_read_resource(dev, 0, &inno->phy);
933 if (ret < 0) {
934 dev_err(dev, "resource \"phy\" not found\n");
935 return ret;
936 }
937
938 ret = dev_read_resource(dev, 1, &inno->host);
939 if (ret < 0) {
940 dev_err(dev, "resource \"host\" not found\n");
941 return ret;
942 }
943
944 phy->dev = dev;
945
946 return 0;
947 }
948
949 static const struct rockchip_phy_funcs inno_video_phy_funcs = {
950 .power_on = inno_video_phy_power_on,
951 .power_off = inno_video_phy_power_off,
952 .set_pll = inno_video_phy_set_pll,
953 .set_mode = inno_video_phy_set_mode,
954 };
955
956 static struct rockchip_phy px30_inno_video_phy_driver_data = {
957 .soc_type = PX30_VIDEO_PHY,
958 .funcs = &inno_video_phy_funcs,
959 .data = &inno_video_mipi_dphy_max_1GHz,
960 };
961
962 static struct rockchip_phy px30s_inno_video_phy_driver_data = {
963 .soc_type = PX30S_VIDEO_PHY,
964 .funcs = &inno_video_phy_funcs,
965 .data = &inno_video_mipi_dphy_max_2_5GHz,
966 };
967
968 static struct rockchip_phy rk3128_inno_video_phy_driver_data = {
969 .soc_type = RK3128_VIDEO_PHY,
970 .funcs = &inno_video_phy_funcs,
971 .data = &inno_video_mipi_dphy_max_1GHz,
972 };
973
974 static struct rockchip_phy rk3368_inno_video_phy_driver_data = {
975 .soc_type = RK3368_VIDEO_PHY,
976 .funcs = &inno_video_phy_funcs,
977 .data = &inno_video_mipi_dphy_max_1GHz,
978 };
979
980 static struct rockchip_phy rk3568_inno_video_phy_driver_data = {
981 .soc_type = RK3568_VIDEO_PHY,
982 .funcs = &inno_video_phy_funcs,
983 .data = &inno_video_mipi_dphy_max_2_5GHz,
984 };
985
986 static const struct udevice_id inno_video_phy_ids[] = {
987 {
988 .compatible = "rockchip,px30-video-phy",
989 .data = (ulong)&px30_inno_video_phy_driver_data,
990 },
991 {
992 .compatible = "rockchip,px30s-video-phy",
993 .data = (ulong)&px30s_inno_video_phy_driver_data,
994 },
995 {
996 .compatible = "rockchip,rk3128-video-phy",
997 .data = (ulong)&rk3128_inno_video_phy_driver_data,
998 },
999 {
1000 .compatible = "rockchip,rk3368-video-phy",
1001 .data = (ulong)&rk3368_inno_video_phy_driver_data,
1002 },
1003 {
1004 .compatible = "rockchip,rk3568-video-phy",
1005 .data = (ulong)&rk3568_inno_video_phy_driver_data,
1006 },
1007 {}
1008 };
1009
1010 U_BOOT_DRIVER(inno_video_combo_phy) = {
1011 .name = "inno_video_combo_phy",
1012 .id = UCLASS_PHY,
1013 .of_match = inno_video_phy_ids,
1014 .probe = inno_video_phy_probe,
1015 .priv_auto_alloc_size = sizeof(struct inno_video_phy),
1016 };
1017