1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 /* 3 * Copyright (c) 2023 Rockchip Electronics Co. Ltd. 4 * Author: Elaine Zhang <zhangqing@rock-chips.com> 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H 9 10 /* cru-clocks indices */ 11 12 /* cru plls */ 13 #define PLL_BPLL 1 14 #define PLL_LPLL 3 15 #define PLL_VPLL 4 16 #define PLL_AUPLL 5 17 #define PLL_CPLL 6 18 #define PLL_GPLL 7 19 #define PLL_PPLL 9 20 #define ARMCLK_L 10 21 #define ARMCLK_B 11 22 23 /* cru clocks */ 24 #define CLK_CPLL_DIV20 15 25 #define CLK_CPLL_DIV10 16 26 #define CLK_GPLL_DIV8 17 27 #define CLK_GPLL_DIV6 18 28 #define CLK_CPLL_DIV4 19 29 #define CLK_GPLL_DIV4 20 30 #define CLK_SPLL_DIV2 21 31 #define CLK_GPLL_DIV3 22 32 #define CLK_CPLL_DIV2 23 33 #define CLK_GPLL_DIV2 24 34 #define CLK_SPLL_DIV1 25 35 #define PCLK_TOP_ROOT 26 36 #define ACLK_TOP 27 37 #define HCLK_TOP 28 38 #define CLK_AUDIO_FRAC_0 29 39 #define CLK_AUDIO_FRAC_1 30 40 #define CLK_AUDIO_FRAC_2 31 41 #define CLK_AUDIO_FRAC_3 32 42 #define CLK_UART_FRAC_0 33 43 #define CLK_UART_FRAC_1 34 44 #define CLK_UART_FRAC_2 35 45 #define CLK_UART1_SRC_TOP 36 46 #define CLK_AUDIO_INT_0 37 47 #define CLK_AUDIO_INT_1 38 48 #define CLK_AUDIO_INT_2 39 49 #define CLK_PDM0_SRC_TOP 40 50 #define CLK_PDM1_OUT 41 51 #define CLK_GMAC0_125M_SRC 42 52 #define CLK_GMAC1_125M_SRC 43 53 #define LCLK_ASRC_SRC_0 44 54 #define LCLK_ASRC_SRC_1 45 55 #define REF_CLK0_OUT_PLL 46 56 #define REF_CLK1_OUT_PLL 47 57 #define REF_CLK2_OUT_PLL 48 58 #define REFCLKO25M_GMAC0_OUT 49 59 #define REFCLKO25M_GMAC1_OUT 50 60 #define CLK_CIFOUT_OUT 51 61 #define CLK_GMAC0_RMII_CRU 52 62 #define CLK_GMAC1_RMII_CRU 53 63 #define CLK_OTPC_AUTO_RD_G 54 64 #define CLK_OTP_PHY_G 55 65 #define CLK_MIPI_CAMERAOUT_M0 56 66 #define CLK_MIPI_CAMERAOUT_M1 57 67 #define CLK_MIPI_CAMERAOUT_M2 58 68 #define MCLK_PDM0_SRC_TOP 59 69 #define HCLK_AUDIO_ROOT 60 70 #define HCLK_ASRC_2CH_0 61 71 #define HCLK_ASRC_2CH_1 62 72 #define HCLK_ASRC_4CH_0 63 73 #define HCLK_ASRC_4CH_1 64 74 #define CLK_ASRC_2CH_0 65 75 #define CLK_ASRC_2CH_1 66 76 #define CLK_ASRC_4CH_0 67 77 #define CLK_ASRC_4CH_1 68 78 #define MCLK_SAI0_8CH_SRC 69 79 #define MCLK_SAI0_8CH 70 80 #define HCLK_SAI0_8CH 71 81 #define HCLK_SPDIF_RX0 72 82 #define MCLK_SPDIF_RX0 73 83 #define HCLK_SPDIF_RX1 74 84 #define MCLK_SPDIF_RX1 75 85 #define MCLK_SAI1_8CH_SRC 76 86 #define MCLK_SAI1_8CH 77 87 #define HCLK_SAI1_8CH 78 88 #define MCLK_SAI2_2CH_SRC 79 89 #define MCLK_SAI2_2CH 80 90 #define HCLK_SAI2_2CH 81 91 #define MCLK_SAI3_2CH_SRC 82 92 #define MCLK_SAI3_2CH 83 93 #define HCLK_SAI3_2CH 84 94 #define MCLK_SAI4_2CH_SRC 85 95 #define MCLK_SAI4_2CH 86 96 #define HCLK_SAI4_2CH 87 97 #define HCLK_ACDCDIG_DSM 88 98 #define MCLK_ACDCDIG_DSM 89 99 #define CLK_PDM1 90 100 #define HCLK_PDM1 91 101 #define MCLK_PDM1 92 102 #define HCLK_SPDIF_TX0 93 103 #define MCLK_SPDIF_TX0 94 104 #define HCLK_SPDIF_TX1 95 105 #define MCLK_SPDIF_TX1 96 106 #define CLK_SAI1_MCLKOUT 97 107 #define CLK_SAI2_MCLKOUT 98 108 #define CLK_SAI3_MCLKOUT 99 109 #define CLK_SAI4_MCLKOUT 100 110 #define CLK_SAI0_MCLKOUT 101 111 #define HCLK_BUS_ROOT 102 112 #define PCLK_BUS_ROOT 103 113 #define ACLK_BUS_ROOT 104 114 #define HCLK_CAN0 105 115 #define CLK_CAN0 106 116 #define HCLK_CAN1 107 117 #define CLK_CAN1 108 118 #define CLK_KEY_SHIFT 109 119 #define PCLK_I2C1 110 120 #define PCLK_I2C2 111 121 #define PCLK_I2C3 112 122 #define PCLK_I2C4 113 123 #define PCLK_I2C5 114 124 #define PCLK_I2C6 115 125 #define PCLK_I2C7 116 126 #define PCLK_I2C8 117 127 #define PCLK_I2C9 118 128 #define PCLK_WDT_BUSMCU 119 129 #define TCLK_WDT_BUSMCU 120 130 #define ACLK_GIC 121 131 #define CLK_I2C1 122 132 #define CLK_I2C2 123 133 #define CLK_I2C3 124 134 #define CLK_I2C4 125 135 #define CLK_I2C5 126 136 #define CLK_I2C6 127 137 #define CLK_I2C7 128 138 #define CLK_I2C8 129 139 #define CLK_I2C9 130 140 #define PCLK_SARADC 131 141 #define CLK_SARADC 132 142 #define PCLK_TSADC 133 143 #define CLK_TSADC 134 144 #define PCLK_UART0 135 145 #define PCLK_UART2 136 146 #define PCLK_UART3 137 147 #define PCLK_UART4 138 148 #define PCLK_UART5 139 149 #define PCLK_UART6 140 150 #define PCLK_UART7 141 151 #define PCLK_UART8 142 152 #define PCLK_UART9 143 153 #define PCLK_UART10 144 154 #define PCLK_UART11 145 155 #define SCLK_UART0 146 156 #define SCLK_UART2 147 157 #define SCLK_UART3 148 158 #define SCLK_UART4 149 159 #define SCLK_UART5 150 160 #define SCLK_UART6 151 161 #define SCLK_UART7 152 162 #define SCLK_UART8 153 163 #define SCLK_UART9 154 164 #define SCLK_UART10 155 165 #define SCLK_UART11 156 166 #define PCLK_SPI0 157 167 #define PCLK_SPI1 158 168 #define PCLK_SPI2 159 169 #define PCLK_SPI3 160 170 #define PCLK_SPI4 161 171 #define CLK_SPI0 162 172 #define CLK_SPI1 163 173 #define CLK_SPI2 164 174 #define CLK_SPI3 165 175 #define CLK_SPI4 166 176 #define PCLK_WDT0 167 177 #define TCLK_WDT0 168 178 #define PCLK_PWM1 169 179 #define CLK_PWM1 170 180 #define CLK_OSC_PWM1 171 181 #define CLK_RC_PWM1 172 182 #define PCLK_BUSTIMER0 173 183 #define PCLK_BUSTIMER1 174 184 #define CLK_TIMER0_ROOT 175 185 #define CLK_TIMER0 176 186 #define CLK_TIMER1 177 187 #define CLK_TIMER2 178 188 #define CLK_TIMER3 179 189 #define CLK_TIMER4 180 190 #define CLK_TIMER5 181 191 #define PCLK_MAILBOX0 182 192 #define PCLK_GPIO1 183 193 #define DBCLK_GPIO1 184 194 #define PCLK_GPIO2 185 195 #define DBCLK_GPIO2 186 196 #define PCLK_GPIO3 187 197 #define DBCLK_GPIO3 188 198 #define PCLK_GPIO4 189 199 #define DBCLK_GPIO4 190 200 #define ACLK_DECOM 191 201 #define PCLK_DECOM 192 202 #define DCLK_DECOM 193 203 #define CLK_TIMER1_ROOT 194 204 #define CLK_TIMER6 195 205 #define CLK_TIMER7 196 206 #define CLK_TIMER8 197 207 #define CLK_TIMER9 198 208 #define CLK_TIMER10 199 209 #define CLK_TIMER11 200 210 #define ACLK_DMAC0 201 211 #define ACLK_DMAC1 202 212 #define ACLK_DMAC2 203 213 #define ACLK_SPINLOCK 204 214 #define HCLK_I3C0 205 215 #define HCLK_I3C1 206 216 #define HCLK_BUS_CM0_ROOT 207 217 #define FCLK_BUS_CM0_CORE 208 218 #define CLK_BUS_CM0_RTC 209 219 #define PCLK_PMU2 210 220 #define PCLK_PWM2 211 221 #define CLK_PWM2 212 222 #define CLK_RC_PWM2 213 223 #define CLK_OSC_PWM2 214 224 #define CLK_FREQ_PWM1 215 225 #define CLK_COUNTER_PWM1 216 226 #define SAI_SCLKIN_FREQ 217 227 #define SAI_SCLKIN_COUNTER 218 228 #define CLK_I3C0 219 229 #define CLK_I3C1 220 230 #define PCLK_CSIDPHY1 221 231 #define PCLK_DDR_ROOT 222 232 #define PCLK_DDR_MON_CH0 223 233 #define TMCLK_DDR_MON_CH0 224 234 #define ACLK_DDR_ROOT 225 235 #define HCLK_DDR_ROOT 226 236 #define FCLK_DDR_CM0_CORE 227 237 #define CLK_DDR_TIMER_ROOT 228 238 #define CLK_DDR_TIMER0 229 239 #define CLK_DDR_TIMER1 230 240 #define TCLK_WDT_DDR 231 241 #define PCLK_WDT 232 242 #define PCLK_TIMER 233 243 #define CLK_DDR_CM0_RTC 234 244 #define ACLK_RKNN0 235 245 #define ACLK_RKNN1 236 246 #define HCLK_RKNN_ROOT 237 247 #define CLK_RKNN_DSU0 238 248 #define PCLK_NPUTOP_ROOT 239 249 #define PCLK_NPU_TIMER 240 250 #define CLK_NPUTIMER_ROOT 241 251 #define CLK_NPUTIMER0 242 252 #define CLK_NPUTIMER1 243 253 #define PCLK_NPU_WDT 244 254 #define TCLK_NPU_WDT 245 255 #define ACLK_RKNN_CBUF 246 256 #define HCLK_NPU_CM0_ROOT 247 257 #define FCLK_NPU_CM0_CORE 248 258 #define CLK_NPU_CM0_RTC 249 259 #define HCLK_RKNN_CBUF 250 260 #define HCLK_NVM_ROOT 251 261 #define ACLK_NVM_ROOT 252 262 #define SCLK_FSPI_X2 253 263 #define HCLK_FSPI 254 264 #define CCLK_SRC_EMMC 255 265 #define HCLK_EMMC 256 266 #define ACLK_EMMC 257 267 #define BCLK_EMMC 258 268 #define TCLK_EMMC 259 269 #define PCLK_PHP_ROOT 260 270 #define ACLK_PHP_ROOT 261 271 #define PCLK_PCIE0 262 272 #define CLK_PCIE0_AUX 263 273 #define ACLK_PCIE0_MST 264 274 #define ACLK_PCIE0_SLV 265 275 #define ACLK_PCIE0_DBI 266 276 #define ACLK_USB3OTG1 267 277 #define CLK_REF_USB3OTG1 268 278 #define CLK_SUSPEND_USB3OTG1 269 279 #define ACLK_MMU0 270 280 #define ACLK_SLV_MMU0 271 281 #define ACLK_MMU1 272 282 #define ACLK_SLV_MMU1 273 283 #define PCLK_PCIE1 275 284 #define CLK_PCIE1_AUX 276 285 #define ACLK_PCIE1_MST 277 286 #define ACLK_PCIE1_SLV 278 287 #define ACLK_PCIE1_DBI 279 288 #define CLK_RXOOB0 280 289 #define CLK_RXOOB1 281 290 #define CLK_PMALIVE0 282 291 #define CLK_PMALIVE1 283 292 #define ACLK_SATA0 284 293 #define ACLK_SATA1 285 294 #define CLK_USB3OTG1_PIPE_PCLK 286 295 #define CLK_USB3OTG1_UTMI 287 296 #define CLK_USB3OTG0_PIPE_PCLK 288 297 #define CLK_USB3OTG0_UTMI 289 298 #define HCLK_SDGMAC_ROOT 290 299 #define ACLK_SDGMAC_ROOT 291 300 #define PCLK_SDGMAC_ROOT 292 301 #define ACLK_GMAC0 293 302 #define ACLK_GMAC1 294 303 #define PCLK_GMAC0 295 304 #define PCLK_GMAC1 296 305 #define CCLK_SRC_SDIO 297 306 #define HCLK_SDIO 298 307 #define CLK_GMAC1_PTP_REF 299 308 #define CLK_GMAC0_PTP_REF 300 309 #define CLK_GMAC1_PTP_REF_SRC 301 310 #define CLK_GMAC0_PTP_REF_SRC 302 311 #define CCLK_SRC_SDMMC0 303 312 #define HCLK_SDMMC0 304 313 #define SCLK_FSPI1_X2 305 314 #define HCLK_FSPI1 306 315 #define ACLK_DSMC_ROOT 307 316 #define ACLK_DSMC 308 317 #define PCLK_DSMC 309 318 #define CLK_DSMC_SYS 310 319 #define HCLK_HSGPIO 311 320 #define CLK_HSGPIO_TX 312 321 #define CLK_HSGPIO_RX 313 322 #define ACLK_HSGPIO 314 323 #define PCLK_PHPPHY_ROOT 315 324 #define PCLK_PCIE2_COMBOPHY0 316 325 #define PCLK_PCIE2_COMBOPHY1 317 326 #define CLK_PCIE_100M_SRC 318 327 #define CLK_PCIE_100M_NDUTY_SRC 319 328 #define CLK_REF_PCIE0_PHY 320 329 #define CLK_REF_PCIE1_PHY 321 330 #define CLK_REF_MPHY_26M 322 331 #define HCLK_RKVDEC_ROOT 323 332 #define ACLK_RKVDEC_ROOT 324 333 #define HCLK_RKVDEC 325 334 #define CLK_RKVDEC_HEVC_CA 326 335 #define CLK_RKVDEC_CORE 327 336 #define ACLK_UFS_ROOT 328 337 #define ACLK_USB_ROOT 329 338 #define PCLK_USB_ROOT 330 339 #define ACLK_USB3OTG0 331 340 #define CLK_REF_USB3OTG0 332 341 #define CLK_SUSPEND_USB3OTG0 333 342 #define ACLK_MMU2 334 343 #define ACLK_SLV_MMU2 335 344 #define ACLK_UFS_SYS 336 345 #define ACLK_VPU_ROOT 337 346 #define ACLK_VPU_MID_ROOT 338 347 #define HCLK_VPU_ROOT 339 348 #define ACLK_JPEG_ROOT 340 349 #define ACLK_VPU_LOW_ROOT 341 350 #define HCLK_RGA2E_0 342 351 #define ACLK_RGA2E_0 342 352 #define CLK_CORE_RGA2E_0 344 353 #define ACLK_JPEG 345 354 #define HCLK_JPEG 346 355 #define HCLK_VDPP 347 356 #define ACLK_VDPP 348 357 #define CLK_CORE_VDPP 349 358 #define HCLK_RGA2E_1 350 359 #define ACLK_RGA2E_1 351 360 #define CLK_CORE_RGA2E_1 352 361 #define DCLK_EBC_FRAC_SRC 353 362 #define HCLK_EBC 354 363 #define ACLK_EBC 355 364 #define DCLK_EBC 356 365 #define HCLK_VEPU0_ROOT 357 366 #define ACLK_VEPU0_ROOT 358 367 #define HCLK_VEPU0 359 368 #define ACLK_VEPU0 360 369 #define CLK_VEPU0_CORE 361 370 #define ACLK_VI_ROOT 362 371 #define HCLK_VI_ROOT 363 372 #define PCLK_VI_ROOT 364 373 #define DCLK_VICAP 365 374 #define ACLK_VICAP 366 375 #define HCLK_VICAP 367 376 #define CLK_ISP_CORE 368 377 #define CLK_ISP_CORE_MARVIN 369 378 #define CLK_ISP_CORE_VICAP 370 379 #define ACLK_ISP 371 380 #define HCLK_ISP 372 381 #define ACLK_VPSS 373 382 #define HCLK_VPSS 374 383 #define CLK_CORE_VPSS 375 384 #define PCLK_CSI_HOST_0 376 385 #define PCLK_CSI_HOST_1 377 386 #define PCLK_CSI_HOST_2 378 387 #define PCLK_CSI_HOST_3 379 388 #define PCLK_CSI_HOST_4 380 389 #define ICLK_CSIHOST01 381 390 #define ICLK_CSIHOST0 382 391 #define CLK_ISP_PVTPLL_SRC 383 392 #define ACLK_VI_ROOT_INTER 384 393 #define CLK_VICAP_I0CLK 385 394 #define CLK_VICAP_I1CLK 386 395 #define CLK_VICAP_I2CLK 387 396 #define CLK_VICAP_I3CLK 388 397 #define CLK_VICAP_I4CLK 389 398 #define ACLK_VOP_ROOT 390 399 #define HCLK_VOP_ROOT 391 400 #define PCLK_VOP_ROOT 392 401 #define HCLK_VOP 393 402 #define ACLK_VOP 394 403 #define DCLK_VP0_SRC 395 404 #define DCLK_VP1_SRC 396 405 #define DCLK_VP2_SRC 397 406 #define DCLK_VP0 398 407 #define DCLK_VP1 400 408 #define DCLK_VP2 401 409 #define PCLK_VOPGRF 402 410 #define ACLK_VO0_ROOT 403 411 #define HCLK_VO0_ROOT 404 412 #define PCLK_VO0_ROOT 405 413 #define PCLK_VO0_GRF 406 414 #define ACLK_HDCP0 407 415 #define HCLK_HDCP0 408 416 #define PCLK_HDCP0 409 417 #define CLK_TRNG0_SKP 410 418 #define PCLK_DSIHOST0 411 419 #define CLK_DSIHOST0 412 420 #define PCLK_HDMITX0 413 421 #define CLK_HDMITX0_EARC 414 422 #define CLK_HDMITX0_REF 415 423 #define PCLK_EDP0 416 424 #define CLK_EDP0_24M 417 425 #define CLK_EDP0_200M 418 426 #define MCLK_SAI5_8CH_SRC 419 427 #define MCLK_SAI5_8CH 420 428 #define HCLK_SAI5_8CH 421 429 #define MCLK_SAI6_8CH_SRC 422 430 #define MCLK_SAI6_8CH 423 431 #define HCLK_SAI6_8CH 424 432 #define HCLK_SPDIF_TX2 425 433 #define MCLK_SPDIF_TX2 426 434 #define HCLK_SPDIF_RX2 427 435 #define MCLK_SPDIF_RX2 428 436 #define HCLK_SAI8_8CH 429 437 #define MCLK_SAI8_8CH_SRC 430 438 #define MCLK_SAI8_8CH 431 439 #define ACLK_VO1_ROOT 432 440 #define HCLK_VO1_ROOT 433 441 #define PCLK_VO1_ROOT 434 442 #define MCLK_SAI7_8CH_SRC 435 443 #define MCLK_SAI7_8CH 436 444 #define HCLK_SAI7_8CH 437 445 #define HCLK_SPDIF_TX3 438 446 #define HCLK_SPDIF_TX4 439 447 #define HCLK_SPDIF_TX5 440 448 #define MCLK_SPDIF_TX3 441 449 #define CLK_AUX16MHZ_0 442 450 #define ACLK_DP0 443 451 #define PCLK_DP0 444 452 #define PCLK_VO1_GRF 445 453 #define ACLK_HDCP1 446 454 #define HCLK_HDCP1 447 455 #define PCLK_HDCP1 448 456 #define CLK_TRNG1_SKP 449 457 #define HCLK_SAI9_8CH 450 458 #define MCLK_SAI9_8CH_SRC 451 459 #define MCLK_SAI9_8CH 452 460 #define MCLK_SPDIF_TX4 453 461 #define MCLK_SPDIF_TX5 454 462 #define CLK_GPU_SRC_PRE 455 463 #define CLK_GPU 456 464 #define PCLK_GPU_ROOT 457 465 #define ACLK_CENTER_ROOT 458 466 #define ACLK_CENTER_LOW_ROOT 459 467 #define HCLK_CENTER_ROOT 460 468 #define PCLK_CENTER_ROOT 461 469 #define ACLK_DMA2DDR 462 470 #define ACLK_DDR_SHAREMEM 463 471 #define PCLK_DMA2DDR 464 472 #define PCLK_SHAREMEM 465 473 #define HCLK_VEPU1_ROOT 466 474 #define ACLK_VEPU1_ROOT 467 475 #define HCLK_VEPU1 468 476 #define ACLK_VEPU1 469 477 #define CLK_VEPU1_CORE 470 478 #define CLK_JDBCK_DAP 471 479 #define PCLK_MIPI_DCPHY 472 480 #define CLK_32K_USB2DEBUG 473 481 #define PCLK_CSIDPHY 474 482 #define PCLK_USBDPPHY 475 483 #define CLK_PMUPHY_REF_SRC 476 484 #define CLK_USBDP_COMBO_PHY_IMMORTAL 477 485 #define CLK_HDMITXHPD 478 486 #define PCLK_MPHY 479 487 #define CLK_REF_OSC_MPHY 480 488 #define CLK_REF_UFS_CLKOUT 481 489 #define HCLK_PMU1_ROOT 482 490 #define HCLK_PMU_CM0_ROOT 483 491 #define CLK_200M_PMU_SRC 484 492 #define CLK_100M_PMU_SRC 485 493 #define CLK_50M_PMU_SRC 486 494 #define FCLK_PMU_CM0_CORE 487 495 #define CLK_PMU_CM0_RTC 488 496 #define PCLK_PMU1 489 497 #define CLK_PMU1 490 498 #define PCLK_PMU1WDT 491 499 #define TCLK_PMU1WDT 492 500 #define PCLK_PMUTIMER 493 501 #define CLK_PMUTIMER_ROOT 494 502 #define CLK_PMUTIMER0 495 503 #define CLK_PMUTIMER1 496 504 #define PCLK_PMU1PWM 497 505 #define CLK_PMU1PWM 498 506 #define CLK_PMU1PWM_OSC 499 507 #define PCLK_PMUPHY_ROOT 500 508 #define PCLK_I2C0 501 509 #define CLK_I2C0 502 510 #define SCLK_UART1 503 511 #define PCLK_UART1 504 512 #define CLK_PMU1PWM_RC 505 513 #define CLK_PDM0 506 514 #define HCLK_PDM0 507 515 #define MCLK_PDM0 508 516 #define HCLK_VAD 509 517 #define CLK_OSCCHK_PVTM 510 518 #define CLK_PDM0_OUT 511 519 #define CLK_HPTIMER_SRC 512 520 #define PCLK_PMU0_ROOT 516 521 #define PCLK_PMU0 517 522 #define PCLK_GPIO0 518 523 #define DBCLK_GPIO0 519 524 #define CLK_OSC0_PMU1 520 525 #define PCLK_PMU1_ROOT 521 526 #define XIN_OSC0_DIV 522 527 #define ACLK_USB 523 528 #define ACLK_UFS 524 529 #define ACLK_SDGMAC 525 530 #define HCLK_SDGMAC 526 531 #define PCLK_SDGMAC 527 532 #define HCLK_VO1 528 533 #define HCLK_VO0 529 534 #define PCLK_CCI_ROOT 532 535 #define ACLK_CCI_ROOT 533 536 #define HCLK_VO0VOP_CHANNEL 534 537 #define ACLK_VO0VOP_CHANNEL 535 538 #define ACLK_TOP_MID 536 539 #define ACLK_SECURE_HIGH 537 540 #define CLK_USBPHY_REF_SRC 538 541 #define CLK_PHY_REF_SRC 539 542 #define CLK_CPLL_REF_SRC 540 543 #define CLK_AUPLL_REF_SRC 541 544 #define PCLK_SECURE_NS 542 545 #define HCLK_SECURE_NS 543 546 #define ACLK_SECURE_NS 544 547 #define PCLK_OTPC_NS 545 548 #define HCLK_CRYPTO_NS 546 549 #define HCLK_TRNG_NS 547 550 #define CLK_OTPC_NS 548 551 #define SCLK_DSU 549 552 #define SCLK_DDR 550 553 #define ACLK_CRYPTO_NS 551 554 #define CLK_PKA_CRYPTO_NS 552 555 556 /* secure clk */ 557 #define CLK_STIMER0_ROOT 600 558 #define CLK_STIMER1_ROOT 601 559 #define PCLK_SECURE_S 602 560 #define HCLK_SECURE_S 603 561 #define ACLK_SECURE_S 604 562 #define CLK_PKA_CRYPTO_S 605 563 #define HCLK_VO1_S 606 564 #define PCLK_VO1_S 607 565 #define HCLK_VO0_S 608 566 #define PCLK_VO0_S 609 567 #define PCLK_KLAD 610 568 #define HCLK_CRYPTO_S 611 569 #define HCLK_KLAD 612 570 #define ACLK_CRYPTO_S 613 571 #define HCLK_TRNG_S 614 572 #define PCLK_OTPC_S 615 573 #define CLK_OTPC_S 616 574 #define PCLK_WDT_S 617 575 #define TCLK_WDT_S 618 576 #define PCLK_HDCP0_TRNG 619 577 #define PCLK_HDCP1_TRNG 620 578 #define HCLK_HDCP_KEY0 621 579 #define HCLK_HDCP_KEY1 622 580 #define PCLK_EDP_S 623 581 #define ACLK_KLAD 624 582 583 #define CLK_NR_CLKS (ACLK_KLAD + 1) 584 585 /********Name=SOFTRST_CON01,Offset=0xA04********/ 586 #define SRST_A_TOP_BIU 19 587 #define SRST_P_TOP_BIU 21 588 #define SRST_A_TOP_MID_BIU 22 589 #define SRST_A_SECURE_HIGH_BIU 23 590 #define SRST_H_TOP_BIU 30 591 /********Name=SOFTRST_CON02,Offset=0xA08********/ 592 #define SRST_H_VO0VOP_CHANNEL_BIU 32 593 #define SRST_A_VO0VOP_CHANNEL_BIU 33 594 /********Name=SOFTRST_CON06,Offset=0xA18********/ 595 #define SRST_BISRINTF 98 596 /********Name=SOFTRST_CON07,Offset=0xA1C********/ 597 #define SRST_H_AUDIO_BIU 114 598 #define SRST_H_ASRC_2CH_0 115 599 #define SRST_H_ASRC_2CH_1 116 600 #define SRST_H_ASRC_4CH_0 117 601 #define SRST_H_ASRC_4CH_1 118 602 #define SRST_ASRC_2CH_0 119 603 #define SRST_ASRC_2CH_1 120 604 #define SRST_ASRC_4CH_0 121 605 #define SRST_ASRC_4CH_1 122 606 #define SRST_M_SAI0_8CH 124 607 #define SRST_H_SAI0_8CH 125 608 #define SRST_H_SPDIF_RX0 126 609 #define SRST_M_SPDIF_RX0 127 610 /********Name=SOFTRST_CON08,Offset=0xA20********/ 611 #define SRST_H_SPDIF_RX1 128 612 #define SRST_M_SPDIF_RX1 129 613 #define SRST_M_SAI1_8CH 133 614 #define SRST_H_SAI1_8CH 134 615 #define SRST_M_SAI2_2CH 136 616 #define SRST_H_SAI2_2CH 138 617 #define SRST_M_SAI3_2CH 140 618 #define SRST_H_SAI3_2CH 142 619 /********Name=SOFTRST_CON09,Offset=0xA24********/ 620 #define SRST_M_SAI4_2CH 144 621 #define SRST_H_SAI4_2CH 146 622 #define SRST_H_ACDCDIG_DSM 147 623 #define SRST_M_ACDCDIG_DSM 148 624 #define SRST_PDM1 149 625 #define SRST_H_PDM1 151 626 #define SRST_M_PDM1 152 627 #define SRST_H_SPDIF_TX0 153 628 #define SRST_M_SPDIF_TX0 154 629 #define SRST_H_SPDIF_TX1 155 630 #define SRST_M_SPDIF_TX1 156 631 /********Name=SOFTRST_CON11,Offset=0xA2C********/ 632 #define SRST_A_BUS_BIU 179 633 #define SRST_P_BUS_BIU 180 634 #define SRST_P_CRU 181 635 #define SRST_H_CAN0 182 636 #define SRST_CAN0 183 637 #define SRST_H_CAN1 184 638 #define SRST_CAN1 185 639 #define SRST_P_INTMUX2BUS 188 640 #define SRST_P_VCCIO_IOC 189 641 #define SRST_H_BUS_BIU 190 642 #define SRST_KEY_SHIFT 191 643 /********Name=SOFTRST_CON12,Offset=0xA30********/ 644 #define SRST_P_I2C1 192 645 #define SRST_P_I2C2 193 646 #define SRST_P_I2C3 194 647 #define SRST_P_I2C4 195 648 #define SRST_P_I2C5 196 649 #define SRST_P_I2C6 197 650 #define SRST_P_I2C7 198 651 #define SRST_P_I2C8 199 652 #define SRST_P_I2C9 200 653 #define SRST_P_WDT_BUSMCU 201 654 #define SRST_T_WDT_BUSMCU 202 655 #define SRST_A_GIC 203 656 #define SRST_I2C1 204 657 #define SRST_I2C2 205 658 #define SRST_I2C3 206 659 #define SRST_I2C4 207 660 /********Name=SOFTRST_CON13,Offset=0xA34********/ 661 #define SRST_I2C5 208 662 #define SRST_I2C6 209 663 #define SRST_I2C7 210 664 #define SRST_I2C8 211 665 #define SRST_I2C9 212 666 #define SRST_P_SARADC 214 667 #define SRST_SARADC 215 668 #define SRST_P_TSADC 216 669 #define SRST_TSADC 217 670 #define SRST_P_UART0 218 671 #define SRST_P_UART2 219 672 #define SRST_P_UART3 220 673 #define SRST_P_UART4 221 674 #define SRST_P_UART5 222 675 #define SRST_P_UART6 223 676 /********Name=SOFTRST_CON14,Offset=0xA38********/ 677 #define SRST_P_UART7 224 678 #define SRST_P_UART8 225 679 #define SRST_P_UART9 226 680 #define SRST_P_UART10 227 681 #define SRST_P_UART11 228 682 #define SRST_S_UART0 229 683 #define SRST_S_UART2 230 684 #define SRST_S_UART3 233 685 #define SRST_S_UART4 236 686 #define SRST_S_UART5 239 687 /********Name=SOFTRST_CON15,Offset=0xA3C********/ 688 #define SRST_S_UART6 242 689 #define SRST_S_UART7 245 690 #define SRST_S_UART8 248 691 #define SRST_S_UART9 249 692 #define SRST_S_UART10 250 693 #define SRST_S_UART11 251 694 #define SRST_P_SPI0 253 695 #define SRST_P_SPI1 254 696 #define SRST_P_SPI2 255 697 /********Name=SOFTRST_CON16,Offset=0xA40********/ 698 #define SRST_P_SPI3 256 699 #define SRST_P_SPI4 257 700 #define SRST_SPI0 258 701 #define SRST_SPI1 259 702 #define SRST_SPI2 260 703 #define SRST_SPI3 261 704 #define SRST_SPI4 262 705 #define SRST_P_WDT0 263 706 #define SRST_T_WDT0 264 707 #define SRST_P_SYS_GRF 265 708 #define SRST_P_PWM1 266 709 #define SRST_PWM1 267 710 711 /********Name=SOFTRST_CON17,Offset=0xA44********/ 712 #define SRST_P_BUSTIMER0 275 713 #define SRST_P_BUSTIMER1 276 714 #define SRST_TIMER0 278 715 #define SRST_TIMER1 279 716 #define SRST_TIMER2 280 717 #define SRST_TIMER3 281 718 #define SRST_TIMER4 282 719 #define SRST_TIMER5 283 720 #define SRST_P_BUSIOC 284 721 #define SRST_P_MAILBOX0 285 722 #define SRST_P_GPIO1 287 723 /********Name=SOFTRST_CON18,Offset=0xA48********/ 724 #define SRST_GPIO1 288 725 #define SRST_P_GPIO2 289 726 #define SRST_GPIO2 290 727 #define SRST_P_GPIO3 291 728 #define SRST_GPIO3 292 729 #define SRST_P_GPIO4 293 730 #define SRST_GPIO4 294 731 #define SRST_A_DECOM 295 732 #define SRST_P_DECOM 296 733 #define SRST_D_DECOM 297 734 #define SRST_TIMER6 299 735 #define SRST_TIMER7 300 736 #define SRST_TIMER8 301 737 #define SRST_TIMER9 302 738 #define SRST_TIMER10 303 739 /********Name=SOFTRST_CON19,Offset=0xA4C********/ 740 #define SRST_TIMER11 304 741 #define SRST_A_DMAC0 305 742 #define SRST_A_DMAC1 306 743 #define SRST_A_DMAC2 307 744 #define SRST_A_SPINLOCK 308 745 #define SRST_REF_PVTPLL_BUS 309 746 #define SRST_H_I3C0 311 747 #define SRST_H_I3C1 313 748 #define SRST_H_BUS_CM0_BIU 315 749 #define SRST_F_BUS_CM0_CORE 316 750 #define SRST_T_BUS_CM0_JTAG 317 751 /********Name=SOFTRST_CON20,Offset=0xA50********/ 752 #define SRST_P_INTMUX2PMU 320 753 #define SRST_P_INTMUX2DDR 321 754 #define SRST_P_PVTPLL_BUS 323 755 #define SRST_P_PWM2 324 756 #define SRST_PWM2 325 757 #define SRST_FREQ_PWM1 328 758 #define SRST_COUNTER_PWM1 329 759 #define SRST_I3C0 332 760 #define SRST_I3C1 333 761 /********Name=SOFTRST_CON21,Offset=0xA54********/ 762 #define SRST_P_DDR_MON_CH0 337 763 #define SRST_P_DDR_BIU 338 764 #define SRST_P_DDR_UPCTL_CH0 339 765 #define SRST_TM_DDR_MON_CH0 340 766 #define SRST_A_DDR_BIU 341 767 #define SRST_DFI_CH0 342 768 #define SRST_DDR_MON_CH0 346 769 #define SRST_P_DDR_HWLP_CH0 349 770 #define SRST_P_DDR_MON_CH1 350 771 #define SRST_P_DDR_HWLP_CH1 351 772 /********Name=SOFTRST_CON22,Offset=0xA58********/ 773 #define SRST_P_DDR_UPCTL_CH1 352 774 #define SRST_TM_DDR_MON_CH1 353 775 #define SRST_DFI_CH1 354 776 #define SRST_A_DDR01_MSCH0 355 777 #define SRST_A_DDR01_MSCH1 356 778 #define SRST_DDR_MON_CH1 358 779 #define SRST_DDR_SCRAMBLE_CH0 361 780 #define SRST_DDR_SCRAMBLE_CH1 362 781 #define SRST_P_AHB2APB 364 782 #define SRST_H_AHB2APB 365 783 #define SRST_H_DDR_BIU 366 784 #define SRST_F_DDR_CM0_CORE 367 785 /********Name=SOFTRST_CON23,Offset=0xA5C********/ 786 #define SRST_P_DDR01_MSCH0 369 787 #define SRST_P_DDR01_MSCH1 370 788 #define SRST_DDR_TIMER0 372 789 #define SRST_DDR_TIMER1 373 790 #define SRST_T_WDT_DDR 374 791 #define SRST_P_WDT 375 792 #define SRST_P_TIMER 376 793 #define SRST_T_DDR_CM0_JTAG 377 794 #define SRST_P_DDR_GRF 379 795 /********Name=SOFTRST_CON25,Offset=0xA64********/ 796 #define SRST_DDR_UPCTL_CH0 401 797 #define SRST_A_DDR_UPCTL_0_CH0 402 798 #define SRST_A_DDR_UPCTL_1_CH0 403 799 #define SRST_A_DDR_UPCTL_2_CH0 404 800 #define SRST_A_DDR_UPCTL_3_CH0 405 801 #define SRST_A_DDR_UPCTL_4_CH0 406 802 /********Name=SOFTRST_CON26,Offset=0xA68********/ 803 #define SRST_DDR_UPCTL_CH1 417 804 #define SRST_A_DDR_UPCTL_0_CH1 418 805 #define SRST_A_DDR_UPCTL_1_CH1 419 806 #define SRST_A_DDR_UPCTL_2_CH1 420 807 #define SRST_A_DDR_UPCTL_3_CH1 421 808 #define SRST_A_DDR_UPCTL_4_CH1 422 809 /********Name=SOFTRST_CON27,Offset=0xA6C********/ 810 #define SRST_REF_PVTPLL_DDR 432 811 #define SRST_P_PVTPLL_DDR 433 812 813 /********Name=SOFTRST_CON28,Offset=0xA70********/ 814 #define SRST_A_RKNN0 457 815 #define SRST_A_RKNN0_BIU 459 816 #define SRST_L_RKNN0_BIU 460 817 /********Name=SOFTRST_CON29,Offset=0xA74********/ 818 #define SRST_A_RKNN1 464 819 #define SRST_A_RKNN1_BIU 466 820 #define SRST_L_RKNN1_BIU 467 821 /********Name=SOFTRST_CON31,Offset=0xA7C********/ 822 #define SRST_NPU_DAP 496 823 #define SRST_L_NPUSUBSYS_BIU 497 824 #define SRST_P_NPUTOP_BIU 505 825 #define SRST_P_NPU_TIMER 506 826 #define SRST_NPUTIMER0 508 827 #define SRST_NPUTIMER1 509 828 #define SRST_P_NPU_WDT 510 829 #define SRST_T_NPU_WDT 511 830 /********Name=SOFTRST_CON32,Offset=0xA80********/ 831 #define SRST_A_RKNN_CBUF 512 832 #define SRST_A_RVCORE0 513 833 #define SRST_P_NPU_GRF 514 834 #define SRST_P_PVTPLL_NPU 515 835 #define SRST_NPU_PVTPLL 516 836 #define SRST_H_NPU_CM0_BIU 518 837 #define SRST_F_NPU_CM0_CORE 519 838 #define SRST_T_NPU_CM0_JTAG 520 839 #define SRST_A_RKNNTOP_BIU 523 840 #define SRST_H_RKNN_CBUF 524 841 #define SRST_H_RKNNTOP_BIU 525 842 /********Name=SOFTRST_CON33,Offset=0xA84********/ 843 #define SRST_H_NVM_BIU 530 844 #define SRST_A_NVM_BIU 531 845 #define SRST_S_FSPI 534 846 #define SRST_H_FSPI 535 847 #define SRST_C_EMMC 536 848 #define SRST_H_EMMC 537 849 #define SRST_A_EMMC 538 850 #define SRST_B_EMMC 539 851 #define SRST_T_EMMC 540 852 /********Name=SOFTRST_CON34,Offset=0xA88********/ 853 #define SRST_P_GRF 545 854 #define SRST_P_PHP_BIU 549 855 #define SRST_A_PHP_BIU 553 856 #define SRST_P_PCIE0 557 857 #define SRST_PCIE0_POWER_UP 559 858 /********Name=SOFTRST_CON35,Offset=0xA8C********/ 859 #define SRST_A_USB3OTG1 563 860 #define SRST_A_MMU0 571 861 #define SRST_A_SLV_MMU0 573 862 #define SRST_A_MMU1 574 863 /********Name=SOFTRST_CON36,Offset=0xA90********/ 864 #define SRST_A_SLV_MMU1 576 865 #define SRST_P_PCIE1 583 866 #define SRST_PCIE1_POWER_UP 585 867 /********Name=SOFTRST_CON37,Offset=0xA94********/ 868 #define SRST_RXOOB0 592 869 #define SRST_RXOOB1 593 870 #define SRST_PMALIVE0 594 871 #define SRST_PMALIVE1 595 872 #define SRST_A_SATA0 596 873 #define SRST_A_SATA1 597 874 #define SRST_ASIC1 598 875 #define SRST_ASIC0 599 876 /********Name=SOFTRST_CON40,Offset=0xAA0********/ 877 #define SRST_P_CSIDPHY1 642 878 #define SRST_SCAN_CSIDPHY1 643 879 /********Name=SOFTRST_CON42,Offset=0xAA8********/ 880 #define SRST_P_SDGMAC_GRF 675 881 #define SRST_P_SDGMAC_BIU 676 882 #define SRST_A_SDGMAC_BIU 677 883 #define SRST_H_SDGMAC_BIU 678 884 #define SRST_A_GMAC0 679 885 #define SRST_A_GMAC1 680 886 #define SRST_P_GMAC0 681 887 #define SRST_P_GMAC1 682 888 #define SRST_H_SDIO 684 889 /********Name=SOFTRST_CON43,Offset=0xAAC********/ 890 #define SRST_H_SDMMC0 690 891 #define SRST_S_FSPI1 691 892 #define SRST_H_FSPI1 692 893 #define SRST_A_DSMC_BIU 694 894 #define SRST_A_DSMC 695 895 #define SRST_P_DSMC 696 896 #define SRST_H_HSGPIO 698 897 #define SRST_HSGPIO 699 898 #define SRST_A_HSGPIO 701 899 /********Name=SOFTRST_CON45,Offset=0xAB4********/ 900 #define SRST_H_RKVDEC 723 901 #define SRST_H_RKVDEC_BIU 725 902 #define SRST_A_RKVDEC_BIU 726 903 #define SRST_RKVDEC_HEVC_CA 728 904 #define SRST_RKVDEC_CORE 729 905 /********Name=SOFTRST_CON47,Offset=0xABC********/ 906 #define SRST_A_USB_BIU 755 907 #define SRST_P_USBUFS_BIU 756 908 #define SRST_A_USB3OTG0 757 909 #define SRST_A_UFS_BIU 762 910 #define SRST_A_MMU2 764 911 #define SRST_A_SLV_MMU2 765 912 #define SRST_A_UFS_SYS 767 913 /********Name=SOFTRST_CON48,Offset=0xAC0********/ 914 #define SRST_A_UFS 768 915 #define SRST_P_USBUFS_GRF 769 916 #define SRST_P_UFS_GRF 770 917 /********Name=SOFTRST_CON49,Offset=0xAC4********/ 918 #define SRST_H_VPU_BIU 790 919 #define SRST_A_JPEG_BIU 791 920 #define SRST_A_RGA_BIU 794 921 #define SRST_A_VDPP_BIU 795 922 #define SRST_A_EBC_BIU 796 923 #define SRST_H_RGA2E_0 797 924 #define SRST_A_RGA2E_0 798 925 #define SRST_CORE_RGA2E_0 799 926 /********Name=SOFTRST_CON50,Offset=0xAC8********/ 927 #define SRST_A_JPEG 800 928 #define SRST_H_JPEG 801 929 #define SRST_H_VDPP 802 930 #define SRST_A_VDPP 803 931 #define SRST_CORE_VDPP 804 932 #define SRST_H_RGA2E_1 805 933 #define SRST_A_RGA2E_1 806 934 #define SRST_CORE_RGA2E_1 807 935 #define SRST_H_EBC 810 936 #define SRST_A_EBC 811 937 #define SRST_D_EBC 812 938 /********Name=SOFTRST_CON51,Offset=0xACC********/ 939 #define SRST_H_VEPU0_BIU 818 940 #define SRST_A_VEPU0_BIU 819 941 #define SRST_H_VEPU0 820 942 #define SRST_A_VEPU0 821 943 #define SRST_VEPU0_CORE 822 944 /********Name=SOFTRST_CON53,Offset=0xAD4********/ 945 #define SRST_A_VI_BIU 851 946 #define SRST_H_VI_BIU 852 947 #define SRST_P_VI_BIU 853 948 #define SRST_D_VICAP 854 949 #define SRST_A_VICAP 855 950 #define SRST_H_VICAP 856 951 #define SRST_ISP0 858 952 #define SRST_ISP0_VICAP 859 953 /********Name=SOFTRST_CON54,Offset=0xAD8********/ 954 #define SRST_CORE_VPSS 865 955 #define SRST_P_CSI_HOST_0 868 956 #define SRST_P_CSI_HOST_1 869 957 #define SRST_P_CSI_HOST_2 870 958 #define SRST_P_CSI_HOST_3 871 959 #define SRST_P_CSI_HOST_4 872 960 /********Name=SOFTRST_CON59,Offset=0xAEC********/ 961 #define SRST_CIFIN 944 962 #define SRST_VICAP_I0CLK 945 963 #define SRST_VICAP_I1CLK 946 964 #define SRST_VICAP_I2CLK 947 965 #define SRST_VICAP_I3CLK 948 966 #define SRST_VICAP_I4CLK 949 967 /********Name=SOFTRST_CON61,Offset=0xAF4********/ 968 #define SRST_A_VOP_BIU 980 969 #define SRST_A_VOP2_BIU 981 970 #define SRST_H_VOP_BIU 982 971 #define SRST_P_VOP_BIU 983 972 #define SRST_H_VOP 984 973 #define SRST_A_VOP 985 974 #define SRST_D_VP0 989 975 /********Name=SOFTRST_CON62,Offset=0xAF8********/ 976 #define SRST_D_VP1 992 977 #define SRST_D_VP2 993 978 #define SRST_P_VOP2_BIU 994 979 #define SRST_P_VOPGRF 995 980 /********Name=SOFTRST_CON63,Offset=0xAFC********/ 981 #define SRST_H_VO0_BIU 1013 982 #define SRST_P_VO0_BIU 1015 983 #define SRST_A_HDCP0_BIU 1017 984 #define SRST_P_VO0_GRF 1018 985 #define SRST_A_HDCP0 1020 986 #define SRST_H_HDCP0 1021 987 #define SRST_HDCP0 1022 988 /********Name=SOFTRST_CON64,Offset=0xB00********/ 989 #define SRST_P_DSIHOST0 1029 990 #define SRST_DSIHOST0 1030 991 #define SRST_P_HDMITX0 1031 992 #define SRST_HDMITX0_REF 1033 993 #define SRST_P_EDP0 1037 994 #define SRST_EDP0_24M 1038 995 /********Name=SOFTRST_CON65,Offset=0xB04********/ 996 #define SRST_M_SAI5_8CH 1044 997 #define SRST_H_SAI5_8CH 1045 998 #define SRST_M_SAI6_8CH 1048 999 #define SRST_H_SAI6_8CH 1049 1000 #define SRST_H_SPDIF_TX2 1050 1001 #define SRST_M_SPDIF_TX2 1053 1002 #define SRST_H_SPDIF_RX2 1054 1003 #define SRST_M_SPDIF_RX2 1055 1004 /********Name=SOFTRST_CON66,Offset=0xB08********/ 1005 #define SRST_H_SAI8_8CH 1056 1006 #define SRST_M_SAI8_8CH 1058 1007 /********Name=SOFTRST_CON67,Offset=0xB0C********/ 1008 #define SRST_H_VO1_BIU 1077 1009 #define SRST_P_VO1_BIU 1078 1010 #define SRST_M_SAI7_8CH 1081 1011 #define SRST_H_SAI7_8CH 1082 1012 #define SRST_H_SPDIF_TX3 1083 1013 #define SRST_H_SPDIF_TX4 1084 1014 #define SRST_H_SPDIF_TX5 1085 1015 #define SRST_M_SPDIF_TX3 1086 1016 /********Name=SOFTRST_CON68,Offset=0xB10********/ 1017 #define SRST_DP0 1088 1018 #define SRST_P_VO1_GRF 1090 1019 #define SRST_A_HDCP1_BIU 1091 1020 #define SRST_A_HDCP1 1092 1021 #define SRST_H_HDCP1 1093 1022 #define SRST_HDCP1 1094 1023 #define SRST_H_SAI9_8CH 1097 1024 #define SRST_M_SAI9_8CH 1099 1025 #define SRST_M_SPDIF_TX4 1100 1026 #define SRST_M_SPDIF_TX5 1101 1027 /********Name=SOFTRST_CON69,Offset=0xB14********/ 1028 #define SRST_GPU 1107 1029 #define SRST_A_S_GPU_BIU 1110 1030 #define SRST_A_M0_GPU_BIU 1111 1031 #define SRST_P_GPU_BIU 1113 1032 #define SRST_P_GPU_GRF 1117 1033 #define SRST_GPU_PVTPLL 1118 1034 #define SRST_P_PVTPLL_GPU 1119 1035 /********Name=SOFTRST_CON72,Offset=0xB20********/ 1036 #define SRST_A_CENTER_BIU 1156 1037 #define SRST_A_DMA2DDR 1157 1038 #define SRST_A_DDR_SHAREMEM 1158 1039 #define SRST_A_DDR_SHAREMEM_BIU 1159 1040 #define SRST_H_CENTER_BIU 1160 1041 #define SRST_P_CENTER_GRF 1161 1042 #define SRST_P_DMA2DDR 1162 1043 #define SRST_P_SHAREMEM 1163 1044 #define SRST_P_CENTER_BIU 1164 1045 /********Name=SOFTRST_CON75,Offset=0xB2C********/ 1046 #define SRST_LINKSYM_HDMITXPHY0 1201 1047 /********Name=SOFTRST_CON78,Offset=0xB38********/ 1048 #define SRST_DP0_PIXELCLK 1249 1049 #define SRST_PHY_DP0_TX 1250 1050 #define SRST_DP1_PIXELCLK 1251 1051 #define SRST_DP2_PIXELCLK 1252 1052 /********Name=SOFTRST_CON79,Offset=0xB3C********/ 1053 #define SRST_H_VEPU1_BIU 1265 1054 #define SRST_A_VEPU1_BIU 1266 1055 #define SRST_H_VEPU1 1267 1056 #define SRST_A_VEPU1 1268 1057 #define SRST_VEPU1_CORE 1269 1058 1059 /********Name=PHPPHYSOFTRST_CON00,Offset=0x8A00********/ 1060 #define SRST_P_PHPPHY_CRU 131073 1061 #define SRST_P_APB2ASB_SLV_CHIP_TOP 131075 1062 #define SRST_P_PCIE2_COMBOPHY0 131077 1063 #define SRST_P_PCIE2_COMBOPHY0_GRF 131078 1064 #define SRST_P_PCIE2_COMBOPHY1 131079 1065 #define SRST_P_PCIE2_COMBOPHY1_GRF 131080 1066 /********Name=PHPPHYSOFTRST_CON01,Offset=0x8A04********/ 1067 #define SRST_PCIE0_PIPE_PHY 131093 1068 #define SRST_PCIE1_PIPE_PHY 131096 1069 1070 /********Name=SECURENSSOFTRST_CON00,Offset=0x10A00********/ 1071 #define SRST_H_CRYPTO_NS 262147 1072 #define SRST_H_TRNG_NS 262148 1073 #define SRST_P_OTPC_NS 262152 1074 #define SRST_OTPC_NS 262153 1075 1076 /********Name=PMU1SOFTRST_CON00,Offset=0x20A00********/ 1077 #define SRST_P_HDPTX_GRF 524288 1078 #define SRST_P_HDPTX_APB 524289 1079 #define SRST_P_MIPI_DCPHY 524290 1080 #define SRST_P_DCPHY_GRF 524291 1081 #define SRST_P_BOT0_APB2ASB 524292 1082 #define SRST_P_BOT1_APB2ASB 524293 1083 #define SRST_USB2DEBUG 524294 1084 #define SRST_P_CSIPHY_GRF 524295 1085 #define SRST_P_CSIPHY 524296 1086 #define SRST_P_USBPHY_GRF_0 524297 1087 #define SRST_P_USBPHY_GRF_1 524298 1088 #define SRST_P_USBDP_GRF 524299 1089 #define SRST_P_USBDPPHY 524300 1090 #define SRST_USBDP_COMBO_PHY_INIT 524303 1091 /********Name=PMU1SOFTRST_CON01,Offset=0x20A04********/ 1092 #define SRST_USBDP_COMBO_PHY_CMN 524304 1093 #define SRST_USBDP_COMBO_PHY_LANE 524305 1094 #define SRST_USBDP_COMBO_PHY_PCS 524306 1095 #define SRST_M_MIPI_DCPHY 524307 1096 #define SRST_S_MIPI_DCPHY 524308 1097 #define SRST_SCAN_CSIPHY 524309 1098 #define SRST_P_VCCIO6_IOC 524310 1099 #define SRST_OTGPHY_0 524311 1100 #define SRST_OTGPHY_1 524312 1101 #define SRST_HDPTX_INIT 524313 1102 #define SRST_HDPTX_CMN 524314 1103 #define SRST_HDPTX_LANE 524315 1104 #define SRST_HDMITXHPD 524317 1105 /********Name=PMU1SOFTRST_CON02,Offset=0x20A08********/ 1106 #define SRST_MPHY_INIT 524320 1107 #define SRST_P_MPHY_GRF 524321 1108 #define SRST_P_VCCIO7_IOC 524323 1109 /********Name=PMU1SOFTRST_CON03,Offset=0x20A0C********/ 1110 #define SRST_H_PMU1_BIU 524345 1111 #define SRST_P_PMU1_NIU 524346 1112 #define SRST_H_PMU_CM0_BIU 524347 1113 #define SRST_PMU_CM0_CORE 524348 1114 #define SRST_PMU_CM0_JTAG 524349 1115 /********Name=PMU1SOFTRST_CON04,Offset=0x20A10********/ 1116 #define SRST_P_CRU_PMU1 524353 1117 #define SRST_P_PMU1_GRF 524355 1118 #define SRST_P_PMU1_IOC 524356 1119 #define SRST_P_PMU1WDT 524357 1120 #define SRST_T_PMU1WDT 524358 1121 #define SRST_P_PMUTIMER 524359 1122 #define SRST_PMUTIMER0 524361 1123 #define SRST_PMUTIMER1 524362 1124 #define SRST_P_PMU1PWM 524363 1125 #define SRST_PMU1PWM 524364 1126 /********Name=PMU1SOFTRST_CON05,Offset=0x20A14********/ 1127 #define SRST_P_I2C0 524369 1128 #define SRST_I2C0 524371 1129 #define SRST_S_UART1 525373 1130 #define SRST_P_UART1 525374 1131 #define SRST_PDM0 524381 1132 #define SRST_H_PDM0 524383 1133 /********Name=PMU1SOFTRST_CON06,Offset=0xA18********/ 1134 #define SRST_M_PDM0 524384 1135 #define SRST_H_VAD 524385 1136 /********Name=PMU1SOFTRST_CON07,Offset=0x20A1C********/ 1137 #define SRST_P_PMU0GRF 524404 1138 #define SRST_P_PMU0IOC 524405 1139 #define SRST_P_GPIO0 524406 1140 #define SRST_DB_GPIO0 524407 1141 1142 #define SRST_NR_RSTS (SRST_DB_GPIO0 + 1) 1143 #endif 1144