1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2022 Rockchip Electronics Co. Ltd. 4 * Author: 5 * Elaine Zhang <zhangqing@rock-chips.com> 6 * Finley Xiao <finley.xiao@rock-chips.com> 7 */ 8 9 #ifndef _ASM_ARCH_CRU_RK3562_H 10 #define _ASM_ARCH_CRU_RK3562_H 11 12 #define MHz 1000000 13 #define KHz 1000 14 #define OSC_HZ (24 * MHz) 15 16 #define CPU_PVTPLL_HZ (1008 * MHz) 17 #define APLL_HZ (600 * MHz) 18 #define GPLL_HZ (1188 * MHz) 19 #define CPLL_HZ (1000 * MHz) 20 #define HPLL_HZ (1000 * MHz) 21 22 /* RK3562 pll id */ 23 enum rk3562_pll_id { 24 APLL, 25 GPLL, 26 VPLL, 27 HPLL, 28 CPLL, 29 DPLL, 30 PLL_COUNT, 31 }; 32 33 struct rk3562_clk_info { 34 unsigned long id; 35 char *name; 36 }; 37 38 struct rk3562_clk_priv { 39 struct rk3562_cru *cru; 40 ulong gpll_hz; 41 ulong vpll_hz; 42 ulong hpll_hz; 43 ulong cpll_hz; 44 ulong armclk_hz; 45 ulong armclk_enter_hz; 46 ulong armclk_init_hz; 47 bool sync_kernel; 48 bool set_armclk_rate; 49 }; 50 51 struct rk3562_cru { 52 /* top cru */ 53 uint32_t apll_con[5]; 54 uint32_t reserved0014[19]; 55 uint32_t gpll_con[5]; 56 uint32_t reserved0074[3]; 57 uint32_t vpll_con[5]; 58 uint32_t reserved0094[3]; 59 uint32_t hpll_con[5]; 60 uint32_t reserved00b4[19]; 61 uint32_t clksel_con[48]; 62 uint32_t reserved01c0[80]; 63 uint32_t gate_con[28]; 64 uint32_t reserved370[36]; 65 uint32_t softrst_con[28]; 66 uint32_t reserved0470[100]; 67 uint32_t mode_con[1]; 68 uint32_t reserved0604[3]; 69 uint32_t glb_cnt_th; 70 uint32_t glb_srst_fst; 71 uint32_t glb_srst_snd; 72 uint32_t glb_rst_con; 73 uint32_t glb_rst_st; 74 unsigned int sdmmc0_con[2]; 75 unsigned int sdmmc1_con[2]; 76 uint32_t reserved0634[2]; 77 unsigned int emmc_con[1]; 78 uint32_t reserved0640[15984]; 79 80 /* pmu0 cru */ 81 uint32_t reserved10000[64]; 82 uint32_t pmu0clksel_con[4]; 83 uint32_t reserved10110[28]; 84 uint32_t pmu0gate_con[3]; 85 uint32_t reserved1018c[29]; 86 uint32_t pmu0softrst_con[3]; 87 uint32_t reserved1020c[8061]; 88 89 /* pmu1 cru */ 90 uint32_t reserved18000[16]; 91 uint32_t cpll_con[5]; 92 uint32_t reserved18054[43]; 93 uint32_t pmu1clksel_con[7]; 94 uint32_t reserved1811c[25]; 95 uint32_t pmu1gate_con[4]; 96 uint32_t reserved18190[28]; 97 uint32_t pmu1softrst_con[3]; 98 uint32_t reserved1820c[93]; 99 uint32_t pmu1mode_con[1]; 100 uint32_t reserved18384[7967]; 101 102 /* ddr cru */ 103 uint32_t reserved20000[64]; 104 uint32_t ddrclksel_con[2]; 105 uint32_t reserved20108[30]; 106 uint32_t ddrgate_con[2]; 107 uint32_t reserved20188[30]; 108 uint32_t ddrsoftrst_con[2]; 109 uint32_t reserved20208[8062]; 110 111 /* subddr cru */ 112 uint32_t reserved28000[8]; 113 uint32_t dpll_con[5]; 114 uint32_t reserved28034[51]; 115 uint32_t sudbddrclksel_con[1]; 116 uint32_t reserved28104[31]; 117 uint32_t subddrgate_con[1]; 118 uint32_t reserved28184[31]; 119 uint32_t sudbddrsoftrst_con[1]; 120 uint32_t reserved28204[95]; 121 uint32_t subddrmode_con[1]; 122 uint32_t reserved28384[7967]; 123 124 /* peri cru */ 125 uint32_t reserved30000[64]; 126 uint32_t periclksel_con[48]; 127 uint32_t reserved301c0[80]; 128 uint32_t perigate_con[18]; 129 uint32_t reserved30348[46]; 130 uint32_t perisoftrst_con[18]; 131 uint32_t reserved30448[143]; 132 }; 133 check_member(rk3562_cru, reserved0640[0], 0x00640); 134 check_member(rk3562_cru, reserved1020c[0], 0x1020c); 135 check_member(rk3562_cru, reserved18384[0], 0x18384); 136 check_member(rk3562_cru, reserved20208[0], 0x20208); 137 check_member(rk3562_cru, reserved28384[0], 0x28384); 138 check_member(rk3562_cru, reserved30448[0], 0x30448); 139 140 struct pll_rate_table { 141 unsigned long rate; 142 unsigned int fbdiv; 143 unsigned int postdiv1; 144 unsigned int refdiv; 145 unsigned int postdiv2; 146 unsigned int dsmpd; 147 unsigned int frac; 148 }; 149 150 #define RK3562_PMU0_CRU_BASE 0x10000 151 #define RK3562_PMU1_CRU_BASE 0x18000 152 #define RK3562_DDR_CRU_BASE 0x20000 153 #define RK3562_SUBDDR_CRU_BASE 0x28000 154 #define RK3562_PERI_CRU_BASE 0x30000 155 156 #define RK3562_PLL_CON(x) ((x) * 0x4) 157 #define RK3562_PMU1_PLL_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x40) 158 #define RK3562_SUBDDR_PLL_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x20) 159 #define RK3562_MODE_CON 0x600 160 #define RK3562_PMU1_MODE_CON (RK3562_PMU1_CRU_BASE + 0x380) 161 #define RK3562_SUBDDR_MODE_CON (RK3562_SUBDDR_CRU_BASE + 0x380) 162 #define RK3562_GLB_SRST_FST 0x614 163 #define RK3562_GLB_SRST_SND 0x618 164 #define RK3562_GLB_RST_CON 0x61c 165 #define RK3562_GLB_RST_ST 0x620 166 167 enum { 168 /* CRU_CLKSEL_CON10 */ 169 CLK_CORE_PRE_DIV_SHIFT = 0, 170 CLK_CORE_PRE_DIV_MASK = 0x1f << CLK_CORE_PRE_DIV_SHIFT, 171 172 /* CRU_CLKSEL_CON11 */ 173 ACLK_CORE_PRE_DIV_SHIFT = 0, 174 ACLK_CORE_PRE_DIV_MASK = 0x7 << ACLK_CORE_PRE_DIV_SHIFT, 175 CLK_SCANHS_ACLKM_CORE_DIV_SHIFT = 8, 176 CLK_SCANHS_ACLKM_CORE_DIV_MASK = 0x7 << CLK_SCANHS_ACLKM_CORE_DIV_SHIFT, 177 178 /* CRU_CLKSEL_CON12 */ 179 PCLK_DBG_PRE_DIV_SHIFT = 0, 180 PCLK_DBG_PRE_DIV_MASK = 0xf << PCLK_DBG_PRE_DIV_SHIFT, 181 CLK_SCANHS_PCLK_DBG_DIV_SHIFT = 8, 182 CLK_SCANHS_PCLK_DBG_DIV_MASK = 0xf << CLK_SCANHS_PCLK_DBG_DIV_SHIFT, 183 184 /* CRU_CLKSEL_CON28 */ 185 ACLK_VOP_DIV_SHIFT = 0, 186 ACLK_VOP_DIV_MASK = 0x1f << ACLK_VOP_DIV_SHIFT, 187 ACLK_VOP_SEL_SHIFT = 6, 188 ACLK_VOP_SEL_MASK = 0x3 << ACLK_VOP_SEL_SHIFT, 189 ACLK_VOP_SEL_GPLL = 0, 190 ACLK_VOP_SEL_CPLL, 191 ACLK_VOP_SEL_VPLL, 192 ACLK_VOP_SEL_HPLL, 193 194 /* CRU_CLKSEL_CON30 */ 195 DCLK_VOP_DIV_SHIFT = 0, 196 DCLK_VOP_DIV_MASK = 0xff << DCLK_VOP_DIV_SHIFT, 197 DCLK_VOP_SEL_SHIFT = 14, 198 DCLK_VOP_SEL_MASK = 0x3 << DCLK_VOP_SEL_SHIFT, 199 DCLK_VOP_SEL_GPLL = 0, 200 DCLK_VOP_SEL_HPLL, 201 DCLK_VOP_SEL_VPLL, 202 DCLK_VOP_SEL_APLL, 203 204 /* CRU_CLKSEL_CON31 */ 205 DCLK_VOP1_DIV_SHIFT = 0, 206 DCLK_VOP1_DIV_MASK = 0xff << DCLK_VOP1_DIV_SHIFT, 207 DCLK_VOP1_SEL_SHIFT = 14, 208 DCLK_VOP1_SEL_MASK = 0x3 << DCLK_VOP1_SEL_SHIFT, 209 210 /* CRU_CLKSEL_CON40 */ 211 ACLK_BUS_DIV_SHIFT = 0, 212 ACLK_BUS_DIV_MASK = 0x1f << ACLK_BUS_DIV_SHIFT, 213 ACLK_BUS_SEL_SHIFT = 7, 214 ACLK_BUS_SEL_MASK = 0x1 << ACLK_BUS_SEL_SHIFT, 215 ACLK_BUS_SEL_GPLL = 0, 216 ACLK_BUS_SEL_CPLL, 217 HCLK_BUS_DIV_SHIFT = 8, 218 HCLK_BUS_DIV_MASK = 0x3f << HCLK_BUS_DIV_SHIFT, 219 HCLK_BUS_SEL_SHIFT = 15, 220 HCLK_BUS_SEL_MASK = 0x1 << HCLK_BUS_SEL_SHIFT, 221 222 /* CRU_CLKSEL_CON41 */ 223 PCLK_BUS_DIV_SHIFT = 0, 224 PCLK_BUS_DIV_MASK = 0x1f << PCLK_BUS_DIV_SHIFT, 225 PCLK_BUS_SEL_SHIFT = 7, 226 PCLK_BUS_SEL_MASK = 0x1 << PCLK_BUS_SEL_SHIFT, 227 CLK_I2C_SEL_SHIFT = 8, 228 CLK_I2C_SEL_MASK = 0x3 << CLK_I2C_SEL_SHIFT, 229 CLK_I2C_SEL_200M = 0, 230 CLK_I2C_SEL_100M, 231 CLK_I2C_SEL_50M, 232 CLK_I2C_SEL_24M, 233 DCLK_BUS_GPIO_SEL_SHIFT = 15, 234 DCLK_BUS_GPIO_SEL_MASK = 0x1 << DCLK_BUS_GPIO_SEL_SHIFT, 235 236 /* CRU_CLKSEL_CON43 */ 237 CLK_TSADC_DIV_SHIFT = 0, 238 CLK_TSADC_DIV_MASK = 0x7ff << CLK_TSADC_DIV_SHIFT, 239 CLK_TSADC_TSEN_DIV_SHIFT = 11, 240 CLK_TSADC_TSEN_DIV_MASK = 0x1f << CLK_TSADC_TSEN_DIV_SHIFT, 241 242 /* CRU_CLKSEL_CON44 */ 243 CLK_SARADC_VCCIO156_DIV_SHIFT = 0, 244 CLK_SARADC_VCCIO156_DIV_MASK = 0xfff << CLK_SARADC_VCCIO156_DIV_SHIFT, 245 246 /* CRU_CLKSEL_CON45 */ 247 CLK_GMAC_125M_SEL_SHIFT = 8, 248 CLK_GMAC_125M_SEL_MASK = 0x1 << CLK_GMAC_125M_SEL_SHIFT, 249 CLK_GMAC_125M = 0, 250 CLK_GMAC_24M, 251 CLK_GMAC_50M_SEL_SHIFT = 7, 252 CLK_GMAC_50M_SEL_MASK = 0x1 << CLK_GMAC_50M_SEL_SHIFT, 253 CLK_GMAC_50M = 0, 254 255 /* CRU_CLKSEL_CON46 */ 256 CLK_GMAC_ETH_OUT2IO_SEL_SHIFT = 7, 257 CLK_GMAC_ETH_OUT2IO_SEL_MASK = 0x1 << CLK_GMAC_ETH_OUT2IO_SEL_SHIFT, 258 CLK_GMAC_ETH_OUT2IO_GPLL = 0, 259 CLK_GMAC_ETH_OUT2IO_CPLL, 260 CLK_GMAC_ETH_OUT2IO_DIV_SHIFT = 0, 261 CLK_GMAC_ETH_OUT2IO_DIV_MASK = 0x7f, 262 263 /* PMU0CRU_CLKSEL_CON03 */ 264 CLK_PMU0_I2C0_DIV_SHIFT = 8, 265 CLK_PMU0_I2C0_DIV_MASK = 0x1f << CLK_PMU0_I2C0_DIV_SHIFT, 266 CLK_PMU0_I2C0_SEL_SHIFT = 14, 267 CLK_PMU0_I2C0_SEL_MASK = 0x3 << CLK_PMU0_I2C0_SEL_SHIFT, 268 CLK_PMU0_I2C0_SEL_200M = 0, 269 CLK_PMU0_I2C0_SEL_24M, 270 CLK_PMU0_I2C0_SEL_32K, 271 272 /* PMU1CRU_CLKSEL_CON02 */ 273 CLK_PMU1_UART0_SRC_DIV_SHIFT = 0, 274 CLK_PMU1_UART0_SRC_DIV_MASK = 0xf << CLK_PMU1_UART0_SRC_DIV_SHIFT, 275 CLK_PMU1_UART0_SEL_SHIFT = 6, 276 CLK_PMU1_UART0_SEL_MASK = 0x3 << CLK_PMU1_UART0_SEL_SHIFT, 277 278 /* PMU1CRU_CLKSEL_CON04 */ 279 CLK_PMU1_SPI0_DIV_SHIFT = 0, 280 CLK_PMU1_SPI0_DIV_MASK = 0x3 << CLK_PMU1_SPI0_DIV_SHIFT, 281 CLK_PMU1_SPI0_SEL_SHIFT = 6, 282 CLK_PMU1_SPI0_SEL_MASK = 0x3 << CLK_PMU1_SPI0_SEL_SHIFT, 283 CLK_PMU1_SPI0_SEL_200M = 0, 284 CLK_PMU1_SPI0_SEL_24M, 285 CLK_PMU1_SPI0_SEL_32K, 286 CLK_PMU1_PWM0_DIV_SHIFT = 8, 287 CLK_PMU1_PWM0_DIV_MASK = 0x3 << CLK_PMU1_PWM0_DIV_SHIFT, 288 CLK_PMU1_PWM0_SEL_SHIFT = 14, 289 CLK_PMU1_PWM0_SEL_MASK = 0x3 << CLK_PMU1_PWM0_SEL_SHIFT, 290 CLK_PMU1_PWM0_SEL_200M = 0, 291 CLK_PMU1_PWM0_SEL_24M, 292 CLK_PMU1_PWM0_SEL_32K, 293 294 /* PERICRU_CLKSEL_CON00 */ 295 ACLK_PERI_DIV_SHIFT = 0, 296 ACLK_PERI_DIV_MASK = 0x1f << ACLK_PERI_DIV_SHIFT, 297 ACLK_PERI_SEL_SHIFT = 7, 298 ACLK_PERI_SEL_MASK = 0x1 << ACLK_PERI_SEL_SHIFT, 299 ACLK_PERI_SEL_GPLL = 0, 300 ACLK_PERI_SEL_CPLL, 301 HCLK_PERI_DIV_SHIFT = 8, 302 HCLK_PERI_DIV_MASK = 0x3f << HCLK_PERI_DIV_SHIFT, 303 HCLK_PERI_SEL_SHIFT = 15, 304 HCLK_PERI_SEL_MASK = 0x1 << HCLK_PERI_SEL_SHIFT, 305 306 /* PERICRU_CLKSEL_CON01 */ 307 PCLK_PERI_DIV_SHIFT = 0, 308 PCLK_PERI_DIV_MASK = 0x1f << PCLK_PERI_DIV_SHIFT, 309 PCLK_PERI_SEL_SHIFT = 7, 310 PCLK_PERI_SEL_MASK = 0x1 << PCLK_PERI_SEL_SHIFT, 311 CLK_SAI0_SRC_DIV_SHIFT = 8, 312 CLK_SAI0_SRC_DIV_MASK = 0x3f << CLK_SAI0_SRC_DIV_SHIFT, 313 CLK_SAI0_SRC_SEL_SHIFT = 14, 314 CLK_SAI0_SRC_SEL_MASK = 0x3 << CLK_SAI0_SRC_SEL_SHIFT, 315 316 /* PERICRU_CLKSEL_CON16 */ 317 CCLK_SDMMC0_DIV_SHIFT = 0, 318 CCLK_SDMMC0_DIV_MASK = 0xff << CCLK_SDMMC0_DIV_SHIFT, 319 CCLK_SDMMC0_SEL_SHIFT = 14, 320 CCLK_SDMMC0_SEL_MASK = 0x3 << CCLK_SDMMC0_SEL_SHIFT, 321 CCLK_SDMMC_SEL_GPLL = 0, 322 CCLK_SDMMC_SEL_CPLL, 323 CCLK_SDMMC_SEL_24M, 324 CCLK_SDMMC_SEL_HPLL, 325 326 /* PERICRU_CLKSEL_CON17 */ 327 CCLK_SDMMC1_DIV_SHIFT = 0, 328 CCLK_SDMMC1_DIV_MASK = 0xff << CCLK_SDMMC1_DIV_SHIFT, 329 CCLK_SDMMC1_SEL_SHIFT = 14, 330 CCLK_SDMMC1_SEL_MASK = 0x3 << CCLK_SDMMC1_SEL_SHIFT, 331 332 /* PERICRU_CLKSEL_CON18 */ 333 CCLK_EMMC_DIV_SHIFT = 0, 334 CCLK_EMMC_DIV_MASK = 0xff << CCLK_EMMC_DIV_SHIFT, 335 CCLK_EMMC_SEL_SHIFT = 14, 336 CCLK_EMMC_SEL_MASK = 0x3 << CCLK_EMMC_SEL_SHIFT, 337 CCLK_EMMC_SEL_GPLL = 0, 338 CCLK_EMMC_SEL_CPLL, 339 CCLK_EMMC_SEL_24M, 340 CCLK_EMMC_SEL_HPLL, 341 342 /* PERICRU_CLKSEL_CON19 */ 343 BCLK_EMMC_DIV_SHIFT = 8, 344 BCLK_EMMC_DIV_MASK = 0x7f << BCLK_EMMC_DIV_SHIFT, 345 BCLK_EMMC_SEL_SHIFT = 15, 346 BCLK_EMMC_SEL_MASK = 0x1 << BCLK_EMMC_SEL_SHIFT, 347 BCLK_EMMC_SEL_GPLL = 0, 348 BCLK_EMMC_SEL_CPLL, 349 350 /* PERICRU_CLKSEL_CON20 */ 351 SCLK_SFC_DIV_SHIFT = 0, 352 SCLK_SFC_DIV_MASK = 0xff << SCLK_SFC_DIV_SHIFT, 353 SCLK_SFC_SEL_SHIFT = 8, 354 SCLK_SFC_SEL_MASK = 0x3 << SCLK_SFC_SEL_SHIFT, 355 SCLK_SFC_SRC_SEL_GPLL = 0, 356 SCLK_SFC_SRC_SEL_CPLL, 357 SCLK_SFC_SRC_SEL_24M, 358 CLK_SPI1_SEL_SHIFT = 12, 359 CLK_SPI1_SEL_MASK = 0x3 << CLK_SPI1_SEL_SHIFT, 360 CLK_SPI_SEL_200M = 0, 361 CLK_SPI_SEL_100M, 362 CLK_SPI_SEL_50M, 363 CLK_SPI_SEL_24M, 364 CLK_SPI2_SEL_SHIFT = 14, 365 CLK_SPI2_SEL_MASK = 0x3 << CLK_SPI2_SEL_SHIFT, 366 367 /* PERICRU_CLKSEL_CON21 */ 368 CLK_UART_SRC_DIV_SHIFT = 0, 369 CLK_UART_SRC_DIV_MASK = 0x7f << CLK_UART_SRC_DIV_SHIFT, 370 CLK_UART_SRC_SEL_SHIFT = 8, 371 CLK_UART_SRC_SEL_MASK = 0x1 << CLK_UART_SRC_SEL_SHIFT, 372 CLK_UART_SRC_SEL_GPLL = 0, 373 CLK_UART_SRC_SEL_CPLL, 374 CLK_UART_SEL_SHIFT = 14, 375 CLK_UART_SEL_MASK = 0x3 << CLK_UART_SEL_SHIFT, 376 CLK_UART_SEL_SRC = 0, 377 CLK_UART_SEL_FRAC, 378 CLK_UART_SEL_XIN24M, 379 380 /* PERICRU_CLKSEL_CON22 */ 381 CLK_UART_FRAC_NUMERATOR_SHIFT = 16, 382 CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << 16, 383 CLK_UART_FRAC_DENOMINATOR_SHIFT = 0, 384 CLK_UART_FRAC_DENOMINATOR_MASK = 0xffff, 385 386 /* PERICRU_CLKSEL_CON40 */ 387 CLK_PWM1_PERI_SEL_SHIFT = 0, 388 CLK_PWM1_PERI_SEL_MASK = 0x3 << CLK_PWM1_PERI_SEL_SHIFT, 389 CLK_PWM_SEL_100M = 0, 390 CLK_PWM_SEL_50M, 391 CLK_PWM_SEL_24M, 392 CLK_PWM2_PERI_SEL_SHIFT = 6, 393 CLK_PWM2_PERI_SEL_MASK = 0x3 << CLK_PWM2_PERI_SEL_SHIFT, 394 CLK_PWM3_PERI_SEL_SHIFT = 8, 395 CLK_PWM3_PERI_SEL_MASK = 0x3 << CLK_PWM3_PERI_SEL_SHIFT, 396 397 /* PERICRU_CLKSEL_CON43 */ 398 CLK_CORE_CRYPTO_SEL_SHIFT = 0, 399 CLK_CORE_CRYPTO_SEL_MASK = 0x3 << CLK_CORE_CRYPTO_SEL_SHIFT, 400 CLK_CORE_CRYPTO_SEL_200M = 0, 401 CLK_CORE_CRYPTO_SEL_100M, 402 CLK_CORE_CRYPTO_SEL_24M, 403 CLK_PKA_CRYPTO_SEL_SHIFT = 6, 404 CLK_PKA_CRYPTO_SEL_MASK = 0x3 << CLK_PKA_CRYPTO_SEL_SHIFT, 405 CLK_PKA_CRYPTO_SEL_300M = 0, 406 CLK_PKA_CRYPTO_SEL_200M, 407 CLK_PKA_CRYPTO_SEL_100M, 408 CLK_PKA_CRYPTO_SEL_24M, 409 TCLK_PERI_WDT_SEL_SHIFT = 15, 410 TCLK_PERI_WDT_SEL_MASK = 0x1 << TCLK_PERI_WDT_SEL_SHIFT, 411 412 /* PERICRU_CLKSEL_CON46 */ 413 CLK_SARADC_DIV_SHIFT = 0, 414 CLK_SARADC_DIV_MASK = 0xfff << CLK_SARADC_DIV_SHIFT, 415 }; 416 #endif 417